EL8188FSZ-T7 [INTERSIL]
Micropower Single Supply Rail-to-Rail Input-Output Precision Op Amp; 微功耗单电源轨至轨输入输出精密运算放大器
| 型号： | EL8188FSZ-T7 |
| 厂家： | 
Intersil |
| 描述： | Micropower Single Supply Rail-to-Rail Input-Output Precision Op Amp |
| 文件： | 总11页 (文件大小：874K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EL8188
®
Data Sheet
February 22, 2007
FN7467.3
PRELIMINARY
Micropower Single Supply Rail-to-Rail
Input-Output Precision Op Amp
Features
• 50µA supply current
The EL8188 is a micropower precision op amp optimized for
single supply operation at 5V and can operate down to 2.4V.
• 1mV typ offset voltage
• 2pA input bias current
The EL8188 draws minimal supply current while meeting
excellent DC-accuracy, noise, and output drive
• 266kHz gain-bandwidth product
• 0.13V/µs slew rate
specifications. Competing devices seriously degrade these
parameters to achieve rail-to-rail operation and microamp
supply current. Offset current, voltage and current noise,
slew rate, and gain-bandwidth product are all 2X to 10X
better than on previous micropower rail-to-rail op amps.
• Single supply operation down to 2.4V
• Rail-to-rail input and output
• Output sources and sinks 26mA load current
• Pb-free plus anneal available (RoHS compliant)
The EL8188 can be operated from one lithium cell or two
Ni-Cd batteries. The input range includes both the positive
and negative rails. The output swings to both rails.
Applications
• Battery- or solar-powered systems
• 4mA to 20mA current loops
• Handheld consumer products
• Medical devices
Ordering Information
PART
TAPE & PACKAGE
PKG.
DWG. #
PART NUMBER MARKING
REEL
(Pb-Free)
Coming Soon
EL8188FWZ-T7
(Note)
8178FW
8178FW
7”
6 Ld SOT-23 MDP0038
(3k pcs)
• Thermocouple amplifiers
• Photodiode pre-amps
• pH probe amplifiers
Coming Soon
EL8188FWZ-T7A
(Note)
7”
6 Ld SOT-23 MDP0038
(250 pcs)
EL8188FSZ
(Note)
8178FSZ
8178FSZ
97/Tube 8 Ld SO
MDP0027
MDP0027
Pinouts
EL8188
(6 LD SOT-23 - Coming Soon)
TOP VIEW
EL8188FSZ-T7
(Note)
7”
8 Ld SO
(1k pcs)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
OUT
VS-
IN+
1
2
3
6
5
4
VS+
ENABLE
IN-
+
-
EL8188
(8 LD SO)
TOP VIEW
NC
IN-
1
2
3
4
8
7
6
5
ENABLE
VS+
-
+
IN+
VS-
OUT
NC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004-2007. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
EL8188
Absolute Maximum Ratings (T = +25°C)
Thermal Information
A
Supply Voltage (V ) and Pwr-up Ramp Rate . . . . . . . . 5.5V, 1V/µs
S
Thermal Resistance
θ
(°C/W)
JA
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V
Current into IN+, IN-, and ENABLE . . . . . . . . . . . . . . . . . . . . . . 5mA
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . V -0.5V to V +0.5V
S- S+
ESD tolerance, Human Body Model . . . . . . . . . . . . . . . . . . . TBDkV
6 Ld SOT Package . . . . . . . . . . . . . . . . . . . . . . . . .
8 Ld SO Package . . . . . . . . . . . . . . . . . . . . . . . . . .
230
110
Ambient Operating Temperature Range . . . . . . . . -40°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . . . . . -65°C to +150°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . +125°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
ESD tolerance, Machine Model . . . . . . . . . . . . . . . . . . . . . . . TBDV
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T = T = T
J
C
A
Electrical Specifications
V
= 5V, V = 0V, V
S-
= 0.1V, V = 1.4V, T = +25°C unless otherwise specified. Boldface limits apply over
CM O A
S+
the operating temperature range, -40°C to +125°C
PARAMETER
DESCRIPTION
Input Offset Voltage
TEST CONDITIONS
MIN
TYP
1
MAX
UNIT
mV
V
SOT
4
OS
ΔV
Long Term Input Offset Voltage
Stability
1.2
µV/Mo
OS
------------------
ΔTime
ΔV
Input Offset Drift vs Temperature
1.1
2
2.1
µV/°C
OS
---------------
ΔT
I
Input Bias Current
-15
15
pA
pA
B
-600
600
e
Input Noise Voltage Peak-to-Peak
Input Noise Voltage Density
Input Noise Current Density
Input Voltage Range
f = 0.1Hz to 10Hz
2.8
48
µV
P-P
N
f
f
= 1kHz
= 1kHz
nV/√Hz
pA/√Hz
V
O
O
i
0.15
N
CMIR
Guaranteed by CMRR test
0
5
CMRR
Common-Mode Rejection Ratio
V
V
V
= 0V to 5V
80
100
100
400
dB
CM
75
dB
PSRR
Power Supply Rejection Ratio
Large Signal Voltage Gain
= 2.4V to 5V
80
dB
S
80
dB
A
= 0.5V to 4.5V,
= 100kΩ to (V + V )/2
S+ S-
100
100
V/mV
V/mV
V/mV
VOL
O
R
L
V
R
= 0.5V to 4.5V,
= 1kΩ to (V + V )/2
S+ S-
15
3
O
L
V
Maximum Output Voltage Swing
V
R
; Output low,
= 100kΩ to (V + V )/2
8
mV
mV
mV
mV
V
OUT
OL
L
S+ S-
10
V
R
; Output low,
130
200
300
OL
= 1kΩ to (V + V )/2
L
S+
S-
V
R
; Output high,
= 100kΩ to (V + V )/2
4.994
4.992
4.750
4.7
4.997
4.867
OH
L
S+ S-
V
V
R
; Output high,
V
OH
= 1kΩ to (V + V )/2
L
S+ S-
V
SR
Slew Rate
0.05
0.13
266
0.25
V/µs
kHz
GBWP
Gain Bandwidth Product
f = 100kHz
O
FN7467.3
February 22, 2007
2
EL8188
Electrical Specifications
V
= 5V, V = 0V, V
S-
= 0.1V, V = 1.4V, T = +25°C unless otherwise specified. Boldface limits apply over
S+
CM
O
A
the operating temperature range, -40°C to +125°C (Continued)
PARAMETER
DESCRIPTION
Supply Current, Enabled
TEST CONDITIONS
MIN
35
TYP
MAX
75
UNIT
µA
µA
µA
µA
mA
mA
mA
mA
V
I
I
I
I
50
S, ON
30
90
Supply Current, Disabled
Short Circuit Output Current
Short Circuit Output Current
Minimum Supply Voltage
3
10
S, OFF
10
+
-
R
R
= 10Ω to opposite supply
= 10Ω to opposite supply
23
18
20
15
31
26
2.2
SC
SC
L
L
V
2.4
S
2.4
V
V
V
Enable Pin High Level
Enable Pin Low Level
Enable Pin Input Current
2
V
INH
INL
0.8
2
V
I
V
V
= 5V
= 0V
0.25
0.25
-0.5
-0.5
0.7
0
µA
µA
µA
µA
ENH
EN
EN
2.5
+0.5
+0.5
I
Enable Pin Input Current
ENL
FN7467.3
February 22, 2007
3
EL8188
Typical Performance Curves
V
= ±2.5V, T = +25°C, Unless Otherwise Specified
S
A
1
80
R
≥ 10kΩ
L
R
≥ 10kΩ
GAIN = 1k
L
70
V
= 0.2V
OUT
P-P
V
= 0.2V
OUT
P-P
GAIN = 500
GAIN = 200
GAIN = 100
60
50
40
30
20
10
0
0
V
= ±1.25
S
-1
-2
-3
GAIN = 10
GAIN = 5
GAIN = 2
V
= ±2.5V
S
V
= ±1.0V
S
-10
-20
GAIN = 1
1k
10k
100k
1M
1
10
100
1k
10k
100k 1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 1. UNITY GAIN FREQUENCY RESPONSE at
VARIOUS SUPPLY VOLTAGES
FIGURE 2. FREQUENCY RESPONSE at VARIOUS CLOSED
LOOP GAINS
60
50
40
30
20
10
0
200
A
= -1
= V /2
V
V
CM
DD
100
0
-100
-200
2
2.5
3
3.5
4
4.5
5
5.5
-0.5
0.5
1.5
2.5
3.5
4.5
5.5
SUPPLY VOLTAGE (V)
OUTPUT VOLTAGE (V)
FIGURE 3. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 4. INPUT OFFSET VOLTAGE vs OUTPUT VOLTAGE
250
150
50
20
I
OS
10
I -
B
0
-50
-10
I +
B
-150
-250
-20
-0.5
-0.5
0.5
1.5
2.5
3.5
4.5
5.5
0.5
1.5
2.5
3.5
4.5
5.5
COMMON-MODE INPUT VOLTAGE (V)
COMMON-MODE INPUT VOLTAGE (V)
FIGURE 5. INPUT OFFSET VOLTAGE vs COMMON-MODE
INPUT VOLTAGE
FIGURE 6. INPUT BIAS, OFFSET CURRENT vs COMMON-
MODE INPUT VOLTAGE
FN7467.3
February 22, 2007
4
EL8188
Typical Performance Curves (Continued) V = ±2.5V, T = +25°C, Unless Otherwise Specified (Continued)
S
A
100
90
80
70
60
50
40
30
20
10
0
100
80
60
40
20
0
0
45
90
90
PHASE
GAIN
PHASE
135
180
135
180
GAIN
-10
-20
10
10
100
1k
10k
100k
1M
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 7. OPEN LOOP GAIN AND PHASE vs FREQUENCY
(R = 1kΩ)
FIGURE 8. OPEN LOOP GAIN AND PHASE vs FREQUENCY
(R = 100kΩ)
L
L
10
10
0
ΔV
= 1V
P-P
= 100kΩ
= +1
ΔV = 1V
CM
S
P-P
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
R
L
R
= 100kΩ
L
A
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
V
A
= +1
V
-PSRR
+PSRR
10
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 10. PSRR vs FREQUENCY
FIGURE 9. CMRR vs FREQUENCY
100
10
1
1000
100
10
VOLTAGE
CURRENT
2.8µV
P-P
0.1
100k
1
1
10
100
1k
10k
TIME (1s/DIV)
FREQUENCY (Hz)
FIGURE 12. 0.1Hz TO 10Hz INPUT VOLTAGE NOISE
FIGURE 11. INPUT VOLTAGE AND CURRENT NOISE vs
FREQUENCY
FN7467.3
February 22, 2007
5
EL8188
Typical Performance Curves (Continued) V = ±2.5V, T = +25°C, Unless Otherwise Specified (Continued)
S
A
400
300
200
100
0
150
100
50
10 SAMPLES
0
-100
-200
-300
-400
-50
-100
-150
35 SOIC SAMPLES
TYPICAL = 1.1µV/C
-60 -40 -20
0
20 40 60 80 100 120
0
10 20 30 40 50 60 70 80 90 100
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 14. EL8188 SOIC V
vs TEMPERATURE (V = 5V)
S
FIGURE 13. V
vs TEMPERATURE
OS
OS
800
35 6 LD SOT-23 SAMPLES
600 TYPICAL = 1.9µV/C
400
200
0
-200
-400
-600
-800
-60 -40 -20
0
20 40 60 80 100 120
TEMPERATURE (°C)
FIGURE 15. EL8188 SOT V
vs TEMPERATURE (V = 5V)
S
OS
20
15
10
5
18
n = 10
n = 10
MAX
13
8
MAX
MEDIAN
MEDIAN
3
0
-2
-7
-12
-5
-10
-15
MIN
MIN
0
500
1000
HOURS
1500
1900
0
500
1000
HOURS
1500
1900
FIGURE 16. V
DRIFT SOT-23 vs TIME
FIGURE 17. V
DRIFT SOIC vs TIME
OS
OS
FN7467.3
February 22, 2007
6
EL8188
Pin Descriptions
SO PIN
NUMBER
SOT-23 PIN
NUMBER
EQUIVALENT
CIRCUIT
PIN NAME
NC
DESCRIPTION
1
2
3
4
5
6
7
8
No internal connection
Amplifier’s inverting input
Amplifier’s non-inverting input
Negative power supply
No internal connection
Amplifier’s output
4
3
2
IN-
Circuit 1
Circuit 1
Circuit 4
IN+
VS-
NC
1
6
5
OUT
VS+
Circuit 3
Circuit 4
Circuit 2
Positive power supply
ENABLE
Amplifier’s enable pin with internal pull-down; Logic “1” selects the disabled state;
Logic “0” selects the enabled state.
V
V
S+
S+
V
S+
V
S+
CAPACITIVELY
COUPLED
ESD CLAMP
OUT
ENABLE
IN-
IN+
V
S-
V
V
S-
S-
V
S-
CIRCUIT 1
CIRCUIT 2
CIRCUIT 3
CIRCUIT 4
Rail-to-Rail Output
Application Information
A pair of complementary MOSFET devices achieves rail-to-rail
output swing. The NMOS sinks current to swing the output in
the negative direction, while the PMOS sources current to
swing the output in the positive direction. The EL8188 with a
100kΩ load swings to within 3mV of the supply rails.
Introduction
The EL8188 is a rail-to-rail input and output (RRIO), micro-
power, precision, single supply op amp with an enable
feature. This amplifier is designed to operate from single
supply (2.4V to 5.0V) or dual supply (±1.2V to ±2.5V) while
drawing only 50µA of supply current.The device achieves
rail-to-rail input and output operation while eliminating the
drawbacks of many conventional RRIO op amps.
Enable/Disable Feature
The EL8188 features an active low ENABLE pin that when
pulled up to at least 2V disables the output, and drops the
already low I
to a 3µA trickle. The ENABLE pin has an
CC
Rail-to-Rail Input
internal pull down, so an undriven pin pulls to the negative
rail, thereby enabling the op amp by default.
The PFET input stage of the EL8188 has an input common-
mode voltage range that includes the negative and positive
supplies without introducing offset errors or degrading
performance like some existing rail-to-rail input op amps.
Many rail-to-rail input stages use two differential input pairs:
a long-tail PNP (or PFET) and an NPN (or NFET). Severe
penalties result from using this topology. As the input signal
moves from one supply rail to the other, the op amp switches
from one input pair to the other causing drastic changes in
input offset voltage and an undesired change in the input
offset current’s magnitude and polarity.
The high impedance output during disable allows for
connecting multiple EL8188s together to implement a Mux
Amp. The outputs are connected together and activating the
appropriate ENABLE pin selects the desired channel. If
utilizing non-unity gain op amp configurations, then the
loading effects of the disabled amplifiers’ feedback networks
must be considered when evaluating the active amplifier’s
performance in Mux Amp configurations.
Note that feedthrough from the IN+ to IN- pins occurs on any
Mux Amp disabled channel where the input differential
voltage exceeds 0.5V (e.g., active channel V
disabled channel V = GND), so the mux implementation is
best suited for small signal applications. If large signals are
The EL8188 achieves rail-to-rail input performance without
sacrificing important precision specifications and without
degrading distortion performance. The EL8188's input offset
voltage exhibits a smooth behavior throughout the entire
common-mode input range.
= 1V, while
OUT
IN
required, use series IN+ resistors, or large value R s, to
F
keep the feedthrough current low enough to minimize the
impact on the active channel. See the “Usage Implications”
on page 8 for more details.
FN7467.3
February 22, 2007
7
EL8188
the safe operating area. These parameters are related as
IN+ and IN- Input Protection
follows:
In addition to ESD protection diodes to each supply rail, the
EL8188 has additional back-to-back protection diodes across
the differential input terminals (see “Circuit 1” on page 7).
Obviously, one of these diodes conducts if the magnitude of
(EQ. 1)
T
= T
+ (θ × PD
)
MAX
JMAX
MAX
JA
where PD
is calculated using:
MAX
the differential input voltage ever exceeds the diode’s V .
F
V
OUTMAX
R
L
Usage Implications
----------------------------
PD
= V × I
+ (V - V ) ×
OUTMAX
MAX
S
SMAX
S
If the input differential voltage is expected to exceed 0.5V, an
external current limiting resistor must be used to ensure the
input current never exceeds 5mA. For noninverting unity gain
applications the current limiting can be via a series IN+ resistor,
or via a feedback resistor of appropriate value. For other gain
configurations, the series IN+ resistor is the best choice, unless
(EQ. 2)
where:
• T
= Maximum ambient temperature
MAX
• θ = Thermal resistance of the package
JA
the feedback (R ) and gain setting (R ) resistors are both
sufficiently large to limit the input current to 5mA.
F
G
• PD
= Maximum power dissipation of the amplifier
MAX
• V = Supply voltage
S
Large differential input voltages can arise from several
sources:
• I
= Maximum supply current of the amplifier
MAX
• V
= Maximum output voltage swing of the
OUTMAX
application
1) During open loop (comparator) operation. Used this way,
the IN+ and IN- voltages don’t track, so differentials arise.
• R = Load resistance
L
2) When the amplifier is disabled but an input signal is still
Proper Layout Maximizes Precision
present. An R or R to GND keeps the IN- at GND, while
L
G
the varying IN+ signal creates a differential voltage. Mux
Amp applications are similar, except that the active channel
To achieve the optimum levels of high input impedance (i.e.,
low input currents) and low offset voltage, care should be
taken in the circuit board layout. The PC board surface must
remain clean and free of moisture to avoid leakage currents
between adjacent traces. Surface coating of the circuit board
will reduce surface moisture and provide a humidity barrier,
reducing parasitic resistance on the board. When input
leakage current is a paramount concern, the use of guard
rings around the amplifier inputs will further reduce leakage
currents. Figure 18 shows a guard ring example for a unity
gain amplifier that uses the low impedance amplifier output
at the same voltage as the high impedance input to eliminate
surface leakage. The guard ring does not need to be a
specific width, but it should form a continuous loop around
both inputs. For further reduction of leakage currents, mount
components to the PC board using Teflon standoffs.
V
determines the voltage on the IN- terminal.
OUT
3) When the slew rate of the input pulse is considerably
faster than the op amp’s slew rate. If the V can’t keep up
OUT
with the IN+ signal, a differential voltage results, and visible
distortion occurs on the input and output signals. To avoid
this issue, keep the input slew rate below 0.2V/µs, or use
appropriate current limiting resistors.
Large (>2V) differential input voltages can also cause an
increase in disabled I
.
CC
ENABLE Input Protection
The ENABLE input has internal ESD protection diodes to both
the positive and negative supply rails, limiting the input
voltage range to within one diode beyond the supply rails (see
“Circuit 2” on page 7). If the input voltage is expected to
V+
HIGH IMPEDANCE INPUT
exceed V or V , then an external series resistor should be
S+ S-
added to limit the current to 5mA.
IN
Output Current Limiting
The EL8188 has no internal current-limiting circuitry. If the
output is shorted, it is possible to exceed the “Absolute
Maximum Rating” for “operating junction temperature”,
potentially resulting in the destruction of the device.
FIGURE 18. GUARD RING EXAMPLE FOR UNITY GAIN
AMPLIFIER
Power Dissipation
It is possible to exceed the +150°C maximum junction
temperature (T
) under certain load and power-supply
JMAX
conditions. It is therefore important to calculate T
for all
JMAX
applications to determine if power supply voltages, load
conditions, or package type need to be modified to remain in
FN7467.3
February 22, 2007
8
EL8188
Typical Applications
R
V
4
S+
+
EL8188
100kΩ
+
-
GENERAL
PURPOSE
V
COAX
R
R
10kΩ
10kΩ
S-
3V
3
2
V
S+
+
COMBINATION
pH PROBE
EL8188
-
410µV/°C
+
K TYPE
THERMOCOUPLE
V
S-
5V
FIGURE 19. pH PROBE AMPLIFIER
R
1
A general-purpose combination pH probe has extremely
high output impedance typically in the range of 10GΩ to
12GΩ. Low loss and expensive Teflon cables are often used
to connect the pH probe to the meter electronics. Figure 19
details a low-cost alternative solution using the EL8188 and
a low-cost coax cable. The EL8188 PMOS high impedance
input senses the pH probe output signal and buffers it to
drive the coax cable. Its rail-to-rail input nature also
eliminates the need for a bias resistor network required by
other amplifiers in the same application.
100kΩ
FIGURE 20. THERMOCOUPLE AMPLIFIER
Thermocouples are the most popular temperature sensing
devices because of their low cost, interchangeability, and
ability to measure a wide range of temperatures. In
Figure 20, the EL8188 converts the differential thermocouple
voltage into single-ended signal with 10X gain. The
EL8188's rail-to-rail input characteristic allows the
thermocouple to be biased at ground and permits the
op amp to operate from a single 5V supply.
FN7467.3
February 22, 2007
9
EL8188
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M
C A B
e
H
C
A2
A1
GAUGE
PLANE
SEATING
PLANE
0.010
L
4° ±4°
0.004 C
b
0.010 M
C
A
B
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
SO24
(SOL-24)
SO28
(SOL-28)
SYMBOL
SO-8
0.068
0.006
0.057
0.017
0.009
0.193
0.236
0.154
0.050
0.025
0.041
0.013
8
SO-14
0.068
0.006
0.057
0.017
0.009
0.341
0.236
0.154
0.050
0.025
0.041
0.013
14
(SOL-20)
0.104
0.007
0.092
0.017
0.011
0.504
0.406
0.295
0.050
0.030
0.056
0.020
20
TOLERANCE
MAX
NOTES
A
A1
A2
b
0.068
0.006
0.057
0.017
0.009
0.390
0.236
0.154
0.050
0.025
0.041
0.013
16
0.104
0.007
0.092
0.017
0.011
0.406
0.406
0.295
0.050
0.030
0.056
0.020
16
0.104
0.007
0.092
0.017
0.011
0.606
0.406
0.295
0.050
0.030
0.056
0.020
24
0.104
0.007
0.092
0.017
0.011
0.704
0.406
0.295
0.050
0.030
0.056
0.020
28
-
±0.003
±0.002
±0.003
±0.001
±0.004
±0.008
±0.004
Basic
-
-
-
c
-
D
1, 3
E
-
E1
e
2, 3
-
L
±0.009
Basic
-
L1
h
-
Reference
Reference
-
N
-
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
FN7467.3
February 22, 2007
10
EL8188
SOT-23 Package Family
MDP0038
e1
D
SOT-23 PACKAGE FAMILY
MILLIMETERS
SOT23-5
A
6
4
N
SYMBOL
SOT23-6
1.45
0.10
1.14
0.40
0.14
2.90
2.80
1.60
0.95
1.90
0.45
0.60
6
TOLERANCE
MAX
A
A1
A2
b
1.45
0.10
1.14
0.40
0.14
2.90
2.80
1.60
0.95
1.90
0.45
0.60
5
±0.05
E1
E
±0.15
2
3
±0.05
0.15
2X
C
D
c
±0.06
1
2
3
0.20
2X
C
D
Basic
5
e
E
Basic
E1
e
Basic
0.20
C
A-B
D
M
B
b
NX
Basic
e1
L
Basic
±0.10
L1
N
Reference
Reference
Rev. F 2/07
0.15
2X
C
A-B
1
3
D
NOTES:
C
1. Plastic or metal protrusions of 0.25mm maximum per side are not
included.
A2
SEATING
PLANE
2. Plastic interlead protrusions of 0.25mm maximum per side are not
included.
A1
0.10
NX
C
3. This dimension is measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Index area - Pin #1 I.D. will be located within the indicated zone
(SOT23-6 only).
6. SOT23-5 version has no center lead (shown as a dashed line).
(L1)
H
A
GAUGE
PLANE
0.25
c
+3°
-0°
L
0°
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FN7467.3
February 22, 2007
11
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