EL8171ISZ-T7 [INTERSIL]
Micropower, Single Supply, Rail-to-Rail Input-Output Instrumentation Amplifiers; 微功耗,单电源,轨到轨输入输出仪表放大器型号: | EL8171ISZ-T7 |
厂家: | Intersil |
描述: | Micropower, Single Supply, Rail-to-Rail Input-Output Instrumentation Amplifiers |
文件: | 总11页 (文件大小:825K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
EL8171, EL8172
®
Data Sheet
October 26, 2005
FN6293.0
Micropower, Single Supply, Rail-to-Rail
Input-Output Instrumentation Amplifiers
Features
• 78µA maximum supply current
The EL8171 and EL8172 are micropower instrumentation
amplifiers optimized for operation at 2.9V to 5V single
supplies. Inputs and outputs can operate rail-to-rail. As with
all instrumentation amplifiers, a pair of inputs provide very
high common-mode rejection and are completely
independent from a pair of feedback terminals. The
feedback terminals allow zero input to be translated to any
output offset, including ground. A feedback divider controls
the overall gain of the amplifier.
• Maximum input offset voltage
- 300µV (EL8172)
- 1000µV (EL8171)
• 200pA maximum input bias current
• 3µV/°C offset voltage drift
• 450kHz -3dB bandwidth (G = 10)
• 170kHz -3dB bandwidth (G = 100)
• 0.5V/µs slew rate
The EL8172 is compensated for a gain of 100 or more, and
the EL8171 is compensated for a gain of 10 or more. The
EL8171 and EL8172 have PMOS input devices that provide
sub-nA input bias currents.
• Single supply operation
- Input voltage range is rail-to-rail
- Output swings rail-to-rail
The amplifiers can be operated from one lithium cell or two
Ni-Cd batteries. The EL8171 and EL8172 input range goes
from below ground to slightly above positive rail. The output
stage swings completely to ground or positive supply - no
pull-up or pull-down resistors are needed.
• Output sources and sinks ±29mA load current
• 0.2% gain accuracy
• Pb-free plus anneal available (RoHS compliant)
Applications
• Battery- or solar-powered systems
Pinout
EL8171, EL8172
(8 LD SO)
• Strain gauges
TOP VIEW
• Current monitors
+
-
ENABLE
IN-
1
2
3
4
8
7
6
5
FB+
VS+
OUT
FB-
• Thermocouple amplifiers
-
Σ
+
IN+
VS-
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2005. All Rights Reserved.
1
All other trademarks mentioned are the property of their respective owners.
EL8171, EL8172
Ordering Information
PART
TAPE &
REEL
PKG.
PART
PART NUMBER MARKING
TAPE &
REEL
PKG.
PART NUMBER MARKING
PACKAGE
8 Ld SO
8 Ld SO
8 Ld SO
DWG. #
MDP0027
MDP0027
MDP0027
MDP0027
PACKAGE
8 Ld SO
8 Ld SO
8 Ld SO
DWG. #
EL8171IS
8171IS
8171IS
8171IS
8171ISZ
-
7”
13”
-
EL8172IS
8172IS
8172IS
8172IS
8172ISZ
-
7”
13”
-
MDP0027
MDP0027
MDP0027
MDP0027
EL8171IS-T7
EL8171IS-T13
EL8172IS-T7
EL8172IS-T13
EL8171ISZ
(See Note)
8 Ld SO
(Pb-free)
EL8172ISZ
(See Note)
8 Ld SO
(Pb-free)
EL8171ISZ-T7
(See Note)
8171ISZ
8171ISZ
7”
8 Ld SO
(Pb-free)
MDP0027
MDP0027
EL8172ISZ-T7
(See Note)
8172ISZ
8172ISZ
7”
8 Ld SO
(Pb-free)
MDP0027
MDP0027
EL8171ISZ-T13
(See Note)
13”
8 Ld SO
(Pb-free)
EL8172ISZ-T13
(See Note)
13”
8 Ld SO
(Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pin Description
EL8171/EL8172
PIN NAME
PIN FUNCTION
1
ENABLE
Active Low. When pulled up above 2V, the in-amp conserves 3µA disabled supply current and the output is
in a high impedance state. An internal pull down defines the ENABLE low when left floating.
2
3
5
8
IN-
IN+
FB-
FB+
Inverting (IN-) and non-inverting (IN+) high impedance input terminals. The input terminals are equivalent to
the gate of PMOS transistor.
High impedance feedback terminals. The feedback terminals have a very similar equivalent circuit as the
input terminals. The negative feedback (FB-) pin connects to an external resistive network to set the gain of
the in-amp. The positive feedback (FB+) pin can be used to shift the DC level of the output or as an output
offset.
7
4
6
VS+
VS-
Positive supply terminal.
Negative supply terminal.
Output Voltage.
VOUT
FN6293.0
2
October 26, 2005
EL8171, EL8172
Absolute Maximum Ratings (T = 25°C)
A
Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Output Short-Circuit Duration . . . . . . . . . . . . . . . . . . . . . . .Indefinite
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
S
Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5V to V + + 0.5V
S
EN
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T = T = T
A
J
C
Electrical Specifications V + = +5V, V - = GND, VCM = 1/2V + T = 25°C, unless otherwise specified.
S
S
S
A
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
400
150
3
MAX
1000
300
UNIT
µV
V
Input Offset Voltage
EL8171
EL8172
OS
µV
TCV
Input Offset Voltage Temperature
Coefficient
Temperature = -40°C to 85°C
µV/°C
OS
I
I
Input Offset Current
Input Bias Current
Input Noise Voltage
10
10
10
4
200
200
pA
pA
OS
B
e
EL8171
EL8172
f = 0.1Hz to 10Hz
µV
µV
N
P-P
P-P
Input Noise Voltage Density
Input Resistance
f = 1kHz
50
25
nV/√Hz
GΩ
V
o
R
IN
V
Input Voltage Range
Guaranteed by CMRR test
0
80
80
80
70
-1.5
-0.8
0
5
IN
CMRR
PSRR
Common Mode Rejection Ratio
EL8172, V
EL8171, V
= 0V to +5V
= 0V to +5V
108
104
104
90
dB
CM
CM
dB
Power Supply Rejection Ratio
Gain Error
EL8172, V = 2.4V to 5V
dB
S
EL8171, V = 2.4V to 5V
dB
S
E
V
EL8172, R = 100kΩ to 2.5V
+0.3
+0.2
4
+1.5
+0.8
10
%
G
L
EL8171, R = 100kΩ to 2.5V
%
L
Maximum Voltage Swing
Output low, 100kΩ to 2.5V
Output low, 1kΩ to 2.5V
Output high, 100kΩ to 2.5V
Output high, 1kΩ to GND
mV
V
OUT
0.13
4.996
4.88
0.5
450
210
66
0.25
4.990
4.75
0.3
V
V
SR
Slew Rate
R = 1kΩ to GND
0.7
V/µs
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
µA
L
-3dB BW
-3dB Bandwidth
EL8171
Gain = 10V/V
Gain = 20
Gain = 50
Gain = 100
Gain = 100
Gain = 200
Gain = 500
Gain = 1000
33
EL8172
172
70
25
12
I
Supply Current, Enabled
40
60
78
S,EN
FN6293.0
3
October 26, 2005
EL8171, EL8172
Electrical Specifications V + = +5V, V - = GND, VCM = 1/2V + T = 25°C, unless otherwise specified. (Continued)
S
S
S
A
PARAMETER
DESCRIPTION
CONDITIONS
MIN
1.5
2
TYP
MAX
UNIT
µA
V
I
Supply Current, Disabled
Enable Pin for Shut-down
Enable Pin for Power-on
Minimum Supply Voltage
EN = V +
2.9
5
S,DIS
S
V
V
V
ENH
ENL
S
0.8
2.4
V
2.2
±29
±7.5
V
I
Output Current into 10Ω to V /2
V
V
= 5V
±18
±4
mA
mA
O
S
S
= 2.9V
S
Typical Performance Curves
70
60
50
40
30
G=2000
G=100
40
G=1000
G=500
G=50
30
G=20
G=200
G=100
G=10
20
G=5
G=50
10
Vs=5V
Vs=5V
10
20
1
0
100
1K
10K
100K
1M
1
10
100
1K
10K
100K
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 1. EL8171 FREQUENCY RESPONSE vs CLOSED
LOOP GAIN
FIGURE 2. EL8172 FREQUENCY RESPONSE vs CLOSED
LOOP GAIN
25
45
V =±2.5V
V =±2.5V
S
S
40
20
35
V =±1.25V
S
V =±1V
S
30
25
20
15
10
5
15
10
5
V =±1V
S
V =±1.25V
S
A =10
A =100
V
V
L
R =10kΩ
R =10kΩ
L
C =10pF
C =10pF
L
L
R /R =9.08Ω
R /R =99.02Ω
F G
F
G
R =178kΩ
R =221kΩ
F
F
G
R
=19.6kΩ
R
=2.23kΩ
G
0
0
100
1k
10k
100k
1M
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 3. EL8171 FREQUENCY RESPONSE vs SUPPLY
VOLTAGE
FIGURE 4. EL8172 FREQUENCY RESPONSE vs SUPPLY
VOLTAGE
FN6293.0
October 26, 2005
4
EL8171, EL8172
Typical Performance Curves (Continued)
30
50
45
40
35
30
25
25
20
15
10
5
C =100pF
L
C =47pF
L
C =2200pF
L
C =1000pF
L
C =27pF
L
C =820pF
L
A =10
V
A =100
V
C =390pF
V =5V
L
S
V =5V
S
R =10kΩ
L
R =10kΩ
L
R /R =9.08Ω
F
G
R /R =99.02Ω
F
G
R =178kΩ
F
G
R =221kΩ
F
R
=19.6kΩ
R =2.23kΩ
G
0
100
1k
10k
100k
1M
100
1k
10k
FREQUENCY (Hz)
FIGURE 6. EL8172 FREQUENCY RESPONSE vs C
100k
1M
FREQUENCY (Hz)
FIGURE 5. EL8171 FREQUENCY RESPONSE vs C
LOAD
LOAD
4
4
25°C
-45°C
2
0
2
0
Vs=2.9V
Vs=2.9V
Vs=3.3V
Vs=3.3V
-2
-2
Vs=5V
Vs=5V
-4
-0.5
-4
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
COMMON-MODE INPUT VOLTAGE (V)
COMMON-MODE INPUT VOLTAGE (V)
FIGURE 7. EL8171 AND EL8172 AVERAGE INPUT BIAS
CURRENT vs COMMON-MODE INPUT VOLTAGE
@ 25°C
FIGURE 8. EL8171 AND EL8172 AVERAGE INPUT BIAS
CURRENT vs COMMON-MODE INPUT VOLTAGE
@ -45°C
100
10
85°C
Vs=5V
50
0
5
0
Vs=5V
-5
-50
Vs=2.9V
Vs=3.3V
-10
-0.5
-100
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
COMMON-MODE INPUT VOLTAGE (V)
COMMON-MODE INPUT VOLTAGE (V)
FIGURE 9. EL8171 AND EL8172 AVERAGE INPUT BIAS
FIGURE 10. EL8171 AND EL8172 INPUT OFFSET CURRENT
vs COMMON-MODE INPUT VOLTAGE
CURRENT vs COMMON-MODE INPUT VOLTAGE
@ 85°C
FN6293.0
October 26, 2005
5
EL8171, EL8172
Typical Performance Curves (Continued)
200
600
25°C
25°C
500
400
300
200
100
0
Vs=5V
100
0
Vs=5.0V
Vs=2.9V
Vs=2.9V
Vs=3.3V
Vs=3.3V
-100
-200
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
COMMON-MODE INPUT VOLTAGE (V)
COMMON-MODE INPUT VOLTAGE (V)
FIGURE 11. EL8171 INPUT OFFSET VOLTAGE vs COMMON-
MODE INPUT VOLTAGE @ 25°C
FIGURE 12. EL8172 INPUT OFFSET VOLTAGE vs COMMON-
MODE INPUT VOLTAGE @ 25°C
600
100
-45°C
-45°C
500
400
300
200
100
0
0
-100
-200
-300
Vs=5V
Vs=5.0V
Vs=2.9V
Vs=2.9V
Vs=3.3V
Vs=3.3V
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
COMMON-MODE INPUT VOLTAGE (V)
COMMON-MODE INPUT VOLTAGE (V)
FIGURE 13. EL8171 INPUT OFFSET VOLTAGE vs COMMON-
MODE INPUT VOLTAGE @ -45°C
FIGURE 14. EL8172 INPUT OFFSET VOLTAGE vs COMMON-
MODE INPUT VOLTAGE @ -45°C
800
500
85°C
85°C
700
600
500
400
300
200
400
300
200
100
Vs=5V
Vs=2.9V
Vs=5.0V
Vs=3.3V
Vs=2.9V
Vs=3.3V
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
COMMON-MODE INPUT VOLTAGE (V)
COMMON-MODE INPUT VOLTAGE (V)
FIGURE 15. EL8171 INPUT OFFSET VOLTAGE vs COMMON-
MODE INPUT VOLTAGE @ 85°C
FIGURE 16. EL8172 INPUT OFFSET VOLTAGE vs COMMON-
MODE INPUT VOLTAGE @ 85°C
FN6293.0
6
October 26, 2005
EL8171, EL8172
Typical Performance Curves (Continued)
120
110
100
90
120
110
100
GAIN=100
90
80
80
70
60
GAIN=1000
GAIN=100
70
60
50
50
GAIN=10
40
40
1
10
100
1K
10K
100K
1M
1
10
100
1K
10K
100K
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 17. EL8171 CMRR vs FREQUENCY
FIGURE 18. EL8172 CMRR vs FREQUENCY
100
80
120
100
80
PSRR+
PSRR+
PSRR-
PSRR-
60
60
40
40
1
10
100
1K
10K
100K
1M
1
10
100
1K
10K
100K
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 19. EL8171 PSRR vs FREQUENCY
FIGURE 20. EL8172 PSRR vs FREQUENCY
1s/DIV
1s/DIV
FIGURE 21. EL8171 0.1Hz to 10Hz INPUT VOLTAGE NOISE
(GAIN = 10)
FIGURE 22. EL8172 0.1Hz to 10Hz INPUT VOLTAGE NOISE
(GAIN = 100)
FN6293.0
October 26, 2005
7
EL8171, EL8172
Typical Performance Curves (Continued)
70
60
50
40
30
20
10
0
2
2.5
3
3.5
SUPPLY VOLTAGE (V)
FIGURE 23. EL8171 AND EL8172 SUPPLY CURRENT vs SUPPLY VOLTAGE
4
4.5
5
5.5
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
CONDUCTIVITY TEST BOARD
1.4
1.2
1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
909mW
625mW
0.8
0.6
0.4
0.2
0
0
25
50
75 85 100
125
150
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
FIGURE 24. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 25. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FN6293.0
October 26, 2005
8
EL8171, EL8172
obsession of the EL8171 and EL8172 in-amp is to maintain
Description of Operation and Application
Information
Product Description
The EL8171 and EL8172 are micropower instrumentation
amplifiers (in-amps) which deliver rail-to-rail input
the differential voltage across FB+ and FB- equal to IN+ and
IN-; (FB+ - FB-) = (IN+ - IN-). Consequently, the transfer
function can be derived. The gain of the EL8171 and EL8172
is set by two external resistors, the feedback resistor RF, and
the gain resistor RG.
amplification and rail-to-rail output swing on a single 2.4V to
5V supply. The EL8171 and EL8172 also deliver excellent
DC and AC specifications while consuming only 60µA typical
supply current. Because EL8171 and EL8172 provide an
independent pair of feedback terminals to set the gain and to
adjust the output level, these in-amps achieve high common-
mode rejection ratio regardless of the tolerance of the gain
setting resistors. The EL8171 is internally compensated for a
minimum closed loop gain of 10 or greater, well suited for
moderate to high gains. For higher gains, the EL8172 is
internally compensated for a minimum gain of 100. An
ENABLE pin is used to reduce power consumption, typically
2.9µA, while the instrumentation amplifier is disabled.
2.9V to 5V
EN_BAR
7
1
VIN/2
VIN/2
VS+
EN
2
3
8
5
IN+
IN-
+
-
6
VOUT
EL8171/2
FB+
FB-
+
-
VCM
VS-
4
RG
RF
Input Protection
FIGURE 26. CIRCUIT 1 - GAIN IS BY EXTERNAL RESISTORS
R
AND R
All input and feedback terminals of the EL8171 and EL8172
have internal ESD protection diodes to both positive and
negative supply rails, limiting the input voltage to within one
diode drop beyond the supply rails. If overdriving the inputs
is necessary, the external input current must never exceed
5mA. External series resistor may be used as a protection to
limit excessive external voltage and current from damaging
the inputs.
F
G
R
F
VOUT = 1 + -------- VIN
R
G
In Figure 26, the FB+ pin and one end of resistor RG are
connected to GND. With this configuration, the above gain
equation is only true for a positive swing in VIN; negative
input swings will be ignored and the output will be at ground.
Input Stage and Input Voltage Range
Reference Connection
The input terminals (IN+ and IN-) of the EL8171 and EL8172
are single differential pair P-MOSFET devices aided by an
Input Range Enhancement Circuit to increase the headroom
of operation of the common-mode input voltage. The
feedback terminals (FB+ and FB-) also have a similar
topology. As a result, the input common-mode voltage range
of both the EL8171 and EL8172 is rail-to-rail. These in-amps
are able to handle input voltages that are at or slightly
beyond the supply and ground making these in-amps well
suited for single 5V or 3.3V low voltage supply systems.
There is no need then to move the common-mode input of
the in-amps to achieve symmetrical input voltage.
Unlike a three-opamp instrumentation amplifier, a finite
series resistance seen at the REF terminal does not degrade
the EL8171 and EL8172's high CMRR performance
eliminating the need for an additional external buffer
amplifier. Circuit 2 (Figure 27) uses the FB+ pin to provide a
high impedance REF terminal.
2.9V to 5V
EN_BAR
7
1
VIN/2
VIN/2
VS+
EN
2
3
8
5
IN+
IN-
+
-
6
VOUT
EL8171/2
FB+
FB-
+
-
Output Stage and Output Voltage Range
VCM
2.9V to 5V
A pair of complementary MOSFET devices drives the output
VOUT to within a few mV of the supply rails. At a 100kΩ
load, the PMOS sources current and pulls the output up to
4mV below the positive supply, while the NMOS sinks
current and pulls the output down to 4mV above the negative
supply, or ground in the case of a single supply operation.
The current sinking and sourcing capability of the EL8171
and EL8172 are internally limited to 29mA.
VS-
4
R1
REF
R2
RG
RF
FIGURE 27. CIRCUIT 2 - GAIN SETTING AND REFERENCE
CONNECTION
Gain Setting
R
R
F
R
G
F
VIN, the potential difference across IN+ and IN-, is replicated
(less the input offset voltage) across FB+ and FB-. The
VOUT = 1 + -------- (VIN) + 1 + -------- (VREF)
R
G
FN6293.0
9
October 26, 2005
EL8171, EL8172
The FB+ pin is used as a REF terminal to center or to adjust
error due to the tolerance of the resistors used. The resulting
non-ideal transfer function effectively becomes:
the output. Because the FB+ pin is a high impedance input,
an economical resistor divider can be used to set the voltage
at the REF terminal without degrading or affecting the CMRR
performance. Any voltage applied to the REF terminal will
shift VOUT by VREF times the closed loop gain, which is set
by resistors RF and RG. See Circuit 2 (Figure 27).
R
F
VOUT = 1 + -------- × [1 – (E
+ E
+ E )] × VIN
RF G
RG
R
G
Where:
ERG = Tolerance of RG
ERF = Tolerance of RF
The FB+ pin can also be connected to the other end of
resistor, RG. See Circuit 3 (Figure 28). Keeping the basic
concept that the EL8171 and EL8172 in-amps maintain
constant differential voltage across the input terminals and
feedback terminals (IN+ - IN- = FB+ - FB-), the transfer
function of Circuit 3 can be derived.
EG = Gain Error of the EL8171 or EL8172
The term [1-(ERG +ERF +EG)] is the deviation from the
theoretical gain. Thus, (ERG +ERF +EG) is the total gain
error. For example, if 1% resistors are used for the EL8171,
the total gain error would be:
2.9V to 5V
EN_BAR
7
1
= ±(E
+ E
+ E (typical))
RF G
VIN/2
VIN/2
RG
VS+
EN
2
3
8
5
IN+
IN-
+
= ±(0.01 + 0.01 + 0.003)
= ±2.3%
-
6
VOUT
EL8171/2
FB+
FB-
+
-
VCM
VS-
4
Disable/Power-Down
The EL8171 and EL8172 can be powered down reducing
the supply current to typically 2.9µA. When disabled, the
output is in a high impedance state. The active low ENABLE
bar pin has an internal pull down and hence can be left
floating and the in-amp enabled by default. When the
ENABLE bar is connected to an external logic, the in-amp
will power down when ENABLE bar is pulled above 2V, and
will power on when ENABLE bar is pulled below 0.8V.
RG
RF
VREF
FIGURE 28. CIRCUIT 3 - REFERENCE CONNECTION WITH AN
AVAILABLE VREF
R
F
VOUT = 1 + -------- (VIN) + (VREF)
R
G
A finite resistance Rs in series with the VREF source, adds
an output offset of VIN*(RS/RG). As the series resistance Rs
approaches zero, the gain equation is simplified to the above
equation for Circuit 3. VOUT is simply shifted by an amount
VREF.
External Resistor Mismatches
Because of the independent pair of feedback terminals
provided by the EL8171 and EL8172, the CMRR is not
degraded by any resistor mismatches. Hence, unlike a three
opamp and especially a two opamp in-amp, the EL8171 and
EL8172 reduce the cost of external components by allowing
the use of 1% or more tolerance resistors without sacrificing
CMRR performance. The EL8171 and EL8172 CMRR will be
108dB regardless of the tolerance of the resistors used.
Gain Error and Accuracy
The EL8172 has a Gain Error, EG, of 0.2% typical. The
EL8171 has an EG of 0.3% typical. The gain error indicated
in the electrical specifications table is the inherent gain error
of the EL8171 and EL8172 and does not include the gain
error contributed by the resistors. There is an additional gain
FN6293.0
10
October 26, 2005
EL8171, EL8172
Package Outline Drawing
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at
http://www.intersil.com/design/packages/index.asp
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6293.0
11
October 26, 2005
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