EL5175IY_技术文档

EL5175, EL5375

®

Data Sheet

February 11, 2005

FN7306.5

550MHz Differential Line Receivers

Features

• Differential input range ±2.3V

The EL5175 and EL5375 are single and triple high

bandwidth amplifiers designed to extract the difference

signal from noisy environments. They are primarily targeted

for applications such as receiving signals from twisted-pair

lines or any application where common mode noise injection

is likely to occur.

• 550MHz 3dB bandwidth

• 900V/µs slew rate

• 60mA maximum output current

• Single 5V or dual ±5V supplies

• Low power - 9.6mA per channel

• Pb-free available (RoHS compliant)

The EL5175 and EL5375 are stable for a gain of one and

requires two external resistors to set the voltage gain for

each channel.

The output common mode level is set by the reference pin

Applications

• Twisted-pair receivers

(V

), which has a -3dB bandwidth of over 450MHz.

REF

Generally, this pin is grounded but it can be tied to any

voltage reference.

• Differential line receivers

The output can deliver a maximum of ±60mA and is short

circuit protected to withstand a temporary overload

condition.

• VGA over twisted-pair

• ADSL/HDSL receivers

• Differential to single-ended amplification

• Reception of analog signals in a noisy environment

The EL5175 is available in the 8-pin SO and 8-pin MSOP

packages and the EL5375 in the 24-pin QSOP package. All

are specified for operation over the full -40°C to +85°C

temperature range.

Pinouts

EL5175

(8-PIN SO, MSOP)

TOP VIEW

EL5375

(24-PIN QSOP)

TOP VIEW

FB

IN+

IN-

1

2

3

4

8

7

6

5

OUT

VS-

VS+

EN

REF1

INP1

INN1

NC

1

2

3

4

5

6

7

8

9

24 NC

+

-

23 FB1

22 OUT1

21 NC

+

-

REF

REF2

INP2

INN2

NC

20 VSP

19 VSN

18 NC

+

-

17 FB2

16 OUT2

15 EN

REF3

+

-

INP3 10

INN3 11

NC 12

14 FB3

13 OUT3

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

1

All other trademarks mentioned are the property of their respective owners.

EL5175, EL5375

Ordering Information

PART

TAPE &

REEL

NUMBER

PACKAGE

8-Pin SO

PKG. DWG. #

EL5175IS

-

7”

13”

-

MDP0027

EL5175IS-T7

EL5175IS-T13

EL5175ISZ

(See Note 1)

8-Pin SO

(Pb-free)

EL5175ISZ-T7

(See Note 1)

8-Pin SO

(Pb-free)

7”

MDP0027

EL5175ISZ-T13

(See Note 1)

8-Pin SO

(Pb-free)

13”

EL5175IY

8-Pin MSOP

-

7”

13”

-

MDP0043

EL5175IY-T7

EL5175IY-T13

EL5175IYZ

(See Note 1)

8-Pin MSOP

(Pb-free)

EL5175IYZ-T7

(See Note 1)

8-Pin MSOP

(Pb-free)

7”

MDP0043

EL5175IYZ-T13

(See Note 1)

8-Pin MSOP

(Pb-free)

13”

EL5375IU

24-Pin QSOP

-

7”

13”

-

MDP0040

EL5375IU-T7

EL5375IU-T13

EL5375IUZ

(See Note 1, 2)

24-Pin QSOP

(Pb-free)

EL5375IUZ-T7

(See Note 1, 2)

24-Pin QSOP

(Pb-free)

7”

MDP0040

EL5375IUZ-T13

(See Note 1, 2)

24-Pin QSOP

(Pb-free)

13”

NOTES:

1. Intersil Pb-free products employ special Pb-free material sets;

molding compounds/die attach materials and 100% matte tin

plate termination finish, which are RoHS compliant and

compatible with both SnPb and Pb-free soldering operations.

Intersil Pb-free products are MSL classified at Pb-free peak

reflow temperatures that meet or exceed the Pb-free

requirements of IPC/JEDEC J STD-020.

2. Coming soon

FN7306.5

2

EL5175, EL5375

Absolute Maximum Ratings (T = 25°C)

A

Supply Voltage (V + to V -) . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V

Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +135°C

Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C

S

Maximum Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . ±60mA

Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are

at the specified temperature and are pulsed tests, therefore: T = T = T

A

J

C

Electrical Specifications

V + = +5V, V - = -5V, T = 25°C, V = 0V, R = 500Ω, R = 0, R = OPEN, C = 2.7pF, unless otherwise

S

A

IN

L

F

G

L

specified.

PARAMETER

DESCRIPTION

CONDITIONS

MIN

TYP

MAX

UNIT

AC PERFORMANCE

BW

-3dB Bandwidth

A

=1, C = 2.7pF

550

190

20

MHz

V/µs

ns

V

L

A

=2, R = 806, C = 2.7pF

F L

V

A

=10, R = 806, C = 2.7pF

F L

V

BW

SR

± 0.1dB Bandwidth

A

=1, C = 2.7pF

60

V

L

Slew Rate

V

= 3V , 20% to 80%, R = 100Ω

P-P

600

900

10

OUT

L

= 3V , 20% to 80%, R = 500Ω

P-P

L

T

Settling Time to 0.1%

= 2V

STL

Output Overdrive Recovery time

Gain Bandwidth Product

20

ns

OVR

GBWP

200

450

1000

21

MHz

V/µs

nV/√Hz

pA/√Hz

dBc

%

V

BW (-3dB) V

-3dB Bandwidth

Slew Rate

A =1, C = 2.7pF

V L

REF

N

REF

SR

V

= 2V , 20% to 80%

P-P

OUT

Input Voltage Noise

at f = 10kHz

I

Input Current Noise

2.7

-70

-66

-94

-84

0.1

90

N

HD2

HD3

dG

Second Harmonic Distortion

Third Harmonic Distortion

Differential Gain at 3.58MHz

Differential Phase at 3.58MHz

Channel Separation (EL5375)

V

= 1V , 5MHz

P-P

OUT

= 1V , 5MHz

P-P

= 1V , 5MHz

P-P

= 1V , 5MHz

P-P

R

= 150Ω , A =2

V

L

dθ

R

= 150Ω , A =2

°

V

e

at f = 100kHz

dB

S

INPUT CHARACTERISTICS

Input Referred Offset Voltage

V

EL5175

EL5375

-3

±40

±30

-6

mV

µA

kΩ

pF

V

OS

I

Input Bias Current (V , V , V

IN INB REF

)

-25

-12.5

150

1

IN

R

Differential Input Resistance

Differential Input Capacitance

Differential Mode Input Range

IN

C

DMIR

CMIR

±2.1

-4.3

±2.3

±2.5

+3.3

Common Mode Input Range at V +,

IN

V

-

IN

V

Reference Input Voltage Range

V

+ = V - = 0V

IN

-3.6

75

3.3

V

REFIN

CMRR

IN

Input Common Mode Rejection Ratio

= ±2.5V

95

dB

FN7306.5

3

EL5175, EL5375

Electrical Specifications

V + = +5V, V - = -5V, T = 25°C, V = 0V, R = 500Ω, R = 0, R = OPEN, C = 2.7pF, unless otherwise

S

A

IN

L

F

G

L

specified. (Continued)

DESCRIPTION

Gain Accuracy

PARAMETER

CONDITIONS

MIN

TYP

0.994

0.992

MAX

1.009

1.007

UNIT

V

Gain

EL5175, V = 1V

IN

0.979

0.977

EL5375, V = 1V

IN

V

OUTPUT CHARACTERISTICS

Positive Output Voltage Swing

V

R

= 500Ω to GND

= 10Ω

3.3

3.54

-3.95

±67

V

OUT

L

Negative Output Voltage Swing

Maximum Output Current

Output Impedance

-3.6

I

(Max)

OUT

±40

mA

mΩ

R

130

OUT

SUPPLY

V

Supply Operating Range

V + to V -

4.75

8

11

V

SUPPLY

S

I

Power Supply Current Per Channel -

Enabled

9.6

mA

S (on)

I

+

-

Positive Power Supply Current - Disabled EN pin tied to 4.8V, EL5175

EN pin tied to 4.8V, EL5375

80

1.7

100

5

µA

S (off)

I

Negative Power Supply Current -

Disabled

-150

45

-120

-90

PSRR

Power Supply Rejection Ratio

V

from ±4.5V to ±5.5V

56

dB

S

ENABLE

t

Enable Time

80

ns

µs

V

EN

DS

Disable Time

1.2

V

EN Pin Voltage for Power-up

V +

S

IH

-1.5

V

EN Pin Voltage for Shut-down

V +

S

V

IL

-0.5

I

EN Pin Input Current High Per Channel At V

= 5V

= 0V

40

-3

60

µA

IH-EN

IL-EN

EN

EN Pin Input Current Low Per Channel

At V

-10

FN7306.5

4

EL5175, EL5375

Pin Descriptions

EL5175

EL5375

PIN NAME

PIN FUNCTION

1

2

3

4

5

6

7

8

FB

IN+

Feedback input

Non-inverting input

Inverting input

IN-

REF

Sets the common mode output voltage level to V

REF

EN

Enabled when this pin is floating or the applied voltage ≤ V + - 1.5

S

VS+

Positive supply voltage

VS-

Negative supply voltage

OUT

Output voltage

1, 5, 9

2, 6, 10

3, 7, 11

REF1, 2, 3

INP1, 2, 3

INN1, 2, 3

NC

Reference input, controls common-mode output voltage

Non-inverting inputs

Inverting inputs

4, 8, 12, 18, 21, 24

No connect, grounded for best crosstalk performance

Non-inverting outputs

13, 16, 22

OUT1, 2, 3

FB1, 2, 3

EN

14, 17, 23

Feedback from outputs

15

19

20

Enabled when this pin is floating or the applied voltage ≤ V + - 1.5

S

VSN

Negative supply

Positive supply

VSP

FN7306.5

5

EL5175, EL5375

Typical Performance Curves

4

2

A =1

V

R =500Ω

R =100Ω

L

C =2.7pF

L

2

0

V =±5V

S

0

V =±5V

S

V =±2.5V

S

V =±2.5V

S

-2

-4

-6

-2

-4

-6

1M

10M

100M

1G

1M

10M

100M

1G

FREQUENCY (Hz)

FIGURE 1. FREQUENCY RESPONSE vs SUPPLY VOLTAGE

FIGURE 2. FREQUENCY RESPONSE vs SUPPLY VOLTAGE

4

5

V =±5V

S

C =15pF

L

R =500Ω

L

C =2.7pF

A =1

V

L

2

0

3

1

C =10pF

L

A =1

V

A =5

V

A =10

-2

-4

-6

-1

-3

-5

V

C =2.7pF

L

A =2

V

C =0pF

L

1M

10M

100M

1G

1M

10M

100M

1G

FREQUENCY (Hz)

FIGURE 3. FREQUENCY RESPONSE vs VARIOUS GAIN

FIGURE 4. FREQUENCY RESPONSE vs C

4

L

5

V =±2.5V

V =±5V

S

C =15pF

L

R =500Ω

L

A =1

A =2

V

3

1

2

0

R =1kΩ

R =806Ω

F

C =2.7pF

L

F

C =10pF

L

R =500Ω

F

R =200Ω

-1

-3

-5

-2

-4

-6

F

C =2.7pF

L

C =0pF

L

1M

10M

100M

1G

1M

10M

100M

1G

FREQUENCY (Hz)

FIGURE 5. FREQUENCY RESPONSE vs C

FIGURE 6. FREQUENCY RESPONSE FOR VARIOUS R

F

L

FN7306.5

7

EL5175, EL5375

Typical Performance Curves (Continued)

4

60

40

20

0

90

R =500Ω

L

A =1

V

C =2.7pF

L

2

0

-90

-180

-270

-360

V =±5V

S

V =±2.5V

-2

-4

-6

S

-20

-40

1M

10M

100M

1G

10K

100K

1M

10M

100M

1G

FREQUENCY (Hz)

FIGURE 7. FREQUENCY RESPONSE FOR V

FIGURE 8. OPEN LOOP GAIN

REF

100

30

10

1

-10

-30

-50

-70

-90

PSRR+

PSRR-

0.1

10K

100K

1M

10M

100M

10K

100K

1M

10M

100M

FREQUENCY (Hz)

FIGURE 9. OUTPUT IMPEDANCE vs FREQUENCY

FIGURE 10. PSRR vs FREQUENCY

120

100

80

1K

100

10

60

E

N

40

I

N

20

-90

1

1K

10K

100K

1M

10M

100M

1G

10

100

1K

10K

100K

1M

10M

FREQUENCY (Hz)

FIGURE 11. CMRR vs FREQUENCY

FIGURE 12. VOLTAGE AND CURRENT NOISE vs FREQUENCY

FN7306.5

8

EL5175, EL5375

Typical Performance Curves (Continued)

0

-20

-40

-50

V =±5V

S

f=5MHz

R =500Ω

L

-60

-70

CH1↔CH2, CH2↔CH3

-60

-80

CH1↔CH3

-90

-100

100K

1M

10M

100M

1G

1

2

3

4

5

6

7

FREQUENCY (Hz)

V

(V)

OP-P

FIGURE 13. CHANNEL ISOLATION vs FREQUENCY

(EL5375 ONLY)

FIGURE 14. HARMONIC DISTORTION vs OUTPUT VOLTAGE

-50

-60

-50

-60

-70

-80

HD2 (A =2)

V

HD

2 (

A =

1)

V

-70

-80

V =±5V

S

V =±5V

S

-90

f=5MHz

R =500Ω

L

1)

(A =

HD3

V

=1V (A =1)

V

=1V (A =1)

V

OP-P

V

OP-P

=2V (A =2)

V

-100

100 200 300 400 500 600 700 800 900 1K

0

5

10

15

20

25

30

35

40

R

(Ω)

R

(Ω)

LOAD

FIGURE 15. HARMONIC DISTORTION vs LOAD RESISTANCE

FIGURE 16. HARMONIC DISTORTION vs FREQUENCY

50mV/DIV

0.5V/DIV

10ns/DIV

FIGURE 17. SMALL SIGNAL TRANSIENT RESPONSE

FIGURE 18. LARGE SIGNAL TRANSIENT RESPONSE

FN7306.5

9

EL5175, EL5375

Typical Performance Curves (Continued)

M=100ns

CH1=200mV/DIV

CH2=5V/DIV

M=400ns

CH1=200mV/DIV

CH2=5V/DIV

CH1

CH2

CH1

CH2

100ns/DIV

400ns/DIV

FIGURE 19. ENABLED RESPONSE

JEDEC JESD51-3 LOW EFFECTIVE THERMAL

FIGURE 20. DISABLED RESPONSE

JEDEC JESD51-7 HIGH EFFECTIVE THERMAL

CONDUCTIVITY TEST BOARD

1.2

1.4

1.2

1

1.136W

1

QSOP24

JA

870mW

θ

=88°C/W

909mW

QSOP24

=115°C/W

0.8

0.6

0.4

0.2

0

θ

JA

SO8

=110°C/W

625mW

486mW

0.8 870mW

θ

JA

SO8

=160°C/W

0.6

0.4

0.2

0

MSOP8

=115°C/W

θ

JA

θ

JA

MSOP8

JA

θ

=206°C/W

0

25

50

75 85 100

125

150

0

25

50

75 85 100

125

150

AMBIENT TEMPERATURE (°C)

FIGURE 21. PACKAGE POWER DISSIPATION vs AMBIENT

TEMPERATURE

FIGURE 22. PACKAGE POWER DISSIPATION vs AMBIENT

TEMPERATURE

Simplified Schematic

V +

S

I

R

4

1

2

3

4

3

R

D2

D1

Q

8

V

VIN+

VIN-

V

FB

Q

7

B1

REF

Q

4

1

2

3

Q

9

x1

V

OUT

Q

6

25

V

B2

C

R

1

2

V -

S

FN7306.5

10

EL5175, EL5375

Choice of Feedback Resistor and Gain Bandwidth

Description of Operation and Application

Information

Product Description

Product

For applications that require a gain of +1, no feedback

resistor is required. Just short the OUT+ pin to FBP pin and

OUT- pin to FBN pin. For gains greater than +1, the

feedback resistor forms a pole with the parasitic capacitance

at the inverting input. As this pole becomes smaller, the

amplifier's phase margin is reduced. This causes ringing in

the time domain and peaking in the frequency domain.

The EL5175 and EL5375 are wide bandwidth, low power

and single/differential ended to single ended output

amplifiers. The EL5175 is a single channel differential to

single ended amplifier. The EL5375 is a triple channel

differential to single ended amplifier. The EL5175 and

EL5375 are internally compensated for closed loop gain of

+1 of greater. Connected in gain of 1 and driving a 500Ω

load, the EL5175 and EL5375 have a -3dB bandwidth of

550MHz. Driving a 150Ω load at gain of 2, the bandwidth is

about 130MHz. The bandwidth at the REF input is about

450MHz. The EL5175 and EL5375 is available with a power

down feature to reduce the power while the amplifier is

disabled.

Therefore, R has some maximum value that should not be

F

exceeded for optimum performance. If a large value of R

F

must be used, a small capacitor in the few Pico farad range

in parallel with R can help to reduce the ringing and

F

peaking at the expense of reducing the bandwidth.

The bandwidth of the EL5175 and EL5375 depends on the

load and the feedback network. R and R appear in

F

G

parallel with the load for gains other than +1. As this

combination gets smaller, the bandwidth falls off.

Input, Output, and Supply Voltage Range

Consequently, R also has a minimum value that should not

The EL5175 and EL5375 have been designed to operate

with a single supply voltage of 5V to 10V or a split supplies

with its total voltage from 5V to 10V. The amplifiers have an

input common mode voltage range from -4.3V to 3.3V for

±5V supply. The differential mode input range (DMIR)

between the two inputs is about from -2.3V to +2.3V. The

input voltage range at the REF pin is from -3.6V to 3.3V. If

the input common mode or differential mode signal is outside

the above-specified ranges, it will cause the output signal

distorted.

F

be exceeded for optimum bandwidth performance. For gain

of +1, R = 0 is optimum. For the gains other than +1,

F

optimum response is obtained with R between 500Ω to

F

1kΩ. For A = 2 and R = R = 806Ω, the BW is about

V

F

G

190MHz and the frequency response is very flat.

The EL5175 and EL5375 have a gain bandwidth product of

200MHz. For gains ≥5, its bandwidth can be predicted by the

following equation:

Gain × BW = 200MHz

The output of the EL5175 and EL5375 can swing from -3.9V

to 3.5V at 500Ω load at ±5V supply. As the load resistance

becomes lower, the output swing is reduced respectively.

Driving Capacitive Loads and Cables

The EL5175 and EL5375 can drive 15pF capacitance in

parallel with 500Ω load to ground with less than 4.5dB of

peaking at gain of +1. If less peaking is desired in

Over All Gain Settings

The gain setting for the EL5175 and EL5375 is similar to the

conventional operational amplifier. The output voltage is

equal to the difference of the inputs plus V

times the gain.

applications, a small series resistor (usually between 5Ω to

50Ω) can be placed in series with each output to eliminate

most peaking. However, this will reduce the gain slightly. If

and then

REF

R

the gain setting is greater than 1, the gain resistor R can









G

F

V

= (V + – V - + V

) × 1 + --------



O

IN

REF

then be chosen to make up for any gain loss which may be

created by the additional series resistor at the output.

R



G

When used as a cable driver, double termination is always

recommended for reflection-free performance. For those

applications, a back-termination series resistor at the

amplifier's output will isolate the amplifier from the cable and

allow extensive capacitive drive. However, other applications

may have high capacitive loads without a back-termination

resistor. Again, a small series resistor at the output can help

to reduce peaking.

EN

V

+

IN

+

IN

V

-

Σ

G/B

V

O

V

+

-

REF

FB

R

F

Disable/Power-Down

R

G

The EL5175 and EL5375 can be disabled and placed its

outputs in a high impedance state. The turn off time is about

1.2µs and the turn on time is about 80ns. When disabled, the

FIGURE 23.

amplifier's supply current is reduced to 80µA for I + and

S

FN7306.5

11

EL5175, EL5375

120µA for I - typically, thereby effectively eliminating the

For sourcing:

S

power consumption. The amplifier's power down can be

V

OUT

controlled by standard CMOS signal levels at the ENABLE

-------------------

PD

=

V

× I

+ (V + – V

OUT

) ×

× i

MAX

S

SMAX

S

R

LOAD

pin. The applied logic signal is relative to V + pin. Letting the

S

EN pin float or applying a signal that is less than 1.5V below

For sinking:

V + will enable the amplifier. The amplifier will be disabled

S

when the signal at EN pin is above V + - 0.5V. If a TTL

S

signal is used to control the enabled/disabled function,

PD

= [V × I

+ (V

– V -) × I

] × i

LOAD

MAX

S

SMAX

OUT

S

Figure 22 could be used to convert the TTL signal to CMOS

signal.

Where:

• V = Total supply voltage

5V

S

10K

• I

= Maximum quiescent supply current per channel

= Maximum output voltage of the application

SMAX

EN

1K

CMOS/TTL

• V

• R

OUT

= Load resistance

LOAD

• I

= Load current

LOAD

• i = Number of channels

By setting the two PD

FIGURE 24.

Output Drive Capability

equations equal to each other, we

MAX

The EL5175 and EL5375 have internal short circuit

protection. Its typical short circuit current is ±67mA. If the

output is shorted indefinitely, the power dissipation could

easily increase such that the part will be destroyed.

Maximum reliability is maintained if the output current never

exceeds ±60mA. This limit is set by the design of the internal

metal interconnections.

can solve the output current and R

overheat.

to avoid the device

LOAD

Power Supply Bypassing and Printed Circuit

Board Layout

As with any high frequency device, a good printed circuit

board layout is necessary for optimum performance. Lead

lengths should be as sort as possible. The power supply pin

must be well bypassed to reduce the risk of oscillation. For

Power Dissipation

With the high output drive capability of the EL5175 and

EL5375. It is possible to exceed the 135°C absolute

maximum junction temperature under certain load current

conditions. Therefore, it is important to calculate the

maximum junction temperature for the application to

determine if the load conditions or package types need to be

modified for the amplifier to remain in the safe operating

area.

normal single supply operation, where the V - pin is

S

connected to the ground plane, a single 4.7µF tantalum

capacitor in parallel with a 0.1µF ceramic capacitor from V +

S

to GND will suffice. This same capacitor combination should

be placed at each supply pin to ground if split supplies are to

be used. In this case, the V - pin becomes the negative

supply rail.

S

For good AC performance, parasitic capacitance should be

kept to minimum. Use of wire wound resistors should be

avoided because of their additional series inductance. Use

of sockets should also be avoided if possible. Sockets add

parasitic inductance and capacitance that can result in

compromised performance. Minimizing parasitic capacitance

at the amplifier's inverting input pin is very important. The

feedback resistor should be placed very close to the

inverting input pin. Strip line design techniques are

recommended for the signal traces.

The maximum power dissipation allowed in a package is

determined according to:

T

– T

AMAX

JMAX

PD

= --------------------------------------------

MAX

Θ

JA

• T

= Maximum junction temperature

= Maximum ambient temperature

JMAX

AMAX

• θ = Thermal resistance of the package

JA

Assume the REF pin is tired to GND for V = ±5V

S

application, the maximum power dissipation actually

produced by an IC is the total quiescent supply current times

the total power supply voltage, plus the power in the IC due

to the load, or:

FN7306.5

12

EL5175, EL5375

Typical Applications

0Ω

50

V

FB

50Ω

IN

EL5173/

EL5373

EL5175/

EL5375

V

OUT

V

INB

Z

= 100Ω

O

REF

FIGURE 25. TWISTED PAIR CABLE RECEIVER

As the signal is transmitted through a cable, the high

frequency signal will be attenuated. One way to compensate

this loss is to boost the high frequency gain at the receiver

side.

R

2

3

1

Gain

(dB)

C

1

1 + R / R

2

1

V

FB

IN

50Ω

EL5175/

EL5375

V

OUT

V

INB

1 + R / (R + R )

2

1

3

Z

= 100Ω

O

REF

f

A

C

FIGURE 26. COMPENSATED LINE RECEIVER

Level Shifter and Signal Summer

The EL5175 and EL5375 contains two pairs of differential

pair input stages. It makes the inputs are all high impedance

inputs. To take advantage of the two high impedance inputs,

the EL5175 and EL5375 can be used as a signal summer to

add two signals together. Like, one signal can be applied to

V

+, the second signal can be applied to REF and V - is

IN

ground. The output is equal to:

IN

V

= (V + + V

) × Gain

REF

O

IN

Also, the EL5175 and EL5375 can be used as a level shifter

by applying a level control signal to the REF input.

FN7306.5

13

EL5175, EL5375

SO Package Outline Drawing

FN7306.5

14

EL5175, EL5375

MSOP Package Outline Drawing

FN7306.5

15

EL5175, EL5375

QSOP Package Outline Drawing

NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at

http://www.intersil.com/design/packages/index.asp

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN7306.5

16


型号：	EL5175IY
厂家：	Intersil
描述：	550MHz Differential Line Receivers 550MHz的差动线路接收器
文件：	总16页 (文件大小：673K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

EL5175IY [INTERSIL]

相关型号：

EL5175IY-T13

EL5175IY-T7

EL5175IYZ

EL5175IYZ-T13

EL5175IYZ-T7

EL5175_07

EL5176

EL5176IY

EL5176IY-T13

EL5176IY-T7

EL5176IYZ

EL5176IYZ-T