DG526BK [INTERSIL]
Analog CMOS Latchable Multiplexers; CMOS模拟多路复用器可锁存
| 型号： | DG526BK |
| 厂家： | 
Intersil |
| 描述： | Analog CMOS Latchable Multiplexers |
| 文件： | 总16页 (文件大小：311K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DG526, DG527,
DG528, DG529
Semiconductor
Analog CMOS
April 1999
Latchable Multiplexers
Features
Description
• Direct RESET
The DG526, DG527, DG528, and DG529 are CMOS
Monolithic 16-Channel/Dual 4-Channel Analog Multiplexers.
Each device has on-chip address and control latches to sim-
plify design in microprocessor based applications. The DG526
uses 4 address lines to control its 16 channels; the DG527,
DG528 both use 3 address lines to control their 8 channels;
and the DG529 uses 2 address lines to control its 4 channels.
The enable pin is used to enable the address latches during
the WR pulse. It can be hard wired to the logic supply if one of
the channels will always be used (except during a reset) or it
can be tied to address decoding circuitry for memory mapped
operation. The RS pin is used to clear all latches regardless of
the state of any other latch or control line. The WR pin is used
to transfer the state of the address control lines to their
latches, except during a reset or when EN is low.
• TTL and CMOS Compatible Address and Enable
Inputs
• Maximum Power Supply Rating . . . . . . . . . . . . . . . .44V
• Break-Before-Make Switching
• Alternate Source
Applications
• Data Acquisition Systems
• Communication Systems
• Automatic Test Equipment
• Microprocessor Controlled Systemd
A channel in the ON state conducts signals equally well in
both directions. In the OFF state each channel blocks volt-
ages up to the supply rails. The address inputs, WR, RS and
the enable input are TTL and CMOS compatible over the full
specified operation temperature range.
Part Number Information
PART
NUMBER
TEMP.
RANGE ( C)
PART
NUMBER
TEMP.
RANGE ( C)
o
o
PACKAGE
PKG. NO.
F28.6
F28.6
F28.6
M28.3
E28.6
F28.6
M28.3
F28.6
F28.6
F28.6
M28.3
E28.6
F28.6
M28.3
PACKAGE
PKG. NO.
F18.3
F18.3
F18.3
M18.3
E18.3
F18.3
M18.3
F18.3
F18.3
F18.3
M18.3
E18.3
F18.3
M18.3
DG526AK
-55 to 125 28 Ld CERDIP
-55 to 125 28 Ld CERDIP
DG528AK
-55 to 125 18 Ld CERDIP
-55 to 125 18 Ld CERDIP
DG526AK/883B
DG526BK
DG526BY
DG526CJ
DG528AK/883B
DG528BK
DG528BY
DG528CJ
-25 to 85
-25 to 85
0 to 70
28 Ld CERDIP
28 Ld SOIC
28 Ld PDIP
-25 to 85
-25 to 85
0 to 70
18 Ld CERDIP
18 Ld SOIC
18 Ld PDIP
DG526CK
DG526CY
DG527AK
DG527AK/883B
DG527BK
DG527BY
DG527CJ
0 to 70
28 Ld CERDIP
28 Ld SOIC
DG528CK
DG528CY
DG529AK
DG529AK/883B
DG529BK
DG529BY
DG529CJ
0 to 70
18 Ld CERDIP
18 Ld SOIC
0 to 70
0 to 70
-55 to 125 28 Ld CERDIP
-55 to 125 28 Ld CERDIP
-55 to 125 18 Ld CERDIP
-55 to 125 18 Ld CERDIP
-25 to 85
-25 to 85
0 to 70
28 Ld CERDIP
28 Ld SOIC
28 Ld PDIP
-25 to 85
-25 to 85
0 to 70
18 Ld CERDIP
18 Ld SOIC
18 Ld PDIP
DG527CK
DG527CY
0 to 70
28 Ld CERDIP
28 Ld SOIC
DG529CK
DG529CY
0 to 70
18 Ld CERDIP
18 Ld SOIC
0 to 70
0 to 70
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
File Number 3139.2
Copyright © Harris Corporation 1999
12-1
DG526, DG527, DG528, DG529
Pinouts
DG526
(PDIP, CERDIP, SOIC)
TOP VIEW
DG527
(PDIP, CERDIP, SOIC)
TOP VIEW
V+
NC
RS
1
28 D
27 V-
V+
1
2
28 D
B
2
3
D
27 V-
B
26 S
25 S
24 S
23 S
22 S
21 S
3
26 S
25 S
24 S
23 S
22 S
21 S
RS
8
7
6
5
4
3
2
1
8A
7A
6A
5A
4A
3A
2A
1A
S
4
S
4
16
15
14
13
12
8B
7B
6B
5B
4B
3B
2B
1B
S
S
S
S
5
S
S
S
S
S
S
S
5
6
6
7
7
8
8
S
9
20
9
20
S
S
11
S
10
11
19 S
10
11
19 S
10
S
18 EN
18 EN
9
GND 12
WR 13
17 A
16 A
15 A
GND 12
WR 13
NC 14
17 A
16 A
15 A
0
1
2
0
1
2
A
14
3
DG528
DG529
(PDIP, CERDIP, SOIC)
(PDIP, CERDIP, SOIC)
TOP VIEW
TOP VIEW
1
2
3
4
5
6
7
8
9
18
17
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
WR
RS
WR
RS
A
A
A
A
1
0
1
0
GND
V+
EN
V-
16 A
EN
V-
2
15 GND
14 V+
S
S
1
S
1B
1A
2A
3A
4A
S
S
2
13 S
5
S
S
S
2B
S
S
3
12
11
10
S
S
S
3B
6
7
8
S
4
S
4B
D
D
A
D
B
12-2
DG526, DG527, DG528, DG529
Functional Diagrams
DG526
16-CHANNEL SINGLE ENDED MULTIPLEXER
DG527
DIFFERENTIAL 8-CHANNEL MULTIPLEXER
V+
V-
GND
V+
V-
GND
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
1
2
3
4
5
6
7
8
9
1A
2A
3A
4A
5A
6A
7A
8A
1B
2B
3B
4B
5B
6B
7B
8B
D
A
D
S
10
S
S
11
D
12
13
14
15
16
B
S
S
S
S
RS
RS
WR
DECODER LOGIC AND LATCHES
WR
DECODER LOGIC AND LATCHES
A
A
A
A
EN
A
A
A
0
EN
3
2
1
0
2
1
DG528
8-CHANNEL SINGLE ENDED MULTIPLEXER
DG529
DUAL 4-CHANNEL MULTIPLEXER
V+
V-
GND
V+
V-
GND
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
1
2
3
4
5
6
7
8
1A
2A
3A
4A
D
A
D
1B
2B
3B
4B
D
B
DECODER LOGIC AND LATCHES
LATCHES
DECODERLOGICANDLATCHES
LATCHES
RS
RS
WR
WR
A
A
A
EN
A
A
0
EN
2
1
0
0
12-3
DG526, DG527, DG528, DG529
Schematic Diagrams
LOGIC INTERFACE AND LEVEL SHIFTER
V+
+
LOGIC
TO
DECODER
-
TRIP
POINT
REF
GND
A , EN,
X
RS, WR
V-
DECODER AND SWITCH
V+
S
X
A ‘
X
V+
EN‘
RS‘
DE-
CODER
WR‘
D
X
V-
12-4
DG526, DG527, DG528, DG529
Absolute Maximum Ratings
Thermal Information
o
o
V+ to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +44V Thermal Resistance (Typical, Note 1)
θ
( C/W)
θ
( C/W)
JA
JC
V- to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-25V
18 Ld PDIP Package . . . . . . . . . . . . . .
18 Ld CERDIP Package . . . . . . . . . . .
18 Ld SOIC Package. . . . . . . . . . . . . .
28 Ld PDIP Package . . . . . . . . . . . . . .
28 Ld CERDIP Package . . . . . . . . . . .
28 Ld SOIC Package. . . . . . . . . . . . . .
90
75
95
60
55
70
N/A
22
N/A
N/A
18
V
V
V
to Ground (Note 1). . . . . . . . . . . . . . . . . . . . (V- - 2V), (V+ + 2V)
IN
S
or V to V+ (Note 1) . . . . . . . . . . . . . . . . . . . . . . . .+2V, (V- - 2V)
D
or V to V- (Note 1). . . . . . . . . . . . . . . . . . . . . . . . -2V, (V+ + 2V)
S
D
Current, Any Terminal Except S or D . . . . . . . . . . . . . . . . . . . .30mA
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . .20mA
N/A
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40mA Maximum Junction Temperature
o
(Pulsed at 1ms, 10% Duty Cycle Max)
Ceramic Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 C
o
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range
Operating Conditions
o
o
Operating Temperature
C Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 C to 70 C
B Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25 C to 85 C
A Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
C Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65 C to 125 C
A and B Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300 C
(SOIC - Lead Tips Only)
o
o
o
o
o
o
o
o
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
o
Electrical Specifications (Note 3) V+ = +15V, V- = -15V, GND = 0V, WR = 0V, RS = 2.4V, EN = 2.4V, T = 25 C,
A
Unless Otherwise Specified
A SUFFIX
B AND C SUFFIX
(NOTE 6)
(NOTE 2)
(NOTE 2)
PARAMETER
DYNAMIC
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
SwitchingTime DG526, See Figure 3 (Note 7)
of Multiplexer, DG527
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.65
0.6
0.2
0.2
0.7
1
1
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.65
0.6
0.2
0.2
0.7
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
µs
µs
µs
µs
µs
µs
µs
µs
dB
dB
pF
pF
pF
pF
t
TRANSITION
DG528, See Figure 3
DG529
Break-Before- DG526, See Figure 4
Make Interval, DG527
t
OPEN
DG528,
DG529
-
Enable and
DG526, See Figures 1, 6 (Note 7)
1.5
1.5
1
1
-
Write Turn-ON DG527
Time,
DG528, See Figures 5, 6 (Note 7)
DG529
t
(EN, WR)
ON
Enable and
Reset Turn
OFF Time,
DG526, See Figures 2, 7 (Note 7)
DG527
0.4
0.4
55
68
6
0.4
0.4
55
68
6
DG528, See Figures 5, 6 (Note 7)
DG529
t
(EN, RS)
OFF
Off Isolation,
OIRR
DG526,
DG527
V
V
= 0V, R = 1kΩ, C = 15pF,
L
EN
= 7V
, f = 500kHz (Note 4)
S
RMS
DG528,
DG529
-
Logic Input
Capacitance,
DG526, f = 1MHz
DG527
-
C
IN
DG528,
DG529
2.5
10
5
-
2.5
10
5
Source OFF
Capacitance,
DG526,
DG527
V
= 0V
V
= 0V,
-
S
EN
f = 140kHz
C
S(OFF)
DG528,
DG529
-
12-5
DG526, DG527, DG528, DG529
o
Electrical Specifications (Note 3) V+ = +15V, V- = -15V, GND = 0V, WR = 0V, RS = 2.4V, EN = 2.4V, T = 25 C,
A
Unless Otherwise Specified (Continued)
A SUFFIX
B AND C SUFFIX
(NOTE 6)
(NOTE 2)
(NOTE 2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
65
35
25
12
6
MAX
UNITS
pF
Drain OFF
Capacitance,
DG526
DG527
DG528
DG529
V
= 0V
V
= 0V,
-
-
-
-
-
65
35
25
12
6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
D
EN
f = 140kHz
pF
C
D(OFF)T
pF
pF
Charge
Injection, Q
DG526, See Figure 8
DG527
pC
DG528,
DG529
-
4
-
-
4
-
pC
INPUT
Address Input DG526,
Current, Input DG527
Voltage High,
V
= 2.4V
= 15V
= 2.4V
= 15V
-10
-
0.02
0.02
-
10
-
-10
-
0.02
0.02
-
10
-
µA
µA
µA
µA
µA
µA
µA
µA
A
V
A
I
DG528,
DG529
V
-10
-
-0.002
0.006
0.01
-10
-
-0.002
0.006
0.01
AH
A
V
10
-
10
-
A
Address Input DG526
Current, Input DG527
Voltage Low,
V
V
V
V
= 2.4V
= 0V
All V = 0V,
A
RS = 0V,
WR = 0V
-10
-10
-10
-10
-10
-10
-10
-10
EN
EN
EN
EN
0.01
-
0.01
-
I
DG528
DG529
= 2.4V
= 0V
-0.002
-0.002
-
-0.002
-0.002
-
AL
-
-
SWITCH
Analog Signal Range,
(Note 7)
-15
-
-
+15
400
-15
-
-
+15
450
V
V
ANALOG
Drain Source ON
Resistance, r
V
= ±10V, V = 0.8V, V = 2.4V,
AL AH
270
270
Ω
D
I
= -200µA
DS(ON)
L
Sequence Each Switch ON
Greatest Change in Drain -10V ≤ V ≤ 10V
-
6
-
-
6
-
%
S
Source ON Resistance
r
- r
DS(ON)MAX DS(ON)MIN
Dr
DS(ON)
=
Between Channels,
∆r
r
DS(ON)AVG.
DS(ON)
Source OFF
Leakage
Current,
DG526,
DG527
V
V
= 0V
= 0V
V
V
= ±10V,
= +10V
-1
-1
0.02
-0.005
0.2
1
1
-
-5
-
0.02
-0.005
0.2
-
5
-
nA
nA
nA
nA
nA
nA
nA
nA
EN
EN
S
D
DG528,
DG529
V
V
= ±10V,
= +10V
S
D
I
S(OFF)
Drain OFF
Leakage
Current,
DG526
DG527
DG528
DG529
V
V
= ±10V,
= +10V
-10
-5
10
5
S
D
V
V
= ±10V,
= +10V
0.2
-
0.2
-
S
D
I
D(OFF)
V
V
= ±10V,
= +10V
-10
-10
-10
-5
-0.015
-0.008
0.2
10
10
10
5
-20
-20
-
0.015
0.008
0.2
20
20
-
S
D
V
V
= ±10V,
= +10V
S
D
Drain ON
Leakage
DG526 Sequence Each
Switch On
V
±10V
= V
=
=
D
S(ALL)
Current,I
V
= 0.8V and
= 2.4V
D(ON)
AL
DG527
V
±10V
= V
0.2
-
0.2
-
D
S(ALL)
V
AH
(Note 5)
12-6
DG526, DG527, DG528, DG529
o
Electrical Specifications (Note 3) V+ = +15V, V- = -15V, GND = 0V, WR = 0V, RS = 2.4V, EN = 2.4V, T = 25 C,
A
Unless Otherwise Specified (Continued)
A SUFFIX
B AND C SUFFIX
(NOTE 6)
(NOTE 2)
(NOTE 2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Drain ON
DG528 Sequence Each
Switch On
V
±10V
= V
=
=
-10
-0.03
10
-20
-0.03
20
nA
D
S(ALL)
Leakage
Current,I
V
V
= 0.8V and
= 2.4V
D(ON)
AL
DG529
V
±10V
= V
-10
-0.015
10
-20
-0.015
20
nA
D
S(ALL)
(Continued)
AH
(Note 5)
SUPPLY
Positive
Supply
Current, I+
DG526,
DG527
V
V
= 0V
= 0V
All V = 0V
-
2.0
3.0
2.5
-
-
2.0
-
mA
mA
mA
mA
EN
EN
A
DG528,
DG529
-
-
-1.2
-
-
-
-
-1.2
-
-2.5
Positive
Supply
Current, I-
DG526,
DG527
All V = 0V
-2.0
-1.5
-
-
A
DG528,
DG529
-
-1.5
Electrical Specifications T = Over Operating Temperature Range, V+ = +15V, V- = -15V, GND = 0V, WR = 0V,
A
RS = 2.4V, EN = 2.4V Unless Otherwise Specified
A SUFFIX
B AND C SUFFIX
(NOTE 6)
(NOTE 2)
(NOTE 2)
PARAMETER
INPUT
Address Input Current
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
V
= 2.4V
-30
-
-
-
-
-
-
-
-
30
-
-30
-
-
-
-
-
-
-
-
30
-
µA
µA
µA
µA
µA
µA
A
Input Voltage High, I
AH
V
= 15V
= 2.4V
= 0V
A
Address Input DG526,
Current, Input DG527
Voltage Low,
V
V
=
-10
-10
-30
-30
-
A
A(ALL)
0V,
V
-
-
-
A
RS = 0V,
WR = 0V
I
AL
DG528,
DG529
-
-30
-30
-
V
= 0V
-
-
A
SWITCH
Analog Signal Range,
Note 7
-15
-
-
-
-
+15
500
50
-
-
-
-
-
-
-
500
-
%
Ω
V
ANALOG
Drain Source ON
Resistance, r
V
= ±10V, V = 0.8V, V = 2.4V,
AL AH
D
I
= -200µA, Sequence Each Switch ON
DS(ON)
Source Off Leakage
Current, I
S
V
= 0V
= 0V
V
V
= ±10V,
= +10V
-50
nA
EN
EN
S
D
S(OFF)
Drain OFF
Leakage
Current,
DG526
DG527
DG528
DG529
V
V
V
= ±10V,
= +10V
-300
-200
-200
-100
-300
-200
-200
-100
-
-
-
-
-
-
-
-
300
200
200
100
300
200
200
100
-300
-200
-200
-100
-300
-200
-200
-100
-
-
-
-
-
-
-
-
300
200
200
100
300
200
200
100
nA
nA
nA
nA
nA
nA
nA
nA
S
D
I
D(OFF)
V
V
= +10V,
= ±10V
S
D
Drain ON
Leakage
Current, I
DG526 Sequence Each Switch
V
V
±10V
=
D
On, V = 0.8V,
=
AL
S(ALL)
DG527
DG528
DG529
V
= 2.4V (Note 5)
D(ON)
AH
12-7
DG526, DG527, DG528, DG529
Minimum Input Timing Requirements Over Full Temperature Range
PARAMETER
MEASURED TERMINAL
WR, See Figure 1
A , A , (A ), EN, WR; See Figure 1
MIN
300
180
30
UNITS
ns
WRITE Pulse Width, t
WW
A, EN Data Valid After WRITE (Stabilization Time), t
ns
DW
0
1
2
A, EN Data Valid After WRITE (Hold Time), t
A , A , (A ), EN, WR; See Figure 1
ns
WD
0
1
2
RESET Pulse Width, t
NOTES:
RS, (Note 6), V = 5V, See Figure 2
500
ns
RS
S
1. Signals on V , V or V exceeding V+ or V- will be clamped by internal diodes. Limit diode forward current to maximum current ratings.
IN
S
D
2. Typical values are for design aid only, not guaranteed and not subject to production testing.
3. The algebraic convention whereby the most negative value is a minimum, and most positive value is a maximum, is used in this datasheet.
V
S
V
D
---------
4. OFF Isolation = 20
, where V = input to OFF switch, and V = output due to V .
S D S
5. I
is leakage from driver into “ON” switch.
D(ON)
6. Period of Reset (RS) pulse must be at least 50µs during or after power ON.
7. Parameter not tested. Parameter guaranteed by design or characterization.
Test Circuits and Waveforms
3V
3V
0
WR
1.5V
RS
1.5V
0
t
t
RS
WW
t
WD
t
t
DW
OFF(RS)
3V
0
V
O
2.0V
0.8V
O
A , A , (A )
0
1
2
SWITCH
OUTPUT
EN
0.8V
0V
FIGURE 1. WR TIMING WAVEFORMS
FIGURE 2. RS TIMING WAVEFORMS
+15V
+15V
+2.4V
+2.4V
V+
S
V+
S
±10V
±10V
EN
RS
EN
RS
1
7
1B
DG528†
DG529†
S
THRU S
S
S
THRU S
4A,
2
2A
D
A
3B
S
, AND S
A
0
2B
S
+10V
+10V
8
4B
A
1
A
0
SWITCH
OUTPUT
SWITCH
OUTPUT
A
2
A
1
D
D
V
V
B
D
LOGIC
INPUT
LOGIC
INPUT
DB
GND
WR
V-
GND
WR
V-
50Ω
1MΩ
35pF
50Ω
1MΩ
35pF
-15V
-15V
FIGURE 3A. t
SWITCHING TIME TEST CIRCUIT
FIGURE 3B. t
SWITCHING TIME TEST CIRCUIT
TRANSITION
TRANSITION
† Similar connections for DG527
† Similar connections for DG526
12-8
DG526, DG527, DG528, DG529
Test Circuits and Waveforms (Continued)
3V
50%
0
V
S1
S1
0.8V
SWITCH
OUTPUT
0
V
D
0.8V
V
S8
S8
S
ON
8
TRANSITION
ON
S
1
TRANSITION
LOGIC INPUT
t < 20ns
r
t < 20ns
f
FIGURE 3C. t
SWITCHING TIME WAVEFORM
+2.4V
TRANSITION
+15V
3V
50%
0
V+
EN
RS
DG528†
DG529
ALL S AND D
A
+5V
SWITCH
OUTPUT
VS
V
D
80%
SWITCH
OUTPUT
A , A , (A )
D
(D)
0
1
2
V
B
LOGIC
D
0V
INPUT
GND
WR
V-
t
OPEN
50Ω
1kΩ
35pF
LOGIC INPUT
t < 20ns
-15V
r
t < 20ns
f
FIGURE 4A. t
(BREAK-BEFORE-MAKE) SWITCHING TIME
FIGURE 4B. t
(BREAK-BEFORE-MAKE) SWITCHING TIME
TEST CIRCUIT
OPEN
OPEN
WAVEFORM
† Similar connections for DG526, DG527
+2.4V
+15V
+2.4V
+15V
V+
V+
S
RS
EN
RS
EN
-5V
-5V
S
1B
1
7
DG529†
DG528†
S
THRU S
1A
D
4A,
,
, S , S
S
THRU S
A
2B 3B
2
S
4B
A
A
A
0
1
2
A
A
0
SWITCH
OUTPUT
V
SWITCH
OUTPUT
D
D
1
V
B
DB
D
GND
WR
V-
50Ω
GND
WR
V-
EN
50Ω
EN
1kΩ
35pF
1kΩ
35pF
-15V
-15V
FIGURE 5A. ENABLE t
CIRCUIT
† Similar connections for DG526
AND t
OFF
SWITCHING TIME TEST
FIGURE 5B. ENABLE t
CIRCUIT
† Similar connections for DG527
AND t SWITCHING TIME TEST
OFF
ON
ON
12-9
DG526, DG527, DG528, DG529
Test Circuits and Waveforms (Continued)
3V
50%
0
t
(EN)
ON
t
(EN)
OFF
SWITCH
OUTPUT
0
O
V
D
0.1V
0.9V
O
V
O
V
S
EN
t < 20ns
f
r
t < 20ns
FIGURE 5C. ENABLE t
ON
AND t
SWITCHING TIME WAVEFORMS
OFF
+15V
+2.4V
t < 20ns
f
r
t < 20ns
V+
OR
EN
+5V
S
3V
1.5V
0V
1
DG528
DG529†
S
1B
50%
A , A , (A
0
1
2)
REMAINING
SWITCHES
SWITCH
OUTPUT
t
(WR)
ON
V
O
RS
SWITCH
OUTPUT
0.2V
WR
O
D
(D)
V
B
O
0V
RS
GND
V-
35pF
1kΩ
Device must be reset prior to applying WR pulse.
LOGIC
INPUT
WR
-15V
FIGURE 6A. WRITE t
SWITCHING TIME WAVEFORMS
FIGURE 6B. WRITE t
SWITCHING TIME TEST CIRCUIT
† Similar connections for DG526, DG527
ON
ON
+15V
+2.4V
V+
OR
t < 20ns
r
S
1
+5V
EN
t < 20ns
f
DG528
DG529†
S
1B
3V
A , A , (A
0
1
2)
50%
1.5V
0V
RS
REMAINING
SWITCHES
t
(RS)
OFF
SWITCH
OUTPUT
D
(D)
RS
V
B
O
SWITCH
OUTPUT
GND
WR
V-
0.8V
O
V
1kΩ
35pF
RS
O
-15V
FIGURE 7A. RESET t
SWITCHING TIME WAVEFORMS
FIGURE 7B. RESET t
SWITCHING TIME TEST CIRCUIT
OFF
OFF
† Similar connections for DG526, DG527
12-10
DG526, DG527, DG528, DG529
Test Circuits and Waveforms (Continued)
+15V
V+
A , A , (A
+2.4V
RS
D
0
1
2)
3V
0
DG528
DG529†
EN
Sx
V
O
∆V
O
V
O
C
= 1000pF
L
GND
WR
V-
EN
∆V is the measured voltage error due to charge injection.
-15V
O
The error voltage in Coulombs is Q = C x ∆V .
L
O
FIGURE 8A. CHARGE INJECTION WAVEFORMS
FIGURE 8B. CHARGE INJECTION TEST CIRCUIT
† Similar connections for DG526, DG527
Typical Performance Curves
550
400
(D)
I
V
= -200µA
V+ = +15V V- = -15V
360
O
500
450
400
350
300
250
200
150
100
50
+10V SIGNALS
+10V SIGNALS
= +5V
V
I
= 2.4V
EN
EN
= -200µA
O
320
280
240
200
160
120
80
(C)
(B)
(A)
(A) V+ = +15V, V- = -15V
(B) V+ = +12V, V- = -12V
(C) V+ = +10V, V- = -10V
(D) V+ = +7.5V, V- = -7.5V
40
0
-55
0
-15 -13 -11 -9 -7 -5 -3 -1 0 +1 +3 +5 +7 +9 +11+13 +15
-25
0
25
45
70
100
125
o
ANALOG SIGNAL VOLTAGE (V)
TEMPERATURE ( C)
FIGURE 9. r
vs ANALOG SIGNAL VOLTAGE vs SUPPLY
VOLTAGE
FIGURE 10. TYPICAL r VARIATION WITH TEMPERATURE
DS(ON)
DS(ON)
12-11
DG526, DG527, DG528, DG529
Truth Tables
DG526
EN WR RS ON SWITCH
DG527
A EN WR RS ON SWITCH
0
A
A
A
A
A
A
3
2
1
0
2
1
Latching
Reset
X
X
X
X
X
1
Maintains
Previous
Switch State
Latching
Reset
X
X
X
X
1
Maintains
Previous
Switch State
X
X
X
X
X
X
0
None
X
X
X
X
X
0
None
(Latches
Cleared)
(Latches
Cleared)
Trans-
parent
Operation
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
None
1
Trans-
parent
Operation
X
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
None
0
0
1
2
3
4
5
6
7
8
0
2
1
1
3
0
1
4
1
0
5
0
0
6
1
1
7
0
1
1
8
0
9
Logic “1” = V , V
≥ 2.4V
AH ENH
0
10
11
12
13
14
15
16
1
1
0
0
1
1
Logic “0” = V , V
≤ 0.8V
AL ENL
DG528
EN WR RS
DG529
A
A
A
0
ON SWITCH
A
A
EN
WR
RS
ON SWITCH
2
1
1
0
X
X
X
X
1
Maintains Previous
Switch Condition
X
X
X
1
Maintains Previous Switch
Condition
X
X
0
0
0
0
1
1
1
1
X
X
0
0
1
1
0
0
1
1
X
X
0
1
0
1
0
1
0
1
X
0
1
1
1
1
1
1
1
1
X
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
None (Latches Cleared)
X
X
0
0
1
1
X
X
0
1
0
1
X
0
1
1
1
1
X
0
0
0
0
0
0
1
1
1
1
1
None (Latches Cleared)
None
None
1
2
3
4
5
6
7
8
1
2
3
4
Logic “1”: V ≥ 2.4V
AH
Logic “0”: V ≤ 0.8V
AL
12-12
DG526, DG527, DG528, DG529
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
3810µm x 2769µm
Type: PSG Over Nitride
PSG Thickness: 7kÅ ±1.4kÅ
Nitride Thickness: 8kÅ ±1.2kÅ
METALLIZATION:
Type: Al
Thickness: 10kÅ ±1kÅ
WORST CASE CURRENT DENSITY:
4
2
9.1 x 10 A/cm
Metallization Mask Layout
DG526
PIN 11
PIN 10 PIN 9
PIN 8 PIN 7
PIN 6 PIN 5
PIN 4
S
S
S
S
S
S
S
S
16
9
10
11
12
13
14
15
PIN 12
GND
PIN 3
RS
PIN 13
WR
PIN 14
PIN 2
NC
A
3
PIN 15
A
2
PIN 1
V+
PIN 16
A
1
PIN 28
D
PIN 17
A
0
PIN 27
V-
PIN18
EN
PIN 19 PIN 20 PIN 21 PIN 22 PIN 23 PIN 24 PIN 25
PIN 26
S
S
S
S
S
S
S
S
8
1
2
3
4
5
6
7
12-13
DG526, DG527, DG528, DG529
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
3810µm x 2769µm
Type: PSG Over Nitride
PSG Thickness: 7kÅ ±1.4kÅ
Nitride Thickness: 8kÅ ±1.2kÅ
METALLIZATION:
Type: Al
Thickness: 10kÅ ±1kÅ
WORST CASE CURRENT DENSITY:
4
2
9.1 x 10 A/cm
Metallization Mask Layout
DG527
PIN 11 PIN 10 PIN 9
PIN 8 PIN 7
PIN 6
PIN 5
PIN 4
S
S
S
S
S
S
S
S
8B
1B
2B
3B
4B
5B
6B
7B
PIN 12
GND
PIN 3
RS
PIN 13
WR
PIN 14
NC
PIN 2
D
B
PIN 15
A
2
PIN 1
V+
PIN 16
A
1
PIN 28
PIN 17
D
A
A
0
PIN 27
V-
PIN18
EN
PIN 19 PIN 20 PIN 21 PIN 22 PIN 23 PIN 24 PIN 25
PIN 26
S
S
S
S
S
S
S
S
8A
1A
2A
3A
4A
5A
6A
7A
12-14
DG526, DG527, DG528, DG529
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
3100µm x 2083µm
Type: PSG Over Nitride
PSG Thickness: 7kÅ ±1.4kÅ
Nitride Thickness: 8kÅ ±1.2kÅ
METALLIZATION:
Type: Al
Thickness: 10kÅ ±1kÅ
WORST CASE CURRENT DENSITY:
4
2
9.1 x 10 A/cm
Metallization Mask Layout
DG528
PIN 15
GND
PIN 14
V+
PIN 13
PIN 12
PIN 11
S
7
S
S
5
6
PIN 16
A
2
PIN 17
A
1
PIN 18
RS
PIN 10
S
8
PIN 9
D
PIN 1
WR
PIN 2
A
0
PIN 8
S
4
PIN 3
EN
PIN 4
V-
PIN 5
PIN 6
PIN 7
S
3
S
S
1
2
12-15
DG526, DG527, DG528, DG529
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
3100µm x 2083µm
Type: PSG Over Nitride
PSG Thickness: 7kÅ ±1.4kÅ
Nitride Thickness: 8kÅ ±1.2kÅ
METALLIZATION:
Type: Al
Thickness: 10kÅ ±1kÅ
WORST CASE CURRENT DENSITY:
4
2
9.1 x 10 A/cm
Metallization Mask Layout
DG529
PIN 15
V+
PIN 14
PIN 13
PIN 12
PIN 11
S
4B
S
S
S
1G
2B
3B
PIN 16
GND
PIN 17
A
1
PIN 10
PIN 18
RS
S
8A
PIN 9
D
A
PIN 1
WR
PIN 2
A
PIN 8
0
S
4A
PIN 3
EN
PIN 4
V-
PIN 5
PIN 6
PIN 7
S
3A
S
S
1A
2A
12-16
相关型号：
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