DG508ACJZ [INTERSIL]
CMOS Analog Multiplexers; CMOS模拟多路复用器
| 型号： | DG508ACJZ |
| 厂家： | 
Intersil |
| 描述： | CMOS Analog Multiplexers |
| 文件： | 总19页 (文件大小：460K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DG506A, DG507A, DG508A, DG509A
Data Sheet
November 1999
File Number 3137.3
CMOS Analog Multiplexers
Features
The DG506A, DG507A, DG508A and DG509A are CMOS
Monolithic 16-Channel/Dual 8-Channel and 8-Channel/Dual
4-Channel Analog Multiplexers, which can also be used as
demultiplexers. An enable input is provided. When the
enable input is high, a channel is selected by the address
inputs, and when low, all channels are off.
• Low Power Consumption
• TTL and CMOS-Compatible Address and Enable Inputs
• 44V Maximum Power Supply Rating
• High Latch-Up Immunity
• Break-Before-Make Switching
• Alternate Source
A channel in the ON state conducts current equally well in
both directions. In the OFF state each channel blocks
voltages up to the supply rails. The address inputs and the
enable input are TTL and CMOS compatible over the full
specified operating temperature range.
Applications
• Data Acquisition Systems
• Communication Systems
• Signal Multiplexing/Demultiplexing
• Audio Signal Multiplexing
The DG506A, DG507A, DG508A and DG509A are pinout
compatible with the industry standard devices.
Ordering Information
TEMP.
PKG.
NO.
TEMP.
PKG.
NO.
o
o
PART NUMBER RANGE ( C)
PACKAGE
PART NUMBER RANGE ( C)
PACKAGE
DG508AAK
DG508ABK
DG508ACJ
DG509ACJ
DG509ACY
-55 to 125 16 Ld CERDIP
F16.3
DG506AAK
DG506ACJ
DG506ACY
DG507ABK
DG507ACJ
DG507ACY
-55 to 125 28 Ld CERDIP
F28.6
-25 to 85
0 to 70
0 to 70
0 to 70
16 Ld CERDIP
16 Ld PDIP
16 Ld PDIP
16 Ld SOIC
F16.3
E16.3
E16.3
M16.3
0 to 70
0 to 70
-25 to 85
0 to 70
0 to 70
28 Ld PDIP
28 Ld SOIC
28 Ld CERDIP
28 Ld PDIP
28 Ld SOIC
E28.6
M28.3
F28.6
E28.6
M28.3
Pinouts
DG506A (PDIP, CERDIP, SOIC)
DG507A (PDIP, CERDIP, SOIC)
DG508A (PDIP, CERDIP)
DG509A (PDIP, SOIC)
TOP VIEW
TOP VIEW
TOP VIEW
TOP VIEW
V+
D
A
V+
NC
NC
1
2
28 D
1
2
28
27
26
25
A
1
2
3
4
5
6
7
8
16
15
A
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A
A
1
1
0
0
D
B
V-
S
27
26
25
24
23
V-
S
A
GND
V+
EN
V-
EN
V-
2
NC
3
3
8A
8
14 GND
13 V+
S
S
S
4
S
S
S
4
8B
7B
6B
5B
4B
3B
2B
1B
7A
6A
5A
4A
3A
2A
1A
16
15
14
13
12
11
10
7
6
5
4
3
2
1
S
1
S
1A
S
1B
S
S
S
S
S
S
S
24 S
23 S
22 S
21 S
5
5
S
S
S
S
S
S
S
S
2
S
S
12
11
10
9
2A
5
2B
6
6
S
S
3
S
S
3A
6
3B
7
22 S
21
7
S
S
4
S
S
4A
4B
7
8
8
S
D
A
D
B
D
S
8
9
20 S
19 S
9
20
19
18
17
16
15
S
S
10
11
10
11
12
13
14
18 EN
S
EN
9
A
0
GND 12
17 A
0
GND
NC
A
1
13
16
15
A
NC
1
2
NC
A
2
A
A
14
3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
1
DG506A, DG507A, DG508A, DG509A
Truth Tables
DG506A
DG507A
A
A
A
A
EN
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ON SWITCH
A
A
A
0
EN
0
ON SWITCH
3
2
1
0
2
1
X
X
X
X
None
1
X
X
X
None
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
2
3
4
5
6
7
8
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
Logic “0” = V , V
AL ENL
≤ 0.8V, Logic “1” = V , V
AH ENH
≥ 2.4V.
10
11
12
13
14
15
16
DG509A
A
A
EN
0
ON SWITCH
None
1
0
X
X
0
0
1
1
0
1
0
1
1
1A, 1B
1
2A, 2B
1
3A, 3B
1
4A, 4B
Logic “0” = V , V
AL
≤ 0.8V, Logic “1” = V , V
≥ 2.4V.
ENL
AH
ENH
A , A , EN
0
1
Logic “1” = V ≥ 2.4V, Logic “0” = V ≤ 0.8V.
AH AL
DG508A
A
A
A
0
EN
0
ON SWITCH
2
1
X
X
X
None
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
2
3
4
5
6
7
8
1
1
1
1
1
1
1
A , A , A , EN
0
1
2
Logic “1” = V ≥ 2.4V, Logic “0” = V ≤ 0.8V
AH AL
2
DG506A, DG507A, DG508A, DG509A
Functional Diagrams
DG506A
DG507A
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
1
1A
2A
3A
4A
5A
6A
7A
8A
1B
2B
3B
4B
5B
6B
7B
8B
S
2
S
3
S
S
S
S
S
S
4
D
A
5
6
7
8
9
D
S
10
S
11
12
13
14
15
16
S
S
S
S
S
D
B
ADDRESS DECODER
1 OF 8
ENABLE
1 OF 2
ADDRESS DECODER
1 OF 16
ENABLE
1 OF 4
A
A
A
2
EN (ENABLE INPUT)
0
1
A
A
A
A
3
EN
0
1
2
4 Line Binary Address Inputs
(0 0 0 1) and EN = 5V
3 Line Binary Address Inputs
(0 0 0) and EN = 5V
Above example shows channel 2 turned ON.
Above example shows channels 1 and 1 turned ON.
A
B
DG508A
DG509A
S
S
S
S
S
1
1A
2A
3A
4A
S
2
S
3
D
A
S
S
S
S
S
4
D
5
6
7
8
S
S
S
S
1B
2B
3B
4B
ADDRESS DECODER
1 OF 8
D
B
A
A
A
2
EN (ENABLE INPUT)
0
1
3 Line Binary Address Inputs
(1 0 1) and EN = 1
2 Line Binary Address Inputs
(0 0) and EN = 1
Above example shows channel 6 turned ON.
Above example shows channels 1 and 1 turned ON.
A B
Schematic Diagram
V+
S
D
X
V+
DECODER
LOGIC TRIP
POINT REF
+
-
A
X
GND
X
LOGIC A
X
INPUT OR EN
V-
LOGIC INTERFACE
AND LEVEL SHIFTER
TYPICAL
SWITCH
3
DG506A, DG507A, DG508A, DG509A
Absolute Maximum Ratings
Thermal Information
o
o
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44V
V- to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V
Thermal Resistance (Typical, Note 2)
θ
( C/W)
θ
( C/W)
JA
JC
16 Ld CERDIP Package. . . . . . . . . . . .
28 Ld CERDIP Package. . . . . . . . . . . .
16 Ld PDIP Package . . . . . . . . . . . . . .
28 Ld PDIP Package . . . . . . . . . . . . . .
16 Ld SOIC Package . . . . . . . . . . . . . .
28 Ld SOIC Package . . . . . . . . . . . . . .
Maximum Junction Temperature
75
55
90
55
100
70
20
18
N/A
N/A
N/A
N/A
Digital Inputs, V , V (Note 1). . . . . . . . . . . . . .(V- -2V) To (V+ +2V)
S
D
Continuous Current, (Any Terminal Except S or D) . . . . . . . . . 30mA
Continuous Current, (S or D) . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle Max) . . . . . 40mA
Operating Conditions
o
CERDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 C
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 C
Temperature Range
“A” Suffix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
“B” Suffix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25 C to 85 C
“C” Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 70 C
o
o
o
Maximum Storage Temperature
o
o
o
o
“A” and “B” Suffix . . . . . . . . . . . . . . . . . . . . . . . . . -65 C to 150 C
“C” Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 C to 125 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C
o
o
o
o
o
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Signals on S , D , E , or A exceeding V+ or V- are clamped by internal diodes. Limit diode current to maximum current ratings.
X
X
N
X
2. θ is measured with the component mounted on an evaluation PC board in free air.
JA
o
Electrical Specifications T = 25 C, V+ = +15V, V- = -15V, GND = 0V, V = 2.4V, Unless Otherwise Specified
A
EN
“A” SUFFIX
“B” AND “C” SUFFIX
(NOTE 4) (NOTE 3) (NOTE 4) (NOTE 4) (NOTE 3) (NOTE 4)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
DYNAMIC CHARACTERISTICS
Switching Time of
Multiplexer, t
See Figure 1
See Figure 3
See Figure 2
See Figure 2
-
-
-
-
-
0.6
0.2
1
1
-
-
-
-
-
-
0.6
0.2
1
-
-
-
-
-
µs
µs
µs
µs
dB
TRANSITION
Break-Before-Make
Interval, t
OPEN
Enable Turn-ON Time,
1.5
1.0
-
t
ON(EN)
Enable Turn-OFF Time,
0.4
68
0.4
68
t
OFF(EN)
OFF Isolation, OIRR
V
V
= 0V, R = 1kΩ, C = 15pF,
EN L L
= 7V
, f = 500kHz (Note 5)
S
RMS
Source OFF Capacitance,
V
V
= 0V, V
= 0V, f = 140kHz
S
EN
C
S(OFF)
DG506A, DG507A
-
-
6
5
-
-
-
-
6
5
-
-
pF
pF
DG508A, DG509A
Drain OFF Capacitance,
= 0V, V
= 0V, f = 140kHz
D
EN
C
D(OFF)
DG506A
-
-
-
-
45
23
25
12
-
-
-
-
-
-
-
-
45
23
25
12
-
-
-
-
pF
pF
pF
pF
DG507A
DG508A
DG509A
Charge Injection, Q
DG506A, DG507A
See Figure 4
-
-
6
4
-
-
-
-
6
4
-
-
pC
pC
DG508A, DG509A
DIGITAL INPUT CHARACTERISTICS
Address Input Current,
Input Voltage High, I
V
= 2.4V
= 15V
-10
-
-0.002
0.006
-0.002
-0.002
-
10
-
-10
-
-0.002
0.006
-
10
-
µA
µA
µA
µA
A
AH
V
A
Address Input Current
Input Voltage Low, I
AL
V
V
= 2.4V
= 0V
V
= 0V
-10
-10
-10
-10
-0.002
-0.0002
EN
EN
A
-
-
4
DG506A, DG507A, DG508A, DG509A
o
Electrical Specifications T = 25 C, V+ = +15V, V- = -15V, GND = 0V, V = 2.4V, Unless Otherwise Specified (Continued)
A
EN
“A” SUFFIX
“B” AND “C” SUFFIX
(NOTE 4) (NOTE 3) (NOTE 4) (NOTE 4) (NOTE 3) (NOTE 4)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range,
(Note 7)
-15
-
+15
-15
-
+15
V
V
ANALOG
Drain-Source ON
Resistance, r
SequenceEach
Switch ON
I
I
= -200µA, V = +10V
-
-
270
230
400
400
-
-
270
230
450
450
Ω
Ω
S
D
DS(ON)
= -200µA, V = -10V
S
D
V
= 0.8V
= 2.4V
AL
V
AH
r
Matching
-10V ≤ V ≤ +10V
-
6
-
-
6
-
%
DS(ON)
S
Between Channels
r
– r
DS(ON)MAX
DS(ON)MIN
∆r
= -----------------------------------------------------------------------
DS(ON)
r
DS(ON)AVG
Source OFF Leakage
Current, I
S(OFF)
V
= 0V
= 0V
V
V
= +10V, V = -10V
-1
-1
0.002
1
1
-5
-5
0.002
5
5
nA
nA
EN
EN
S
S
D
= -10V, V = +10V
-0.005
-0.005
D
Drain OFF Leakage
Current, I
V
D(OFF)
DG506A
V
V
V
V
V
V
V
V
= -10V, V = +10V
-10
-10
-5
0.02
-0.03
10
10
5
-20
-20
-10
-10
-
0.02
-0.03
20
20
10
10
20
-
nA
nA
nA
nA
nA
nA
nA
nA
S
S
S
S
S
S
S
S
D
= +10V, V = -10V
D
DG507A
DG508A
DG509A
= -10V, V = +10V
0.007
-0.015
0.01
0.007
-0.015
0.01
D
= +10V, V = -10V
-5
5
D
= -10V, V = +10V
-
10
-
D
= +10V, V = -10V
-10
-
-0.015
0.005
-0.008
-20
-
-0.015
0.005
-0.008
D
= -10V, V = +10V
10
-
20
-
D
= +10V, V = -10V
-10
-20
D
Drain ON Leakage Current, (Note 6)
I
SequenceEach
Switch ON
D(ON)
DG506A
V
V
V
V
V
V
V
V
= V
= V
= V
= V
= V
= V
= V
= V
= +10V
= -10V
= +10V
= -10V
= +10V
= -10V
= +10V
= -10V
-10
-10
-5
0.03
-0.06
0.015
-0.03
0.015
-0.03
0.007
-0.015
10
10
5
-20
-20
-10
-10
-
0.03
-0.06
0.015
-0.03
0.015
-0.03
0.007
-0.015
20
20
10
10
20
-
nA
nA
nA
nA
nA
nA
nA
nA
D
D
D
D
D
D
D
D
S(ALL)
S(ALL)
S(ALL)
S(ALL)
S(ALL)
S(ALL)
S(ALL)
S(ALL)
V
= 0.8V
= 2.4V
AL
V
AH
DG507A
DG508A
DG509A
-5
5
-
10
-
-10
-
-20
-
10
-
20
-
-10
-20
POWER SUPPLY CHARACTERISTICS
Positive Supply Current,
I+
V
= 5.0V, V = 0V
-
1.3
-0.7
1.3
2.4
-
-
1.3
-0.7
1.3
2.4
-
mA
mA
mA
mA
EN
(Enabled)
A
Negative Supply Current,
I-
-1.5
-
-1.5
-
Positive Supply Current,
I+ Standby
V
= 0V, V = 0V
2.4
-
2.4
-
EN
A
(Standby)
Negative Supply Current,
I- Standby
-1.5
-0.7
-1.5
-0.7
5
DG506A, DG507A, DG508A, DG509A
Electrical Specifications T = Over Operating Temperature Range, V+ = +15V, V- = -15V, GND = 0V, V = 2.4V,
A
EN
Unless Otherwise Specified
“A” SUFFIX
“B” AND “C” SUFFIX
(NOTE 3)
(NOTE 3)
PARAMETER
DIGITAL INPUT CHARACTERISTICS
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Address Input Current, Input
Voltage High, I
V
= 2.4V
= 15V
-30
-
-
-
-
-
-
30
-
-
-
-
-
-
-
-
-
-
-
-
-
µA
µA
µA
µA
A
AH
V
A
Address Input Current Input
Voltage Low, I
V
= 2.4V
= 0V
V
= 0V
-30
-30
EN
EN
A
AL
V
-
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range,
(Note 7)
-15
-
+15
-
-
-
V
V
ANALOG
Drain-Source ON
Resistance, r
Sequence Each
Switch ON
I
I
= -200µA, V = +10V
-
-
-
-
500
500
-
-
-
-
-
-
Ω
Ω
S
S
D
DS(ON)
= -200µA, V = -10V
D
V
= 0.8V
= 2.4V
AL
V
AH
Source OFF Leakage
Current, I
V
= 0V
V
V
= +10V, V = -10V
-
-
-
50
-
-
-
-
-
-
-
nA
nA
EN
EN
S
S
D
S(OFF)
= -10V, V = +10V
-50
D
Drain OFF Leakage Current,
V
= 0V
I
D(OFF)
DG506A
V
V
V
V
V
V
V
V
= -10V, V = +10V
-
-300
-
-
-
-
-
-
-
-
-
300
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
nA
nA
nA
nA
nA
nA
nA
nA
S
S
S
S
S
S
S
S
D
= +10V, V = -10V
-
200
-
D
DG507A
DG508A
DG509A
= -10V, V = +10V
D
= +10V, V = -10V
-200
-
D
= -10V, V = +10V
200
-
D
= +10V, V = -10V
-200
-
D
= -10V, V = +10V
100
-
D
= +10V, V = -10V
-100
D
Drain ON Leakage Current, (Note 6)
I
Sequence Each
Switch ON
D(ON)
DG506A
V
V
V
V
V
V
V
V
= V
= V
= V
= V
= V
= V
= V
= V
= +10V
= -10V
= +10V
= -10V
= +10V
= -10V
= +10V
= -10V
-
-300
-
-
-
-
-
-
-
-
-
300
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
nA
nA
nA
nA
nA
nA
nA
nA
D
D
D
D
D
D
D
D
S(ALL)
S(ALL)
S(ALL)
S(ALL)
S(ALL)
S(ALL)
S(ALL)
S(ALL)
V
= 0.8V
= 2.4V
AL
-
200
-
V
AH
DG507A
DG508A
DG509A
-200
-
200
-
-200
-
100
-
-100
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
Negative Supply Current, I-
Positive Standby Supply Current, I+
Negative Standby Supply Current, I-
NOTES:
V
V
= 5.0V, V = 0V
-3.2
-3.2
-3.2
-3.2
-
-
-
-
4.5
4.5
4.5
4.5
-
-
-
-
-
-
-
-
-
-
-
-
mA
mA
mA
mA
EN
EN
A
= 0V, V = 0V
A
3. Typical values are for design aid only, not guaranteed and not subject to production testing.
4. The algebraic convention whereby the most negative value is a minimum, and the most positive value is a maximum, is used in this data sheet.
5. Off isolation = 20Log |V |/|V |, where V = input to Off switch, and V = output due to V .
S
D
S
D
S
6. I
is leakage from driver into “ON” switch.
D(ON)
7. Parameter not tested. Parameter guaranteed by design or characterization.
6
DG506A, DG507A, DG508A, DG509A
Test Circuits and Waveforms
+15V
V+
+2.4V
+15V
V+
+2.4V
±10V
EN
S
1B
±10V
EN
S
1
DG507A
(NOTE)
DG506A
(NOTE)
S
THRU S
8A,
A
3
1A
S
THRU S
2
15
D
A
7B
S
, AND S
2B
A
2
A
2
S
+10V
S
8B
+10V
16
D
A
1
A
1
SWITCH
OUTPUT
SWITCH
OUTPUT
A
0
D
A
0
V
O
B
V
LOGIC
INPUT
LOGIC
INPUT
O
GND
V-
GND
V-
50Ω
1MΩ
35pF
50Ω
1MΩ
35pF
-15V
-15V
NOTE: Similar connections for DG508A.
NOTE: Similar connections for DG509A.
FIGURE 1B. DG507A TEST CIRCUIT
FIGURE 1A. DG506A TEST CIRCUIT
3V
t < 20ns
r
t < 20ns
f
50%
0
LOGIC INPUT
S
ON
1
V
S1
S1
0.8V
SWITCH
OUTPUT
0
V
O
0.8V
V
S8
S8
S
ON
8
TRANSITION
TIME
TRANSITION
TIME
FIGURE 1C. MEASUREMENT POINTS
FIGURE 1. SWITCHING TIME
+15V
1
+15V
V+
S
V+
-5V
-5V
EN
EN
S
1B
DG506A
(NOTE)
DG507A
(NOTE)
A
A
3
S
THRU S
S THRU S
1A 8A
,
,
2
16
D
A
8B
A
0
S
THRU S
2
2B
A
A
A
1
1
SWITCH
OUTPUT
SWITCH
OUTPUT
A
D
D
B
V
V
0
2
O
O
50Ω
EN
EN
GND
V-
-15V
GND
V-
1kΩ
35pF
50Ω
1kΩ
35pF
-15V
NOTE: Similar connections for DG508A.
NOTE: Similar connections for DG509A.
FIGURE 2B. DG507A TEST CIRCUIT
FIGURE 2A. DG506A TEST CIRCUIT
7
DG506A, DG507A, DG508A, DG509A
Test Circuits and Waveforms (Continued)
t < 20ns
f
50%
r
3V
0V
t < 20ns
EN
50%
t
ON (EN)
t
OFF (EN)
0V
0.1V
O
SWITCH
OUTPUT
V
O
0.9V
O
V
O
FIGURE 2C. MEASUREMENT POINTS
FIGURE 2. ENABLE TIMES
+15V
+2.4V
V+
+5V (V )
EN ALL S AND D
t < 20ns
f
S
A
r
3V
0V
t < 20ns
LOGIC
INPUT
DG506A
DG507A
(NOTE)
A
A
A
A
0
1
V
S
2
3
SWITCH
OUTPUT
SWITCH
OUTPUT
50%
50%
V
D
V
O
B
O
LOGIC
INPUT
GND
V-
0V
50Ω
1kΩ
35pF
t
OPEN
-15V
NOTE: Similar connections for DG508A, DG509A.
FIGURE 3B. MEASUREMENT POINTS
FIGURE 3A. TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE INTERVAL
+15V
V+
+15V
V+
EN
EN
DG506A
(NOTE)
DG507A
(NOTE)
A
A
S
1
3
A
A
A
S
, S
2
2
1
0
1A 1B
A
A
1
D
D
OR D
B
V
O
V
0
A
O
LOGIC
INPUT
LOGIC
INPUT
GND
V-
GND
V-
1000pF
1000pF
-15V
-15V
NOTE: Similar connections for DG508A.
FIGURE 4A. DG506A TEST CIRCUIT
NOTE: Similar connections for DG509A.
FIGURE 4B. DG507A TEST CIRCUIT
8
DG506A, DG507A, DG508A, DG509A
Test Circuits and Waveforms (Continued)
3V
0
EN
∆V
O
V
O
∆V is the measured voltage error due to charge injection.
O
The charge transfer error in Coulombs is Q = C x ∆V .
L
O
FIGURE 4C. CHARGE INJECTION WAVEFORMS
FIGURE 4. CHARGE INJECTION
Typical Performance Curves
400
550
V+ = +15V, V- = -15V
V+ = +15V V- = -15V
500
V+ = +10V, V- = -10V
+10V SIGNALS
V
I
= 2.4V
EN
= -200µA
V+ = +12V, V- = -12V
V+ = +7.5V, V- = -7.5V
450
400
350
300
250
200
150
100
50
O
300
200
100
0
+10V SIGNALS
0
-15
-10
-5
0
5
10
15
-55
-25
0
20
45
70
100
125
o
ANALOG SIGNAL VOLTAGE (V)
TEMPERATURE ( C)
FIGURE 5. r
vs ANALOG SIGNAL VOLTAGE vs
FIGURE 6. TYPICAL r
VARIATION WITH TEMPERATURE
DS(ON)
DS(ON)
SUPPLY VOLTAGE
9
DG506A
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
3810µm x 2770µm
Type: PSG/Nitride
Thickness: PSG: 7kÅ ±1.4kÅ
Nitride: 8kÅ ±1.2kÅ
METALLIZATION:
Type: Al
Thickness: 10kÅ ±1kÅ
WORST CASE CURRENT DENSITY:
4
2
9.1 x 10 A/cm
Metallization Mask Layout
DG506A
V+
NC
NC
D
V-
S
S
S
S
S
S
S
16
15
8
7
6
5
4
S
14
S
S
13
12
S
S
S
S
11
10
3
2
S
S
9
1
GND
NC
A
A
A
A
0
EN
3
2
1
10
DG507A
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
3810µm x 2770µm
Type: PSG/Nitride
Thickness: PSG: 7kÅ ±1.4kÅ
Nitride: 8kÅ ±1.2kÅ
METALLIZATION:
Type: Al
Thickness: 10kÅ ±1kÅ
WORST CASE CURRENT DENSITY:
4
2
9.1 x 10 A/cm
Metallization Mask Layout
DG507A
V+
NC
D
D
V-
B
A
S
S
S
S
S
S
S
8B
7B
8A
7A
6A
5A
4A
S
6B
S
S
5B
4B
S
S
S
S
S
3B
2B
1B
3A
2A
S
1A
GND
NC
NC
A
A
A
0
EN
2
1
11
DG508A
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
3100µm x 2083µm
Type: PSG/Nitride
Thickness: PSG: 7kÅ ±1.4kÅww
Nitride: 8kÅ ±1.2kÅ
METALLIZATION:
Type: Al
Thickness: 10kÅ ±1kÅ
WORST CASE CURRENT DENSITY:
4
2
9.1 x 10 A/cm
Metallization Mask Layout
DG508A
EN
A
A
A
2
0
1
GND
V+
V-
S
1
S
5
S
2
S
6
S
7
S
3
S
D
S
8
4
12
DG509A
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
3100µm x 2083µm
Type: PSG/Nitride
Thickness: PSG: 7kÅ ±1.4kÅ
Nitride: 8kÅ ±1.2kÅ
METALLIZATION:
Type: Al
Thickness: 10kÅ ±1kÅ
WORST CASE CURRENT DENSITY:
4
2
9.1 x 10 A/cm
Metallization Mask Layout
DG509A
EN
A
A
GND
0
1
V+
V-
S
1B
S
S
S
1A
2B
3B
S
2A
S
S
4B
3A
S
D
D
B
4A
A
13
DG506A, DG507A, DG508A, DG509A
Dual-In-Line Plastic Packages (PDIP)
E16.3 (JEDEC MS-001-BB ISSUE D)
N
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
INCHES
MILLIMETERS
1 2
3
N/2
SYMBOL
MIN
MAX
0.210
-
MIN
-
MAX
5.33
-
NOTES
-B-
A
A1
A2
B
-
4
-A-
0.015
0.115
0.014
0.045
0.008
0.735
0.005
0.300
0.240
0.39
2.93
0.356
1.15
0.204
18.66
0.13
7.62
6.10
4
D
E
BASE
PLANE
0.195
0.022
0.070
0.014
0.775
-
4.95
0.558
1.77
0.355
19.68
-
-
A2
A
-C-
-
SEATING
PLANE
B1
C
8, 10
L
C
L
-
D1
B1
eA
A1
A
D1
e
D
5
eC
C
B
D1
E
5
eB
0.010 (0.25) M
C
B S
0.325
0.280
8.25
7.11
6
NOTES:
E1
e
5
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
0.100 BSC
0.300 BSC
2.54 BSC
7.62 BSC
-
e
A
6
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
e
-
0.430
0.150
-
10.92
3.81
7
B
L
0.115
2.93
4
9
4. Dimensions A, A1 and L are measured with the package seated in JE-
N
16
16
DEC seating plane gauge GS-3.
Rev. 0 12/93
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
e
6. E and
are measured with the leads constrained to be perpendic-
A
-C-
ular to datum
.
7. e and e are measured at the lead tips with the leads unconstrained.
B
C
e
must be zero or greater.
C
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
14
DG506A, DG507A, DG508A, DG509A
Dual-In-Line Plastic Packages (PDIP)
E28.6 (JEDEC MS-001-BF ISSUE D)
28 LEAD NARROW BODY DUAL-IN-LINE PLASTIC
PACKAGE
N
E1
INDEX
AREA
1 2
3
N/2
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
0.250
-
MIN
-
MAX
6.35
-
NOTES
-A-
A
A1
A2
B
-
4
D
E
0.015
0.125
0.014
0.030
0.008
1.380
0.005
0.600
0.485
0.39
3.18
0.356
0.77
0.204
4
BASE
PLANE
A2
0.195
0.022
0.070
0.015
1.565
-
4.95
0.558
1.77
0.381
39.7
-
-
A
-C-
SEATING
PLANE
-
L
C
L
B1
C
8
D1
B1
eA
A1
A
D1
-
e
eC
C
B
D
35.1
5
eB
0.010 (0.25) M
C
B S
D1
E
0.13
15.24
12.32
5
0.625
0.580
15.87
14.73
6
NOTES:
E1
e
5
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
0.100 BSC
0.600 BSC
2.54 BSC
15.24 BSC
-
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
e
e
6
A
B
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
-
0.700
0.200
-
17.78
5.08
7
L
0.115
2.93
4
9
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
N
28
28
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
Rev. 0 12/93
e
6. E and
are measured with the leads constrained to be perpendic-
A
-C-
ular to datum
.
7. e and e are measured at the lead tips with the leads unconstrained.
B
C
e
must be zero or greater.
C
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
15
DG506A, DG507A, DG508A, DG509A
Small Outline Plastic Packages (SOIC)
N
M16.3 (JEDEC MS-013-AA ISSUE C)
INDEX
AREA
0.25(0.010)
M
B M
H
16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
E
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.33
0.23
MAX
2.65
0.30
0.51
0.32
10.50
7.60
NOTES
A
A1
B
C
D
E
e
0.0926
0.0040
0.013
0.1043
0.0118
0.0200
0.0125
-
1
2
3
L
-
9
SEATING PLANE
A
0.0091
0.3977
0.2914
-
-A-
o
h x 45
D
0.4133 10.10
3
0.2992
7.40
4
-C-
α
0.050 BSC
1.27 BSC
-
e
A1
H
h
0.394
0.010
0.016
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
C
B
0.10(0.004)
5
0.25(0.010) M
C
A M B S
L
6
N
α
16
16
7
NOTES:
o
o
o
o
0
8
0
8
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm (0.024
inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
16
DG506A, DG507A, DG508A, DG509A
Small Outline Plastic Packages (SOIC)
M28.3 (JEDEC MS-013-AE ISSUE C)
N
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.33
0.23
MAX
2.65
0.30
0.51
0.32
18.10
7.60
NOTES
-B-
A
A1
B
C
D
E
e
0.0926
0.0040
0.013
0.1043
0.0118
0.0200
0.0125
-
-
1
2
3
L
9
SEATING PLANE
A
0.0091
0.6969
0.2914
-
-A-
0.7125 17.70
3
o
h x 45
D
0.2992
7.40
4
0.05 BSC
1.27 BSC
-
-C-
α
H
h
0.394
0.01
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
e
A1
C
5
B
0.10(0.004)
L
0.016
6
0.25(0.010) M
C
A M B S
N
α
28
28
7
o
o
o
o
0
8
0
8
-
NOTES:
Rev. 0 12/93
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
17
DG506A, DG507A, DG508A, DG509A
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 LEAD FINISH
F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A)
16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
-D-
E
-A-
INCHES
MIN
MILLIMETERS
BASE
(c)
METAL
SYMBOL
MAX
0.200
0.026
0.023
0.065
0.045
0.018
0.015
0.840
0.310
MIN
-
MAX
5.08
0.66
0.58
1.65
1.14
0.46
0.38
21.34
7.87
NOTES
b1
A
b
-
-
M
M
(b)
0.014
0.014
0.045
0.023
0.008
0.008
-
0.36
0.36
1.14
0.58
0.20
0.20
-
2
-B-
b1
b2
b3
c
3
SECTION A-A
bbb
C A - B
D
D
S
S
S
-
4
BASE
PLANE
Q
2
A
-C-
SEATING
PLANE
c1
D
3
L
α
5
S1
b2
eA
A A
e
E
0.220
5.59
5
b
C A - B
eA/2
aaa M C A - B S D S
c
e
0.100 BSC
2.54 BSC
-
eA
eA/2
L
0.300 BSC
0.150 BSC
7.62 BSC
3.81 BSC
-
ccc
D
S
M
S
-
NOTES:
0.125
0.200
0.060
-
3.18
5.08
1.52
-
-
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
Q
0.015
0.005
0.38
0.13
6
S1
7
o
o
o
o
90
105
90
105
-
α
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
aaa
bbb
ccc
M
-
-
-
-
0.015
0.030
0.010
0.0015
-
-
-
-
0.38
0.76
0.25
0.038
-
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
-
2, 3
8
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
N
16
16
Rev. 0 4/94
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
18
DG506A, DG507A, DG508A, DG509A
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 LEAD FINISH
F28.6 MIL-STD-1835 GDIP1-T28 (D-10, CONFIGURATION A)
28 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
-D-
E
-A-
INCHES
MIN
MILLIMETERS
BASE
(c)
METAL
SYMBOL
MAX
0.232
0.026
0.023
0.065
0.045
0.018
0.015
1.490
0.610
MIN
-
MAX
5.92
NOTES
b1
A
b
-
-
M
M
(b)
0.014
0.014
0.045
0.023
0.008
0.008
-
0.36
0.36
1.14
0.58
0.20
0.20
-
0.66
2
-B-
b1
b2
b3
c
0.58
3
SECTION A-A
bbb
C A - B
D
D
S
S
S
1.65
-
1.14
4
BASE
PLANE
Q
0.46
2
A
-C-
SEATING
PLANE
c1
D
0.38
3
L
α
37.85
15.49
5
S1
b2
eA
A A
e
E
0.500
12.70
5
b
C A - B
eA/2
aaa M C A - B S D S
c
e
0.100 BSC
2.54 BSC
-
eA
eA/2
L
0.600 BSC
0.300 BSC
15.24 BSC
7.62 BSC
-
ccc
D
S
M
S
-
NOTES:
0.125
0.200
0.060
-
3.18
5.08
1.52
-
-
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
Q
0.015
0.005
0.38
0.13
6
S1
7
o
o
o
o
90
105
90
105
-
α
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
aaa
bbb
ccc
M
-
-
-
-
0.015
0.030
0.010
0.0015
-
-
-
-
0.38
0.76
0.25
0.038
-
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
-
2, 3
8
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
N
28
28
Rev. 0 4/94
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
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Intersil Corporation
Intersil SA
Mercure Center
100, Rue de la Fusee
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Republic of China
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TEL: (321) 724-7000
FAX: (321) 724-7240
19
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