DG187AA [INTERSIL]
High-Speed Drivers with JFET Switch; 与JFET开关高速驱动器
| 型号： | DG187AA |
| 厂家： | 
Intersil |
| 描述： | High-Speed Drivers with JFET Switch |
| 文件： | 总9页 (文件大小：78K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Semiconductor
DG181 thru DG191
High-Speed Drivers with JFET Switch
April 1999
Features
Description
• Constant ONSignals to ±10V (DG182, The DG181 thru DG191 series of analog gates consist of 2
DG185, DG18191), to ±7.5V (All Devices)
or 4 N-channel junction-type field-effect transistors (JFET)
designed to function as electronic switches. Level-shifting
drivers enable low-level inputs (0.8V to 2V) to control the
ON-OFF state of each switch. The driver is designed to
provide a turn-off speed which is faster than turn-on speed,
so that break-before-make action is achieved when
switching from one channel to another. In the ON state, each
switch conducts current equally well in both directions. In the
OFF condition, the switches will block voltages up to 20V
peak-to-peak. Switch-OFF input-output isolation 50dB at
10MHz, due to the low output impedance of the FET-gate
driving circuit.
• ±15V Power Supplies
• <2nA Leakage from Signal Channel in Both ON and
OFF States
• TTL, DTL, RTL Direct Drive Compatibility
• tON, tOFF <150ns, Break-Before-Make Action
• Cross-Talk and Open Switch Isolation >50dB at 10MHz
(75Ω Load)
Functional Diagrams (Typical Channel)
DG186, DG187, DG188 - ONE AND TWO CHANNEL
SPDT AND SPST CIRCUIT CONFIGURATION
DG183, DG184, DG185 - TWO CHANNEL DPST
CIRCUIT CONFIGURATION
VL
VL
V+
V+
S1
D1
S
D
IN
IN
S2
D2
S
D
GND
GND
V-
V-
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
File Number 3114.4
Copyright © Harris Corporation 1999
1
DG181 Series
Part Number Information (Continued)
Part Number Information
R
R
DS(ON)
DS(ON)
PART NUMBER
DG187AA
TYPE
SPDT
(MAX)
30Ω
30Ω
30Ω
30Ω
30Ω
30Ω
75Ω
75Ω
75Ω
75Ω
75Ω
75Ω
30Ω
30Ω
30Ω
75Ω
75Ω
75Ω
PACKAGE
PART NUMBER
DG181AA
TYPE
(MAX)
30Ω
30Ω
30Ω
30Ω
30Ω
30Ω
75Ω
75Ω
75Ω
75Ω
75Ω
75Ω
30Ω
30Ω
30Ω
75Ω
75Ω
75Ω
PACKAGE
10 Lead CAN
10 Lead CAN
14 Lead SBDIP
14 Lead SBDIP
10 Lead CAN
14 Lead SBDIP
10 Lead CAN
10 Lead CAN
14 Lead SBDIP
14 Lead SBDIP
10 Lead CAN
14 Lead SBDIP
16 Lead SBDIP
16 Lead SBDIP
16 Lead SBDIP
16 Lead SBDIP
16 Lead SBDIP
16 Lead SBDIP
Dual SPST
Dual SPST
Dual SPST
Dual SPST
Dual SPST
Dual SPST
Dual SPST
Dual SPST
Dual SPST
Dual SPST
Dual SPST
Dual SPST
Dual DPST
Dual DPST
Dual DPST
Dual DPST
Dual DPST
Dual DPST
10 Lead CAN
10 Lead CAN
14 Lead SBDIP
14 Lead SBDIP
10 Lead CAN
14 Lead SBDIP
10 Lead CAN
10 Lead CAN
14 Lead SBDIP
14 Lead SBDIP
10 Lead CAN
14 Lead SBDIP
16 Lead SBDIP
16 Lead SBDIP
16 Lead SBDIP
16 Lead SBDIP
16 Lead SBDIP
16 Lead SBDIP
DG187AA/883B
DG187AP
SPDT
DG181AA/883B
DG181AP
SPDT
DG187AP/883B
DG187BA
SPDT
DG181AP/883B
DG181BA
SPDT
DG187BP
SPDT
DG181BP
DG188AA
SPDT
DG182AA
DG188AA/883B
DG188AP
SPDT
DG182AA/883B
DG182AP
SPDT
DG188AP/883B
DG188BA
SPDT
DG182AP/883B
DG182BA
SPDT
DG188BP
SPDT
DG182BP
DG190AP
Dual SPDT
Dual SPDT
Dual SPDT
Dual SPDT
Dual SPDT
Dual SPDT
DG184AP
DG190AP/883B
DG190BP
DG184AP/883B
DG184BP
DG191AP
DG185AP
DG191AP/883B
DG191BP
DG185AP/883B
DG185BP
2
DG181 Series
Pinouts and Switching State Diagrams
DUAL SPST - DG181, DG182
(TO-100 METAL CAN)
TOP VIEW
DUAL SPST - DG181, DG182
(CDIP)
TOP VIEW
S2
S1
D1
1
2
3
4
5
6
7
14 S2
13 D2
12 NC
11 NC
10 IN2
10
S1
2
D2
8
1
9
NC
NC
IN1
V+
VL
D1
IN2
V-
3
7
IN1
9
8
V-
4
6
GND
V+
GND
5
VL
DUAL DPST - DG184, DG185
(CDIP)
SPDT - DG187, DG188
(TO-100 METAL CAN)
TOP VIEW
TOP VIEW
D2
D1
NC
D3
S3
1
2
3
4
5
6
7
8
16 S1
15 IN1
14 V-
10
D1
S2
8
1
9
13 GND
12 VL
11 V+
10 IN2
2
NC
V-
S1
IN
S4
3
7
D4
NC
D2
4
6
V+
GND
9
S2
5
VL
SPDT - DG187, DG188
(CDIP)
DUAL SPDT - DG190, DG191
(CDIP)
TOP VIEW
TOP VIEW
D1
NC
D3
S3
1
2
3
4
5
6
7
8
16 S1
15 IN1
14 V-
NC
NC
D1
S1
1
2
3
4
5
6
7
14 NC
13 NC
12 D2
11 S2
10 NC
13 GND
12 VL
11 V+
10 IN2
S4
IN
D4
NC
D2
V+
VL
9
8
V-
GND
9
S2
3
DG181 Series
Absolute Maximum Ratings
Thermal Information
o
o
V+ - V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36V Operating Temperature . . . . . . . . . . . . . . . . . . . . . .-55 C to +125 C
V+ - V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33V Maximum Power Dissipation †
D
V
V
- V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33V
TO Metal Can Packages . . . . . . . . . . . . . . . . . . . . . . . . . . 450mW
D
D
o
o
- V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±22V
Derate 6mW/ C above +75 C
S
V - V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36V
Ceramic DIP Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . 825mW
L
o
o
V - V , V - GND, V - GND . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V
Derate 11mW/ C above +75 C
L
IN
L
IN
GND - V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27V † Device mounted with all leads welded or soldered to PC board.
GND - V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V
IN
Current (S or D) (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . .200mA
o
o
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . -65 C to +150 C
o
Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . +300 C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications V+ = +15V, V- = -15V, V = 5V, Unless Otherwise Specified
L
A SERIES
B SERIES
DEVICE
NUMBER
(NOTE 1)
TEST CONDITIONS
o
o
o
o
o
o
PARAMETER
-55 C
+25 C +125 C -20 C
+25 C
+85 C
UNITS
SWITCH
I
I
I
DG181, DG182,
DG184, DG185, V+ = 10V, V- = -20V,
DG187, DG188,
DG190, DG191
V
= 10V, V = -10V,
-
±1
100
-
±5
100
nA
S(OFF)
S
D
V
= “OFF”
IN
DG181, DG184,
DG187, DG190
V
V
= 7.5V, V = -7.5V,
-
-
-
±1
±1
±1
100
100
100
-
-
-
±5
±5
±5
100
100
100
nA
nA
nA
S
D
= “OFF”
IN
DG182, DG185,
DG188, DG191
V
V
= 10V, V = -10V,
S
D
= “OFF”
IN
DG181, DG182,
DG184, DG185, V+ = 10V, V- = -20V,
DG187, DG188,
DG190, DG191
V
= 10V, V = -10V,
D
D(OFF)
S
V
= “OFF”
IN
DG181, DG184,
DG187, DG190
V
V
= 7.5V, V = -7.5V,
-
-
-
-
±1
±1
±2
±2
100
100
-
-
-
-
±5
±5
100
100
nA
nA
nA
nA
S
D
= “OFF”
IN
DG182, DG185,
DG188, DG191
V
V
= 10V, V = -10V,
S
D
= “OFF”
IN
+ I
DG181, DG184,
DG187, DG190
V
= V = -7.5V, V = “ON”
-200
-200
-10
-10
-200
-200
D(ON)
S(ON)
D
D
S
IN
DG182, DG185,
DG188, DG191
V
= V = -10V, V = “ON”
S
IN
INPUT
I
All
All
V
V
= 0V
= 5V
-250
-
-250
10
-250
20
-250
-
-250
10
-250
20
µA
µA
INL
IN
IN
I
INH
DYNAMIC
t
30Ω Switches
75Ω Switches
See Switching Time
Test Circuit
-
-
-
150
250
130
-
-
-
-
-
-
180
300
150
-
-
-
ns
ns
ns
ON
t
30Ω and 75Ω
OFF
Switches
C
DG181, DG182,
DG184, DG185,
DG187, DG188,
DG190, DG191
V
V
V
= -5V, I = 0, f = 1MHz
9 Typical
pF
pF
pF
S(OFF)
S
D
D
D
= +5V, I = 0, f = 1MHz
6 Typical
S
C
C
+
= V = 0, f = 1MHz
14 Typical
D(ON)
S(ON)
S
OFF Isolation
R = 75Ω, C = 3pF
Typically >50dB at 10MHz
-
L
L
4
DG181 Series
Electrical Specifications V+ = +15V, V- = -15V, V = 5V, Unless Otherwise Specified (Continued)
L
A SERIES
B SERIES
DEVICE
NUMBER
(NOTE 1)
TEST CONDITIONS
o
o
o
o
o
o
PARAMETER
SUPPLY
I+
-55 C
+25 C +125 C -20 C
+25 C
+85 C
UNITS
DG181, DG182,
DG190, DG191
V
= 5V
-
1.5
-
-
1.5
-
mA
IN
DG184, DG185
DG187, DG188
-
-
-
0.1
0.8
-
-
-
-
-
-
0.1
0.8
-
-
-
mA
mA
mA
I-
DG181, DG182,
DG190, DG191
-5.0
-5.0
DG184, DG185
DG187, DG188
-
-
-
-4.0
-3.0
4.5
-
-
-
-
-
-
-4.0
-3.0
4.5
-
-
-
mA
mA
mA
I
I
DG181, DG182,
DG184, DG185,
DG190, DG191
L
DG187, DG188
All
-
-
-
3.2
-2.0
1.5
-
-
-
-
-
-
3.2
-2.0
1.5
-
-
-
mA
mA
mA
GND
I+
DG181, DG182,
DG190, DG191
V
= 0V
IN
DG184, DG185
DG187, DG188
-
-
-
3.0
0.8
-
-
-
-
-
-
3.0
0.8
-
-
-
mA
mA
mA
I-
DG181, DG182,
DG190, DG191
-5.0
-5.0
DG184, DG185
DG187, DG188
-
-
-
-5.5
-3.0
4.5
-
-
-
-
-
-
-5.5
-3.0
4.5
-
-
-
mA
mA
mA
I
I
DG181, DG182,
DG184, DG185,
DG190, DG191
L
DG187, DG188
All
-
-
3.2
-
-
-
-
3.2
-
-
mA
mA
-2.0
-2.0
GND
NOTE:
1. See Switching State Diagrams for V “ON” and V “OFF” Test Conditions.
IN
IN
Electrical Specifications Maximum Resistances (R
MAX)
DS(ON)
MILITARY
TEMPERATURE
o
INDUSTRIAL
TEMPERATURE
DEVICE
NUMBER
TEST CONDITIONS (NOTE 1)
V+ = 15V, V- = -15V, V = 5V
o
o
o
o
o
-55 C
+25 C +125 C -20 C
+25 C
50
+85 C
UNITS
L
DG181
DG182
DG184
DG185
DG187
DG188
DG190
DG191
NOTES:
V
= -7.5V
= -10V
= -7.5V
= -10V
= -7.5V
= -10V
= -7.5V
= -10V
I
= -10mA, V = “ON”
30
75
30
75
30
75
30
75
30
75
30
75
30
75
30
75
60
100
60
50
100
50
75
150
75
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
D
S
IN
V
100
50
D
D
V
V
150
60
100
50
100
50
150
75
D
D
V
V
150
60
100
50
100
50
150
75
D
D
V
V
150
100
100
150
D
1. See Switching State Diagrams for V “ON” and V “OFF” Test Conditions.
IN
IN
2. Normally the minimum signal handling capability of the DG181 thru DG191 family is 20V peak to peak for the 75Ω switches and 15V peak-
to-peak for the 30Ω (refer I and I tests above).
D
S
3. For other Analog Signals, the following guidelines can be used: proper switch turn-off requires that V- ≤ V
(peak) - V where V =
P P
ANALOG
7.5V for the 80Ω switches and V = 5.0V for 75Ω switches e.g., - 10V minimum (-peak) analog signal and a 75Ω switch (V = 5V), requires
P
P
that V- ≤ -10V -5V = -15V.
5
DG181 Series
DUAL DPST - DG184/185
DUAL SPST - DG181/182
TEST CONDITIONS
TEST CONDITIONS
V
V
“ON” = 2.0V
“OFF” = 0.8V
All Channels
All Channels
V
V
“ON” = 0.8V
“OFF” = 2.0V
All Channels
All Channels
IN
IN
IN
IN
NOTE:
NOTE:
1. Switch states are for logic “1” input = 2.0V.
1. Switch states are for logic “1” input = 2.0V.
SPDT - DG190/191
SPDT - DG187/188
TEST CONDITIONS
TEST CONDITIONS
V
V
V
V
“ON” = 2.0V
“ON” = 0.8V
“OFF” = 2.0V
“OFF” = 0.8V
Channel 1 and 2
Channel 3 and 4
Channel 3 and 4
Channel 1 and 2
V
V
V
V
“ON” = 2.0V
“ON” = 0.8V
“OFF” = 2.0V
“OFF” = 0.8V
Channel 1
Channel 2
Channel 2
Channel 1
IN
IN
IN
IN
IN
IN
IN
IN
NOTE:
1. Switch states are for logic “1” input = 2.0V.
NOTE:
1. Switch states are for logic “1” input = 2.0V.
Switching Time Test Circuits
+5V
+15V
VCC
VL
SWITCH
OUTPUT
VO
LOGIC
3V
S1
D1
INPUT
50%
SWITCH
INPUT
50%
tR < 10ns
tF < 10ns
0V
t
t
ON, VS = +10V
OFF, VS = -10V
RL
1kΩ
CL
30pF
IN1
LOGIC
INPUT
SWITCH
VS
INPUT
90%
90%
(REPEAT TEST FOR
ALL CHANNELS)
SWITCH
0V
GND
V-
-15V
OUTPUT
tON
0V
tOFF
RL
VO = VS
RL + RDS(ON)
FIGURE 1. SWITCHING TIME TEST WAVEFORMS (Note 1)
FIGURE 2. SWITCHING TIME TEST CIRCUIT (Note 2)
NOTES:
1. Switch output waveform shown for V = constant with logic input waveform as shown.
S
2. V may be + or - as per switching time test circuit. V is the steady state output with switch on. Feedthrough via gate capacitance may
S
O
result in spikes at leading and trailing edge of output waveform.
6
DG181 Series
Ceramic Dual-In-Line Metal Seal Packages (SBDIP)
D14.3 MIL-STD-1835 CDIP2-T14 (D-1, CONFIGURATION C)
14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
c1 LEAD FINISH
-A-
-D-
E
INCHES MILLIMETERS
MIN
BASE
METAL
(c)
SYMBOL
MAX
0.200
0.026
0.023
0.065
0.045
0.018
0.015
0.785
0.310
MIN
-
MAX
5.08
0.66
0.58
1.65
1.14
0.46
0.38
19.94
7.87
NOTES
A
b
-
-
b1
M
M
0.014
0.014
0.045
0.023
0.008
0.008
-
0.36
0.36
1.14
0.58
0.20
0.20
-
2
-B-
(b)
b1
b2
b3
c
3
SECTION A-A
S
S
S
D
bbb
C
A - B
-
D
4
BASE
PLANE
S2
Q
2
A
-C-
SEATING
PLANE
c1
D
3
L
-
S1
b2
eA
A A
E
0.220
5.59
-
e
0.100 BSC
2.54 BSC
-
e
eA/2
C A - B
b
C A - B
c
eA
eA/2
L
0.300 BSC
0.150 BSC
7.62 BSC
3.81 BSC
-
ccc
D
aaa
D
S S
M
S
S
M
-
NOTES:
0.125
0.200
3.18
5.08
-
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
Q
0.015
0.005
0.005
0.060
0.38
0.13
0.13
1.52
5
S1
S2
-
-
-
-
6
7
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
o
o
o
o
90
105
90
105
-
α
aaa
bbb
ccc
M
-
-
-
-
0.015
0.030
0.010
0.0015
-
-
-
-
0.38
0.76
0.25
0.038
-
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
-
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
2
8
N
14
14
Rev. 0 4/94
5. Dimension Q shall be measured from the seating plane to the
base plane.
6. Measure dimension S1 at all four corners.
7. Measure dimension S2 from the top of the ceramic body to the
nearest metallization or lead.
8. N is the maximum number of terminal positions.
9. Braze fillets shall be concave.
10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
11. Controlling dimension: INCH.
7
DG181 Series
Ceramic Dual-In-Line Metal Seal Packages (SBDIP)
D16.3 MIL-STD-1835 CDIP2-T16 (D-2, CONFIGURATION C)
16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
c1 LEAD FINISH
-A-
-D-
E
INCHES MILLIMETERS
MIN
BASE
METAL
(c)
SYMBOL
MAX
0.200
0.026
0.023
0.065
0.045
0.018
0.015
0.840
0.310
MIN
-
MAX
5.08
0.66
0.58
1.65
1.14
0.46
0.38
21.34
7.87
NOTES
A
b
-
-
b1
M
M
0.014
0.014
0.045
0.023
0.008
0.008
-
0.36
0.36
1.14
0.58
0.20
0.20
-
2
-B-
(b)
b1
b2
b3
c
3
SECTION A-A
S
S
S
D
bbb
C
A - B
-
D
4
BASE
PLANE
S2
Q
2
A
-C-
SEATING
PLANE
c1
D
3
L
-
S1
b2
eA
A A
E
0.220
5.59
-
e
0.100 BSC
2.54 BSC
-
e
eA/2
C A - B
b
C A - B
c
eA
eA/2
L
0.300 BSC
0.150 BSC
7.62 BSC
3.81 BSC
-
ccc
D
aaa
D
S S
M
S
S
M
-
NOTES:
0.125
0.200
3.18
5.08
-
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
Q
0.015
0.005
0.005
0.060
0.38
0.13
0.13
1.52
5
S1
S2
-
-
-
-
6
7
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
o
o
o
o
90
105
90
105
-
α
aaa
bbb
ccc
M
-
-
-
-
0.015
0.030
0.010
0.0015
-
-
-
-
0.38
0.76
0.25
0.038
-
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
-
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
2
8
N
16
16
Rev. 0 4/94
5. Dimension Q shall be measured from the seating plane to the
base plane.
6. Measure dimension S1 at all four corners.
7. Measure dimension S2 from the top of the ceramic body to the
nearest metallization or lead.
8. N is the maximum number of terminal positions.
9. Braze fillets shall be concave.
10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
11. Controlling dimension: INCH.
8
DG181 Series
Metal Can Packages (Can)
REFERENCE PLANE
T10.B MIL-STD-1835 MACY1-X10 (A2)
10 LEAD METAL CAN PACKAGE
A
e1
L
INCHES
MILLIMETERS
L2
L1
SYMBOL
A
MIN
MAX
0.185
0.019
0.021
0.024
0.375
0.335
0.160
MIN
4.19
0.41
0.41
0.41
8.51
7.75
2.79
MAX
4.70
0.48
0.53
0.61
9.52
8.51
4.06
NOTES
ØD2
0.165
0.016
0.016
0.016
0.335
0.305
0.110
-
A
A
Øb
Øb1
Øb2
ØD
ØD1
ØD2
e
1
k1
1
Øe
ØD ØD1
-
2
N
1
-
-
Øb1
β
α
C
-
L
Øb
k
F
0.230 BSC
0.115 BSC
5.84 BSC
2.92 BSC
-
BASE AND
Q
e1
-
SEATING PLANE
F
-
0.040
0.034
0.045
0.750
0.050
-
-
1.02
0.86
1.14
19.05
1.27
-
-
BASE METAL
LEAD FINISH
Øb2
k
0.027
0.027
0.500
-
0.69
0.69
12.70
-
-
k1
2
Øb1
L
1
L1
1
SECTION A-A
L2
0.250
0.010
6.35
0.25
1
Q
0.045
1.14
-
NOTES:
o
o
36 BSC
36 BSC
3
α
β
1. (All leads) Øb applies between L1 and L2. Øb1 applies between
L2 and 0.500 from the reference plane. Diameter is uncontrolled
in L1 and beyond 0.500 from the reference plane.
o
o
36 BSC
36 BSC
3
4
N
10
10
2. Measured from maximum diameter of the product.
Rev. 0 5/18/94
3. α is the basic spacing from the centerline of the tab to terminal 1
and β is the basic spacing of each lead or lead position (N -1
places) from α, looking at the bottom of the package.
4. N is the maximum number of terminal positions.
5. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
6. Controlling dimension: INCH.
9
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