CDP1871 [INTERSIL]
CMOS Keyboard Encoder; CMOS键盘编码器
| 型号： | CDP1871 |
| 厂家： | 
Intersil |
| 描述： | CMOS Keyboard Encoder |
| 文件： | 总10页 (文件大小：60K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDP1871A,
CDP1871AC
REFERENCE APP NOTE 7374
August 1996
CMOS Keyboard Encoder
Features
Description
• Directly Interfaces with CDP1800-Series Microprocessor
• Low Power Dissipation
The CDP1871A is a keyboard encoder designed to
directly interface between a CDP1800-series micro-
processor and a mechanical keyboard array, providing
up to 53 ASCII coded keys and 32 HEX coded keys,
as shown in the system diagram (Figure 1).
• Three-State Outputs
• Scans and Generates Code for 53 Key ASCII Keyboard Plus
32 HEX Keys (SPST Mechanical Contact Switches)
The keyboard may consist of simple single-pole
single-throw (SPST) mechanical switches. Inputs are
provided for alpha-lock, control, and shift functions,
allowing 160 unique codes. An external R-C input is
available for user-selectable debounce times. The N-
key lock-out feature prevents unwanted key codes if
two or more keys are pressed simultaneously.
• Shift, Control, and Alpha Lock Input
• RC-Controlled Debounce Circuitry
• Single Supply 4V to 10.5V. . . . . . . . . . . . . (CDP1871A)
4V to 6.5V. . . . . . . . . . . . . (CDP1871AC)
• N-Key Lockout
The CDP1871A and CDP1871AC are functionally
identical. They differ in that the CDP1871A has a
recommended operating voltage range of 4V to 10.5V,
and the CDP1871AC has a recommended operating
voltage range 4V to 6.5V. These types are supplied in
40 lead dual-in-line ceramic packages (D suffix), and
40 lead dual-in-line plastic packages (E suffix), and 44
lead plastic chip-carrier packages (Q suffix).
Ordering Information
PKG.
NO.
PACKAGE TEMP. RANGE
5V
10V
o
o
PDIP
-40 C to +85 C CDP1871ACE CDP1871AE E40.6
o
o
PLCC
SBDIP
-40 C to +85 C CDP1871ACQ
-
N44.65
-40 C to +85 C CDP1871ACD CDP1871AD D40.6
CDP1871ACDX D40.6
o
o
Burn-In
-
Pinouts
44 LEAD PLCC
40 LEAD PDIP, CERDIP
TOP VIEW
(Q Suffix) TOP VIEW
D1
1
2
3
4
5
6
7
8
9
40 VDD
D2
D3
D4
D5
D6
D7
D8
D9
39 SHIFT
38 CONTROL
37 ALPHA
36 DEBOUNCE
35 RTP
6
5
4
3
2
1
44 43 42 41 40
D5
D6
D7
D8
D9
D10
D11
S1
7
39
38
37
36
35
34
33
32
31
30
29
RPT
8
TPB
34 TPB
9
DA
33 DA
10
11
12
13
14
15
16
17
BUS 7
BUS 6
BUS 5
BUS 4
BUS 3
BUS 2
BUS 1
NC
32 BUS 7
31 BUS 6
30 BUS 5
29 BUS 4
28 BUS 3
27 BUS 2
26 BUS 1
25 BUS 0
24 CS4
D10 10
D11 11
S1 12
S2 13
S3 14
S4 15
S5 16
S6 17
S7 18
S8 19
VSS 20
S2
S3
S4
18 19 20 21 22 23 24 25 26 27 28
23 CS3
22 CS2
21 CS1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 1374.2
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-66
CDP1871A, CDP1871AC
VDD
0.1µF
100K
40
36
DEBOUNCE
21
CONTROL
23
24
11
CS1,
N0-N2
D11
CS2,
CS3
MRD
TPB
CS4
TPB
34
UP TO 11 SETS
OF 8 SWITCHES EACH
CDP1800-SERIES
CDP1871A
CPU
VDD
SHIFT
39
1
SHIFT
D1
CONTROL
38
CONTROL
ALPHA
12
13
14
15
16
17
18
19
S1
S2
S3
S4
S5
S6
S7
S8
ALPHA LOCK
37
NORMAL
BUS0-BUS7
BUS0-BUS7
25 32
8 BIT DATA BUS
FIGURE 1. TYPICAL CDP1800 SERIES MICROPROCESSOR SYSTEM USING THE CDP1871A
CS1
CS2
CS3
SCAN CLOCK
21
22
23
24
34
CS
THREE-STAGE
SCAN COUNTER
FIVE-STAGE
SCAN COUNTER
BUS ENABLE
CS4
TPB
CONTROL
LOGIC
BUS 0
BUS 7
25
32
C1-C3
C4-C8
THREE-STATE
OUTPUT
BUFFERS
KEY
DETECT
F/F
VDD
RX
DEBOUNCE
36
CX
RN
40
20
VDD
VSS
33
35
DA
KEY DOWN
DETECT
LATCH
RPD
STATUS
LATCHES
RPT
1 OF 8
MUX
RPD
RPD
II
DECODER/
DRIVERS
RPD
FROM
KEY BOARD
TO
KEY BOARD
12
19
1
11
37
39
38
CONTROL
SENSE
LINES
DRIVE
LINES
DI
DII
ALPHA SHIFT
FIGURE 2. CDP1871A BLOCK DIAGRAM
4-67
CDP1871A, CDP1871AC
Absolute Maximum Ratings
Thermal Information
o
o
(All Voltages Referenced to V Terminal)
Thermal Resistance (Typical)
θ
( C/W)
θ
( C/W)
SS
JA
JC
CDP1871A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V
CDP1871AC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
PDIP Package . . . . . . . . . . . . . . . . . . .
PLCC Package . . . . . . . . . . . . . . . . . .
SBDIP Package. . . . . . . . . . . . . . . . . .
Device Dissipation Per Output Transistor
60
50
60
N/A
N/A
18
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to V +0.5V
DD
DC Input Current, any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA
T = Full Package Temperature Range
A
(All Package Types). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW
Operating Temperature Range (T )
A
o
o
Package Type D. . . . . . . . . . . . . . . . . . . . . . . . . .-55 C to +125 C
Package Type E and Q . . . . . . . . . . . . . . . . . . . . .-40 C to +85 C
o
o
o
o
Storage Temperature Range (T
) . . . . . . . . . . . .-65 C to +150 C
STG
Lead Temperature (During Soldering)
At distance 1/16 ± 1/32 In. (1.59 ± 0.79mm)
from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265 C
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
o
Recommended Operating Conditions At T = -40 to +85 C. For maximum reliability, operating conditions should be selected
A
so that operation is always within the following ranges:
LIMITS
CDP1871AD, CDP1871AE
CDP1871ACD, CDP1871ACE
V
DD
PARAMETER
Supply Voltage Range
(V)
MIN
MAX
MIN
MAX
UNITS
4
10.5
4
6.5
V
V
Recommended Input Voltage
Range
V
V
V
V
DD
SS
DD
SS
Clock Input Frequency, TPB
(Keyboard Capacitance = 200 pF)
f
5
DC
DC
0.4
0.8
DC
-
0.4
-
MHz
MHz
CL
10
NOTE:
1. Printed-circuit board mount: 57mm x 57mm minimum area x 1.6mm thick G10 epoxy glass, or equivalent.
o
Static Electrical Specifications At T = -40 to +85 C, Unless Otherwise Specified
A
CONDITIONS
LIMITS
CDP1871AD
CDP1871AE
CDP1871ACD
CDP1871ACE
V
V
V
DD
(NOTE 1)
(NOTE1)
O
IN
PARAMETER
Quiescent Device
(V)
(V)
(V)
MIN
-
TYP
MAX
MIN
TYP
MAX
UNITS
µA
I
-
0.5
5
0.1
1
50
-
1
-
200
DD
Current
-
0, 10
0, 5
10
5
-
200
-
0.5
-
-
-
-
-
-
-
-
µA
Output Low Drive (Sink)
Current (Except Debounce
and D1-D11)
I
I
I
0.4
0.5
0.4
0.5
0.4
0.5
0.5
1
1
-
-
-
-
-
-
1
mA
mA
mA
mA
mA
mA
OL
0, 10
0, 5
10
5
2
-
Debounce
0.75
1
1.5
2
0.75
-
1.5
-
OL
OL
0, 10
0, 5
10
5
D1-D11
0.05
0.1
0.1
0.2
0.05
-
0.1
-
0, 10
10
4-68
CDP1871A, CDP1871ACCDP1871A, CDP1871AC
o
Static Electrical Specifications At T = -40 to +85 C, Unless Otherwise Specified (Continued)
A
CONDITIONS
LIMITS
CDP1871AD
CDP1871AE
CDP1871ACD
CDP1871ACE
V
V
V
DD
(NOTE 1)
(NOTE1)
O
IN
PARAMETER
(V)
(V)
(V)
MIN
-0.3
-0.75
-
TYP
MAX
MIN
TYP
MAX
UNITS
Output High Drive (Source)
Current
I
4.6
0, 5
5
-0.6
-
-
-0.3
-0.6
-
mA
mA
V
OH
9.5
0, 10
10
5
-1.5
-
-
-
-
1.5
-
Input Low Voltage
(Except Debounce)
V
0.5, 4.5
1, 9
-
-
-
-
-
-
1.5
3
-
IL
10
5
-
-
-
-
-
-
V
Input High Voltage
(Except Debounce)
V
0.5, 4.5
1, 9
3.5
7
-
3.5
-
-
V
IH
10
5
-
-
-
-
V
Debounce Schmitt Trigger
Input Voltage
V
0.4
2.0
3.3
4.0
2.0
3.3
4.0
V
D
Positive Trigger Voltage
Negative Trigger Voltage
0.5
-
10
5
4.0
6.3
1.8
4.0
1.6
2.3
0
8.0
3.0
6.0
2.6
4.7
0.05
0.05
-
-
-
-
V
V
V
V
0.4
-
0.8
0.8
1.8
3.0
N
H
0.5
-
10
5
1.9
-
-
-
V
Hysteresis
0.4
0, 5
0, 10
0, 5
0, 10
0, 5
0, 10
0, 5
0, 10
0, 5
0, 10
-
0.3
0.3
1.6
2.6
V
0.5
10
5
0.7
-
-
-
V
Output Voltage Low Level
Output Voltage High Level
V
-
-
-
0
0.05
V
OL
OH
IN
-
10
5
-
0
-
-
-
-
V
V
I
-
4.95
5
4.95
5
V
-
10
5
9.95
10
-
-
-
-
0.01
-
-
V
Input Leakage Current
(Except S1-S8, Shift,
Control)
-
-
-
-
0.01
0.01
0.01
0.02
14
1
1
-
µA
µA
µA
µA
kΩ
10
5
1
-
Three-State Output Leakage
Current
I
0, 5
0, 10
-
-
1
-
0.02
-
2
-
OUT
10
-
-
2
-
Pull-Down Resistor Value
(S1-S8, Shift, Control)
R
7
24
7
14
24
PD
Operating Current
(All Outputs Unloaded)
f
= 0.4MHz
= 0.8MHz
I
0.5, 4.5
1, 9
0, 5
5
-
-
0.6
2.7
-
-
-
-
0.6
-
-
-
mA
mA
CL
CL
OPER
f
0, 10
10
NOTE:
1. Typical values are for T = +25 C and nominal V
o
.
DD
A
4-69
CDP1871A, CDP1871AC
Functional Description of
CDP1871A Terminals
D1 - D11 (Outputs):
TPB (Input):
Drive lines for the 11 x 8 keyboard switch matrix. These The input clock used to drive the scan generator and reset
outputs are connected through the external switch matrix to the status flag (DA). This input is normally connected to the
the sense lines (S1 - S8).
TPB output of the CDP1800-series microprocessor.
S1 - S8 (Inputs):
RPT (Output):
Sense lines for the 11 x 8 keyboard maxtrix. These inputs The repeat output flag which is used to indicate that a key is
have internal pull-down resistors and are driven high by still closed after data has been read from the CDP1871A
appropriate drive line when a keyboard switch is closed.
(DA = high). It remains low as long as the key is closed and
is used for an autorepeat function, under CPU control. This
output is normally connected to a flag input (EF1 - EF4) of
the CDP1800-series microprocessor.
CS1, CS2, CS3, CS4 (Inputs):
Chip select inputs, which are used to enable the three-state
data bus outputs (BUS 0 - BUS 7) and to enable the reset-
ting of the status flag (DA), which occurs on the low-to-high
DEBOUNCE (Input):
transition of TPB. These four inputs are normally connected This input is connected to the junction of an external resistor
to the N-lines (N0-N2) and MRD output of the CDP1800- to VDD and capacitor to VSS. It provides a debounce time
series microprocessor. (Table 2)
delay (t RC) after the release of a key. If a debounce is not
desired, the external pull-up resistor is still required.
BUS 0 - BUS 7 (Outputs):
ALPHA, SHIFT, CONTROL (Inputs):
Three-state data bus outputs which provide the ASCll and
HEX codes of the detected keys. The outputs are normally A high on the SHIFT or CONTROL inputs will be internally
connected to the BUS 0 - BUS 7 terminals of the CDP1800- latched (after the debounce time) and the drive and sense
series microprocessor.
line decoding will be modified as shown in Table 3. They are
normally connected to the keyboard, but produce no code by
themselves. The SHIFT and CONTROL inputs have internal
pull-down resistors to simplify use with momentary contact
switches. The ALPHA input is not latched and is designed for
a standard SPDT switch to provide an alpha-lock function.
When ALPHA = 1 the drive and sense line decoding will be
modified as shown in Table 3.
DA (Output):
The data available output flag which is set low when a valid
key closure is detected. It is reset high by the low-to-high
transition of TPB when data is read from the CDP1871A.
This output is normally connected to a flag input (EF1 - EF4)
of the CDP1800-series microprocessor.
VDD, VSS:
VDD is the positive supply voltage input. VSS is the most
negative supply voltage terminal and is normal connected to
ground. All outputs swing from VSS to VDD
.
The
recommended input voltage swing is from VSS to VDD
.
TABLE 1. SWITCH INPUT FUNCTIONS
SHIFT ALPHA
CONTROL
KEY FUNCTION
Normal
0
0
0
1
X
1
0
X
X
1
Control
0
Shift
0
Alpha
NOTE: X = Don’t Care
4-70
CDP1871A, CDP1871AC
TABLE 2. VALID N-LINE CONNECTIONS
CDP1871A SIGNAL
CPU INPUT
CPU
CS4
MRD
MRD
MRD
CS3
N2
CS2
N0
CS1
N1
INSTRUCTION
CDP1800- Series Signal
INP5
INP3
INP6
N0
N1
N2
N2
N1
N0
TABLE 3. DRIVE AND SENSE LINE KEYBOARD CONNECTIONS (NOTE 2)
DRIVE LINES
SENSE
LINES
D
D
D
D
D
D
D
D
D
D
D
11
1
2
3
4
5
6
7
8
9
10
S
SP
0
0
(
8
‘
@
H
h
H
P
p
P
X
x
X
Space
80
88
90
98
1
1
16
16
16
6
8
@
NUL
BS
DLE
CA
N
S
S
!
1
2
)
9
*
:
9
:
A
a
B
b
A
SOH
B
I
i
I
Q
q
R
r
Q
DC1
R
Y
y
Y
EM
Z
81
89
91
92
99
2
3
1
1
16
16
16
16
6
1
“
HT
J
J
j
Z
z
Line
Feed
82
8A
8B
8C
8D
8E
9A
9B
9C
9D
9E
16
16
16
16
16
16
16
16
16
16
16
16
6
2
STX
LF
DC2
SU
B
S
S
S
S
S
#
3
3
4
5
6
7
+
;
;
,
-
.
/
C
c
C
K
k
K
S
s
S
{
[
[
Escape
83
93
94
95
96
97
4
5
6
7
8
1
1
1
1
1
16
16
16
16
16
6
ETX
VT
DC3
ES
C
$
<
D
D
L
L
T
T
|
|
\
84
6
4
%
5
,
=
-
d
E
e
EOT
E
I
FF
M
t
DC4
U
\
}
]
FS
]
M
m
U
u
Carriage 85
Return
6
ENQ
CR
NA
K
GS
&
6
>
.
F
f
F
N
n
N
V
v
V
~
↑
86
6
ACK
SO
SY
N
↑
RS
‘
?
/
G
g
G
O
o
O
W
W
W
Del
-
-
Delete
87
8F
9F
6
7
BEL
SI
ETB
US
SHIFT (Note 1)
NORMAL
ALPHA (Note 1)
KEY:
CONTROL (Note 1)
NOTES:
1. CONTROL overrides SHIFT and ALPHA
= No Response
2. Showing ASCII outputs for all combinations with and without SHIFT, ALPHA LOCK and CONTROL.
3. Drive lines 8, 9, 10 and 11 generate non-ASCII hex values which can be used for special codes.
4-71
CDP1871A, CDP1871AC
TABLE 4. HEXIDECIMAL VALUES OF ASCII CHARACTERS
MSD
b7
0
0
0
0
1
1
1
1
b6
b5
0
0
1
1
0
0
1
1
BITS
0
1
0
1
0
1
0
1
HEX
b4
0
0
0
0
0
0
0
0
1
1
1
1
1
b3
0
0
0
0
1
1
1
1
0
0
0
0
1
b2
0
0
1
1
0
0
1
1
0
0
1
1
0
b1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
2
SP
!
3
0
1
2
3
4
5
6
7
8
9
:
4
@
A
B
C
D
E
F
G
H
I
5
P
Q
R
S
T
U
V
W
X
Y
Z
[
6
\
7
p
q
r
0
1
2
3
4
5
6
7
8
9
A
B
C
NUL
SOH
STX
ETX
EOT
ENQ
ACK
BEL
BS
DLE
DC1
DC2
DC3
DC4
NAK
SYN
ETB
CAN
EM
a
b
c
d
e
f
“
#
$
%
&
/
s
t
u
v
w
x
y
z
{
g
h
i
LSD
(
HT
)
LF
SUB
ESC
FS
*
J
j
VT
+
,
;
K
L
k
l
FF
<
\
|
|
1
1
1
1
1
1
0
1
1
1
0
1
D
E
F
CR
SO
SI
GS
RS
US
-
.
/
=
>
?
M
N
O
]
↑
-
m
n
}
~
o
DEL
Operation
The CDP1871A is made up of two major sections: the outputs (C1 - C8) represent the ASCII and HEX key codes
counter/scan-selection logic and the control logic (Figure 2). and are used to drive the BUS 0 - BUS 7 outputs, which
The counter and scan-selection logic scans the keyboard interface directly to the CDP1800-Series data bus. The BUS
array using the drive lines (D1-D11) and the sense lines (S1- 0 - BUS 7 outputs, which are normally three-stated, are
S8). The outputs of the internal 5-stage scancounter are enabled by decoding the CS inputs during a CPU input
conditionally encoded by the ALPHA, SHIFT, and CONTROL instruction (Table 2). The low-to-high transition of TPB during
inputs (Table 1, Table 3) and are used to drive the D1-D11 the input instruction resets the DA output high. Once the DA
output lines high one at a time. Each D1-D11 output may output has been reset, it cannot go low again until the
drive up to eight keys, which are sampled by the sense line present key is released and a new keydown condition is
inputs (S1-S8). The S1-S8 inputs are enabled by the internal detected. (This prevents unwanted repeated keycode out-
3-stage scancounter.
puts which may be caused by fast software routines).
The control logic interfaces with the CDP1800-series I/O and After the depressed key is released and the debounce delay
timing signals to establish timing and status conditions for (determined by RX, CX) has occurred, the scan clock inhibit
the CDP1871A.
is removed, allowing the scancounters to advance on the fol-
lowing high-to-low transitions of TPB. This provides an N-key
lockout feature, which prevents the entry of erroneous codes
when two or more keys are pressed simultaneously. The first
key pressed in the scanning order is recognized, while all
other keys pressed are ignored until the first key is released
The TPB input clocks the scancounters and is also used to
reset the Data Available output (DA). When a valid keydown
condition is detected on a sense line, the control logic inhib-
its the clock to the scancounters on the next low-to-high tran-
sition of TPB and the DA output is set low. The scancounter
4-72
CDP1871A, CDP1871AC
and read by the CPU, at which time the next key pressed in (CX) is discharged, providing a key closure debounce time
the scanning order is detected. If the first key remains closed RNCX. This discharge is sensed by the Schmitt-trigger
after the CPU reads the data and resets the DA output, on inverter, which clocks the DA flip-flop (latching the DA output
the low-to-high transition of TPB, an auxiliary signal (RPT) is low and inhibiting the scan clock). (The DA F/F is reset by
generated and is available to the CPU to indicate an auto- the low-to-high transition of TPB when the CS inputs are
repeat condition. The RPT output is reset high at the end of enabled). When a valid key-release is detected RN is dis-
the debounce delay after the depressed key is released.
abled and CX begins to charge through the external resistor
(RX), providing a key-release debounce time RXCX. This
charge time is again sensed by the Schmitt-trigger inverter,
enabling the scan clock to continue on the next high-to-low
transitions of TPB, after the current keycode data is read by
the CPU.
The DEBOUNCE input provides a terminal connection for an
external user-selected RC circuit to eliminate false detection
of a keydown condition caused by keyboard noise. The oper-
ation of the DEBOUNCE circuit is shown in Figure 2 (Pin
36). When a valid keydown is detected, the on-chip active-
resistor device (RN) is enabled and the external capacitor
o
Dynamic Electrical Specifications At T = -40 to +85 C, V ±5%, Unless Otherwise Specified
A
DD
LIMITS
CDP1871AD, CDP1871AE
CDP1871ACD, CDP1871ACE
V
(NOTE 1)
(NOTE 1)
DD
PARAMETER
Clock Cycle Time
(V)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Note 2
Note 2
ns
t
5
-
-
-
-
-
-
-
CC
10
5
-
-
-
-
40
-
-
Clock Pulse Width High
t
100
40
-
100
-
CWH
10
5
50
-
20
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
Data Available Valid Delay
Data Available Invalid Delay
t
260
130
70
500
250
150
75
260
-
500
ns
DAL
DAH
10
5
-
-
ns
t
-
70
-
150
ns
10
5
-
35
-
ns
Scan Count Delay
(Non-Repeat)
t
-
850
425
120
60
1900
950
250
125
200
100
400
200
700
350
850
-
1900
ns
CD1
CDV
CDH
10
5
-
-
250
-
ns
Data Out Valid Delay
Data Out Hold Time
Repeat Valid Delay
Repeat Invalid Delay
NOTES:
t
-
120
-
ns
10
5
-
ns
t
-
100
50
100
-
200
-
ns
10
5
-
ns
t
-
150
75
150
-
400
-
ns
RPL
RPH
10
5
-
ns
t
-
350
170
350
-
700
-
ns
10
-
ns
o
1. Typical values are for T = +25 C and nominal V
.
A
DD
2. t = t
+ t
CWL
CC
CWH
t
= t
+ KC
CWL
CD1
k = 0.9ns per pF
c = Keyboard capacitance (pF)
4-73
CDP1871A, CDP1871AC
tCC
tCWL
TPB
tCWH
KEY
CLOSURE
OPEN
CLOSED
tDAL
tDAH
DA
RPT
RNCX
RXCX
DEBOUNCE
D1-D11
tCD1
NEXT COUNT
PRESENT COUNT
CS
(NOTE)
tCDV
tCDH
BUS0-BUS7
VALID
NOTE: CS = CS1 • CS2 • CS3 • CS4
CS1, CS2, CS3 = (CPU N-LINES)
CS4 (MRD) is High for CPU Input Instruction
FIGURE 3. CDP1871A DYNAMIC TIMING DIAGRAM (NON-REPEAT)
TPB
KEY
DEPRESSED
OPEN
CLOSED
tDAH
DA
tRPH
tRPL
RPT
RXCX
DEBOUNCE
D1-D11
NEXT COUNT
PRESENT COUNT
CS
(NOTE)
tCDV
tCDH
BUS0-BUS7
VALID
NOTE: CS = CS1 • CS2 • CS3 • CS4
CS1, CS2, CS3 = (CPU N-LINES)
CS4 (MRD) is High for CPU Input Instruction
FIGURE 4. FIGURE 4. CDP1871A DYNAMIC TIMING DIAGRAM (REPEAT)
4-74
CDP1871A, CDP1871AC
START
MAIN
PROGRAM
N
DA
= 0 ?
Y
INPUT KEY
DATA
STORE KEY
DATA
DATA =
ASCII CTRL
CHAR. OR
HEX
N
CODE
?
DISPLAY
CHARACTER
Y
PERFORM CONTROL
FUNCTION
IS
N
CHAR. A
REPEATABLE
CHAR.
?
Y
DELAY
Y
RPT
= 0 ?
N
FIGURE 5. TYPICAL SYSTEM SOFTWARE FLOWCHART FOR CDP1871A, CDP1871AC
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
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4-75
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