概述
数据手册CDP1826CE 概述
CMOS 64-Word x 8-Bit Static RAM CMOS 64字×8位的静态RAM
CDP1826CE 数据手册
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PDF下载CDP1826C
CMOS 64-Word x 8-Bit
Static RAM
March 1997
Features
Description
• Ideal for Small, Low-Power RAM Memory Require- The CDP1826C is a general purpose, fully static, 64-word x
ments in Microprocessor and Microcomputer Applica- 8-bit random-access memory, for use in CDP1800-series or
tions
other microprocessor systems where minimum component
count and/or price performance and simplicity in use are
desirable.
• Interfaces with CDP1800-Series Microprocessors
Without Additional Address Decoding
The CDP1826C has 8 common data input and data-output
terminals with three-state capability for direct connection to a
standard bidirectional data bus. Two chip-select inputs - CS1
and CS2 - are provided to simplify memory-system expan-
sion. An additional select pin, CS/A5, is provided to enable
the CDP1826C to be selected directly from the CDP1800
multiplexed address bus without additional latching or
decoding. In an 1800 system, the CS/A5 pin can be tied to
any MA address line from the CDP1800 processor. A TPA
input is provided to latch the high-order bit of this address
line as a chip-select for the CDP1826C. If this CS/A5 input is
latched high, and if CS = 1 and CS2 = 0 at the appropriate
time in the memory cycle, the CDP1826C will be enabled for
writing or reading. In a non-1800 system, the TPA pin can be
tied high, and the CS/A5 pin can be used as a normal
address input.
• Daisy Chain Feature to Further Reduce External
Decoding Needs
• Multiple Chip-Select Inputs for Versatility
• Single Voltage Supply
• No Clock or Precharge Required.
Ordering Information
PKG.
PACKAGE
PDIP
TEMP. RANGE PART NUMBER
NO.
o
o
-40 C to +85 C CDP1826CE
E22.4
Pinout
CDP1826C (PDIP)
The six input-address buffers are gated with the chip-select
function to reduce standby current when the device is dese-
lected, as well as to provide for a simplified power down
mode by reducing address buffer sensitivity to long fall times
from address drivers which are being powered down.
TOP VIEW
22
V
DD
BUS 0
BUS 1
BUS 2
BUS 3
BUS 4
BUS 5
BUS 6
BUS 7
CS1
1
2
21 A0
3
20
19
18
17
16
15
14
13
12
CS/A5
Two memory control signals, MRD and MWR, are provided
for reading from the writing to the CDP1826C. The logic is
designed so that MWR overrides MRD, allowing the chip to
be controlled from a single R/W.
4
A1
5
A2
6
A3
7
A4
A CHIP ENABLE OUTPUT is provided for daisy-chaining to
additional memories or I/O devices. This output is high
whenever the chip-select function selects the CDP1826C,
which deselects any other chip which has its CS input con-
nected to the CDP1826C CEO output. The connected chip is
selected when the CDP1826C is deselected and the MRD
input is low. Thus, the CEO is only active for a read cycle
and can be setup so that a CEO of another device can feed
the MRD of the CDP1826C, which in turn selects a third chip
in the daisy chain.
8
TPA
MRD
MWR
CEO
9
10
11
CS2
V
SS
The CDP1826C has a recommended operating voltage of
4.5V to 5.5V and is supplied in 22 lead dual-in-line plastic
packages (E suffix). The CDP1826C is also available in chip
form (H suffix).
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 1311.2
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-47
CDP1826C
CLEAR WAIT
N0 - N2 MRD
ADDR BUS
TPA
ADDR BUS
TPB
Q
TPA
DATA
CPU
CDP1800
SERIES
SCO SCI
RAM
CDP1826C
ROM
I/O
CONTROL
INTERRUPT
MRD
CEO
MRD
MWR
DMA - IN DMA OUT
EF1 - EF4
8-BIT BIDIRECTIONAL DATA BUS
FIGURE 1. TYPICAL CDP1802 MICROPROCESSOR SYSTEM
6-48
CDP1826C
Absolute Maximum Ratings
Thermal Information
o
o
DC Supply Voltage Range, (V
DD
)
Thermal Resistance (Typical)
θ
( C/W)
θ
( C/W)
JA
JC
(All Voltages Referenced to V Terminal)
PDIP Package . . . . . . . . . . . . . . . . . . .
75
N/A
SS
CDP1826C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V Device Dissipation Per Output Transistor
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to V +0.5V T = Full Package Temperature Range
DD
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Power Dissipation Per Package (P )
A
(All Package Types). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW
Operating Temperature Range (T )
Package Type D. . . . . . . . . . . . . . . . . . . . . . . . . .-55 C to +125 C
Package Type E. . . . . . . . . . . . . . . . . . . . . . . . . . .-40 C to +85 C
D
A
o
o
o
o
T = -40 C to +60 C (Package Type E) . . . . . . . . . . . . . . 500mW
A
o
o
o
o
T = +60 C to +85 C (Package Type E). . . . . . Derate Linearly at
A
o
o
o
12mW/ C to 200mW
Storage Temperature Range (T ). . . . . . . . . . . .-65 C to +150 C
STG
o
o
T = -55 C to +100 C (Package Type D) . . . . . . . . . . . . . 500mW Lead Temperature (During Soldering)
A
o
o
T = +100 C to +125 C (Package Type D). . . . Derate Linearly at
At distance 1/16 ±1/32 In. (1.59 ±0.79mm)
from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265 C
A
o
o
12mW/ C to 200mW
Recommended Operating Conditions At T = Full Package Temperature Range. For maximum reliability, operating conditions
A
should be selected so that operation is always within the following ranges:
CDP1826C
PARAMETER
DC Operating Voltage Range
SYMBOL
MIN
MAX
UNITS
4
6.5
V
V
Input Voltage Range
V
V
DD
SS
-
Input Signal Rise or Fall Time, V
= 5V
t , t
R F
10
µs
DD
o
o
Static Electrical Specifications At T = -40 C to +85 C, V = 5V ±5%, Except as Noted:
A
DD
CONDITIONS
LIMITS
CDP1826C
V
(V)
V
(NOTE 1)
TYP
O
IN
(V)
PARAMETER
Quiescent Device Current
SYMBOL
MIN
-
MAX
50
-
UNITS
I
-
0, V
5
µA
mA
mA
mA
mA
V
DD
DD
DD
DD
DD
DD
DD
DD
Output Low (Sink) Current
BUS
I
0.4
0.4
0, V
0, V
0, V
0, V
0, V
0, V
-
1.6
0.8
-1.0
-0.6
-
3.2
1.6
-1.5
-1.0
0
OL
CEO
BUS
CEO
-
Output High (Source) Current
I
V
V
-0.4
-
OH
DD
DD
-0.4
-
Output Voltage Low-Level
Output Voltage High-Level
Input Low Voltage
V
-
0.1
-
OL
V
-
-
-
V
-0.1
V
V
OH
DD
DD
-
V
-
1.5
-
V
IL
IH
IN
Input High Voltage
V
-
3.5
-
V
Input Leakage Current
Operating Device Current (Note 2)
Three-State Output Leakage Current
Input Capacitance
I
Any Input
-
0, V
0, V
0, V
-
-
-
-
-
-
±0.1
5
±1
10
±1
7.5
15
µA
mA
µA
pF
pF
DD
DD
DD
I
OPER
I
0, V
±0.1
5
OUT
DD
C
-
-
IN
Output Capacitance
C
0, V
10
OUT
DD
NOTES:
o
1. Typical values are for T = +25 C and nominal V
A
.
DD
2. Outputs open circuited; Cycle time = 1µs.
6-49
CDP1826C
Signal Descriptions
A0 - A4, CS/A5 (Address Inputs): These inputs must be sition of the TPA input. Tie TPA high to disable the CS/A5
stable prior to a write operation, but may change asynchro- latch feature.
nously during Read operations.
CS1, CS2 (Chip Selector): Either chip select (CS1 or CS2),
In an 1800 system, the multiplexed high-order address bit at when not valid, powers down the chip, disables READ and
pin CS/A5 can be latched at the end of TPA. A high level will WRITE functions, and gates off the address and output buffers.
provide a valid chip select for the CDP1826C. The low-order
MRD, MWR: Read and Write control signals. MWR over-
address bit which appears after TPA is used for data word
rides MRD, allowing the CDP1826C to be controlled from a
selection. In non-1800 systems, TPA can be tied high to dis-
single R/W line.
able the latch and allow the CS/A5 pin to function as a nor-
mal address input.
CEO (Chip Enable Output): Allows daisy chaining to addi-
tional memories. CEO is high whenever the CDP1826C is
selected. CEO is only active (low) for a Read cycle with the
CDP1826C deselected and the MRD input low.
BUS 0 - BUS 7: 8-bit three-state common input/output data
bus.
TPA: High-order address strobe input. The high-order
address bit at input CS/A5 is latched on the high-to-low tran-
V
, V : Power supply connections.
DD SS
BUS 0
BUS 1
BUS 2
A0
A1
INPUT/OUTPUT
DATA
BUFFERS
AND
INPUT
ADDRESS
BUFFERS
A2
A3
BUS 3
BUS 4
XY
DECODE
64 x 8
MATRIX
CONTROL
A4
BUS 5
BUS 6
BUS 7
CS/A5
D
C
Q
TPA
CS1
CS2
MWR
MRD
CEO
FIGURE 2. FUNCTIONAL DIAGRAM
6-50
CDP1826C
1800 CLOCK
A5
TPA
MRD
CEO
BUS
VALID DATA
VALID DATA
RAM CYCLE
CS1 = 1, CS2 = 0
(RAM SELECTED)
ROM CYCLE
(RAM DESELECTED)
OPERATING MODES
(NOTE 1)
FUNCTION
MRD
MWR
CS1 • CS2
TPA
CS/A5
CEO
CDP1800 Mode
Write
X
O
I
O
I
I
I
I
I
I
Read
I
Deselect
Deselect
Deselect
Deselect
Deselect
Write
I
I
I
I
I
X
X
X
X
O
I
O
O
X
X
I
X
X
X
X
O
O
X
X
X
X
X
I
O
I
O
I
O
X
O
I
O
I
Non-CDP1800 Mode
I
I
I
I
I
Read
I
I
Deselect
Deselect
Deselect
I
I
I
I
X
X
O
O
I
O
O
NOTE:
1. For CDP1800 Mode, refers to high order memory address bit level at time when TPA
place.
transition takes
FIGURE 3. CHIP ENABLE OUTPUT TIMING WAVEFORMS FOR CDP1800 BASED SYSTEMS
6-51
CDP1826C
o
Dynamic Electrical Specifications At T = -40 to +85 C, V = 5V ±5%, Input t , t = 10ns; C = 50pF and 1 TTL Load
A
DD
R
F
L
LIMITS
CDP1826C
(NOTE 1)
(NOTE 2)
PARAMETER
READ - CYCLE TIMES (FIGURES 4 AND 5)
Address to TPA Setup
MIN
TYP
MAX
UNITS
t
t
100
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ASH
Address to TPA Hold
100
-
500
-
AH
Access from Address Change
TPA Pulse Width
T
-
1000
-
AA
t
t
t
t
t
t
t
200
PAW
AM
Output Valid from MRD
-
-
500
500
150
-
1000
1000
300
-
Access from Chip Select
AC
CEO Delay from TPA
MRD to CEO Delay
Edge
-
CA
75
-
MC
RHZ
SHZ
Output High Z from Invalid MRD
Output High Z from Chip Deselect
NOTES:
-
125
225
-
-
1. Time required by a limit device to allow tor the indicated function.
o
2. Typical values are or T = 25 C and nominal V
.
DD
A
HIGH ORDER
ADDRESS BYTE
A0 - A5
LOW ORDER ADDRESS BYTE
t
t
t
ASH
AA
AH
TPA
t
PAW
MRD
t
t
RHZ
AC
CS1 - CS2
VALID CHIP SELECT
t
t
SHZ
CA
CEO
BUS
t
MC
VALID DATA
HIGH IMPEDANCE
t
AM
FIGURE 4. TIMING WAVEFORMS FOR READ CYCLE 1
6-52
CDP1826C
HIGH ORDER
ADDRESS BYTE
A0 - A5
LOW ORDER ADDRESS BYTE
t
AA
MRD
t
t
RHZ
AC
CS1 • CS2
VALID CHIP SELECT
t
SHZ
HIGH IMPEDANCE
BUS
VALID DATA
t
AM
FIGURE 5. TIMING WAVEFORMS FOR READ-CYCLE 2 (TPA HIGH)
o
Dynamic Electrical Specifications At T = -40 to +85 C, V = 5V ± 5%,Input t , t = 10ns; C = 50pF and 1 TTL Load
A
DD
R
F
L
LIMITS
CDP1826C
(NOTE 1)
(NOTE 2)
PARAMETER
WRITE - CYCLE TIMES (FIGURES 6 AND 7)
Address to TPA Setup, High Byte
Address to TPA Hold
MIN
TYP
MAX
UNITS
t
t
100
100
500
200
700
300
100
400
100
125
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ASH
AH
Address Setup, Low Byte
TPA Pulse Width
T
250
-
ASL
t
t
t
t
t
t
t
PAW
CS
Chip Select Setup
350
200
-
Write Pulse Width
WW
WR
DS
Write Recovery
Data Setup
200
50
50
Data Hold from End of MWR
Data Hold from End of Chip Select
NOTES:
DH1
DH2
1. Time required by a limit device to allow tor the indicated function.
o
2. Typical values are for T = 25 C and nominal V
.
A
DD
6-53
CDP1826C
HIGH ORDER
ADDRESS BYTE
A0 - A5
LOW ORDER ADDRESS BYTE
t
t
t
WR
t
ASH
AH
ASL
TPA
t
PAW
t
WW
MWR
t
CS
CS1 • CS2
VALID CHIP SELECT
t
t
t
DS
DH1, DH2
BUS
DATA IN STABLE
FIGURE 6. TIMING WAVEFORMS FOR WRITE-CYCLE 1
HIGH ORDER
ADDRESS BYTE
A0 - A5
LOW ORDER ADDRESS BYTE
t
ASL
t
WR
t
WW
MWR
t
CS
CS1 • CS2
VALID CHIP SELECT
t
t
t
DS
DH1, DH2
BUS
DATA IN STABLE
FIGURE 7. TIMING WAVEFORMS FOR WRITE-CYCLE 2 (TPA = HIGH)
6-54
CDP1826C
o
Data Retention Specifications At T = -40 to +85 C, see Figure 8
A
LIMITS
TEST
CONDITIONS
CDP1826C
V
V
(NOTE 1)
DR
DD
PARAMETER
Minimum Data Retention
(V)
(V)
MIN
TYP
MAX
UNITS
-
-
-
2
5
-
2.5
V
Voltage
V
DR
Data Retention Quiescent
Current
2.5
-
-
-
25
-
µA
ns
ns
µA
t
t
t
t
DD
Chip Deselect to Data
Retention Time
5
5
5
600
600
1
CDR
RC
Recovery to Normal
Operation Time
-
-
-
V
to V
Rise and
DR
2.5
-
-
DD
Fall Time
t
R, F
NOTE:
o
1. Typical values are or T = 25 C and nominal V
.
DD
A
DATA RETENTION
MODE
V
DD
0.95 V
DD
0.95 V
DD
V
DR
t
t
t
t
RC
CDR
F
R
CS1
V
V
IH
IH
V
V
IL
IL
FIGURE 8. LOW V
DD
DATA RETENTION TIMING WAVEFORMS
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
EUROPE
ASIA
Intersil Corporation
Intersil SA
Mercure Center
100, Rue de la Fusee
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TEL: (32) 2.724.2111
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P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
6-55
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