CA5160M96 [INTERSIL]
4MHz, BiMOS Microprocessor Operational Amplifiers with MOSFET Input/CMOS Output; 为4MHz ，采用BiMOS微处理器与MOSFET的输入运算放大器/ CMOS输出
| 型号： | CA5160M96 |
| 厂家： | 
Intersil |
| 描述： | 4MHz, BiMOS Microprocessor Operational Amplifiers with MOSFET Input/CMOS Output |
| 文件： | 总18页 (文件大小：912K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CA5160
4MHz, BiMOS Microprocessor Operational
Amplifiers with MOSFET Input/CMOS Output
NOT RECOMMENDED FOR NEW DESIGNS
September 1998
Features
Description
• MOSFET Input Stage
12
CA5160 is an integrated circuit operational amplifier that com-
bines the advantage of both CMOS and bipolar transistors on
a monolithic chip. The CA5160 is a frequency compensated
version of the popular CA5130 series. It is designed and guar-
anteed to operate in microprocessor or logic systems that use
+5V supplies.
- Very High Z ; 1.5TΩ (1.5 x 10 Ω) (Typ)
I
- Very Low I ; 5pA (Typ) at 15V Operation
I
2pA (Typ) at 5V Operation
• Common-Mode Input Voltage Range Includes
Negative Supply Rail; Input Terminals Can be
Swung 0.5V Below Negative Supply Rail
Gate-protected P-Channel MOSFET (PMOS) transistors are
used in the input circuit to provide very high input impedance,
• CMOS Output Stage Permits Signal Swing to Either
(or Both) Supply Rails
very low input current, and exceptional speed performance.
The use of PMOS field effect transistors in the input stage
results in common-mode input voltage capability down to 0.5V
below the negative supply terminal, an important attribute in
single supply applications.
• CA5160 Has Full Military Temperature Range
Guaranteed Specifications for V+ = 5V
• CA5160 is Guaranteed to Operate Down to 4.5V for A
OL
A complementary symmetry MOS (CMOS) transistor pair,
capable of swinging the output voltage to within 10mV of
either supply voltage terminal (at very high values of load
impedance), is employed as the output circuit.
• CA5160 is Guaranteed Up to ±7.5V
Applications
• Ground Referenced Single Supply Amplifiers
The CA5160 operates at supply voltages ranging from +5V to
+16V, or ±2.5V to ±8V when using split supplies, and have ter-
minals for adjustment of offset voltage for applications requir-
ing offset-null capability. Terminal provisions are also made to
permit strobing of the output stage. It has guaranteed specifi-
cations for 5V operation over the full military temperature
• Fast Sample-Hold Amplifiers
• Long Duration Timers/Monostables
• Ideal Interface With Digital CMOS
• High Input Impedance Wideband Amplifiers
o
o
range of -55 C to 125 C.
• Voltage Followers (e.g., Follower for Single Supply
D/A Converter)
Ordering Information
• Wien-Bridge Oscillators
• Voltage Controlled Oscillators
• Photo Diode Sensor Amplifiers
• 5V Logic Systems
PART NUMBER
(BRAND)
TEMP.
RANGE ( C)
PKG.
NO.
o
PACKAGE
CA5160E
-55 to 125 8 Ld PDIP
-55 to 125 8 Ld SOIC
E8.3
M8.15
CA5160M96
(5160)
Tape and Reel
• Microprocessor Interface
Pinout
CA5160 (PDIP, SOIC)
TOP VIEW
1
2
3
4
8
7
6
5
OFFSET NULL
INV. INPUT
STROBE
V+
-
+
OUTPUT
OFFSET NULL
NON INV. INPUT
V-
NOTE: CA5160 devices have an on-chip frequency compensation network. Supplementary phase-compensation or frequency roll-off
(if desired) can be connected externally between terminals 1 and 8.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 1924.4
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
3-1
CA5160
Absolute Maximum Ratings
Thermal Information
o
o
Supply Voltage (V+ to V-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16V
Differential Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) to (V- -0.5V)
Input Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1mA
Output Short Circuit Duration (Note 2) . . . . . . . . . . . . . . . . Indefinite
Thermal Resistance (Typical, Note 1)
PDIP Package . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . .
θ
( C/W)
θ
( C/W)
JA
JC
120
165
N/A
N/A
o
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
o
o
o
(SOIC - Lead Tips Only)
Operating Conditions
o
o
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
2. Short circuit may be applied to ground or to either supply.
o
Electrical Specifications T = 25 C, V+ = 5V, V- = 0V, Unless Otherwise Specified
A
CA5160
TYP
2
TEST
CONDITIONS
PARAMETER
Input Offset Voltage
SYMBOL
MIN
-
MAX
UNITS
mV
pA
pA
dB
dB
V
V
V
= 2.5V
= 2.5V
= 2.5V
10
10
15
-
IO
O
Input Offset Current
Input Current
I
V
-
0.1
2
IO
O
I
V
-
I
O
Common Mode Rejection Ratio
CMRR
V
V
= 0 to 1V
70
60
2.5
-
80
CM
CM
= 0 to 2.5V
69
-
Common Mode Input Voltage Range
Power Supply Rejection Ratio
V
+
2.8
-0.5
67
-
lCR
V
-
0
-
V
lCR
PSRR
∆V+ = 1V; ∆V- = 1V
R = ∞
55
95
85
dB
dB
dB
Large Signal Voltage
Gain (Note 3)
V
= 0.1 to 4.1V
= 0.1 to 3.6V
A
117
102
-
O
OL
L
V
-
O
R =10kΩ
L
Source Current
I
V
= 0V
= 5V
= ∞
1.0
3.4
2.2
5
4.0
4.0
-
mA
mA
V
SOURCE
O
Sink Current
I
V
1.0
SINK
O
Maximum Output Voltage
V
+
V
R
R
R
4.99
OM
OUT
L
L
L
V
-
-
0
0.01
-
V
OM
V
+
-
= 10kΩ
= 2kΩ
4.4
4.7
0
V
OM
V
-
0.01
-
V
OM
V
+
-
2.5
3.3
0
V
OM
V
-
-
-
0.01
100
400
V
OM
Supply Current
NOTE:
I
V
= 0V
50
320
µA
µA
SUPPLY
O
I
V
= 2.5V
SUPPLY
O
3. For V+ = 4.5V and V- = GND; V
OUT
= 0.5V to 3.2V at R = 10kΩ.
L
o
o
Electrical Specifications T = -55 C to 125 C, V+ = 5V, V- = 0V, Unless Otherwise Specified
A
CA5160
TYP
3
TEST
PARAMETER
SYMBOL
CONDITIONS
= 2.5V
O
MIN
MAX
UNITS
mV
Input Offset Voltage
Input Offset Current
V
V
-
-
15
10
IO
I
V
= 2.5 V
0.1
nA
IO
O
3-2
CA5160
o
o
Electrical Specifications T = -55 C to 125 C, V+ = 5V, V- = 0V, Unless Otherwise Specified (Continued)
A
CA5160
TEST
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
nA
dB
dB
V
Input Current
I
V
= 2.5V
-
2
15
I
O
Common Mode Rejection Ratio
Common Mode Input Voltage Range
Power Supply Rejection Ratio
CMRR
V
V
= 0 to 1V
60
50
2.5
-
80
75
2.8
-0.5
60
110
100
-
-
CM
= 0 to 2.5V
-
CM
V
+
-
0
lCR
V
-
V
lCR
PSRR
∆V+ = 2V
40
90
75
0.6
0.6
4.99
-
-
dB
dB
dB
mA
mA
V
Large Signal Voltage Gain
(Note 4)
V
= 0.1 to 4.1V
= 0.1 to 3.6V
A
R = ∞
-
O
OL
L
V
R =10kΩ
-
O
L
Source Current
I
V
= 0V
= 5V
5.0
5.0
-
SOURCE
O
Sink Current
I
V
-
SINK
O
Maximum Output Voltage
V
+
V
R = ∞
5
OM
OUT
L
V
-
0
0.01
-
V
OM
V
+
-
R
= 10kΩ
= 2kΩ
4.0
-
4.3
0
V
OM
L
L
V
0.01
-
V
OM
V
+
-
R
2.0
-
2.5
0
V
OM
V
0.01
220
500
V
OM
Supply Current
NOTE:
V
= 0V
I
-
170
410
µA
µA
O
SUPPLY
SUPPLY
V
= 2.5V
I
-
O
4. For V+ = 4.5V and V- = GND; V
OUT
= 0.5V to 3.2V at R = 10kΩ.
L
o
Electrical Specifications T = 25 C, V+ = 15V, V- = 0V, Unless Otherwise Specified
A
CA5160
TEST
PARAMETER
Input Offset Voltage
SYMBOL
CONDITIONS
MIN
-
TYP
MAX
15
30
50
-
UNITS
mV
pA
V
V
V
V
= ±7.5V
6
0.5
IO
S
S
S
Input Offset Current
Input Current
I
= ±7.5V
-
IO
I
= ±7.5V
-
5
pA
I
Large Signal Voltage Gain
A
V
= 10V
P-P
= 2kΩ
50
94
70
10
-
320
110
90
kV/V
dB
OL
O
R
L
-
Common Mode Rejection Ratio
Common Mode Input Voltage Range
Power Supply Rejection Ratio
CMRR
-
dB
V
-0.5 to 12
32
0
V
lCR
PSRR
∆V+ = 1V; ∆V- = 1V
320
µV/V
V
= ±7.5V
S
Maximum Output
Voltage
V
+
-
V
R
= 2kΩ
12
13.3
0.002
15
-
0.01
-
V
V
V
V
OM
OUT
L
L
V
-
14.99
-
OM
V
+
-
R
= ∞
OM
V
0
0.1
OM
3-3
CA5160
o
Electrical Specifications T = 25 C, V+ = 15V, V- = 0V, Unless Otherwise Specified (Continued)
A
CA5160
TEST
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
22
20
10
2
MAX
45
45
15
3
UNITS
mA
Maximum Output
Current
I
I
+ (Source)
- (Sink)
I
V
V
= 0V
12
12
-
OM
OM
O
O
O
= 15V
mA
Supply Current
I+
R
R
= ∞, V = 7.5V
mA
L
L
O
= ∞, V = 0V
-
mA
O
o
Input Offset Voltage Temperature Drift
∆V /∆T
-
8
-
µV/ C
IO
o
Electrical Specifications For Design Guidance, At T = 25 C, V
= ±7.5V, Unless Otherwise Specified
A
SUPPLY
TYPICAL
VALUES
CA5160
±22
1.5
PARAMETER
Input Offset Voltage Adjustment Range
Input Resistance
SYMBOL
TEST CONDITIONS
UNITS
10kΩ Across Terminals 4 and 5 or 4 and 1
mV
TΩ
R
C
I
I
Input Capacitance
f = 1MHz
4.3
pF
Equivalent Input Noise Voltage
e
BW = 0.2MHz, R = 1MΩ
40
µV
N
S
BW = 0.2MHz, R = 10MΩ
50
µV
S
Equivalent Input Noise Voltage
e
R
R
= 100Ω, 1kHz
= 100Ω, 10kHz
72
nV/√Hz
nV/√Hz
MHz
V/µs
µs
N
T
S
30
S
Unity Gain Crossover Frequency
Slew Rate
f
4
SR
10
Transient Response
Rise Time
Overshoot
t
C
C
= 25pF, R = 2kΩ (Voltage Follower)
0.09
10
R
C
L
OS
%
Settling Time (To <0.1%, V = 4V
IN
)
t
= 25pF, R = 2kΩ, (Voltage Follower)
1.8
µs
P-P
S
C
L
Block Diagram
7
V+
8mA
200µA
1.35mA
200µA
(NOTE 5)
NOTE:
0mA
(NOTE 6)
5. Total supply voltage (for indicated voltage
gains) = 15V with input terminals biased so
that Terminal 6 potential is +7.5V above
Terminal 4.
BIAS CKT.
6. Total supply voltage (for indicated voltage
gains) = 15V with output terminal driven to
either supply rail.
+
3
OUTPUT
6
A ≈
V
INPUT
A ≈ 30X
A ≈ 5X
V
V
6000X
2
-
4
V-
C
C
5
1
8
STROBE
COMPENSATION
(WHEN DESIRED)
OFFSET
NULL
3-4
CA5160
Schematic Diagram
7
V+
BIAS CIRCUIT
CURRENT SOURCE
“CURRENT SOURCE
FOR Q AND Q
LOAD” FOR Q
6
7
11
Q
3
Q
1
Q
2
D
D
D
D
1
2
3
4
Q
4
Q
5
Z
8.3V
1
R
1
40kΩ
R
2
5kΩ
INPUT STAGE
SECOND
STAGE
D
5
D
7
D
6
NON-INV.
INPUT
OUTPUT
STAGE
Q
8
3
+
Q
Q
7
6
OUTPUT
2kΩ
2
6
-
30
pF
INV. INPUT
R
3
1kΩ
R
1kΩ
4
Q
12
Q
9
Q
Q
10
11
R
R
5
6
1kΩ
1kΩ
SUPPLEMENTARY
COMP IF DESIRED
5
1
8
4
OFFSET NULL
STROBING
NOTE: Diodes D through D provide gate oxide protection for MOSFET Input Stage.
5
7
Application Information
Circuit Description
Input Stages
Refer to the block diagram of the CA5160 CMOS Operational
Amplifier. The input terminals may be operated down to 0.5V
below the negative supply rail, and the output can be swung
very close to either supply rail in many applications. Conse-
quently, the CA5160 circuit is ideal for single supply operation.
Three class A amplifier stages, having the individual gain
capability and current consumption shown in the block dia-
gram, provide the total gain of the CA5160. A biasing circuit
provides two potentials for common use in the first and sec-
ond stages. Terminals 8 and 1 can be used to supplement the
internal phase compensation network if additional phase com-
pensation or frequency roll-off is desired. Terminals 8 and 4
can also be used to strobe the output stage into a low quies-
cent current state. When Terminal 8 is tied to the negative
supply rail (Terminal 4) by mechanical or electrical means, the
output potential at Terminal 6 essentially rises to the positive
supply rail potential at Terminal 7. This condition of essentially
zero current drain in the output stage under the strobed “OFF”
condition can only be achieved when the ohmic load resis-
tance presented to the amplifier is very high (e.g., when the
amplifier output is used to drive CMOS digital circuits in com-
parator applications).
The circuit of the CA5160 is shown in the schematic diagram.
It consists of a differential input stage using PMOS field effect
transistors (Q , Q ) working into a mirror pair of bipolar tran-
6
7
sistors (Q , Q ) functioning as load resistors together with
9
10
resistors R through R . The mirror pair transistors also func-
3
6
tion as a differential-to-single-ended converter to provide base
drive to the second-stage bipolar transistor (Q ). Offset null-
11
ing, when desired, can be effected by connecting a 100,000Ω
potentiometer across Terminals 1 and 5 and the potentiome-
ter slider arm to Terminal 4.
Cascode-connected PMOS transistors Q , Q , are the
2
4
constant current source for the input stage. The biasing
circuit for the constant current source is subsequently
described. The small diodes D through D provide gate-
5
7
oxide protection against high voltage transients, including
static electricity during handling for Q and Q .
6
7
Second Stage
Most of the voltage gain in the CA5160 is provided by the
second amplifier stage, consisting of bipolar transistor Q
11
and its cascode-connected load resistance provided by
3-5
CA5160
o
PMOS transistors Q and Q . The source of bias potentials T = 25 C when Terminals 2 and 3 are at a common-mode
3
5
A
for these PMOS transistors is described later. Miller Effect potential of +7.5V with respect to negative supply Terminal
compensation (roll off) is accomplished by means of the 4. Figure 1 contains data showing the variation of input
30pF capacitor and 2kΩ resistor connected between the current as a function of common-mode input voltage at
o
base and collector of transistor Q . These internal compo- T = 25 C. These data show that circuit designers can
11
A
nents provide sufficient compensation for unity gain opera- advantageously exploit these characteristics to design
tion in most applications. However, additional compensation, circuits which typically require an input current of less than
if desired, may be used between Terminals 1 and 8.
1pA, provided the common-mode input voltage does not
exceed 2V. As previously noted, the input current is
essentially the result of the leakage current through the gate-
protection diodes in the input circuit and, therefore, a
function of the applied voltage. Although the finite resistance
of the glass terminal-to-case insulator of the metal can
package also contributes an increment of leakage current,
there are useful compensating factors. Because the gate-
protection network functions as if it is connected to Terminal
4 potential, and the metal can case of the CA5160 is also
internally tied to Terminal 4, input terminal 3 is essentially
“guarded” from spurious leakage currents.
Bias-Source Circuit
At total supply voltages, somewhat above 8.3V, resistor R
2
and zener diode Z serve to establish a voltage of 8.3V across
1
the series connected circuit, consisting of resistor R , diodes
1
D through D , and PMOS transistor Q . A tap at the junction
1
4
1
of resistor R and diode D provides a gate bias potential of
1
4
about 4.5V for PMOS transistors Q and Q with respect to
4
5
Terminal 7. A potential of about 2.2V is developed across
diode connected PMOS transistor Q with respect to Terminal
1
7 to provide gate bias for PMOS transistors Q and Q . It
2
3
should be noted that Q is “mirror connected” to both Q and
1
2
10
Q . Since transistors Q , Q and Q are designed to be iden-
o
= 25 C
3
1
2
3
T
A
tical, the approximately 200µA current in Q establishes a
1
similar current in Q and Q as constant current sources for
2
3
both the first and second amplifier stages, respectively.
7.5
5
At total supply voltages somewhat less than 8.3V, zener diode
15V
TO
5V
V+
7
Z
becomes non-conductive and the potential, developed
1
across series connected R , D -D , and Q varies directly
1
1
4
1
2
3
with variations in supply voltage. Consequently, the gate bias
CA5160
PA
6
for Q , Q and Q , Q varies in accordance with supply
4
5
2
3
voltage variations. This variation results in deterioration of the
power supply rejection ration (PSRR) at total supply voltages
below 8.3V. Operation at total supply voltages below about
4.5V results in seriously degraded performance.
2.5
0
4
8
V
IN
5
0V
TO
-10V
V-
Output Stage
-1
0
1
2
3
4
6
7
The output stage consists of a drain loaded inverting ampli-
fier using CMOS transistors operating in the Class A mode.
When operating into very high resistance loads, the output
can be swung within millivolts of either supply rail. Because
the output stage is a drain loaded amplifier, its gain is depen-
dent upon the load impedance. The transfer characteristics
of the output stage for a load returned to the negative supply
INPUT CURRENT (pA)
FIGURE 1. CA5160 INPUT CURRENT vs COMMON MODE
VOLTAGE
Input Current Variation with Temperature
rail are shown in Figure 20. Typical op-amp loads are readily The input current of the CA5160 series circuits is typically
o
driven by the output stage. Because large signal excursions 5pA at 25 C. The major portion of this input current is due to
are nonlinear, requiring feedback for good waveform repro- leakage current through the gate protective diodes in the
duction, transient delays may be encountered. As a voltage input circuit. As with any semiconductor-junction device,
follower, the amplifier can achieve 0.01% accuracy levels, including op amps with a junction-FET input stage, the
o
including the negative supply rail.
leakage current approximately doubles for every 10 C
increase in temperature. Figure 2 provides data on the
typical variation of input bias current as a function of
temperature in the CA5160.
Offset Nulling
Offset voltage nulling is usually accomplished with a 100,000Ω
potentiometer connected across Terminals 1 and 5 and with the In applications requiring the lowest practical input current
potentiometer slider arm connected to Terminal 4. A fine offset and incremental increases in current because of “warm-up”
null adjustment usually can be affected with the slider arm posi- effects, it is suggested that an appropriate heat sink be used
tioned in the mid point of the potentiometer’s total range.
with the CA5160. In addition, when “sinking” or “sourcing”
significant output current the chip temperature increases,
causing an increase in the input current. In such cases, heat-
sinking can also very markedly reduce and stabilize input
current variations.
Input Current Variation with Common Mode Input Voltage
As shown in the Table of Electrical Specifications, the input
current for the CA5160 Series Op Amps is typically 5pA at
3-6
CA5160
Power Supply Considerations
4000
1000
V
= ±7.5V
S
Because the CA5160 is very useful in single-supply applica-
tions, it is pertinent to review some considerations relating to
power-supply current consumption under both single-and
dual-supply service. Figures 4A and 4B show the CA5160
connected for both dual and single-supply operation.
100
10
1
Dual-supply Operation: When the output voltage at Termi-
nal 6 is 0V, the currents supplied by the two power supplies
are equal. When the gate terminals of Q and Q
driven increasingly positive with respect to ground, current
are
8
12
flow through Q (from the negative supply) to the load is
12
increased and current flow through Q (from the positive
supply) decreases correspondingly. When the gate terminals
8
-80 -60 -40 -20
0
20 40 60 80 100 120 140
o
of Q and Q are driven increasingly negative with respect
8
12
TEMPERATURE ( C)
to ground, current flow through Q is increased and current
8
flow through Q is decreased accordingly.
12
FIGURE 2. INPUT CURRENT vs TEMPERATURE
Single Supply Operation: Initially, let it be assumed that the
Input Offset Voltage (V ) Variation with DC Bias vs
IO
Device Operating Life
value of R is very high (or disconnected), and that the input-
L
terminal bias (Terminals 2 and 3) is such that the output termi-
nal (Number 6) voltage is at V+/2, i.e., the voltage-drops
It is well known that the characteristics of a MOSFET device
can change slightly when a DC gate-source bias potential is
applied to the device for extended time periods. The magni-
tude of the change is increased at high temperatures. Users
of the CA5160 should be alert to the possible impacts of this
effect if the application of the device involves extended opera-
tion at high temperatures with a significant differential DC bias
voltage applied across Terminals 2 and 3. Figure 3 shows typ-
ical data pertinent to shifts in offset voltage encountered with
CA5160 devices in metal can packages during life testing. At
lower temperatures (metal can and plastic) for example at
across Q and Q are of equal magnitude. Figure 21 shows
8
12
typical quiescent supply-current vs supply-voltage for the
CA5160 operated under these conditions. Since the output
stage is operating as a Class A amplifier, the supply-current
will remain constant under dynamic operating conditions as
long as the transistors are operated in the linear portion of
their voltage transfer characteristics (see Figure 20). If either
Q or Q are swung out of their linear regions toward cutoff
8
12
(a nonlinear region), there will be a corresponding reduction in
supply-current. In the extreme case, e.g., with Terminal 8
swung down to ground potential (or tied to ground), NMOS
o
85 C, this change in voltage is considerably less. In typical lin-
ear applications where the differential voltage is small and
symmetrical, these incremental changes are of about the
same magnitude as those encountered in an operational
transistor Q is completely cut off and the supply-current to
12
series-connected transistors Q , Q goes essentially to zero.
12
8
The two preceding stages in the CA5160, however, continue
to draw modest supply-current (see the lower curve in Figure
21) even through the output stage is strobed off. Figure 4A
shows a dual-supply arrangement for the output stage that
amplifier employing a bipolar transistor input stage. The 2V
DC
differential voltage example represents conditions when the
amplifier output state is “toggled”, e.g., as in comparator appli-
cations.
can also be strobed off, assuming R = ∞, by pulling the
L
potential of Terminal 8 down to that of Terminal 4.
7
o
= 125 C FOR METAL CAN PACKAGES
T
A
Let it now be assumed that a load-resistance of nominal
value (e.g., 2kΩ) is connected between Terminal 6 and
ground in the circuit of Figure 4B. Let it further be assumed
again that the input terminal bias (Terminals 2 and 3) is such
that the output terminal (Number 6) voltage is V+/2. Since
6
5
4
3
2
DIFFERENTIAL DC VOLTAGE
(ACROSS TERMINALS 2 AND 3) = 2V
OUTPUT STAGE TOGGLED
PMOS transistor Q must now supply quiescent current to
8
both R and transistor Q , it should be apparent that under
L
12
these conditions the supply current must increase as an
inverse function of the R magnitude. Figure 27 shows the
L
voltage drop across PMOS transistor Q as a function of
8
DIFFERENTIAL DC VOLTAGE
(ACROSS TERMINALS 2 AND 3) = 0V
OUTPUT VOLTAGE = V+/2
load current at several supply voltages. Figure 20 shows the
voltage transfer characteristics of the output stage for sev-
eral values of load resistance.
1
0
0
500 1000 1500 2000 2500 3000 3500 4000
TIME (HOURS)
FIGURE 3. TYPICAL INCREMENTAL OFFSET VOLTAGE
SHIFT vs OPERATING LIFE
3-7
CA5160
Wideband Noise
From the standpoint of low-noise performance consider-
ations, the use of the CA5160 is most advantageous in appli-
cations where in the source resistance of the input signal is
on the order of 1MΩ or more. In this case, the total input-
referred noise voltage is typically only 40µV when the test-
circuit amplifier of Figure 5 is operated at a total supply volt-
age of 15V. This value of total input-referred noise remains
essentially constant, even though the value of source resis-
tance is raised by an order of magnitude. This characteristic
is due to the fact that reactance of the input capacitance
becomes a significant factor in shunting the source resis-
tance. It should be noted, however, that for values of source
resistance very much greater than 1MΩ, the total noise volt-
age generated can be dominated by the thermal noise con-
tributions of both the feedback and source resistors.
V+
7
3
2
+
Q
8
OUTPUT
STAGE
6
Q
R
12
L
-
4
8
V-
FIGURE 4A. DUAL POWER-SUPPLY OPERATION
+7.5V
0.01µF
R
S
7
4
V+
7
3
2
+
NOISE
VOLTAGE
OUTPUT
1MΩ
6
-
30.1kΩ
1kΩ
0.01
µF
3
2
+
Q
Q
8
OUTPUT
STAGE
6
-7.5V
R
L
12
-
BW (-3dB) = 200kHz
TOTAL NOISE VOLTAGE
(INPUT REFERRED) = 40µV (TYP)
4
8
FIGURE 5. TEST-CIRCUIT AMPLIFIER (30dB GAIN) USED FOR
WIDEBAND NOISE MEASUREMENTS
FIGURE 4B. SINGLE POWER-SUPPLY OPERATION
FIGURE 4. CA5160 OUTPUT STAGE IN DUAL AND SINGLE
POWER SUPPLY OPERATION
Typical Applications
Voltage Followers
section, illustrates the practical use of the CA5160 in a single-
supply voltage follower application.
Operational amplifiers with very high input resistances, like
the CA5160, are particularly suited to service as voltage
followers. Figure 6 shows the circuit of a classical voltage
follower, together with pertinent waveforms using the
CA5160 in a split supply-configuration.
+7.5V
0.01µF
7
3
+
A voltage follower, operated from a single-supply, is shown in
Figure 7 together with related waveforms. This follower circuit
is linear over a wide dynamic range, as illustrated by the
reproduction of the output waveform in Figure 7B with input
signal ramping. The waveforms in Figure 7C show that the
follower does not lose its input-to-output phase-sense, even
though the input is being swung 7.5V below ground potential.
This unique characteristic is an important attribute in both
operational amplifier and comparator applications. Figure 7C
also shows the manner in which the CMOS output stage
permits the output signal to swing down to the negative supply
rail potential (i.e., ground in the case shown). The digital-to-
analog converter (DAC) circuit, described in the following
10kΩ
6
-
2
4
2kΩ
0.01
µF
-7.5V
25pF
2kΩ
SIMULATED
LOAD
CAPACITANCE
BW (-3dB) = 4MHz
SR = 10V/µs
0.1µF
FIGURE 6A. DUAL SUPPLY FOLLOWER
3-8
CA5160
with series and parallel combinations of 806,000Ω resistors from
the same manufacturing lot.
A single 15V supply provides a positive bus for the CA5160 fol-
lower amplifier and feeds the CA3085 voltage regulator. A “scale-
adjust” function is provided by the regulator output control, set to
a nominal 10V level in this system. The line-voltage regulation
(approximately 0.2%) permits a 9 bit accuracy to be maintained
with variations of several volts in the supply. The flexibility afforded
by the CMOS building blocks simplifies the design of DAC sys-
tems tailored to particular needs.
Error Amplifier in Regulated Power Supplies
The CA5160 is an ideal choice for error-amplifier service in regu-
lated power supplies since it can function as an error-amplifier
when the regulated output voltage is required to approach 0V.
The circuit shown in Figure 9 uses a CA5160 as an error ampli-
fier in a continuously adjustable 1A power supply. One of the key
features of this circuit is its ability to regulate down to the vicinity
of zero with only one DC power supply input.
Top Trace: Output
Bottom Trace: Input
FIGURE 6B. SMALL SIGNAL RESPONSE
An RC network, connected between the base of the output drive
transistor and the input voltage, prevents “turn-on overshoot”, a
condition typical of many operational-amplifier regulator circuits.
As the amplifier becomes operational, this RC network ceases
to have influence on the regulator performance.
NOTE: “Digital-to-Analog Conversion Using the Intersil
CD4007A CMOS IC”, Application Note AN6080.
+15V
0.01µF
3
2
7
4
+
10kΩ
6
-
5
100kΩ
1
OFFSET
ADJUST
Top Trace: Output Signal
Center Trace: Difference Signal 5mV/Div.
Bottom Trace: Input Signal
2kΩ
FIGURE 6C. INPUT-OUTPUT DIFFERENCE SIGNAL SHOWING
SETTLING TIME
0.1µF
FIGURE 6. SPLIT SUPPLY VOLTAGE FOLLOWER WITH
ASSOCIATED WAVEFORMS
FIGURE 7A. SINGLE SUPPLY FOLLOWER
9 Bit CMOS DAC
A typical circuit of a 9 bit Digital-to-Analog Converter (DAC) (see
Note) is shown in Figure 8. This system combines the concepts
of multiple-switch CMOS ICs, a low cost ladder network of dis-
crete metal-oxide-film resistors, a CA5160 op amp connected as
a follower, and an inexpensive monolithic regulator in a simple
single power supply arrangement. An additional feature of the
DAC is that it is readily interfaced with CMOS input logic, e.g.,
10V logic levels are used in the circuit of Figure 8.
The circuit uses an R/2R voltage-ladder network, with the output-
potential obtained directly by terminating the ladder arms at either
the positive or the negative power-supply terminal. Each CD4007A
contains three “inverters”, each “inverter” functioning as a single-
pole double-throw switch to terminate an arm of the R/2R network
at either the positive or negative power-supply terminal. The resis-
tor ladder is an assembly of 1% tolerance metal-oxide film resis-
tors. The five arms requiring the highest accuracy are assembled
0
FIGURE 7B. OUTPUT SIGNAL WITH INPUT SIGNAL RAMPING
3-9
CA5160
Precision Voltage-Controlled Oscillator
The circuit diagram of a precision voltage-controlled oscillator is
shown in Figure 10. The oscillator operates with a tracking error
on the order of 0.02% and a temperature coefficient of
o
0.01%/ C. A multivibrator (A ) generates pulses of constant
1
amplitude (V) and width (T ). Since the output (Terminal 6) of A
(a CA5130) can swing within about 10mV of either supply-rail,
the output pulse amplitude (V) is essentially equal to V+. The
2
1
0
0
average output voltage (E
AVG
= V T /T ) is applied to the non-
2 1
inverting input terminal of comparator A (a CA5160) via an
2
integrating network R , C . Comparator A operates to establish
3
2
2
circuit conditions such that E
= V . This circuit condition is
AVG
1
accomplished by feeding an output signal from Terminal 6 of A
2
through R , D to the inverting terminal (Terminal 2) of A ,
4
4
1
thereby adjusting the multivibrator interval, T .
3
Voltmeter With High Input Resistance
Top Trace: Output
Bottom Trace: Input
The voltmeter circuit shown in Figure 11 illustrates an
application in which a number of the CA5160 characteristics are
FIGURE 7C. OUTPUT-WAVEFORM WITH GROUND-REFERENCE
SINE-WAVE INPUT
exploited. Range-switch SW is ganged between input and
1
output circuitry to permit selection of the proper output voltage
for feedback to Terminal 2 via 10kΩ current-limiting resistor. The
circuit is powered by a single 8.4V mercury battery. With zero
input signal, the circuit consumes somewhat less than 500µA
plus the meter current required to indicate a given voltage. Thus,
at full-scale input, the total supply current rises to slightly more
than 1500µA.
FIGURE 7. SINGLE SUPPLY VOLTAGE FOLLOWER WITH
ASSOCIATED WAVEFORMS (e.g., FOR USE IN
SINGLE-SULLPL D/A CONVERTER; SEE FIGURE 9
IN AN6080)
10V LOGIC INPUTS
+10.010V
14
11
LSB
MSB
9
6
8
3
7
6
6
5
3
4
3
6
2
3
1
10
10
10
2
CD4007A
CD4007A
CD4007A
“SWITCHES”
“SWITCHES”
“SWITCHES”
9
7
13
8
1
5
12
13
8
1
5
12
13
8
1
5
12
(2)
806K
1%
(4)
806K
1%
(8)
806K
1%
4
806K
1%
402K
1%
200K
1%
100K
1%
806K
1%
806K
1%
806K 750K
1% 1%
806K
1%
+15V
+
PARALLELED
RESISTORS
10K
7
3
2
OUTPUT
VOLTAGE
FOLLOWER
6
CA5160
VOLTAGE
REQUIRED RATIO-
MATCH
REGULATOR
-
+15V
62
BIT
1
4
5
2
1
6
Standard
±0.1%
LOAD
1
+10.010V
8
CA3085
2
100K
OFFSET
NULL
3
3
±0.2%
22.1K
1%
7
4
4
±0.4%
2K
REGULATED
VOLTAGE
ADJUST
+
2µF
25V
1K
5
±0.8%
0.001µF
-
0.1µF
3.83K
1%
6 - 9
±1% ABS.
FIGURE 8. 9 BIT DAC USING CMOS DIGITAL SWITCHES AND CA5160
3-10
CA5160
2N6385
POWER DARLINGTON
SHORT-CIRCUIT CURRENT
LIMIT ADJUSTMENT
INPUT 40V
+
1Ω
3
2
OUTPUT
10kΩ
0V
35V
AT 1A
0.2µF
TURN
ON
DELAY
1kΩ
1.5kΩ
1W
2.4kΩ
1W
100kΩ
2N2102
1kΩ
1
1N914
+
56pF
43kΩ
100µF
-
8
2.2kΩ
7
5
10kΩ
+
5µF
+
+
3
2
100µF
25V
2kΩ
CA3086
10 11
-
-
6
2
1
-
1
8.2
kΩ
9
3
5
4
10kΩ
8
7
12
14
13
6
4
4.7kΩ
1kΩ
50kΩ
100kΩ
62kΩ
0.01µF
-
-
Hum and Noise Output <250µV
; Regulation (No Load to Full Load) <0.005%; Input Regulation <0.01%/V
RMS
FIGURE 9. CA5160 VOLTAGE REGULATOR CIRCUIT (0.1 TO 35V AT 1A)
T
T
VCO CONTROL VOLTAGE (V )
I
2
3
(0V - 10V)
V
f
+15V
(SENSITIVITY = 1kHz/V)
o
T
1
D
10K
1M
1
0.01µF
+15V
7
R
100K
5
+15V
7
D
2
100K
0.1
µF
2
3
2
+
-
A1 MULTI-
VIBRATOR
CA5130
A2 COM-
R
6
100K
E
= V T /T
2
6
AVG
1
C
6
1
PARATOR
CA5160
500pF
R
3
1M
-
+
4
3
4
5
C
2
0.01µF
1
0.01µF
R
7
D
D
3
100K
R
182K
1
R
10K
2
D
5
4
D
- D = 1N914
1
5
R 3K
4
FIGURE 10. VOLTAGE CONTROLLED OSCILLATOR
3-11
CA5160
BATTERY
TEST
OFF
ON
300V
100V
30V
300V
100MΩ
100V
30V
3 POSITION
SLIDE SWITCH
9.9
kΩ
+
1.02
MΩ
500
µF
10V
10V
-
M
BATTERY
+9V
BATTERY
0-1mA
SW
1B
22MΩ
SW
1A
3V CAL.
3V
3V
7
4
3
2
500Ω
+
2.7kΩ
820Ω
INPUT
1V
1V
300V
100V
6
CA5160
0.001
µF
300mV
100mV
300mV
100mV
300V
100V
-
200Ω
30V
10V
3V
5
30mV
10mV
30mV
10mV
1
30V
1V CAL.
10V
SW
SW
1D
1V
1C
3V
1V
100kΩ
300mV
100mV
30mV
10mV
9kΩ
9.1kΩ
300mV
100mV
30mV
ZERO
ADJUST
900Ω
100Ω
10kΩ
10mV
FIGURE 11. CA5160A HIGH INPUT RESISTANCE DC VOLTMETER
THRESHOLD
DETECTOR
8.2kΩ
BUFFER
VOLTAGE FOLLOWER
CENTERING
100kΩ
20pF
-7.5V
+7.5V
30kΩ
+7.5V
+7.5V
+7.5V
0.9 - 7pF
1
VOLTAGE-CONTROLLED
CURRENT SOURCE
430pF
C
HIGH
7
0.1µF
FREQ.
6.8MΩ
7
SHAPE
3
+
5
6.2kΩ
3
6
CA3080A
7
4
+
1kΩ
1kΩ
10kΩ
2
3
4 - 60pF
6
2
CA5160
-
-
4
10-80pF
C
3
6
5
CA3080
2
-
C
2
2MΩ
+
-7.5V
4
4.7kΩ
-7.5V
SYMMETRY
EXTERNAL
SWEEPING INPUT
0.1
µF
10kΩ
-7.5V
+7.5V
100kΩ
-7.5V
C
4
2-1N914
50kΩ
4 - 60pF
MAX FREQ
SET
MIN. FREQ. SET
-7.5V
2kΩ
C
5
7.5V
HIGH FREQ
LEVEL
15 - 115pF
6.2kΩ
500Ω
FREQ
10kΩ
500Ω
ADJUST
ADJUST
FIGURE 12A. FUNCTION GENERATOR CIRCUIT
3-12
CA5160
NOTE: A square wave signal modulates the external sweeping
input to produce 1Hz and 1MHz, showing the 1,000,000/1
frequency range of the function generator.
NOTE: The bottom trace is the sweeping signal and the top trace is
the actual generator output. The center trace displays the 1MHz signal
via delayed oscilloscope triggering of the upper swept output signal.
FIGURE 12B. TWO-TONE OUTPUT SIGNAL FROM THE
FUNCTION GENERATOR
FIGURE 12C. TRIPLE-TRACE OF THE FUNCTION GENERATOR
SWEEPING TO 1MHz
FIGURE 12. CA5160 1,000,000/1 SINGLE CONTROL FUNCTION GENERATOR - 1MHz TO 1Hz
+15V
5.1kΩ
1N914
+15V
470pF
7
STAIRCASE
OUTPUT
100
kΩ
100
kΩ
1MΩ
STEP HEIGHT
ADJUST
7
+15V
+15V
4 - 60pF
3
+
7
8.2kΩ
100
kΩ
6
2
3
CA5130
10kΩ
+15V
-
+
6
3
2
2
CA5160
-
1N914
8
6
CA5130
15 - 115pF
FREQ
ADJUST
+
2kΩ
4
-
8
4
1.5
MΩ
4
CHARGE
COMMUTATING
NETWORK
INTEGRATOR
MULTIVIBRATOR
HYSTERESIS SWITCH
MULTIVIBRATOR RETRACE INHIBIT
51kΩ
+15mV TO +10V
100kΩ
FIGURE 13A. STAIRCASE GENERATOR CIRCUIT
3-13
CA5160
Function Generator
A function generator having a wide tuning range is shown in
Figure 12. The adjustment range, in excess of 1,000,000/1, is
accomplished by a single potentiometer. Three operational
amplifiers are utilized: a CA5160 as a voltage follower, a CA3080
as a high-speed comparator, and a second CA3080A as a
STAIRCASE
OUTPUT
2V STEPS
programmable current source. Three variable capacitors C , C ,
1
2
and C shape the triangular signal between 500kHz and 1MHz.
3
COMPARATOR
OSCILLATOR
Capacitors C , C , and the trimmer potentiometer in series with
4
5
C maintain essentially constant (±10%) amplitude up to 1MHz.
5
Staircase Generator
Figure 13 shows a staircase generator circuit utilizing three
CMOS operational amplifiers. Two CA5130s are used; one as a
multivibrator, the other as a hysteresis switch. The third ampli-
fier, a CA5160, is used as a linear staircase generator.
Top Trace: Staircase Output 2V Steps
Center Trace: Comparator
Bottom Trace: Oscillator
FIGURE 13B. STAIRCASE GENERATOR WAVEFORM
FIGURE 13. STAIRCASE GENERATOR CIRCUIT UTILIZING
THREE CMOS OPERATIONAL AMPLIFIERS
10GΩ
+15V
7
1MΩ
+15V
7
10pF
0.1µF
10MΩ
3
2
+
6
2
CA5160
-
10kΩ
6
CA3140
-
4
5
3
+
5.6kΩ
500Ω
1
9.9kΩ
4
560kΩ
100kΩ
9.1kΩ
0.1µF
100Ω
500-0-500µA
M
-15V
-15V
FIGURE 14. CURRENT-TO-VOLTAGE CONVERTER TO PROVIDE A PICOAMMETER WITH ±3pA FULL SCALE DEFLECTION
100kΩ
+15V
+15V
2200pF
30pF
+15V
0.1
µF
0.1µF
7
1MΩ
39kΩ
8.2Ω
3
2
+
7
6
2
CA5160
7
-
-
8
1N914
3
CA3080A
6
2
-
4
6
CA3140
5
+
1MΩ
1
100kΩ
4
3
+
5
4
100kΩ
0.1µF
0.1
µF
8.2kΩ
DROOP
ZERO
ADJUST
39kΩ
OFFSET
VOLTAGE
ADJUST
27kΩ
500µA
STROBE INPUT
9.1kΩ
2kΩ
SAMPLE - 15V
HOLD - 0V
FIGURE 15A. SAMPLE AND HOLD CIRCUIT
3-14
CA5160
SAMPLED
OUTPUT
SAMPLED
OUTPUT
0V-
INPUT
0V-
INPUT
SIGNAL
SAMPLING
PULSES
SAMPLING
PULSE
Top Trace: Sampled Output
Center Trace: Input Signal
Top Trace: Sampled Output
Center Trace: Input
Bottom Trace: Sampling Pulses
Bottom Trace: Sampling Pulses
FIGURE 15C. SAMPLE AND HOLD WAVEFORM
FIGURE 15B. SAMPLE AND HOLD WAVEFORM
FIGURE 15. SINGLE SUPPLY SAMPLE AND HOLD SYSTEM, INPUT 0V TO 10V
Picoammeter Circuit
Figure 14 is a current-to-voltage converter configuration uti- CA3140 output integrator and storage capacitor. The CA3140
lizing a CA5160 and CA3140 to provide a picoampere meter was chosen because of its low output impedance and con-
for ±3pA full-scale meter deflection. By placing Terminals 2 stant gain-bandwidth product. Pulse “droop” during the hold
and 4 of the CA5160 at ground potential, the CA5160 input interval can be reduced to zero by adjusting the 100kΩ bias-
is operated in the “guarded mode”. Under this operating con- voltage potentiometer on the positive input of the CA3140.
dition, even slight leakage resistance present between Ter- This zero adjustment sets the CA3080A output voltage at its
minals 3 and 2 or between Terminals 3 and 4 would result in zero current position. In this sample-and-hold circuit it is
0V across this leakage resistance, thus substantially reduc- essential that the amplifier bias current be reduced to zero to
ing the leakage current.
minimize output signal current during the hold mode. Even
with 320mV at the amplifier bias circuit (Terminal 5) at least
±100pA of output current will be available.
If the CA5160 is operated with the same voltage on input
Terminals 3 and 2 as on Terminal 4, a further reduction in the
input current to the less than 1pA level can be achieved as
shown in Figure 1.
+15V
+15V
R
3
51kΩ
R
1
0.1
OUTPUT
C
51pF
2
100kΩ
7
4
To further enhance the stability of this circuit, the CA5160
can be operated with its output (Terminal 6) near ground,
thus markedly reducing the dissipation by reducing the sup-
ply current to the device.
µF
f = 100kHz
2% THD AT 1.1V
P-P
3
2
+
6
CA5160
-
R
2
C
1
The CA3140 stage serves as a X100 gain stage to provide
the required plus and minus output swing for the meter and
feedback network. A 100-to-1 voltage divider network con-
sisting of a 9.9kΩ resistor in series with a 100Ω resistor sets
the voltage at the 10GΩ resistor (in series with Terminal 3) to
±30mV full-scale deflection. This 30mV signal results from
±3V appearing at the top of the voltage divider network
which also drives the meter circuitry.
100kΩ
10-80pF
2kΩ
2-1N914
0.01µF
680Ω
1
f =
500Ω
2 π √(R || R ) C
R C
3
1
2
1
2
By utilizing a switching technique in the meter circuit and in
the 9.9kΩ and 100Ω network similar to that used in the volt-
meter circuit shown in Figure 11, a current range of 3pA to
1nA full scale can be handled with the single 10GΩ resistor.
FIGURE 16. SINGLE-SUPPLY WEIN BRIDGE OSCILLATOR
Wien Bridge Oscillator
Single Supply Sample-and-Hold System
A simple, single-supply Wien Bridge oscillator using a CA5160
is shown in Figure 16. A pair of parallel-connected 1N914
diodes comprise the gain-setting network which standardizes
the output voltage at approximately 1.1V. The 500Ω potentiom-
eter is adjusted so that the oscillator will always start and the
oscillation will be maintained. Increasing the amplitude of the
Figure 15 shows a single-supply sample-and-hold system
using a CA5160 to provide a high input impedance and an
input-voltage range of 0V to 10V. The output from the input
buffer integrator network is coupled to a CA3080A. The
CA3080A functions as a strobeable current source for the
3-15
CA5160
voltage may lower the threshold level for starting and for sus- output stage in the CA5160. In the Class A mode of CA3600E
taining the oscillation, but will introduce more distortion.
shown, a typical device consumes 20mA of supply current at
15V operation. This arrangement boosts the current-handling
capability of the CA5160 output stage by about 2.5X.
Operation with Output-Stage Power-Booster
The current sourcing and sinking capability of the CA5160 out-
put stage is easily supplemented to provide power-boost capa-
bility. In the circuit of Figure 17, three CMOS transistor-pairs in
a single CA3600 lC array are shown parallel-connected with the
The amplifier circuit in Figure 17 employs feedback to estab-
lish a closed-loop gain of 20dB. The typical large-signal-
bandwidth (-3dB) is 190kHz.
+15V
14
2
11
0.01µF
1MΩ
CA3600 (NOTE)
1µF
7
Q
Q
Q
P3
+
P1
P2
-
3
2
+
680kΩ
13
3
1
6
CA5160
INPUT
500µF
-
8
2kΩ
6
10
12
1µF
4
50Ω
100mW
AT 10%
THD
8
5
Q
Q
Q
N3
N1
N2
A = 20dB
LARGE SIGNAL
BW (-3dB) = 190kHz
7
4
9
20kΩ
NOTE: See File Number 619.
FIGURE 17. CMOS TRANSISTOR ARRAY (CA3600E) CONNECTED AS POWER BOOSTER IN THE OUTPUT STAGE OF THE CA5160.
Typical Performance Curves
150
140
130
120
110
100
90
120
100
V
= ±7.5V
= 25 C
R
= 2kΩ
S
0
L
o
T
A
50
100
150
200
80
60
40
20
0
φ OL
C
L
= 30pF
R
= 2kΩ
L
80
-100
1
2
10
3
4
5
6
7
8
-50
0
50
100
10
10
10
10
10
10
10
o
TEMPERATURE ( C)
FREQUENCY (Hz)
FIGURE 18. OPEN-LOOP VOLTAGE GAIN AND PHASE SHIFT
vs FREQUENCY
FIGURE 19. OPEN-LOOP GAIN vs TEMPERATURE
3-16
CA5160
Typical Performance Curves (Continued)
15
12.5
10
17.5
LOAD RESISTANCE = ∞
SUPPLY VOLTAGE: V+ = 15V, V- = 0V
o
o
T
= 25 C
A
T
= 25 C
A
OUTPUT VOLTAGE BALANCED = V+/2
15
V- = 0
LOAD RESISTANCE = 5kΩ
12.5
2kΩ
1kΩ
10
500Ω
7.5
5
7.5
5
OUTPUT VOLTAGE HIGH = V+
OR LOW = V-
2.5
0
2.5
0
0
2.5
5
7.5
10
12.5
15 17.5
20 22.5
6
8
10
12
14
16
18
GATE VOLTAGE (TERMINALS 4 AND 8) (V)
POSITIVE SUPPLY VOLTAGE (V)
FIGURE 20. VOLTAGE TRANSFER CHARACTERISTICS OF
CMOS OUTPUT STAGE
FIGURE 21. QUIESCENT SUPPLY CURRENT vs SUPPLY
VOLTAGE
14
600
OUTPUT VOLTAGE = V+/2
V+ = 5V, V- = 0V
525
o
T
= -55 C
V- = 0
12
10
8
A
o
450
o
25 C
125 C
375
300
225
150
75
o
o
25 C
125 C
6
4
o
-55 C
2
0
0
0
2
4
6
8
10
12
14
16
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
POSITIVE SUPPLY VOLTAGE (V)
OUTPUT VOLTAGE (V)
FIGURE 22. QUIESCENT SUPPLY CURRENT vs SUPPLY
VOLTAGE
FIGURE 23. SUPPLY CURRENT vs OUTPUT VOLTAGE
8
9
V+ = 5V, V- = 0V
V+ = 5V, V- = 0V
7
8
7
6
5
4
3
2
1
0
6
5
4
o
-55 C
3
o
25 C
o
2
1
0
125 C
1
2
3
4
5
6
7
8
9
10
11
0.1 0.2
0.6 1
2
4
6 8
20 40 80 200
800
LOAD RESISTANCE (kΩ)
LOAD RESISTANCE (kΩ)
FIGURE 24. OUTPUT VOLTAGE SWING vs LOAD RESISTANCE
FIGURE 25. OUTPUT SWING vs LOAD RESISTANCE
3-17
CA5160
Typical Performance Curves (Continued)
8
50
10
V+ = 5V, V- = 0V
7
V- = 0V
o
15V
T
= 25 C
A
10V
V+= 5V
6
5
4
1
0.1
SINK
3
2
0.01
SOURCE
1
0.001
0
0.001
0.01
0.1
1
10
100
-60 -40 -20
0
20 40 60 80 100 120 140
o
TEMPERATURE ( C)
MAGNITUDE OF LOAD CURRENT (mA)
FIGURE 26. OUTPUT CURRENT vs TEMPERATURE
FIGURE 27. VOLTAGE ACROSS PMOS OUTPUT TRANSISTOR
(Q ) vs LOAD CURRENT
8
1000
100
10
50
o
T
V
= 25 C
A
V- = 0V
o
= ±7.5V
S
T
= 25 C
A
V+ = 15V
10V
10
5V
1
0.1
0.01
0.001
1
0.001
0.01
0.1
1
10
100
1
2
3
4
5
1
10
10
10
10
10
MAGNITUDE OF LOAD CURRENT (mA)
FREQUENCY (Hz)
FIGURE 28. VOLTAGE ACROSS NMOS OUTPUT TRANSISTOR
(Q ) vs LOAD CURRENT
FIGURE 29. EQUIVALENT NOISE VOLTAGE vs FREQUENCY
12
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
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3-18
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