CA3304 [INTERSIL]
4-Bit, 25 MSPS, Flash A/D Converters; 4位， 25 MSPS时，Flash A / D转换器
| 型号： | CA3304 |
| 厂家： | 
Intersil |
| 描述： | 4-Bit, 25 MSPS, Flash A/D Converters |
| 文件： | 总11页 (文件大小：119K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CA3304, CA3304A
4-Bit, 25 MSPS,
August 1997
Flash A/D Converters
Features
Description
• CMOS/SOS Low Power with Video Speed (Typ) . . 25mW
The Intersil CA3304 is a CMOS parallel (FLASH) analog-to-
digital converter designed for applications demanding both
low-power consumption and high speed digitization. Digitiz-
ing at 25MHz, for example, requires only about 35mW.
• Parallel Conversion Technique
• Single Power Supply Voltage . . . . . . . . . . . . 3V to 7.5V
• 25MHz Sampling Rate (40ns Conversion Time) at 5V
Supply
The CA3304 operates over a wide, full-scale signal input
voltage range of 0.5V up to the supply voltage. Power
consumption is as low as 10mW, depending upon the clock
frequency selected.
• 4-Bit Latched Three-State Output with Overflow and
Data Change Outputs
1
•
/ LSB Maximum Nonlinearity (A Version)
8
• Inherent Resistance to Latch-Up Due to SOS Process
• Bipolar Input Range with Optional Second Supply
• Wide Input Bandwidth (Typ) . . . . . . . . . . . . . . . . 25MHz
The intrinsic high conversion rate makes the CA3304 types
ideally suited for digitizing high speed signals. The overflow
bit makes possible the connection of two or more CA3304s
in series to increase the resolution of the conversion system.
A series connection of two CA3304s may be used to pro-
duce a 5-bit, 25MHz converter. Operation of two CA3304s in
parallel doubles the conversion speed (i.e., increases the
sampling rate from 25MHz to 50MHz). A data change pin
indicates when the present output differs from the previous,
thus allowing compaction of data storage.
Applications
• High Speed A/D Conversion
• Ultrasound Signature Analysis
• Transient Signal Analysis
• High Energy Physics Research
• General-Purpose Hybrid ADCs
• Optical Character Recognition
• Radar Pulse Analysis
Sixteen paralleled auto-balanced voltage comparators mea-
sure the input voltage with respect to a known reference to
produce the parallel-bit outputs in the CA3304. Fifteen com-
parators are required to quantize all input voltage levels in this
4-bit converter, and the additional comparator is required for
the overflow bit.
• Motion Signature Analysis
• Robot Vision
• RSSI Circuits
Ordering Information
o
PART NUMBER LINEARITY (INL, DNL)
SAMPLING RATE
25MHz (40ns)
25MHz (40ns)
25MHz (40ns)
25MHZ (40ns)
25MHz (40ns)
25MHz (40ns)
TEMP. RANGE ( C)
-40 to 85
PACKAGE
16 Ld PDIP
PKG. NO.
E16.3
CA3304E
CA3304AE
CA3304M
CA3304AM
CA3304D
CA3304AD
±0.25 LSB
±0.125 LSB
±0.25 LSB
±0.125 LSB
±0.25 LSB
±0.125 LSB
-40 to 85
16 Ld PDIP
E16.3
M16.3
M16.3
D16.3
D16.3
-40 to 85
16 Ld SOIC (W)
16 Ld SOIC (W)
16 Ld SBDIP
16 Ld SBDIP
-40 to 85
-55 to 125
-55 to 125
Pinout
CA3304 (SBDIP, PDIP, SOIC)
TOP VIEW
BIT 1 (LSB)
BIT 2
1
2
3
4
5
6
7
8
16 V
DD
15 CLK
BIT 3
14 V
AA
-
BIT 4
13 V
12 V
11 V
10 V
-
REF
REF
IN
DATA CHANGE (DC)
OVERFLOW (OF)
CE2
+
+
AA
9
CE1
V
SS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
File Number 1790.2
4-7
CA3304, CA3304A
Absolute Maximum Ratings
Thermal Information
o
o
DC Supply Voltage Range (V
or V +)
AA
Thermal Resistance (Typical, Note 1)
θ
( C/W)
θ
( C/W)
DD
JA
JC
(Voltage Referenced to V or V - Terminal,
Whichever is More Negative) . . . . . . . . . . . . . . . . . . -0.5V to +8V
Input Voltage Range
SBDIP Package. . . . . . . . . . . . . . . . . . . .
PDIP Package . . . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . . . .
80
90
100
22
N/A
N/A
SS AA
CE1, CE2 Inputs . . . . . . . . . . . . . . . . . . . V -0.5V to V
+0.5V Maximum Junction Temperature
SS
DD
o
Clock, V
REF
+, V
-, V Inputs . . . . . V - -0.5V to V - +0.5V
Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 C
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range (T
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
(SOIC - Lead Tips Only)
REF
IN AA AA
o
DC Input Current, Any Input . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA
o
o
) . . . -65 C to 150 C
STG
o
Operating Conditions
Recommended Supply Voltage Range (V
DD
or V +) . . . . .3V to 7.5V
AA
Recommended V + Voltage Range. . . . . . V
-1V to V
+2.5V
AA
DD
DD
Recommended V - Voltage Range . . . . . . .V -2.5V to V +1V
AA
SS
SS
Operating Temperature
CA3304D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
CA3304E, CA3304M. . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C
o
o
o
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
o
Electrical Specifications T = 25 C, V
+ = 2V, V
DD
= V + = 5V, V - = V
AA AA REF
- = V = GND, f = 25MHz
SS CLK
A
REF
Unless Otherwise Specified
PARAMETER
SYSTEM PERFORMANCE
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Resolution
4
-
-
-
-
-
-
-
-
-
-
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
Input Errors
Integral Linearity
Error
CA3304A
CA3304
CA3304A
CA3304
CA3304A
CA3304
CA3304A
CA3304
±0.1
±0.125
±0.25
±0.125
±0.25
±0.75
±1.0
±0.125
Differential Linearity
Error
±0.1
±0.125
Offset Error
(Unadjusted)
-
-
-
-
Gain Error
(Unadjusted)
±0.75
±1.0
DYNAMIC CHARACTERISTICS (Input Signal Level 0.5dB Below Full Scale)
Conversion Timing Aperture Delay
-
-
-
3
-
-
-
ns
dB
dB
Signal to Noise Ratio, SNR
f
f
= 25MHz, f = 100kHz
IN
23.7
23.6
S
RMS Signal
= 25MHz, f = 5MHz
IN
S
=
RMS Noise
Signal to Noise Ratio, SINAD
f
f
= 25MHz, f = 100kHz
IN
-
-
23.4
22.8
-
-
dB
dB
S
RMS Signal
= 25MHz, f = 5MHz
IN
S
=
RMS Noise + Distortion
Total Harmonic Distortion, THD
f
f
f
f
= 25MHz, f = 100kHz
IN
-
-
-
-
-34.5
-31.0
3.67
3.57
-
-
-
-
dBc
dBc
Bits
Bits
S
S
S
S
= 25MHz, f = 5MHz
IN
Effective Number of Bits, ENOB
= 25MHz, f = 100kHz
IN
= 25MHz, f = 5MHz
IN
ANALOG INPUTS
Input Range
Full Scale Input Range
(Notes 1, 4)
0.5
-
V
V
AA
Input Loading
Input Capacitance
Input Current
-
-
10
-
pF
µA
V
= 2V (Note 2)
150
200
IN
4-8
CA3304, CA3304A
o
Electrical Specifications T = 25 C, V
+ = 2V, V
DD
= V + = 5V, V - = V
AA AA REF
- = V = GND, f = 25MHz
SS CLK
A
REF
Unless Otherwise Specified (Continued)
PARAMETER
Allowable Input Bandwidth
TEST CONDITIONS
(Note 4)
MIN
TYP
25
MAX
UNITS
MHz
-
-
f
/2
CLK
-
-3dB Input Bandwidth
REFERENCE INPUTS
Input Range
40
MHz
V
V
+ Range
- Range
(Note 4)
(Note 4)
V
-+0.5
-
-
-
V
+
V
V
Ω
REF
REF
AA
AA
V
-
V
+-0.5
AA
AA
Input Loading
DIGITAL INPUTS
Digital Input
Resistor Ladder Impedance
V
= 5V, CLK = Low
640
960
IN
Maximum V , Low
IN
CLOCK
(Notes 3, 4)
(Note 4)
-
-
-
0.3 x V
AA
V
V
CE1, CE2
CLOCK
-
0.3 x V
DD
Minimum V , High
IN
(Notes 3, 4)
(Note 4)
0.7 x V
AA
-
-
-
V
CE1, CE2
0.7 x V
-
-
V
DD
Input Leakage, Except CLK
Input Leakage, CLK
V = 0V, 5V
(Note 3)
-
-
±1
µA
µA
±100
±150
DIGITAL OUTPUTS
Digital Outputs
Output Low (Sink) Current
Output High (Source) Current
Three-State Leakage Current
V
= 0.4V
6
-3
-
-
-
-
-
mA
mA
µA
O
V
= 4.6V
O
V
= 0V, 5V
±0.2
±5
O
TIMING CHARACTERISTICS
Conversion Timing
Maximum Conversion Speed
CLK = Square Wave
25
20
35
-
-
MSPS
ns
Auto-Balance Time (φ1)
-
Sample Time (φ2)
Data Valid Delay
Data Hold Time
20
-
-
5000
ns
ns
ns
ns
ns
Output Timing
(Note 4)
(Note 4)
30
25
15
10
40
-
15
-
Output Enable Time
Output Disable Time
-
-
-
POWER SUPPLY CHARACTERISTICS
Device Current, I
Continuous Clock
Continuous φ2
Continuous φ1
Continuous Clock
Continuous φ2
-
-
-
-
-
5.5
0.4
2
-
-
mA
mA
mA
mA
mA
AA
-
Device Current, I
1.5
5
-
DD
V
V
+ = 5V,
10
AA
= CE1 = V - = CLK = GND
AA
SS
V
+ = 7V
Continuous φ1
-
5
20
mA
AA
NOTES:
1. Full scale input range, V
however.
+ - V
REF
-, may be in the range of 0.5V to V + -V - volts. Linearity errors increase at lower full scale ranges,
AA AA
REF
2. Input current is due to energy transferred to the input at the start of the sample period. The average value is dependent on input and V
voltage.
DD
3. The CLK input is a CMOS inverter with a 50kΩ feedback resistor. It operates from the V + and V - supplies. It may be AC-coupled
AA AA
with a 1V
minimum source.
P-P
4. Parameter not tested, but guaranteed by design or characterization.
4-9
CA3304, CA3304A
Pin Descriptions
PIN NUMBER
NAME
Bit 1
Bit 2
Bit 3
Bit 4
DC
DESCRIPTION
1
2
Bit 1 (LSB).
Bit 2.
3
Bit 3.
Output Data Bits
(High = True)
4
Bit 4 (MSB).
Data Change.
Overflow.
5
6
OF
7
CE2
Three-State Output Enable Input, active low. See the Chip Enable Truth Table.
8
V
Digital Ground.
SS
CE1
9
Three-State Output Enable Input, active high. See the Chip Enable Truth Table.
Analog Power Supply, +5V.
10
11
12
13
14
15
16
V
+
AA
V
Analog Signal Input.
IN
V
+
Reference Voltage Positive Input.
Reference Voltage Negative Input.
Analog Ground.
REF
V
-
REF
V
-
AA
CLK
Clock Input.
V
Digital Power Supply, +5V.
DD
CHIP ENABLE TRUTH TABLE
CE1
0
CE2
BIT 1 - BIT 4
Valid
DC, OF
Valid
1
1
0
1
Three-State
Three-State
Valid
X
Three-State
X = Don't Care
TABLE 1. OUTPUT CODE TABLE
INPUT VOLTAGE (V)
OUTPUT CODE
CODE
DESCRIPTION
V
V
+ = 1V
- = -1V
1.6V
0V
2V
0V
3.2V
0V
4.8V
0V
DECIMAL
COUNT
REF
REF
OF
0
0
0
•
B4
0
0
0
•
B3
0
0
0
•
B2
0
0
1
•
B1
0
1
0
•
Zero
-1.000
0
0.1
0.2
•
0
0
0.2
0.4
•
0
0.3
0.6
•
0
1
2
•
1 LSB
-0.875
0.125
2 LSB
-0.750
0.250
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
/ Full Scale -1 LSB
2
-0.125
0.7
0.8
0.9
•
0.875
1.000
1.125
•
1.4
1.6
1.8
•
2.1
2.4
2.7
•
0
0
0
•
0
1
1
•
1
0
0
•
1
0
0
•
1
0
1
•
7
8
9
•
1
/ Full Scale
2
0
/
Full Scale +1 LSB
0.125
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Full Scale -1 LSB
Full Scale
0.750
0.875
1.000
0.125
1.4
1.5
1.6
0.1
1.750
1.875
2.000
0.125
2.8
3.0
3.2
0.2
4.2
4.5
4.8
0.3
0
0
1
1
1
1
1
1
1
1
1
1
0
1
1
14
15
31
Overflow
Step Size
NOTE:
1. The voltages listed are the ideal centers of each output code shown as a function of its associated reference voltage See Ideal Transfer
1
Curve Figure 6. The output code should exist for an input equal to the ideal center voltage ± / of the step size.
2
4-10
CA3304, CA3304A
Functional Diagram
THREE-STATE
DRIVERS
φ2
OUTPUT
REGISTER
V
+
V
DD
AA
DATA
CHANGE
10
16
5
D Q
CLK
φ1
φ1
φ1
φ2 φ1
V
IN
COUNT
16
11
D
Q
1
/ R
2
6
4
3
OVERFLOW
LATCH
16
D Q
CLK
12
CAB #16
†
V
+
R
REF
BIT 4
D Q
CLK
COUNT
ENCODER
LOGIC
ARRAY
R
R
8
D
Q
BIT 3
D Q
CLK
LATCH
8
CAB #8
†
2
1
BIT 2
D Q
CLK
COUNT
1
R
BIT 1 (LSB)
D Q
CLK
V
-
D
Q
REF 1
/ R
2
LATCH
0
13
CAB COMPARATOR #1
†
50kΩ
CLOCK
15
9
7
CE1
CE2
φ1 (AUTO BALANCE)
14
8
φ2 (SAMPLE UNKNOWN)
V
-
V
SS
AA
†Cascaded Auto Balance (CAB)
NOTE: CE1 and CE2 inputs and data outputs have standard CMOS protection networks to V
and V . Analog inputs and clock have
SS
DD
standard CMOS protection networks to V + and V -.
AA AA
Timing Diagrams
DATA SHIFTED INTO
OUTPUT REGISTERS
COMPARATOR DATA
LATCHED
φ 1
AUTO
φ 2
AUTO
BALANCE
AUTO
BALANCE
1
BALANCE
CLOCK
SAMPLE 1
SAMPLE 2
SAMPLE 3
0
1
0
DATA VALID 0
DATA VALID 1
DATA VALID 2
B1 - B4, DC & OF
t
HO
t
D
FIGURE 1. TIMING DIAGRAM
CE1
CE2
BITS 1-4
DC, OF
t
t
t
EN
DIS
EN
t
DIS
HIGH
HIGH
IMPEDANCE
IMPEDANCE
HIGH
IMPEDANCE
FIGURE 2. OUTPUT ENABLE/DISABLE TIMING
4-11
CA3304, CA3304A
Timing Diagrams (Continued)
SAMPLE ENDS
SAMPLE ENDS
φ 1
φ 1
φ 1
φ 1
φ 2
φ 2
φ 2
φ 2
CLOCK
CLOCK
t
t
D
D
OUTPUT
OLD DATA
NEW DATA
OUTPUT
OLD DATA
OLD DATA + 1
NEW DATA
FIGURE 3A.
FIGURE 3B.
With 1 as standby state (indefinite standby, double pulse needed)
φ
φ
With 2 as standby state (fastest method, but standby limited to 5µs
maximum)
SAMPLE ENDS
CLOCK
φ 1
φ 1
φ 2
φ 2
φ 2
t
D
OUTPUT
OLD DATA
INVALID DATA
NEW DATA
FIGURE 3C.
φ
With 2 as standby state (indefinite standby, lower power than 3B)
FIGURE 3. PULSE-MODE TIMING DIAGRAMS
Typical Performance Curves
8
7
40
38
36
34
32
6
5
4
30
28
3
2
-50
-25
0
25
50
75
100
5
10
15
20
25
30
o
TEMPERATURE ( C)
f
(MHz)
S
FIGURE 4. DATA DELAY vs TEMPERATURE
FIGURE 5. DEVICE CURRENT vs SAMPLE FREQUENCY
4-12
CA3304, CA3304A
Typical Performance Curves (Continued)
0.10
0.25
0.22
0.20
0.17
0.15
0.12
0.10
0.07
0.05
0.02
0.00
0.09
0.08
0.07
INL
0.06
0.05
0.04
0.03
0.02
0.01
0.00
INL
DNL
DNL
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
1
2
3
4
5
o
TEMPERATURE ( C)
REFERENCE VOLTAGE (V)
FIGURE 6. NON-LINEARITY vs TEMPERATURE
FIGURE 7. NON-LINEARITY vs REFERENCE VOLTAGE
0.50
4.00
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
3.80
3.60
3.40
3.20
3.00
2.80
2.60
2.40
INL
2.20
2.00
DNL
15
20
25
30
35
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
o
f
(MHz)
TEMPERATURE ( C)
S
FIGURE 8. NON-LINEARITY vs SAMPLE FREQUENCY
FIGURE 9. EFFECTIVE BITS vs TEMPERATURE
7.00
6.80
6.60
6.40
6.20
4.00
3.80
3.60
3.40
3.20
3.00
2.80
2.60
2.40
6.00
5.80
5.60
5.40
5.20
5.00
2.20
2.00
0
1
2
3
4
5
6
7
8
9
10
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
o
f (MHz)
I
TEMPERATURE ( C)
FIGURE 10. EFFECTIVE BITS vs INPUT FREQUENCY
FIGURE 11. DEVICE CURRENT vs TEMPERATURE
4-13
CA3304, CA3304A
Typical Performance Curves (Continued)
27Ω
+5V SUPPLY
CA3304
V
+
V
AA
DD
CE2
+
+
0.1µF
CER
4.7µF TAN
4.7µF TAN
+
0.1µF
CER
4.7µF TAN
V
+
2V REFERENCE
REF
0.1µF
CER
DC, OF,
B1-B4
OUTPUT DATA
REMOTE
2V INTO 50Ω
CMOS CLOCK
SOURCE
V
CLK
IN
SOURCE
V
V
-
CE1
REF
-
V
50Ω
AA
SS
ANALOG
GROUND
DIGITAL
GROUND
FIGURE 12A. TYPICAL CA3304 UNIPOLAR CIRCUIT CONFIGURATION
27Ω
+5V SUPPLY
CA3304
V
+
V
AA
DD
CE2
+
0.1µF
CER
4.7µF TAN
+
0.1µF
CER
4.7µF TAN
V
+
+1V REFERENCE
REF
0.1µF
CER
DC, OF,
B1 - B4
REMOTE
±1V INTO 50Ω
SOURCE
OUTPUT DATA
IN914
V
V
IN
CMOS CLOCK
SOURCE
-1V
REFERENCE
CLK
-
REF
0.1µF
CER
10K
CE1
50Ω
0.001µF
-1.5V SUPPLY
V
SS
V
-
AA
0.1µF
CER
4.7µF TAN
ANALOG
GROUND
DIGITAL
GROUND
FIGURE 12B. TYPICAL CA3304 BIPOLAR CIRCUIT CONFIGURATION
FIGURE 12.
4-14
CA3304, CA3304A
Continuous Clock Operation
Description
One complete conversion cycle can be traced through the
CA3304 via the following steps. (Refer to timing diagram
Figure 3). The rising edge of the clock input will start a
“sample” phase. During this entire “High” state of the clock,
the 16 comparators will track the input voltage and the 16
latches will track the comparator outputs. At the falling edge
of the clock, all 16 comparator outputs are captured by the
16 latches. This ends the “sample” phase and starts the
“auto balance” phase for the comparators. During this “Low”
state of the clock the output of the latches propagates
through the decode array and a 6-bit code appears at the D
inputs of the output registers. On the next rising edge of the
clock, this 6-bit code is shifted into the output registers and
Device Operation
A sequential parallel technique is used by the CA3304
converter to obtain its high speed operation. The sequence
consists of the “Auto Balance” phase and the “Sample
Unknown” phase (Refer to the circuit diagram). Each
conversion takes one clock cycle (see Note). The “Auto
Balance” (φ1) occurs during the Low period of the clock
cycle, and the “Sample Unknown” (φ2) occurs during the
High period of the clock cycle.
NOTE: This device requires only a single-phase clock. The terminology
of φ1 and φ2 refers to the High and Low periods of the same clock.
During the “Auto Balance” phase, a transmission-gate switch
is used to connect each of 16 commutating capacitors to
their associated ladder reference tap. Those tap voltages will
be as follows:
appears with time delay t as valid data at the output of the
D
three-state drivers. This also marks the start of a new
“sample” phase, thereby repeating the conversion process
for this next cycle.
V
(N) = [(V
REF
/16) x N] - [V
/(2 x 16)]
REF
TAP
Pulse Mode Operation
= V
REF
[(2N - 1)/32],
For sampling high speed nonrecurrent or transient data, the
converter may be operated in a pulse mode in one of three
ways. The fastest method is to keep the converter in the
Sample Unknown phase, φ2, during the standby state. The
device can now be pulsed through the Auto Balance phase
with as little as 20ns. The analog value is captured on the
leading edge of φ1 and is transferred into the output registers
on the trailing edge of φ1. We are now back in the standby
state, φ2, and another conversion can be started within
20ns, but not later than 5µs due to the eventual droop of the
commutating capacitors. Another advantage of this method
is that it has the potential of having the lowest power drain.
The larger the time ratio between φ2 and φ1, the lower the
power consumption. (See Timing Diagram Figure 3A).
Where:
V
V
(N) = Reference ladder tap voltage at point N,
= Voltage across V
TAP
REF
- to V
+, and
REF
REF
N = Tap number (1 through 16).
The other side of the capacitor is connected to a single-
stage inverting amplifier whose output is shorted to its input
by a switch. This biases the amplifier at its intrinsic trip point,
which is approximately (V
charge to their associated tap voltages, priming the circuit for
the next phase.
- V )/2. The capacitors now
DD
SS
In the “Sample Unknown” phase, all ladder tap switches are
opened, the comparator amplifiers are no longer shorted,
and V is switched to all 16 capacitors. Since the other end
IN
The second method uses the Auto Balance phase, φ1, as
the standby state. In this state the converter can stay
indefinitely waiting to start a conversion. A conversion is
performed by strobing the clock input with two φ2 pulses.
The first pulse starts a Sample Unknown phase and
captures the analog value in the comparator latches on the
trailing edge. A second φ2 pulse is needed to transfer the
date into the output registers. This occurs on the leading
edge of the second pulse. The conversion now takes place
in 40ns, but the repetition rate may be as slow as desired.
The disadvantage to this method is the slightly higher device
dissipation due to the low ratio of φ2 to φ1. (See Timing
Diagram Figure 3B).
of the capacitor is now looking into an effectively open cir-
cuit, any voltage that differs from the previous tap voltage will
appear as a voltage shift at the comparator amplifiers. All
comparators whose tap voltages were lower than V will
IN
drive the comparator outputs to a “low” state. All compara-
tors whose tap voltages were higher than V will drive the
IN
comparator outputs to a “high” state. A second, capacitor-
coupled, auto-zeroed amplifier further amplifies the outputs.
The status of all these comparator amplifiers are stored at the
end of this phase (φ2), by a secondary latching amplifier stage.
Once latched, the status of the 16 comparators is decoded by
a 16 to 5 bit decode array and the results are clocked into a
storage register at the rising edge of the next φ2.
For applications requiring both indefinite standby and lowest
power, standby can be in the φ2 (Sample Unknown) state
with two φ1 pulses to generate valid data (see Figure 3C).
The conversion process now takes 60ns. [Note that the
If the input is greater than 31/32 x V
, the overflow output
REF
will go “high”. (The bit outputs will remain high). If the output
differs from that of the previous conversion, the data change
output will go “high”.
above numbers do not include the t (Output Delay) time.]
D
Increased Accuracy
A three-state buffer is used at the output of the 7 storage
registers which are controlled by two chip-enable signals.
CE1 will independently disable B1 through B4 when it is in a
high state. CE2 will independently disable B1 through B4
and the OF and DC buffers when it is in the low state.
In most case the accuracy of the CA3304 should be
sufficient without any adjustments. In applications where
accuracy is of utmost importance, two adjustments can be
made to obtain better accuracy; i.e., offset trim and gain trim.
4-15
CA3304, CA3304A
Offset Trim
Digital Input And Output Levels
In general offset correction can be done in the preamp The clock input is a CMOS inverter operating from and with
circuitry by introducing a DC shift to V or by the offset trim logic input levels determined by the V supplies. If V + or
IN
AA
AA
of the op amp. When this is not possible the V
- input can
V
- are outside the range of the digital supplies, it may be
REF
AA
necessary to level shift the clock input to meet the required
30% to 70% of V input swing. Figure 12B shows an exam-
be adjusted to produce an offset trim.
AA
The theoretical input voltage to produce the first transition is
ple for a negative V -.
AA
1
/ LSB. The equation is as follows:
2
An alternate way of driving the clock is to capacitively couple
1
1
V
(0 to 1 transition) = / LSB = / (V
/16)
REF
IN
2
2
the pin from a source of at least 1V
. An internal 50kΩ
P-P
= V
/32.
feedback resistor will keep the DC level at the intrinsic trip
point. Extremely non-symmetrical clock waveforms should
be avoided, however.
REF
Adjust offset by applying this input voltage and adjusting the
- voltage or input amplifier offset until an output code
V
REF
alternating between 0 and 1 occurs.
The remaining digital inputs and outputs are referenced to
V
and V . If TTL or other lower voltage sources are to
DD
SS
Gain Trim
drive the CA3304, either pull-up resistors or CD74HCT
In general the gain trim can also be done in the preamp circuitry
by introducing a gain adjustment for the op amp. When this is
not possible, then a gain adjustment circuit should be made to
series “QMOS” buffers are recommended.
5-Bit Resolution
adjust the reference voltage. To perform this trim, V should be
set to the 15 to overflow transition. That voltage is / LSB less
2
To obtain 5-bit resolution, two CA3304s can be wired together.
Necessary ingredients include an open-ended ladder net-
work, an overflow indicator, three-state outputs, and chip-
enable controls - all of which are available on the CA3304.
IN
1
than V
+ and is calculated as follows:
REF
V
(15 to 16 transition) = V
- V
/32
lN
REF
REF
(31/32).
The first step for connecting a 5-bit circuit is to totem-pole
the ladder networks, as illustrated in Figure 13. Since the
absolute-resistance value of each ladder may vary, external
trim of the mid-reference voltage may be required.
= V
REF
To perform the gain trim, first do the offset trim and then
apply the required V for the 15 to overflow transition. Now
IN
+ until that transition occurs on the outputs.
adjust V
REF
The overflow output of the lower device now becomes the
fifth bit. When it goes high, all counts must come from the
upper device. When it goes low, all counts must come from
the lower device. This is done simply by connecting the
lower overflow signal to the CE1 control of the lower A/D
converter and the CE2 control of the upper A/D converter.
The three-state outputs of the two devices (bits 1 through 4)
are now connected in parallel to complete the circuitry.
Layout, Input And Supply Considerations
The CA3304 should be mounted on a ground-planed,
printed-circuit board, with good high-frequency decoupling
capacitors mounted as close as possible. If the supply is
noisy, decouple V + with a resistor as shown in Figure 12A.
AA
The CA3304 outputs current spikes to its input at the start of
the auto-balance and sample clock phases.
A low
impedance source, such as a locally-terminated 50Ω coax
cable, should be used to drive the input terminal. A fast-
settling buffer such as the HA-5033, HA-5242, or CA3450
Definitions
Dynamic Performance Definitions
should be used if the source is high impedance. The V
REF
terminals also have current spikes, and should be well
bypassed.
Fast Fourier Transform (FFT) techniques are used to evaluate
the dynamic performance of the CA3304. A low distortion sine
wave is applied to the input, it is sampled, and the output is
stored in RAM. The data is then transformed into the fre-
quency domain with a 4096 point FFT and analyzed to evalu-
ate the dynamic performance of the A/D. The sine wave input
to the part is -0.5dB down from full scale for all these tests.
Care should be taken to keep digital signals away from the
analog input, and to keep digital ground currents away from
the analog ground. If possible, the analog ground should be
connected to digital ground only at the CA3304.
Bipolar Operation
Signal-to-Noise (SNR)
The CA3304, with separate analog (V +, V -) and digital
AA AA
SNR is the measured RMS signal to RMS noise at a speci-
fied input and sampling frequency. The noise is the RMS
sum of all of the spectral components except the fundamen-
tal and the first five harmonics.
(V , V ) supply pins, allows true bipolar or negative input
DD SS
operation. The V - pin may be returned to a negative
AA
supply (observing maximum voltage ratings to V + or V
AA DD
and recommended rating to V ), thus allowing the V
SS REF
-
potential also to be negative. Figure 12B shows operation
Signal-to-Noise + Distortion Ratio (SINAD)
with an input range of -1V to +1V. Similarly, V + and
AA
+ could be maintained at a higher voltage than V
SINAD is the measured RMS signal to RMS sum of all other
spectral components below the Nyquist frequency excluding DC.
V
,
REF
for an input range above the digital supply.
DD
4-16
CA3304, CA3304A
Effective Number of Bits (ENOB)
+5V
V
+
DC
OF
NC
NC
AA
The effective number of bits (ENOB) is derived from the
SINAD data. ENOB is calculated from:
V
DD
+FULL
SCALE
REF.
B4
V
V
+
-
REF
IN
ENOB = (SINAD - 1.76 + V
CORR
)/6.02,
B3
V
V
B2
REF
where:
V
= 0.5dB.
CORR
-
B1
AA
V
CE1
CE2
Total Harmonic Distortion (THD)
SS
CLK
CLOCK
INPUT
THD is the ratio of the RMS sum of the first 5 harmonic
components to the RMS value of the measured input signal.
BUFFER
INPUT
1K
CA3304
ADJUST
CENTER
NC
+5V
CLK
DC
OF
Operating and Handling Considerations
B5 MSB
V
+
AA
V
V
V
HANDLING
DD
B4
B4
B3
B2
B1
+
-
B3
REF
IN
All inputs and outputs of CMOS devices have a network for
electrostatic protection during handling. Recommended han-
dling practices for CMOS devices are described in
lCAN-6525. “Guide to Better Handling and Operation of
CMOS Integrated Circuits.”
B2
V
V
B1
REF
-
CE1
CE2
AA
+5V
V
SS
CA3304
OPERATING
FIGURE 13. TYPICAL CA3304 5-BIT CONFIGURATION
Operating Voltage
During operation near the maximum supply voltage limit, care
should be taken to avoid or suppress power supply turn-on
and turn-off transients, power supply ripple, or ground noise;
any of these conditions must not cause the power supply
voltages to exceed the absolute maximum rating.
OVERFLOW
15
14
13
12
11
10
9
Input Signals
To prevent damage to the input protection circuit, input signals
should never be greater than V
or V + nor less than V
DD
AA SS
or V - (depending upon which supply the protection network
AA
is referenced. See Maximum Ratings.). Input currents must
not exceed 20mA even when the power supply is off.
8
7
6
5
4
3
Unused Inputs
2
1
0
A connection must be provided at every input terminal. All
unused input terminals must be connected to either V
or
DD
V
, whichever is appropriate.
SS
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
Output Short Circuits
INPUT VOLTAGE
Shorting of outputs to any supply potential may damage
CMOS devices by exceeding the maximum device dissipation.
FIGURE 14. IDEAL TRANSFER CURVE
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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4-17
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