AD7545_01_技术文档

AD7545

TM

Data Sheet

May 2001

File Number 3108.3

12-Bit, Buffered, Multiplying CMOS DAC

Features

The AD7545 is a low cost monolithic 12-bit, CMOS

multiplying DAC with on-board data latches. Data is loaded

• 12-Bit Resolution

• Low Gain T.C. 2ppm/ C (Typ)

itle

o

D75 in a single 12-bit wide word which allows interfacing directly

• Fast TTL/CMOS Compatible Data Latches

• Single +5V to +15V Supply

• Low Power

to most 12-bit and 16-bit bus systems. Loading of the input

)

latches is under the control of the CS and WR inputs. A logic

low on these control inputs makes the input latches

transparent allowing direct unbuffered operation of the DAC.

bjec

2-

t,

ffer

• Low Cost

Part Number Information

,

Pinout

TEMP.

PKG.

NO.

o

ltip

ng

PART NUMBER RANGE ( C)

PACKAGE

20 Ld PDIP

AD7545

(PDIP)

TOP VIEW

AD7545JN

AD7545KN

0 to 70

E20.3

OS

C)

1

2

OUT 1

AGND

DGND

DB11 (MSB)

DB10

20

19

18

R

V

FB

utho

)

eyw

s

REF

DD

Functional Diagram

3

V

R

FB

4

17 WR

16 CS

20

5

AD7545

DB9

DB0 (LSB)

6

15

14

13

12

tersi

R

DB1

DB2

DB3

DB8

7

1

2

OUT1

12-BIT

V

REF

19

8

DB7

MULTIPLYING DAC

rpor

on,

ico

AGND

DB6

9

12

DB5

10

11 DB4

18

3

17

16

V

WR

CS

DD

ucto

INPUT DATA LATCHES

12

DGND

ltip

ng,

L,

DB11 - DB0

(PINS 4 - 15)

OS

reato

)

OCI

O

fmar

ge

de

seO

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

AD7545

Absolute Maximum Ratings

Thermal Information

o

Supply Voltage (V

to DGND). . . . . . . . . . . . . . . . . . . -0.3V, +17V

Thermal Resistance (Typical, Note 1)

θ

( C/W)

DD

Digital Input Voltage to DGND . . . . . . . . . . . . . . . . -0.3V, V

JA

+0.3V

DD

PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

80

o

V

, V to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V

RFB REF

Maximum Junction Temperature (PDIP Package) . . . . . . . . .150 C

o

V

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V, V

+0.3V

PIN1

DD

Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C

o

AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V, V

Operating Conditions

o

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 70 C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θ is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

Electrical Specifications

T

= See Note 2, V

= +10V, V

= 0V, AGND = DGND, Unless Otherwise Specified

OUT1

A

REF

V

= +5V (NOTE 7)

V

= +15V (NOTE 7)

DD

PARAMETER

STATIC PERFORMANCE

Resolution

TEST CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

12

-

12

-

Bits

LSB

Relative Accuracy

J

2

K

J

-

1

4

-

1

Differential Nonlinearity

10-Bit Monotonic T

12-Bit Monotonic T

to T

-

4

MIN

MAX

K

J

-

1

-

1

MAX

Gain Error

(Using Internal RFB)

DAC Register Loaded with

1111 1111 1111

-

20

-

25

K

Gain Error is Adjustable

Using the Circuits of

-

10

-

15

LSB

Figures 5 and 6 (Note 3)

o

Gain Temperature Coefficient

∆Gain/∆Temperature

Typical Value is 2ppm/ C for

-

0.015

-

5

0.03

50

-

0.01

-

10

0.02

50

ppm/ C

V

= +5V (Note 4)

DD

DC Supply Rejection

∆Gain/∆V

DD

∆V

=

5%

%

DD

Output Leakage Current at

OUT1

J, K

DB0 - DB11 = 0V; WR,

CS = 0V (Note 2)

nA

DYNAMIC CHARACTERISTICS

1

Current Settling Time

To

/

LSB, OUT1 LOAD = 100Ω,

-

2

-

2

µs

2

DAC Output Measured fromFalling

Edge of WR, CS = 0V (Note 4)

Propagation Delay from Digital Input

OUT1 LOAD = 100Ω,

300

250

ns

Change to 90% of Final Analog Output

Digital to Analog Glitch Impulse

AC Feedthrough at OUT1

C

= 13pF (Notes 4 and 5)

EXT

REF

V

= AGND

-

400

5

-

250

5

-

nV/s

=

10V, 10kHz Sinewave

mV

P-P

ANALOG OUTPUTS

Output Capacitance

C

DB0 - DB11 = 0V,

WR, CS = 0V (Note 4)

-

70

-

70

pF

OUT1

DB0 - DB11 = V

,

200

pF

DD

WR, CS = 0V (Note 4)

2

AD7545

Electrical Specifications

T

= See Note 2, V

= +10V, V

= 0V, AGND = DGND, Unless Otherwise Specified (Continued)

OUT1

A

REF

V

= +5V (NOTE 7)

V

= +15V (NOTE 7)

DD

PARAMETER

REFERENCE INPUT

TEST CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

Input Resistance (Pin 19 to GND)

Input Resistance

TC = -300ppm/ C (Typ)

7

-

7

-

kΩ

o

Typical Input Resistance = 11kΩ

25

DIGITAL INPUTS

Input High Voltage, V

IH

2.4

-

13.5

1.5

10

V

Input Low Voltage, V

-

0.8

10

7

-

IL

Input Current, I

V

= 0 or V

DD

(Note 6)

1

-

1

-

µA

pF

IN

Input Capacitance

DB0 -

DB11

= 0 (Note 4)

7

IN

WR, CS

V

= 0 (Note 4)

-

20

-

20

pF

IN

SWITCHING CHARACTERISTICS (Note 4)

Chip Select to Write Setup Time, t

See Figure 1

380

0

200

-

200

0

120

-

ns

CS

Chip Select to Write Hold Time, t

CH

Write Pulse Width, t

WR

t

≥ t

, t

≥ 0, See Figure 1

400

210

10

175

100

-

240

120

10

100

60

-

CS

WR CH

Data Setup Time, t

DS

See Figure 1

-

Data Hold Time, t

DH

POWER SUPPLY CHARACTERISTICS

All Digital Inputs V or V

I

-

2

500

-

2

500

-

mA

µA

DD

IL

IH

All Digital Inputs 0V or V

100

10

100

10

DD

All Digital Inputs 0V or V

NOTES:

o

2. Temperature Ranges as follows: J, K versions:

o

0 C to 70 C

T

= 25 C for TYP Specifications. MIN and MAX are measured over the specified operating range.

A

3. This includes the effect of 5ppm maximum gain TC.

4. Parameter not tested. Parameter guaranteed by design, simulation, or characterization.

5. DB0 - DB11 = 0V to V

or V

to 0V.

6. Logic inputs are MOS gates. Typical input current (25 C) is less than 1nA.

DD

o

7. Typical values are not guaranteed but reflect mean performance specification. Specifications subject to change without notice.

Timing Diagrams

t

CH

V

0

V

t

DD

CHIP

SELECT

CHIP

SELECT

CS

t

CS

t

0

V

WR

DD

WRITE

0

t

DH

t

DS

V

0

V

0

DD

DATA IN

(DB0 - DB11)

DATA VALID

(DB0 - DB11)

FIGURE 1A. TYPICAL WRITE CYCLE

FIGURE 1B. PREFERRED WRITE CYCLE

FIGURE 1. WRITE CYCLE TIMING DIAGRAM

3

AD7545

Circuit Information - Digital Section

MODE SELECTION

HOLD MODE:

Figure 4 shows the digital structure for one bit. The digital

signals CONTROL and CONTROL are generated from CS

and WR.

WRITE MODE:

CS and WR low, DAC responds Either CS or WR high, data bus

to data bus (DB0 - DB11) inputs (DB0 - DB11) is locked out; DAC

holds last data present when WR

or CS assumed high state.

TO AGND SWITCH

NOTES:

8. V

9. V

= +5V; t = t = 20ns.

r f

DD

TO OUT1 SWITCH

= +15V; t = t = 40ns.

r

f

INPUTS BUFFERS

10. All input signal rise and fall times measured from 10% to 90% of

V

.

DD

11. Timing measurement reference level is (V + V )/2.

CONTROL

IH IL

12. Since input data latches are transparent for CS and WR both

low, it is preferred to have data valid before CS and WR both go

low. This prevents undesirable changes at the analog output

while the data inputs settle.

FIGURE 4. DIGITAL INPUT STRUCTURE

The input buffers are simple CMOS inverters designed such

that when the AD7545 is operated with V

= 5V, the buffers

DD

convert TTL input levels (2.4V and 0.8V) into CMOS logic

Circuit Information - D/A Converter Section

levels. When V is in the region of 2.0V to 3.5V the input

IN

Figure 2 shows a simplified circuit of the D/A converter

section of the AD7545. Note that the ladder termination

resistor is connected to AGND. R is typically 11kΩ.

buffers operate in their linear region and draw current from

the power supply. To minimize power supply currents it is

recommended that the digital input voltages be as close to

the supply rails (V

and DGND) as is practically possible.

The binary weighted currents are switched between the OUT1

bus line and AGND by N-Channel switches, thus maintaining a

constant current in each ladder leg independent of the switch

state. One of the current switches is shown in Figure 3.

DD

The AD7545 may be operated with any supply voltage in the

range 5V ≤ V ≤ 15V. With V = +15V the input logic

DD

levels are CMOS compatible only, i.e., 1.5V and 13.5V.

V

REF

R

Application

Output Offset

2R

CMOS current-steering D/A converters exhibit a code

dependent output resistance which in turn causes a code

dependent amplifier noise gain. The effect is a code

dependent differential nonlinearity term at the amplifier

R

FB

OUT1

AGND

output which depends on V

where V

is the amplifier

OS

DB10

DB9

DB1

DB0

(LSB)

DB11

(MSB)

input offset voltage. To maintain monotonic operation it is

-6

recommended that V

be no greater than (25 x 10 )

OS

FIGURE 2. SIMPLIFIED D/A CIRCUIT OF AD7545

TO LADDER

(V

) over the temperature range of operation.

REF

General Ground Management

FROM

INTERFACE

LOGIC

AC or transient voltages between AGND and DGND can

cause noise injection into the analog output. The simplest

method of ensuring that voltages at AGND and DGND are

equal is to tie AGND and DGND together at the AD7545. In

more complex systems where the AGND and DGND

connection is on the backplane, it is recommended that two

diodes be connected in inverse parallel between the AD7545

AGND and DGND pins (1N914 or equivalent).

AGND

OUT1

FIGURE 3. N-CHANNEL CURRENT STEERING SWITCH

The capacitance at the OUT1 bus line, C

dependent and varies from 70pF (all switches to AGND) to

200pF (all switches to OUT1).

, is code

OUT1

Digital Glitches

The input resistance at V

(Figure 2) is always equal to

When WR and CS are both low the latched are transparent

and the D/A converter inputs follow the data inputs. In some

bus systems, data on the data bus is not always valid for the

whole period during which WR is low and as a result invalid

data can briefly occur at the D/A converter inputs during a

write cycle. Such invalid data can cause unwanted glitches

at the output of the D/A converter. The solution to this

REF

is the R/2R ladder characteristic resistance and is

R

(R

LDR LDR

equal to the value “R”). Since R at the V

pin is constant,

IN REF

the reference terminal can be driven by a reference voltage or a

reference current, AC or DC, of positive or negative polarity. (If a

current source is used, a low temperature coefficient external

R

is recommended to define scale factor).

FB

4

AD7545

problem, if it occurs, is to retime the write pulse (WR) so that

it only occurs when data is valid.

operational amplifiers which are good candidates for many

applications. The main selection criteria for these

operational amplifiers is to have low V , low V

bias current and low settling time.

drift, low

OS

Another cause of digital glitches is capacitive coupling from the

digital lines to the OUT1 and AGND terminals. This should be

minimized by isolating the analog pins of the AD7545 (pins 1, 2,

19, 20) from the digital pins by a ground track run between pins

2 and 3 and between pins 18 and 19 of the AD7545. Note how

the analog pins are at one end of the package and separated

These amplifiers need to maintain the low nonlinearity and

monotonic operation of the D/A while providing enough

speed for maximum converter performance.

Operational Amplifiers

from the digital pins by V

and DGND to aid isolation at the

DD

HA-5127 Ultra Low Noise, Precision

board level. On-chip capacitive coupling can also give rise to

crosstalk from the digital to analog sections of the AD7545,

particularly in circuits with high currents and fast rise and fall

HA-5137 Ultra Low Noise, Precision, Wide Band

HA-5147 Ultra Low Noise, Precision, High Slew Rate

HA-5170 Precision, JFET Input

times. This type of crosstalk is minimized by using V

= +5V.

DD

However, great care should be taken to ensure that the +5V

used to power the AD7545 is free from digitally induced noise.

TABLE 1. RECOMMENDED TRIM RESISTOR VALUES vs

GRADES FOR V

= +5V

DD

TRIM RESISTOR

J

K

Temperature Coefficients

R1

R2

500Ω

150Ω

200Ω

68Ω

The gain temperature coefficient of the AD7545 has a

o

maximum value of 5ppm/ C and a typical value of 2ppm/ C.

This corresponds to worst case gain shifts of 2 LSBs and

o

0.8 LSBs respectively over a 100 C temperature range.

TABLE 2. UNIPOLAR BINARY CODE TABLE FOR CIRCUIT

OF FIGURE 5

When trim resistors R1 and R2 are used to adjust full scale

range, the temperature coefficient of R1 and R2 should also

be taken into account.

BINARY NUMBER IN DAC

REGISTER

ANALOG OUTPUT

Basic Applications













4095

------------

4096

Figures 5 and 6 show simple unipolar and bipolar circuits

using the AD7545. Resistor R1 is used to trim for full scale.

Capacitor C1 provides phase compensation and helps

prevent overshoot and ringing when using high speed op

amps. Note that the circuits of Figures 5 and 6 have constant

1111

1000

0000

1111

0000

0001

0000

–V

IN









2048

4096

1

2

0000

–V

------------ = –--V



IN











1

0000

–V

------------



input impedance at the V

terminal.

IN

4096

REF



The circuit of Figure 5 can either be used as a fixed reference

D/A converter so that it provides an analog output voltage in the

0000

0V

range 0V to -V (note the inversion introduced by the op amp)

IN

or V can be an AC signal in which case the circuit behaves as

IN

TABLE 3. 2’S COMPLEMENT CODE TABLE FOR CIRCUIT OF

FIGURE 6

an attenuator (2-Quadrant Multiplier). V can be any voltage in

IN

the range -20V ≤ V ≤ +20V (provided the op amp can handle

IN

such voltages) since V

shows the code relationship for the circuit of Figure 5.

is permitted to exceed V . Table 2

DATA INPUT

1111

ANALOG OUTPUT

REF

DD













2047

------------

2048

0111

0000

1111

1000

1111

0001

0000

1111

0000

+V

•

Figure 6 and Table 3 illustrate the recommended circuit and

code relationship for bipolar operation. The D/A function itself

uses offset binary code and inverter U on the MSB line

IN













1

------------

2048

0000

converts 2’s complement input code to offset binary code. If

appropriate, inversion of the MSB may be done in software

using an exclusive -OR instruction and the inverter omitted. R3,

R4 and R5 must be selected to match within 0.01% and they

should be the same type of resistor (preferably wire-wound or

metal foil), so that their temperature coefficients match.

Mismatch of R3 value to R4 causes both offset and full scale

error. Mismatch of R5 to R4 and R3 causes full scale error.

0000

0V









1

–V

•

------------

2048

1111





IN













2048

------------

2048

0000

•

The choice of the operational amplifiers in Figure 5 and

Figure 6 depends on the application and the trade off

between required precision and speed. Below is a list of

5

AD7545

V

R2 (NOTE)

DD

C1

33pF

18

20

V

R

OUT 1

AGND

DGND

DD

FB

V

1

2

V

IN

-

OUT

19

17

V

REF

AD7545

+

R1 (NOTE)

WR

CS

16

3

ANALOG

COMMON

DB11 - DB0

(PINS 4 - 15)

NOTE: REFER TO TABLE 1

FIGURE 5. UNIPOLAR BINARY OPERATION

V

R2 (NOTE)

DD

R4

20K

C1

33pF

18

20

R3

10K

R5

20K

V

R

OUT 1

AGND

DD

FB

V

1

2

IN

A1

19

17

V

REF

AD7545

-

V

A2

OUT

R1 (NOTE)

R6

5K

DB11

4

WR

CS

+

DB10 - DB0

16

3

DGND

ANALOG

COMMON

11

12

U

1

(SEE TEXT)

NOTE: FOR VALUES OF R1 AND R2

SEE TABLE 1

DATA INPUT

FIGURE 6. BIPOLAR OPERATION (2’S COMPLEMENT CODE)

6

AD7545

Die Characteristics

DIE DIMENSIONS

PASSIVATION

121 mils x 123 mils (3073µm x 3124µm)

Type: PSG/Nitride

PSG: 7 1.4kÅ

Nitride: 8 1.2kÅ

METALLIZATION

Type: Pure Aluminum

Thickness: 10 1kÅ

PROCESS

CMOS Metal Gate

Metallization Mask Layout

AD7545

PIN 4

DB11

(MSB)

PIN 7

DB8

PIN 6

DB9

PIN 5

DB10

PIN 3

DGND

PIN 2

AGND

PIN 1

OUT1

PIN 8

DB7

PIN 9

DB6

PIN 10

DB5

PIN 11

DB4

PIN 20

R

FEEDBACK

PIN 19

PIN 12

DB3

V

REF

PIN 13

DB2

PIN 18

V

DD

PIN 14

DB1

PIN 15

DB0

(LSB)

PIN 16

CS

PIN 17

WR

7

AD7545

Dual-In-Line Plastic Packages (PDIP)

E20.3 (JEDEC MS-001-AD ISSUE D)

20 LEAD DUAL-IN-LINE PLASTIC PACKAGE

N

E1

INDEX

AREA

INCHES

MILLIMETERS

1

2

3

N/2

SYMBOL

MIN

MAX

0.210

-

MIN

-

MAX

5.33

-

NOTES

-B-

A

A1

A2

B

-

4

-A-

0.015

0.115

0.014

0.045

0.008

0.980

0.005

0.300

0.240

0.39

2.93

0.356

1.55

0.204

24.89

0.13

7.62

6.10

4

D

E

BASE

PLANE

0.195

0.022

0.070

0.014

1.060

-

4.95

0.558

1.77

0.355

26.9

-

A2

A

-C-

-

SEATING

PLANE

L

C

L

B1

C

8

D1

B1

-

e_A

A1

A

D1

e

D

5

e_C

B S

C

B

e_B

D1

E

5

0.010 (0.25) M

C

0.325

0.280

8.25

7.11

6

E1

e

5

NOTES:

0.100 BSC

0.300 BSC

2.54 BSC

7.62 BSC

-

1. Controlling Dimensions: INCH. In case of conflict between English

and Metric dimensions, the inch dimensions control.

e

6

A

B

-

0.430

0.150

-

10.92

3.81

7

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

L

0.115

2.93

4

9

3. Symbols are defined in the “MO Series Symbol List” in Section 2.2

of Publication No. 95.

N

20

4. Dimensions A, A1 and L are measured with the package seated in

Rev. 0 12/93

JEDEC seating plane gauge GS-3.

5. D, D1, and E1 dimensions do not include mold flash or protrusions.

Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).

e

6. E and

dicular to datum

7. e and e are measured at the lead tips with the leads uncon-

are measured with the leads constrained to be perpen-

A

-C-

.

B

C

strained. e must be zero or greater.

C

8. B1 maximum dimensions do not include dambar protrusions. Dam-

bar protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,

E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).

All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at website www.intersil.com/design/quality/iso.asp.

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.

Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. How-

ever, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use.

No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site www.intersil.com

Sales Office Headquarters

NORTH AMERICA

Intersil Corporation

2401 Palm Bay Rd.

Palm Bay, FL 32905

TEL: (321) 724-7000

FAX: (321) 724-7240

EUROPE

Intersil SA

Mercure Center

100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111

FAX: (32) 2.724.22.05

ASIA

Intersil Ltd.

8F-2, 96, Sec. 1, Chien-kuo North,

Taipei, Taiwan 104

Republic of China

TEL: 886-2-2515-8508

FAX: 886-2-2515-8369

8


型号：	AD7545_01
厂家：	Intersil
描述：	12-Bit, Buffered, Multiplying CMOS DAC 12位缓冲乘法CMOS DAC
文件：	总8页 (文件大小：272K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD7545_01 [INTERSIL]

相关型号：

AD7546AD

AD7546BD

AD7546JN

AD7546KN

AD7547

AD7547ACHIPS

AD7547AQ

AD7547BQ

AD7547CQ

AD7547JC/D

AD7547JCWG

AD7547JEWG