ACTS74K [INTERSIL]
Radiation Hardened Dual D Flip Flop with Set and Reset; 抗辐射双D触发器具有置位和复位
| 型号： | ACTS74K |
| 厂家： | 
Intersil |
| 描述： | Radiation Hardened Dual D Flip Flop with Set and Reset |
| 文件： | 总3页 (文件大小：110K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TM
ACTS74MS
Radiation Hardened Dual D
Flip Flop with Set and Reset
January 1996
Features
Pinouts
14 PIN CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR CDIP2-T14,
LEAD FINISH C
• Devices QML Qualified in Accordance with MIL-PRFF-38535
• Detailed Electrical and Screening Requirements are Contained in
SMD# 5962-96713 and Intersil’s QM Plan
itle
CTS
MS)
b-
TOP VIEW
• 1.25 Micron Radiation Hardened SOS CMOS
R1
D1
1
2
3
4
5
6
7
14 VCC
13 R2
12 D2
11 CP2
10 S2
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
-10
t
• Single Event Upset (SEU) Immunity: <1 x 10
(Typ)
Errors/Bit/Day
CP1
S1
adia-
n
rd-
ed
al D
p
p
th
tand
set)
2
• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm /mg
Q1
11
• Dose Rate Upset . . . . . . . . . . . . . . . . >10 RAD (Si)/s, 20ns Pulse
Q1
9
8
Q2
Q2
12
• Dose Rate Survivability. . . . . . . . . . . >10 RAD (Si)/s, 20ns Pulse
GND
• Latch-Up Free Under Any Conditions
o
o
• Military Temperature Range . . . . . . . . . . . . . . . . . . -55 C to +125 C
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
14 PIN CERAMIC FLATPACK
MIL-STD-1835 DESIGNATOR CDFP3-F14,
LEAD FINISH C
• Input Logic Levels
- VIL = 0.8V Max
TOP VIEW
1
2
3
4
5
6
7
14
13
VCC
R2
thor
R1
D1
- VIH = VCC/2 Min
• Input Current ≤ 1µA at VOL, VOH
D2
12
11
10
CP1
S1
ey-
rds
ter-
CP2
S2
• Fast Propagation Delay. . . . . . . . . . . . . . . . 20ns (Max), 13ns (Typ)
Q1
Q2
Q1
9
8
Description
Q2
GND
The Intersil ACTS74MS is a Radiation Hardened Dual D Flip Flop with
Set(s) and Reset (R). The logic level at data input is transferred to the
output during the positive transition of the clock. The Set and Reset are
independent from the clock and accomplished by a low level on the
appropriate input.
mi-
n-
ctor,
dia-
n
rd-
ed,
,
The ACTS74MS utilizes advanced CMOS/SOS technology to achieve
high-speed operation. This device is a member of a radiation hardened,
high-speed, CMOS/SOS Logic Family.
The ACTS74MS is supplied in a 14 lead Ceramic Flatpack (K suffix) or a
14 Lead Ceramic Dual-In-Line Package (D suffix).
d
Ordering Information
rd,
L,
tel-
,
D,
ass
PART NUMBER
5962F9671301VCC
5962F9671301VXC
ACTS74D/Sample
ACTS74K/Sample
ACTS74HMSR
TEMPERATURE RANGE
-55oC to +125oC
-55oC to +125oC
25oC
SCREENING LEVEL
PACKAGE
MIL-PRF-38535 Class V
14 Lead SBDIP
MIL-PRF-38535 Class V
14 Lead Ceramic Flatpack
14 Lead SBDIP
Sample
Sample
Die
25oC
14 Lead Ceramic Flatpack
Die
25oC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc.
Spec Number 518787
File Number 3382.1
Copyright © Intersil Americas Inc. 2001, All Rights Reserved
1
ACTS74MS
Functional Diagram
S
CL
4(10)
P
N
CL
CL
D
P
N
CL
P
N
2(12)
CL
CL
CL
P
N
Q
CL
R
6(8)
1(13)
Q
Cp
5(9)
3(11)
CL
CL
TRUTH TABLE
INPUTS
OUTPUTS
SET
RESET
CP
X
D
X
X
X
H
L
Q
Q
L
L
H
L
H
L
H
L
X
H
L
X
H (Note 2) H (Note 2)
H
H
H
H
H
H
H
L
L
H
L
X
Q0
Q0
H = High Level (Steady State)
L = Low Level (Steady State)
X = Don’t Care
= Transition from Low to
High Level
NOTES:
1. Q0 = the level of Q before the indicated input conditions were es-
tablished.
2. This configuration is nonstable, that is, it will not persist when set
and reset inputs return to their inactive (high) level.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reli-
able. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Spec Number 518787
2
ACTS74MS
Die Characteristics
DIE DIMENSIONS:
88 mils x 88 mils
2240mm x 2240mm
METALLIZATION:
Type: AlSi
Metal 1 Thickness: 7.125kÅ ±1.125kÅ
Metal 2 Thickness: 9kÅ ±1kÅ
GLASSIVATION:
Type: SiO
2
Thickness: 8kÅ ±1kÅ
WORST CASE CURRENT DENSITY:
5
2
<2.0 x 10 A/cm
BOND PAD SIZE:
110µm x 110µm
4.3 mils x 4.3 mils
Metallization Mask Layout
ACTS74MS
D1
(2)
R1
(1)
VCC
(14)
R2
(13)
CP1 (3)
S1 (4)
(12) D2
(11) CP2
Q1 (5)
NC
(10) S2
NC
(6)
Q1
(7)
GND
(8)
Q2
(9)
Q2
Spec Number 518787
3
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