ACS20KMSR [INTERSIL]
Radiation Hardened Dual 4-Input NAND Gate; 抗辐射双4输入与非门
| 型号： | ACS20KMSR |
| 厂家： | 
Intersil |
| 描述： | Radiation Hardened Dual 4-Input NAND Gate |
| 文件： | 总8页 (文件大小：88K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ACS20MS
Radiation Hardened
Dual 4-Input NAND Gate
April 1995
Features
Pinouts
14 LEAD CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR, CDIP2-T14, LEAD FINISH C
TOP VIEW
• 1.25 Micron Radiation Hardened SOS CMOS
• Total Dose 300K RAD (Si)
• Single Event Upset (SEU) Immunity
<1 x 10-10 Errors/Bit-Day (Typ)
A1
B1
1
2
3
4
5
6
7
14 VCC
13 D2
12 C2
11 NC
10 B2
• SEU LET Threshold >80 MEV-cm2/mg
NC
C1
• Dose Rate Upset >1011 RAD (Si)/s, 20ns Pulse
• Latch-Up Free Under Any Conditions
D1
• Military Temperature Range: -55oC to +125oC
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range: 4.5V to 5.5V
Y1
9
8
A2
Y2
GND
• Input Logic Levels
14 LEAD CERAMIC FLATPACK
MIL-STD-1835 DESIGNATOR, CDFP3-F14, LEAD FINISH C
TOP VIEW
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
• Input Current ≤1µA at VOL, VOH
1
2
3
4
5
6
7
14
13
12
11
10
9
VCC
D2
A1
B1
Description
C2
NC
C1
The Intersil ACS20MS is a radiation hardened dual 4-input
NAND gate. A low on any input forces the output to a high logic
state.
NC
B2
D1
Y1
A2
The ACS20MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of the
radiation hardened, high-speed, CMOS/SOS Logic Family.
Y2
GND
8
Ordering Information
PART NUMBER
ACS20DMSR
TEMPERATURE RANGE
SCREENING LEVEL
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
PACKAGE
o
o
-55 C to +125 C
14 Lead SBDIP
o
o
ACS20KMSR
-55 C to +125 C
14 Lead Ceramic Flatpack
14 Lead SBDIP
o
ACS20D/Sample
ACS20K/Sample
ACS20HMSR
+25 C
o
+25 C
Sample
14 Lead Ceramic Flatpack
Die
o
+25 C
Die
Truth Table
Functional Diagram
(1, 9)
An
INPUTS
OUTPUT
An
L
Bn
Cn
X
Dn
Yn
H
H
H
H
L
Bn
(2, 10)
X
L
X
X
X
L
(6, 8)
Yn
X
X
X
X
X
H
L
(4, 12)
Cn
X
X
H
H
H
Dn
(5, 13)
NOTE: L = Logic Level Low, H = Logic level High, X = Don’t Care
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Spec Number 518815
File Number 3616
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
1
Specifications ACS20MS
Absolute Maximum Ratings
Reliability Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +6.0V
Input Voltage Range. . . . . . . . . . . . . . . . . . . . . .-0.5V to VCC +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Impedance
DIP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flatpack. . . . . . . . . . . . . . . . . . . . . . . . . . 116 C/W
Maximum Package Power Dissipation at +125 C
DIP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.7W
Flatpack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.4W
Maximum Device Power Dissipation. . . . . . . . . . . . . . . . . . .(TBD)W
θ
θ
JA
JC
o
o
74 C/W
24 C/W
o
o
30 C/W
o
o
o
Storage Temperature Range (TSTG) . . . . . . . . . . . -65 C to +150 C
o
Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +265 C
o
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Gates
(All Voltages Reference to VSS)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Input Rise and Fall Time at 4.5V VCC (TR, TF). . . . . . .10ns/V Max
Operating Temperature Range. . . . . . . . . . . . . . . . -55 C to +125 C
Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . VCC to 70% of VCC
Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . . .0V to 30% of VCC
o
o
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP
A SUB-
LIMITS
(NOTE 1)
PARAMETER
SYMBOL
CONDITIONS
GROUPS
TEMPERATURE
MIN
MAX
UNITS
µA
o
Supply Current
ICC
VCC = 5.5V,
VIN = VCC or GND
1
2, 3
1
+25 C
-
-
5
o
o
+125 C, -55 C
100
µA
o
Output Current
(Source)
IOH
IOL
VCC = 4.5V, VIH = 4.5V,
VOUT = VCC -0.4V,
VIL = 0V, (Note 2)
+25 C
-12
-8
12
8
-
-
-
-
-
mA
mA
mA
mA
V
o
o
2, 3
1
+125 C, -55 C
o
Output Current
(Sink)
VCC = 4.5V, VIH = 4.5V,
VOUT = 0.4V, VIL = 0V,
(Note 2)
+25 C
o
o
2, 3
1, 2, 3
+125 C, -55 C
o
o
o
Output Voltage High
VOH
VCC = 5.5V, VIH = 3.85V,
+25 C, +125 C, -55 C VCC -0.1
VIL = 1.65V, IOH = -50µA
o
o
o
VCC = 4.5V, VIH = 3.15V,
VIL = 1.35V, IOH = -50µA
1, 2, 3
1, 2, 3
1, 2, 3
+25 C, +125 C, -55 C VCC -0.1
-
V
V
V
o
o
o
Output Voltage Low
VOL
VCC = 5.5V, VIH = 3.85V,
VIL = 1.65V, IOL = 50µA
+25 C, +125 C, -55 C
-
-
0.1
0.1
o
o
o
VCC = 4.5V, VIH = 3.15V,
+25 C, +125 C, -55 C
VIL = 1.35V, IOL = 50µA
o
Input Leakage
Current
IIN
FN
VCC = 5.5V,
VIN = VCC or GND
1
+25 C
-
-
-
±0.5
±1.0
-
µA
µA
V
o
o
2, 3
+125 C, -55 C
o
o
o
Noise Immunity
Functional Test
VCC = 4.5V, VIH = 3.15V,
VIL = 1.35V, (Note 3)
7, 8A, 8B
+25 C, +125 C, -55 C
NOTES:
1. All voltages referenced to device GND.
2. Force/Measure functions may be interchanged.
3. For functional tests, VO ≥4.0V is recognized as a logic “1”, and VO ≤0.5V is recognized as a logic “0”.
Spec Number 518815
2
Specifications ACS20MS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP
LIMITS
(NOTES 1, 2)
A SUB-
PARAMETER
SYMBOL
CONDITIONS
GROUPS
TEMPERATURE
MIN
MAX
UNITS
o
Propagation Delay
Input to Output
TPHL
VCC = 4.5V, VIH = 4.5V,
VIL = 0V
9
+25 C
2
12
ns
o
o
TPLH
VCC = 4.5V, VIH = 4.5V,
VIL = 0V
10, 11
+125 C, -55 C
2
15
ns
NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
CONDITIONS
NOTE
TEMP
MIN
TYP
18
20
-
MAX
UNITS
pF
o
Capacitance Power
Dissipation
CPD
VCC = 5.0V, VIH = 5.0V,
VIL = 0V, f = 1MHz
1
+25 C
-
-
-
-
-
o
+125 C
-
pF
o
Input Capacitance
CIN
VCC = 5.0V, VIH = 5.0V,
VIL = 0V, f = 1MHz
1
+25 C
10
10
pF
o
+125 C
-
pF
NOTE:
1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly
tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
RAD LIMITS
(NOTE 1)
PARAMETER
Supply Current
SYMBOL
ICC
CONDITIONS
TEMPERATURE
MIN
-
MAX
100
-
UNITS
µA
o
VCC = 5.5V, VIN = VCC or GND
+25 C
o
Output Current
(Source)
IOH
VCC = VIH = 4.5V,
VOUT = VCC -0.4V, VIL = 0
+25 C
-8.0
mA
o
Output Current (Sink)
IOL
VCC = VIH = 4.5V,
VOUT = 0.4V, VIL = 0
+25 C
8.0
-
-
mA
V
o
Output Voltage High
VOH
VCC = 5.5V, VIH = 3.85V,
+25 C
VCC -0.1
VIL = 1.65V, IOH = -50µA
o
VCC = 4.5V, VIH = 3.15V,
+25 C
VCC -0.1
-
V
VIL = 1.35V, IOH = -50µA
o
Output Voltage Low
VOL
VCC = 5.5V, VIH = 3.85V,
VIL = 1.65V, IOL = 50µA
+25 C
-
-
0.1
0.1
V
o
VCC = 4.5V, VIH = 3.15V,
+25 C
V
VIL = 1.35V, IOL = 50µA
o
Input Leakage Current
IIN
FN
VCC = 5.5V, VIN = VCC or GND
+25 C
-
-
±1
µA
o
Noise Immunity
Functional Test
VCC = 4.5V, VIH = 3.15V,
VIL = 1.35V, (Note 2)
+25 C
-
V
o
Propagation Delay
Input to Output
TPHL
TPLH
VCC = 4.5V, VIH = 4.5V, VIL = 0V
+25 C
2
15
ns
NOTES:
1. All voltages referenced to device GND.
2. For functional tests, VO ≥4.0V is recognized as a logic “1”, and VO ≤0.5V is recognized as a logic “0”.
o
TABLE 5. DELTA PARAMETERS (+25 C)
(NOTE 1)
PARAMETER
Supply Current
SYMBOL
DELTA LIMIT
UNITS
µA
ICC
±1.0
Output Current
NOTE:
IOL/IOH
±15
%
1. All delta calculations are referenced to 0 hour readings or pre-life readings.
Spec Number 518815
3
Specifications ACS20MS
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
Initial Test (Preburn-In)
METHOD
100%/5004
100%/5004
100%/5004
100%/5004
100%/5004
100%/5004
100%/5004
Sample/5005
Sample/5005
Sample/5005
Sample/5005
GROUP A SUBGROUPS
READ AND RECORD
ICC, IOL/H
1, 7, 9
1, 7, 9
Interim Test 1 (Postburn-In)
Interim Test 2 (Postburn-In)
PDA
ICC, IOL/H
ICC, IOL/H
1, 7, 9
1, 7, 9, Deltas
1, 7, 9
Interim Test 3 (Postburn-In)
PDA
ICC, IOL/H
1, 7, 9, Deltas
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
1, 7, 9
Final Test
Group A (Note 1)
Group B
Subgroup B-5
Subgroup B-6
Subgroups 1, 2, 3, 9, 10, 11
Group D
NOTE:
1, 7, 9
1. Alternate Group A testing may be exercised in accordance with MIL-STD-883, Method 5005.
TABLE 7. TOTAL DOSE IRRADIATION
TEST
READ AND RECORD
CONFORMANCE GROUP
Group E Subgroup 2
NOTE:
METHOD
PRE RAD
POST RAD
PRE RAD
1, 9
POST RAD
5005
1, 7, 9
Table 4
Table 4 (Note 1)
1. Except FN test which will be performed 100% Go/No-Go.
o
o
TABLE 8. BURN-IN TEST CONNECTIONS (+125 C < TA < 139 C)
OSCILLATOR
OPEN
GROUND
1/2 VCC = 3V ±0.5V
VCC = 6V ±0.5V
50kHz
25kHz
STATIC 1 BURN-IN (Notes 1, 2)
-
1, 2, 4, 5, 7, 9, 10,
12, 13
3, 6, 8, 11
14
-
-
STATIC 2 BURN-IN (Notes 1, 2)
-
7
3, 6, 8, 11
3, 6, 8, 11
1, 2, 4, 5, 9,
10, 12, 13
-
-
-
DYNAMIC BURN-IN (Notes 1, 2)
-
7
14
1, 2, 4, 5, 9,
10, 12, 13
NOTES:
1. Each lead except VCC and GND will have a series resistor of 500Ω ±5%.
2. No-connect pins 3 and 11 may be connected to any voltage level.
TABLE 9. IRRADIATION TEST CONNECTIONS
FUNCTION
Irradiation Circuit (Note 1)
NOTE:
OPEN
GROUND
VCC = 5V ±0.5V
1, 2, 4, 5, 9, 10, 11, 12, 13, 14
3, 6, 8, 11
7
1. Each pin except VCC and GND will have a series resistor of 47kΩ ±5%. Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures.
Spec Number 518815
4
Specifications ACS20MS
Intersil - Space Products MS Screening
Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) 100% Static Burn-In 2 Method 1015, 24 Hours at +125oC Min
Radiation Verification (Each Wafer) Method 1019,
4 Samples/Wafer, 0 Rejects
100% Interim Electrical Test 2 (Note 1)
100% Dynamic Burn-In Method 1015, 240 Hours at +125oC
100% Nondestructive Bond Pull Method 2023
100% Internal Visual Inspection Method 2010
or 180 Hours at +135oC
100% Interim Electrical Test 3 (Note 1)
100% Final Electrical Test
100% Temperature Cycling Method 1010 Condition C
(-65o to +150oC)
100% Fine and Gross Seal Method 1014
100% Radiographics Method 2012 (2 Views)
100% External Visual Method 2009
100% Constant Acceleration
100% PIND Testing
100% External Visual Inspection
100% Serialization
Group A (All Tests) Method 5005 (Class S)
Group B (Optional) Method 5005 (Class S) (Note 2)
Group D (Optional) Method 5005 (Class S) (Note 2)
CSI and/or GSI (Optional) (Note 2)
100% Initial Electrical Test
100% Static Burn-In 1 Method 1015, 24 Hours at +125oC Min
100% Interim Electrical Test 1 (Note 1)
Data Package Generation (Note 3)
NOTES:
1. Failures from interim electrical tests 1 and 2 are combined for determining PDA (PDA = 5% for subgroups 1, 7, 9 and delta failures com-
bined, PDA = 3% for subgroup 7 failures). Interim electrical tests 3 PDA (PDA = 5% for subgroups 1, 7, 9 and delta failures combined,
PDA = 3% for subgroup 7 failures).
2. These steps are optional, and should be listed on the purchase order if required.
3. Data Package Contents:
Cover Sheet (P.O. Number, Customer Number, Lot Date Code, Intersil Number, Lot Number, Quantity).
Certificate of Conformance (as found on shipper).
Lot Serial Number Sheet (Good Unit(s) Serial Number and Lot Number).
Variables Data (All Read, Record, and delta operations).
Group A Attributes Data Summary.
Wafer Lot Acceptance Report (Method 5007) to include reproductions of SEM photos. NOTE: SEM photos to include percent of step coverage.
X-Ray Report and Film, including penetrometer measurements.
GAMMA Radiation Report with initial shipment of devices from the same wafer lot; containing a Cover Page, Disposition, RAD Dose,
Lot Number, Test Package, Spec Number(s), Test Equipment, etc. Irradiation Read and Record data will be on file at Intersil.
Propagation Delay Timing Diagram and Load Circuit
DUT
TEST
POINT
VIH
RL
500Ω
CL
50pF
INPUT
VS
VSS
TPLH
TPHL
VOH
VOL
VS
OUTPUT
AC VOLTAGE LEVELS
PARAMETER
VCC
ACS
4.50
4.50
2.25
0
UNITS
V
V
V
V
V
VIH
VS
VIL
GND
0
Spec Number 518815
5
ACS20MS
Die Characteristics
DIE DIMENSIONS:
88 mils x 88 mils
DIE ATTACH:
Material: Silver Glass or JM7000 Polymer after 7/1/95
2,240mm x 2,240mm
WORST CASE CURRENT DENSITY:
< 2.0 x 105 A/cm2
METALLIZATION:
Type: AlSiCu
Metal 1 Thickness: 6.75kÅ (Min), 8.25kÅ (Max)
Metal 2 Thickness: 9kÅ (Min), 11kÅ (Max)
BOND PAD SIZE:
> 4.3 mils x 4.3 mils
> 110µm x 110µm
GLASSIVATION:
Type: SiO2
Thickness: 8kÅ ±1kÅ
Metallization Mask Layout
ACS20MS
B1
(2)
A1
(1)
VCC
(14)
D2
(13)
NC (3)
C1 (4)
(12) C2
(11) NC
(X) NC
(10) B2
NC (X)
D1 (5)
(6)
Y1
(7)
GND
(8)
Y2
(9)
A2
Spec Number 518815
6
ACS20MS
Ceramic Dual-In-Line Metal Seal Packages (SBDIP)
D14.3 MIL-STD-1835 CDIP2-T14 (D-1, CONFIGURATION C)
14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
c1 LEAD FINISH
-A-
-D-
E
INCHES MILLIMETERS
MIN
BASE
METAL
(c)
SYMBOL
MAX
0.200
0.026
0.023
0.065
0.045
0.018
0.015
0.785
0.310
MIN
-
MAX
5.08
0.66
0.58
1.65
1.14
0.46
0.38
19.94
7.87
NOTES
A
b
-
-
b1
M
M
0.014
0.014
0.045
0.023
0.008
0.008
-
0.36
0.36
1.14
0.58
0.20
0.20
-
2
-B-
(b)
b1
b2
b3
c
3
SECTION A-A
S
S
S
D
bbb
C
A - B
-
D
4
BASE
PLANE
S2
Q
2
A
-C-
SEATING
PLANE
c1
D
3
L
-
S1
b2
eA
A A
E
0.220
5.59
-
e
0.100 BSC
2.54 BSC
-
e
eA/2
C A - B
b
C A - B
c
eA
eA/2
L
0.300 BSC
0.150 BSC
7.62 BSC
3.81 BSC
-
ccc
D
aaa
D
S S
M
S
S
M
-
NOTES:
0.125
0.200
3.18
5.08
-
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
Q
0.015
0.005
0.005
0.060
0.38
0.13
0.13
1.52
5
S1
S2
-
-
-
-
6
7
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
o
o
o
o
90
105
90
105
-
α
aaa
bbb
ccc
M
-
-
-
-
0.015
0.030
0.010
0.0015
-
-
-
-
0.38
0.76
0.25
0.038
-
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
-
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
2
8
N
14
14
Rev. 0 4/94
5. Dimension Q shall be measured from the seating plane to the
base plane.
6. Measure dimension S1 at all four corners.
7. Measure dimension S2 from the top of the ceramic body to the
nearest metallization or lead.
8. N is the maximum number of terminal positions.
9. Braze fillets shall be concave.
10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
11. Controlling dimension: INCH.
Spec Number 518815
7
ACS20MS
Ceramic Metal Seal Flatpack Packages (Flatpack)
K14.A MIL-STD-1835 CDFP3-F14 (F-2A, CONFIGURATION B)
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
A
A
e
INCHES MILLIMETERS
MIN
PIN NO. 1
ID AREA
SYMBOL
MAX
0.115
0.022
0.019
0.009
0.006
0.390
0.260
0.290
-
MIN
1.14
0.38
0.38
0.10
0.10
-
MAX
2.92
0.56
0.48
0.23
0.15
9.91
6.60
7.11
-
NOTES
D
A
b
0.045
0.015
0.015
0.004
0.004
-
-
-
-A-
-B-
S1
b1
c
-
-
b
c1
D
-
E1
3
-
M
S
S
M
S
C
S
D
0.004
Q
H
A - B
D
0.036
H
A - B
E
0.235
-
5.97
-
E
E1
E2
E3
e
3
-
-D-
A
0.125
0.030
3.18
0.76
-H-
-C-
-
-
7
-
L
E2
L
E3
E3
0.050 BSC
1.27 BSC
SEATING AND
BASE PLANE
c1
LEAD FINISH
k
0.008
0.270
0.026
0.005
-
0.015
0.370
0.045
-
0.20
6.86
0.66
0.13
-
0.38
9.40
1.14
-
2
-
L
BASE
METAL
Q
S1
M
N
8
6
-
(c)
b1
M
0.0015
0.04
M
14
14
-
(b)
SECTION A-A
Rev. 0 5/18/94
NOTES:
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark. Alternately, a tab (dimension k)
may be used to identify pin one.
5. N is the maximum number of terminal positions.
6. Measure dimension S1 at all four corners.
7. For bottom-brazed lead packages, no organic or polymeric mate-
rials shall be molded to the bottom of the package to cover the
leads.
2. If a pin one identification mark is used in addition to a tab, the lim-
its of dimension k do not apply.
8. Dimension Q shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension Q minimum
shall be reduced by 0.0015 inch (0.038mm) maximum when sol-
der dip lead finish is applied.
3. This dimension allows for off-center lid, meniscus, and glass overrun.
4. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness. The maximum lim-
its of lead dimensions b and c or M shall be measured at the cen-
troid of the finished lead surfaces, when solder dip or tin plate
lead finish is applied.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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Spec Number 518815
8
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