80C88_08_技术文档

80C88

®

Data Sheet

February 22, 2008

FN2949.4

CMOS 8-/16-Bit Microprocessor

Features

The Intersil 80C88 high performance 8-/16-bit CMOS CPU is

manufactured using a self-aligned silicon gate CMOS

process (Scaled SAJI IV). Two modes of operation,

MINimum for small systems and MAXimum for larger

applications such as multiprocessing, allow user

• Compatible with NMOS 8088

• Direct Software Compatibility with 80C86, 8086, 8088

• 8-Bit Data Bus Interface; 16-Bit Internal Architecture

• Completely Static CMOS Design

configuration to achieve the highest performance level.

- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5MHz (80C88)

- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . .8MHz (80C88-2)

Full TTL compatibility (with the exception of CLOCK) and

industry-standard operation allow use of existing NMOS

8088 hardware and Intersil CMOS peripherals.

• Low Power Operation

- ICCSB. . . . . . . . . . . . . . . . . . . . . . . . . 500µA Maximum

- ICCOP . . . . . . . . . . . . . . . . . . . . .10mA/MHz Maximum

Complete software compatibility with the 80C86, 8086, and

8088 microprocessors allows use of existing software in new

designs.

• 1 Megabyte of Direct Memory Addressing Capability

• 24 Operand Addressing Modes

• Bit, Byte, Word, and Block Move Operations

• 8-Bit and 16-Bit Signed/Unsigned Arithmetic

• Bus-Hold Circuitry Eliminates Pull-up Resistors

• Wide Operating Temperature Ranges

- C80C88 . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

- I80C88 . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

- M80C88 . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C

• Pb-Free Available (RoHS Compliant)

Ordering Information

TEMPERATURE

RANGE

PART NUMBER

(5MHz)

PART

MARKING

PART NUMBER

(8MHz)

PART

MARKING

(°C)

PACKAGE

40 LD PDIP

PKG. DWG. #

E40.6

CP80C88

IP80C88

CP80C88

CP80C88-2

IP80C88-2

CP80C88-2

IP80C88-2

0 to +70

IP80C88

-40 to +85

-55 to +125

0 to +70

40 LD PDIP

E40.6

F40.6

E40.6

MD80C88/B

CP80C88Z

40 LD CERDIP

CP80C88Z

(Note)

40 LD PDIP*

(Pb-Free)

NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%

matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.

Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J

STD-020.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

80C88

Pinouts

80C88

(40 LD PDIP, 40 LD CERIDP)

TOP VIEW

MIN

MODE

MAX

MODE

GND

A14

A13

A12

A11

A10

A9

1

2

3

4

5

6

7

8

9

40 V

CC

39 A15

38 A16/S3

37 A17/S4

36 A18/S5

35 A19/S6

34 SS0

(HIGH)

A8

33 MN/MX

32 RD

AD7

AD6 10

AD5 11

AD4 12

AD3 13

AD2 14

AD1 15

AD0 16

NMI 17

INTR 18

CLK 19

GND 20

31 HOLD

30 HLDA

29 WR

(RQ/GT0)

(RQ/GT1)

(LOCK)

(S2)

28 IO/M

27 DT/R

26 DEN

(S1)

(S0)

25 ALE

(QS0)

(QS1)

24 INTA

23 TEST

22 READY

21 RESET

FN2949.4

February 22, 2008

2

80C88

Functional Diagram

EXECUTION UNIT

REGISTER FILE

BUS INTERFACE UNIT

RELOCATION

REGISTER FILE

DATA POINTER

AND

INDEX REGS

(8 WORDS)

SEGMENT REGISTERS

AND

INSTRUCTION POINTER

(5 WORDS)

SSO/HIGH

16-BIT ALU

FLAGS

4

8

A19/S6. . . A16/S3

AD7-AD0

A8-A15

BUS

INTERFACE

UNIT

3

4

INTA, RD, WR

DT/R, DEN, ALE, IO/M

4-BYTE

INSTRUCTION

QUEUE

TEST

INTR

LOCK

NMI

2

QS0, QS1

CONTROL AND TIMING

RQ/GT0, 1

2

HOLD

HLDA

3

S2, S1, S0

3

CLK

RESET READY MN/MX

GND

V

CC

MEMORY INTERFACE

C-BUS

INSTRUCTION

STREAM BYTE

QUEUE

B-BUS

ES

CS

BUS

INTERFACE

UNIT

SS

DS

IP

EXECUTION UNIT

CONTROL SYSTEM

A-BUS

AH

AL

BL

CL

DL

ARITHMETIC/

LOGIC UNIT

BH

CH

DH

EXECUTION

UNIT

SP

BP

SI

FLAGS

DI

FN2949.4

February 22, 2008

3

80C88

Pin Description

The following pin function descriptions are for 80C88 systems in either minimum or maximum mode. The “local bus” in these

descriptions is the direct multiplexed bus interface connection to the 80C88 (without regard to additional bus buffers).

SYMBOL

NUMBER

TYPE

DESCRIPTION

MAXIMUM OR MINIMUM MODE. THE “LOCAL BUS” IN THESE DESCRIPTIONS IS THE DIRECT MULTIPLEXEDBUS INTERFACE

CONNECTION TO THE 80C88 (WITHOUT REGARD TO ADDITIONAL BUS BUFFERS).

AD7 thru

AD0

9 thru 16

I/O

ADDRESS DATA BUS: These lines constitute the time multiplexed memory/IO address (T1) and data

(T2,T3,Tw and T4) bus. These lines are active HIGH and are held at high impedance to the last valid level

during interrupt acknowledge and local bus “hold acknowledge” or “grant sequence”

A15,

A14 thru A8

39, 2 thru 8

O

ADDRESS BUS: These lines provide address bits 8 through 15 for the entire bus cycle (T1-T4). These

lines do not have to be latched by ALE to remain valid. A15-A8 are active HIGH and are held at high

impedance to the last valid logic level during interrupt acknowledge and local bus “hold acknowledge” or

“grant sequence”.

A19/S6,

A18/S5,

A17/S4,

A16/S3

35

36

37

38

O

ADDRESS/STATUS: During T1, these are the four most

S4

0

S3 CHARACTERISTICS

significant address lines for memory operations. During I/O

operations, these lines are LOW. During memory and I/O

operations, status information is available on these lines during

T2, T3, TW and T4. S6 is always LOW. The status of the

interrupt enable flag bit (S5) is updated at the beginning of each

clock cycle. S4 and S3 are encoded as shown.

0

1

0

1

Alternate Data

Stack

0

1

Code or None

Data

This information indicates which segment register is presently

being used for data accessing.

1

These lines are held at high impedance to the last valid logic

level during local bus “hold acknowledge” or “grant Sequence”.

RD

32

O

READ: Read strobe indicates that the processor is performing a memory or I/O read cycle, depending on

the state of the IO/M pin or S2. This signal is used to read devices which reside on the 80C88 local bus.

RD is active LOW during T2, T3, Tw of any read cycle, and is guaranteed to remain HIGH in T2 until the

80C88 local bus has floated.

This line is held at a high impedance logic one state during “hold acknowledge” or “grant sequence”.

READY

INTR

22

18

I

READY: is the acknowledgment from the address memory or I/O device that it will complete the data

transfer. The RDY signal from memory or I/O is synchronized by the 82C84A clock generator to from

READY. This signal is active HIGH. The 80C88 READY input is not synchronized. Correct operation is not

guaranteed if the set up and hold times are not met.

INTERRUPT REQUEST: is a level triggered input which is sampled during the last clock cycle of each

instruction to determine if the processor should enter into an interrupt acknowledge operation. A subroutine

is vectored to via an interrupt vector lookup table located in system memory. It can be internally masked by

software resetting the interrupt enable bit. INTR is internally synchronized. This signal is active HIGH.

TEST

NMI

23

17

I

TEST: input is examined by the “wait for test” instruction. If the TEST input is LOW, execution continues,

otherwise the processor waits in an “idle” state. This input is synchronized internally during each clock cycle

on the leading edge of CLK.

NONMASKABLE INTERRUPT: is an edge triggered input which causes a type 2 interrupt. A subroutine is

vectored to via an interrupt vector lookup table located in system memory. NMI is not maskable internally

by software. A transition from a LOW to HIGH initiates the interrupt at the end of the current instruction.

This input is internally synchronized.

RESET

21

I

RESET: cases the processor to immediately terminate its present activity. The signal must transition LOW

to HIGH and remain active HIGH for at least four clock cycles. It restarts execution, as described in the

instruction set description, when RESET returns LOW. RESET is internally synchronized.

CLK

V_CC

19

40

CLOCK: provides the basic timing for the processor and bus controller. It is asymmetric with a 33% duty

cycle to provide optimized internal timing.

V_CC: is the +5V power supply pin. A 0.1µF capacitor between pins 20 and 40 recommended for

decoupling.

GND

1, 20

33

GND: are the ground pins (both pins must be connected to system ground). A 0.1µF capacitor between

pins 1 and 20 is recommended for decoupling.

MN/MX

I

MINIMUM/MAXIMUM: indicates the mode in which the processor is to operate. The two modes are

discussed in the following sections.

FN2949.4

February 22, 2008

4

80C88

Pin Description

The following pin function descriptions are for 80C88 system in minimum mode (i.e., MN/MX = V_CC). Only the pin functions which

are unique to the minimum mode are described; all other pin functions are as described above.

SYMBOL

NUMBER

TYPE

DESCRIPTION

MINIMUM MODE SYSTEM (i.e., MN/MX = V_CC

)

IO/M

WR

28

29

O

STATUS LINE: is an inverted maximum mode S2. It is used to distinguish a memory access from an I/O

access. IO/M becomes valid in the T4 preceding a bus cycle and remains valid until the final T4 of the cycle

(I/O = HIGH, M = LOW). IO/M is held to a high impedance logic one during local bus “hold acknowledge”.

Write: strobe indicates that the processor is performing a write memory or write I/O cycle, depending on

the state of the IO/M signal. WR is active for T2, T3, and Tw of any write cycle. It is active LOW, and is held

to high impedance logic one during local bus “hold acknowledge”.

INTA

ALE

24

25

O

INTA: is used as a read strobe for interrupt acknowledge cycles. It is active LOW during T2, T3 and Tw of

each interrupt acknowledge cycle. Note that INTA is never floated.

ADDRESS LATCH ENABLE: is provided by the processor to latch the address into the 82C82/82C83

address latch. It is a HIGH pulse active during clock low of T1 of any bus cycle. Note that ALE is never

floated.

DT/R

DEN

27

26

O

DATA TRANSMIT/RECEIVE: is needed in a minimum system that desires to use an 82C86/82C87 data

bus transceiver. It is used to control the direction of data flow through the transceiver. Logically, DT/R is

equivalent to S1 in the maximum mode, and its timing is the same as for IO/M (T = HIGH, R = LOW). This

signal is held to a high impedance logic one during local bus “hold acknowledge”.

DATA ENABLE: is provided as an output enable for the 82C86/82C87 in a minimum system which uses

the transceiver. DEN is active LOW during each memory and I/O access, and for INTA cycles. For a read

or INTA cycle, it is active from the middle of T2 until the middle of T4, while for a write cycle, it is active from

the beginning of T2 until the middle of T4. DEN is held to high impedance logic one during local bus “hold

acknowledge”.

HOLD,

HLDA

31

30

I

O

HOLD: indicates that another master is requesting a local bus “hold”. To be acknowledged, HOLD must be

active HIGH. The processor receiving the “hold” request will issue HLDA (HIGH) as an acknowledgment,

in the middle of a T4 or T1 clock cycle. Simultaneous with the issuance of HLDA the processor will float the

local bus and control lines. After HOLD is detected as being LOW, the processor lowers HLDA, and when

the processor needs to run another cycle, it will again drive the local bus and control lines.

Hold is not an asynchronous input. External synchronization should be provided if the system cannot

otherwise guarantee the set up time.

SS0

34

O

STATUS LINE: is logically equivalent to S0 in

IO/M

DT/R

SS0 CHARACTERISTICS

the maximum mode. The combination of SS0,

IO/M and DT/R allows the system to completely

decode the current bus cycle status. SS0 is held

to high impedance logic one during local bus

“hold acknowledge”.

1

0

1

0

1

0

1

0

1

0

1

0

1

Interrupt Acknowledge

Read I/O Port

Write I/O Port

Halt

Code Access

Read Memory

Write Memory

Passive

FN2949.4

February 22, 2008

5

80C88

Pin Description (Continued)

The following pin function descriptions are for 80C88 system in maximum mode (i.e., MN/MX = GND). Only the pin functions which

are unique to the maximum mode are described; all other pin functions are as described above.

SYMBOL

NUMBER

TYPE

DESCRIPTION

MAXIMUM MODE SYSTEM (i.e., MN/MX = GND).

S0

S1

S2

26

27

28

O

STATUS: is active during clock high of T4, T1 and T2,

S2

0

S1

0

S0

0

CHARACTERISTICS

Interrupt Acknowledge

Read I/O Port

Write I/O Port

Halt

and is returned to the passive state (1, 1, 1) during T3 or

during Tw when READY is HIGH. This status is used by

the 82C88 bus controller to generate all memory and I/O

access control signals. Any change by S2, S1 or S0

during T4 is used to indicate the beginning of a bus

cycle, and the return to the passive state in T3 or Tw is

used to indicate the end of a bus cycle.

0

1

0

1

0

1

0

Code Access

Read Memory

Write Memory

Passive

These signals are held at a high impedance logic one

state during “grant sequence”.

1

0

1

0

1

RQ/GT0,

RQ/GT1

31

30

I/O

REQUEST/GRANT: pins are used by other local bus masters to force the processor to release the local

bus at the end of the processor’s current bus cycle. Each pin is bidirectional with RQ/GT0 having higher

priority than RQ/GT1. RQ/GT has internal bus-hold high circuitry and, if unused, may be left unconnected.

The request/grant sequence is as follows (see RQ/GT Timing Sequence):

1. A pulse of one CLK wide from another local bus master indicates a local bus request (“hold”) to the

80C88 (pulse 1).

2. During a T4 or T1 clock cycle, a pulse one clock wide from the 80C88 to the requesting master (pulse

2), indicates that the 80C88 has allowed the local bus to float and that it will enter the “grant sequence”

state at the next CLK. The CPUs bus interface unit is disconnected logically from the local bus during

“grant sequence”.

3. A pulse one CLK wide from the requesting master indicates to the 80C88 (pulse 3) that the “hold”

request is about to end and that the 80C88 can reclaim the local bus at the next CLK. The CPU then

enters T4 (or T1 if no bus cycles pending).

Each master-master exchange of the local bus is a sequence of three pulses. There must be one idle CLK

cycle after bus exchange. Pulses are active LOW.

If the request is made while the CPU is performing a memory cycle, it will release the local bus during T4

of the cycle when all the following conjugations are met:

1. Request occurs on or before T2.

2. Current cycle is not the low bit of a word.

3. Current cycle is not the first acknowledge of an interrupt acknowledge sequence.

4. A locked instruction is not currently executing.

If the local bus is idle when the request is made the two possible events will follow:

1. Local bus will be released during the next clock.

2. A memory cycle will start within 3 clocks. Now the four rules for a currently active memory cycle apply

with condition number 1 already satisfied.

LOCK

29

O

LOCK: indicates that other system bus masters are not to gain control of the system bus while LOCK is

active (LOW). The LOCK signal is activated by the “LOCK” prefix instruction and remains active until the

completion of the next instruction. This signal is active LOW, and is held at a high impedance logic one

state during “grant sequence”. In Max Mode, LOCK is automatically generated during T2 of the first INTA

cycle and removed during T2 of the second INTA cycle.

FN2949.4

February 22, 2008

6

80C88

Pin Description (Continued)

The following pin function descriptions are for 80C88 system in maximum mode (i.e., MN/MX = GND). Only the pin functions which

are unique to the maximum mode are described; all other pin functions are as described above.

SYMBOL

NUMBER

TYPE

DESCRIPTION

MAXIMUM MODE SYSTEM (i.e., MN/MX = GND).

QS1, QS0

24, 25

O

QUEUE STATUS: provide status to allow external

QS1 QS0

CHARACTERISTICS

No Operation

tracking of the internal 80C88 instruction queue.

The queue status is valid during the CLK cycle after

which the queue operation is performed. Note that the

queue status never goes to a high impedance statue

(floated).

0

1

First Byte of Opcode from

Queue

1

0

1

Empty the Queue

Subsequent Byte from

Queue

34

O

Pin 34 is always a logic one in the maximum mode and is held at a high impedance logic one during a “grant

sequence”.

this unit serves to increase processor performance through

improved bus bandwidth utilization. Up to 4-bytes of the

instruction stream can be queued while waiting for decoding

Functional Description

Static Operation

All 80C88 circuitry is static in design. Internal registers,

counters and latches are static and require not refresh as

with dynamic circuit design. This eliminates the minimum

operating frequency restriction placed on other

microprocessors. The CMOS 80C88 can operate from DC to

the specified upper frequency limit. The processor clock may

be stopped in either state (high/low) and held there

indefinitely. This type of operation is especially useful for

system debug or power critical applications.

and execution.

The instruction stream queuing mechanism allows the BIU to

keep the memory utilized very efficiently. Whenever there is

space for at least 1-byte in the queue, the BIU will attempt a

byte fetch memory cycle. This greatly reduces “dead time”:

on the memory bus. The queue acts as a First-In-First-Out

(FIFO) buffer, from which the EU extracts instruction bytes

as required. If the queue is empty (following a branch

instruction, for example), the first byte into the queue

immediately becomes available to the EU.

The 80C88 can be single stepped using only the CPU clock.

This state can be maintained as long as is necessary. Single

step clock operation allows simple interface circuitry to

provide critical information for start-up.

The execution unit receives pre-fetched instructions from the

BIU queue and provides unrelocated operand addresses to

the BIU. Memory operands are passed through the BIU for

processing by the EU, which passes results to the BIU for

storage.

Static design also allows very low frequency operation (as

low as DC). In a power critical situation, this can provide

extremely low power operation since 80C88 power

dissipation is directly related to operation frequency. As the

system frequency is reduced, so is the operating power until,

at a DC input frequency, the power requirement is the 80C88

standby current.

Memory Organization

The processor provides a 20-bit address to memory which

locates the byte being referenced. The memory is organized

as a linear array of up to 1 million bytes, addressed as

00000(H) to FFFFF(H). The memory is logically divided into

code, data, extra, and stack segments of up to 64-bytes

each, with each segment falling on 16-byte boundaries. (See

Figure 1).

Internal Architecture

The internal functions of the 80C88 processor are partitioned

logically into two processing units. The first is the Bus

Interface Unit (BIU) and the second is the Execution Unit

(EU) as shown in the CPU block diagram.

These units can interact directly but for the most part

perform as separate asynchronous operational processors.

The bus interface unit provides the functions related to

instruction fetching and queuing, operand fetch and store,

and address relocation. This unit also provides the basic bus

control. The overlap of instruction pre-fetching provided by

FN2949.4

February 22, 2008

7

80C88

.

Certain locations in memory are reserved for specific CPU

operations. (See Figure 2). Locations from addresses

FFFF0H through FFFFFH are reserved for operations

including a jump to initial system initialization routine.

Following RESET, the CPU will always begin execution at

location FFFF0H where the jump must be located. Locations

00000H through 003FFH are reserved for interrupt

7

0

FFFFFH

64K-BIT

CODE SEGMENT

XXXXOH

operations. Each of the 256 possible interrupt service

routines is accessed through its own pair of 16-bit pointers -

segment address pointer and offset address pointer. The

first pointer, used as the offset address, is loaded into the IP,

and the second pointer, which designates the base address,

is loaded into the CS. At this point program control is

transferred to the interrupt routine. The pointer elements are

assumed to have been stored at their respective places in

reserved memory prior to the occurrence of interrupts.

STACK SEGMENT

DATA SEGMENT

+ OFFSET

WORD

SEGMENT

REGISTER FILE

LSB

BYTE

MSB

CS

SS

DS

ES

Minimum and Maximum Modes

EXTRA SEGMENT

00000H

The requirements for supporting minimum and maximum

80C88 systems are sufficiently different that they cannot be

done efficiently with 40 uniquely defined pins. Consequently,

the 80C88 is equipped with a strap pin (MN/MX) which

defines the system configuration. The definition of a certain

subset of the pins changes, dependent on the condition of

the strap pin. When the MN/MX pin is strapped to GND, the

80C88 defines pins 24 through 31 and 34 in maximum

mode. When the MN/MX pins is strapped to V_CC, the 80C88

generates bus control signals itself on pins 24 through 31

and 34.

FIGURE 1. MEMORY ORGANIZATION

All memory references are made relative to base addresses

contained in high speed segment registers. The segment

types were chosen based on the addressing needs of

programs. The segment register to be selected is

automatically chosen according to specific rules as shown in

Table1. All information in one segment type share the same

logical attributes (e.g., code or data). By structuring memory

into relocatable areas of similar characteristics and by

automatically selecting segment registers, programs are

shorter, faster, and more structured.

The minimum mode 80C88 can be used with either a

muliplexed or demultiplexed bus. This architecture provides

the 80C88 processing power in a highly integrated form.

TABLE 1.

MEMORY

REFERENCE

NEED

SEGMENT

REGISTER

USED

The demultiplexed mode requires one latch (for 64k address

ability) or two latches (for a full megabyte of addressing). An

82C86 or 82C87 transceiver can also be used if data bus

buffering is required. (See Figure 3). The 80C88 provides

DEN and DT/R to control the transceiver, and ALE to latch

the addresses. This configuration of the minimum mode

provides the standard demultiplexed bus structure with

heavy bus buffering and relaxed bus timing requirements.

SEGMENT

SELECTION RULE

Instructions

CODE (CS)

Automatic with all instruction

prefetch.

Stack

STACK (SS) All stack pushes and pops.

Memory references relative to

BP base register except data

references.

The maximum mode employs the 82C88 bus controller (See

Figure 4). The 82C88 decode status lines S0, S1 and S2,

and provides the system with all bus control signals. Moving

the bus control to the 82C88 provides better source and sink

current capability to the control lines, and frees the 80C88

pins for extended large system features. Hardware lock,

queue status, and two request/grant interfaces are provided

by the 80C88 in maximum mode. These features allow

coprocessors in local bus and remote bus configurations.

Local Data

DATA (DS)

Data references when: relative

to stack, destination of string

operation, or explicitly

overridden.

External Data

(Global)

EXTRA (ES) Destination of string

operations: Explicitly selected

using a segment override.

Word (16-bit) operands can be located on even or odd

address boundaries. For address and data operands, the

least significant byte of the word is stored in the lower valued

address location and the most significant byte in the next

higher address location.

The BIU will automatically execute two fetch or write cycles

for 16-bit operands.

FN2949.4

February 22, 2008

8

80C88

FFFFFH

FFFF0H

RESET BOOTSTRAP

PROGRAM JUMP

TYPE 255 POINTER

(AVAILABLE)

3FFH

3FCH

AVAILABLE

INTERRUPT

POINTERS

(224)

TYPE 33 POINTER

(AVAILABLE)

084H

080H

07FH

TYPE 32 POINTER

(AVAILABLE)

TYPE 31 POINTER

(AVAILABLE)

RESERVED

INTERRUPT

POINTERS

(27)

TYPE 5 POINTER

(RESERVED)

014H

TYPE 4 POINTER

OVERFLOW

010H

00CH

008H

004H

000H

TYPE 3 POINTER

1 BYTE INT INSTRUCTION

DEDICATED

INTERRUPT

POINTERS

(5)

TYPE 2 POINTER

NON MASKABLE

TYPE 1 POINTER

SINGLE STEP

TYPE 0 POINTER

DIVIDE ERROR

CS BASE ADDRESS

IP OFFSET

16-BITS

FIGURE 2. RESERVED MEMORY LOCATIONS

During T1 of any bus cycle, the ALE (Address latch enable)

Bus Operation

signal is emitted (by either the processor or the 82C88 bus

controller, depending on the MN/MX strap). At the trailing

edge of this pulse, a valid address and certain status

information for the cycle may be latched.

The 80C88 address/data bus is broken into three parts: the

lower eight address/data bits (AD0-AD7), the middle eight

address bits (A8-A15), and the upper four address bits (A16-

A19). The address/data bits and the highest four address

bits are time multiplexed. This technique provides the most

efficient use of pins on the processor, permitting the use of

standard 40 lead package. The middle eight address bits are

not multiplexed, i.e., they remain valid throughout each bus

cycle. In addition, the bus can be demultiplexed at the

processor with a single address latch if a standard, non

multiplexed bus is desired for the system.

Status bits S0, S1, and S2 are used by the bus controller, in

maximum mode, to identify the type of bus transaction

according to Table 2.

Status bits S3 through S6 are multiplexed with high order

address bits and are therefore valid during T2 through T4.

S3 and S4 indicate which segment register was used to this

bus cycle in forming the address according to Table 3.

Each processor bus cycle consists of at least four CLK

cycles. These are referred to as T1, T2, T3 and T4. (See

Figure 5). The address is emitted from the processor during

T1 and data transfer occurs on the bus during T3 and T4. T2

is used primarily for changing the direction of the bus during

read operations. In the event that a “Not Ready” indication is

given by the addressed device, “wait” states (TW) are

inserted between T3 and T4. Each inserted “wait” state is of

the same duration as a CLK cycle. Periods can occur

between 80C88 driven bus cycles. These are referred to as

“idle” states (TI), or inactive CLK cycles. The processor uses

these cycles for internal housekeeping.

S5 is a reflection of the PSW interrupt enable bit. S6 is

always equal to 0.

FN2949.4

February 22, 2008

9

80C88

V

CC

V

MN/MX

IO/M

CC

82C84A/85

CLK

RD

READY

RESET

RES

RDY

WR

CLOCK

GENERATOR

INTA

DT/R

DEN

GND

80C88

CPU

STB

OE

ALE

1

GND

ADDR/DATA

AD0-AD7

A8-A19

C1

C2

ADDRESS

V

82C82

CC

20

LATCH

GND

(1, 2 OR 3)

40

V

CC

T

C1 = C2 = 0.1μF

INTR

OE

DATA

82C86

TRANSCEIVER

OE CS

RDWR

EN

82C59A

HM-65162

HS-6616

INTERRUPT

CONTROL

82CXX

PERIPHERALS

CMOS PROM CMOS PROM

INT

IR0-7

FIGURE 3. DEMULTIPLEXED BUS CONFIGURATION

V

CC

CLK

S0

GND

MRDC

MWTC

AMWC

IORC

IOWC

AIOWC

INTA

MN/MX

S0

82C84A/85

CLK

82C88

NC

READY

RESET

RES

RDY

S1

S2

S1

S2

DEN

DT/R

ALE

GND

80C88

CPU

STB

OE

1

GND

ADDR/DATA

AD0-AD7

A8-A19

GND

C1

20

ADDRESS

V

82C82

LATCH

(1, 2 OR 3)

CC

C2

40

V

CC

T

C1 = C2 = 0.1μF

INT

OE

DATA

82C86

TRANSCEIVER

OE CS

RDWR

82C59A

INTERRUPT

CONTROL

HM-65162

HS-6616

82CXX

PERIPHERALS

CMOS PROM CMOS PROM

IR0-7

FIGURE 4. FULLY BUFFERED SYSTEM USING BUS CONTROLLER

FN2949.4

February 22, 2008

10

80C88

(4 + NWAIT) = TCY

T3 TWAIT

(4 + NWAIT) = TCY

T3 TWAIT

T1

T2

T4

T1

T2

T4

CLK

GOES INACTIVE IN THE STATE

JUST PRIOR TO T4

ALE

S2-S0

ADDR

STATUS

A19-A16

S6-S3

A15-A8

ADDR

D15-D0

VALID

BUS RESERVED

FOR DATA IN

ADDR DATA

A7-A0

DATA OUT (D7-D0)

RD, INTA

READY

WAIT

DT/R

DEN

WP

MEMORY ACCESS TIME

FIGURE 5. BASIC SYSTEM TIMING

TABLE 2.

TABLE 3.

S2

0

S1

0

S0

CHARACTERISTICS

Interrupt Acknowledge

S4

0

S3

0

CHARACTERISTICS

0

1

0

1

0

1

0

1

Alternate Data (Extra Segment)

0

Read I/O

0

1

Stack

0

1

Write I/O

1

0

Code or None

Data

0

1

Halt

1

0

Instruction Fetch

Read Data from Memory

Write Data to Memory

Passive (No Bus Cycle)

1

0

I/O Addressing

1

In the 80C88, I/O operations can address up to a maximum

of 64k I/O registers. The I/O address appears in the same

format as the memory address on bus lines A15-A0. The

address lines A19-A16 are zero in I/O operations. The

variable I/O instructions, which use register DX as a pointer,

have full address capability, while the direct I/O instructions

directly address one or two of the 256 I/O byte locations in

page 0 of the I/O address space. I/O ports are addressed in

the same manner as memory locations.

1

FN2949.4

February 22, 2008

11

80C88

Designers familiar with the 8085 or upgrading an 8085

design should note that the 8085 addresses I/O with an 8-bit

address on both halves of the 16-bit address bus. The

80C88 uses a full 16-bit address on its lower 16 address

lines.

appropriate element to the new interrupt service program

location.

EXTERNAL

BOND

PAD

OUTPUT

DRIVER

External Interface

INPUT

BUFFER

Processor Reset and Initialization

INPUT

Processor initialization or start up is accomplished with

activation (HIGH) of the RESET pin. The 80C88 RESET is

required to be HIGH for greater than four clock cycles. The

80C88 will terminate operations on the high-going edge of

RESET and will remain dormant as long as RESET is HIGH.

The low-going transition of RESET triggers an internal reset

sequence for approximately 7 clock cycles. After this interval

the 80C88 operates normally, beginning with the instruction

in absolute location FFFFOH (see Figure 2). The RESET

input is internally synchronized to the processor clock. At

initialization, the HIGH to LOW transition of RESET must

occur no sooner than 50μs after power up, to allow complete

initialization of the 80C88.

PROTECTION

CIRCUITRY

FIGURE 6A. BUS HOLD CIRCUITRY PINS 2-16 AND 35-39

EXTERNAL

BOND

PAD

V

P

CC

OUTPUT

DRIVER

INPUT

BUFFER

INPUT

PROTECTION

CIRCUITRY

FIGURE 6B. BUS HOLD CIRCUITRY PINS 26-32 AND 34

FIGURE 6.

NMI will not be recognized if asserted prior to the second

CLK cycle following the end of RESET.

Bus Hold Circuitry

Non-Maskable Interrupt (NMI)

To avoid high current conditions caused by floating inputs to

CMOS devices and to eliminate the need for pull-up/down

resistors, “bus-hold” circuitry has been used on 80C88 pins

2-16, 26-32 and 34-39 (see Figure 6A and 6B). These

circuits maintain a valid logic state if no driving source is

present (i.e., an unconnected pin or a driving source which

goes to a high impedance state).

The processor provides a single non-maskable interrupt

(NMI) pin which has higher priority than the maskable

interrupt request (INTR) pin. A typical use would be to

activate a power failure routine. The NMI is edge-triggered

on a LOW to High transition. The activation of this pin

causes a type 2 interrupt.

NMI is required to have a duration in the HIGH state of

greater than two clock cycles, but is not required to be

synchronized to the clock. An high going transition of NMI is

latched on-chip and will be serviced at the end of the current

instruction or between whole moves (2-bytes in the case of

word moves) of a block type instruction. Worst case

response to NMI would be for multiply, divide, and variable

shift instructions. There is no specification on the occurrence

of the low-going edge; it may occur before, during, or after

the servicing of NMI. Another high-going edge triggers

another response if it occurs after the start of the NMI

procedure.

To override the “bus hold” circuits, an external driver must be

capable of supplying 400μA minimum sink or source current

at valid input voltage levels. Since this “bus hold” circuitry is

active and not a “resistive” type element, the associated

power supply current is negligible. Power dissipation is

significantly reduced when compared to the use of passive

pull-up resistors.

Interrupt Operations

Interrupt operations fall into two classes: software or

hardware initiated. The software initiated interrupts and

software aspects of hardware interrupts are specified in the

instruction set description. Hardware interrupts can be

classified as nonmusical or maskable.

The signal must be free of logical spikes in general and be

free of bounces on the low-going edge to avoid triggering

extraneous responses.

Interrupts result in a transfer of control to a new program

location. A 256 element table containing address pointers to

the interrupt service program locations resides in absolute

locations 0 through 3FFH (see Figure 2), which are reserved

for this purpose. Each element in the table is 4-bytes in size

and corresponds to an interrupt “type”. An interrupting

device supplies an 8-bit type number, during the interrupt

acknowledge sequence, which is used to vector through the

Maskable Interrupt (INTR)

The 80C88 provides a singe interrupt request input (INTR)

which can be masked internally by software with the

resetting of the interrupt enable (IF) flag bit. The interrupt

request signal is level triggered. It is internally synchronized

during each clock cycle on the high-going edge of CLK.

FN2949.4

February 22, 2008

12

80C88

To be responded to, INTR must be present (HIGH) during

the clock period preceding the end of the current instruction

or the end of a whole move for a block type instruction. INTR

may be removed anytime after the falling edge of the first

INTA signal. During interrupt response sequence, further

interrupts are disabled. The enable bit is reset as part of the

response to any interrupt (INTR, NMI, software interrupt, or

single step). The FLAGS register, which is automatically

pushed onto the stack, reflects the state of the processor

prior to the interrupt. The enable bit will be zero until the old

FLAGS register is restored, unless specifically set by an

instruction.

An interrupt request or RESET will force the 80C88 out of

the HALT state.

Read/Modify/Write (Semaphore) Operations Via

LOCK

The LOCK status information is provided by the processor

when consecutive bus cycles are required during the

execution of an instruction. This allows the processor to

perform read/modify/write operations on memory (via the

“exchange register with memory” instruction), without

another system bus master receiving intervening memory

cycles. This is useful in multiprocessor system

configurations to accomplish “test and set lock” operations.

The LOCK signal is activated (LOW) in the clock cycle

following decoding of the LOCK prefix instruction. It is

deactivated at the end of the last bus cycle of the instruction

following the LOCK prefix. While LOCK is active, a request

on a RQ/GT pin will be recorded, and then honored at the

end of the LOCK.

During the response sequence (see Figure 7), the processor

executes two successive (back-to-back) interrupt

acknowledge cycles. The 80C88 emits to LOCK signal

(maximum mode only) from T2 of the first bus cycle until T2

of the second. A local bus “hold” request will not be honored

until the end of the second bus cycle. In the second bus

cycle, a byte is fetched from the external interrupt system

(e.g., 82C59A PIC) which identifies the source (type) of the

interrupt. This byte is multiplied by four and used as a

pointer into the interrupt vector lookup table.

External Synchronization Via TEST

As an alternative to interrupts, the 80C88 provides a single

software-testable input pin (TEST). This input is utilized by

executing a WAIT instruction. The single WAIT instruction is

repeatedly executed until the TEST input goes active (LOW).

The execution of WAIT does not consume bus cycles once

the queue is full.

An INTR signal left HIGH will be continually responded to

within the limitations of the enable bit and sample period.

INTR may be removed anytime after the falling edge of the

first INTA signal. The interrupt return instruction includes a

flags pop which returns the status of the original interrupt

enable bit when it restores the flags.

If a local bus request occurs during WAIT execution, the

80C88 three-states all output drivers while inputs and I/O

pins are held at valid logic levels by internal bus-hold

circuits. If interrupts are enabled, the 80C88 will recognize

interrupts and process them when it regains control of the

bus.

T1

T3

T1

T2

T3

T4

T2

T4

ALE

Basic System Timing

LOCK

In minimum mode, the MN/MX pin is strapped to V_CCand

the processor emits bus control signals (RD, WR, IO/M, etc.)

directly. In maximum mode, the MN/MX pin is strapped to

GND and the processor emits coded status information

which the 82C88 bus controller uses to generate

INTA

AD0-

AD7

TYPE

VECTOR

MULTIBUS™ compatible bus control signals.

System Timing - Minimum System

FIGURE 7. INTERRUPT ACKNOWLEDGE SEQUENCE

The read cycle begins in T1 with the assertion of the address

latch enable (ALE) signal (see Figure 5). The trailing (low

going) edge of this signal is used to latch the address

information, which is valid on the address data bus (ADO-

AD7) at this time, into the 82C82/82C83 latch. Address lines

A8 through A15 do not need to be latched because they

remain valid throughout the bus cycle. From T1 to T4 the

IO/M signal indicates a memory or I/O operation. At T2 the

address is removed from the address data bus and the bus

is held at the last valid logic state by internal bus-hold

devices. The read control signal is also asserted at T2. The

read (RD) signal causes the addressed device to enable its

data bus drivers to the local bus. Some time later, valid data

Halt

When a software HALT instruction is executed, the

processor indicates that it is entering the HALT state in one

of two ways, depending upon which mode is strapped. In

minimum mode, the processor issues ALE, delayed by one

clock cycle, to allow the system to latch the halt status. Halt

status is available on IO/M, DT/R, and SS0. In maximum

mode, the processor issues appropriate HALT status on S2,

S1 and S0, and the 82C88 bus controller issues one ALE.

The 80C88 will not leave the HALT state when a local bus

hold is entered while in HALT. In this case, the processor

reissues the HALT indicator at the end of the local bus hold.

FN2949.4

February 22, 2008

13

80C88

will be available on the bus and the addressed device will

drive the READY line HIGH. When the processor returns the

read signal to a HIGH level, the addressed device will again

three-state its bus drivers. If a transceiver (82C86/82C87) is

required to buffer the local bus, signals DT/R and DEN are

provided by the 80C88.

disabled when reading from the master 82C59A during the

interrupt acknowledge sequence and software “poll”.

The 80C88 Compared to the 80C86

The 80C88 CPU is a 8-bit processor designed around the

8086 internal structure. Most internal functions of the 80C88

are identical to the equivalent 80C86 functions. The 80C88

handles the external bus the same way the 80C86 does with

the distinction of handling only 8-bits at a time. Sixteen-bit

operands are fetched or written in two consecutive bus

cycles. Both processors will appear identical to the software

engineer, with the exception of execution time. The internal

register structure is identical and all instructions have the

same end result. Internally, there are three differences

between the 80C88 and the 80C86. All changes are related

to the 8-bit bus interface.

A write cycle also begins with the assertion of ALE and the

emission of the address. The IO/M signal is again asserted

to indicate a memory or I/O write operation. In T2,

immediately following the address emission, the processor

emits the data to be written into the addressed location. This

data remains valid until at least the middle of T4. During T2,

T3, and Tw, the processor asserts the write control signal.

The write (WR) signal becomes active at the beginning of

T2, as opposed to the read, which is delayed somewhat into

T2 to provide time for output drivers to become inactive.

• The queue length is 4-bytes in the 80C88, whereas the

80C86 queue contains 6-bytes, or three words. The queue

was shortened to prevent overuse of the bus by the BIU

when prefetching instructions. This was required because

of the additional time necessary to fetch instructions 8-bits

at a time.

The basic difference between the interrupt acknowledge

cycle and a read cycle is that the interrupt acknowledge

(INTA) signal is asserted in place of the read (RD) signal and

the address bus is held at the last valid logic state by internal

bus-hold devices (see Figure 6. In the second of two

successive INTA cycles, a byte of information is read from

the data bus, as supplied by the interrupt system logic (i.e.,

82C59A priority interrupt controller). This byte identifies the

source (type) of the interrupt. It is multiplied by four and used

as a pointer into the interrupt vector lookup table, as

described earlier.

• To further optimize the queue, the prefetching algorithm

was changed. The 80C88 BIU will fetch a new instruction

to load into the queue each time there is a 1-byte space

available in the queue. The 80C86 waits until a 2-byte

space is available.

The internal execution time of the instruction set is affected

by the 8-bit interface. All 16-bit fetches and writes from/to

memory take an additional four clock cycles. The CPU is

also limited by the speed of instruction fetches. This latter

problem only occurs when a series of simple operations

occur. When the more sophisticated instructions of the

80C88 are being used, the queue has time to fill the

execution proceeds as fast as the execution unit will allow.

Bus Timing - Medium Complexity Systems

For medium complexity systems, the MN/MX pin is

connected to GND and the 82C88 bus controller is added to

the system, as well as an 82C82/82C83 latch for latching the

system address, and an 82C86/82C87 transceiver to allow

for bus loading greater than the 80C88 is capable of

handling (see Figure 8). Signals ALE, DEN, and DT/R are

generated by the 82C88 instead of the processor in this

configuration, although their timing remains relatively the

same. The 80C88 status outputs (S2, S1 and S0) provide

type of cycle information and become 82C88 inputs. This

bus cycle information specifies read (code, data or I/O), write

(data or I/O), interrupt acknowledge, or software halt. The

82C88 thus issues control signals specifying memory read

or write, I/O read or write, or interrupt acknowledge. The

82C88 provides two types of write strobes, normal and

advanced, to be applied as required. The normal write

strobes have data valid at the leading edge of write. The

advanced write strobes have the same timing as read

strobes, and hence, data is not valid at the leading edge of

write. The 82C86/82C87 transceiver receives the usual T

and OE inputs from the 82C88 DT/R and DEN outputs.

The 80C88 and 80C86 are completely software compatible

by virtue of their identical execution units. Software that is

system dependent may not be completely transferable, but

software that is not system dependent will operate equally as

well on an 80C88 or an 80C86.

The hardware interface of the 80C88 contains the major

differences between the two CPUs. The pin assignments are

nearly identical, however, with the following functional

changes:

• A8-A15: These pins are only address outputs on the

80C88. These address lines are latched internally and

remain valid throughout a bus cycle in a manner similar to

the 8085 upper address lines.

• BHE has no meaning on the 80C88 and has been

eliminated.

The pointer into the interrupt vector table, which is passed

during the second INTA cycle, can derive from an 82C59A

located on either the local bus or the system bus. If the

master 82C59A priority interrupt controller is positioned on

the local bus, the 82C86/82C87 transceiver must be

• SS0 provides the S0 status information in the minimum

mode. This output occurs on pin 34 in minimum mode

FN2949.4

February 22, 2008

14

80C88

only. DT/R, IO/M and SS0 provide the complete bus status

in minimum mode.

• IO/M has been inverted to be compatible with the 8085

bus structure.

• ALE is delayed by one clock cycle in the minimum mode

when entering HALT, to allow the status to be latched with

ALE.

T1

T2

T3

T4

CLK

QS1, QS0

80C88

S2, S1, S0

A19/S6 - A16/S3

ALE

A19 - A16

S6 - S3

RDY 82C84

80C88

READY 80C88

AD7 - AD0

DATA OUT

A7-A0

DATA IN

A15 - A8

80C88

RD

DT/R

80C88

MRDC

DEN

FIGURE 8. MEDIUM COMPLEXITY SYSTEM TIMING

FN2949.4

February 22, 2008

15

80C88

Absolute Maximum Ratings

Thermal Information

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V

Input, Output or I/O Voltage . . . . . . . . . . . GND - 0.5V to V_CC+ 0.5V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

Thermal Resistance (Typical) . . . . . . . . . . . . . . . . . . . . . .θ_JA(^oC/W)

PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

CERDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Maximum Junction Temperature

Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C

Plastic Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

Storage Temperature Range . . . . . . . . . . . . . . . . . -65°C to +150°C

Pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . . . see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

*Pb-free PDIPs can be used for through hole wave solder processing

only. They are not intended for use in Reflow solder processing applica-

tions.

Operating Conditions

Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V

M80C88-2 Only . . . . . . . . . . . . . . . . . . . . . . . . . +4.75V to +5.25V

Operating Temperature Range

C80C88/-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

I80C88/-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

M80C88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C

Die Characteristics

Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9750 Gates

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

Electrical Specifications V_CC= 5.0V, ±10%; T_A= 0°C to +70°C (C80C88, C80C88-2)

V

_CC= 5.0V, ±10%; T_A= -40°C to +85°C (l80C88, I80C88-2)

_CC= 5.0V, ±10%; T_A= -55°C to +125°C (M80C88)

SYMBOL

PARAMETER

TEST CONDITION

C80C88, I80C88 (Note 4)

M80C88 (Note 4)

MIN

MAX

UNITS

V_lH

Logical One Input Voltage

2.0

-

V

2.2

V_IL

Logical Zero Input Voltage

CLK Logical One Input Voltage

CLK Logical Zero Input Voltage

Output High Voltage

-

0.8

-

V

VIHC

VILC

V_OH

V_CC- 0.8

V

-

3.0

0.8

-

V

lOH = -2.5mA

lOH = -100µA

lOL = +2.5mA

V

V_CC- 0.4

-

V

V_OL

I_I

Output Low Voltage

0.4

1.0

V

Input Leakage Current

V_IN= 0V or V_CC

-1.0

µA

Pins 17 thru 19, 21 thru 23 and 33

lBHH

lBHL

Input Current-Bus Hold High

Input Current-Bus Hold Low

Output Leakage Current

V_IN= - 3.0V (Note 1)

-40

-400

400

-10.0

500

10

µA

V

_IN= - 0.8V (Note 2)

V_OUT= 0V (Note 5)

_CC= 5.5V (Note 3)

40

-

I_O

µA

ICCSB

ICCOP

Standby Power Supply Current

Operating Power Supply Current

V

-

µA

FREQ = Max, V_IN= V_CCor GND,

Outputs Open

-

mA/MHz

NOTES:

1. lBHH should be measured after raising V_INto V_CCand then lowering to 3.0V on the following pins 2 thru16, 26 thru 32, 34 thru 39.

2. IBHL should be measured after lowering V_INto GND and then raising to 0.8V on the following pins: 2 thru16, 35 thru 39.

3. lCCSB tested during clock high time after HALT instruction executed. V_IN= V_CCor GND, V_CC= 5.5V, Outputs unloaded.

4. MN/MX is a strap option and should be held to V_CCor GND.

5. IO should be measured by putting the pin in a high impedance state and then driving V_OUTto GND on the following pins: 26-29 and 32.

Capacitance T_A= +25°C

SYMBOL

C_IN

PARAMETER

Input Capacitance

TEST CONDITIONS

TYPICAL

UNITS

pF

FREQ = 1MHz. All measurements are referenced to device GND

25

C_OUT

CI/O

Output Capacitance

I/O Capacitance

pF

FN2949.4

February 22, 2008

16

80C88

AC Electrical Specifications V_CC= 5.0V ±10%; T_A= 0°C to +70°C (C80C88, C80C88-2)

V_CC= 5.0V ±10%; T_A= -40°C to +85°C (I80C88, I80C88-2)

V_CC= 5.0V ±10%; T_A= -55° to +125°C (M80C88)

80C88

TEST

80C88-2

MIN

SYMBOL

PARAMETER

CONDITIONS

MIN

MAX

UNITS

MINIMUM COMPLEXITY SYSTEM

Timing Requirements

(1)

(2)

(3)

(4)

(5)

(6)

(7)

(8)

TCLCL

TCLCH

TCHCL

CLK Cycle Period

CLK Low Time

CLK High Time

200

118

69

-

125

68

44

-

ns

-

TCH1CH2 CLK Rise Time

TCL2CL1 CLK FaIl Time

From 1.0V to 3.5V

From 3.5V to 1.0V

10

-

10

-

TDVCL

Data In Setup Time

30

10

35

20

10

35

TCLDX1 Data In Hold Time

-

TR1VCL

TCLR1X

RDY Setup Time into 82C84A

(Notes 6,7)

-

(9)

RDY Hold Time into 82C84A

(Notes 6,7)

0

-

0

-

ns

(10)

(11)

(12)

(13)

(14)

TRYHCH READY Setup Time into 80C88

TCHRYX READY Hold Time into 80C88

TRYLCL READY Inactive to CLK (Note 8)

118

30

-8

-

68

20

-8

-

ns

THVCH

TINVCH

HOLD Setup Time

35

30

20

15

lNTR, NMI, TEST Setup Time

(Note 7)

(15)

(16)

TILIH

TIHIL

Input Rise Time (Except CLK)

Input FaIl Time (Except CLK)

From 0.8V to 2.0V

From 2.0V to 0.8V

-

15

-

15

ns

Timing Responses

(17)

(18)

(19)

(20)

(21)

(22)

(23)

(24)

(25)

TCLAV

TCLAX

TCLAZ

TCHSZ

TCHSV

TLHLL

TCLLH

TCHLL

TLLAX

Address Valid Delay

Address Hold Time

Address Float Delay

Status Float Delay

Status Active Delay

ALE Width

CL = 100pF

10

110

-

10

60

-

ns

10

TCLAX

80

110

-

TCLAX

50

60

-

10

TCLCH-20

TCLCH-10

ALE Active Delay

ALE Inactive Delay

-

80

85

-

50

55

-

Address Hold Time to ALE

Inactive

TCHCL-10

(26)

(27)

(28)

(29)

(30)

(31)

(32)

TCLDV

TCLDX2

TWHDX

TCVCTV

Data Valid Delay

CL = 100pF

10

110

-

10

60

-

ns

Data Hold Time

10

Data Hold Time After WR

Control Active Delay 1

TCLCL-30

-

TCLCL-30

-

10

0

110

-

10

0

70

60

70

-

TCHCTV Control Active Delay 2

TCVCTX

TAZRL

Control Inactive Delay

Address Float to READ Active

FN2949.4

February 22, 2008

17

80C88

AC Electrical Specifications V_CC= 5.0V ±10%; T_A= 0°C to +70°C (C80C88, C80C88-2)

V_CC= 5.0V ±10%; T_A= -40°C to +85°C (I80C88, I80C88-2)

V_CC= 5.0V ±10%; T_A= -55° to +125°C (M80C88) (Continued)

80C88

TEST

80C88-2

MIN

SYMBOL

TCLRL

PARAMETER

RD Active Delay

CONDITIONS

MIN

MAX

165

150

-

MAX

100

80

UNITS

ns

(33)

(34)

(35)

CL = 100pF

10

TCLRH

TRHAV

RD Inactive Delay

CL = 100pF

10

ns

RD Inactive to Next Address

Active

CL = 100pF

TCLCL-45

TCLCL-40

-

ns

(36)

(37)

TCLHAV

TRLRH

TWLWH

TAVAL

HLDA Valid Delay

RD Width

CL = 100pF

10

160

-

10

100

-

ns

CL = 100pF

2TCLCL-75

2TCLCL-50

(38)

WR Width

CL = 100pF

2TCLCL-60

-

2TCLCL-40

-

(39)

Address Valid to ALE Low

Output Rise Time

Output Fall Time

CL = 100pF

TCLCH-60

-

TCLCH-40

-

(40)

TOLOH

TOHOL

From 0.8V to 2.0V

From 2.0V to 0.8V

-

15

-

15

(41)

NOTES:

6. Signal at 82C84A shown for reference only.

7. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.

8. Applies only to T2 state (8ns into T3).

FN2949.4

February 22, 2008

18

80C88

Waveforms

T1

T2

T3

(5)

TCL2CL1

T4

TW

(2)

(1)

TCLCL

TCH1CH2

(4)

CLK (82C84A OUTPUT)

(3)

TCHCTV

(30)

TCLCH

TCHCL

(30) TCHCTV

IO/M, SSO

(17)

TCLAV

A15-A8

A15-A8 (FLOAT DURING INTA)

(17)

TCLAV

(17)

TCLAV

(26) TCLDV

(18) TCLAX

S6-S3

A19-A16

TLHLL

A19/S6-A16/S3

(23) TCLLH

(22)

TLLAX

(25)

ALE

(24)

TR1VCL (8)

TCLR1X (9)

TCHLL

V

IH

RDY (82C84A INPUT)

SEE NOTE 9, 10

TAVAL

(39)

V

IL

(12)

TRYLCL

(11)

TCHRYX

READY (80C88 INPUT)

(10)

TRYHCH

(7)

TCLDX1

(19)

TCLAZ

(16)

TDVCL

AD7-AD0

DATA IN

(34) TCLRH

AD7-AD0

(35)

TRHAV

(32) TAZRL

RD

(30)

TCHCTV

(30)

TCHCTV

READ CYCLE

TRLRH

(37)

TCLRL

(33)

(WR, INTA = V

)

OH

DT/R

DEN

(29) TCVCTV

TCVCTX

(31)

FIGURE 9. BUS TIMING - MINIMUM MODE SYSTEM

NOTES:

9. RDY is sampled near the end of T2, T3, TW to determine if TW machine states are to be inserted.

10. Signals at 82C84A are shown for reference only.

FN2949.4

February 22, 2008

19

80C88

Waveforms (Continued)

T1

T2

T3

(5)

TCL2CL1

TW

T4

(4)

TCH1CH2

TW

CLK (82C84A OUTPUT)

AD7-AD0

(26)

TCLDV

TCLAX

(27)

TCLDX2

(17)

TCLAV

(18)

AD7-AD0

DATA OUT

TWHDX

(28)

(29)

TCVCTV

(31) TCVCTX

DEN

WR

WRITE CYCLE

(29) TCVCTV

(38)

TWLWH

TCVCTX

TDVCL

(31)

(6)

(19)

TCLAZ

TCLDX1 (7)

POINTER

AD7-AD0

TCHCTV (30)

TCHCTV

(30)

DT/R

INTA

INTA CYCLE

(NOTE 11)

(29) TCVCTV

RD, WR = V

OH

TCVCTX

(31)

(29) TCVCTV

DEN

SOFTWARE

HALT -

INVALID ADDRESS

SOFTWARE HALT

AD7-AD0

ALE

DEN, RD,

TCLAV

(17)

WR, INTA = V

OH

TCHLL

(24)

TCLLH

(23)

TCHCTV

(30)

TCVCTX

(31)

IO/M

DT/R

SSO

FIGURE 10. BUS TIMING - MINIMUM MODE SYSTEM (Continued)

NOTES:

1. Two INTA cycles run back-to-back. The 80C88 local ADDR/DATA bus is floating during both INTA cycles. Control signals are shown for the

second INTA cycle.

2. Signals at 82C84A are shown for reference only.

FN2949.4

February 22, 2008

20

80C88

AC Electrical Specifications V_CC= 5.0V±10%; T_A= 0°C to +70°C (C80C88, C80C88-2)

V

_CC= 5.0V±10%; T_A= -40°C to +85°C (I80C88, I80C88-2)

_CC= 5.0V±10%; T_A= -55°C to +125°C (M80C88)

MAX MODE SYSTEM (USING 82C88 BUS CONTROLLER)

80C88

MAX

80C88-2

MAX

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

UNITS

TIMING REQUIREMENTS

(1)

(2)

(3)

(4)

(5)

(6)

(7)

(8)

TCLCL

TCLCH

TCHCL

CLK Cycle Period

200

118

69

-

125

68

44

-

ns

CLK Low Time

CLK High Time

-

TCH1CH2 CLK Rise Time

TCL2CL1 CLK Fall Time

From 1.0V to 3.5V

From 3.5V to 1.0V

10

-

10

-

TDVCL

TCLDX1

TR1VCL

Data in Setup Time

Data In Hold Time

30

10

35

20

10

35

-

RDY Setup Time into 82C84

(Notes 13,14)

-

(9)

TCLR1X

RDY Hold Time into 82C84

(Notes 13,14)

0

-

0

-

ns

(10)

(11)

(12)

(13)

TRYHCH READY Setup Time into 80C88

TCHRYX READY Hold Time into 80C88

118

30

-8

-

68

20

-8

-

ns

TRYLCL

TlNVCH

READY Inactive to CLK (Note15)

Setup Time for Recognition

(lNTR, NMl, TEST) (Note 14)

30

15

(14)

(15)

TGVCH

TCHGX

RQ/GT Setup Time

30

40

-

15

30

-

ns

RQ Hold Time into 80C88 (Note 16)

TCHCL +

10

TCHCL +

10

(16)

(17)

TILlH

TIHIL

Input Rise Time (Except CLK)

Input Fall Time (Except CLK)

From 0.8V to 2.0V

From 2.0V to 0.8V

-

15

-

15

ns

TIMING RESPONSES

(18)

(19)

(20)

TCLML

TCLMH

Command Active Delay (Note13)

Command Inactive (Note 13)

5

-

35

5

-

35

65

ns

TRYHSH READY Active to Status Passive

(Notes 15, 17)

110

(21)

(22)

(23)

(24)

(25)

(26)

(27)

(28)

(29)

(30)

(31)

TCHSV

TCLSH

TCLAV

TCLAX

TCLAZ

TCHSZ

TSVLH

Status Active Delay

10

110

130

110

-

10

60

70

60

-

ns

Status Inactive Delay (Note 17)

Address Valid Delay

10

CL = 100pF

for all 80C88 outputs in

addition to internal

loads.

Address Hold Time

10

Address Float Delay

TCLAX

80

20

30

20

25

18

TCLAX

50

20

30

20

25

18

Status Float Delay

-

Status Valid to ALE High (Note 13)

TSVMCH Status Valid to MCE High (Note 13)

TCLLH CLK Low to ALE Valid (Note 13)

TCLMCH CLK Low to MCE High (Note 13)

-

TCHLL

ALE Inactive Delay (Note 13)

4

FN2949.4

February 22, 2008

21

80C88

AC Electrical Specifications V_CC= 5.0V±10%; T_A= 0°C to +70°C (C80C88, C80C88-2)

V

_CC= 5.0V±10%; T_A= -40°C to +85°C (I80C88, I80C88-2)

_CC= 5.0V±10%; T_A= -55°C to +125°C (M80C88)

MAX MODE SYSTEM (USING 82C88 BUS CONTROLLER) (Continued)

80C88

MAX

80C88-2

MAX

SYMBOL

TCLMCL

PARAMETER

MCE Inactive Delay (Note 13)

Data Valid Delay

TEST CONDITIONS

MIN

-

MIN

-

UNITS

ns

(32)

(33)

(34)

(35)

(36)

(37)

(38)

(39)

(40)

15

110

-

15

60

-

TCLDV

TCLDX2

TCVNV

TCVNX

TAZRL

TCLRL

TCLRH

TRHAV

10

5

10

5

ns

Data Hold Time

ns

Control Active Delay (Note 13)

Control Inactive Delay (Note 13)

Address Float to Read Active

RD Active Delay

45

-

45

-

ns

10

0

10

0

ns

10

165

150

-

10

100

80

-

ns

CL = 100pF

RD Inactive Delay

ns

for all 80C88 outputs in

addition to internal

loads.

RD Inactive to Next Address Active

TCLCL

- 45

TCLCL

ns

- 40

(41)

(42)

TCHDTL

Direction Control Active Delay

(Note 13)

-

50

30

-

50

30

ns

TCHDTH Direction Control Inactive Delay

(Note 1)

-

(43)

(44)

(45)

TCLGL

TCLGH

TRLRH

GT Active Delay

GT Inactive Delay

RD Width

0

85

-

0

50

-

ns

2TCLCL

- 75

2TCLCL

- 50

(46)

(47)

TOLOH

TOHOL

Output Rise Time

Output Fall Time

From 0.8V to 2.0V

From 2.0V to 0.8V

-

15

-

15

ns

NOTES:

3. Signal at 82C84A or 82C88 shown for reference only.

4. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.

5. Applies only to T2 state (8ns into T3).

6. The 80C88 actively pulls the RQ/GT pin to a logic one on the following clock low time.

7. Status lines return to their inactive (logic one) state after CLK goes low and READY goes high.

FN2949.4

February 22, 2008

22

80C88

Waveforms

T1

T2

T3

T4

(4)

TCH1CH2

(1)

TCLCL

(5)

TCL2CL1 TW

CLK

(23)

TCLAV

TCLCH

(2)

TCHCL (3)

QS0, QS1

TCLSH

(21) TCHSV

(22)

S2, S1, S0 (EXCEPT HALT)

(SEE NOTE 20)

A15-A8

(33)

(24)

TCLDV

TCLAX

(23) TCLAV

(23)

TCLAV

A19/S6-A16/S3

TSVLH

A19-A16

S6-S3

(31)

TCHLL

(27)

TCLLH

(29)

ALE (82C88 OUTPUT)

NOTES 18, 19

TR1VCL

(8)

RDY (82C84 INPUT)

TCLR1X

(12) TRYLCL

(9)

(11)

TCHRYX

READY 80C86 INPUT)

TRYHSH

(20)

(24)

TCLAX

(10)

TRYHCH

(7)

TCLDX1

(25)

TCLAZ

(6)

TDVCL

READ CYCLE

TCLAV

(23)

AD7-AD0

DATA IN

(39) TCLRH

AD7-AD0

RD

(37) TAZRL

TRHAV

(40)

(42)

TCHDTH

(41) TCHDTL

TRLRH

(45)

TCLRL

(38)

DT/R

TCLML

(18)

TCLMH

(19)

(36)

82C88

MRDC OR IORC

OUTPUTS

SEE NOTES 19, 21

(35) TCVNV

DEN

TCVNX

FIGURE 11. BUS TIMING - MAXIMUM MODE (USING 82C88)

NOTES:

8. RDY is sampled near the end of T2, T3, TW to determine if TW machine states are to be inserted.

9. Signals at 82C84A or 82C88 are shown for reference only.

10. Status inactive in state just prior to T4.

11. The issuance of the 82C88 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA, and DEN) lags the active high

82C88 CEN.

FN2949.4

February 22, 2008

23

80C88

Waveforms (Continued)

T1

T2

T3

T4

TW

CLK

TCHSV (21)

(SEE NOTE 24)

TCLDX2

S2, S1, S0 (EXCEPT HALT)

(22)

TCLDV

TCLAX

(33)

(24)

(34)

TCLAV

WRITE CYCLE

AD7-AD0

TCLSH

(23)

DATA

TCVNV

(35)

TCVNX (36)

DEN

TCLMH

(19)

(18) TCLML

82C88

OUTPUTS

SEE NOTES 22, 23

AMWC OR AIOWC

TCLMH (19)

(18)TCLML

MWTC OR IOWC

INTA CYCLE

A15-A8

(SEE NOTES 25, 26)

RESERVED FOR

CASCADE ADDR

(25) TCLAZ

AD7-AD0

(6)

TDVCL

POINTER

TCLDX1 (7)

(32)

TCLMCL

(28) TSVMCH

MCE/PDEN

(41)

TCHDTL

TCHDTH

(30) TCLMCH

DT/R

(42)

82C88 OUTPUTS

SEE NOTES 22, 23, 25

(18) TCLML

INTA

DEN

(19) TCLMH

TCVNV

(35)

TCVNX

(36)

SOFTWARE

HALT - RD, MRDC, IORC, MWTC, AMWC, IOWC, AIOWC, INTA, S0, S1 = VOH

AD7-AD0

INVALID ADDRESS

A15-A8

TCLAV

(23)

S2, S1, S0

TCLSH

(22)

TCHSV

(21)

FIGURE 12. BUS TIMING - MAXIMUM MODE SYSTEM (USING 82C88) (Continued)

NOTES:

12. Signals at 82C84A or 82C86 are shown for reference only.

13. The issuance of the 82C88 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA and DEN) lags the active high

82C88 CEN.

14. Status inactive in state just prior to T4.

15. Cascade address is valid between first and second INTA cycles.

16. Two INTA cycles run back-to-back. The 80C88 local ADDR/DATA bus is floating during both INTA cycles. Control for pointer address is shown

for second INTA cycle.

FN2949.4

February 22, 2008

24

80C88

Waveforms (Continued)

> 0-CLK

CYCLES

ANY

CLK

CYCLE

CLK

TCLGH

(44)

TCLGH (44)

TGVCH (14)

TCHGX (15)

TCLGL

(43)

(1)

TCLCL

PULSE 2

80C88 GT

RQ/GT

PULSE 3

PULSE 1

COPROCESSOR

RQ

COPROCESSOR

RELEASE

TCLAZ (25)

TCHSZ (26)

PREVIOUS GRANT

AD7-AD0

80C88

COPROCESSOR

TCHSV (21)

(SEE NOTE)

RD, LOCK

A19/S6-A16/S3

S2, S1, S0

FIGURE 13. REQUEST/GRANT SEQUENCE TIMING (MAXIMUM MODE ONLY)

NOTE: The coprocessor may not drive the busses outside the region shown without risking contention.

≥ 1CL

CYCLE

1 OR 2

CYCLES

CLK

HOLD

HLDA

THVCH (13)

(SEE NOTE)

TCLHAV (36)

80C88

TCLAZ (19)

A15-A8

80C88

COPROCESSOR

TCHSZ (20)

AD7-AD0

TCHSV (21)

A19/S6-A16/S3

RD, WR, I/O/M, DT/R, DEN, SSO

FIGURE 14. HOLD/HOLD ACKNOWLEDGE TIMING (MINIMUM MODE ONLY)

NOTE: Setup requirements for asynchronous signals only to guarantee recognition at next CLK.

CLK

ANY CLK CYCLE

(13)

CLK

TINVCH (SEE NOTE)

NMI

INTR

TEST

TCLAV

(23)

TCLAV

(23)

SIGNAL

LOCK

FIGURE 15. ASYNCHRONOUS SIGNAL RECOGNITION

NOTE: Setup requirements for asynchronous signals only to

guarantee recognition at next CLK.

FIGURE 16. BUS LOCK SIGNAL TIMING (MAXIMUM MODE

ONLY)

FN2949.4

February 22, 2008

25

80C88

Waveforms (Continued)

≥ 50µS

V

CC

CLK

(7) TCLDX1

(6) TDVCL

RESET

≥ 4 CLK CYCLE

FIGURE 17. RESET TIMING

AC Test Circuit

AC Testing Input, Output Waveform

INPUT

+ 20% V

OUTPUT

OUTPUT FROM

DEVICE UNDER TEST

TEST

POINT

V

IH

V

CL (NOTE)

OH

1.5V

V

OL

V

- 50% V

IL

17. All input signals (other than CLK) must switch between V

-50%

NOTE: Includes stay and jig capacitance.

ILMAX

V

and V

+20% V . CLK must switch between 0.4V and

IL

IHMIN IH

-0.4V. Input rise and fall times are driven at 1ns/V.

CC

Burn-In Circuits

MD80C88 (CERDIP)

C

GND

1

2

3

4

5

6

7

8

9

GND

A14

A13

A12

A11

A10

A9

V

40

CC

GND

V

CC

RIO

A15 39

A16 38

A17 37

A18 36

A19 35

BHE 34

VCL

RO

VCL

VCC/2

RIO

RO

VCC/2

GND

VCL

RO

VCC/2

RO

VCC/2

RO

RIO

VCC/2

GND

VCL

33

32

31

30

29

28

27

26

25

24

23

22

21

A8

MX

RD

GND

RO

VIL

RI

AD7

10 AD6

11 AD5

12 AD4

13 AD3

14 AD2

15 AD1

16 AD0

17 NMI

18 INTR

19 CLK

20 GND

RQ0

RQ1

LOCK

S2

VCL

RO

VCL

RO

VCC/2

RO

VCL

VCC/2

RO

OPEN

S1

VCC/2

RO

S0

VCC/2

OPEN

GND

F0

RO

QS0

VCC/2

RO

QS2

VCC/2

GND

TEST

READY

RESET

RI

RC

VCL

RI

NODE

A

GND

FROM

PROGRAM

CARD

FN2949.4

February 22, 2008

26

80C88

Burn-In Circuits (Continued)

NOTES:

COMPONENTS:

1. V_CC= 5.5V ±0.5V, GND = 0V.

2. Input voltage limits (except clock):

1. RI = 10kΩ ±5%, 1/4W

2. RO = 1.2kΩ ±5%, 1/4W

3. RIO = 2.7kΩ ±5%, 1/4W

4. RC = 1kΩ ±5%, 1/4W

5. C = 0.01μF (Minimum)

V

_IL(Maximum) = 0.4V

_IH(Minimum) = 2.6V, V_IH(Clock) = V_CC- 0.4V) minimum.

3. VCC/2 is external supply set to 2.7V ±10%.

4. V_CLis generated on program card (V_CC- 0.65V).

5. Pins 13 - 16 input sequenced instructions from internal hold

devices, (DIP Only).

6. F0 = 100kHz ±10%.

7. Node

= a 40μs pulse every 2.56ms.

A

FN2949.4

February 22, 2008

27

80C88

Die Characteristics

METALLIZATION:

Type: Silicon - Aluminum

Thickness: 11KÅ ±2kÅ

GLASSIVATION:

Type: SiO₂

Thickness: 8kÅ ±1kÅ

WORST CASE CURRENT DENSITY:

1.5 x 10⁵A/cm²

Metallization Mask Layout

80C88

GND

A11

A12

A13 A14

V

A15 A16/S3 A17/S4 A18/S5

CC

A19/S6

A10

A9

SSO

MN/MX

A8

RD

AD7

HOLD

AD6

AD5

HLDA

AD4

AD3

WR

AD2

AD1

IO/M

DT/R

AD0

NMI INTR CLK

GND

RESET READY TEST INTA

ALE

DEN

FN2949.4

February 22, 2008

28

80C88

Instruction Set Summary

INSTRUCTION CODE

MNEMONIC AND

DESCRIPTION

7 6 5 4 3 2 1 0

DATA TRANSFER

MOV = MOVE:

Register/Memory to/from

Register

1 0 0 0 1 0 d w

1 1 0 0 0 1 1 w

mod reg r/m

Immediate to Regis-

ter/Memory

mod 0 0 0 r/m

data

data if w 1

Immediate to Register

Memory to Accumulator

Accumulator to Memory

1 0 1 1 w reg

1 0 1 0 0 0 0 w

1 0 1 0 0 0 1 w

1 0 0 0 1 1 1 0

data

data if w 1

addr-high

addr-low

Register/Memory to Seg-

mod 0 reg r/m

ment Register ††

Segment Register to Reg-

ister/Memory

1 0 0 0 1 1 0 0

mod 0 reg r/m

mod 1 1 0 r/m

PUSH = Push:

Register/Memory

Register

1 1 1 1 1 1 1 1

0 1 0 1 0 reg

0 0 0 reg 1 1 0

Segment Register

POP = Pop:

Register/Memory

Register

1 0 0 0 1 1 1 1

0 1 0 1 1 reg

0 0 0 reg 1 1 1

mod 0 0 0 r/m

mod reg r/m

Segment Register

XCHG = Exchange:

Register/Memory with

Register

1 0 0 0 0 1 1 w

1 0 0 1 0 reg

Register with Accumula-

tor

IN = Input from:

Fixed Port

1 1 1 0 0 1 0 w

1 1 1 0 1 1 0 w

port

Variable Port

OUT = Output to:

Fixed Port

1 1 1 0 0 1 1 w

1 1 1 0 1 1 1 w

1 1 0 1 0 1 1 1

Variable Port

XLAT = Translate Byte to

AL

LEA = Load EA to

1 0 0 0 1 1 0 1

mod reg r/m

Register2

LDS = Load Pointer to DS

LES = Load Pointer to ES

1 1 0 0 0 1 0 1

1 1 0 0 0 1 0 0

1 0 0 1 1 1 1 1

mod reg r/m

LAHF = Load AH with

Flags

SAHF = Store AH into

1 0 0 1 1 1 1 0

Flags

PUSHF = Push Flags

POPF = Pop Flags

1 0 0 1 1 1 0 0

1 0 0 1 1 1 0 1

FN2949.4

February 22, 2008

29

80C88

Instruction Set Summary (Continued)

INSTRUCTION CODE

MNEMONIC AND

DESCRIPTION

7 6 5 4 3 2 1 0

ARITHMETIC

ADD = Add:

Register/Memory with

Register to Either

0 0 0 0 0 0 d w

1 0 0 0 0 0 s w

0 0 0 0 0 1 0 w

mod reg r/m

mod 0 0 0 r/m

data

Immediate to Regis-

ter/Memory

data

data if s:w = 01

Immediate to Accumula-

tor

data if w = 1

ADC = Add with Carry:

Register/Memory with

Register to Either

0 0 0 1 0 0 d w

1 0 0 0 0 0 s w

0 0 0 1 0 1 0 w

mod reg r/m

mod 0 1 0 r/m

data

Immediate to Regis-

ter/Memory

data

data if s:w = 01

Immediate to Accumula-

tor

data if w = 1

INC = Increment:

Register/Memory

Register

1 1 1 1 1 1 1 w

0 1 0 0 0 reg

mod 0 0 0 r/m

AAA = ASCll Adjust for

0 0 1 1 0 1 1 1

Add

DAA = Decimal Adjust for

0 0 1 0 0 1 1 1

Add

SUB = Subtract:

Register/Memory and

Register to Either

0 0 1 0 1 0 d w

1 0 0 0 0 0 s w

0 0 1 0 1 1 0 w

mod reg r/m

mod 1 0 1 r/m

data

Immediate from Regis-

ter/Memory

data

data if s:w = 01

Immediate from Accumu-

lator

data if w = 1

SBB = Subtract with

Borrow

Register/Memory and

Register to Either

0 0 0 1 1 0 d w

1 0 0 0 0 0 s w

0 0 0 1 1 1 0 w

mod reg r/m

mod 0 1 1 r/m

data

Immediate from Regis-

ter/Memory

data

data if s:w = 01

Immediate from Accumu-

lator

data if w = 1

DEC = Decrement:

Register/Memory

Register

1 1 1 1 1 1 1 w

0 1 0 0 1 reg

mod 0 0 1 r/m

mod 0 1 1 r/m

NEG = Change Sign

CMP = Compare:

1 1 1 1 0 1 1 w

Register/Memory and

Register

0 0 1 1 1 0 d w

1 0 0 0 0 0 s w

mod reg r/m

Immediate with Regis-

ter/Memory

mod 1 1 1 r/m

data

data if s:w = 01

FN2949.4

February 22, 2008

30

80C88

Instruction Set Summary (Continued)

INSTRUCTION CODE

MNEMONIC AND

DESCRIPTION

7 6 5 4 3 2 1 0

Immediate with Accumu-

lator

0 0 1 1 1 1 0 w

data

data if w = 1

AAS = ASCll Adjust for

Subtract

0 0 1 1 1 1 1 1

0 0 1 0 1 1 1 1

1 1 1 1 0 1 1 w

1 1 0 1 0 1 0 0

DAS = Decimal Adjust for

Subtract

MUL = Multiply (Un-

signed)

mod 1 0 0 r/m

mod 1 0 1 r/m

0 0 0 0 1 0 1 0

IMUL = Integer Multiply

(Signed)

AAM = ASCll Adjust for

Multiply

DlV = Divide (Unsigned)

1 1 1 1 0 1 1 w

mod 1 1 0 r/m

mod 1 1 1 r/m

IDlV = Integer Divide

(Signed)

AAD = ASClI Adjust for

Divide

1 1 0 1 0 1 0 1

1 0 0 1 1 0 0 0

1 0 0 1 1 0 0 1

0 0 0 0 1 0 1 0

CBW = Convert Byte to

Word

CWD = Convert Word to

Double Word

LOGIC

NOT = Invert

1 1 1 1 0 1 1 w

1 1 0 1 0 0 v w

mod 0 1 0 r/m

mod 1 0 0 r/m

SHL/SAL = Shift Logi-

cal/Arithmetic Left

SHR = Shift Logical Right

1 1 0 1 0 0 v w

mod 1 0 1 r/m

mod 1 1 1 r/m

SAR = Shift Arithmetic

Right

ROL = Rotate Left

ROR = Rotate Right

1 1 0 1 0 0 v w

mod 0 0 0 r/m

mod 0 0 1 r/m

mod 0 1 0 r/m

RCL = Rotate Through

Carry Flag Left

RCR = Rotate Through

1 1 0 1 0 0 v w

mod 0 1 1 r/m

Carry Right

AND = And:

Reg./Memory and Regis-

ter to Either

0 0 1 0 0 0 0 d w

1 0 0 0 0 0 0 w

0 0 1 0 0 1 0 w

mod reg r/m

mod 1 0 0 r/m

data

Immediate to Regis-

ter/Memory

data

data if w = 1

Immediate to Accumula-

tor

data if w = 1

TEST = And Function to

Flags, No Result:

Register/Memory and

Register

1 0 0 0 0 1 0 w

1 1 1 1 0 1 1 w

mod reg r/m

Immediate Data and Reg-

ister/Memory

mod 0 0 0 r/m

data

data if w = 1

FN2949.4

February 22, 2008

31

80C88

Instruction Set Summary (Continued)

INSTRUCTION CODE

MNEMONIC AND

DESCRIPTION

7 6 5 4 3 2 1 0

Immediate Data and Ac-

cumulator

1 0 1 0 1 0 0 w

data

data if w = 1

OR = Or:

Register/Memory and

Register to Either

0 0 0 0 1 0 d w

1 0 0 0 0 0 0 w

0 0 0 0 1 1 0 w

mod reg r/m

mod 1 0 1 r/m

data

Immediate to Regis-

ter/Memory

data

data if w = 1

Immediate to Accumula-

tor

data if w = 1

XOR = Exclusive or:

Register/Memory and

Register to Either

0 0 1 1 0 0 d w

1 0 0 0 0 0 0 w

0 0 1 1 0 1 0 w

mod reg r/m

mod 1 1 0 r/m

data

Immediate to Regis-

ter/Memory

data

data if w = 1

Immediate to Accumula-

tor

data if w = 1

STRING MANIPULA-

TION

REP = Repeat

1 1 1 1 0 0 1 z

1 0 1 0 0 1 0 w

1 0 1 0 0 1 1 w

MOVS = Move Byte/Word

CMPS = Compare

Byte/Word

SCAS = Scan Byte/Word

1 0 1 0 1 1 1 w

1 0 1 0 1 1 0 w

LODS = Load Byte/Word

to AL/AX

STOS = Stor Byte/Word

1 0 1 0 1 0 1 w

from AL/A

CONTROL TRANSFER

CALL = Call:

Direct Within Segment

Indirect Within Segment

Direct Intersegment

1 1 1 0 1 0 0 0

1 1 1 1 1 1 1 1

1 0 0 1 1 0 1 0

disp-low

mod 0 1 0 r/m

offset-low

disp-high

offset-high

seg-high

seg-low

Indirect Intersegment

1 1 1 1 1 1 1 1

mod 0 1 1 r/m

FN2949.4

February 22, 2008

32

80C88

Instruction Set Summary (Continued)

INSTRUCTION CODE

MNEMONIC AND

DESCRIPTION

7 6 5 4 3 2 1 0

JMP = Unconditional

Jump:

Direct Within Segment

1 1 1 0 1 0 0 1

1 1 1 0 1 0 1 1

disp-low

disp

disp-high

Direct Within Segment-

Short

Indirect Within Segment

Direct Intersegment

1 1 1 1 1 1 1 1

1 1 1 0 1 0 1 0

mod 1 0 0 r/m

offset-low

offset-high

seg-high

seg-low

Indirect Intersegment

1 1 1 1 1 1 1 1

mod 1 0 1 r/m

RET = Return from

CALL:

Within Segment

1 1 0 0 0 0 1 1

1 1 0 0 0 0 1 0

Within Seg Adding lmmed

to SP

data-low

data-high

Intersegment

1 1 0 0 1 0 1 1

FN2949.4

February 22, 2008

33

80C88

Instruction Set Summary (Continued)

INSTRUCTION CODE

MNEMONIC AND

DESCRIPTION

7 6 5 4 3 2 1 0

Intersegment Adding Im-

mediate to SP

1 1 0 0 1 0 1 0

data-low

data-high

JE/JZ = Jump on

Equal/Zero

0 1 1 1 0 1 0 0

0 1 1 1 1 1 0 0

disp

JL/JNGE = Jump on

Less/Not Greater or

Equal

JLE/JNG = Jump on Less

or Equal/ Not Greater

0 1 1 1 1 1 1 0

0 1 1 1 0 0 1 0

0 1 1 1 0 1 1 0

0 1 1 1 1 0 1 0

disp

JB/JNAE = Jump on Be-

low/Not Above or Equal

JBE/JNA = Jump on Be-

low or Equal/Not Above

JP/JPE = Jump on Pari-

ty/Parity Even

JO = Jump on Overflow

JS = Jump on Sign

0 1 1 1 0 0 0 0

0 1 1 1 1 0 0 0

0 1 1 1 0 1 0 1

disp

JNE/JNZ = Jump on Not

Equal/Not Zero

JNL/JGE = Jump on Not

Less/Greater or Equal

0 1 1 1 1 1 0 1

0 1 1 1 1 1 1 1

0 1 1 1 0 0 1 1

0 1 1 1 0 1 1 1

0 1 1 1 1 0 1 1

0 1 1 1 0 0 0 1

disp

JNLE/JG = Jump on Not

Less or Equal/Greater

JNB/JAE = Jump on Not

Below/Above or Equal

JNBE/JA = Jump on Not

Below or Equal/Above

JNP/JPO = Jump on Not

Par/Par Odd

JNO = Jump on Not Over-

flow

JNS = Jump on Not Sign

LOOP = Loop CX Times

0 1 1 1 1 0 0 1

1 1 1 0 0 0 1 0

1 1 1 0 0 0 0 1

disp

LOOPZ/LOOPE = Loop

While Zero/Equal

LOOPNZ/LOOPNE =

Loop While Not Ze-

ro/Equal

1 1 1 0 0 0 0 0

1 1 1 0 0 0 1 1

disp

JCXZ = Jump on CX Zero

INT = Interrupt

Type Specified

Type 3

disp

type

1 1 0 0 1 1 0 1

1 1 0 0 1 1 0 0

1 1 0 0 1 1 1 0

INTO = Interrupt on Over-

flow

IRET = Interrupt Return

1 1 0 0 1 1 1 1

PROCESSOR CONTROL

FN2949.4

February 22, 2008

34

80C88

Instruction Set Summary (Continued)

INSTRUCTION CODE

MNEMONIC AND

DESCRIPTION

7 6 5 4 3 2 1 0

1 1 1 1 1 0 0 0

1 1 1 1 0 1 0 1

7 6 5 4 3 2 1 0

CLC = Clear Carry

CMC = Complement Car-

ry

STC = Set Carry

CLD = Clear Direction

STD = Set Direction

CLl = Clear Interrupt

ST = Set Interrupt

HLT = Halt

1 1 1 1 1 0 0 1

1 1 1 1 1 1 0 0

1 1 1 1 1 1 0 1

1 1 1 1 1 0 1 0

1 1 1 1 1 0 1 1

1 1 1 1 0 1 0 0

1 0 0 1 1 0 1 1

1 1 0 1 1 x x x

WAIT = Wait

ESC = Escape (to Exter-

mod x x x r/m

nal Device)

LOCK = Bus Lock Prefix

1 1 1 1 0 0 0 0

FN2949.4

February 22, 2008

35

80C88

Instruction Set Summary (Continued)

INSTRUCTION CODE

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

MNEMONIC AND

DESCRIPTION

7 6 5 4 3 2 1 0

NOTES:

if s:w = 01 then 16-bits of immediate data form the operand.

if s:w = 11 then an immediate data byte is sign extended

to form the 16-bit operand.

if v = 0 then “count” = 1; if v = 1 then “count” in (C_L)

x = don't care

AL = 8-bit accumulator

AX = 16-bit accumulator

CX = Count register

DS= Data segment

ES = Extra segment

Above/below refers to un-

signed value.

Greater = more positive;

Less = less positive (more

negative) signed values

if d = 1 then “to” reg; if d =

0 then “from” reg

if w = 1 then word instruc-

tion; if w = 0 then byte

instruction

if mod = 11 then r/m is

treated as a REG field

if mod = 00 then DISP =

0†, disp-low and disp-high

are absent

z is used for string primitives for comparison with ZF FLAG.

SEGMENT OVERRIDE PREFIX

001 reg 11 0

REG is assigned according to the following table:

16-BIT (w = 1)

000 AX

001 CX

010 DX

011 BX

100 SP

101 BP

110 SI

8-BIT (w = 0)

000 AL

SEGMENT

00 ES

001 CL

01 CS

010 DL

10 SS

011 BL

11 DS

100 AH

101 CH

110 DH

111 BH

if mod = 01 then DISP =

disp-low sign-extended

16-bits, disp-high is ab-

sent

111 DI

if mod = 10 then DISP =

disp-high:disp-low

Instructions which reference the flag register file as a 16-bit object use the symbol

FLAGS to represent the file:

if r/m = 000 then EA =

(BX) + (SI) + DISP

if r/m = 001 then EA =

(BX) + (DI) + DISP

if r/m = 010 then EA =

(BP) + (SI) + DISP

if r/m = 011 then EA =

(BP) + (DI) + DISP

if r/m = 100 then EA = (SI)

+ DISP

FLAGS =

X:X:X:X:(OF):(DF):(IF):(TF):(SF):(ZF):X:(AF):X:(PF):X:(CF)

if r/m = 101 then EA = (DI)

+ DISP

if r/m = 110 then EA =

(BP) + DISP †

if r/m = 111 then EA =

(BX) + DISP

DISP follows 2nd byte of

instruction (before data

if required)

†

except if mod = 00 and

r/m = 110 then

EA = disp-high: disp-

low.

†† MOV CS, REG/MEM-

ORY not allowed.

FN2949.4

February 22, 2008

36

80C88

Dual-In-Line Plastic Packages (PDIP)

E40.6 (JEDEC MS-011-AC ISSUE B)

N

40 LEAD DUAL-IN-LINE PLASTIC PACKAGE

E1

INCHES

MILLIMETERS

INDEX

1

2

3

N/2

AREA

SYMBOL

MIN

MAX

0.250

-

MIN

-

MAX

6.35

-

NOTES

-B-

-C-

A

A1

A2

B

-

4

-A-

0.015

0.125

0.014

0.030

0.008

1.980

0.005

0.600

0.485

0.39

3.18

0.356

0.77

0.204

4

D

E

0.195

0.022

0.070

0.015

2.095

-

4.95

0.558

1.77

0.381

53.2

-

BASE

PLANE

A2

A

-

SEATING

PLANE

B1

C

8

L

C

L

-

D1

B1

e_A

A1

A

D1

e

D

50.3

5

e_C

C

B

D1

E

0.13

15.24

12.32

5

e_B

0.010 (0.25) M

C

B S

0.625

0.580

15.87

14.73

6

E1

e

5

NOTES:

1. Controlling Dimensions: INCH. In case of conflict between English

and Metric dimensions, the inch dimensions control.

0.100 BSC

0.600 BSC

2.54 BSC

15.24 BSC

-

e_A

e_B

L

6

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

-

0.700

0.200

-

17.78

5.08

7

3. Symbols are defined in the “MO Series Symbol List” in Section 2.2

of Publication No. 95.

0.115

2.93

4

9

4. Dimensions A, A1 and L are measured with the package seated in

N

40

JEDEC seating plane gauge GS-3.

Rev. 0 12/93

5. D, D1, and E1 dimensions do not include mold flash or protrusions.

Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).

e_A

6. E and

are measured with the leads constrained to be per-

-C-

pendicular to datum

.

7. e_Band e_Care measured at the lead tips with the leads uncon-

strained. e_Cmust be zero or greater.

8. B1 maximum dimensions do not include dambar protrusions. Dam-

bar protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,

E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).

FN2949.4

February 22, 2008

37

80C88

Ceramic Dual-In-Line Frit Seal Packages (CERDIP)

c1 LEAD FINISH

F40.6 MIL-STD-1835 GDIP1-T40 (D-5, CONFIGURATION A)

40 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE

-D-

E

-A-

INCHES

MIN

MILLIMETERS

BASE

(c)

METAL

SYMBOL

MAX

0.225

0.026

0.023

0.065

0.045

0.018

0.015

2.096

0.620

MIN

-

MAX

5.72

NOTES

b1

A

b

-

M

(b)

0.014

0.045

0.023

0.008

-

0.36

1.14

0.58

0.20

-

0.66

2

-B-

b1

b2

b3

c

0.58

3

SECTION A-A

bbb

C

D

A - B

D

S

1.65

-

1.14

4

BASE

PLANE

Q

0.46

2

A

-C-

SEATING

PLANE

c1

D

0.38

3

L

α

53.24

15.75

5

S1

b2

eA

A A

E

0.510

12.95

5

e

S

b

eA/2

aaa M

c

e

0.100 BSC

2.54 BSC

-

eA

eA/2

L

0.600 BSC

0.300 BSC

15.24 BSC

7.62 BSC

-

ccc

C

A - B

D

C

A - B S D S

M

S

-

NOTES:

0.125

0.200

0.070

-

3.18

5.08

1.78

-

1. Index area: A notch or a pin one identification mark shall be locat-

ed adjacent to pin one and shall be located within the shaded

area shown. The manufacturer’s identification shall not be used

as a pin one identification mark.

Q

0.015

0.38

6

S1

0.005

0.13

7

90^o

105^o

0.015

0.030

0.010

0.0015

90^o

105^o

0.38

0.76

0.25

0.038

-

α

aaa

bbb

ccc

M

2. The maximum limits of lead dimensions b and c or M shall be

measured at the centroid of the finished lead surfaces, when

solder dip or tin plate lead finish is applied.

-

3. Dimensions b1 and c1 apply to lead base metal only. Dimension

M applies to lead plating and finish thickness.

-

2, 3

8

4. Corner leads (1, N, N/2, and N/2+1) may be configured with a

partial lead paddle. For this configuration dimension b3 replaces

dimension b2.

N

40

Rev. 0 4/94

5. This dimension allows for off-center lid, meniscus, and glass

overrun.

6. Dimension Q shall be measured from the seating plane to the

base plane.

7. Measure dimension S1 at all four corners.

8. N is the maximum number of terminal positions.

9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.

10. Controlling dimension: INCH.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN2949.4

February 22, 2008

38


型号：	80C88_08
厂家：	Intersil
描述：	CMOS 8-/16-Bit Microprocessor CMOS 8位/ 16位微处理器微处理器
文件：	总38页 (文件大小：607K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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