7555IPA [INTERSIL]
General Purpose Timers; 通用定时器
| 型号： | 7555IPA |
| 厂家： | 
Intersil |
| 描述： | General Purpose Timers |
| 文件： | 总12页 (文件大小：287K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICM7555, ICM7556
®
Data Sheet
August 24, 2006
FN2867.9
General Purpose Timers
Features
• Exact Equivalent in Most Cases for SE/NE555/556 or
TLC555/556
The ICM7555 and ICM7556 are CMOS RC timers providing
significantly improved performance over the standard
SE/NE 555/6 and 355 timers, while at the same time being
direct replacements for those devices in most applications.
Improved parameters include low supply current, wide
operating supply voltage range, low THRESHOLD,
TRIGGER and RESET currents, no crowbarring of the
supply current during output transitions, higher frequency
performance and no requirement to decouple CONTROL
VOLTAGE for stable operation.
• Low Supply Current
- ICM7555. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60μA
- ICM7556. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120μA
• Extremely Low Input Currents . . . . . . . . . . . . . . . . . 20pA
• High Speed Operation . . . . . . . . . . . . . . . . . . . . . . . 1MHz
• Guaranteed Supply Voltage Range . . . . . . . . . 2V to 18V
• Temperature Stability . . . . . . . . . . . . 0.005%/°C at +25°C
Specifically, the ICM7555 and ICM7556 are stable
controllers capable of producing accurate time delays or
frequencies. The ICM7556 is a dual ICM7555, with the two
timers operating independently of each other, sharing only
V+ and GND. In the one shot mode, the pulse width of each
circuit is precisely controlled by one external resistor and
capacitor. For astable operation as an oscillator, the free
running frequency and the duty cycle are both accurately
controlled by two external resistors and one capacitor. Unlike
the regular bipolar SE/NE 555/6 devices, the CONTROL
VOLTAGE terminal need not be decoupled with a capacitor.
The circuits are triggered and reset on falling (negative)
waveforms, and the output inverter can source or sink
currents large enough to drive TTL loads, or provide minimal
offsets to drive CMOS loads.
• Normal Reset Function - No Crowbarring of Supply During
Output Transition
• Can be Used with Higher Impedance Timing Elements
than Regular 555/6 for Longer RC Time Constants
• Timing from Microseconds through Hours
• Operates in Both Astable and Monostable Modes
• Adjustable Duty Cycle
• High Output Source/Sink Driver can Drive TTL/CMOS
• Outputs have Very Low Offsets, HI and LO
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Precision Timing
• Pulse Generation
• Sequential Timing
• Time Delay Generation
• Pulse Width Modulation
• Pulse Position Modulation
• Missing Pulse Detector
Pinouts
ICM7555 (8 LD PDIP, SOIC)
ICM7556 (14 LD PDIP, CERDIP)
TOP VIEW
TOP VIEW
DISCHARGE
1
2
3
4
5
6
7
14 V
DD
THRESH-
OLD
CONTROL
VOLTAGE
13 DISCHARGE
12 THRESHOLD
1
2
3
4
8
7
6
5
GND
TRIGGER
OUTPUT
RESET
V
DD
DISCHARGE
THRESHOLD
CONTROL
11
RESET
OUTPUT
TRIGGER
GND
VOLTAGE
10 RESET
CONTROL
VOLTAGE
9
8
OUTPUT
TRIGGER
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002, 2004, 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ICM7555, ICM7556
Ordering Information
TEMP. RANGE
(°C)
PART NUMBER
ICM7555CBA
PART MARKING
7555 CBA
PACKAGE
8 Ld SOIC
PKG. DWG. #
M8.15
0 to +70
0 to +70
0 to +70
0 to +70
ICM7555CBA-T
7555 CBA
7555 CBAZ
7555 CBAZ
8 Ld SOIC Tape and Reel
8 Ld SOIC (Pb-free)
M8.15
M8.15
M8.15
ICM7555CBAZ (Note)
ICM7555CBAZ-T (Note)
8 Ld SOIC (Pb-free)
Tape and Reel
ICM7555IBA
7555 IBA
7555 IBA
7555 IBAZ
7555 IBAZ
-25 to +85
-25 to +85
-25 to +85
-25 to +85
8 Ld SOIC
M8.15
M8.15
M8.15
M8.15
ICM7555IBAT
8 Ld SOIC Tape and Reel
8 Ld SOIC (Pb-free)
ICM7555IBAZ (Note)
ICM7555IBAZ-T (Note)
8 Ld SOIC (Pb-free)
Tape and Reel
ICM7555IPA
7555 IPA
-25 to +85
-25 to +85
-25 to +85
-25 to +85
-55 to +125
8 Ld PDIP
E8.3
ICM7555IPAZ (Note)
ICM7556IPD
7555 IPAZ
8 Ld PDIP** (Pb-free)
14 Ld PDIP
E8.3
ICM7556IPD
ICM7556IPDZ
ICM7556MJD
E14.3
E14.3
F14.3
ICM7556IPDZ (Note)
ICM7556MJD
14 Ld PDIP** (Pb-free)
14 Ld Cerdip
**Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing
applications.
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN2867.9
August 24, 2006
2
ICM7555, ICM7556
Absolute Maximum Ratings
Thermal Information
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+18V
Input Voltage
Trigger, Control Voltage, Threshold,
Reset (Note 1) . . . . . . . . . . . . . . . . . . . . . V+ +0.3V to GND -0.3V
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical, Note 2)
14 Lead CERDIP Package. . . . . . . . . .
14 Lead PDIP Package* . . . . . . . . . . .
8 Lead PDIP Package* . . . . . . . . . . . .
8 Lead SOIC Package . . . . . . . . . . . . .
θ
(°C/W)
80
115
130
170
θ
(°C/W)
24
N/A
N/A
N/A
JA
JC
Maximum Junction Temperature (Hermetic Package) . . . . . . . +175°C
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . -65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300°C
(SOIC - Lead Tips Only)
* Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
Operating Conditions
Temperature Range
ICM7555C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
ICM7555I, ICM7556I . . . . . . . . . . . . . . . . . . . . . . -25°C to +85°C
ICM7556M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Due to the SCR structure inherent in the CMOS process used to fabricate these devices, connecting any terminal to a voltage greater than
V+ +0.3V or less than V- -0.3V may cause destructive latchup. For this reason it is recommended that no inputs from external sources not
operating from the same power supply be applied to the device before its power supply is established. In multiple supply systems, the supply
of the ICM7555 and ICM7556 must be turned on first.
2. θ is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief 379 for details.
JA
Electrical Specifications Applies to ICM7555 and ICM7556, unless otherwise specified
(NOTE 4)
T
= +25°C
-55°C TO +125°C
A
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP MAX MIN TYP MAX UNITS
Static Supply Current
I
ICM7555
ICM7556
V
V
V
V
= 5V
40
60
80
120
2
200
300
400
600
300
300
600
600
μA
μA
DD
DD
DD
DD
DD
= 15V
= 5V
μA
= 15V
μA
Monostable Timing Accuracy
R
= 10K, C = 0.1μF, V
= 5V
DD
%
A
858
1161
μs
Drift with Temperature
(Note 3)
V
V
V
V
R
= 5V
150
200
250
0.5
ppm/°C
ppm/°C
ppm/°C
%/V
DD
DD
DD
DD
= 10V
= 15V
Drift with Supply (Note 3)
= 5V to 15V
0.5
2
Astable Timing Accuracy
= R = 10K, C = 0.1μF, V = 5V
DD
%
A
B
1717
2323
μs
Drift with Temperature
(Note 3)
V
V
V
V
V
V
V
V
V
= 5V
150
200
250
0.5
ppm/°C
ppm/°C
ppm/°C
%/V
DD
DD
DD
DD
DD
DD
DD
DD
DD
= 10V
= 15V
= 5V to 15V
= 15V
= 15V
= 15V
= 15V
= 15V
Drift with Supply (Note 3)
Threshold Voltage
Trigger Voltage
0.5
67
32
V
62
28
71
36
10
10
71
61
27
72
37
50
50
72
% V
% V
TH
DD
V
TRIG
DD
Trigger Current
I
nA
nA
% V
TRIG
Threshold Current
Control Voltage
I
TH
V
62
67
61
CV
DD
FN2867.9
August 24, 2006
3
ICM7555, ICM7556
Electrical Specifications Applies to ICM7555 and ICM7556, unless otherwise specified (Continued)
(NOTE 4)
T
= +25°C
-55°C TO +125°C
A
PARAMETER
Reset Voltage
SYMBOL
TEST CONDITIONS
= 2V to 15V
MIN
TYP MAX MIN
TYP MAX UNITS
V
V
V
V
V
V
V
V
V
V
0.4
1.0
10
0.2
1.2
50
V
nA
nA
V
RST
DD
DD
DD
DD
DD
DD
DD
DD
DD
Reset Current
I
= 15V
= 15V
= 15V, I
RST
Discharge Leakage
Output Voltage
I
10
50
DIS
V
= 20mA
0.4
0.2
1.0
0.4
1.25
0.5
OL
OH
DIS
SINK
= 5V, I
SINK
= 3.2mA
V
V
= 15V, I
= 0.8mA
14.3
4.0
14.6
4.3
14.2
3.8
V
SOURCE
= 5V, I
= 0.8mA
V
SOURCE
= 15mA
Discharge Output Voltage
V
= 5V, I
0.2
0.4
0.6
0.4
V
SINK
= 15V, I
= 15mA
V
SINK
Supply Voltage (Note 3)
Output Rise Time (Note 3)
Output Fall Time (Note 3)
V
Functional Operation
2.0
18.0
3.0
16.0
V
DD
t
R
R
= 10M, C = 10pF, V
= 5V
75
75
1
ns
ns
MHz
R
L
L
DD
t
= 10M, C = 10pF, V
= 5V
F
L
L
DD
Oscillator Frequency
(Note 3)
f
V
= 5V, R = 470Ω, R = 270Ω,
DD A B
MAX
C = 200pF
NOTES:
3. These parameters are based upon characterization data and are not tested.
4. Applies only to military temperature range product (M suffix).
Functional Diagram
V
DD
FLIP-FLOP
RESET
8
4
OUTPUT
DRIVERS
R
R
COMPARATOR
A
THRESHOLD
+
6
5
OUTPUT
3
-
CONTROL
VOLTAGE
7
DISCHARGE
1
n
+
TRIGGER
2
-
COMPARATOR
B
R
1
GND
NOTE: This functional diagram reduces the circuitry down to its simplest equivalent components. Tie down unused inputs.
TRUTH TABLE
THRESHOLD VOLTAGE
TRIGGER VOLTAGE
RESET
Low
OUTPUT
Low
DISCHARGE SWITCH
Don’t Care
2
Don’t Care
1
On
On
> / (V+)
3
> / (V+)
3
High
Low
2
1
< / (V+)
3
> / (V+)
3
High
Stable
High
Stable
Off
1
Don’t Care
< / (V+)
High
3
NOTE: RESET will dominate all other inputs: TRIGGER will dominate over THRESHOLD.
FN2867.9
August 24, 2006
4
ICM7555, ICM7556
Schematic Diagram
V
DD
P
P
P
P
R
R
R
THRESHOLD
N
N
NPN
CONTROL
VOLTAGE
OUTPUT
P
P
TRIGGER
N
N
N
N
N
N
N
GND
RESET
DISCHARGE
R = 100kΩ ±20% (TYP)
The ICM7555 and ICM7556 produce supply current spikes
of only 2mA - 3mA instead of 300mA - 400mA and supply
decoupling is normally not necessary. Also, in most
instances, the CONTROL VOLTAGE decoupling capacitors
are not required since the input impedance of the CMOS
comparators on chip are very high. Thus, for many
applications, two capacitors can be saved using an ICM7555
and three capacitors with an ICM7556.
Application Information
General
The ICM7555 and ICM7556 devices are, in most instances,
direct replacements for the NE/SE 555/6 devices. However,
it is possible to effect economies in the external component
count using the ICM7555 and ICM7556. Because the bipolar
NE/SE 555/6 devices produce large crowbar currents in the
output driver, it is necessary to decouple the power supply
lines with a good capacitor close to the device. The ICM7555
and ICM7556 devices produce no such transients. See
Figure 1.
POWER SUPPLY CONSIDERATIONS
Although the supply current consumed by the ICM7555 and
ICM7556 devices is very low, the total system supply current
can be high unless the timing components are high
impedance. Therefore, use high values for R and low values
for C in Figures 2A, 2B, and 3.
500
T
= 25°C
A
400
V
DD
V
300
200
DD
GND
TRIGGER
10K
1
2
3
4
8
7
6
5
SE/NE555
DISCHARGE
THRESHOLD
V
100
0
DD
CONTROL
VOLTAGE
RESET
OPTIONAL
CAPACITOR
ICM7555/56
R
C
0
200
400
600
800
TIME (ns)
FIGURE 2A. ASTABLE OPERATION
FIGURE 1. SUPPLY CURRENT TRANSIENT COMPARED WITH
A STANDARD BIPOLAR 555 DURING AN OUTPUT
TRANSITION
FN2867.9
August 24, 2006
5
ICM7555, ICM7556
t
= -ln (1/3) R C = 1.1R C
V
OUTPUT
A
A
DD
R
R
V
A
B
DD
R
A
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
DISCHARGE
THRESHOLD
TRIGGER
OUTPUT
OUTPUT
ICM7555
CONTROL
VOLTAGE
V
DD
RESET
OPTIONAL
CAPACITOR
OPTIONAL
CAPACITOR
C
C
V
≤18V
DD
FIGURE 2B. ALTERNATE ASTABLE CONFIGURATION
FIGURE 3. MONOSTABLE OPERATION
CONTROL VOLTAGE
OUTPUT DRIVE CAPABILITY
The CONTROL VOLTAGE terminal permits the two trip
voltages for the THRESHOLD and TRIGGER internal
The output driver consists of a CMOS inverter capable of
driving most logic families including CMOS and TTL. As
such, if driving CMOS, the output swing at all supply
voltages will equal the supply voltage. At a supply voltage of
4.5V or more, the ICM7555 and ICM7556 will drive at least
two standard TTL loads.
comparators to be controlled. This provides the possibility of
oscillation frequency modulation in the astable mode or even
inhibition of oscillation, depending on the applied voltage. In
the monostable mode, delay times can be changed by
varying the applied voltage to the CONTROL VOLTAGE pin.
ASTABLE OPERATION
RESET
The circuit can be connected to trigger itself and free run as
a multivibrator, see Figure 2A. The output swings from rail to
rail, and is a true 50% duty cycle square wave. (Trip points
and output swings are symmetrical.) Less than a 1%
frequency variation is observed over a voltage range of +5V
to +15V.
The RESET terminal is designed to have essentially the
same trip voltage as the standard bipolar 555/6, i.e., 0.6V to
0.7V. At all supply voltages it represents an extremely high
input impedance. The mode of operation of the RESET
function is, however, much improved over the standard
bipolar NE/SE 555/6 in that it controls only the internal flip-
flop, which in turn controls simultaneously the state of the
OUTPUT and DISCHARGE pins. This avoids the multiple
threshold problems sometimes encountered with slow falling
edges in the bipolar devices.
1
------------------
f =
(EQ. 1)
1.4 RC
The timer can also be connected as shown in Figure 2B. In this
circuit, the frequency is:
(EQ. 2)
f = 1.44 ⁄ (R + 2R )C
A
B
The duty cycle is controlled by the values of R and R , by the
A
B
equation:
(EQ. 3)
D = (R + R ) ⁄ (R + 2R
)
A
B
A
B
MONOSTABLE OPERATION
In this mode of operation, the timer functions as a one-shot.
See Figure 3. Initially the external capacitor (C) is held
discharged by a transistor inside the timer. Upon application of
a negative TRIGGER pulse to pin 2, the internal flip-flop is set
which releases the short circuit across the external capacitor
and drives the OUTPUT high. The voltage across the capacitor
now increases exponentially with a time constant t = R C.
A
2
When the voltage across the capacitor equals / V+, the
3
comparator resets the flip-flop, which in turn discharges the
capacitor rapidly and also drives the OUTPUT to its low state.
TRIGGER must return to a high state before the OUTPUT can
return to a low state.
FN2867.9
August 24, 2006
6
ICM7555, ICM7556
Typical Performance Curves
200
180
400
360
320
280
1200
T
= 25°C
1100
1000
900
A
160
140
120
800
T
T
T
= -20°C
= 25°C
= 70°C
A
A
A
240
200
160
120
700
600
500
400
100
80
V
= 2V
DD
60
300
200
40
20
0
80
40
0
V
= 5V
DD
V
= 18V
DD
100
0
0
2
4
6
8
10 12 14 16 18 20
0
10
20
30
40
)
SUPPLY VOLTAGE (V)
LOWEST VOLTAGE LEVEL OF TRIGGER PULSE (%V
DD
FIGURE 4. MINIMUM PULSE WIDTH REQUIRED FOR
TRIGGERING
FIGURE 5. SUPPLY CURRENT vs SUPPLY VOLTAGE
-0.1
100
T
= 25°C
A
T
= -20°C
A
V
= 2V
DD
V
= 5V
V
= 18V
DD
DD
-1.0
10.0
1.0
V
= 5V
DD
V
= 2V
DD
-10.0
-100
V
= 18V
DD
0.1
0.01
0.1
1.0
10.0
-10
-1.0
-0.1
-0.01
OUTPUT VOLTAGE REFERENCED TO V
(V)
OUTPUT LOW VOLTAGE (V)
DD
FIGURE 6. OUTPUT SOURCE CURRENT vs OUTPUT VOLTAGE
FIGURE 7. OUTPUT SINK CURRENT vs OUTPUT VOLTAGE
100
100
T
= 70°C
A
T
= 25°C
A
V
= 18V
V
= 18V
DD
DD
V
= 5V
DD
10.0
10.0
1.0
V
= 5V
DD
V
= 2V
V
= 2V
DD
DD
1.0
0.1
0.1
0.01
0.01
0.1
1.0
10.0
0.1
1.0
10.0
OUTPUT LOW VOLTAGE (V)
OUTPUT LOW VOLTAGE (V)
FIGURE 8. OUTPUT SINK CURRENT vs OUTPUT VOLTAGE
FIGURE 9. OUTPUT SINK CURRENT vs OUTPUT VOLTAGE
FN2867.9
August 24, 2006
7
ICM7555, ICM7556
Typical Performance Curves (Continued)
8
6
4
2
0
2
4
100
T
= 25°C
A
T
= 25°C
A
V
= 5V
DD
V
= 18V
DD
10.0
R
= R = 10MΩ
B
A
V
= 2V
DD
C = 100pF
R
= R = 10kΩ
B
A
1.0
0.1
C = 0.1μF
6
8
0.1
1.0
10.0
100.0
0.01
0.1
1.0
10.0
SUPPLY VOLTAGE (V)
DISCHARGE LOW VOLTAGE (V)
FIGURE 10. NORMALIZED FREQUENCY STABILITY IN THE
ASTABLE MODE vs SUPPLY VOLTAGE
FIGURE 11. DISCHARGE OUTPUT CURRENT vs DISCHARGE
OUTPUT VOLTAGE
600
+1.0
R
= R = 10kΩ
B
A
V
= 5V
+0.9
+0.8
DD
C = 0.1μF
500
+0.7
+0.6
+0.5
400
300
V
= 5V
DD
+0.4
+0.3
V = 18V
DD
T
= 70°C
A
200
100
0
T
= 25°C
+0.2
+0.1
V
= 2V
40
A
DD
T
= -20°C
20
A
V
= 2V
0
DD
-0.1
0
10
30
40
)
-20
0
20
60
80
LOWEST VOLTAGE LEVEL OF TRIGGER PULSE (%V
TEMPERATURE (°C)
DD
FIGURE 12. PROPAGATION DELAY vs VOLTAGE LEVEL OF
TRIGGER PULSE
FIGURE 13. NORMALIZED FREQUENCY STABILITY IN THE
ASTABLE MODE vs TEMPERATURE
1.0
1.0
T
= 25°C
A
T
= 25°C
100m
10m
A
100m
R
A
10m
1m
1kΩ
(R + 2R )
1m
100μ
10μ
1μ
A
B
1kΩ
10kΩ
100kΩ
1MΩ
10MΩ
100MΩ
10kΩ
100kΩ
1MΩ
10MΩ
100MΩ
100μ
10μ
1μ
100n
10n
1n
100n
10n
1n
100p
100p
10p
1p
10p
1p
0.1
1
10
100
1k
10k
100k
1M
10M
100n
1μ
10μ
100μ 1m
10m 100m
1
10
FREQUENCY (Hz)
TIME DELAY (s)
FIGURE 14. FREE RUNNING FREQUENCY vs R , R AND C
A
B
FIGURE 15. TIME DELAY IN THE MONOSTABLE MODE vs
AND C
R
A
FN2867.9
August 24, 2006
8
ICM7555, ICM7556
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
N
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
NOTES
-B-
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
-
1
2
3
L
9
SEATING PLANE
A
0.0075
0.1890
0.1497
0.0098
0.1968
0.1574
-
-A-
3
h x 45°
D
4
-C-
0.050 BSC
1.27 BSC
-
α
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
0.25(0.010) M
C
A M B S
N
α
8
8
7
NOTES:
0°
8°
0°
8°
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
FN2867.9
August 24, 2006
9
ICM7555, ICM7556
Dual-In-Line Plastic Packages (PDIP)
E8.3 (JEDEC MS-001-BA ISSUE D)
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
N
E1
INDEX
AREA
INCHES MILLIMETERS
1
2
3
N/2
SYMBOL
MIN
MAX
0.210
-
MIN
-
MAX
5.33
-
NOTES
-B-
-C-
A
A1
A2
B
-
4
-A-
D
E
0.015
0.115
0.014
0.045
0.008
0.355
0.005
0.300
0.240
0.39
2.93
0.356
1.15
0.204
9.01
0.13
7.62
6.10
4
BASE
PLANE
0.195
0.022
0.070
0.014
0.400
-
4.95
0.558
1.77
0.355
10.16
-
-
A2
A
-
SEATING
PLANE
L
C
L
B1
C
8, 10
D1
B1
eA
-
A
A
1
D1
e
D
5
eC
C
B
eB
D1
E
5
0.010 (0.25) M
C
B S
0.325
0.280
8.25
7.11
6
NOTES:
E1
e
5
1. Controlling Dimensions: INCH. In case of conflict between
0.100 BSC
0.300 BSC
2.54 BSC
7.62 BSC
-
English and Metric dimensions, the inch dimensions control.
e
e
6
A
B
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
-
0.430
0.150
-
10.92
3.81
7
3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.
L
0.115
2.93
4
9
4. Dimensions A, A1 and L are measured with the package seated
N
8
8
in JEDEC seating plane gauge GS-3.
Rev. 0 12/93
5. D, D1, and E1 dimensions do not include mold flash or protru-
sions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
e
6. E and
pendicular to datum
7. e and e are measured at the lead tips with the leads uncon-
are measured with the leads constrained to be per-
A
-C-
.
B
C
strained. e must be zero or greater.
C
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
FN2867.9
August 24, 2006
10
ICM7555, ICM7556
Dual-In-Line Plastic Packages (PDIP)
N
E14.3 (JEDEC MS-001-AA ISSUE D)
14 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
1
2
3
N/2
INCHES MILLIMETERS
-B-
-C-
SYMBOL
MIN
MAX
0.210
-
MIN
-
MAX
5.33
-
NOTES
-A-
A
A1
A2
B
-
4
D
E
0.015
0.115
0.014
0.045
0.008
0.735
0.005
0.300
0.240
0.39
2.93
0.356
1.15
0.204
18.66
0.13
7.62
6.10
4
BASE
PLANE
A2
A
0.195
0.022
0.070
0.014
0.775
-
4.95
0.558
1.77
0.355
19.68
-
-
SEATING
PLANE
-
L
C
L
B1
C
8
D1
B1
eA
A1
A
D1
-
e
eC
C
B
D
5
eB
0.010 (0.25) M
C
B S
D1
E
5
NOTES:
0.325
0.280
8.25
7.11
6
1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.
E1
e
5
0.100 BSC
0.300 BSC
2.54 BSC
7.62 BSC
-
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
e
e
6
A
B
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
-
0.430
0.150
-
10.92
3.81
7
4. Dimensions A, A1 and L are measured with the package seated in
L
0.115
2.93
4
9
JEDEC seating plane gauge GS-3.
N
14
14
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
Rev. 0 12/93
e
6. E and
dicular to datum
7. e and e are measured at the lead tips with the leads uncon-
are measured with the leads constrained to be perpen-
A
-C-
.
B
C
strained. e must be zero or greater.
C
8. B1maximumdimensionsdonotincludedambarprotrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 -
1.14mm).
FN2867.9
August 24, 2006
11
ICM7555, ICM7556
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 LEAD FINISH
F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A)
14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
-D-
E
-A-
INCHES MILLIMETERS
MIN
BASE
(c)
METAL
SYMBOL
MAX
0.200
0.026
0.023
0.065
0.045
0.018
0.015
0.785
0.310
MIN
-
MAX
5.08
0.66
0.58
1.65
1.14
0.46
0.38
19.94
7.87
NOTES
b1
A
b
-
-
M
M
(b)
0.014
0.014
0.045
0.023
0.008
0.008
-
0.36
0.36
1.14
0.58
0.20
0.20
-
2
-B-
b1
b2
b3
c
3
SECTION A-A
bbb
C
D
A - B
D
S
S
S
-
4
BASE
PLANE
Q
2
A
-C-
SEATING
PLANE
c1
D
3
L
α
5
S1
b2
eA
A A
E
0.220
5.59
5
e
S
b
eA/2
aaa M
c
e
0.100 BSC
2.54 BSC
-
eA
eA/2
L
0.300 BSC
0.150 BSC
7.62 BSC
3.81 BSC
-
ccc
C
A - B
D
C
A - B S D S
M
S
-
NOTES:
0.125
0.200
0.060
-
3.18
5.08
1.52
-
-
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
Q
0.015
0.38
6
S1
0.005
0.13
7
90°
105°
0.015
0.030
0.010
0.0015
90°
105°
0.38
0.76
0.25
0.038
-
α
aaa
bbb
ccc
M
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
-
-
-
-
-
-
-
-
-
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
-
2, 3
8
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
N
14
14
Rev. 0 4/94
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN2867.9
August 24, 2006
12
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