5962-9163401M2A [INTERSIL]
Low Noise, Wideband, Precision Operational Amplifier; 低噪声，宽带，精密运算放大器
| 型号： | 5962-9163401M2A |
| 厂家： | 
Intersil |
| 描述： | Low Noise, Wideband, Precision Operational Amplifier |
| 文件： | 总10页 (文件大小：286K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
HA-5221/883
Low Noise, Wideband,
Precision Operational Amplifier
Features
Description
• This Circuit is Processed in Accordance to MIL-STD- The HA-5221/883 is a high performance, dielectrically isolated,
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
monolithic op amp, featuring precision DC characteristics while
providing excellent AC characteristics. Designed for audio,
video, and other demanding applications, noise (3.6nV/√Hz at
1kHz typ), total harmonic distortion (<0.005% typ), and DC
errors are kept to a minimum.
• Gain Bandwidth Product. . . . . . . . . . . . . .100MHz (Min)
• Unity Gain Bandwidth . . . . . . . . . . . . . . . . .30MHz (Min)
40MHz (Typ)
The precision performance is shown by low offset voltage
(0.3mV typ), low bias currents (40nA typ), low offset currents
(15nA typ), and high open loop gain (128dB typ). The combi-
nation of these excellent DC characteristics with fast settling
time (0.4µs typ) make the HA-5221/883 ideally suited for
precision signal conditioning.
• High Slew Rate. . . . . . . . . . . . . . . . . . . . . . .25V/µs (Min)
37V/µs (Typ)
• Low Offset Voltage . . . . . . . . . . . . . . . . . .0.75mV (Max)
0.30mV (Typ)
• High Open Loop Gain . . . . . . . . . . . . . . . . . 106dB (Min)
128dB (Typ)
The unique design of the HA-5221/883 gives this device out-
standing AC characteristics, including high unity gain band-
• Low Voltage Noise (at 1kHz). . . . . . . . .5.8nV/√Hz (Max)
3.6nV/√Hz (Typ) width (40MHz typ) and high slew rate (37V/µs typ), not
normally associated with precision op amps. Other key spec-
• Low Current Noise (at 1kHz). . . . . . . . 2.0pA/√Hz (Max)
ifications include high CMRR (95dB typ) and high PSRR
(100dB typ). The combination of these specifications will
allow the HA-5221/883 to be used in RF signal conditioning
as well as video amplifiers.
1.4pA/√Hz (Typ)
• High Output Current . . . . . . . . . . . . . . . . . ±30mA (Min)
±56mA (Typ)
• Low Supply Current. . . . . . . . . . . . . . . . . . . 10mA (Max)
8mA (Typ)
Ordering Information
Applications
OBSOLETE
PART
NUMBER
TEMP
RANGE
(oC)
• Precision Test Systems
• Active Filtering
SMD NO.
PACKAGE
HA4-5221/883 5962-9163401M2A -55 to 125 20 Ld CLCC
HA7-5221/883 5962-9163401MPA -55 to 125 8 Ld CERDIP
• Small Signal Video
• Accurate Signal Processing
• RF Signal Conditioning
Pinouts
HA-5221/883
(CERDIP)
HA-5221/883
(CLCC)
TOP VIEW
TOP VIEW
-BAL
-IN
1
2
3
4
8
7
6
5
+ BAL
V+
3
2
1 20 19
-
18
17
16
15
14
4
5
6
7
8
NC
V+
NC
-IN
+
+IN
V-
OUT
NC
-
NC
NC
+IN
NC
+
OUT
NC
9
10 11 12 13
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
File Number 3716.1
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1
HA-5221/883
Absolute Maximum Ratings
Thermal Information
Voltage Between V+ and V- Terminals . . . . . . . . . . . . . . . . . . . 36V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V
Voltage at Either Input Terminal. . . . . . . . . . . . . . . . . . . . . . V+ to V-
Peak Output Current (Pulsed at 1ms, 10% Duty Cycle). . . . .100mA
Continuous Output Current. . . . . . . . . . . . . . Short Circuit Protected
Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC
ESD Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <2000V
Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300oC
Thermal Resistance
θJA
θJC
CerDIP Package . . . . . . . . . . . . . . . . . . . 110oC/W
27oC/W
13oC/W
67oC/W
Ceramic LCC Package . . . . . . . . . . . . . .
64oC/W
Metal Can Package . . . . . . . . . . . . . . . . . 148oC/W
Package Power Dissipation Limit at +75oC
CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.91W
Ceramic LCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.56W
Metal Can Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.68W
Package Power Dissipation Derating Factor Above +75oC
CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1mW/oC
Ceramic LCC Package . . . . . . . . . . . . . . . . . . . . . . . . 15.6mW/oC
Metal Can Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8mW/oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC
Operating Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . ±10V to ±15V
VINCM ≤ 1/2 (V+ - V-)
RL ≥ 1kΩ
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Tested at: VSUPPLY = ±15V, RLOAD = 1kΩ, VOUT = 0V, Unless Otherwise Specified.
LIMITS
MIN
GROUP A
SUBGROUPS TEMPERATURE
PARAMETERS
SYMBOL
CONDITIONS
VCM = 0V
MAX
0.75
1.5
UNITS
mV
Input Offset Voltage
VIO
1
+25oC
+125oC, -55oC
+25oC
-0.75
-1.5
-80
2, 3
1
mV
Input Bias Current
+IB
VCM = 0V,
80
nA
+RS = 100.1kΩ,
-RS = 100Ω
2, 3
+125oC, -55oC
-200
200
nA
-IB
VCM = 0V, +RS = 100Ω,
-RS = 100.1kΩ
1
+25oC
+125oC, -55oC
+25oC
-80
-200
-50
80
200
50
nA
nA
nA
nA
2, 3
1
Input Offset Current
IIO
VCM = 0V,
+RS = 100.1kΩ,
-RS = 100.1kΩ
2, 3
+125oC, -55oC
-150
150
Common Mode Range
+CMR
-CMR
V+ = +3V, V- = -27V
V+ = +27V, V- = -3V
VOUT = 0V and +10V
VOUT = 0V and -10V
1
2, 3
1
+25oC
+125oC, -55oC
+25oC
12
12
-
-
V
V
-
-12
V
2, 3
4
+125oC, -55oC
+25oC
-
-12
V
Large Signal Voltage
Gain
+AVOL
106
100
106
100
88
86
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
5, 6
4
+125oC, -55oC
+25oC
-AVOL
5, 6
1
+125oC, -55oC
+25oC
Common Mode
Rejection Ratio
+CMRR
∆VCM = +10V,
V+ = +5V, V- = -25V,
2, 3
+125oC, -55oC
VOUT = -10V
-CMRR
∆VCM = -10V,
V+ = +25V, V- = -5V,
1
+25oC
88
86
-
-
dB
dB
2, 3
+125oC, -55oC
VOUT = +10V
Output Voltage Swing
+VOUT
RL = 1kΩ
4
+25oC
+125oC, -55oC
+25oC
12.0
-
V
V
V
V
5, 6
4
11.5
-
-VOUT
RL = 1kΩ
-
-
-12.0
-11.5
5, 6
+125oC, -55oC
2
HA-5221/883HA-5221/883
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
Device Tested at: VSUPPLY = ±15V, RLOAD = 1kΩ, VOUT = 0V, Unless Otherwise Specified.
LIMITS
GROUP A
PARAMETERS
Output Current
SYMBOL
CONDITIONS
SUBGROUPS TEMPERATURE
MIN
MAX
UNITS
mA
mA
mA
mA
mA
mA
mA
mA
dB
+IOUT
VOUT = +10V, RL = 1kΩ
4
5, 6
4
+25oC
+125oC, -55oC
+25oC
30
30
-
-
-
-IOUT
VOUT = -10V, RL = 1kΩ
VOUT = 0V, IOUT = 0mA
VOUT = 0V, IOUT = 0mA
-30
-30
10
11
-
5, 6
1
+125oC, -55oC
+25oC
-
Quiescent Power Supply
Current
+ICC
-
2, 3
1
+125oC, -55oC
+25oC
-
-ICC
-10
-11
90
86
2, 3
1
+125oC, -55oC
+25oC
-
Power Supply
Rejection Ratio
+PSRR
∆VSUP = 10V,
V+ = +20V, V- = -15V,
V+ = +10V, V- = -15V
-
2, 3
+125oC, -55oC
-
dB
-PSRR
∆VSUP = 10V,
V+ = +15V, V- = -20V,
V+ = +15V, V- = -10V
1
+25oC
90
86
-
-
dB
dB
2, 3
+125oC, -55oC
Offset Voltage
Adjustment
+VIOAdj
-VIOAdj
Note 1
1
+25oC
+125oC, -55oC
+25oC
VIO-1
VIO-1
VIO+1
VIO+1
-
-
-
-
mV
mV
mV
mV
2, 3
1
Note 1
2, 3
+125oC, -55oC
NOTE:
1. Offset adjustment range is [VIO (Measured ±1mV] minimum referred to output. This test is for functionality only to assure adjustment
through 0V.
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
Table 2 Intentionally Left Blank. See AC specifications in Table 3.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Characterized at: VSUPPLY = ±15V, RLOAD = 1kΩ, CLOAD = 50pF, Unless Otherwise Specified.
LIMITS
PARAMETERS
SYMBOL
CONDITIONS
NOTES
1, 5
1, 5
1, 5
1, 5
1, 5
1, 5
1
TEMPERATURE
+25oC
MIN
MAX
24.0
8.0
5.8
11.5
6.0
2.0
-
UNITS
nV/√Hz
nV/√Hz
nV/√Hz
pA/√Hz
pA/√Hz
pA/√Hz
MHz
Input Noise Voltage
Density
EN
RS = 0Ω, fO = 10Hz
RS = 0Ω, fO = 100Hz
RS = 0Ω, fO = 1kHz
RS = 500kΩ, fO = 10Hz
RS = 500kΩ, fO = 100Hz
RS = 500kΩ, fO = 1kHz
-
-
+25oC
+25oC
-
Input Noise Current
Density
IN
+25oC
-
+25oC
-
+25oC
-
Gain Bandwidth Product
Unity Gain Bandwidth
Slew Rate
GBWP
UGBW
±SR
VOUT = 200mVP-P
O = 100kHz
,
+25oC
100
90
30
25
25
f
-55oC to +125oC
+25oC
-
MHz
VOUT = 200mV
1
1
-
MHz
-55oC to +125oC
-55oC to +125oC
-
MHz
VOUT = ±2.5V
-
V/µs
CL = 50pF
3
HA-5221/883HA-5221/883
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
Device Characterized at: VSUPPLY = ±15V, RLOAD = 1kΩ, CLOAD = 50pF, Unless Otherwise Specified.
LIMITS
PARAMETERS
SYMBOL
FPBW
CONDITIONS
VPEAK = 10V
NOTES
1, 2
TEMPERATURE
-55oC to +125oC
-55oC to +125oC
MIN
MAX
UNITS
kHz
Full Power Bandwidth
398
1
-
-
Minimum Closed Loop
Stable Gain
CLSG
RL = 1kΩ, CL = 50pF
1
V/V
Rise and Fall Time
Overshoot
t
R, tF
VOUT = ±100mV
VOUT = ±100mV
1, 4
1
+25oC
-
-
-
-
20
25
ns
%
±OS
+25oC
-55oC to +125oC
-55oC to +125oC
30
%
Power Consumption
NOTES:
PC
VOUT = 0V, IOUT
0mA
=
1, 3
660
mW
1. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested at final production. These param-
eters are lab characterized upon initial design release, or upon design changes. These parameters are guaranteed by characterization
based upon data from multiple production runs which reflect lot to lot and within lot variation.
2. Full Power Bandwidth guarantee based on Slew Rate measurement using FPBW = Slew Rate/(2πVPEAK).
3. Power Consumption based upon Quiescent Supply Current test maximum. (No load on outputs.).
4. Measured between 10% and 90% points.
5. Input Noise Voltage Density and Input Noise Current Density limits are based on characterization data.
TABLE 4. ELECTRICAL TEST REQUIREMENTS
MIL-STD-883 TEST REQUIREMENTS
Interim Electrical Parameters (Pre Burn-In)
Final Electrical Test Parameters
Group A Test Requirements
SUBGROUPS (SEE TABLE 1)
1
1 (Note 1), 2, 3, 4, 5, 6
1, 2, 3, 4, 5, 6
1
Groups C and D Endpoints
NOTE:
1. PDA applies to Subgroup 1 only.
4
HA-5221/883
Die Characteristics
DIE DIMENSIONS:
72 x 94 x 19 mils ± 1 mils
1840 x 2400 x 483µm ± 25.4µm
METALLIZATION:
Type: Al, 1% Cu
Thickness: 16kÅ ± 2kÅ
GLASSIVATION:
Type: Nitride (Si3N4) over Silox (SIO2, 5% Phos.)
Silox Thickness: 12kÅ ± 2kÅ
Nitride Thickness: 3.5kÅ ± 1.5kÅ
WORST CASE CURRENT DENSITY:
4
2
4.2 x 10 A/cm
SUBSTRATE POTENTIAL (Powered Up): V-
TRANSISTOR COUNT: 62
PROCESS: Bipolar Dielectric Isolation
Metallization Mask Layout
HA-5221/883
V-
+IN
-IN
-BAL
+BAL
OUT
V+
5
HA-5221
DESIGN INFORMATION(Continued)
The information contained in this section has been developed through characterization by Intersil Corporation and is for use as application
and design information only. No guarantee is implied.
Typical Performance Curves Unless Otherwise Specified: TA = +25oC, VSUPPLY = ±15V
SUPPLY CURRENT vs TEMPERATURE
TYPICAL PERFORMANCE CHARACTERISTICS
Device Characterized at: Supply Voltage = ±15V, RL = 1kΩ, CL = 50pF, Unless Otherwise Specified
PARAMETERS
Input Offset Voltage
CONDITIONS
See Table 1
TEMPERATURE
+25oC
Full
TYPICAL
0.3
0.35
0.5
40
UNITS
mV
mV
Average Offset Voltage Drift
Input Bias Current
See Table 1
See Table 1
Full
µV/oC
nA
+25oC
Full
70
nA
Input Offset Current
See Table 1
+25oC
Full
15
nA
30
nA
Differential Input Resistance
Input Noise Voltage
See Table 1
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
Full
70
kΩ
fO = 0.1Hz to 10Hz
0.25
10
µVP-P
nV/√Hz
nV/√Hz
nV/√Hz
pA/√Hz
pA/√Hz
pA/√Hz
%
Input Noise Voltage Density
fO = 10Hz
fO = 100Hz
fO = 1kHz
fO = 10Hz
fO = 100Hz
fO = 1kHz
See Note 1
5
3.6
7
Input Noise Current Density
3
1.4
0.005
128
120
THD & N
Large Signal Voltage Gain
VOUT = 0V to ±10V
dB
dB
6
HA-5221
DESIGN INFORMATION(Continued)
The information contained in this section has been developed through characterization by Intersil Corporation and is for use as application
and design information only. No guarantee is implied.
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
Device Characterized at: Supply Voltage = ±15V, RL = 1kΩ, CL = 50pF, Unless Otherwise Specified
PARAMETERS
Common Mode Rejection Ratio
Unity Gain Bandwidth
CONDITIONS
∆VCM = ±10V
TEMPERATURE
Full
TYPICAL
95
UNITS
dB
(-3dB)
+25oC
+125oC
-55oC
+25oC
+125oC
-55oC
Full
40
MHz
MHz
MHz
MHz
MHz
MHz
V/V
V
33
45
Gain Bandwidth Product
1kHz to 400kHz
130
110
150
1
Minimum Gain Stability
Output Voltage Swing
RL = 333Ω
Full
±10
±12.5
±12.1
±56
10
RL = 1K
+25oC
Full
V
V
Output Current
VOUT = ±10V
Full
mA
W
Output Resistance
Full Power Bandwidth
+25oC
+25oC
FPBW = SR/2πVPEAK
PEAK = 10V
,
398
kHz
V
Slew Rate
Rise Time
Overshoot
Settling Time
VOUT = ±2.5V
+25oC
+125oC
-55oC
+25oC
+125oC
-55oC
+25oC
+125oC
-55oC
+25oC
+25oC
Full
37
37
34
13
13
15
13
13
11
0.4
1.5
100
8
V/µs
V/µs
V/µs
ns
V
V
OUT = ±100mV
ns
ns
OUT = ±100mV
%
%
%
10VSTEP, AV = -1
0.1%
µs
0.01%
µs
Power Supply Rejection Ratio
Supply Current
∆VS = ±10V to ±20V
dB
mA
V
Full
Minimum Supply Voltage
Functional Operation Only.
Other Parameters May Vary.
+25oC
±5
NOTE:
1. AVCL = 10, fO = 1kHz, VOUT = 5Vrms, RL = 600Ω, 10Hz to 100Hz, Minimum resolution of test equipment is 0.005%.
7
HA-5221
DESIGN INFORMATION(Continued)
The information contained in this section has been developed through characterization by Intersil Corporation and is for use as application
and design information only. No guarantee is implied.
CONDI-
PARAMETERS
TIONS
TEMPERATURE
TYPICAL
UNITS
pA/qHz
pA/qHz
pA/qHz
%
Input Noise Current Density
fO = 10Hz
fO = 100Hz
fO = 1kHz
See Note 1
+25oC
+25oC
+25oC
+25oC
+25oC
7
3
1.4
THD & N
0.005
128
Large Signal Voltage Gain
VOUT = 0 to
110V
dB
Full
Full
120
95
dB
dB
Common Mode Rejection Ratio
Unity Gain Bandwidth
Delta VCM =
110V
(-3)
8
HA-5221
Ceramic Leadless Chip Carrier Packages (CLCC)
J20.A MIL-STD-1835 CQCC1-N20 (C-2)
0.010 S E H S
20 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE
D
INCHES
MIN
MILLIMETERS
D3
SYMBOL
MAX
0.100
0.088
-
MIN
1.52
1.27
-
MAX
2.54
2.23
-
NOTES
j x 45o
A
A1
B
0.060
0.050
-
6, 7
-
-
B1
B2
B3
D
0.022
0.028
0.56
0.71
2, 4
-
0.072 REF
1.83 REF
E3
E
B
0.006
0.342
0.022
0.358
0.15
8.69
0.56
9.09
-
-
D1
D2
D3
E
0.200 BSC
0.100 BSC
5.08 BSC
2.54 BSC
-
-
h x 45o
-
0.358
0.358
-
9.09
9.09
2
-
0.010 S E F S
A1
0.342
8.69
E1
E2
E3
e
0.200 BSC
0.100 BSC
0.358
0.050 BSC
0.015
5.08 BSC
2.54 BSC
9.09
1.27 BSC
0.38
1.02 REF
0.51 REF
-
A
-
PLANE 2
PLANE 1
-
-
2
-
-E-
e1
h
-
-
2
5
5
-
0.040 REF
0.020 REF
j
0.007 M E F S H S
L
0.045
0.055
0.055
0.095
0.015
1.14
1.14
1.91
0.08
1.40
1.40
2.41
0.38
L1
L2
L3
ND
NE
N
0.045
0.075
0.003
-
B1
e
-
L3
L
-H-
-
5
5
5
5
3
3
3
20
20
Rev. 0 5/18/94
-F-
NOTES:
B3
E1
1. Metallized castellations shall be connected to plane 1 terminals
and extend toward plane 2 across at least two layers of ceramic
or completely across all of the ceramic layers to make electrical
connection with the optional plane 2 terminals.
L2
E2
B2
2. Unless otherwise specified, a minimum clearance of 0.015 inch
(0.38mm) shall be maintained between all metallized features
(e.g., lid, castellations, terminals, thermal pads, etc.)
L1
3. Symbol “N” is the maximum number of terminals. Symbols “ND”
and “NE” are the number of terminals along the sides of length
“D” and “E”, respectively.
D2
e1
D1
4. The required plane 1 terminals and optional plane 2 terminals (if
used) shall be electrically connected.
5. The corner shape (square, notch, radius, etc.) may vary at the
manufacturer’s option, from that shown on the drawing.
6. Chip carriers shall be constructed of a minimum of two ceramic
layers.
7. Dimension “A” controls the overall package thickness. The maxi-
mum “A” dimension is package height before being solder dipped.
8. Dimensioning and tolerancing per ANSI Y14.5M-1982.
9. Controlling dimension: INCH.
9
HA-5221
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 LEAD FINISH
F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A)
8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
-D-
E
-A-
INCHES
MIN
MILLIMETERS
BASE
(c)
METAL
SYMBOL
MAX
0.200
0.026
0.023
0.065
0.045
0.018
0.015
0.405
0.310
MIN
-
MAX
5.08
0.66
0.58
1.65
1.14
0.46
0.38
10.29
7.87
NOTES
b1
A
b
-
-
M
M
(b)
0.014
0.014
0.045
0.023
0.008
0.008
-
0.36
0.36
1.14
0.58
0.20
0.20
-
2
-B-
b1
b2
b3
c
3
SECTION A-A
bbb
C A - B
D
D
S
S
S
-
4
BASE
PLANE
Q
2
A
-C-
SEATING
PLANE
c1
D
3
L
α
5
S1
b2
eA
A A
e
E
0.220
5.59
5
eA/2
C A - B
b
C A - B
c
e
0.100 BSC
2.54 BSC
-
eA
eA/2
L
0.300 BSC
0.150 BSC
7.62 BSC
3.81 BSC
-
ccc
D
aaa
D
S
M
S
S
M
S
-
NOTES:
0.125
0.200
0.060
-
3.18
5.08
1.52
-
-
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
Q
0.015
0.38
6
S1
0.005
0.13
7
90o
105o
0.015
0.030
0.010
0.0015
90o
105o
0.38
0.76
0.25
0.038
-
α
aaa
bbb
ccc
M
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
-
-
-
-
-
-
-
-
-
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
-
2, 3
8
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
N
8
8
Rev. 0 4/94
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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10
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