5962-8601601XA_技术文档

80C88

CMOS 8/16-Bit Microprocessor

March 1997

Features

Description

• Compatible with NMOS 8088

The Intersil 80C88 high performance 8/16-bit CMOS CPU is

manufactured using a self-aligned silicon gate CMOS pro-

cess (Scaled SAJI IV). Two modes of operation, MINimum

for small systems and MAXimum for larger applications such

as multiprocessing, allow user conﬁguration to achieve the

highest performance level.

• Direct Software Compatibility with 80C86, 8086, 8088

• 8-Bit Data Bus Interface; 16-Bit Internal Architecture

[ /Title

(80C88

)

/Sub-

ject

• Completely Static CMOS Design

- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5MHz (80C88)

- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . .8MHz (80C88-2)

Full TTL compatibility (with the exception of CLOCK) and

industry-standard operation allow use of existing NMOS

8088 hardware and Intersil CMOS peripherals.

• Low Power Operation

(CMO

S 8/16-

Bit

Micro-

proces-

sor)

/Autho

r ()

/Key-

words

(Inter-

sil

- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . 500µA Maximum

- ICCOP . . . . . . . . . . . . . . . . . . . . 10mA/MHz Maximum

Complete software compatibility with the 80C86, 8086, and

8088 microprocessors allows use of existing software in new

designs.

• 1 Megabyte of Direct Memory Addressing Capability

• 24 Operand Addressing Modes

• Bit, Byte, Word, and Block Move Operations

• 8-Bit and 16-Bit Signed/Unsigned Arithmetic

• Bus-Hold Circuitry Eliminates Pull-up Resistors

• Wide Operating Temperature Ranges

o

- C80C88 . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to + 70 C

o

- I80C88 . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to +85 C

o

- M80C88 . . . . . . . . . . . . . . . . . . . . . . . -55 C to +125 C

Corpo-

ration,

8/16

Ordering Information

Bit uP,

micro-

proces-

sor, 8

bit, 16

bit, 8-

bit, 16-

bit,

8088,

PC)

/Cre-

ator ()

PACKAGE

Plastic DIP

TEMPERATURE RANGE

5MHz

8MHz

CP80C88-2

PKG. NO.

E40.6

o

0 C to +70 C

CP80C88

IP80C88

CS80C88

lS80C88

CD80C88

ID80C88

o

-40 C to +85 C

IP80C88-2

CS80C88-2

IS80C88-2

CD80C88-2

ID80C88-2

MD80C88-2/B

-

E40.6

N44.65

F40.6

J44.A

o

PLCC

0 C to +70 C

o

-40 C to +85 C

o

CERDIP

0 C to +70 C

o

-40 C to +85 C

o

-55 C to +125 C

MD80C88/B

o

SMD#

LCC

-55 C to +125 C

5962-8601601QA

MR80C88/B

o

-55 C to +125 C

MR80C88-2/B

-

o

SMD#

-55 C to +125 C

5962-8601601XA

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 2949.1

80C88

Pinouts

80C88 (DIP)

TOP VIEW

MIN

MODE

MAX

MODE

GND

A14

A13

A12

A11

A10

A9

1

2

3

4

5

6

7

8

9

40 V

CC

39 A15

38 A16/S3

37 A17/S4

36 A18/S5

35 A19/S6

34 SS0

(HIGH)

A8

33 MN/MX

32 RD

AD7

AD6 10

AD5 11

AD4 12

AD3 13

AD2 14

AD1 15

AD0 16

NMI 17

INTR 18

CLK 19

GND 20

31 HOLD

30 HLDA

29 WR

(RQ/GT0)

(RQ/GT1)

(LOCK)

(S2)

28 IO/M

27 DT/R

26 DEN

(S1)

(S0)

25 ALE

(QS0)

(QS1)

24 INTA

23 TEST

22 READY

21 RESET

80C88 (PLCC/LCC)

TOP VIEW

MAX MODE

80C88

MIN MODE

80C88

44

43 42 41 40

6

5

4

3

2

1

7

39

A10

A9

A10

A9

NC

A19/S6

38

37

36

35

34

33

32

31

30

29

8

A8

9

SS0

MN/MX

RD

(HIGH)

MN/MX

RD

AD7

AD6

AD5

AD4

AD3

AD2

10

11

12

13

14

15

16

17

AD7

AD6

AD5

AD4

AD3

AD2

HOLD

HLDA

WR

RQ/GT0

RQ/GT1

LOCK

S2

IO/M

AD1

AD0

AD1

AD0

DT/R

DEN

S1

S0

18 19 20 21 22 23 24 25 26 27 28

MIN MODE

80C88

MAX MODE

80C88

3-2

80C88

Functional Diagram

EXECUTION UNIT

REGISTER FILE

BUS INTERFACE UNIT

RELOCATION

REGISTER FILE

DATA POINTER

AND

INDEX REGS

(8 WORDS)

SEGMENT REGISTERS

AND

INSTRUCTION POINTER

(5 WORDS)

SSO/HIGH

16-BIT ALU

FLAGS

4

A19/S6. . . A16/S3

AD7-AD0

A8-A15

8

BUS

INTERFACE

UNIT

8

3

4

INTA, RD, WR

DT/R, DEN, ALE, IO/M

4-BYTE

INSTRUCTION

QUEUE

TEST

INTR

NMI

LOCK

2

QS0, QS1

CONTROL AND TIMING

RQ/GT0, 1

2

HOLD

HLDA

3

S2, S1, S0

3

CLK

RESET READY MN/MX

GND

V

CC

MEMORY INTERFACE

C-BUS

INSTRUCTION

STREAM BYTE

QUEUE

B-BUS

ES

CS

SS

BUS

INTERFACE

UNIT

DS

IP

EXECUTION UNIT

CONTROL SYSTEM

A-BUS

AH

AL

BL

CL

DL

ARITHMETIC/

LOGIC UNIT

BH

CH

DH

EXECUTION

UNIT

SP

BP

SI

FLAGS

DI

3-3

80C88

Pin Description

The following pin function descriptions are for 80C88 systems in either minimum or maximum mode. The “local bus” in these

descriptions is the direct multiplexed bus interface connection to the 80C88 (without regard to additional bus buffers).

SYMBOL

NUMBER

TYPE

DESCRIPTION

AD7-AD0

9-16

I/O

ADDRESS DATA BUS: These lines constitute the time multiplexed memory/IO address (T1) and

data (T2,T3,Tw and T4) bus. These lines are active HIGH and are held at high impedance to the last

valid level during interrupt acknowledge and local bus “hold acknowledge” or “grant sequence”

A15-A8

2-8, 39

O

ADDRESS BUS: These lines provide address bits 8 through 15 for the entire bus cycle (T1-T4).

These lines do not have to be latched by ALE to remain valid. A15-A8 are active HIGH and are held

at high impedance to the last valid logic level during interrupt acknowledge and local bus “hold

acknowledge” or “grant sequence”.

A19/S6,

A18/S5,

A17/S4,

A16/S3

35

36

37

38

O

ADDRESS/STATUS: During T1, these are the four most

S4

0

S3 CHARACTERISTICS

signiﬁcant address lines for memory operations. During

I/O operations, these lines are LOW. During memory and

I/O operations, status information is available on these

lines during T2, T3, TW and T4. S6 is always LOW. The

status of the interrupt enable ﬂag bit (S5) is updated at the

beginning of each clock cycle. S4 and S3 are encoded as

shown.

0

1

0

1

Alternate Data

Stack

0

1

Code or None

Data

1

This information indicates which segment register is

presently being used for data accessing.

These lines are held at high impedance to the last valid

logic level during local bus “hold acknowledge” or “grant

Sequence”.

RD

32

O

READ: Read strobe indicates that the processor is performing a memory or I/O read cycle, depend-

ing on the state of the IO/M pin or S2. This signal is used to read devices which reside on the 80C88

local bus. RD is active LOW during T2, T3, Tw of any read cycle, and is guaranteed to remain HIGH

in T2 until the 80C88 local bus has ﬂoated.

This line is held at a high impedance logic one state during “hold acknowledge” or “grant sequence”.

READY

INTR

22

18

I

READY: is the acknowledgment from the address memory or I/O device that it will complete the data

transfer. The RDY signal from memory or I/O is synchronized by the 82C84A clock generator to from

READY. This signal is active HIGH. The 80C88 READY input is not synchronized. Correct operation

is not guaranteed if the set up and hold times are not met.

INTERRUPT REQUEST: is a level triggered input which is sampled during the last clock cycle of

each instruction to determine if the processor should enter into an interrupt acknowledge operation.

A subroutine is vectored to via an interrupt vector lookup table located in system memory. It can be

internally masked by software resetting the interrupt enable bit. INTR is internally synchronized. This

signal is active HIGH.

TEST

NMI

23

17

I

TEST: input is examined by the “wait for test” instruction. If the TEST input is LOW, execution con-

tinues, otherwise the processor waits in an “idle” state. This input is synchronized internally during

each clock cycle on the leading edge of CLK.

NONMASKABLE INTERRUPT: is an edge triggered input which causes a type 2 interrupt. A sub-

routine is vectored to via an interrupt vector lookup table located in system memory. NMI is not

maskable internally by software. A transition from a LOW to HIGH initiates the interrupt at the end

of the current instruction. This input is internally synchronized.

RESET

CLK

21

I

RESET: cases the processor to immediately terminate its present activity. The signal must transition

LOW to HIGH and remain active HIGH for at least four clock cycles. It restarts execution, as de-

scribed in the instruction set description, when RESET returns LOW. RESET is internally synchro-

nized.

19

40

CLOCK: provides the basic timing for the processor and bus controller. It is asymmetric with a 33%

duty cycle to provide optimized internal timing.

V

: is the +5V power supply pin. A 0.1µF capacitor between pins 20 and 40 recommended for de-

CC

coupling.

GND

1, 20

33‘

GND: are the ground pins (both pins must be connected to system ground). A 0.1µF capacitor be-

tween pins 1 and 20 is recommended for decoupling.

MN/MX

I

MINIMUM/MAXIMUM: indicates the mode in which the processor is to operate. The two modes are

discussed in the following sections.

3-4

80C88

Pin Description (Continued)

The following pin function descriptions are for 80C88 system in minimum mode (i.e., MN/MX = V ). Only the pin functions

CC

which are unique to the minimum mode are described; all other pin functions are as described above.

MINIMUM MODE SYSTEM

SYMBOL

NUMBER

TYPE

DESCRIPTION

IO/M

28

O

STATUS LINE: is an inverted maximum mode S2. It is used to distinguish a memory access from

an I/O access. IO/M becomes valid in the T4 preceding a bus cycle and remains valid until the ﬁnal

T4 of the cycle (I/O = HIGH, M = LOW). IO/M is held to a high impedance logic one during local bus

“hold acknowledge”.

WR

29

O

Write: strobe indicates that the processor is performing a write memory or write I/O cycle, depend-

ing on the state of the IO/M signal. WR is active for T2, T3, and Tw of any write cycle. It is active

LOW, and is held to high impedance logic one during local bus “hold acknowledge”.

INTA

ALE

24

25

O

INTA: is used as a read strobe for interrupt acknowledge cycles. It is active LOW during T2, T3 and

Tw of each interrupt acknowledge cycle. Note that INTA is never ﬂoated.

ADDRESS LATCH ENABLE: is provided by the processor to latch the address into the

82C82/82C83 address latch. It is a HIGH pulse active during clock low of T1 of any bus cycle. Note

that ALE is never ﬂoated.

DT/R

DEN

27

26

O

DATA TRANSMIT/RECEIVE: is needed in a minimum system that desires to use an 82C86/82C87

data bus transceiver. It is used to control the direction of data ﬂow through the transceiver. Logically,

DT/R is equivalent to S1 in the maximum mode, and its timing is the same as for IO/M (T = HIGH,

R = LOW). This signal is held to a high impedance logic one during local bus “hold acknowledge”.

DATA ENABLE: is provided as an output enable for the 82C86/82C87 in a minimum system which

uses the transceiver. DEN is active LOW during each memory and I/O access, and for INTA cycles.

For a read or INTA cycle, it is active from the middle of T2 until the middle of T4, while for a write

cycle, it is active from the beginning of T2 until the middle of T4. DEN is held to high impedance logic

one during local bus “hold acknowledge”.

HOLD,

HLDA

31

30

I

O

HOLD: indicates that another master is requesting a local bus “hold”. To be acknowledged, HOLD

must be active HIGH. The processor receiving the “hold” request will issue HLDA (HIGH) as an

acknowledgment, in the middle of a T4 or T1 clock cycle. Simultaneous with the issuance of HLDA

the processor will ﬂoat the local bus and control lines. After HOLD is detected as being LOW, the

processor lowers HLDA, and when the processor needs to run another cycle, it will again drive the

local bus and control lines.

Hold is not an asynchronous input. External synchronization should be provided if the system cannot

otherwise guarantee the set up time.

SS0

34

O

STATUS LINE: is logically equivalent to S0

IO/M

DT/R

SS0 CHARACTERISTICS

in the maximum mode. The combination of

SS0, IO/M and DT/R allows the system to

completely decode the current bus cycle

status. SS0 is held to high impedance logic

one during local bus “hold acknowledge”.

1

0

1

0

1

0

1

0

1

0

1

0

1

Interrupt Acknowledge

Read I/O Port

Write I/O Port

Halt

Code Access

Read Memory

Write Memory

Passive

3-5

80C88

Pin Description (Continued)

The following pin function descriptions are for 80C88 system in maximum mode (i.e., MN/MX = GND). Only the pin functions

which are unique to the maximum mode are described; all other pin functions are as described above.

MAXIMUM MODE SYSTEM

SYMBOL

NUMBER

TYPE

DESCRIPTION

S0

S1

S2

26

27

28

O

STATUS: is active during clock high of T4, T1 and

S2

0

S1

0

S0

0

CHARACTERISTICS

Interrupt Acknowledge

Read I/O Port

Write I/O Port

Halt

T2, and is returned to the passive state (1, 1, 1)

during T3 or during Tw when READY is HIGH. This

status is used by the 82C88 bus controller to gener-

ate all memory and I/O access control signals. Any

change by S2, S1 or S0 during T4 is used to

indicate the beginning of a bus cycle, and the return

to the passive state in T3 or Tw is used to indicate

the end of a bus cycle.

0

1

0

1

0

1

0

Code Access

Read Memory

Write Memory

Passive

1

0

1

These signals are held at a high impedance logic

one state during “grant sequence”.

1

0

1

RQ/GT0,

RQ/GT1

31

30

I/O

REQUEST/GRANT: pins are used by other local bus masters to force the processor to release the

local bus at the end of the processor’s current bus cycle. Each pin is bidirectional with RQ/GT0

having higher priority than RQ/GT1. RQ/GT has internal bus-hold high circuitry and, if unused, may

be left unconnected. The request/grant sequence is as follows (see RQ/GT Timing Sequence):

1. A pulse of one CLK wide from another local bus master indicates a local bus request (“hold”) to

the 80C88 (pulse 1).

2. During a T4 or T1 clock cycle, a pulse one clock wide from the 80C88 to the requesting master

(pulse 2), indicates that the 80C88 has allowed the local bus to float and that it will enter the

“grant sequence” state at the next CLK. The CPUs bus interface unit is disconnected logically

from the local bus during “grant sequence”.

3. A pulse one CLK wide from the requesting master indicates to the 80C88 (pulse 3) that the “hold”

request is about to end and that the 80C88 can reclaim the local bus at the next CLK. The CPU

then enters T4 (or T1 if no bus cycles pending).

Each master-master exchange of the local bus is a sequence of three pulses. There must be one

idle CLK cycle after bus exchange. Pulses are active LOW.

If the request is made while the CPU is performing a memory cycle, it will release the local bus during

T4 of the cycle when all the following conjugations are met:

1. Request occurs on or before T2.

2. Current cycle is not the low bit of a word.

3. Current cycle is not the first acknowledge of an interrupt acknowledge sequence.

4. A locked instruction is not currently executing.

If the local bus is idle when the request is made the two possible events will follow:

1. Local bus will be released during the next clock.

2. A memory cycle will start within 3 clocks. Now the four rules for a currently active memory cycle

apply with condition number 1 already satisfied.

LOCK

29

O

LOCK: indicates that other system bus masters are not to gain control of the system bus while

LOCK is active (LOW). The LOCK signal is activated by the “LOCK” preﬁx instruction and remains

active until the completion of the next instruction. This signal is active LOW, and is held at a high

impedance logic one state during “grant sequence”. In Max Mode, LOCK is automatically generated

during T2 of the ﬁrst INTA cycle and removed during T2 of the second INTA cycle.

QS1, QS0

24, 25

QUEUE STATUS: provide status to allow external

tracking of the internal 80C88 instruction queue.

QS1 QS0

CHARACTERISTICS

No Operation

0

1

The queue status is valid during the CLK cycle after

which the queue operation is performed. Note that

the queue status never goes to a high impedance

statue (ﬂoated).

First Byte of Opcode from

Queue

1

0

1

Empty the Queue

Subsequent Byte from

Queue

-

34

O

Pin 34 is always a logic one in the maximum mode and is held at a high impedance logic one during

a “grant sequence”.

3-6

80C88

as a linear array of up to 1 million bytes, addressed as

Functional Description

00000(H) to FFFFF(H). The memory is logically divided into

code, data, extra, and stack segments of up to 64K bytes

each, with each segment falling on 16 byte boundaries. (See

Figure 1).

Static Operation

All 80C88 circuitry is static in design. Internal registers,

counters and latches are static and require not refresh as

with dynamic circuit design. This eliminates the minimum

operating frequency restriction placed on other microproces-

sors. The CMOS 80C88 can operate from DC to the

speciﬁed upper frequency limit. The processor clock may be

stopped in either state (high/low) and held there indeﬁnitely.

This type of operation is especially useful for system debug

or power critical applications.

7

0

FFFFFH

64K-BIT

CODE SEGMENT

XXXXOH

The 80C88 can be single stepped using only the CPU clock.

This state can be maintained as long as is necessary. Single

step clock operation allows simple interface circuitry to

provide critical information for start-up.

STACK SEGMENT

DATA SEGMENT

+ OFFSET

WORD

SEGMENT

REGISTER FILE

Static design also allows very low frequency operation (as

low as DC). In a power critical situation, this can provide

extremely low power operation since 80C88 power dissipa-

tion is directly related to operation frequency. As the system

frequency is reduced, so is the operating power until, at a

DC input frequency, the power requirement is the 80C88

standby current.

LSB

BYTE

MSB

CS

SS

DS

ES

EXTRA SEGMENT

00000H

Internal Architecture

FIGURE 14. MEMORY ORGANIZATION

The internal functions of the 80C88 processor are

partitioned logically into two processing units. The ﬁrst is the

Bus Interface Unit (BIU) and the second is the Execution

Unit (EU) as shown in the CPU block diagram.

All memory references are made relative to base addresses

contained in high speed segment registers. The segment

types were chosen based on the addressing needs of

programs. The segment register to be selected is automati-

cally chosen according to speciﬁc rules as shown in Table 1.

All information in one segment type share the same logical

attributes (e.g., code or data). By structuring memory into

relocatable areas of similar characteristics and by automati-

cally selecting segment registers, programs are shorter,

faster, and more structured.

These units can interact directly but for the most part

perform as separate asynchronous operational processors.

The bus interface unit provides the functions related to

instruction fetching and queuing, operand fetch and store,

and address relocation. This unit also provides the basic bus

control. The overlap of instruction pre-fetching provided by

this unit serves to increase processor performance through

improved bus bandwidth utilization. Up to 4 bytes of the

instruction stream can be queued while waiting for decoding

and execution.

TABLE 6.

MEMORY

REFERENCE

NEED

SEGMENT

REGISTER

USED

SEGMENT

SELECTION RULE

The instruction stream queuing mechanism allows the BIU

to keep the memory utilized very efﬁciently. Whenever there

is space for at least 1 byte in the queue, the BIU will attempt

a byte fetch memory cycle. This greatly reduces “dead time”:

on the memory bus. The queue acts as a First-In-First-Out

(FIFO) buffer, from which the EU extracts instruction bytes

as required. If the queue is empty (following a branch

instruction, for example), the ﬁrst byte into the queue

immediately becomes available to the EU.

Instructions

CODE (CS)

Automatic with all instruction

prefetch.

Stack

STACK (SS) All stack pushes and pops.

Memory references relative to

BP base register except data

references.

Local Data

DATA (DS)

Data references when: relative

to stack, destination of string op-

eration, or explicitly overridden.

The execution unit receives pre-fetched instructions from the

BIU queue and provides unrelocated operand addresses to

the BIU. Memory operands are passed through the BIU for

processing by the EU, which passes results to the BIU for

storage.

External Data

(Global)

EXTRA (ES) Destination of string

operations: Explicitly selected

using a segment override.

Word (16-bit) operands can be located on even or odd

address boundaries. For address and data operands, the

least signiﬁcant byte of the word is stored in the lower valued

address location and the most signiﬁcant byte in the next

higher address location.

Memory Organization

The processor provides a 20-bit address to memory which

locates the byte being referenced. The memory is organized

3-7

80C88

The BIU will automatically execute two fetch or write cycles the strap pin. When the MN/MX pin is strapped to GND, the

for 16-bit operands.

80C88 deﬁnes pins 24 through 31 and 34 in maximum

mode. When the MN/MX pins is strapped to V , the 80C88

generates bus control signals itself on pins 24 through 31

and 34.

CC

Certain locations in memory are reserved for speciﬁc CPU

operations. (See Figure 2). Locations from addresses

FFFF0H through FFFFFH are reserved for operations

including a jump to initial system initialization routine. Follow- The minimum mode 80C88 can be used with either a

ing RESET, the CPU will always begin execution at location muliplexed or demultiplexed bus. This architecture provides

FFFF0H where the jump must be located. Locations 00000H the 80C88 processing power in a highly integrated form.

through 003FFH are reserved for interrupt operations. Each

The demultiplexed mode requires one latch (for 64K addres-

of the 256 possible interrupt service routines is accessed

sability) or two latches (for a full megabyte of addressing).

through its own pair of 16-bit pointers - segment address

An 82C86 or 82C87 transceiver can also be used if data bus

pointer and offset address pointer. The ﬁrst pointer, used as

buffering is required. (See Figure 3). The 80C88 provides

the offset address, is loaded into the IP, and the second

DEN and DT/R to control the transceiver, and ALE to latch

pointer, which designates the base address, is loaded into

the addresses. This conﬁguration of the minimum mode pro-

the CS. At this point program control is transferred to the

vides the standard demultiplexed bus structure with heavy

interrupt routine. The pointer elements are assumed to have

bus buffering and relaxed bus timing requirements.

been stored at their respective places in reserved memory

prior to the occurrence of interrupts.

The maximum mode employs the 82C88 bus controller (See

Figure 4). The 82C88 decode status lines S0, S1 and S2,

and provides the system with all bus control signals. Moving

the bus control to the 82C88 provides better source and sink

current capability to the control lines, and frees the 80C88

pins for extended large system features. Hardware lock,

queue status, and two request/grant interfaces are provided

by the 80C88 in maximum mode. These features allow

coprocessors in local bus and remote bus conﬁgurations.

Minimum and Maximum Modes

The requirements for supporting minimum and maximum

80C88 systems are sufﬁciently different that they cannot be

done efﬁciently with 40 uniquely deﬁned pins. Consequently,

the 80C88 is equipped with a strap pin (MN/MX) which

deﬁnes the system conﬁguration. The deﬁnition of a certain

subset of the pins changes, dependent on the condition of

FFFFFH

FFFF0H

RESET BOOTSTRAP

PROGRAM JUMP

TYPE 255 POINTER

(AVAILABLE)

3FFH

3FCH

AVAILABLE

INTERRUPT

POINTERS

(224)

TYPE 33 POINTER

(AVAILABLE)

084H

080H

07FH

TYPE 32 POINTER

(AVAILABLE)

TYPE 31 POINTER

(AVAILABLE)

RESERVED

INTERRUPT

POINTERS

(27)

TYPE 5 POINTER

(RESERVED)

014H

TYPE 4 POINTER

OVERFLOW

010H

00CH

008H

004H

000H

TYPE 3 POINTER

1 BYTE INT INSTRUCTION

DEDICATED

INTERRUPT

POINTERS

(5)

TYPE 2 POINTER

NON MASKABLE

TYPE 1 POINTER

SINGLE STEP

TYPE 0 POINTER

DIVIDE ERROR

CS BASE ADDRESS

IP OFFSET

16-BITS

FIGURE 15. RESERVED MEMORY LOCATIONS

3-8

80C88

V

CC

V

MN/MX

IO/M

CC

82C84A/85

CLK

RD

READY

RESET

RES

RDY

WR

CLOCK

GENERATOR

INTA

DT/R

DEN

GND

80C88

CPU

STB

OE

ALE

1

GND

ADDR/DATA

AD0-AD7

A8-A19

C1

C2

ADDRESS

V

CC

82C82

20

LATCH

GND

(1, 2 OR 3)

40

V

CC

T

C1 = C2 = 0.1µF

INTR

OE

DATA

82C86

TRANSCEIVER

OE

CS

RD WR

EN

82C59A

INTERRUPT

CONTROL

HM-65162

CMOS PROM

HS-6616

CMOS PROM

82CXX

PERIPHERALS

INT

IR0-7

FIGURE 16. DEMULTIPLEXED BUS CONFIGURATION

V

CC

CLK

S0

GND

MRDC

MWTC

AMWC

IORC

MN/MX

S0

82C84A/85

CLK

82C88

NC

READY

RESET

RES

RDY

S1

S2

S1

S2

IOWC

AIOWC

INTA

DEN

DT/R

ALE

GND

80C88

CPU

STB

OE

1

GND

ADDR/DATA

AD0-AD7

A8-A19

GND

C1

ADDRESS

V

CC

82C82

20

LATCH

(1, 2 OR 3)

C2

40

V

CC

T

C1 = C2 = 0.1µF

INT

OE

DATA

82C86

TRANSCEIVER

OE

CS

RD WR

82C59A

INTERRUPT

CONTROL

HM-65162

CMOS PROM

HS-6616

CMOS PROM

82CXX

PERIPHERALS

IR0-7

FIGURE 17. FULLY BUFFERED SYSTEM USING BUS CONTROLLER

3-9

80C88

Bus Operation

the same duration as a CLK cycle. Periods can occur

between 80C88 driven bus cycles. These are referred to as

“idle” states (TI), or inactive CLK cycles. The processor uses

these cycles for internal housekeeping.

The 80C88 address/data bus is broken into three parts: the

lower eight address/data bits (AD0-AD7), the middle eight

address bits (A8-A15), and the upper four address bits (A16-

A19). The address/data bits and the highest four address During T1 of any bus cycle, the ALE (Address latch enable)

bits are time multiplexed. This technique provides the most signal is emitted (by either the processor or the 82C88 bus

efﬁcient use of pins on the processor, permitting the use of controller, depending on the MN/MX strap). At the trailing

standard 40 lead package. The middle eight address bits are edge of this pulse, a valid address and certain status infor-

not multiplexed, i.e., they remain valid throughout each bus mation for the cycle may be latched.

cycle. In addition, the bus can be demultiplexed at the

Status bits S0, S1, and S2 are used by the bus controller, in

processor with a single address latch if a standard, nonmulti-

maximum mode, to identify the type of bus transaction

plexed bus is desired for the system.

according to Table 2.

Each processor bus cycle consists of at least four CLK

Status bits S3 through S6 are multiplexed with high order

cycles. These are referred to as T1, T2, T3 and T4. (See

address bits and are therefore valid during T2 through T4.

Figure 5). The address is emitted from the processor during

S3 and S4 indicate which segment register was used to this

T1 and data transfer occurs on the bus during T3 and T4. T2

bus cycle in forming the address according to Table 3.

is used primarily for changing the direction of the bus during

read operations. In the event that a “Not Ready” indication is

given by the addressed device, “wait” states (TW) are

inserted between T3 and T4. Each inserted “wait” state is of

S5 is a reﬂection of the PSW interrupt enable bit. S6 is

always equal to 0.

(4 + NWAIT) = TCY

T1

T2

T3

TWAIT

T4

T1

T2

T3

TWAIT

T4

CLK

GOES INACTIVE IN THE STATE

JUST PRIOR TO T4

ALE

S2-S0

ADDR

STATUS

A19-A16

S6-S3

A15-A8

ADDR

D15-D0

VALID

BUS RESERVED

FOR DATA IN

ADDR DATA

A7-A0

DATA OUT (D7-D0)

RD, INTA

READY

WAIT

DT/R

DEN

WP

MEMORY ACCESS TIME

FIGURE 18. BASIC SYSTEM TIMING

3-10

80C88

Bus Hold Circuitry

TABLE 7.

CHARACTERISTICS

To avoid high current conditions caused by ﬂoating inputs to

CMOS devices and to eliminate the need for pull-up/down

resistors, “bus-hold” circuitry has been used on 80C88 pins

2-16, 26-32 and 34-39 (see Figure 6A and 6B). These

circuits maintain a valid logic state if no driving source is

present (i.e., an unconnected pin or a driving source which

goes to a high impedance state).

S2

0

S1

0

S0

0

Interrupt Acknowledge

Read I/O

0

1

0

1

0

Write I/O

0

1

Halt

1

0

Instruction Fetch

Read Data from Memory

Write Data to Memory

Passive (No Bus Cycle)

To override the “bus hold” circuits, an external driver must be

capable of supplying 400µA minimum sink or source current

at valid input voltage levels. Since this “bus hold” circuitry is

active and not a “resistive” type element, the associated

power supply current is negligible. Power dissipation is sig-

niﬁcantly reduced when compared to the use of passive pull-

up resistors.

1

0

1

0

1

TABLE 8.

EXTERNAL

BOND

PAD

S4

S3

0

CHARACTERISTICS

0

1

Alternate Data (Extra Segment)

OUTPUT

DRIVER

1

Stack

INPUT

BUFFER

0

Code or None

Data

INPUT

PROTECTION

CIRCUITRY

1

I/O Addressing

FIGURE 19A. BUS HOLD CIRCUITRY PIN 2-16, 35-39

In the 80C88, I/O operations can address up to a maximum

of 64K I/O registers. The I/O address appears in the same

format as the memory address on bus lines A15-A0. The

address lines A19-A16 are zero in I/O operations. The vari-

able I/O instructions, which use register DX as a pointer,

have full address capability, while the direct I/O instructions

directly address one or two of the 256 I/O byte locations in

page 0 of the I/O address space. I/O ports are addressed in

the same manner as memory locations.

EXTERNAL

BOND

PAD

V

P

CC

OUTPUT

DRIVER

INPUT

BUFFER

Designers familiar with the 8085 or upgrading an 8085

design should note that the 8085 addresses I/O with an 8-bit

address on both halves of the 16-bit address bus. The

80C88 uses a full 16-bit address on its lower 16 address

lines.

INPUT

PROTECTION

CIRCUITRY

FIGURE 19B. BUS HOLD CIRCUITRY PIN 26-32, 34

External Interface

Interrupt Operations

Interrupt operations fall into two classes: software or

hardware initiated. The software initiated interrupts and

software aspects of hardware interrupts are speciﬁed in the

instruction set description. Hardware interrupts can be

classiﬁed as nonmaskable or maskable.

Processor Reset and Initialization

Processor initialization or start up is accomplished with

activation (HIGH) of the RESET pin. The 80C88 RESET is

required to be HIGH for greater than four clock cycles. The

80C88 will terminate operations on the high-going edge of

RESET and will remain dormant as long as RESET is HIGH.

The low-going transition of RESET triggers an internal reset

sequence for approximately 7 clock cycles. After this interval

the 80C88 operates normally, beginning with the instruction

in absolute location FFFFOH (see Figure 2). The RESET

input is internally synchronized to the processor clock. At

initialization, the HIGH to LOW transition of RESET must

occur no sooner than 50µs after power up, to allow complete

initialization of the 80C88.

Interrupts result in a transfer of control to a new program

location. A 256 element table containing address pointers to

the interrupt service program locations resides in absolute

locations 0 through 3FFH (see Figure 2), which are reserved

for this purpose. Each element in the table is 4 bytes in size

and corresponds to an interrupt “type”. An interrupting

device supplies an 8-bit type number, during the interrupt

acknowledge sequence, which is used to vector through the

appropriate element to the new interrupt service program

location.

NMI will not be recognized if asserted prior to the second

CLK cycle following the end of RESET.

3-11

80C88

Non-Maskable Interrupt (NMI)

T1

T3

T1

T2

T3

T4

T2

T4

The processor provides a single non-maskable interrupt

(NMI) pin which has higher priority than the maskable

interrupt request (INTR) pin. A typical use would be to

activate a power failure routine. The NMI is edge-triggered

on a LOW to High transition. The activation of this pin

causes a type 2 interrupt.

ALE

LOCK

NMI is required to have a duration in the HIGH state of

greater than two clock cycles, but is not required to be

synchronized to the clock. An high going transition of NMI is

latched on-chip and will be serviced at the end of the current

instruction or between whole moves (2 bytes in the case of

word moves) of a block type instruction. Worst case

response to NMI would be for multiply, divide, and variable

shift instructions. There is no speciﬁcation on the occurrence

of the low-going edge; it may occur before, during, or after

INTA

AD0-

AD7

TYPE

VECTOR

FIGURE 20. INTERRUPT ACKNOWLEDGE SEQUENCE

Halt

the servicing of NMI. Another high-going edge triggers When a software HALT instruction is executed, the proces-

another response if it occurs after the start of the NMI sor indicates that it is entering the HALT state in one of two

procedure.

ways, depending upon which mode is strapped. In minimum

mode, the processor issues ALE, delayed by one clock

cycle, to allow the system to latch the halt status. Halt status

is available on IO/M, DT/R, and SS0. In maximum mode, the

processor issues appropriate HALT status on S2, S1 and

S0, and the 82C88 bus controller issues one ALE. The

80C88 will not leave the HALT state when a local bus hold is

entered while in HALT. In this case, the processor reissues

the HALT indicator at the end of the local bus hold. An inter-

rupt request or RESET will force the 80C88 out of the HALT

state.

The signal must be free of logical spikes in general and be

free of bounces on the low-going edge to avoid triggering

extraneous responses.

Maskable Interrupt (INTR)

The 80C88 provides a singe interrupt request input (INTR)

which can be masked internally by software with the

resetting of the interrupt enable (IF) ﬂag bit. The interrupt

request signal is level triggered. It is internally synchronized

during each clock cycle on the high-going edge of CLK.

Read/Modify/Write (Semaphore) Operations Via LOCK

To be responded to, INTR must be present (HIGH) during

the clock period preceding the end of the current instruction

or the end of a whole move for a block type instruction. INTR

may be removed anytime after the falling edge of the ﬁrst

INTA signal. During interrupt response sequence, further

interrupts are disabled. The enable bit is reset as part of the

response to any interrupt (INTR, NMI, software interrupt, or

single step). The FLAGS register, which is automatically

pushed onto the stack, reﬂects the state of the processor

prior to the interrupt. The enable bit will be zero until the old

FLAGS register is restored, unless speciﬁcally set by an

instruction.

The LOCK status information is provided by the processor

when consecutive bus cycles are required during the execu-

tion of an instruction. This allows the processor to perform

read/modify/write operations on memory (via the “exchange

register with memory” instruction), without another system

bus master receiving intervening memory cycles. This is

useful in multiprocessor system conﬁgurations to accomplish

“test and set lock” operations. The LOCK signal is activated

(LOW) in the clock cycle following decoding of the LOCK

preﬁx instruction. It is deactivated at the end of the last bus

cycle of the instruction following the LOCK preﬁx. While

LOCK is active, a request on a RQ/GT pin will be recorded,

and then honored at the end of the LOCK.

During the response sequence (see Figure 7), the processor

executes two successive (back-to-back) interrupt acknowl-

edge cycles. The 80C88 emits to LOCK signal (maximum

mode only) from T2 of the ﬁrst bus cycle until T2 of the sec-

ond. A local bus “hold” request will not be honored until the

end of the second bus cycle. In the second bus cycle, a byte

is fetched from the external interrupt system (e.g., 82C59A

PIC) which identiﬁes the source (type) of the interrupt. This

byte is multiplied by four and used as a pointer into the inter-

rupt vector lookup table.

External Synchronization Via TEST

As an alternative to interrupts, the 80C88 provides a single

software-testable input pin (TEST). This input is utilized by

executing a WAIT instruction. The single WAIT instruction is

repeatedly executed until the TEST input goes active (LOW).

The execution of WAIT does not consume bus cycles once

the queue is full.

If a local bus request occurs during WAIT execution, the

80C88 three-states all output drivers while inputs and I/O

pins are held at valid logic levels by internal bus-hold circuits.

If interrupts are enabled, the 80C88 will recognize interrupts

and process them when it regains control of the bus.

An INTR signal left HIGH will be continually responded to

within the limitations of the enable bit and sample period.

INTR may be removed anytime after the falling edge of the

ﬁrst INTA signal. The interrupt return instruction includes a

ﬂags pop which returns the status of the original interrupt

enable bit when it restores the ﬂags.

3-12

80C88

Basic System Timing

conﬁguration, although their timing remains relatively the

same. The 80C88 status outputs (S2, S1 and S0) provide

type of cycle information and become 82C88 inputs. This

bus cycle information speciﬁes read (code, data or I/O), write

(data or I/O), interrupt acknowledge, or software halt. The

82C88 thus issues control signals specifying memory read

or write, I/O read or write, or interrupt acknowledge. The

82C88 provides two types of write strobes, normal and

advanced, to be applied as required. The normal write

strobes have data valid at the leading edge of write. The

advanced write strobes have the same timing as read

strobes, and hence, data is not valid at the leading edge of

write. The 82C86/82C87 transceiver receives the usual T

and OE inputs from the 82C88 DT/R and DEN outputs.

In minimum mode, the MN/MX pin is strapped to V

and

CC

the processor emits bus control signals (RD, WR, IO/M, etc.)

directly. In maximum mode, the MN/MX pin is strapped to

GND and the processor emits coded status information

which the 82C88 bus controller uses to generate

MULTIBUS compatible bus control signals.

System Timing - Minimum System

The read cycle begins in T1 with the assertion of the

address latch enable (ALE) signal (see Figure 5). The trail-

ing (low going) edge of this signal is used to latch the

address information, which is valid on the address data bus

(ADO-AD7) at this time, into the 82C82/82C83 latch.

Address lines A8 through A15 do not need to be latched

because they remain valid throughout the bus cycle. From

T1 to T4 the IO/M signal indicates a memory or I/O opera-

tion. At T2 the address is removed from the address data

bus and the bus is held at the last valid logic state by internal

bus-hold devices. The read control signal is also asserted at

T2. The read (RD) signal causes the addressed device to

enable its data bus drivers to the local bus. Some time later,

valid data will be available on the bus and the addressed

The pointer into the interrupt vector table, which is passed

during the second INTA cycle, can derive from an 82C59A

located on either the local bus or the system bus. If the

master 82C59A priority interrupt controller is positioned on

the local bus, the 82C86/82C87 transceiver must be

disabled when reading from the master 82C59A during the

interrupt acknowledge sequence and software “poll”.

The 80C88 Compared to the 80C86

device will drive the READY line HIGH. When the processor The 80C88 CPU is a 8-bit processor designed around the

returns the read signal to a HIGH level, the addressed 8086 internal structure. Most internal functions of the 80C88

device will again three-state its bus drivers. If a transceiver are identical to the equivalent 80C86 functions. The 80C88

(82C86/82C87) is required to buffer the local bus, signals handles the external bus the same way the 80C86 does with

DT/R and DEN are provided by the 80C88.

the distinction of handling only 8-bits at a time. Sixteen-bit

operands are fetched or written in two consecutive bus

cycles. Both processors will appear identical to the software

engineer, with the exception of execution time. The internal

register structure is identical and all instructions have the

same end result. Internally, there are three differences

between the 80C88 and the 80C86. All changes are related

to the 8-bit bus interface.

A write cycle also begins with the assertion of ALE and the

emission of the address. The IO/M signal is again asserted

to indicate a memory or I/O write operation. In T2, immedi-

ately following the address emission, the processor emits

the data to be written into the addressed location. This data

remains valid until at least the middle of T4. During T2, T3,

and Tw, the processor asserts the write control signal. The

write (WR) signal becomes active at the beginning of T2, as • The queue length is 4 bytes in the 80C88, whereas the

opposed to the read, which is delayed somewhat into T2 to

provide time for output drivers to become inactive.

80C86 queue contains 6 bytes, or three words. The queue

was shortened to prevent overuse of the bus by the BIU

when prefetching instructions. This was required because

of the additional time necessary to fetch instructions 8-bits

at a time.

The basic difference between the interrupt acknowledge

cycle and a read cycle is that the interrupt acknowledge

(INTA) signal is asserted in place of the read (RD) signal and

the address bus is held at the last valid logic state by internal • To further optimize the queue, the prefetching algorithm

bus-hold devices (see Figure 6). In the second of two

successive INTA cycles, a byte of information is read from

the data bus, as supplied by the interrupt system logic (i.e.,

82C59A priority interrupt controller). This byte identiﬁes the

source (type) of the interrupt. It is multiplied by four and used

as a pointer into the interrupt vector lookup table, as

described earlier.

was changed. The 80C88 BIU will fetch a new instruction

to load into the queue each time there is a 1 byte space

available in the queue. The 80C86 waits until a 2 byte

space is available.

• The internal execution time of the instruction set is

affected by the 8-bit interface. All 16-bit fetches and writes

from/to memory take an additional four clock cycles. The

CPU is also limited by the speed of instruction fetches.

This latter problem only occurs when a series of simple

operations occur. When the more sophisticated instruc-

tions of the 80C88 are being used, the queue has time to

ﬁll the execution proceeds as fast as the execution unit will

allow.

Bus Timing - Medium Complexity Systems

For medium complexity systems, the MN/MX pin is

connected to GND and the 82C88 bus controller is added to

the system, as well as an 82C82/82C83 latch for latching the

system address, and an 82C86/82C87 transceiver to allow

for bus loading greater than the 80C88 is capable of

handling (see Figure 8). Signals ALE, DEN, and DT/R are

generated by the 82C88 instead of the processor in this

MULTIBUS is a patented Intel bus.

3-13

80C88

The 80C88 and 80C86 are completely software compatible • BHE has no meaning on the 80C88 and has been elimi-

by virtue of their identical execution units. Software that is

system dependent may not be completely transferable, but

software that is not system dependent will operate equally

as well on an 80C88 or an 80C86.

nated.

• SS0 provides the S0 status information in the minimum

mode. This output occurs on pin 34 in minimum mode

only. DT/R, IO/M and SS0 provide the complete bus status

in minimum mode.

The hardware interface of the 80C88 contains the major

differences between the two CPUs. The pin assignments are

nearly identical, however, with the following functional

changes:

• IO/M has been inverted to be compatible with the 8085

bus structure.

• ALE is delayed by one clock cycle in the minimum mode

when entering HALT, to allow the status to be latched with

ALE.

• A8-A15: These pins are only address outputs on the

80C88. These address lines are latched internally and

remain valid throughout a bus cycle in a manner similar to

the 8085 upper address lines.

T1

T2

T3

T4

CLK

QS1, QS0

80C88

S2, S1, S0

A19/S6 - A16/S3

ALE

A19 - A16

S6 - S3

RDY 82C84

80C88

READY 80C88

AD7 - AD0

DATA OUT

A7-A0

DATA IN

A15 - A8

80C88

RD

DT/R

80C88

MRDC

DEN

FIGURE 21. MEDIUM COMPLEXITY SYSTEM TIMING

3-14

80C88

Absolute Maximum Ratings

Thermal Information

o

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+8.0V Thermal Resistance (Typical)

θ_JA( C/W) θ_JC( C/W)

Input, Output or I/O Voltage . . . . . . . . . . . GND -0.5V to V

ESD Classiﬁcation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

+0.5V

CC

PDIP Package . . . . . . . . . . . . . . . . . . .

PLCC Package . . . . . . . . . . . . . . . . . .

SBDIP Package. . . . . . . . . . . . . . . . . .

CLCC Package . . . . . . . . . . . . . . . . . .

Maximum Junction Temperature

Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C

Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150 C

Storage Temperature Range. . . . . . . . . . . . . . . . . .-65 C to +150 C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300 C

50

46

30

40

-

N/A

Operating Conditions

Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V

M80C88-2 Only. . . . . . . . . . . . . . . . . . . . . . . . . +4.75V to +5.25V

Operating Temperature Range

o

C80C88/-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to +70 C

o

I80C88/-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to +85 C

(Lead tips only for surface mount packages)

o

M80C88/-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to +125 C

Die Characteristics

Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9750 Gates

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

o

DC Electrical Speciﬁcations

V

= 5.0V, ±10%; T = 0 C to +70 C (C80C88, C80C88-2)

A

CC

o

= 5.0V, ±10%; T = -40 C to +85 C (l80C88, I80C88-2)

A

o

= 5.0V, ±10%; T = -55 C to +125 C (M80C88)

A

o

= 5.0V, ±5%; T = -55 C to +125 C (M80C88-2)

A

SYMBOL

PARAMETER

MIN

MAX

UNITS

TEST CONDITION

V

Logical One

Input Voltage

2.0

2.2

-

V

C80C88, I80C88 (Note 4)

M80C88 (Note 4)

lH

V

Logical Zero Input Voltage

CLK Logical One Input Voltage

CLK Logical Zero Input Voltage

Output High Voltage

-

0.8

-

V

IL

VIHC

VILC

V

-0.8

CC

-

0.8

-

V

3.0

V

lOH = -2.5mA

lOH = -100µA

OH

V

-0.4

CC

V

Output Low Voltage

-

0.4

1.0

V

lOL = +2.5mA

OL

I

Input Leakage Current

-1.0

µA

V

= 0V or V

CC

I

IN

Pins 17-19, 21-23, 33

lBHH

lBHL

Input Current-Bus Hold High

Input Current-Bus Hold Low

Output Leakage Current

-40

-400

400

-10.0

500

10

µA

V

= - 3.0V (Note 1)

= - 0.8V (Note 2)

IN

40

-

I

µA

V

= 0V (Note 5)

O

OUT

V = 5.5V (Note 3)

CC

ICCSB

ICCOP

Standby Power Supply Current

Operating Power Supply Current

-

µA

-

mA/MHz

FREQ = Max, V = V

IN

or GND,

CC

Outputs Open

NOTES:

1. lBHH should be measured after raising V to V

and then lowering to 3.0V on the following pins 2-16, 26-32, 34-39.

IN CC

2. IBHL should be measured after lowering V to GND and then raising to 0.8V on the following pins: 2-16, 35-39.

IN

3. lCCSB tested during clock high time after HALT instruction executed. V = V

IN

or GND, V

= 5.5V, Outputs unloaded.

CC

4. MN/MX is a strap option and should be held to V

CC

or GND.

5. IO should be measured by putting the pin in a high impedance state and then driving V

to GND on the following pins: 26-29 and 32.

OUT

o

Capacitance T = 25 C

A

SYMBOL

CIN

PARAMETER

Input Capacitance

Output Capacitance

I/O Capacitance

TYPICAL

UNITS

pF

TEST CONDITIONS

25

FREQ = 1MHz. All measurements are referenced to device GND

COUT

CI/O

pF

3-15

80C88

o

AC Electrical Speciﬁcations

V

= 5.0V ±10%; T = 0 C to +70 C (C80C88, C80C88-2)

CC

A

o

= 5.0V ±100%; T = -40 C to +85 C (I80C88, I80C88-2)

A

o

= 5.0V ±100%; T = -55 C to +125 C (M80C88)

A

o

= 5.0V ±5%;

T = -55 C to +125 C (M80C88-2)

A

MINIMUM COMPLEXITY SYSTEM

80C88

MIN

80C88-2

TEST

CONDITIONS

SYMBOL

PARAMETER

MAX

MIN

MAX

UNITS

TIMING REQUIREMENTS

(1)

(2)

(3)

(4)

(5)

(6)

(7)

(8)

TCLCL

TCLCH

TCHCL

CLK Cycle Period

200

118

69

-

125

68

44

-

ns

CLK Low Time

CLK High Time

-

TCH1CH2 CLK Rise Time

TCL2CL1 CLK FaIl Time

10

-

10

-

From 1.0V to 3.5V

From 3.5V to 1.0V

-

TDVCL

Data In Setup Time

30

10

35

20

10

35

TCLDX1 Data In Hold Time

-

TR1VCL

TCLR1X

RDY Setup Time into 82C84A

(Notes 6, 7)

-

(9)

RDY Hold Time into 82C84A

(Notes 6, 7)

0

-

0

-

ns

(10)

(11)

(12)

(13)

(14)

TRYHCH READY Setup Time into 80C88

TCHRYX READY Hold Time into 80C88

TRYLCL READY Inactive to CLK (Note 8)

118

30

-8

-

68

20

-8

-

ns

THVCH

TINVCH

HOLD Setup Time

35

30

20

15

lNTR, NMI, TEST Setup Time

(Note 7)

(15)

(16)

TILIH

TIHIL

Input Rise Time (Except CLK)

Input FaIl Time (Except CLK)

-

15

-

15

ns

From 0.8V to 2.0V

From 2.0V to 0.8V

TIMING RESPONSES

(17)

(18)

(19)

(20)

(21)

(22)

(23)

(24)

TCLAV

TCLAX

TCLAZ

TCHSZ

TCHSV

TLHLL

TCLLH

TCHLL

Address Valid Delay

Address Hold Time

Address Float Delay

Status Float Delay

Status Active Delay

ALE Width

10

110

-

10

60

-

ns

CL = 100pF

10

TCLAX

80

110

-

TCLAX

50

60

-

10

TCLCH-20

TCLCH-10

ALE Active Delay

ALE Inactive Delay

-

80

85

-

50

55

3-16

80C88

o

AC Electrical Speciﬁcations

V

= 5.0V ±10%; T = 0 C to +70 C (C80C88, C80C88-2)

CC

A

o

= 5.0V ±100%; T = -40 C to +85 C (I80C88, I80C88-2)

A

o

= 5.0V ±100%; T = -55 C to +125 C (M80C88)

A

o

= 5.0V ±5%;

T = -55 C to +125 C (M80C88-2) (Continued)

A

MINIMUM COMPLEXITY SYSTEM

80C88

MIN

80C88-2

MIN

TEST

CONDITIONS

SYMBOL

TLLAX

PARAMETER

Address Hold Time to ALE Inactive

Data Valid Delay

MAX

-

MAX

-

UNITS

ns

(25)

(26)

(27)

(28)

(29)

(30)

(31)

(32)

(33)

(34)

(35)

(36)

(37)

(38)

(39)

(40)

(41)

NOTES:

TCHCL-10

CL = 100pF

From 0.8V to 2.0V

From 2.0V to 0.8V

TCLDV

TCLDX2

TWHDX

TCVCTV

10

110

-

10

60

-

ns

Data Hold Time

10

ns

Data Hold Time After WR

Control Active Delay 1

TCLCL-30

-

TCLCL-30

-

ns

10

110

-

10

70

60

70

-

ns

TCHCTV Control Active Delay 2

10

ns

TCVCTX

TAZRL

TCLRL

TCLRH

TRHAV

TCLHAV

TRLRH

TWLWH

TAVAL

TOLOH

TOHOL

Control Inactive Delay

Address Float to READ Active

RD Active Delay

10

ns

0

ns

10

165

150

-

10

100

80

-

ns

RD Inactive Delay

10

ns

RD Inactive to Next Address Active

HLDA Valid Delay

TCLCL-45

TCLCL-40

ns

10

160

-

10

100

-

ns

RD Width

2TCLCL-75

2TCLCL-50

ns

WR Width

2TCLCL-60

-

2TCLCL-40

-

ns

Address Valid to ALE Low

Output Rise Time

TCLCH-60

-

TCLCH-40

-

ns

-

15

-

15

ns

Output Fall Time

ns

6. Signal at 82C84A shown for reference only.

7. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.

8. Applies only to T2 state (8ns into T3).

3-17

80C88

Waveforms

T1

T2

T3

(5)

TCL2CL1

T4

TW

(2)

(1)

TCLCL

TCH1CH2

(4)

CLK (82C84A OUTPUT)

(3)

TCHCTV

(30)

TCLCH

TCHCL

(30) TCHCTV

IO/M, SSO

(17)

TCLAV

A15-A8

A15-A8 (FLOAT DURING INTA)

(17)

TCLAV

(17)

TCLAV

(26) TCLDV

(18) TCLAX

S6-S3

A19-A16

TLHLL

A19/S6-A16/S3

(23) TCLLH

(22)

TLLAX

(25)

ALE

(24)

TR1VCL (8)

TCLR1X (9)

TCHLL

V

IH

RDY (82C84A INPUT)

SEE NOTE 9, 10

TAVAL

(39)

V

IL

(12)

TRYLCL

(11)

TCHRYX

READY (80C88 INPUT)

(10)

TRYHCH

(7)

TCLDX1

(19)

TCLAZ

(16)

TDVCL

AD7-AD0

DATA IN

(34) TCLRH

AD7-AD0

RD

(35)

TRHAV

(32) TAZRL

(30)

TCHCTV

(30)

TCHCTV

READ CYCLE

(WR, INTA = V

TRLRH

(37)

TCLRL

(33)

)

OH

DT/R

DEN

(29) TCVCTV

TCVCTX

(31)

FIGURE 22. BUS TIMING - MINIMUM MODE SYSTEM

NOTES:

9. RDY is sampled near the end of T2, T3, TW to determine if TW machine states are to be inserted.

10. Signals at 82C84A are shown for reference only.

3-18

80C88

Waveforms (Continued)

T1

T2

T3

(5)

TCL2CL1

TW

T4

(4)

TCH1CH2

TW

CLK (82C84A OUTPUT)

AD7-AD0

(26)

(27)

TCLDX2

(17)

TCLDV

TCLAX

(18)

TCLAV

AD7-AD0

DATA OUT

TWHDX

(28)

(29)

TCVCTV

(31) TCVCTX

DEN

WR

WRITE CYCLE

(29) TCVCTV

(38)

TWLWH

TCVCTX

TDVCL

(31)

(6)

(19)

TCLAZ

TCLDX1 (7)

POINTER

AD7-AD0

TCHCTV (30)

TCHCTV

(30)

DT/R

INTA

INTA CYCLE

(NOTE 11)

(29) TCVCTV

RD, WR = V

OH

TCVCTX

(31)

(29) TCVCTV

DEN

SOFTWARE

HALT -

INVALID ADDRESS

SOFTWARE HALT

AD7-AD0

ALE

DEN, RD,

TCLAV

(17)

WR, INTA = V

OH

TCHLL

(24)

TCLLH

(23)

TCHCTV

(30)

TCVCTX

(31)

IO/M

DT/R

SSO

FIGURE 23. BUS TIMING - MINIMUM MODE SYSTEM (Continued)

NOTES:

11. Two INTA cycles run back-to-back. The 80C88 local ADDR/DATA bus is floating during both INTA cycles. Control signals are shown for

the second INTA cycle.

12. Signals at 82C84A are shown for reference only.

3-19

80C88

o

AC Electrical Speciﬁcations

V

= 5.0V ±10%; T = 0 C to +70 C (C80C88, C80C88-2)

CC

A

o

= 5.0V ±10%; T = -40 C to +85 C (I80C88, I80C88-2)

A

o

= 5.0V ±10%; T = -55 C to +125 C (M80C88)

A

o

= 5.0V ±5%; T = -55 C to +125 C (M80C88-2)

A

MAX MODE SYSTEM (USING 82C88 BUS CONTROLLER)

80C88

MAX

80C88-2

SYMBOL

PARAMETER

MIN

MAX

UNITS TEST CONDITIONS

TIMING REQUIREMENTS

(1)

(2)

(3)

(4)

(5)

(6)

(7)

(8)

TCLCL

TCLCH

TCHCL

CLK Cycle Period

200

118

69

-

125

68

44

-

ns

CLK Low Time

CLK High Time

-

TCH1CH2 CLK Rise Time

TCL2CL1 CLK Fall Time

10

-

10

-

ns

From 1.0V to 3.5V

From 3.5V to 1.0V

-

TDVCL

TCLDX1

TR1VCL

Data in Setup Time

Data In Hold Time

30

10

35

20

10

35

-

RDY Setup Time into 82C84

(Notes 13, 14)

-

(9)

TCLR1X

RDY Hold Time into 82C84

(Notes 13, 14)

0

-

0

-

ns

(10)

(11)

(12)

(13)

TRYHCH READY Setup Time into 80C88

TCHRYX READY Hold Time into 80C88

118

30

-8

-

68

20

-8

-

ns

TRYLCL

TlNVCH

READY Inactive to CLK (Note 15)

Setup Time for Recognition (lNTR,

NMl, TEST) (Note 14)

30

15

(14)

(15)

TGVCH

TCHGX

RQ/GT Setup Time

30

40

-

15

30

-

ns

RQ Hold Time into 80C88 (Note 16)

TCHCL+

10

TCHCL+

10

(16)

(17)

TILlH

TIHIL

Input Rise Time (Except CLK)

Input Fall Time (Except CLK)

-

15

-

15

ns

From 0.8V to 2.0V

From 2.0V to 0.8V

TIMING RESPONSES

(18)

(19)

(20)

TCLML

TCLMH

Command Active Delay (Note 13)

Command Inactive (Note 13)

5

-

35

5

-

35

65

ns

TRYHSH READY Active to Status Passive

(Notes 15, 17)

110

(21)

(22)

(23)

(24)

(25)

(26)

(27)

TCHSV

TCLSH

TCLAV

TCLAX

TCLAZ

TCHSZ

TSVLH

Status Active Delay

10

110

130

110

-

10

60

70

60

-

ns

Status Inactive Delay (Note 17)

Address Valid Delay

10

CL = 100pF

for all 80C88 outputs

in addition to internal

loads.

Address Hold Time

10

Address Float Delay

TCLAX

80

20

30

20

25

18

TCLAX

50

20

30

20

25

18

Status Float Delay

-

Status Valid to ALE High (Note 13)

(28) TSVMCH Status Valid to MCE High (Note 13)

-

(29)

(30)

(31)

TCLLH

TCLMCH CLK Low to MCE High (Note 13)

TCHLL ALE Inactive Delay (Note 13)

CLK Low to ALE Valid (Note 13)

-

4

3-20

80C88

o

AC Electrical Speciﬁcations

V

= 5.0V ±10%; T = 0 C to +70 C (C80C88, C80C88-2)

CC

A

o

= 5.0V ±10%; T = -40 C to +85 C (I80C88, I80C88-2)

A

o

= 5.0V ±10%; T = -55 C to +125 C (M80C88)

A

o

= 5.0V ±5%; T = -55 C to +125 C (M80C88-2) (Continued)

A

MAX MODE SYSTEM (USING 82C88 BUS CONTROLLER)

80C88

MAX

80C88-2

SYMBOL

PARAMETER

MIN

-

MIN

MAX

15

60

-

UNITS TEST CONDITIONS

(32)

(33)

(34)

(35)

(36)

(37)

(38)

(39)

(40)

TCLMCL MCE Inactive Delay (Note 13)

15

110

-

ns

TCLDV

TCLDX2

TCVNV

TCVNX

TAZRL

TCLRL

TCLRH

TRHAV

Data Valid Delay

10

5

10

5

Data Hold Time

Control Active Delay (Note 13)

Control Inactive Delay (Note 13)

Address Float to Read Active

RD Active Delay

45

-

45

-

10

0

10

0

10

165

150

-

10

100

80

-

CL = 100pF

ns

RD Inactive Delay

for all 80C88 outputs

in addition to internal

loads.

RD Inactive to Next Address Active

TCLCL

-45

TCLCL

-40

ns

(41)

(42)

TCHDTL

Direction Control Active Delay

(Note 13)

-

50

30

-

50

30

TCHDTH Direction Control Inactive Delay

(Note 1)

-

(43)

(44)

(45)

TCLGL

TCLGH

TRLRH

GT Active Delay

GT Inactive Delay

RD Width

0

85

-

0

50

-

ns

2TCLC

L -75

2TCLC

L -50

(46)

TOLOH

TOHOL

Output Rise Time

Output Fall Time

-

15

-

15

ns

From 0.8V to 2.0V

From 2.0V to 0.8V

(47)

NOTES:

13. Signal at 82C84A or 82C88 shown for reference only.

14. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.

15. Applies only to T2 state (8ns into T3).

16. The 80C88 actively pulls the RQ/GT pin to a logic one on the following clock low time.

17. Status lines return to their inactive (logic one) state after CLK goes low and READY goes high.

3-21

80C88

Waveforms

T1

T2

T3

T4

(4)

TCH1CH2

(1)

TCLCL

(5)

TCL2CL1 TW

CLK

(23)

TCLAV

TCLCH

(2)

TCHCL (3)

QS0, QS1

TCLSH

(21) TCHSV

(22)

S2, S1, S0 (EXCEPT HALT)

(SEE NOTE 20)

A15-A8

(33)

(24)

TCLDV

(23) TCLAV

(23)

TCLAV

TCLAX

A19/S6-A16/S3

TSVLH

A19-A16

S6-S3

(31)

TCHLL

(27)

TCLLH

(29)

ALE (82C88 OUTPUT)

NOTES 18, 19

TR1VCL

(8)

RDY (82C84 INPUT)

TCLR1X

(12) TRYLCL

(9)

(11)

TCHRYX

READY 80C86 INPUT)

TRYHSH

(20)

(24)

TCLAX

(10)

TRYHCH

(7)

TCLDX1

(25)

TCLAZ

(6)

TDVCL

READ CYCLE

TCLAV

(23)

AD7-AD0

DATA IN

(39) TCLRH

AD7-AD0

RD

(37) TAZRL

TRHAV

(40)

(42)

TCHDTH

(41) TCHDTL

TRLRH

(45)

TCLRL

(38)

DT/R

TCLML

(18)

TCLMH

(19)

82C88

OUTPUTS

MRDC OR IORC

SEE NOTES 19, 21

(35) TCVNV

DEN

TCVNX

(36)

FIGURE 24. BUS TIMING - MAXIMUM MODE (USING 82C88)

NOTES:

18. RDY is sampled near the end of T2, T3, TW to determine if TW machine states are to be inserted.

19. Signals at 82C84A or 82C88 are shown for reference only.

20. Status inactive in state just prior to T4.

21. The issuance of the 82C88 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA, and DEN) lags the active

high 82C88 CEN.

3-22

80C88

Waveforms (Continued)

T1

T2

T3

T4

TW

CLK

TCHSV (21)

(SEE NOTE 24)

TCLDX2

S2, S1, S0 (EXCEPT HALT)

(22)

TCLDV

TCLAX

(33)

(24)

(34)

TCLAV

WRITE CYCLE

AD7-AD0

TCLSH

(23)

DATA

TCVNV

(35)

TCVNX (36)

DEN

TCLMH

(19)

(18) TCLML

82C88

OUTPUTS

SEE NOTES 22, 23

AMWC OR AIOWC

TCLMH (19)

(18)TCLML

MWTC OR IOWC

INTA CYCLE

A15-A8

(SEE NOTES 25, 26)

RESERVED FOR

CASCADE ADDR

(25) TCLAZ

AD7-AD0

(6)

TDVCL

POINTER

TCLDX1 (7)

(32)

TCLMCL

(28) TSVMCH

MCE/PDEN

(41)

TCHDTL

TCHDTH

(30) TCLMCH

DT/R

(42)

82C88 OUTPUTS

SEE NOTES 22, 23, 25

(18) TCLML

INTA

DEN

(19) TCLMH

TCVNV

(35)

TCVNX

(36)

SOFTWARE

HALT - RD, MRDC, IORC, MWTC, AMWC, IOWC, AIOWC, INTA, S0, S1 = VOH

AD7-AD0

INVALID ADDRESS

A15-A8

TCLAV

(23)

S2, S1, S0

TCLSH

(22)

TCHSV

(21)

FIGURE 25. BUS TIMING - MAXIMUM MODE SYSTEM (USING 82C88) (Continued)

NOTES:

22. Signals at 82C84A or 82C86 are shown for reference only.

23. The issuance of the 82C88 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA and DEN) lags the active

high 82C88 CEN.

24. Status inactive in state just prior to T4.

25. Cascade address is valid between first and second INTA cycles.

26. Two INTA cycles run back-to-back. The 80C88 local ADDR/DATA bus is floating during both INTA cycles. Control for pointer address is

shown for second INTA cycle.

3-23

80C88

Waveforms (Continued)

> 0-CLK

CYCLES

ANY

CLK

CYCLE

CLK

TCLGH

(44)

TCLGH (44)

TGVCH (14)

TCHGX (15)

TCLGL

(43)

(1)

TCLCL

PULSE 2

80C88 GT

RQ/GT

PULSE 3

PULSE 1

COPROCESSOR

RQ

COPROCESSOR

RELEASE

TCLAZ (25)

TCHSZ (26)

PREVIOUS GRANT

AD7-AD0

80C88

COPROCESSOR

TCHSV (21)

(SEE NOTE)

RD, LOCK

A19/S6-A16/S3

S2, S1, S0

FIGURE 26. REQUEST/GRANT SEQUENCE TIMING (MAXIMUM MODE ONLY)

NOTE: The coprocessor may not drive the busses outside the region shown without risking contention.

≥ 1CLK

CYCLE

1 OR 2

CYCLES

CLK

HOLD

HLDA

THVCH (13)

(SEE NOTE)

TCLHAV (36)

80C88

TCLAZ (19)

A15-A8

80C88

COPROCESSOR

TCHSZ (20)

AD7-AD0

TCHSV (21)

A19/S6-A16/S3

RD, WR, I/O/M, DT/R, DEN, SSO

FIGURE 27. HOLD/HOLD ACKNOWLEDGE TIMING (MINIMUM MODE ONLY)

NOTE: Setup requirements for asynchronous signals only to guarantee recognition at next CLK.

CLK

ANY CLK CYCLE

(13)

CLK

TINVCH (SEE NOTE)

NMI

INTR

TEST

TCLAV

(23)

TCLAV

(23)

SIGNAL

LOCK

FIGURE 28. ASYNCHRONOUS SIGNAL RECOGNITION

NOTE: Setup requirements for asynchronous signals only to guar-

antee recognition at next CLK.

FIGURE 29. BUS LOCK SIGNAL TIMING (MAXIMUM MODE

ONLY)

3-24

80C88

Waveforms (Continued)

≥ 50µs

V

CC

CLK

(7) TCLDX1

(6) TDVCL

RESET

≥ 4 CLK CYCLES

FIGURE 30. RESET TIMING

AC Test Circuit

AC Testing Input, Output Waveform

INPUT

OUTPUT

OUTPUT FROM

DEVICE UNDER TEST

TEST

POINT

V

+ 20% V

IH

V

CL (NOTE)

OH

1.5V

V

OL

V

- 50% V

IL

AC Testing: All input signals (other than CLK) must switch between

NOTE: Includes stay and jig capacitance.

V

-50% V and V

+20% V . CLK must

ILMAX

IL

IHMIN IH

switch between 0.4V and V

-0.4V. Input rise and fall

CC

times are driven at 1ns/V.

Burn-In Circuits

MD80C88 (CERDIP)

C

GND

1

2

3

4

5

6

7

8

9

GND

A14

A13

A12

A11

A10

A9

V

40

CC

GND

VCL

V

CC

RIO

A15 39

A16 38

A17 37

A18 36

A19 35

BHE 34

VCL

RO

VCC/2

RIO

RO

GND

VCL

VCC/2

RO

VCC/2

RO

VCC/2

RO

RIO

VCC/2

GND

VCL

33

32

31

30

29

28

27

26

25

24

23

22

21

A8

MX

RD

GND

RO

VIL

RI

AD7

10 AD6

11 AD5

12 AD4

13 AD3

14 AD2

15 AD1

16 AD0

17 NMI

18 INTR

19 CLK

20 GND

RQ0

RQ1

LOCK

S2

VCL

RO

VCL

RO

VCC/2

RO

VCL

VCC/2

RO

OPEN

S1

VCC/2

RO

S0

VCC/2

OPEN

GND

F0

RO

QS0

VCC/2

RO

QS2

VCC/2

GND

TEST

READY

RESET

RI

RC

VCL

RI

NODE

A

GND

FROM

PROGRAM

CARD

3-25

80C88

Burn-In Circuits (Continued)

MR80C88 (CLCC)

C

V

CC

CL

44

43 42 41 40

6

5

4

3

2

1

RIO

7

39

38

37

36

35

34

33

32

31

30

29

RO

8

RIO

9

10

11

12

13

14

15

16

17

RO

RI

RIO

RI

RO

18 19 20 21 22 23 24 25 26 27 28

VCC/2

GND

F0

A

(FROM PROGRAM CARD)

NOTES:

COMPONENTS:

1. RI = 10kΩ ±5%, 1/4W

2. RO = 1.2kΩ ±5%, 1/4W

3. RIO = 2.7kΩ ±5%, 1/4W

4. RC = 1kΩ ±5%, 1/4W

5. C = 0.01µF (Minimum)

1. V

= 5.5V ±0.5V, GND = 0V.

CC

2. Input voltage limits (except clock):

V

(Maximum) = 0.4V

(Minimum) = 2.6V, V (Clock) = V

IH

IL

- 0.4V) minimum.

CC

IH

3. VCC/2 is external supply set to 2.7V ±10%.

4. V is generated on program card (V - 0.65V).

CL CC

5. Pins 13 - 16 input sequenced instructions from internal hold

devices, (DIP Only).

6. F0 = 100kHz ±10%.

7. Node

= a 40µs pulse every 2.56ms.

A

3-26

80C88

Die Characteristics

DIE DIMENSIONS:

249.2 x 290.9 x 19 ±1mils

GLASSIVATION:

Type: SiO

2

Thickness: 8kÅ ±1kÅ

METALLIZATION:

Type: Silicon - Aluminum

Thickness: 11kÅ ±2kÅ

WORST CASE CURRENT DENSITY:

1.5 x 10 A/cm

5

2

Metallization Mask Layout

80C88

A11

A12

A13 A14

GND

V

A15 A16/S3 A17/S4 A18/S5

CC

A19/S6

A10

A9

SSO

MN/MX

A8

RD

AD7

HOLD

AD6

AD5

HLDA

AD4

AD3

WR

AD2

AD1

IO/M

DT/R

AD0

NMI INTR CLK

GND

RESET READY TEST INTA

ALE

DEN

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3-27

80C88

Instruction Set Summary

INSTRUCTION CODE

MNEMONIC AND DESCRIPTION

7 6 5 4 3 2 1 0

DATA TRANSFER

MOV = MOVE:

Register/Memory to/from Register

Immediate to Register/Memory

Immediate to Register

Memory to Accumulator

Accumulator to Memory

Register/Memory to Segment Register ††

Segment Register to Register/Memory

PUSH = Push:

1 0 0 0 1 0 d w

1 1 0 0 0 1 1 w

1 0 1 1 w reg

mod reg r/m

mod 0 0 0 r/m

data

data if w 1

addr-high

1 0 1 0 0 0 0 w

1 0 1 0 0 0 1 w

1 0 0 0 1 1 1 0

1 0 0 0 1 1 0 0

addr-low

mod 0 reg r/m

Register/Memory

1 1 1 1 1 1 1 1

0 1 0 1 0 reg

0 0 0 reg 1 1 0

mod 1 1 0 r/m

Register

Segment Register

POP = Pop:

Register/Memory

1 0 0 0 1 1 1 1

0 1 0 1 1 reg

0 0 0 reg 1 1 1

mod 0 0 0 r/m

Register

Segment Register

XCHG = Exchange:

Register/Memory with Register

Register with Accumulator

IN = Input from:

1 0 0 0 0 1 1 w

1 0 0 1 0 reg

mod reg r/m

port

Fixed Port

1 1 1 0 0 1 0 w

1 1 1 0 1 1 0 w

Variable Port

OUT = Output to:

Fixed Port

1 1 1 0 0 1 1 w

1 1 1 0 1 1 1 w

1 1 0 1 0 1 1 1

1 0 0 0 1 1 0 1

1 1 0 0 0 1 0 1

1 1 0 0 0 1 0 0

1 0 0 1 1 1 1 1

1 0 0 1 1 1 1 0

1 0 0 1 1 1 0 0

1 0 0 1 1 1 0 1

port

Variable Port

XLAT = Translate Byte to AL

LEA = Load EA to Register2

LDS = Load Pointer to DS

LES = Load Pointer to ES

LAHF = Load AH with Flags

SAHF = Store AH into Flags

PUSHF = Push Flags

POPF = Pop Flags

mod reg r/m

ARITHMETIC

ADD = Add:

Register/Memory with Register to Either

Immediate to Register/Memory

Immediate to Accumulator

0 0 0 0 0 0 d w

1 0 0 0 0 0 s w

0 0 0 0 0 1 0 w

mod reg r/m

mod 0 0 0 r/m

data

data if s:w = 01

data if w = 1

ADC = Add with Carry:

Register/Memory with Register to Either

0 0 0 1 0 0 d w

mod reg r/m

3-28

80C88

Instruction Set Summary (Continued)

INSTRUCTION CODE

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

MNEMONIC AND DESCRIPTION

Immediate to Register/Memory

Immediate to Accumulator

INC = Increment:

7 6 5 4 3 2 1 0

1 0 0 0 0 0 s w

mod 0 1 0 r/m

data

data if s:w = 01

0 0 0 1 0 1 0 w

data if w = 1

Register/Memory

1 1 1 1 1 1 1 w

0 1 0 0 0 reg

mod 0 0 0 r/m

Register

AAA = ASCll Adjust for Add

DAA = Decimal Adjust for Add

SUB = Subtract:

0 0 1 1 0 1 1 1

0 0 1 0 0 1 1 1

Register/Memory and Register to Either

Immediate from Register/Memory

Immediate from Accumulator

SBB = Subtract with Borrow

Register/Memory and Register to Either

Immediate from Register/Memory

Immediate from Accumulator

DEC = Decrement:

0 0 1 0 1 0 d w

1 0 0 0 0 0 s w

0 0 1 0 1 1 0 w

mod reg r/m

mod 1 0 1 r/m

data

data if s:w = 01

data if w = 1

0 0 0 1 1 0 d w

1 0 0 0 0 0 s w

0 0 0 1 1 1 0 w

mod reg r/m

mod 0 1 1 r/m

data

data if w = 1

Register/Memory

1 1 1 1 1 1 1 w

0 1 0 0 1 reg

mod 0 0 1 r/m

mod 0 1 1 r/m

Register

NEG = Change Sign

1 1 1 1 0 1 1 w

CMP = Compare:

Register/Memory and Register

Immediate with Register/Memory

Immediate with Accumulator

AAS = ASCll Adjust for Subtract

DAS = Decimal Adjust for Subtract

MUL = Multiply (Unsigned)

IMUL = Integer Multiply (Signed)

AAM = ASCll Adjust for Multiply

DlV = Divide (Unsigned)

0 0 1 1 1 0 d w

1 0 0 0 0 0 s w

0 0 1 1 1 1 0 w

0 0 1 1 1 1 1 1

0 0 1 0 1 1 1 1

1 1 1 1 0 1 1 w

1 1 0 1 0 1 0 0

1 1 1 1 0 1 1 w

1 1 0 1 0 1 0 1

1 0 0 1 1 0 0 0

1 0 0 1 1 0 0 1

mod reg r/m

mod 1 1 1 r/m

data

data if s:w = 01

data if w = 1

mod 1 0 0 r/m

mod 1 0 1 r/m

0 0 0 0 1 0 1 0

mod 1 1 0 r/m

mod 1 1 1 r/m

0 0 0 0 1 0 1 0

IDlV = Integer Divide (Signed)

AAD = ASClI Adjust for Divide

CBW = Convert Byte to Word

CWD = Convert Word to Double Word

LOGIC

NOT = Invert

1 1 1 1 0 1 1 w

1 1 0 1 0 0 v w

mod 0 1 0 r/m

mod 1 0 0 r/m

mod 1 0 1 r/m

mod 1 1 1 r/m

mod 0 0 0 r/m

mod 0 0 1 r/m

mod 0 1 0 r/m

SHL/SAL = Shift Logical/Arithmetic Left

SHR = Shift Logical Right

SAR = Shift Arithmetic Right

ROL = Rotate Left

ROR = Rotate Right

RCL = Rotate Through Carry Flag Left

3-29

80C88

Instruction Set Summary (Continued)

INSTRUCTION CODE

MNEMONIC AND DESCRIPTION

RCR = Rotate Through Carry Right

AND = And:

7 6 5 4 3 2 1 0

1 1 0 1 0 0 v w

mod 0 1 1 r/m

Reg./Memory and Register to Either

Immediate to Register/Memory

Immediate to Accumulator

TEST = And Function to Flags, No Result:

Register/Memory and Register

Immediate Data and Register/Memory

Immediate Data and Accumulator

OR = Or:

0 0 1 0 0 0 0 d w

1 0 0 0 0 0 0 w

0 0 1 0 0 1 0 w

mod reg r/m

mod 1 0 0 r/m

data

data if w = 1

1 0 0 0 0 1 0 w

1 1 1 1 0 1 1 w

1 0 1 0 1 0 0 w

mod reg r/m

mod 0 0 0 r/m

data

data if w = 1

Register/Memory and Register to Either

Immediate to Register/Memory

Immediate to Accumulator

XOR = Exclusive or:

0 0 0 0 1 0 d w

1 0 0 0 0 0 0 w

0 0 0 0 1 1 0 w

mod reg r/m

mod 1 0 1 r/m

data

data if w = 1

Register/Memory and Register to Either

Immediate to Register/Memory

Immediate to Accumulator

STRING MANIPULATION

REP = Repeat

0 0 1 1 0 0 d w

1 0 0 0 0 0 0 w

0 0 1 1 0 1 0 w

mod reg r/m

mod 1 1 0 r/m

data

data if w = 1

1 1 1 1 0 0 1 z

1 0 1 0 0 1 0 w

1 0 1 0 0 1 1 w

1 0 1 0 1 1 1 w

1 0 1 0 1 1 0 w

1 0 1 0 1 0 1 w

MOVS = Move Byte/Word

CMPS = Compare Byte/Word

SCAS = Scan Byte/Word

LODS = Load Byte/Word to AL/AX

STOS = Stor Byte/Word from AL/A

CONTROL TRANSFER

CALL = Call:

Direct Within Segment

1 1 1 0 1 0 0 0

1 1 1 1 1 1 1 1

1 0 0 1 1 0 1 0

disp-low

mod 0 1 0 r/m

offset-low

disp-high

Indirect Within Segment

Direct Intersegment

offset-high

seg-high

seg-low

Indirect Intersegment

1 1 1 1 1 1 1 1

mod 0 1 1 r/m

JMP = Unconditional Jump:

Direct Within Segment

1 1 1 0 1 0 0 1

1 1 1 0 1 0 1 1

1 1 1 1 1 1 1 1

1 1 1 0 1 0 1 0

disp-low

disp

disp-high

Direct Within Segment-Short

Indirect Within Segment

Direct Intersegment

mod 1 0 0 r/m

offset-low

seg-low

offset-high

seg-high

Indirect Intersegment

1 1 1 1 1 1 1 1

mod 1 0 1 r/m

RET = Return from CALL:

Within Segment

1 1 0 0 0 0 1 1

1 1 0 0 0 0 1 0

Within Seg Adding lmmed to SP

data-low

data-high

3-30

80C88

Instruction Set Summary (Continued)

INSTRUCTION CODE

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

MNEMONIC AND DESCRIPTION

Intersegment

7 6 5 4 3 2 1 0

1 1 0 0 1 0 1 1

Intersegment Adding Immediate to SP

JE/JZ = Jump on Equal/Zero

1 1 0 0 1 0 1 0

0 1 1 1 0 1 0 0

0 1 1 1 1 1 0 0

0 1 1 1 1 1 1 0

0 1 1 1 0 0 1 0

0 1 1 1 0 1 1 0

0 1 1 1 1 0 1 0

0 1 1 1 0 0 0 0

0 1 1 1 1 0 0 0

0 1 1 1 0 1 0 1

0 1 1 1 1 1 0 1

0 1 1 1 1 1 1 1

0 1 1 1 0 0 1 1

0 1 1 1 0 1 1 1

0 1 1 1 1 0 1 1

0 1 1 1 0 0 0 1

0 1 1 1 1 0 0 1

1 1 1 0 0 0 1 0

1 1 1 0 0 0 0 1

1 1 1 0 0 0 0 0

1 1 1 0 0 0 1 1

data-low

disp

data-high

JL/JNGE = Jump on Less/Not Greater or Equal

JLE/JNG = Jump on Less or Equal/ Not Greater

JB/JNAE = Jump on Below/Not Above or Equal

JBE/JNA = Jump on Below or Equal/Not Above

JP/JPE = Jump on Parity/Parity Even

JO = Jump on Overflow

JS = Jump on Sign

JNE/JNZ = Jump on Not Equal/Not Zero

JNL/JGE = Jump on Not Less/Greater or Equal

JNLE/JG = Jump on Not Less or Equal/Greater

JNB/JAE = Jump on Not Below/Above or Equal

JNBE/JA = Jump on Not Below or Equal/Above

JNP/JPO = Jump on Not Par/Par Odd

JNO = Jump on Not Overﬂow

JNS = Jump on Not Sign

LOOP = Loop CX Times

LOOPZ/LOOPE = Loop While Zero/Equal

LOOPNZ/LOOPNE = Loop While Not Zero/Equal

JCXZ = Jump on CX Zero

INT = Interrupt

Type Specified

1 1 0 0 1 1 0 1

1 1 0 0 1 1 0 0

1 1 0 0 1 1 1 0

1 1 0 0 1 1 1 1

type

Type 3

INTO = Interrupt on Overﬂow

IRET = Interrupt Return

PROCESSOR CONTROL

CLC = Clear Carry

1 1 1 1 1 0 0 0

1 1 1 1 0 1 0 1

1 1 1 1 1 0 0 1

1 1 1 1 1 1 0 0

1 1 1 1 1 1 0 1

1 1 1 1 1 0 1 0

1 1 1 1 1 0 1 1

1 1 1 1 0 1 0 0

1 0 0 1 1 0 1 1

1 1 0 1 1 x x x

1 1 1 1 0 0 0 0

CMC = Complement Carry

STC = Set Carry

CLD = Clear Direction

STD = Set Direction

CLl = Clear Interrupt

ST = Set Interrupt

HLT = Halt

WAIT = Wait

ESC = Escape (to External Device)

LOCK = Bus Lock Prefix

mod x x x r/m

3-31

80C88

Instruction Set Summary (Continued)

INSTRUCTION CODE

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

MNEMONIC AND DESCRIPTION

7 6 5 4 3 2 1 0

NOTES:

AL = 8-bit accumulator

AX = 16-bit accumulator

if s:w = 01 then 16-bits of immediate data form the operand.

if s:w = 11 then an immediate data byte is sign extended

to form the 16-bit operand.

CX = Count register

if v = 0 then “count” = 1; if v = 1 then “count” in (C )

L

DS= Data segment

x = don't care

ES = Extra segment

z is used for string primitives for comparison with ZF FLAG.

Above/below refers to unsigned value.

Greater = more positive;

Less = less positive (more negative) signed values

if d = 1 then “to” reg; if d = 0 then “from” reg

if w = 1 then word instruction; if w = 0 then byte

instruction

SEGMENT OVERRIDE PREFIX

001 reg 11 0

REG is assigned according to the following table:

16-BIT (w = 1)

000 AX

001 CX

010 DX

011 BX

100 SP

101 BP

110 SI

8-BIT (w = 0)

000 AL

SEGMENT

00 ES

if mod = 11 then r/m is treated as a REG ﬁeld

if mod = 00 then DISP = 0†, disp-low and disp-high

are absent

if mod = 01 then DISP = disp-low sign-extended

16-bits, disp-high is absent

if mod = 10 then DISP = disp-high:disp-low

if r/m = 000 then EA = (BX) + (SI) + DISP

if r/m = 001 then EA = (BX) + (DI) + DISP

if r/m = 010 then EA = (BP) + (SI) + DISP

if r/m = 011 then EA = (BP) + (DI) + DISP

if r/m = 100 then EA = (SI) + DISP

if r/m = 101 then EA = (DI) + DISP

if r/m = 110 then EA = (BP) + DISP †

if r/m = 111 then EA = (BX) + DISP

DISP follows 2nd byte of instruction (before data

if required)

001 CL

01 CS

010 DL

10 SS

011 BL

11 DS

100 AH

101 CH

110 DH

111 BH

111 DI

Instructions which reference the flag register file as a 16-bit

object use the symbol FLAGS to represent the file:

FLAGS =

†

except if mod = 00 and r/m = 110 then

EA = disp-high: disp-low.

X:X:X:X:(OF):(DF):(IF):(TF):(SF):(ZF):X:(AF):X:(PF):X:(CF)

Mnemonics Intel, 1978

†† MOV CS, REG/MEMORY not allowed.

3-32


型号：	5962-8601601XA
厂家：	Intersil
描述：	CMOS 8/16-Bit Microprocessor CMOS 8位/ 16位微处理器外围集成电路微处理器时钟
文件：	总32页 (文件大小：248K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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