TS87L51FB_技术文档

8XL51FA/FB/FC

LOW VOLTAGE

CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLERS

Commercial/Express

87L51FA/83L51FA/80L51FA/87L51FB/83L51FB/87L51FC/83L51FC

Y

High Performance CHMOS OTP ROM/

ROM/CPU

Boolean Processor

Y

32 Programmable I/O Lines

7 Interrupt Sources

Y

Low Voltage Operation

20 MHz Commercial/16 MHz Express

Operation

Four Level Interrupt Priority

Programmable Serial Channel with:

Ð Framing Error Detection

Ð Automatic Address Recognition

Y

Three 16-Bit Timer/Counters

Programmable Counter Array with:

Ð High Speed Output,

Ð Compare/Capture,

Ð Pulse Width Modulator,

Ð Watchdog Timer Capabilities

Y

64K External Program Memory Space

64K External Data Memory Space

MCS 51 Microcontroller Compatible

É

Instruction Set

Y

Up/Down Timer/Counter

Y

Power Saving Idle and Power Down

Modes

Three Level Program Lock System

8K/16K/32K On-Chip Program Memory

256 Bytes of On-Chip Data RAM

Y

ONCE (On-Circuit Emulation) Mode

Extended Temperature Range

Improved Quick Pulse Programming

Algorithm

b

a

40 C to 85 C)

(

§

MEMORY ORGANIZATION

ROM/

OTP ROM

Bytes

ROM

OTP ROM

ROMLESS

Version

RAM

Device

Version

Bytes

83L51FA

83L51FB

83L51FC

87L51FA

87L51FB

87L51FC

80L51FA

8K

16K

32K

256

These devices can address up to 64 Kbytes of external program/data memory.

The Intel 8XL51FA/8XL51FB/8XL51FC is a single-chip control oriented microcontroller which is fabricated on

Intel’s reliable CHMOS III-E technology. Being a member of the MCS 51 microcontroller family, the

É

8XL51FA/8XL51FB/8XL51FC uses the same powerful instruction set, has the same architecture, and is pin-

for-pin compatible with the existing MCS 51 microcontroller products.

The 8XL51FX is a 3V version of current 8XC51FX and will operate from 2.7V to 3.6V at a frequency range of

3.5 MHz to 16 MHz (Express)/20 MHz (Commercial).

For the remainder of this document, the 8XL51FA, 8XL51FB, 8XL51FC will be referred to as the 8XL51FX,

unless information applies to a specific device.

*Other brands and names are the property of their respective owners.

Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or

copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make

changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.

©

COPYRIGHT INTEL CORPORATION, 1995

November 1994

Order Number: 272356-003

8XL51FA/FB/FC

NOTE:

Standard 3.5 MHz to 12 MHz; 2.7V to 3.6V

b

Standard

1

20*

X

80L51FA

83L51FA

87L51FA

83L51FB

87L51FB

83L51FC

87L51FC

X

b

1

20*

3.5 MHz to 16 MHz; 2.7V to 3.6V

3.5 MHz to 20 MHz; 2.7V to 3.6V

X

*Only available for commercial standard temperature

range, not available at express temperature range.

X

272356–1

Figure 1. 8XL51FX Block Diagram

2

8XL51FA/FB/FC

Package Type

PROCESS INFORMATION

PACKAGES

Part

Prefix

The 8XL51FA/8XL51FB/8XL51FC is manufactured

on P629.5, a CHMOS III-E process. Additional pro-

cess and reliability information is available in Intel’s

Components Quality and Reliability Handbook, Or-

der Number 210997.

8XL51FX

N

44-Pin PLCC

(OTP)

44-Pin QFP

(OTP)

S

272356–2

PLCC

272356–3

QFP

Figure 2. Pin Connections

3

8XL51FA/FB/FC

Port 1 receives the low-order address bytes during

OTP ROM programming and verifying.

PIN DESCRIPTIONS

V : Supply voltage.

CC

Port 2: Port 2 is an 8-bit bidirectional I/O port with

internal pullups. The Port 2 output buffers can drive

several inputs. Port 2 pins that have 1’s written to

them are pulled high by the internal pullups, and in

that state can be used as inputs. As inputs, Port 2

pins that are externally pulled low will source current

V

: Circuit ground.

SS

Port 0: Port 0 is an 8-bit, open drain, bidirectional I/O

port. As an output port each pin can sink several

inputs. Port 0 pins that have 1’s written to them float,

and in that state can be used as high-impedance

inputs.

(I , on the data sheet) because of the internal pull-

IL

ups.

Port 2 emits the high-order address byte during

fetches from external Program Memory and during

accesses to external Data Memory that use 16-bit

Port 0 is also the multiplexed low-order address and

data bus during accesses to external Program and

Data Memory. In this application it uses strong inter-

nal pullups when emitting 1’s, and can source and

sink several inputs.

@

addresses (MOVX DPTR). In this application it

uses strong internal pullups when emitting 1’s. Dur-

ing accesses to external Data Memory that use 8-bit

@

addresses (MOVX Ri), Port 2 emits the contents of

the P2 Special Function Register.

Port 0 also receives the code bytes during OTP

ROM programming, and outputs the code bytes dur-

ing program verification. External pullup resistors are

required during program verification.

Some Port 2 pins receive the high-order address bits

during OTP ROM programming and program verifi-

cation.

Port 1: Port 1 is an 8-bit bidirectional I/O port with

internal pullups. The Port 1 output buffers can drive

several inputs. Port 1 pins that have 1’s written to

them are pulled high by the internal pullups, and in

that state can be used as inputs. As inputs, Port 1

pins that are externally pulled low will source current

Port 3: Port 3 is an 8-bit bidirectional I/O port with

internal pullups. The Port 3 output buffers can drive

several inputs. Port 3 pins that have 1’s written to

them are pulled high by the internal pullups, and in

that state can be used as inputs. As inputs, Port 3

pins that are externally pulled low will source current

(I , on the data sheet) because of the internal pull-

IL

ups.

(I , on the data sheet) because of the pullups.

IL

In addition, Port 1 serves the functions of the follow-

ing special features of the 8XL51FX:

Port 3 also serves the functions of various special

features of the MCS 51 microcontroller family, as

listed below:

Port Pin

Alternate Function

P1.0

T2 (External Count Input to Timer/

Counter 2), Clock Out

Port Pin

Alternate Function

RXD (serial input port)

TXD (serial output port)

P3.0

P3.1

P3.2

P3.3

P3.4

P3.5

P3.6

P3.7

P1.1

T2EX (Timer/Counter 2 Capture/

Reload Trigger and Direction Control)

INT0 (external interrupt 0)

INT1 (external interrupt 1)

P1.2

P1.3

ECI (External Count Input to the PCA)

CEX0 (External I/O for Compare/

Capture Module 0)

T0 (Timer 0 external input)

T1 (Timer 1 external input)

P1.4

P1.5

P1.6

P1.7

CEX1 (External I/O for Compare/

Capture Module 1)

WR (external data memory write strobe)

RD (external data memory read strobe)

CEX2 (External I/O for Compare/

Capture Module 2)

RST: Reset input. A high on this pin for two machine

cycles while the oscillator is running resets the de-

vice. The port pins will be driven to their reset condi-

tion when a minimum V

er the oscillator is running or not. An internal pull-

down resistor permits a power-on reset with only a

CEX3 (External I/O for Compare/

Capture Module 3)

CEX4 (External I/O for Compare/

Capture Module 4)

voltage is applied wheth-

IH2

capacitor connected to V

.

CC

4

8XL51FA/FB/FC

ALE: Address Latch Enable output pulse for latching

the low byte of the address during accesses to ex-

ternal memory. This pin (ALE/PROG) is also the

program pulse input during OTP ROM programming

for the 87L51FX.

may be used. More detailed information concerning

the use of the on-chip oscillator is available in Appli-

cation Note AP-155, ‘‘Oscillators for Microcontrol-

lers.’’

To drive the device from an external clock source,

XTAL1 should be driven, while XTAL2 floats, as

shown in Figure 4. There are no requirements on the

duty cycle of the external clock signal, since the in-

put to the internal clocking circuitry is through a di-

vide-by-two flip-flop, but minimum and maximum

high and low times specified on the data sheet must

be observed.

In normal operation ALE is emitted at a constant

rate of (/6 the oscillator frequency, and may be used

for external timing or clocking purposes. Note, how-

ever, that one ALE pulse is skipped during each ac-

cess to external Data Memory.

If desired, ALE operation can be disabled by setting

bit 0 of SFR location 8EH. With this bit set, the pin is

weakly pulled high. However, the ALE disable fea-

ture will be suspended during a MOVX or MOVC in-

struction, idle mode, power down mode and ICE

mode. The ALE disable feature will be terminated by

reset. When the ALE disable feature is suspended or

terminated, the ALE pin will no longer be pulled up

weakly. Setting the ALE-disable bit has no affect if

the microcontroller is in external execution mode.

An external oscillator may encounter as much as a

100 pF load at XTAL1 when it starts up. This is due

to interaction between the amplifier and its feedback

capacitance. Once the external signal meets the V

and V specifications the capacitance will not ex-

IL

IH

ceed 20 pF.

Throughout the remainder of this data sheet, ALE

will refer to the signal coming out of the ALE/PROG

pin, and the pin will be referred to as the ALE/PROG

pin.

PSEN: Program Store Enable is the read strobe to

external Program Memory.

272356–4

e

For Ceramic Resonators, contact resonator manufacturer.

g

30 pF 10 pF for Crystals

C1, C2

When the 8XL51FX is executing code from external

Program Memory, PSEN is activated twice each ma-

chine cycle, except that two PSEN activations are

skipped during each access to external Data Memo-

ry.

Figure 3. Oscillator Connections

EA/V

: External Access enable. EA must be

PP

strapped to VSS in order to enable the device to

fetch code from external Program Memory locations

0000H to 0FFFH. Note, however, that if either of the

Program Lock bits are programmed, EA will be inter-

nally latched on reset.

EA must be strapped to V

executions.

for internal program

CC

272356–5

Figure 4. External Clock Drive Configuration

This pin also receives the programming supply volt-

age (V ) during OTP ROM programming.

PP

XTAL1: Input to the inverting oscillator amplifier.

XTAL2: Output from the inverting oscillator amplifier.

IDLE MODE

The user’s software can invoke the Idle Mode. When

the microcontroller is in this mode, power consump-

tion is reduced. The Special Function Registers and

the onboard RAM retain their values during Idle, but

the processor stops executing instructions. Idle

Mode will be exited if the chip is reset or if an en-

abled interrupt occurs. The PCA timer/counter can

optionally be left running or paused during Idle

Mode.

OSCILLATOR CHARACTERISTICS

XTAL1 and XTAL2 are the input and output, respec-

tively, of a inverting amplifier which can be config-

ured for use as an on-chip oscillator, as shown in

Figure 3. Either a quartz crystal or ceramic resonator

5

8XL51FA/FB/FC

All V and V pins must be connected. Please

SS

#

CC

refer to Figure 2, Pin Connections, for the specific

pins.

POWER DOWN MODE

To save even more power, a Power Down mode can

be invoked by software. In this mode, the oscillator

is stopped and the instruction that invoked Power

Down is the last instruction executed. The on-chip

RAM and Special Function Registers retain their val-

ues until the Power Down mode is terminated.

When the idle mode is terminated by a hardware

reset, the device normally resumes program exe-

cution, from where it left off, up to two machine

cycles before the internal reset algorithm takes

control. On-chip hardware inhibits access to inter-

nal RAM in this event, but access to the port pins

is not inhibited. To eliminate the possibility of an

unexpected write when Idle is terminated by re-

set, the instruction following the one that invokes

Idle should not be one that writes to a port pin or

to external memory.

On the 8XL51FX either hardware reset or external

interrupt can cause an exit from Power Down. Reset

redefines all the SFRs but does not change the on-

chip RAM. An external interrupt allows both the

SFRs and the on-chip RAM to retain their values.

To properly terminate Power Down the reset or ex-

ternal interrupt should not be executed before V is

restored to its normal operating level and must be

held active long enough for the oscillator to restart

and stabilize (normally less than 10 ms).

CC

ONCE MODE

The ONCE (‘‘On-Circuit Emulation’’) Mode facilitates

testing and debugging of systems using the

8XL51FX without the 8XL51FX having to be re-

moved from the circuit. The ONCE Mode is invoked

by:

With an external interrupt, INT0 or INT1 must be en-

abled and configured as level-sensitive. Holding the

pin low restarts the oscillator but bringing the pin

back high completes the exit. Once the interrupt is

serviced, the next instruction to be executed after

RETI will be the one following the instruction that put

the device into Power Down.

1) Pull ALE low while the device is in reset and

PSEN is high;

2) Hold ALE low as RST is deactivated.

While the device is in ONCE Mode, the Port 0 pins

float, and the other port pins and ALE and PSEN are

weakly pulled high. The oscillator circuit remains ac-

tive. While the 8XL51FX is in this mode, an emulator

or test CPU can be used to drive the circuit. Normal

operation is restored when a normal reset is applied.

DESIGN CONSIDERATION

The 8XL51FX will operate from 2.7V to 3.6V with

#

a frequency range of 3.5 MHz to 16 MHz (Ex-

press)/20 MHz (Commercial). Operating beyond

these specifications could cause improper device

functionality.

Table 1. Status of the External Pins during Idle and Power Down

Program

Memory

Mode

Idle

ALE

PSEN

PORT0

PORT1

PORT2

PORT3

Internal

External

Internal

External

1

0

1

0

Data

Float

Data

Float

Data

Address

Data

Idle

Power Down

Data

NOTE:

For more detailed information on the reduced power modes refer to current Embedded Microcontrollers and Processors

Ý

Handbook Volume I, 270646, and Application Note AP-252 (Embedded Applications Handbook), 270648, ‘‘Designing

with the 80C51BH.’’

6

8XL51FA/FB/FC

For the extended temperature range option, this

data sheet specifies the parameters which deviate

from their commercial temperature range limits.

8XL51FX EXPRESS

The Intel EXPRESS system offers enhancements to

the operational specifications of the MCS-51 family

of microcontrollers. These EXPRESS products are

designed to meet the needs of those applications

whose operating requirements exceed commercial

standards.

Table 2. Prefix Identification

Package

Type

Temperature

Range

Prefix

N

S

PLCC

QFP

Commercial

Extended

The EXPRESS program includes the commercial

standard temperature range with burn-in and an ex-

tended temperature range with or without burn-in.

TN

TS

PLCC

QFP

Extended

With the commercial standard temperature range,

operational characteristics are guaranteed over the

temperature range of 0 C to 70 C. With the extend-

NOTE:

Contact your distributor or local sales office to match the

EXPRESS prefix with the proper device.

§

ed temperature range option, operational character-

b

istics are guaranteed over the range of 40 C to

§

a

85 C.

§

EXAMPLES:

N87L51FC indicates 87L51FC in

a PLCC package and

specified for commercial temperature range, without burn-

in.

Package types and EXPRESS versions are identified

by a one- or two-letter prefix to the part number. The

prefixes are listed in Table 2.

TN87L51FC indicates 87L51FC in a PLCC package

and specified for extended temperature range with

burn-in.

7

8XL51FA/FB/FC

ABSOLUTE MAXIMUM RATINGS*

NOTICE: This data sheet contains information on

products in the sampling and initial production phases

of development. It is valid for the devices indicated in

the revision history. The specifications are subject to

change without notice.

b

a

Ambient Temperature Under Bias À 40 C to 85 C

§

Storage Temperature ÀÀÀÀÀÀÀÀÀÀ 65 C to 150 C

§

b

a

§

Voltage on EA/V Pin to V ÀÀÀÀÀÀÀ0V to 13.0V

a

PP

SS

*WARNING: Stressing the device beyond the ‘‘Absolute

Maximum Ratings’’ may cause permanent damage.

These are stress ratings only. Operation beyond the

‘‘Operating Conditions’’ is not recommended and ex-

tended exposure beyond the ‘‘Operating Conditions’’

may affect device reliability.

b a

ÀÀ 0.5V to 6.5V

Voltage on Any Other Pin to V

SS

I

per I/O Pin ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ15 mA

OL

Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5W

(based on PACKAGE heat transfer limitations, not

device power consumption)

OPERATING CONDITIONS

Symbol

Description

Min

Max

Units

T

A

Ambient Temperature Under Bias

Commercial

Express

a

0

70

85

C

§

b

40

C

V

CC

Supply Voltage

2.7

3.6

V

DC CHARACTERISTICS (Over Operating Conditions)

All parameter values apply to all devices unless otherwise indicated.

Symbol

Parameter

Min

Max

Units

Test Conditions

b

V

Input Low Voltage

0.5

0.8

V

IL

(except XTAL1, RST)

b

0.1

Input Low Voltage

(XTAL1, RST)

0.5

0.2 V

V

IL1

IH

CC

a

0.5

Input High Voltage

2.0

V

CC

(Except XTAL1, RST, EA)

b

a

V

Input High Voltage (EA)

V

1.0

V

0.5

V

IH1

IH2

CC

Input High Voltage

(XTAL1, RST)

0.7 V

CC

e

V

Output Low Voltage (Note 4)

(Ports 1, 2 and 3)

0.4

V

I

1.6 mA (Note 1)

3.2 mA

OL

Output Low Voltage (Note 4)

(Port 0, ALE/PSEN)

OL1

OH

OL

(Note 1)

b

e b

(Note 2)

Output High Voltage

V

CC

0.7

V

I

30 mA

OH

(Ports 1, 2 and 3, ALE, PSEN

e b

(Note 2)

Output High Voltage

2.4

V

I

1.0 mA

OH1

OH

(Port 0 in External Bus Mode)

b

e

0.4V

I

Logical 0 Input Current

(Ports 1, 2 and 3)

50

mA

V

IL

IN

k

V

g

Input Leakage Current (Port 0)

10

0

V

LI

IN

CC

8

8XL51FA/FB/FC

Test Conditions

DC CHARACTERISTICS (Over Operating Conditions)

All parameter values apply to all devices unless otherwise indicated. (Continued)

Symbol

Parameter

Logical 1 to 0

Min

Max

Units

b

e

1.4V

I

350

mA

V

TL

IN

Transition Current

(Ports 1, 2 and 3)

RRST

RST Pulldown Resistor

40

225

KX

I

Power Supply Current

Active Mode at 16 MHz

Idle Mode at 16 MHz

Power-Down Mode

(Note 3)

CC

25

8

mA

30

NOTES:

1. Capacitive loading on Ports 0 and 2 may cause noise pulses above 0.4V to be superimposed on the V s of ALE and

OL

Ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins

change from 1 to 0. In applications where capacitance loading exceeds 100 pF, the noise pulses on these signals may

exceed 0.8V. It may be desirable to qualify ALE or other signals with a Schmitt Trigger, or CMOS-level input logic.

2. Capacitive loading on Ports 0 and 2 cause the V

address lines are stabilizing.

3. See Figures 6–9 for test conditions. Minimum V

on ALE and PSEN to drop below the 0.9 V specification when the

CC

OH

for power down is 2V.

CC

4. Under steady state (non-transient) conditions, I must be externally limited as follows:

OL

Maximum I per port pin:

OL

10 mA

Maximum I per 8-bit port -

OL

Port 0:

Ports 1, 2, and 3:

Maximum total I for all output pins:

26 mA

15 mA

71 mA

OL

If I exceeds the test condition, V may exceed the related specification. Pins are not guaranteed to sink current greater

OL

than the listed test conditions.

Running the device with EA at a higher voltage than V

sinks additional currrent.

CC

272356–6

I

Max at other frequencies (3.5 MHz to 20 MHz) is given by:

CC

Active Mode

e

c

a

I

MAX

1.1

0.4

FREQ

7.6

1.8

CC

Idle Mode

MAX

c

I

CC

Where FREQ is in MHz, I

MAX is given in mA.

CC

Figure 5. I vs Frequency

CC

9

8XL51FA/FB/FC

272356–7

272356–8

All other pins disconnected

e

All other pins disconnected

e

TCHCL 5 ns

TCLCH

TCHCL

5 ns

TCLCH

Figure 6. I Test Condition, Active Mode

CC

Figure 7. I Test Condition Idle Mode

CC

272356–9

All other pins disconnected

Figure 8. I Test Condition, Power Down Mode.

CC

e

V

2.7V to 3.6V.

CC

272356–10

e

5 ns.

Figure 9. Clock Signal Waveform for I Tests in Active and Idle Modes. TCLCH

CC

TCHCL

10

8XL51FA/FB/FC

L: Logic level LOW, or ALE

P: PSEN

EXPLANATION OF THE AC SYMBOLS

Each timing symbol has 5 characters. The first char-

acter is always a ‘T’ (stands for time). The other

characters, depending on their positions, stand for

the name of a signal or the logical status of that

signal. The following is a list of all the characters and

what they stand for.

Q: Output Data

R: RD signal

T: Time

V: Valid

W: WR signal

A: Address

X: No longer a valid logic level

Z: Float

C: Clock

D: Input Data

For example,

H: Logic level HIGH

I: Instruction (program memory contents)

e

TAVLL

TLLPL

Time from Address Valid to ALE Low

Time from ALE Low to PSEN Low

AC CHARACTERISTICS (Over Operating Conditions, Load Capacitance for Port 0, ALE/PROG and

e

80 pF)

PSEN

100 pF, Load Capacitance for All Other Outputs

EXTERNAL MEMORY CHARACTERISTICS

All parameter values apply to all devices unless otherwise indicated. In this table, 8XL51FX refers to 8XL51FX

and 8XL51FX-1.

12 MHz

20 MHz

Variable

Units

Oscillator

Symbol

Parameter

Min Max Min Max

Min

Max

1/TCLCL Oscillator Frequency

8XL51FX

8XL51FX-1

3.5

12

16

20

MHz

8XL51FX-20

b

TLHLL

TAVLL

ALE Pulse Width

127

43

60

10

2 TCLCL

40

ns

b

Address Valid to

ALE Low

TCLCL

40

b

TLLAX

TLLIV

Address Hold After

ALE Low

53

20

TCLCL

30

ns

ALE Low to Valid

Instruction In

8XL51FX

b

234

4 TCLCL

100

75

ns

8XL51FX-20

125

b

TLLPL

ALE Low to PSEN

Low

53

20

TCLCL

30

ns

b

3 TCLCL 45

TPLPH

TPLIV

PSEN Pulse Width

205

105

ns

PSEN Low to Valid

Instruction In

8XL51FX

b

145

3 TCLCL

105

90

ns

8XL51FX-20

60

TPXIX

Input Instruction

Hold After PSEN

0

ns

11

8XL51FA/FB/FC

EXTERNAL MEMORY CHARACTERISTICS (Continued)

All parameter values apply to all devices unless otherwise indicated.

12 MHz

20 MHz

Variable

Oscillator

Symbol

Parameter

Units

Min Max Min Max

Min

Max

TPXIZ

Input Instruction Float

After PSEN

b

8XL51FX

59

TCLCL 25

ns

b

TCLCL 20

8XL51FX-20

30

b

5 TCLCL 105

TAVIV

TPLAZ

TRLRH

Address to Valid

Instruction In

312

10

145

ns

PSEN Low to Address

Float

10

ns

b

6 TCLCL 100

RD Pulse Width

400

200

ns

b

6 TCLCL 100

TWLWH WR Pulse Width

TRLDV

RD Low to Valid Data In

b

8XL51FX

252

5 TCLCL 165

ns

b

5 TCLCL 95

8XL51FX-20

155

40

TRHDX

TRHDZ

TLLDV

Data Hold After RD

Data Float After RD

0

ns

b

2 TCLCL 60

107

517

ALE Low to Valid Data In

8XL51FX

b

8 TCLCL 150

ns

b

8 TCLCL 90

8XL51FX-20

310

TAVDV

Address to Valid Data In

8XL51FX

b

585

300

9 TCLCL 165

ns

b

9 TCLCL 90

8XL51FX-20

360

200

b

3 TCLCL 50

a

50

TLLWL

TAVWL

ALE Low to RD or WR

Low

200

100

3 TCLCL

ns

Address Valid to WR

Low

b

8XL51FX

203

33

4 TCLCL 130

ns

b

4 TCLCL 90

8XL51FX-20

110

15

TQVWX

TWHQX

TQVWH

Data Valid before WR

8XL51FX

b

TCLCL 50

ns

b

TCLCL 35

8XL51FX-20

Data Hold after WR

8XL51FX

b

33

TCLCL 50

ns

b

TCLCL 40

8XL51FX-20

10

Data Valid to WR High

8XL51FX

b

433

7 TCLCL 150

ns

b

7 TCLCL 70

8XL51FX-20

280

10

TRLAZ

RD Low to Address Float

0

ns

b

TCLCL 40

a

40

TWHLH

RD or WR High to ALE

High

43

123

90

TCLCL

12

8XL51FA/FB/FC

EXTERNAL PROGRAM MEMORY READ CYCLE

272356–23

EXTERNAL DATA MEMORY READ CYCLE

272356–24

EXTERNAL DATA MEMORY WRITE CYCLE

272356–25

13

8XL51FA/FB/FC

SERIAL PORT TIMING - SHIFT REGISTER MODE

e

Test Conditions: Over Operating Conditions; Load Capacitance 80 pF

12 MHz

20 MHz

Variable

Oscillator

Symbol

Parameter

Units

Min Max

Min

Max

Min

Max

TXLXL

TQVXH

TXHQX

Serial Port Clock

Cycle Time

1

0.600

12 TCLCL

ms

b

10 TCLCL 133

Output Data Setup to

Clock Rising Edge

700

367

ns

Output Data Hold

after Clock Rising

Edge

b

8XC5X

50

0

2 TCLCL 117

ns

b

2 TCLCL 50

8XC5X-20

50

0

TXHDX

TXHDV

Input Data Hold After

Clock Rising Edge

0

ns

b

10 TCLCL 133

Clock Rising Edge to

Input Data Valid

700

367

ns

SHIFT REGISTER MODE TIMING WAVEFORMS

272356–26

14

8XL51FA/FB/FC

EXTERNAL CLOCK DRIVE

Symbol

Parameter

Min

Max

Units

1/TCLCL

Oscillator Frequency

8XL51FX

8XL51FX-1

3.5

12

16

20

MHz

8XL51FX-20

TCHCX

TCLCX

TCLCH

TCHCL

High Time

Low Time

Rise Time

Fall Time

20

ns

20

EXTERNAL CLOCK DRIVE WAVEFORM

272356–27

AC TESTING INPUT, OUTPUT WAVEFORMS

FLOAT WAVEFORMS

272356–29

port pin is no longer floating when

100 mV change from load voltage occurs, and begins to float

when a 100 mV change from the loaded V /V level occurs.

272356–28

For timing purposes

a

b

and 0.45V for a Logic ‘‘0’’. Timing measurements are made at V

AC Inputs during testing are driven at V

0.5V for a Logic ‘‘1’’

CC

IH

OH OL

10 mA).

min for a Logic ‘‘1’’ and V max for a Logic ‘‘0’’.

IL

e

g

I

/I

OL OH

20 mA (-L, I /I

OL OH

15

8XL51FA/FB/FC

Normally EA/V is held at logic high until just be-

PP

fore ALE/PROG is to be pulsed. Then EA/V

PROGRAMMING THE OTP ROM

is

raised to V , ALE/PROG is pulsed low, and then

PP

To be programmed, the part must be running with a

4 to 6 MHz oscillator. (The reason the oscillator

needs to be running is that the internal bus is being

used to transfer address and program data to appro-

priate internal OTP ROM locations.) The address of

an OTP ROM location to be programmed is applied

to Port 1 and pins P2.0 - P2.4 of Port 2, while the

code byte to be programmed into that location is

applied to Port 0. The other Port 2 and 3 pins, RST

PP

EA/V is returned to a valid high voltage. The volt-

PP

age on the EA/V pin must be at the valid EA/V

PP

high level before a verify is attempted. Waveforms

and detailed timing specifications are shown in later

sections of this data sheet.

NOTE:

EA/V pin must not be allowed to go above the

PP

maximum specified V level for any amount of

#

PSEN, and EA/V should be held at the ‘‘Program’’

PP

time. Even a narrow glitch above that voltage lev-

el can cause permanent damage to the device.

The V source should be well regulated and free

levels indicated in Table 3. ALE/PROG is pulsed low

to program the code byte into the addressed OTP

ROM location. The setup is shown in Figure 10.

PP

of glitches.

Table 3. OTP ROM Programming Modes

e

5V 10%)

g

(H

2.7V to 3.6V; H1

ALE/

EA/

Mode

RST

PSEN

P2.6

P2.7

P3.3

P3.6

P3.7

V

CC

PROG

V

PP

Program Code Data

Verify Code Data

H1

H

L

ß

H

12.75V

H

L

H1

L

H1

L

H1

H

H1

H

H1

H

Program Encryption

Array Address 0–3FH

H1

ß

12.75V

H1

L

H1

Program Lock

Bits

Bit 1

Bit 2

Bit 3

H1

H

L

ß

H

12.75V

H

H1

L

H1

L

H1

L

H1

L

H1

L

H1

H

H1

L

Read Signature Byte

L

272356–18

*See Table 2 for proper input on these pins

Figure 10. Programming the OTP ROM

16

8XL51FA/FB/FC

Repeat 1 through 5 changing the address and data

for the entire array or until the end of the object file is

reached.

PROGRAMMING ALGORITHM

Refer to Table 3 and Figures 10 and 11 for address,

data, and control signals set up. To program the

87L51FX the following sequence must be exercised.

PROGRAM VERIFY

1. Input the valid address on the address lines.

2. Input the appropriate data byte on the data

lines.

Program verify may be done after each byte or block

of bytes is programmed. In either case a complete

verify of the programmed array will ensure reliable

programming of the 87L51FX.

3. Activate the correct combination of control sig-

nals.

g

to 12.75V 0.25V.

4. Raise EA/V from V

PP

CC

The lock bits cannot be directly verified. Verification

of the lock bits is done by observing that their fea-

tures are enabled.

5. Pulse, ALE/PROG 5 times for the OTP ROM

array, and 25 times for the encryption table and

the lock bits.

272356–19

Figure 11. Programming Signals Waveforms

ROM and OTP ROM Lock System

Encryption Array

The 87L51FX program lock system, when pro-

grammed, protects the onboard program against

software piracy.

Within the OTP ROM array are 64 bytes of Encryp-

tion Array that are initially unprogrammed (all 1’s).

Every time that a byte is addressed during a verify, 6

address lines are used to select a byte of the En-

cryption Array. This byte is then exclusive-NOR’ed

(XNOR) with the code byte, creating an Encryption

Verify byte. The algorithm, with the array in the un-

programmed state (all 1’s), will return the code in its

original, unmodified form. For programming the En-

cryption Array, refer to Table 3 (Programming the

OTP ROM).

The 83L51FX has a one-level program lock system

and a 64-byte encryption table. See line 2 of Table

4. If program protection is desired, the user submits

the encryption table with their code, and both the

lock-bit and encryption array are programmed by the

factory. The encryption array is not available without

the lock bit. For the lock bit to be programmed, the

user must submit an encryption table.

When using the encryption array, one important fac-

tor needs to be considered. If a code byte has the

value 0FFH, verifying the byte will produce the en-

The 87L51FX has a 3-level program lock system

and a 64-byte encryption array. Since this is an OTP

ROM device, all locations are user-programmable.

See Table 4.

l

cryption byte value. lf a large block ( 64 bytes) of

code is left unprogrammed, a verification routine will

display the contents of the encryption array. For this

reason all unused code bytes should be pro-

grammed with some value other than 0FFH, and not

all of them the same value. This will ensure maxi-

mum program protection.

17

8XL51FA/FB/FC

Table 4. Program Lock Bits and the Features

ProtectIon Type

Program Lock Bits

LB1 LB2 LB3

1

2

U

No Program Lock features enabled. (Code verify will still be encrypted by the

Encryption Array if programmed.)

P

U

MOVC instructions executed from external program memory are disabled from

fetching code bytes from internal memory, EA is sampled and latched on Reset,

and further programming of the OTP ROM is disabled.

3

4

P

U

P

Same as 2, also verify is disabled.

Same as 3, also external execution is disabled.

Any other combination of the lock bits is not defined.

Program Lock Bits

Location

30H

Device

All

Contents

89H

The 87L51FX has 3 programmable lock bits that

when programmed according to Table 4 will provide

different levels of protection for the on-chip code

and data.

31H

All

58H

60H

83L51FA

87L51FA

83L51FB

87L51FB

83L51FC

87L51FC

70H

F0H

71H

F1H

72H

F2H

Reading the Signature Bytes

The 87L51FX/83L51FX has 3 signature bytes in lo-

cations 30H, 31H, and 60H. To read these bytes fol-

low the procedure for OTP ROM verify, but activate

the control lines provided in Table 3 for Read Signa-

ture Byte.

18

8XL51FA/FB/FC

OTP ROM PROGRAMMING AND VERIFICATION CHARACTERISTICS

e

0V)

SS

(T

A

21 C to 27 C; V

2.7V to 3.6V; V

§

CC

Symbol

Parameter

Min

Max

13.0

75

Units

V

Programming Supply Voltage

Programming Supply Current

Oscillator Frequency

12.5

PP

I

mA

PP

1/TCLCL

TAVGL

TGHAX

TDVGL

TGHDX

TEHSH

TSHGL

TGHSL

TGLGH

TAVQV

TELQV

TEHQZ

TGHGL

4

6

MHz

Address Setup to PROG Low

Address Hold after PROG

Data Setup to PROG Low

Data Hold after PROG

48TCLCL

10

P2.7 (ENABLE) High to V

PP

V

Setup to PROG Low

Hold after PROG

ms

PP

10

PROG Width

90

100

Address to Data Valid

48TCLCL

ENABLE Low to Data Valid

Data Float after ENABLE

PROG High to PROG Low

0

10

ms

OTP ROM PROGRAMMING AND VERIFICATION WAVEFORMS

272356–20

NOTE:

*5 pulses for the OTP ROM array, 25 pulses for the encryption table and lock bits.

19

8XL51FA/FB/FC

Thermal Impedance

Data Sheet Revision History

The thermal impedance data is approximate for stat-

ic air conditions at 1W of power dissipation. Values

will change depending on operating conditionis and

applications. See the Intel Packaging Handbook (Or-

der Number 240800) for a description of Intel’s ther-

mal impedance test methodology.

This 8XL51FA/FB/FC data sheet (Advanced Infor-

mation) replaces 272356-001 (Product Preview).

Package

i

Device

JA

JC

N

S

46 C/W

§

16 C/W

§

All

52

54

58

87 CW

§

18 C/W

§

96 C/W

§

90 C/W

§

24 C/W

§

22 C/W

§

20


型号：	TS87L51FB
厂家：	INTEL
描述：	Microcontroller, 8-Bit, OTPROM, 8051 CPU, 6MHz, CMOS, PQFP44, QFP-44 可编程只读存储器时钟微控制器外围集成电路装置
文件：	总20页 (文件大小：282K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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