TC83C251TA24 [INTEL]
Microcontroller, 8-Bit, MROM, CMOS, CDIP40, CERAMIC, DIP-40;
| 型号： | TC83C251TA24 |
| 厂家： | 
INTEL |
| 描述： | Microcontroller, 8-Bit, MROM, CMOS, CDIP40, CERAMIC, DIP-40 时钟 CD 微控制器 外围集成电路 |
| 文件： | 总34页 (文件大小：238K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADVANCE INFORMATION
8xC251TA/TB/TP/TQ
HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Commercial/Express
■ Real-time and Programmed Wait State
■ User-selectable Configurations:
Bus Operation
— External Wait States (0-3 wait
states)
— Address Range & Memory Mapping
— Page Mode
— Extended Data Float Timings or
8xC251Sx Compatible AC Timings
®
■ Binary-code Compatible with MCS 51
■ Pin Compatible with 44-pin PLCC and
40-pin PDIP MCS 51 Sockets
®
■ Register-based MCS 251 Architecture
— 40-byte Register File
— Registers Accessible as Bytes,
Words, or Double Words
■ 32 Programmable I/O Lines
■ Eight Maskable Interrupt Sources with
Four Programmable Priority Levels
■ Enriched MCS 51 Instruction Set
■ Three Flexible 16-bit Timer/counters
■ Hardware Watchdog Timer
— 16-bit and 32-bit Arithmetic and
Logic Instructions
— Compare and Conditional Jump
Instructions
— Expanded Set of Move Instructions
■ Programmable Counter Array
— High-speed Output
— Compare/Capture Operation
— Pulse Width Modulator
— Watchdog Timer
■ Linear Addressing
■ 256-Kbyte Expanded External
Code/Data Memory Space
■ Two Programmable Serial I/O Ports
— Framing Error Detection
■ ROM Options:
16 Kbytes (TB/TQ), 8 Kbytes (TA/TP), or
without ROM
— Automatic Address Recognition
■ High-performance CHMOS Technology
■ Static Standby to 24-MHz Operation
■ 16-bit Internal Code Fetch
■ 64-Kbyte Extended Stack Space
■ Complete System Development
■ On-chip Data RAM Options:
Support
1-Kbyte (TA/TB) or 512-Byte (TP/TQ)
— Compatible with Existing Tools
■ 8-bit, 2-clock External Code Fetch in
— MCS 251 Tools Available:
Compiler, Assembler, Debugger,
ICE
Page Mode
■ Fast MCS 251 Instruction Pipeline
■ Package Options (PDIP and PLCC)
© INTEL CORPORATION, 1997
November, 1997
Order Number: 273129-001
Information in this document is provided in connection with Intel products. No license, express or implied, by
estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in
Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel
disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or
warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright
or other intellectual property right. Intel products are not intended for use in medical, life saving, or life
sustaining applications. Intel may make changes to specifications and product descriptions at any time, without
notice. Contact your local Intel sales office or your distributor to obtain the latest specifications and before
placing your product order.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or
"undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or
incompatibilities arising from future changes to them.
The 8xC251TA/TB/TP/TQ may contain design defects or errors known as errata which may cause the product
to deviate from published specifications. Current characterized errata are available on request.
Copies of documents which have an ordering number and are referenced in this document, or other Intel
literature, may be obtained from:
Intel Corporation
P.O. Box 5937
Denver CO 80217-9808
or call 1-800-548-4725.
Many documents are available for download from Intel’s website at http://www.intel.com.
Copyright © Intel Corporation 1997.
*Third party brands and names are the property of their respective owners.
Contents
8xC251TA/TB/TP/TQ
HIGH-PERFORMANCE CHMOS Microcontroller
Commercial/Express
1.0 INTRODUCTION ......................................................................................................................................... 1
2.0 NOMENCLATURE ...................................................................................................................................... 2
3.0 PINOUT ....................................................................................................................................................... 4
4.0 SIGNALS ..................................................................................................................................................... 8
5.0 ADDRESS MAP ........................................................................................................................................ 11
6.0 ELECTRICAL CHARACTERISTICS ......................................................................................................... 12
6.1 D.C. Characteristics ........................................................................................................................... 12
6.2 Definition of AC Symbols ................................................................................................................... 14
6.3 A.C. Characteristics ........................................................................................................................... 14
6.3.1 External Bus Cycles, Nonpage Mode ..................................................................................... 18
6.3.2 External Bus Cycles, Page Mode ........................................................................................... 21
6.3.3 Definition of Real-Time Wait Symbols .................................................................................... 24
6.3.4 External Bus Cycles, Real-Time Wait States .......................................................................... 24
6.4 AC Characteristics — Serial Port, Shift Register Mode ..................................................................... 28
6.5 External Clock Drive .......................................................................................................................... 29
7.0 THERMAL CHARACTERISTICS .............................................................................................................. 30
ADVANCE INFORMATION
iii
Contents
FIGURES
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
8xC251TA/TB/TP/TQ Block Diagram ........................................................................................ 1
The 8xC251TA/TB/TP/TQ Family Nomenclature....................................................................... 2
8xC251TA/TB/TP/TQ 44-pin PLCC Package ............................................................................ 4
8xC251TA/TB/TP/TQ 40-pin PDIP Packages............................................................................ 5
External Bus Cycle: Code Fetch (Nonpage Mode).................................................................. 18
External Bus Cycle: Data Read (Nonpage Mode) ................................................................... 19
External Bus Cycle: Data Write (Nonpage Mode).................................................................... 20
External Bus Cycle: Code Fetch (Page Mode) ........................................................................ 21
External Bus Cycle: Data Read (Page Mode).......................................................................... 22
External Bus Cycle: Data Write (Page Mode).......................................................................... 23
External Bus Cycle: Code Fetch/Data Read (Nonpage Mode)................................................ 24
External Bus Cycle: Data Write (Nonpage Mode).................................................................... 25
External Bus Cycle: Code Fetch/Data Read (Page Mode)...................................................... 26
External Bus Cycle: Data Write (Page Mode).......................................................................... 27
Serial Port Waveform — Shift Register Mode.......................................................................... 28
External Clock Drive Waveforms ............................................................................................. 29
AC Testing Input, Output Waveforms ...................................................................................... 29
Float Waveforms...................................................................................................................... 30
TABLES
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Description of Product Nomenclature ........................................................................................2
Proliferation Options ..................................................................................................................3
Package Information ..................................................................................................................3
8xC251TA/TB/TP/TQ Pin Assignment .......................................................................................6
8xC251TA/TB/TP/TQ PLCC/DIP Pin Assignments Arranged by Functional Category ..............7
Signal Descriptions ....................................................................................................................8
Memory Signal Selections (RD1:0) ..........................................................................................10
8xC251TA/TB/TP/TQ Address Map .........................................................................................11
DC Characteristics at VCC = 4.5 – 5.5 V ..................................................................................12
AC Timing Symbol Definitions .................................................................................................14
AC Characteristics ...................................................................................................................14
Real-time Wait Timing Symbol Definitions ...............................................................................24
Real-Time Wait AC Timing ......................................................................................................27
Serial Port Timing — Shift Register Mode ...............................................................................28
External Clock Drive ................................................................................................................29
Thermal Characteristics ...........................................................................................................30
iv
ADVANCE INFORMATION
8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
feature an enriched instruction set, linear
addressing, and efficient C-language support. The
1.0 INTRODUCTION
8xC251TA/TB/TP/TQ has 512 bytes or 1 Kbyte of
on-chip RAM and is available with 8 Kbytes or 16
Kbytes of on-chip ROM, or without ROM. A variety of
features can be selected by new user-programmable
configurations.
A member of the Intel family of 8-bit MCS 251 micro-
controllers, the 8xC251TA/TB/TP/TQ is binary-code
compatible with MCS 51 microcontrollers and pin
compatible with 40-pin PDIP and 44-pin PLCC
MCS 51 microcontrollers. MCS 251 microcontrollers
I/O Ports and
Peripheral Signals
System Bus and I/O Ports
P0.7:0
P1.7:0
P2.7:0
P3.7:0
Code
OTPROM/ROM
8 Kbytes
or
Data RAM
512 Bytes
or
Port 0
Drivers
Port 2
Drivers
Port 1
Drivers
Port 3
Drivers
1024 Bytes
16 Kbytes
Memory Data (16)
Watchdog
Timer
Memory Address (16)
Peripheral
Interface
Bus Interface
Timer/
Counters
Code Bus (16)
Code Address (24)
Interrupt
Handler
Instruction Sequencer
PCA
SRC1 (8)
SRC2 (8)
Two
Serial I/O
Ports
Clock
&
Reset
Data
Register
File
Memory
Interface
ALU
Peripherals
DST (16)
®
MCS 251 Microcontroller Core
Clock & Reset
8XC251TA/TB/TP/TQ Microcontroller
A4530-01
Figure 1. 8xC251TA/TB/TP/TQ Block Diagram
ADVANCE INFORMATION
1
8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
2.0 NOMENCLATURE
X
XX
8
X
X
XXXXX XX
A2815-01
Figure 2. The 8xC251TA/TB/TP/TQ Family Nomenclature
Table 1. Description of Product Nomenclature
Parameter
Options
Description
Temperature and Burn-in
Options
no mark
Commercial operating temperature range (0°C to 70°C) with
Intel standard burn-in.
T
Express operating temperature range (-40°C to 85°C)
without Intel standard burn-in.
Packaging Options
N
P
44-pin Plastic Leaded Chip Carrier (PLCC)
40-pin Plastic Dual In-line Package (PDIP)
40-pin Ceramic Dual In-line Package (Ceramic DIP)
Without ROM
C
Program Memory Options
0
3
ROM
Process Information
Product Family
C
CHMOS
251
TA
TB
TP
TQ
24
8-bit control architecture
Device Memory Options
1-Kbyte RAM/8-Kbyte ROM
1-Kbyte RAM/16-Kbyte ROM or without ROM
512-byte RAM/8-Kbyte ROM
512-byte RAM/16-Kbyte ROM or without ROM
External clock frequency
Device Speed
2
ADVANCE INFORMATION
8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 2 lists the proliferation options. See Figure 2 for the 8xC251TA/TB/TP/TQ family nomenclature.
Table 2. Proliferation Options
8xC251TA/TB/TP/TQ
(0 – 24 MHz; 5 V ±10%)
80C251TB24
80C251TQ24
83C251TA24
83C251TB24
83C251TP24
83C251TQ24
CPU-only
CPU-only
ROM
ROM
ROM
ROM
Table lists the 8xC251TA/TB/TP/TQ package definitions.
Table 3. Package Information
Pkg.
Definition
Temperature
N
44 ld. PLCC
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
P
40 ld. Plastic DIP
44 ld. PLCC
TN
TP
40 ld. Plastic DIP
ADVANCE INFORMATION
3
8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
3.0 PINOUT
P1.5 / CEX2
P1.6 / CEX3 / WAIT#
P1.7 / CEX4 / A17 / WCLK
RST
7
8
9
39
38
37
36
35
34
33
32
31
30
29
AD4 / P0.4
AD5 / P0.5
AD6 / P0.6
AD7 / P0.7
EA#
SS2
ALE
PSEN#
8XC251TA
8XC251TB
8XC251TP
8XC251TQ
10
11
12
13
14
15
16
17
P3.0 / RXD
V
V
CC2
P3.1 / TXD
P3.2 / INT0#
P3.3 / INT1#
P3.4 / T0
View of component as
mounted on PC board
A15 / P2.7
A14 / P2.6
A13 / P2.5
P3.5 / T1
A4538-01
Figure 3. 8xC251TA/TB/TP/TQ 44-pin PLCC Package
4
ADVANCE INFORMATION
8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
V
P1.0 / T2
P1.1 / T2EX
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
CC
AD0 / P0.0
AD1 / P0.1
AD2 / P0.2
AD3 / P0.3
AD4 / P0.4
AD5 / P0.5
AD6 / P0.6
AD7 / P0.7
EA#
2
P1.2 / ECI / RXD1
P1.3 / CEX0 / TXD1
P1.4 / CEX1
3
4
5
8XC251TA
8XC251TB
8XC251TP
8XC251TQ
P1.5 / CEX2
6
P1.6 / CEX3 / WAIT#
P1.7 / CEX4 / A17 / WCLK
RST
7
8
9
P3.0 / RXD
10
11
12
13
14
15
16
17
18
19
20
P3.1 / TXD
ALE
P3.2 / INT0#
P3.3 / INT1#
P3.4 / T0
PSEN#
A15 / P2.7
A14 / P2.6
A13 / P2.5
A12 / P2.4
A11 / P2.3
A10 / P2.2
A9 / P2.1
A8 / P2.0
View of
component
as mounted
on PC board
P3.5 / T1
P3.6 / WR#
P3.7 / RD# / A16
XTAL2
XTAL1
V
SS
A4532-02
Figure 4. 8xC251TA/TB/TP/TQ 40-pin PDIP Packages
ADVANCE INFORMATION
5
8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 4. 8xC251TA/TB/TP/TQ Pin Assignment
PLCC
1
DIP
Name
PLCC
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
DIP
Name
VSS1
VSS2
2
1
2
P1.0/T2
21
22
23
24
25
26
27
28
29
30
A8/P2.0
A9/P2.1
3
P1.1/T2EX
P1.2/ECI/RXD1
P1.3/CEX0/TXD1
P1.4/CEX1
P1.5/CEX2
P1.6/CEX3/WAIT#
P1.7/CEX4/A17/WCLK
RST
4
3
A10/P2.2
A11/P2.3
A12/P2.4
A13/P2.5
A14/P2.6
A15/P2.7
PSEN#
5
4
6
5
7
6
8
7
9
8
10
11
12
13
14
15
16
17
18
19
20
21
22
9
10
P3.0/RXD
VCC2
ALE
VSS2
11
12
13
14
15
16
17
18
19
20
P3.1/TXD
31
32
33
34
35
36
37
38
39
40
EA#
P3.2/INT0#
P3.3/INT1#
P3.4/T0
AD7/P0.7
AD6/P0.6
AD5/P0.5
AD4/P0.4
AD3/P0.3
AD2/P0.2
AD1/P0.1
AD0/P0.0
VCC
P3.5/T1
P3.6/WR#
P3.7/RD#/A16
XTAL2
XTAL1
VSS
6
ADVANCE INFORMATION
8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 5. 8xC251TA/TB/TP/TQ PLCC/DIP Pin Assignments Arranged by Functional Category
Address & Data
Name PLCC
AD0/P0.0
Input/Output
Name PLCC
DIP
39
38
37
36
35
34
33
32
21
22
23
24
25
26
27
28
17
8
DIP
1
43
42
41
40
39
38
37
36
24
25
26
27
28
29
30
31
19
9
P1.0/T2
2
3
AD1/P0.1
AD2/P0.2
AD3/P0.3
AD4/P0.4
AD5/P0.5
AD6/P0.6
AD7/P0.7
A8/P2.0
P1.1/T2EX
2
P1.2/ECI/RXD1
P1.3/CEX0/TXD1
P1.4/CEX1
4
3
5
4
6
5
P1.5/CEX2
7
6
P1.6/CEX3/WAIT#
P1.7/CEX4/A17/WCLK
P3.0/RXD
8
7
9
8
11
13
16
17
10
11
14
15
A9/P2.1
P3.1/TXD
A10/P2.2
P3.4/T0
A11/P2.3
P3.5/T1
A12/P2.4
A13/P2.5
Power & Ground
A14/P2.6
Name
VCC
PLCC
44
DIP
A15/P2.7
40
P3.7/RD#/A16
P1.7/CEX4/A17/WCLK
VCC2
12
VSS
22
20
31
VSS1
1
VSS2
23, 34
35
Processor Control
EA#
Name
PLCC
14
DIP
12
13
31
9
P3.2/INT0#
P3.3/INT1#
EA#
Bus Control & Status
15
Name
P3.6/WR#
PLCC
18
DIP
16
35
RST
10
P3.7/RD#/A16
ALE
19
17
XTAL1
XTAL2
21
18
19
33
30
20
PSEN#
32
29
ADVANCE INFORMATION
7
8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
4.0 SIGNALS
Table 6. Signal Descriptions (Sheet 1 of 3)
Signal
Name
Alternate
Function
Type
Description
A17
O
18th Address Bit (A17). Output to memory as 18th external address bit P1.7/CEX4/
(A17) in extended bus applications, depending on the values of bits RD0 WCLK
and RD1 in configuration byte UCONFIG0. See also RD# and PSEN#.
A16
O
O
Address Line 16. See RD#.
RD#
A15:81
AD7:01
Address Lines. Upper address lines for the external bus.
P2.7:0
P0.7:0
I/O
Address/Data Lines. Multiplexed lower address lines and data lines for
external memory.
ALE
O
I/O
I
Address Latch Enable. ALE signals the start of an external bus cycle
and indicates that valid address information is available on lines A15:8
and AD7:0. An external latch can use ALE to demultiplex the address
from the address/data bus.
CEX4:0
EA#
Programmable Counter Array (PCA) Input/Output Pins. These are
input signals for the PCA capture mode and output signals for the PCA
compare mode and PCA PWM mode.
P1.6:4
P1.7/A17/
WAIT#
P1.3/TXD1
External Access. Directs program memory accesses to on-chip or off-
chip code memory. For EA# = 0, all program memory accesses are off-
chip. For EA# = 1, an access is to on-chip ROM if the address is within
the range of the on-chip ROM; otherwise the access is off-chip. The value
of EA# is latched at reset. For devices without on-chip ROM, EA# must
be strapped to ground.
ECI
I
I
PCA External Clock Input. External clock input to the 16-bit PCA timer. P1.2/RXD1
INT1:0#
External Interrupts 0 and 1. These inputs set bits IE1:0 in the TCON
register. If bits IT1:0 in the TCON register are set, bits IE1:0 are set by a
falling edge on INT1#/INT0#. If bits INT1:0 are clear, bits IE1:0 are set by
a low level on INT1:0#.
P3.3:2
P0.7:0
I/O
I/O
Port 0. This is an 8-bit, open-drain, bidirectional I/O port.
AD7:0
P1.0
Port 1. This is an 8-bit, bidirectional I/O port with internal pullups.
T2
P1.1
T2EX
P1.2
P1.7:3
ECI/RXD1
CEX3:1
CEX4/A17/
WAIT#/
WCLK
CEX0/TXD1
P2.7:0
I/O
I/O
Port 2. This is an 8-bit, bidirectional I/O port with internal pullups.
Port 3. This is an 8-bit, bidirectional I/O port with internal pullups.
A15:8
P3.0
RXD
P3.1
TXD
P3.3:2
P3.5:4
P3.6
INT1:0#
T1:0
WR#
P3.7
RD#/A16
PSEN#
O
Program Store Enable. Read signal output. This output is asserted for a
memory address range that depends on bits RD0 and RD1 in configu-
ration byte UCONFIG0 (see RD#).
—
8
ADVANCE INFORMATION
8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 6. Signal Descriptions (Sheet 2 of 3)
Signal
Name
Alternate
Type
Description
Function
RD#
O
Read or 17th Address Bit (A16). Read signal output to external data
memory or 17th external address bit (A16), depending on the values of
bits RD0 and RD1 in configuration byte UCONFIG0. (See PSEN#).
P3.7/A16
RST
I
Reset. Reset input to the chip. Holding this pin high for 64 oscillator
periods while the oscillator is running resets the device. The port pins are
driven to their reset conditions when a voltage greater than VIH1 is
applied, whether or not the oscillator is running. This pin has an internal
pulldown resistor, which allows the device to be reset by connecting a
—
capacitor between this pin and VCC
.
Asserting RST when the chip is in idle mode or powerdown mode returns
the chip to normal operation.
RXD
I/O
I/O
Receive Serial Data. RXD sends and receives data in serial I/O mode 0 P3.0
and receives data in serial I/O modes 1, 2, and 3.
RXD1
Receive Serial Data 1. RXD1 sends and receives data in serial I/O
mode 0 and receives data in serial I/O modes 1, 2, and 3 for the 2nd
serial port.
P1.2/ECI
T1:0
T2
I
Timer 1:0 External Clock Inputs. When timer 1:0 operates as a counter, P3.5:4
a falling edge on the T1:0 pin increments the count.
I/O
Timer 2 Clock Input/Output. For the timer 2 capture mode, this signal is P1.0
the external clock input. For the clock-out mode, it is the timer 2 clock
output.
T2EX
I
Timer 2 External Input. In timer 2 capture mode, a falling edge initiates a P1.1
capture of the timer 2 registers. In auto-reload mode, a falling edge
causes the timer 2 registers to be reloaded. In the up-down counter
mode, this signal determines the count direction: 1 = up, 0 = down.
TXD
O
O
Transmit Serial Data. TXD outputs the shift clock in serial I/O mode 0
and transmits serial data in serial I/O modes 1, 2, and 3.
P3.1
TXD1
Transmit Serial Data 1. TXD1 outputs the shift clock in serial I/O mode 0 P1.3/CEX0
and transmits serial data in serial I/O modes 1, 2, and 3 for the 2nd serial
port.
VCC
PWR Supply Voltage. Connect this pin to the +5V supply voltage.
—
—
VCC2
PWR Secondary Supply Voltage 2. This supply voltage connection is
provided to reduce power supply noise. Connection of this pin to the +5V
supply voltage is recommended. However, when using the 8XC251SB as
a pin-for-pin replacement for the 8XC51FX, VSS2 can be unconnected
without loss of compatibility. (Not available on DIP)
VSS
GND Circuit Ground. Connect this pin to ground.
—
—
VSS1
GND Secondary Ground. This ground is provided to reduce ground bounce
and improve power supply bypassing. Connection of this pin to ground is
recommended. However, when using the 8xC251TA/TB/TP/TQ as a pin-
for-pin replacement for the 8XC51BH, VSS1 can be unconnected without
loss of compatibility. (Not available on DIP)
VSS2
GND Secondary Ground 2. This ground is provided to reduce ground bounce
and improve power supply bypassing. Connection of this pin to ground is
recommended. However, when using the 8xC251TA/TB/TP/TQ as a pin-
for-pin replacement for the 8XC51FX, VSS2 can be unconnected without
loss of compatibility. (Not available on DIP)
—
ADVANCE INFORMATION
9
8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 6. Signal Descriptions (Sheet 3 of 3)
Signal
Name
Alternate
Function
Type
Description
WAIT#
I
Real-time Wait State Input. The real-time WAIT# input is enabled by
writing a logical ‘1’ to the WCON.0 (RTWE) bit at S:A7H. During bus
cycles, the external memory system can signal ‘system ready’ to the
microcontroller in real time by controlling the WAIT# input signal on the
port 1.6 input.
P1.6/CEX3
WCLK
O
Wait Clock Output. The real-time WCLK output is driven at port 1.7
(WCLK) by writing a logical ‘1’ to the WCON.1 (RTWCE) bit at S:A7H.
When enabled, the WCLK output produces a square wave signal with a
period of one-half the oscillator frequency.
P1.7/CEX4/
A17
WR#
O
I
Write. Write signal output to external memory.
P3.6
—
XTAL1
Input to the On-chip, Inverting, Oscillator Amplifier. To use the
internal oscillator, a crystal/resonator circuit is connected to this pin. If an
external oscillator is used, its output is connected to this pin. XTAL1 is the
clock source for internal timing.
XTAL2
O
Output of the On-chip, Inverting, Oscillator Amplifier. To use the
internal oscillator, a crystal/resonator circuit is connected to this pin. If an
external oscillator is used, leave XTAL2 unconnected.
—
NOTE:
The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration (compatible with 44-pin
PLCC and 40-pin DIP MCS 51 microcontrollers). If the chip is configured for page-mode operation, port 0 carries the lower
address bits (A7:0), and port 2 carries the upper address bits (A15:8) and the data (D7:0).
Table 7. Memory Signal Selections (RD1:0)
P1.7/CEX/
RD1:0
P3.7/RD#/A16
PSEN#
WR#
Features
A17/WCLK
0
0
1
0
1
0
A17
A16
Asserted for all Asserted for writes to 256-Kbyte external
addresses all memory locations memory
Asserted for all Asserted for writes to 128-Kbyte external
addresses all memory locations memory
Asserted for all Asserted for writes to 64-Kbyte external
P1.7/CEX4/
WCLK
A16
P1.7/CEX4/
WCLK
P3.7 only
addresses
all memory locations
memory. One
additional port pin.
1
1
P1.7/CEX4/
WCLK
RD# asserted
for addresses
≤ 7F:FFFFH
Asserted for
≥ 80:0000H
Asserted only for
writes to MCS 51
microcontroller data
memory locations.
64-Kbyte external
memory. Compatible
with MCS 51 micro-
controllers.
10
ADVANCE INFORMATION
8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 8. 8xC251TA/TB/TP/TQ Address Map
5.0 ADDRESS MAP
Internal
Address)
Description
Notes
FF:FFFFH
FF:4000H
1, 3, 10
External Memory except the top eight bytes (FF:FFF8H–FF:FFFFH) which are
reserved for the configuration array.
FF:3FFFH
FF:0000H
3, 4, 5
External memory or on-chip nonvolatile memory (8Kbytes FF:0000H - FF:1FFFH,
16Kbytes FF:0000H - FF:3FFFH).
FE:FFFFH
FE:0000H
3
External Memory
Reserved
FD:FFFFH
02:0000H
6
01:FFFFH
01:0000H
3
External Memory
00:FFFFH
00:E000H
5, 7
7
External memory or with configuration bit EMAP# = 0, addresses in this range
access on-chip code memory in region FF: (16 Kbyte devices only).
00:DFFFH
00:0420H
External Memory
00:041FH
00:0080H
7
On-chip RAM (512 bytes 00:0020H - 00:021FH, 1024 bytes 00:0020H - 00:041FH)
00:007FH
00:0020H
8
On-chip RAM
00:001FH
00:0000H
2, 9
Storage for R0–R7 of Register File
NOTES:
1. 18 address lines are bonded out (A15:0, A16:0, or A17:0 selected during chip configuration).
2. The special function registers (SFRs) and the register file have separate internal address spaces.
3. Data in this area is accessible by indirect addressing only.
4. Devices reset into internal or external starting locations depending on the state of EA# and configuration byte information
See EA#.
5. The 16-Kbyte ROM devices allow internal locations FF:2000H–FF:3FFFH to map into region 00:. In this case, if EA# = 1,
a data read to 00:E000H–00:FFFFH is redirected to internal ROM (see bit 1 in UCONFIG0). This is not available for 8-
Kbyte ROM devices.
6. This reserved area returns indeterminate values.
7. Data is accessible by direct and indirect addressing.
8. Data is accessible by direct, indirect, and bit addressing.
9. Data is accessible by direct, indirect, and register addressing.
10.Eight addresses at the top of all external memory maps are reserved for current and future device configuration byte
information.
ADVANCE INFORMATION
11
8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
6.0 ELECTRICAL CHARACTERISTICS
NOTICE:This document contains information on
ABSOLUTE MAXIMUM RATINGS
products being sampled or in the initial production
phase of development. Verify with your local Intel
sales office that you have the latest datasheet
before finalizing a design.
Storage Temperature .................................. -65°C to +150°C
Voltage: EA# Pin with respect to VSS ............. 0 V to +13.0 V
Voltage: Any other Pin with respect to VSS... -0.5 V to +6.5 V
IOL per I/O Pin...............................................................15 mA
Power Dissipation......................................................... 1.5 W
WARNING: Stressing the device beyond the
“Absolute Maximum Ratings” may cause
permanent damage. These are stress ratings only.
Operation beyond the “Operating Conditions” is not
recommended and extended exposure beyond the
“Operating Conditions” may affect device
reliability.
OPERATING CONDITIONS
TA (Ambient Temperature Under Bias):
Commercial ................................................. 0°C to +70°C
Express...........................................................-40°C to +85°C
VCC (Digital Supply Voltage) ............................ 4.5 V to 5.5 V
VSS ................................................................................... 0 V
NOTE:Maximum power dissipation is based on
package heat-transfer limitations, not device power
consumption.
6.1 D.C. Characteristics
Parameter values apply to all devices unless otherwise indicated.
Table 9. DC Characteristics at VCC = 4.5 – 5.5 V (Sheet 1 of 2)
Symbol
VIL
Parameter
Min
Typical
Max
Units
Test Conditions
Input Low Voltage
(except EA#)
-0.5
0.2 VCC – 0.1
V
VIL1
VIH
Input Low Voltage
(EA#)
0
0.2 VCC – 0.3
VCC + 0.5
V
V
V
V
Input High Voltage
(except XTAL1, RST)
0.2 VCC + 0.9
0.7 VCC
VIH1
VOL
Input High Voltage
(XTAL1, RST)
VCC + 0.5
Output Low Voltage
(Port 1, 2, 3)
0.3
0.45
1.0
I
OL = 100 µA
OL = 1.6 mA
OL = 3.5 mA
I
I
(Note 1, Note 2)
VOL1
Output Low Voltage
(Port 0, ALE, PSEN#)
0.3
0.45
1.0
V
V
I
I
I
OL = 200 µA
OL = 3.2 mA
OL = 7.0 mA
(Note 1, Note 2)
IOH = -10 µA
VOH
Output High Voltage
(Port 1, 2, 3, ALE,
PSEN#)
VCC – 0.3
VCC – 0.7
VCC – 1.5
I
OH = -30 µA
OH = -60 µA
I
(Note 3)
12
ADVANCE INFORMATION
8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 9. DC Characteristics at VCC = 4.5 – 5.5 V (Sheet 2 of 2)
Symbol
Parameter
Min
Typical
Max
Units
Test Conditions
VOH1
Output High Voltage
(Port 0 in External
Address)
VCC – 0.3
V
IOH = -200 µA
IOH = -3.2 mA
OH = -7.0 mA
V
CC – 0.7
CC – 1.5
I
V
VOH2
Output High Voltage
(Port 2 in External
Address during Page
Mode)
VCC – 0.3
V
IOH = -200 µA
IOH = -3.2 mA
OH = -7.0 mA
V
V
CC – 0.7
CC – 1.5
I
IIL
Logical 0 Input
Current (Port 1, 2, 3)
-50
+/-10
-650
µA
µA
µA
VIN = 0.45 V
0.45 < VIN < VCC
VIN = 2.0 V
ILI
ITL
Input Leakage
Current (Port 0)
Logical 1-to-0
Transition Current
(Port 1, 2, 3)
RRST
CIO
RST Pulldown
Resistor
40
225
kΩ
Pin Capacitance
10
(Note 4)
pF
FOSC = 24 MHz
TA = 25 °C
IPD
Powerdown Current
Idle Mode Current
Operating Current
10
(Note 4)
20
44
83
µA
mA
mA
IDL
35
(Note 4)
FOSC = 24 MHz
FOSC = 24 MHz
ICC
70
(Note 4)
NOTES:
1. Under steady-state (non-transient) conditions, IOL must be externally limited as follows:
•
•
Maximum IOL per port pin:10 mA
Maximum IOL per 8-bit port:
port 0
ports 1–3
26 mA
15 mA
•
Maximum Total IOL for
all output pins
71 mA
If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current
greater than the listed test conditions.
2. Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level outputs of ALE and
ports 1, 2, and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins
change from high to low. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may
exceed 0.8 V. It may be desirable to qualify ALE or other signals with a Schmitt trigger or CMOS-level input logic.
3. Capacitive loading on ports 0 and 2 causes the VOH on ALE and PSEN# to drop below the specification when the address
lines are stabilizing.
Typical values are obtained using VCC = 5.0, TA = 25°C and are not guaranteed.
ADVANCE INFORMATION
13
8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
6.2 Definition of AC Symbols
6.3 A.C. Characteristics
Test Conditions: Capacitive load on all pins = 50 pF.
Table 10. AC Timing Symbol Definitions
Table 11 lists AC timing parameters for the with no
wait states. External wait states can be added by
extending PSEN#/RD#/WR# and/or by extending
ALE. In the table, Notes 2 and 3 mark parameters
affected by an
Signals
Address
Data In
ALE
Conditions
High
A
D
L
H
L
Low
V
X
Z
Valid
Q
R
W
Data Out
RD#/PSEN#
WR#
No Longer Valid
Floating
ALE wait state, and Notes 4 and 5 mark parameters
affected by a PSEN#/RD#/WR# wait state.
Figure 6 through Figure 8 show the bus cycles with the timing parameters.
Table 11. AC Characteristics (Sheet 1 of 4)
@ Max FOSC (1)
FOSC Variable
Symbol
Parameter
Units
Min
N/A
N/A
Max
N/A
N/A
Min
Max
FOSC
TOSC
XTAL1 Frequency
0
24
MHz
ns
1/FOSC
@ 16MHz
@ 24MHz
62.5
41.7
TLHLL
ALE Pulse Width
@ 16MHz
@ 24MHz
ns (3)
ns (3)
55.5
34.7
(0.5+M)
2TOSC-7
TAVLL
Address Valid to ALE Low
@ 16MHz
@ 24MHz
49.5
28.7
(0.5+M)
2TOSC-13
TLLAX
Address Hold after ALE Low
@ 16MHz
@ 24MHz
ns (4)
ns (5)
10
10
10
20
TLLAXA
Address Hold after ALE Low
@ 16MHz
@ 24MHz
20
20
TRLRH
RD# or PSEN# Pulse Width
@ 16MHz
ns (3,4)
115
(1+N)
@ 24MHz
73.4
2TOSC-10
TRLRHA
TWLWH
TWLWHA
RD# or PSEN# Pulse Width
@ 16MHz
@ 24MHz
ns (3,5)
ns (3,4)
ns (3,5)
93
51.4
(1+N)
2TOSC-32
WR# Pulse Width
@ 16MHz
@ 24MHz
115
73.4
(1+N)
2TOSC-10
WR# Pulse Width
@ 16MHz
93
(1+N)
@ 24MHz
51.4
2TOSC-32
14
ADVANCE INFORMATION
8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 11. AC Characteristics (Sheet 2 of 4)
@ Max FOSC (1)
FOSC Variable
Symbol
TLLRL
Parameter
Units
Min
Max
Min
Max
ALE Low to RD# or PSEN#
ns (4)
Low
@ 16MHz
@ 24MHz
10
10
10
20
TLLRLA
ALE Low to RD# or PSEN#
Low
@ 16MHz
@ 24MHz
ns (5)
20
20
TLHAX
TLHAXA
TRLDV
ALE High to Address Hold
@ 16MHz
@ 24MHz
ns (3,4)
ns (3,5)
ns (3,4)
98
56.4
(1+M)
2TOSC-27
ALE High to Address Hold
@ 16MHz
@ 24MHz
77.5
56.7
(0.5+M)
2TOSC+15
RD# or PSEN# Low to Valid
Data/Instruction In
@ 16MHz
95
(1+N)
@ 24MHz
53.4
2TOSC-30
TRLDVA
RD# or PSEN# Low to Valid
Data/Instruction In
@ 16MHz
ns (3,5)
75
(1+N)
@ 24MHz
33.4
2TOSC-50
TRHDX
Data/Instruction Hold after
RD# or PSEN# High
@ 16MHz
ns
0
0
0
@ 24MHz
TRLAZ
RD#/PSEN# Low to
Address Float
@ 16MHz
ns
10
10
10
10
@ 24MHz
TRHDZ1
TRHDZ1A
TRHDZ2
TRHDZ2A
Instruction Float after
PSEN# or RD# high
@ 16MHz
ns (4)
ns (5)
ns (4)
ns (5)
10
10
@ 24MHz
Instruction Float after
PSEN# or RD# high
@ 16MHz
57.5
36.7
TOSC-5
@ 24MHz
Data Float after PSEN# or
RD# high
@ 16MHz
135
93.4
2TOSC+10
@ 24MHz
Data Float after PSEN# or
RD# high
@ 16MHz
@ 24MHz
182.5
120.1
3TOSC-5
ADVANCE INFORMATION
15
8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 11. AC Characteristics (Sheet 3 of 4)
@ Max FOSC (1)
FOSC Variable
Symbol
TRHLH2
Parameter
Units
Min
Max
Min
Max
RD# or PSEN# High to ALE
High (data)
ns (4)
@ 16MHz
135
2TOSC+10
@ 24MHz
93.4
TRHLH2A
RD# or PSEN# High to ALE
High (data)
@ 16MHz
ns (5)
ns (4)
ns (5)
180.5
118.1
3TOSC-7
@ 24MHz
TRHLH1
RD# or PSEN# High to ALE
High (Instruction)
@ 16MHz
10
10
10
@ 24MHz
TRHLH1A
RD# or PSEN# High to ALE
High (Instruction)
@ 16MHz
55.5
34.7
T
OSC-7
@ 24MHz
TWHLH
TWHLHA
TAVDV1
WR# High to ALE Low
@ 16MHz
@ 24MHz
ns (4)
ns (5)
135
93.4
2TOSC+10
3TOSC-7
WR# High to ALE Low
@ 16MHz
@ 24MHz
180.5
118.1
Address (mux’d) valid to
Valid Data/ Instruction In
@ 16MHz
ns (3,4)
190
106.8
(2+M+N)
2TOSC-60
@ 24MHz
TAVDV1A
TAVDV2
TAVDV3
TAVRL
Address (mux’d) valid to
Valid Data/ Instruction In
@ 16MHz
ns (3,4)
ns (3)
159.5
97.1
(1.5+M+N)
2TOSC-28
@ 24MHz
Address (demux’d) valid to
Valid Data/Instruction In
@ 16MHz
212
128.8
(2+M+N)
2TOSC-38
@ 24MHz
Address (P0)Valid to Valid
Instruction In
@ 16MHz
ns (3)
65
23.4
(1+N)
2TOSC-60
@ 24MHz
Address Valid to RD# or
PSEN# Low
@ 16MHz
ns (3,4)
ns (3,5)
85
43.4
(1+M)
2TOSC-40
@ 24MHz
TAVRLA
Address Valid to RD# or
PSEN# Low
@ 16MHz
@ 24MHz
72.5
51.7
(0.5+M)
2TOSC+10
16
ADVANCE INFORMATION
8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 11. AC Characteristics (Sheet 4 of 4)
@ Max FOSC (1)
FOSC Variable
Min Max
Symbol
TAVWL1
Parameter
Units
Min
Max
Address (mux’d) Valid to
WR# Low
ns (3,4)
@ 16MHz
85
(1+M)
@ 24MHz
43.4
2TOSC-40
TAVWL1A
Address (mux’d) Valid to
WR# Low
@ 16MHz
ns (3,5)
ns (3,4)
ns (3,5)
72.5
51.7
(0.5+M)
2TOSC+10
@ 24MHz
TAVWL2
Address (demux’d) Valid to
WR# Low
@ 16MHz
108
66.4
(1+M)
2TOSC-17
@ 24MHz
TAVWL2A
Address (demux’d) Valid to
WR# Low
@ 16MHz
135
(1+M)
@ 24MHz
93.4
2TOSC+10
TWHQX
Data Hold after WR# High
@ 16MHz
@ 24MHz
ns
49.5
28.7
T
OSC-13
TQVWH
Data Valid to WR# High
@ 16MHz
ns (3)
110
(1+N)
@ 24MHz
68.4
2TOSC-15
2TOSC-13
TWHAX
WR# High to Address Hold
@ 16MHz
ns
112
@ 24MHz
70.4
NOTES:
1. 24 MHz XTAL Frequency.
2. Specifications for PSEN# are identical to those for RD#.
3. In the formula, M = number of wait states (0 or 1) for ALE and N = Number of wait states (0,1,2 or 3) for
RD#/PSEN#/WR#.
4. Device configured with the default data float timing for fast memory interface (EDF# = 1).
5. Device configured with extended data float timing for slow memory interface (EDF# = 0).
ADVANCE INFORMATION
17
8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
6.3.1 External Bus Cycles, Nonpage Mode
T
OSC
XTAL1
ALE
†
T
LHLL
†
T
RLRH
T
RHLH1
†
T
LLRL
RD#/PSEN#
†
T
RLDV
T
RLAZ
†
T
LHAX
T
RHDZ1
†
T
T
LLAX
AVLL
T
RHDX
P0
A7:0
D7:0
†
Instruction In
T
AVRL
†
T
T
AVDV1
†
AVDV2
P2/A16/A17
A15:8/A16/A17
†
The value of this parameter depends on wait states. See the table of AC characteristics.
A4211-03
Figure 5. External Bus Cycle: Code Fetch (Nonpage Mode)
18
ADVANCE INFORMATION
8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
T
OSC
XTAL1
ALE
†
T
LHLL
†
T
RLRH
†
T
T
RHLH2
LLRL
RD#/PSEN#
†
T
RLDV
T
RLAZ
†
T
LHAX
T
RHDZ2
†
T
AVLL
T
LLAX
T
RHDX
D7:0
P0
A7:0
†
Data In
T
AVRL
†
T
AVDV1
†
T
AVDV2
A15:8/A16/A17
P2/A16/A17
†
The value of this parameter depends on wait states. See the table of AC characteristics.
A4210-03
Figure 6. External Bus Cycle: Data Read (Nonpage Mode)
ADVANCE INFORMATION
19
8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
T
OSC
XTAL1
†
ALE
T
LHLL
†
T
WLWH
T
WHLH
WR#
†
T
LHAX
†
T
QVWH
T
T
AVLL
LLAX
T
WHQX
P0
A7:0
D7:0
†
Data Out
T
AVWL1
†
T
T
AVWL2
WHAX
P2/A16/A17
A15:8/A16/A17
†
The value of this parameter depends on wait states. See the table of AC characteristics.
A4179-01
Figure 7. External Bus Cycle: Data Write (Nonpage Mode)
20
ADVANCE INFORMATION
8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
6.3.2 External Bus Cycles, Page Mode
T
OSC
XTAL1
ALE
†
T
LHLL
†
T
LLRL
†††
RD#/PSEN#
†
T
RLDV
T
RLAZ
†
T
T
RHDZ1
T
LHAX
†
T
AVLL
T
RHDX
LLAX
P2
A15:8
D7:0
D7:0
†
Instruction In
Instruction In
T
AVRL
†
T
T
AVDV3
AVDV1
†
T
AVDV2
P0/A16/A17
A7:0/A16/A17
A7:0/A16/A17
††
††
Page Miss
Page Hit
†
The value of this parameter depends on wait states. See the table of AC characteristics.
A page hit (i.e., a code fetch to the same 256-byte "page" as the previous code fetch) requires one
state (2TOSC); a page miss requires two states (4TOSC).
††
†††
During a sequence of page hits, PSEN# remains low until the end of the last page-hit cycle.
A4213-02
Figure 8. External Bus Cycle: Code Fetch (Page Mode)
ADVANCE INFORMATION
21
8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
T
OSC
XTAL1
ALE
†
T
LHLL
†
T
RLRH
†
T
T
RHLH2
LLRL
RD#/PSEN#
†
T
RLDV
T
RLAZ
†
T
LHAX
T
RHDZ2
†
T
AVLL
T
LLAX
T
RHDX
D7:0
P2
A15:8
†
Data In
T
AVRL
†
T
AVDV1
†
T
AVDV2
A7:0/A16/A17
P0/A16/A17
†
The value of this parameter depends on wait states. See the table of AC characteristics.
A4212-03
Figure 9. External Bus Cycle: Data Read (Page Mode)
22
ADVANCE INFORMATION
8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
T
OSC
XTAL1
ALE
†
T
LHLL
†
T
WLWH
T
WHLH
WR#
†
T
LHAX
†
T
T
QVWH
AVLL
T
LLAX
T
WHQX
P2
A15:8
D7:0
†
Data Out
T
AVWL1
†
T
T
AVWL2
WHAX
P0/A16/A17
A7:0/A16/A17
†
The value of this parameter depends on wait states. See the table of AC characteristics.
A4182-01
Figure 10. External Bus Cycle: Data Write (Page Mode)
ADVANCE INFORMATION
23
8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
6.3.3 Definition of Real-Time Wait Symbols
Table 12. Real-time Wait Timing Symbol Definitions
Signals
Address
Data
Conditions
Low
A
L
D
C
Y
X
V
Hold
WCLK
Setup
WAIT#
WR#
W
R
RD#/PSEN#
6.3.4 External Bus Cycles, Real-Time Wait States
State 1
State 2
State 3
State 1 (next cycle)
WCLK
TCLYX min
TCLYX max
ALE
TCLYV
RD#/PSEN#
RD#/PSEN#
stretched
TRLYX max
T
RLYX min
TRLYV
WAIT#
P0
A7:0
D7:0
stretched
stretched
A7:0
P2
A15:8
A15:8
A5000-02
Figure 11. External Bus Cycle: Code Fetch/Data Read (Nonpage Mode)
24
ADVANCE INFORMATION
8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
State 1
State 2
State 3
State 4
WCLK
TCLYX min
ALE
TCLYX max
TCLYV
WR#
WR# stretched
TWLYX max
T
WLYX min
TWLYV
WAIT#
P0
D7:0
A7:0
stretched
stretched
P2
A15:8
A5002-02
Figure 12. External Bus Cycle: Data Write (Nonpage Mode)
ADVANCE INFORMATION
25
8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
State 1
State 2
State 3
State 1 (next cycle)
WCLK
TCLYX min
TCLYX max
ALE
TCLYV
RD#/PSEN#
RD#/PSEN# stretched
TRLYX max
T
RLYX min
TRLYV
WAIT#
P2
A15:8
D7:0
stretched
stretched
A15:8
P0
A7:0
A7:0
A5001-02
Figure 13. External Bus Cycle: Code Fetch/Data Read (Page Mode)
26
ADVANCE INFORMATION
8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
State 1
State 2
State 3
State 4
WCLK
TCLYX min
ALE
TCLYX max
TCLYV
WR#
WR# stretched
TWLYX max
T
WLYX min
TWLYV
WAIT#
P2
A15:8
D7:0
stretched
stretched
P0
A7:0
A5003-02
Figure 14. External Bus Cycle: Data Write (Page Mode)
Table 13. Real-Time Wait AC Timing
Symbol
Parameter
Min
Max
Units
TCLYV
Wait Clock Low to Wait Set-up
Wait Hold after Wait Clock Low
PSEN#/RD# Low to Wait Set-up
PSEN#/RD# Low to Wait Set-up
Wait Hold after PSEN#/RD# Low
WR# Low to Wait Set-up
0
TOSC – 13
ns
TCLYX
(2W)TOSC + 5 (1+2W)TOSC – 20
ns (1)
ns
TRLYV
0
0
TOSC – 13
TOSC – 35
TRLYVA
TRLYX
ns (2)
ns (1)
ns
(2W)TOSC + 5 (1+2W)TOSC – 20
TWLYV
TWLYVA
TWLYX
NOTES:
0
0
TOSC – 13
TOSC – 35
WR# Low to Wait Set-up
ns (2)
ns (1)
Wait Hold after WR# Low
(2W)TOSC + 5 (1+2W)TOSC – 20
1. W = 0, 1, 2 — is the number of real time wait states.
2. Device configured with the extended data float timing.
ADVANCE INFORMATION
27
8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
6.4 AC Characteristics — Serial Port, Shift Register Mode
Table 14. Serial Port Timing — Shift Register Mode
Symbol
Parameter
Min
Max
Units
TXLXL
Serial Port Clock Cycle Time
12TOSC
ns
TQVSH
Output Data Setup to Clock Rising Edge
10TOSC – 133
2TOSC – 117
0
ns
ns
TXHQX
Output Data hold after Clock Rising Edge
TXHDX
TXHDV
Input Data Hold after Clock Rising Edge
Clock Rising Edge to Input Data Valid
ns
ns
10TOSC – 133
T
XLXL
TXD
T
XHQX
†
†
Set TI
T
QVXH
RXD
(Out)
0
1
2
7
4
6
3
5
†
T
AV
T
T
XHDV
XHDX
Set RI
RXD
(In)
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
†
TI and RI are set during S1P1 of the peripheral cycle following the shift of the eighth bit.
A2592-02
Figure 15. Serial Port Waveform — Shift Register Mode
28
ADVANCE INFORMATION
8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
6.5 External Clock Drive
Table 15. External Clock Drive
Symbol
Parameter
Min
Max
Units
1/TCLCL
Oscillator Frequency (FOSC
High Time
)
24
MHz
TCHCX
TCLCX
TCLCH
TCHCL
20
20
ns
ns
ns
ns
Low Time
Rise Time
10
10
Fall Time
TCLCH
TCHCX
VCC – 0.5
0.45 V
0.7 VCC
TCLCX
0.2 VCC – 0.1
TCHCL
TCLCL
A4119-01
Figure 16. External Clock Drive Waveforms
Outputs
Inputs
VCC – 0.5
0.45 V
0.2 VCC + 0.9
0.2 VCC – 0.1
VIH MIN
VOL MAX
AC inputs during testing are driven at VCC – 0.5V for a logic 1
and 0.45 V for a logic 0. Timing measurements are made at
a min of VIH for a logic 1 and VOL for a logic 0.
A4118-01
Figure 17. AC Testing Input, Output Waveforms
ADVANCE INFORMATION
29
8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
VLOAD + 0.1 V
VOH – 0.1 V
Timing Reference
Points
VLOAD
VLOAD – 0.1 V
VOL + 0.1 V
For timing purposes, a port pin is no longer floating when a
100 mV change from load voltage occurs and begins to float
when a 100 mV change from the loading VOH/VOL level occurs
with IOL/IOH = ± 20 mA.
A4117-01
Figure 18. Float Waveforms
7.0 THERMAL CHARACTERISTICS
All thermal impedance data is approximate for static
air conditions at 1 watt of power dissipation. Values
change depending on operating conditions and
application requirements. The Intel Packaging
Handbook (order number 240800) describes Intel’s
thermal impedance test methodology.
Table 16. Thermal Characteristics
Package Type
44-pin PLCC
ΘJA
ΘJC
46°C/W
45°C/W
16°C/W
16°C/W
40-pin PDIP
30
ADVANCE INFORMATION
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