S80C198 [INTEL]
COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER; 商业/ EXPRESS CHMOS单片机
| 型号： | S80C198 |
| 厂家： | 
INTEL |
| 描述： | COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER |
| 文件： | 总19页 (文件大小：277K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8XC198
COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER
8 Kbytes of OTPROM
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
8 Kbytes of On-Chip OTPROM or ROM
232 Byte Register File
16 MHz Standard
Y
Y
Y
Y
Y
Y
Y
Y
Full Duplex Serial Port
Register-to-Register Architecture
28 Interrupt Sources/16 Vectors
1.75 ms 16 x 16 Multiply (16 MHz)
3.0 ms 32/16 Divide (16 MHz)
Powerdown and Idle Modes
16-Bit Watchdog Timer
High Speed I/O Subsystem
16-Bit Timer
16-Bit Counter
Pulse-Width-Modulated Output
Four 16-Bit Software Timers
10-Bit A/D Converter with Sample/Hold
Extended Temperature Available
8-Bit External Bus
The 8XC198 family offers low-cost entry into Intel’s powerful MCS -96 16-bit microcontroller architecture.
É
Intel’s CHMOS process provides a high performance processor along with low power consumption. To further
reduce power requirements, the processor can be placed into Idle or Powerdown Mode.
The 8XC198 is the 8-bit bus version of the 8XC196KB. The prefixes mean: 80 (ROMless), 83 (ROM), 87 (OTP)
One Time Programmable. The ROM and OTP are available in 8 Kbytes.
Bit, byte, word and some 32-bit operations are available on the 8XC198. With a 16 MHz oscillator a 16-bit
addition takes 0.50 ms, and the instruction times average 0.37 ms to 1.1 ms in typical applications.
Four high-speed capture inputs are provided to record times when events occur. Six high-speed outputs are
available for pulse or waveform generation. The high-speed output can also generate four software timers or
start an A/D conversion. Events can be based on the timer or counter. Also provided on-chip are an A/D
converter, serial port, watchdog timer and a pulse-width-modulated output signal.
With the commercial (standard) temperature option, operational characteristics are guaranteed over the tem-
a
perature range of 0 C to 70 C. Wth the extended temperature range option, operational characteristics are
guaranteed over the temperature range of 40 C to 85 C.
§
§
b
a
§
§
MCS -96 is a registered trademark of Intel Corporation.
É
*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
©
COPYRIGHT INTEL CORPORATION, 1995
October 1992
Order Number: 272034-003
8XC198
272034–1
Figure 1. 87C198 Block Diagram
0FFFFH
4000H
EXTERNAL MEMORY OR I/O
INTERNAL ROM/EPROM OR
EXTERNAL MEMORY
2080H
2040H
2030H
2020H
2019H
2018H
2014H
RESERVED
UPPER 8 INTERRUPT VECTORS
ROM/OTP SECURITY KEY
RESERVED
CHIP CONFIGURATION BYTE
RESERVED
272034–7
LOWER 8 INTERRUPT VECTORS
PLUS 2 SPECIAL INTERRUPTS
Figure 3. Chip Configuration (2018H)
2000H
1FFEH
0100H
PORT 3 AND PORT 4
EXTERNAL MEMORY OR I/O
INTERNAL DATA MEMORY - REGISTER FILE
(STACK POINTER, RAM AND SFRS)
EXTERNAL PROGRAM CODE MEMORY
0000H
Figure 2. Memory Map
WARNING:
Reserved memory locations must not be written or read. The contents and/or function of these locations may change with
future revisions of the device. Therefore, a program that relies on one or more of these locations may not function properly.
2
8XC198
PACKAGING
The 8XC198 is available in a 52-pin PLCC package and an 80-pin QFP package. Contact your local sales
office to determine the exact ordering code for the part desired.
Package Designators:
e
e
N
S
52-pin PLCC
80-pin QFP
Thermal Characteristics
Package Type
PLCC
i
i
jc
ja
40 C/W
§
70 C/W
QFP
4 C/W
§
§
All thermal impedance data is approximate for static air conditions at 1W of power dissipation. Values will
change depending on operating conditions and application. See the IntelPackaging Handbook (Order Number
240800) for a description of Intel’s thermal impedance test methodology.
272034–2
Figure 4. 52-Pin PLCC Package
NOTE:
The above pinout diagram applies to the OTP (87C198) device. The OTP device uses all of the programming pins shown
above. The ROM (83C198) device only uses programming pins: AINC, PALE, PMODE.n and PROG. The ROMless (80C198)
doesn’t use any of the programming pins.
3
8XC198
272034–4
NOTE:
N.C. means No Connect (do not connect these pins).
Figure 5. 80-Pin QFP Package
NOTE:
The above pinout diagram applies to the OTP (87C198) device. The OTP device uses all of the programming pins shown
above. The ROM (83C198) device only uses programming pins: AINC, PALE, PMODE.n and PROG. The ROMless (80C198)
doesn’t use any of the programming pins.
4
8XC198
PIN DESCRIPTIONS
Symbol
Name and Function
V
V
Main supply voltage (5V).
CC
The PLCC package has 5 V pins and the QFP package has 12 V pins. All must be
SS SS
connected to digital ground.
SS
V
REF
Reference voltage for the A/D converter (5V). V
is also the supply voltage to the
REF
analog portion of the A/D converter and the logic used to read Port 0. Must be
connected for A/D and Port 0 to function.
ANGND
Reference ground for the A/D converter. Must be held at nominally the same potential
.
as V
SS
V
Programming Voltage. Also, timing pin for the return from powerdown circuit.
Input of the oscillator inverter and of the internal clock generator.
Output of the oscillator inverter.
PP
XTAL1
XTAL2
RESET
Reset input to and open-drain output from the chip. Input low for at least 4 state times to
reset the chip. The subsequent low-to-high transition commences the 10-state Reset
Sequence.
INST
EA
Output high during an external memory read indicates the read is an instruction fetch.
INST is valid throughout the bus cycle. INST is activated only during external memory
accesses and output low for a data fetch.
Input for memory select (External Access). EA equal to a TTL-high causes memory
accesses to locations 2000H through 3FFFH to be directed to on-chip ROM/EPROM.
EA equal to a TTL-low causes accesses to these locations to be directed to off-chip
memory.
ALE/ADV
RD
Address Latch Enable or Address Valid output, as selected by CCR. Both pin options
provide a latch to demultiplex the address from the address/data bus. When the pin is
ADV, it goes inactive high at the end of the bus cycle. ALE/ADV is activated only during
external memory accesses.
Read signal output to external memory. RD is activated only during external memory
reads.
WR
Write output to external memory. WR will go low for every external write.
READY
Ready input to lengthen external memory cycles. When the external memory is not
being used, READY has no effect. Internal control of the number of wait states inserted
into a bus cycle held not ready is available through configuration of CCR.
HSI
Inputs to High Speed Input Unit. Four HSI pins are available: HSI.0, HSI.1, HSI.2 and
HSI.3. Two of them (HSI.2 and HSI.3) are shared with the HSO Unit.
HSO
Outputs from High Speed Output Unit. Six HSO pins are available: HSO.0, HSO.1,
HSO.2, HSO.3, HSO.4 and HSO.5. Two of them (HSO.4 and HSO.5) are shared with the
HSI Unit.
Port 0
4-bit high impedance input-only port. These pins can be used as digital inputs and/or as
analog inputs to the on-chip A/D converter. These pins set the Programming Mode on
the EPROM device.
5
8XC198
PIN DESCRIPTIONS (Continued)
Symbol
Name and Function
Port 2
Multi-functional port. All of its pins are shared with other functions in the 80C198.
Ports 3 and 4
8-bit bidirectional I/O ports with open drain outputs. These pins are shared with
the multiplexed address/data bus which has strong internal pullups. Available as
I/O only on the ROM and EPROM devices.
TxD
RxD
The TxD pin is used for serial port transmission in Modes 1, 2 and 3. In mode 0 the
pin is used as the serial clock output.
Serial Port Receive pin used for serial port reception. In mode 0 the pin functions
as input or output data.
EXTINT
T2CLK
A positive transition on the EXTINT pin will generate an external interrupt.
The T2CLK pin is the Timer2 clock input or the serial port baud rate generator
input.
T2RST
PWM
A rising edge on the T2RST pin will reset Timer2.
The PWM output.
PMODE
Programming Mode Select. Determines the EPROM programming algorithm that is
performed. PMODE is sampled after a chip reset and should be static while the
part is operating.
SID
Slave ID Number. Used to assign each slave a pin of Port 3 or 4 to use for passing
programming verification acknowledgement.
PALE
Programming ALE Input. Accepted by the 87C196KB when it is in Slave
Programming Mode. Used to indicate that Ports 3 and 4 contain a command/
address.
PROG
PVAL
PVER
Programming. Falling edge indicates valid data on PBUS and the beginning of
programming. Rising edge indicates end of programming.
Program Valid. This signal indicates the success or failure of programming in the
Auto Programming Mode. A zero indicates successful programming.
Program Verification. Used in Slave Programming and Auto CLB Programming
Modes. Signal is low after rising edge of PROG if the programming was not
successful.
AINC
Auto Increment. Active low signal indicates that the auto increment mode is
enabled. Auto Increment will allow reading or writing of sequential EPROM
locations without address transactions across the PBUS for each read or write.
PORTS 3 and 4
(when programming)
Address/Command/Data Bus. Used to pass commands, addresses, and data to
and from slave mode 87C196KBs. Used by chips in Auto Programming Mode to
pass command, addresses and data to slaves. Also used in the Auto Programming
Mode as a regular system bus to access external memory. Should have pullups to
V
(15 kX).
CC
6
8XC198
ELECTRICAL CHARACTERISTICS
NOTICE: This data sheet contains preliminary infor-
mation on new products in production. It is valid for
the devices indicated in the revision history. The
specifications are subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature
under BiasÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 55 C to 125 C
*WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and ex-
tended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.
b
a
§
§
b
a
Storage Temperature ÀÀÀÀÀÀÀÀÀÀ 65 C to 150 C
§
§
Voltage on V or EA to
V
PP
or ANGND ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 0.3V to 13.0V
b a
SS
b a
ÀÀ 0.5V to 7.0V
Voltage on Any Other Pin to V
(1)
SS
Power Dissipation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5W
NOTE:
1. Power dissipation is based on package heat transfer lim-
itations, not device power consumption.
OPERATING CONDITIONS
(All characteristics in this data sheet apply to these operating conditions unless otherwise noted.)
Symbol
Description
Min
0
Max
Units
a
T
A
Ambient Temperature Under Bias
Digital Supply Voltage
70
C
§
V
V
4.50
4.50
3.5
5.50
5.50
16
V
V
CC
Analog Supply Voltage
REF
OSC
F
Oscillator Frequency 16 MHz
MHz
NOTE:
ANGND and V should be nominally at the same potential.
SS
DC CHARACTERISTICS
Symbol
Description
Input Low Voltage
Min
Max
0.8
a
Units
Test Conditions
b
V
V
V
V
V
0.5
V
V
V
V
IL
(1)
a
Input High Voltage
0.2 V
0.9
V
V
V
0.5
0.5
0.5
IH
CC
CC
a
a
Input High Voltage on XTAL1
Input High Voltage on RESET
Output Low Voltage
0.7 V
CC
IH1
IH2
OL
CC
CC
2.6
e
e
e
0.3
0.45
1.5
V
V
V
I
I
I
200 mA
32 mA
7 mA
OL
OL
OL
b
b
b
e b
e b
e b
V
Output High Voltage
(Standard Outputs)
V
V
V
0.3
0.7
1.5
V
V
V
I
I
I
200 mA
3.2 mA
7 mA
OH
CC
OH
OH
OH
k
CC
CC
k
b
0.3V
g
I
I
I
Input Leakage Current (Std. Inputs)
Input Leakage Current (Port 0)
10
mA
mA
mA
0
0
V
V
IN
V
IN
V
V
LI
CC
k
k
a
3
6
LI1
IL1
REF
b
e
0.45 V
Logical 0 Input Current in Reset
(ALE, RD, INST)
IN
Hyst
Hysteresis on RESET Pin
300
mV
NOTE:
1. All pins except RESET and XTAL1.
7
8XC198
DC CHARACTERISTICS (Continued)
(6)
Symbol
Description
Active Mode Current in Reset
A/D Converter Reference Current
Idle Mode Current
Min Typ
Max Units
Test Conditions
e
16 MHz
I
I
I
I
I
50
2
60
5
mA
mA
mA
mA
mA
X
XTAL1
e
CC
e
e
V
V
PP
V
REF
5.5V
5.5V
CC
REF
IDLE
CC1
PD
10
15
5
25
25
30
50K
10
e
3.5 MHz
Active Mode Current
XTAL1
e
e
V
e
Powerdown Mode Current
Reset Pullup Resistor
V
CC
V
PP
REF
R
RST
6K
e
C
S
Pin Capacitance (Any Pin to V
)
SS
pF
F
1.0 MHz
TEST
NOTES:
(Notes apply to all specifications)
1. Standard Outputs include AD0–15, RD, WR, ALE, INST, HSO pins, PWM/P2.5, RESET, Ports 3 and 4, TXD/P2.0 and
RXD (in serial mode 0). The V specification is not valid for RESET. Ports 3 and 4 are open-drain outputs.
OH
2. Standard Inputs include HSI pins, EA, READY, RXD/P2.1, EXTINT/P2.2, T2CLK/P2.3 and T2RST/P2.4.
3. Maximum current per pin must be externally limited to the following values if V is held above 0.45V or V
is held
OL OH
b
on Output pins: 10 mA
on Standard Output pins: 10 mA
below V
0.7V:
CC
I
I
OL
OH
g
4. Maximum current per bus pin (data and control) during normal operation is 3.2 mA.
5. During normal (non-transient) conditions the following total current limits apply:
HSO, P2.0, RXD, RESET
P2.5, WR
AD0–AD15
I : 29 mA
OL
I : 13 mA
OL
I : 52 mA
OL
I : 13 mA
OL
I : 26 mA
OH
I : 11 mA
OH
I : 52 mA
OH
I : 13 mA
OH
RD, ALE, INST
6. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature
e
e
and V
V
CC
5V.
REF
e
Max
c
a
FREQ
I
I
Max
3.88
e
CC
c
a
FREQ 2.2
1.65
272034–22
IDLE
Figure 8. I and I
CC
vs Frequency
IDLE
8
8XC198
AC CHARACTERISTICS
Test Conditions: Capacitive load on all pins
e
e
e
12/16 MHz
OSC
100 pF, Rise and fall times
10 ns, F
The system must meet these specifications to work with the 87C198:
Symbol
Description
Min
Max
Units
ns
Notes
b
OSC
T
T
T
T
T
T
T
Address Valid to Ready Setup
Non READY Time
2 T
75
AVYV
YLYH
LLYX
AVDV
RLDV
RHDZ
RXDX
No upper limit
ns
b
b
b
READY Hold after ALE Low
Address Valid to Input Data Valid
RD Active to Input Data Valid
End of RD to Input Data Float
Data Hold after RD Inactive
T
15
2 T
40
55
ns
(Note 1)
(Note 2)
(Note 2)
OSC
OSC
OSC
3 T
ns
b
T
T
23
ns
OSC
OSC
b
20
ns
0
ns
NOTES:
1. If max is exceeded, additional wait states will occur.
c
e
2. When using wait states, add 2 T
n, where n
number of wait states.
OSC
9
8XC198
AC CHARACTERISTICS
Test Conditions: Capacitive load on all pins
e
e
e
12/16 MHz
OSC
100 pF, Rise and fall times
10 ns, F
The 87C198 will meet these specifications:
Symbol
Description
Min
3.5
Max
12
Units
MHz
MHz
ns
Notes
(Note 1)
(Note 1)
F
F
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
Frequency on XTAL1 12 MHz
Frequency on XTAL1 16 MHz
XTAL
XTAL
OSC
3.5
16
1/F
1/F
12 MHz
16 MHz
83.3
62.5
286
286
XTAL
XTAL
ns
OSC
ALE Cycle Time
4 T
ns
(Note 3)
LHLH
LHLL
OSC
b
b
b
b
a
ALE High Period
T
T
T
T
10
T
10
ns
OSC
OSC
OSC
OSC
OSC
Address Setup to ALE Falling Edge
Address Hold after ALE Falling Edge
ALE Falling Edge to RD Falling Edge
RD Low Period
20
40
35
5
ns
AVLL
LLAX
LLRL
ns
ns
b
a
a
T
T
T
25
25
ns
(Note 3)
(Note 2)
RLRH
RHLH
RLAZ
LLWL
QVWH
WLWH
WHQX
WHLH
WHBX
LLBX
RHBX
WHAX
RHAX
OSC
OSC
OSC
RD Rising Edge to ALE Rising Edge
RD Low to Address Float
T
ns
OSC
5
ns
b
ALE Falling Edge to WR Falling Edge
Data Stable to WR Rising Edge
WR Low Period
T
T
T
T
T
T
T
T
T
T
10
23
15
15
15
15
10
10
30
25
ns
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
b
b
b
b
b
b
b
b
b
ns
(Note 3)
(Note 3)
a
T
5
ns
OSC
Data Hold after WR Rising Edge
WR Rising Edge to ALE Rising Edge
INST Hold after WR Rising Edge
INST Hold after ALE Rising Edge
INST Hold after RD Rising Edge
AD8–15 Hold after WR Rising Edge
AD8–15 Hold after RD Rising Edge
ns
a
T
10
ns
(Note 2)
OSC
ns
ns
ns
ns
ns
NOTES:
1. Testing performed at 3.5 MHz. However, the part is static by design and will typically operate below 1 Hz.
2. Assuming back-to-back bus cycles.
c
e
3. When using wait states, add 2 T
n, where n
number of wait states.
OSC
10
8XC198
System Bus Timings
272034–23
11
8XC198
READY Timings (One Wait State)
272034–24
EXTERNAL CLOCK DRIVE
Symbol
Parameter
Oscillator Frequency 12 MHz
Oscillator Frequency 16 MHz
Oscillator Period 12 MHz
Oscillator Period 16 MHz
High Time
Min
3.5
Max
12.0
16.0
286
286
Units
MHz
MHz
ns
1/T
1/T
XLXL
XLXL
3.5
T
T
T
T
T
T
83.3
62.5
21.25
21.25
XLXL
ns
XLXL
XHXX
XLXX
XLXH
XHXL
ns
Low Time
ns
Rise Time
10
10
ns
Fall Time
ns
EXTERNAL CLOCK DRIVE WAVEFORMS
272034–25
An external oscillator may encounter as much as a 100 pF load at XTAL1 when it starts-up. This is due to
interaction between the amplifier and its feedback capacitance. Once the external signal meets the V and
IL
V
IH
specifications the capacitance will not exceed 20 pF.
12
8XC198
EXTERNAL CRYSTAL CONNECTIONS
EXTERNAL CLOCK CONNECTIONS
272034–32
272034–33
NOTE:
Keep oscillator components close to chip and use
short direct traces to XTAL1, XTAL2 and V . When
SS
NOTE:
*Required if open collector TTL driver used. Not need-
ed if CMOS driver is used.
e
e
20 pF. When using
using crystals, C1
20 pF, C2
ceramic resonators consult manufacturer for recom-
mended capacitor values.
AC TESTING INPUT, OUTPUT WAVEFORMS
FLOAT WAVEFORMS
272034–26
AC Testing inputs are driven at 2.4V for a Logic ‘‘1’’ and 0.45V for
a Logic ‘‘0’’ Timing measurements are made at 2.0V for a Logic
‘‘1’’ and 0.8V for a Logic ‘‘0’’.
272034–27
For Timing Purposes a Port Pin is no Longer Floating when a
200 mV change from Load Voltage Occurs and Begins to Float
when a 200 mV change from the Loaded V /V Level occurs
OH OL
e
g
15 mA.
I
/I
OL OH
EXPLANATION OF AC SYMBOLS
Each symbol is two pairs of letters prefixed by ‘‘T’’ for time. The characters in a pair indicate a signal and its
condition, respectively. Symbols represent the time between the two signal/condition points.
Conditions:
Signals:
H
L
- High
A
D
L
- Address
- Low
- DATA IN
- ALE/ADV
- DATA OUT
- RD
V
X
Z
- Valid
- No Longer Valid
- Floating
Q
R
W
X
- WR
- XTAL1
- READY
Y
13
8XC198
State times are calculated as follows:
2
state time
10-BIT AID CHARACTERISTICS
At a clock speed of 6 MHz or less, the clock prescal-
er should be disabled. This is accomplished by set-
e
f
XTAL1
e
ting IOC2.4
1.
The converter is ratiometric, so the absolute accura-
cy is directly dependent on the accuracy and stability
At higher frequencies (greater than 6 MHz) the clock
e
of V
. V
must be close to V since it supplies
prescaler should be turned on (IOC2.4
the comparator to settle.
0) to allow
REF REF CC
both the resistor ladder and the digital section of the
converter.
The table below shows two different clock speeds
and their corresponding A/D conversion and sample
times.
See the MCS-96 A/D Converter Quick Reference
for definition of A/D terms.
Example Sample and Conversion Times
Sample Time
at Clock
Speed (ms)
Conversion
Time
(States)
Conversion
Time at Clock
Speed (ms)
AID Clock
Prescaler
Clock Speed
(MHz)
Sample Time
(States)
e
IOC2.4
IOC2.4
0
1
x
x
ON
16
6
15
8
1.875
2.667
156.5
89.5
19.6
29.8
e
OFF
A/D CONVERTER SPECIFICATIONS
Parameter
Resolution
Typical(1)
Minimum
Maximum
Units*
Notes
1024
10
1024
10
Levels
Bits
g
Absolute Error
0
3
LSBs
LSBs
LSBs
LSBs
LSBs
LSBs
LSBs
g
0.25 0.50
Full Scale Error
b
g
0.25 0.50
Zero Offset Error
g
1.5 2.5
g
a
Non-Linearity Error
Differential Non-Linearity Error
Channel-to-Channel Matching
Repeatability
0
3
2
1
l
b
1
g
g
0.1
0
g
0.25
Temperature Coefficients:
Offset
Full Scale
0.009
0.009
0.009
LSB/ C
§
LSB/ C
§
Differential Non-Linearity
LSB/ C
§
b
Off Isolation
Feedthrough
60
dB
dB
dB
X
2, 3
2
b
b
60
60
V
Power Supply Rejection
2
CC
Input Series Resistance
DC Input Leakage
750
0
1.2K
3.0
4
mA
Sample Time: Prescaler On
Prescaler Off
15
8
States
States
Sampling Capacitor
3
pF
NOTES:
*An ‘‘LSB’’, as used here, has a value of approximately 5 mV.
1. Typical values are expected for most devices at 25 C but are not tested or guaranteed.
§
2. DC to 100 KHz.
3. Multiplexer Break-Before-Make Guaranteed.
4. Resistance from device pin, through internal MUX, to sample capacitor.
14
8XC198
EPROM SPECIFICATIONS
EPROM PROGRAMMING OPERATING CONDITIONS
Symbol
Parameter
Min
20
Max
30
Units
T
Ambient Temperature during Programming
Supply Voltages during Programming
Programming Mode Supply Voltage
EPROM Programming Supply Voltage
Digital and Analog Ground
C
§
A
(1)
V
V
V
V
, V , V
CC PD REF
4.5
5.5
13.0
13.0
0
V
(2)
V
12.50
12.50
0
EA
PP
(2)
V
,
V
SS
(3)
ANGND
F
Oscillator Frequency 16 MHz
6.0
16.0
MHz
OSC
NOTES:
1. V , V and V
CC PD
should nominally be at the same voltage during programming.
2. V and V must never exceed the maximum voltage for any amount of time or the device may be damaged.
REF
EA PP
3. V and ANGND should nominally be at the same voltage (0V) during programming.
SS
AC EPROM PROGRAMMING CHARACTERISTICS
Symbol
Description
Reset High to First PALE Low
PALE Pulse Width
Min
1100
40
Max
Units
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
SHLL
LLLH
AVLL
LLAX
LLVL
PLDV
PHDX
DVPL
PLDX
PLPH
PHLL
LHPL
PHPL
PHIL
Address Setup Time
0
Address Hold Time
50
PALE Low to PVER Low
PROG Low to Word Dump Valid
Word Dump Data Hold
Data Setup Time
60
50
50
0
Data Hold Time
50
PROG Pulse Width
40
PROG High to Next PALE Low
PALE High to PROG Low
PROG High to Next PROG Low
PROG High to AINC Low
AINC Pulse Width
120
220
120
0
40
ILIH
PVER Hold after AINC Low
AINC Low to PROG Low
PROG High to PVER Low
50
ILVH
ILPL
170
90
PHVL
DC EPROM PROGRAMMING CHARACTERISTICS
Symbol
Description
Min
Max
100
Units
I
V
Supply Current (When Programming)
PP
mA
PP
15
8XC198
EPROM PROGRAMMING WAVEFORMS
SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE
272034–28
SLAVE PROGRAMMING MODE IN WORD DUMP OR DATA VERIFY MODE WITH AUTO INCREMENT
272034–29
16
8XC198
SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM MODE WITH REPEATED PROG PULSE
AND AUTO INCREMENT
272034–30
17
8XC198
AC CHARACTERISTICSÐSERIAL PORTÐSHIFT REGISTER MODE
SERIAL PORT TIMINGÐSHIFT REGISTER MODE
Symbol
Parameter
Min
6 T
Max
Units
ns
t
Serial Port Clock Period (BRR 8002H)
T
T
XLXL
OSC
b
a
Serial Port Clock Falling Edge
t
to Rising Edge (BRR 8002H)
4 T
50
50
4 T
2 T
50
50
ns
XLXH
OSC
OSC
e
T
T
Serial Port Clock Period (BRR
8001H)
4 T
ns
ns
XLXL
OSC
b
a
Serial Port Clock Falling Edge
e
2 T
XLXH
OSC
OSC
to Rising Edge (BRR
8001H)
b
b
T
QVXH
T
XHQX
T
XHQV
T
DVXH
T
XHDX
T
XHQZ
Output Data Setup to Clock Rising Edge
Output Data Hold after Clock Rising Edge
Next Output Data Valid after Clock Rising Edge
Input Data Setup to Clock Rising Edge
Input Data Hold after Clock Rising Edge
Last Clock Rising to Output Float
2 T
2 T
50
50
ns
ns
ns
ns
ns
ns
OSC
OSC
a
2 T
50
OSC
a
T
50
OSC
0
2 T
OSC
WAVEFORMÐSERIAL PORTÐSHIFT REGISTER MODE
SERIAL PORT WAVEFORMÐSHIFT REGISTER MODE
272034–31
18
8XC198
FUNCTIONAL DEVIATIONS
REVISION HISTORY
Devices marked with an ‘‘E’’, ‘‘F’’, or ‘‘G’’ have the
following errata.
This data sheet (272034-003) is valid for devices
marked with an ‘‘E’’, ‘‘F’’, or ‘‘G’’ at the end of the
top side tracking number. Data sheets are changed
as new device information becomes available. Verify
with your local Intel sales office that you have the
latest version before finalizing a design or ordering
devices.
1. HIGH SPEED INPUTS
The High Speed Input (HSI) has three deviations
from the specifications.
NOTE:
The following differences exist between this data
sheet and the previous version (-002).
‘‘Events’’ are defined as one or more pin tran-
sitions. ‘‘Entries’’ are defined as the recording of
one or more events.
1. This data sheet added the ROMless and ROM
devices 80C198 and 83C198 respectively.
A. The resolution is nine states instead of eight
states. Events occurring on the same pin more
frequently than once every nine states may be
lost.
2. The description of the A/D converter prescalar
bit was improved.
B. A mismatch between the nine state HSI resolu-
tion and the eight state hardware timer causes
one time-tag value to be skipped every nine timer
counts. Events may receive a time-tag one count
later than expected.
C. If the FIFO and Holding Register are empty, the
first event will transfer into the Holding Register,
leaving the FIFO empty again. The next event
that occurs will be the first event loaded into the
empty FIFO. If the first two events into an empty
FIFO (not counting the Holding Register) occur
coincident with each other, both are recorded as
one entry with one time-tag. If the second event
occurs within 9 states after the first, the events
will be entered separately with time-tags at least
one count apart. If the second event enters the
FIFO coincident with the ‘‘skipped’’ time-tag situ-
ation (see B above) the time-tags will be at least
two counts apart.
2. CMPL with R0
Using CMPL with register 0 can set incorrect flags.
Don’t use register 0 with the compare long instruc-
tion. Use another long word register and set it equal
to zero. See Techbit MC0692.
19
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