RK80546KG0721M/SL7PD

Low Voltage Intel^®Xeon™ Processor

with 800 MHz System Bus

Datasheet

Product Features

■ Available at 2.80 GHz

■ 90 nm process technology

■ Dual processing support

■ Enhanced branch prediction

■ Includes 16-KB Level 1 data cache

■ Intel^®Extended Memory 64 Technology

■ Binary compatible with applications

running on previous members of Intel’s

IA-32 microprocessor line

■ 1-MB Advanced Transfer Cache (On-die,

full speed Level 2 (L2) Cache) with 8-way

associativity and Error Correcting Code

(ECC)

■ Intel NetBurst^®microarchitecture

■ Hyper-Threading Technology

■ Enables system support of up to 64 GB of

physical memory

■ Supports Execute Disable Bit capability

■ 144 Streaming SIMD Extensions 2 (SSE2)

■ Hardware support for multithreaded

instructions

applications

■ 13 Streaming SIMD Extensions 3 (SSE3)

■ Faster 800 MHz system bus

instructions

■ Rapid Execution Engine: Arithmetic Logic

Units (ALUs) run at twice the processor

core frequency

■ Enhanced floating-point and multimedia

unit for enhanced video, audio, encryption,

and 3D performance

■ Hyper-Pipelined Technology

■ Advanced Dynamic Execution

■ Very deep out-of-order execution

■ System Management mode

■ Thermal Monitor

■ Machine Check Architecture (MCA)

The Low Voltage Intel^®Xeon™ processor with 800 MHz system bus is designed for

high-performance dual-processor applications. Based on the Intel NetBurst^®microarchitecture

and the Hyper-Threading Technology, it is binary compatible with previous Intel^®Architecture

(IA-32) processors. The Low Voltage Intel Xeon processor with 800 MHz system bus is scalable

to two processors in a multiprocessor system providing exceptional performance for applications

running on advanced operating systems such as Windows XP*, Windows Server* 2003, Linux*,

and UNIX*.

The Low Voltage Intel Xeon processor with 800 MHz

system bus delivers compute power at unparalleled value

and flexibility for powerful workstations, internet

infrastructure, and departmental server applications. The

Intel NetBurst^®microarchitecture and Hyper-Threading

Technology deliver outstanding performance and

headroom for peak internet server workloads, resulting in

faster response times, support for more users, and

improved scalability.

Document Number: 304097-001US

October 2004

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY

ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN

INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS

ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES

RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER

INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Low Voltage Intel^®Xeon™ processor with 800 MHz system bus may contain design defects or errors known as errata which may cause the

product to deviate from published specifications. Current characterized errata are available on request.

Hyper-Threading Technology requires a computer system with an Intel^®Pentium^®4 processor supporting HT Technology and a HT Technology

enabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. See Hyper-Threading

Technology (http://developer.intel.com/products/ht/Hyperthreading_more.htm) for more information.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling

1-800-548-4725 or by visiting Intel's website at http://www.intel.com.

Intel, Pentium, Intel Xeon, Intel Inside, Intel NetBurst and Itanium are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the

United States and other countries.

Intel^®Extended Memory 64 Technology (Intel^®EM64T) requires a computer system with a processor, chipset, BIOS, OS, device drivers and

applications enabled for Intel EM64T. Processor will not operate (including 32-bit operation) without an Intel EM64T-enabled BIOS. Performance will

vary depending on your hardware and software configurations. Intel EM64T-enabled OS, BIOS, device drivers and applications may not be available.

Check with your vendor for more information.

^∆Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across

different processor families. See http://www.intel.com/products/processor_number for details.

* Other names and brands may be claimed as the property of others.

2

Datasheet

Contents

1.0 Introduction....................................................................................................................................9

1.1

1.2

1.3

Terminology........................................................................................................................10

References .........................................................................................................................12

State of Data.......................................................................................................................12

2.0 Electrical Specifications .............................................................................................................13

2.1

2.2

Power and Ground Pins......................................................................................................13

Decoupling Guidelines........................................................................................................13

2.2.1

V

Decoupling .....................................................................................................13

CC

2.2.2 VTT Decoupling .....................................................................................................13

2.2.3 Front Side Bus AGTL+ Decoupling........................................................................14

Front Side Bus Clock (BCLK[1:0]) and Processor Clocking ...............................................14

2.3.1 Front Side Bus Frequency Select Signals (BSEL[1:0])..........................................14

2.3.2 Phase Lock Loop (PLL) and Filter .........................................................................15

Voltage Identification (VID) .................................................................................................16

Reserved or Unused Pins...................................................................................................18

Front Side Bus Signal Groups ............................................................................................19

GTL+ Asynchronous and AGTL+ Asynchronous Signals...................................................22

Test Access Port (TAP) Connection ...................................................................................22

Mixing Processors ..............................................................................................................22

2.3

2.4

2.5

2.6

2.7

2.8

2.9

2.10 Absolute Maximum and Minimum Ratings .........................................................................23

2.11 Processor DC Specifications ..............................................................................................24

2.11.1 VCC Overshoot Specification ................................................................................30

2.11.2 Die Voltage Validation ...........................................................................................31

3.0 Mechanical Specifications..........................................................................................................35

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

Package Mechanical Drawings...........................................................................................35

Processor Component Keepout Zones...............................................................................38

Package Loading Specifications.........................................................................................38

Package Handling Guidelines.............................................................................................39

Package Insertion Specifications........................................................................................39

Processor Mass Specifications...........................................................................................39

Processor Materials............................................................................................................39

Processor Markings............................................................................................................40

Processor Pinout Coordinates ............................................................................................41

4.0

Signal Definitions .......................................................................................................................43

4.1 Signal Definitions................................................................................................................43

5.0 Pin List..........................................................................................................................................53

5.1

Low Voltage Intel^®Xeon™ Processor with 800 MHz System Bus Pin Assignments .........53

5.1.1 Pin Listing by Pin Name.........................................................................................54

5.1.2 Pin Listing by Pin Number .....................................................................................62

6.0

Thermal Specifications ..............................................................................................................71

6.1

Package Thermal Specifications ........................................................................................71

6.1.1 Thermal Specifications ..........................................................................................71

Datasheet

3

6.1.2 Thermal Metrology.................................................................................................74

Processor Thermal Features ..............................................................................................74

6.2.1 Thermal Monitor.....................................................................................................74

6.2.2 On-Demand Mode .................................................................................................75

6.2.3 PROCHOT# Signal Pin..........................................................................................75

6.2.4 FORCEPR# Signal Pin..........................................................................................75

6.2.5 THERMTRIP# Signal Pin.......................................................................................76

6.2.6 TCONTROL and Fan Speed Reduction ................................................................76

6.2.7 Thermal Diode .......................................................................................................76

6.2

7.0 Features........................................................................................................................................79

7.1

7.2

Power-On Configuration Options........................................................................................79

Clock Control and Low Power States.................................................................................79

7.2.1 Normal State..........................................................................................................80

7.2.2 HALT Power-Down State.......................................................................................80

7.2.3 Stop-Grant State....................................................................................................82

7.2.4 HALT Snoop State or Snoop State........................................................................82

7.2.5 Sleep State ............................................................................................................83

8.0 Debug Tools Specifications .......................................................................................................85

8.1

8.2

Debug Port System Requirements .....................................................................................85

Target System Implementation...........................................................................................85

8.2.1 System Implementation .........................................................................................85

Logic Analyzer Interface (LAI) ...........................................................................................85

8.3.1 Mechanical Considerations....................................................................................86

8.3.2 Electrical Considerations .......................................................................................86

8.3

4

Datasheet

Figures

1

2

Phase Lock Loop (PLL) Filter Requirements .............................................................................15

Low Voltage Intel^®Xeon™ Processor with 800 MHz System Bus Load Current vs.

Time (VRM 10.0)........................................................................................................................27

VCC Static and Transient Tolerance..........................................................................................29

VCC Overshoot Example Waveform..........................................................................................30

Processor Package Assembly Sketch........................................................................................35

Processor Package Drawing (Sheet 1 of 2) ...............................................................................36

Processor Package Drawing (Sheet 2 of 2) ...............................................................................37

Processor Top-Side Markings (Example)...................................................................................40

Processor Bottom-Side Markings (Example) .............................................................................40

3

4

5

6

7

8

9

10 Processor Pinout Coordinates, Top View...................................................................................41

11 Processor Pinout Coordinates, Bottom View .............................................................................42

12 Low Voltage Intel^®Xeon™ Processor with 800 MHz System Bus Thermal Profile ...................73

13 Case Temperature (TCASE) Measurement Location ................................................................74

14 Stop Clock State Machine..........................................................................................................81

Datasheet

5

Tables

1

2

3

4

5

6

7

8

9

Features of the Low Voltage Intel^®Xeon™ Processor with 800 MHz System Bus ..................... 9

Core Frequency to Front Side Bus Multiplier Configuration.......................................................14

BSEL[1:0] Frequency Table .......................................................................................................15

Voltage Identification Definition..................................................................................................17

Front Side Bus Signal Groups....................................................................................................20

Signal Description Table ............................................................................................................21

Signal Reference Voltages.........................................................................................................21

Absolute Maximum and Minimum Ratings.................................................................................23

Voltage and Current Specifications............................................................................................25

10 VCC Static and Transient Tolerance..........................................................................................28

11 VCC Overshoot Specifications...................................................................................................30

12 BSEL[1:0] and VID[5:0] Signal Group DC Specifications...........................................................31

13 AGTL+ Signal Group DC Specifications ....................................................................................31

14 PWRGOOD Input and TAP Signal Group DC Specifications.....................................................32

15 GTL+ Asynchronous and AGTL+ Asynchronous Signal Group DC Specifications....................32

16 VIDPWRGD DC Specifications ..................................................................................................33

17 Processor Loading Specifications ..............................................................................................38

18 Package Handling Guidelines ....................................................................................................39

19 Processor Materials ...................................................................................................................39

20 Signal Definitions .......................................................................................................................43

21 Pin Listing by Pin Name .............................................................................................................54

22 Pin Listing by Pin Number..........................................................................................................62

23 Low Voltage Intel^®Xeon™ Processor with 800 MHz System Bus Thermal Specifications .......72

24 Low Voltage Intel^®Xeon™ Processor with 800 MHz System Bus Thermal Profile ...................73

25 Thermal Diode Parameters ........................................................................................................76

26 Thermal Diode Interface.............................................................................................................77

27 Power-On Configuration Option Pins .........................................................................................79

6

Datasheet

Revision History

Date

Revision

001

Description

October 2004

Initial release

Datasheet

7

THIS PAGE INTENTIONALLY LEFT BLANK

8

Datasheet

1.0

Introduction

The Low Voltage Intel^®Xeon™ processor with 800 MHz system bus is a 32-bit processor based

on improvements to the Intel NetBurst^®microarchitecture. It maintains the tradition of

compatibility with IA-32 software and includes features found in the Low-Voltage Intel^®Xeon™

processor such as Hyper-Pipelined Technology, a Rapid Execution Engine, and an Execution Trace

Cache. Hyper-Pipelined Technology includes a multi-stage pipeline, allowing the processor to

reach much higher core frequencies. The 800 MHz system bus is a quad-pumped bus running off a

200 MHz system clock making 6.4 GB per second data transfer rates possible. The Execution

Trace Cache is a level 1 cache that stores decoded micro-operations, which removes the decoder

from the main execution path, thereby increasing performance.

The Low Voltage Intel Xeon processor with 800 MHz system bus supports Hyper-Threading

Technology. This feature allows a single, physical processor to function as two logical processors.

While some execution resources such as caches, execution units, and buses are shared, each logical

processor has its own architecture state with its own set of general-purpose registers, control

registers to provide increased system responsiveness in multitasking environments, and headroom

for next generation multi-threaded applications. More information on Hyper-Threading

Technology can be found at http://www.intel.com/technology/hyperthread.

Other features within the Intel NetBurst^®microarchitecture include Advanced Dynamic Execution,

Advanced Transfer Cache, enhanced floating-point and multi-media unit, Streaming SIMD

Extensions 2 (SSE2) and Streaming SIMD Extensions 3 (SSE3). Advanced Dynamic Execution

improves speculative execution and branch prediction internal to the processor. The Advanced

Transfer Cache is a 1 MB, on-die, level 2 (L2) cache with increased bandwidth. The floating-point

and multi-media units include 128-bit wide registers and a separate register for data movement.

Streaming SIMD2 (SSE2) instructions provide highly efficient double-precision floating-point,

SIMD integer, and memory management operations. In addition, (SSE3) instructions have been

added to further extend the capabilities of Intel^®processor technology. Other processor

enhancements include core frequency improvements and microarchitectural improvements.

The Low Voltage Intel Xeon processor with 800 MHz system bus supports Intel^®Extended

Memory 64 Technology (Intel^®EM64T) as an enhancement to Intel’s IA-32 architecture. This

enhancement allows the processor to execute operating systems and applications written to take

advantage of the 64-bit extension technology. Further details on Intel^®Extended Memory 64

Technology and its programming model can be found in the 64-bit Extension Technology Software

Developer's Guide at http://developer.intel.com/technology/64bitextensions.

The Low Voltage Intel Xeon processor with 800 MHz system bus is intended for high performance

systems with up to two processors on one system bus. The processor will be packaged in a 604-pin

Flip Chip Micro Pin Grid Array (FC-mPGA4) package and will use a surface mount Zero Insertion

Force (ZIF) socket (mPGA604).

Table 1.

Features of the Low Voltage Intel^®Xeon™ Processor with 800 MHz System Bus

No. of Supported

Symmetric

Agents

L2 Advanced

Transfer

Front Side Bus

Frequency

Package

Cache

Low Voltage Intel^®Xeon™

processor with 800 MHz system

bus

604-pin

FC-mPGA4

1–2

1 MB

800 MHz

Datasheet

9

Platforms based on the Low Voltage Intel^®Xeon™ processor with 800 MHz system bus

implement independent power planes for each system bus agent. As a result, the processor core

voltage (V ) and system bus termination voltage (V ) must connect to separate supplies. The

CC

TT

processor core voltage uses power delivery guidelines denoted by VRM 10.0 and the associated

load line (see Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD)

10.0 Design Guidelines for further details).

The Low Voltage Intel Xeon processor with 800 MHz system bus uses a scalable system bus

protocol referred to as the “system bus” in this document. The system bus uses a split-transaction,

deferred reply protocol. The system bus uses Source-Synchronous Transfer (SST) of address and

data to improve performance. The processor transfers data four times per bus clock (4X data

transfer rate, as in AGP 4X). Along with the 4X data bus, the address bus can deliver addresses two

times per bus clock and is referred to as a ‘double-clocked’ or the 2X address bus. In addition, the

Request Phase completes in one clock cycle. Working together, the 4X data bus and 2X address bus

provide a data bus bandwidth of up to 6.4 GBytes/second (6400 MBytes/second). Finally, the

system bus is also used to deliver interrupts.

The Low Voltage Intel Xeon processor with 800 MHz system bus also includes the Execute

Disable Bit capability previously available in Itanium^®processors. This feature combined with a

supported operating system allows memory to be marked as executable or non-executable. When

code attempts to run in non-executable memory, the processor raises an error to the operating

system. This feature can prevent some classes of viruses or worms that exploit buffer overrun

vulnerabilities and can thus help improve the overall security of the system. See the Intel^®

Architecture Software Developer’s Manual for more detailed information.

1.1

Terminology

A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the asserted

state when driven to a low level. For example, when RESET# is low, a reset has been requested.

Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where

the name does not imply an active state but describes part of a binary sequence (such as address or

data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a

hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).

“Front side bus” or “System bus” refers to the interface between the processor, system core logic

(also known as the chipset components), and other bus agents. The system bus is a multiprocessing

interface to processors, memory, and I/O. For this document, “front side bus” or “system bus” are

used as generic terms for the “Low Voltage Intel^®Xeon™ processor with 800 MHz system bus”.

Commonly used terms are explained here for clarification:

• Low Voltage Intel^®Xeon™ Processor with 800 MHz System Bus — Intel^®32-bit

microprocessor intended for single/dual-processor applications. The Low Voltage Intel^®

Xeon™ processor with 800 MHz system bus is based on Intel’s 90 nm process and will

include core frequency improvements, a large cache array, microarchitectural improvements

and additional instructions. The Low Voltage Intel Xeon processor with 800 MHz system bus

will use the mPGA604 socket. For this document, “processor” is used as the generic term for

the “Low Voltage Intel^®Xeon™ processor with 800 MHz system bus”.

• Central Agent — The central agent is the host bridge to the processor and is typically known

as the chipset.

10

Datasheet

• Enterprise Voltage Regulator Down (EVRD) — DC-DC converter integrated onto the

system board that provide the correct voltage and current for the processor based on the logic

state of the VID bits.

• Flip Chip Micro Pin Grid Array (FC-mPGA4) Package — The processor package is a Flip

Chip Micro Pin Grid Array (FC-mPGA4), consisting of a processor core mounted on a pinned

substrate with an integrated heat spreader (IHS). This package technology employs a 1.27 mm

[0.05 in.] pitch for the processor pins.

• Front Side Bus (FSB) — The electrical interface that connects the processor to the chipset.

Also referred to as the processor system bus or the system bus. All memory and I/O

transactions as well as interrupt messages pass between the processor and the chipset over the

FSB.

• Functional Operation — Refers to the normal operating conditions in which all processor

specifications, including DC, AC, system bus, signal quality, mechanical and thermal are

satisfied.

• Integrated Heat Spreader (IHS) — A component of the processor package used to enhance

the thermal performance of the package. Component thermal solutions interface with the

processor at the IHS surface.

• mPGA604 Socket — The Low Voltage Intel^®Xeon™ processor with 800 MHz system bus

mates with the baseboard through this surface mount, 604-pin, zero insertion force (ZIF)

socket. See the mPGA604 Socket Design Guidelines for details regarding this socket.

• Processor Core — The processor’s execution engine.

• Storage Conditions — Refers to a non-operational state. The processor may be installed in a

platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air.

Under these conditions, processor pins should not be connected to any supply voltages, have

any I/Os biased or receive any clocks.

• Symmetric Agent — A symmetric agent is a processor which shares the same I/O subsystem

and memory array, and runs the same operating system as another processor in a system.

Systems using symmetric agents are known as Symmetric Multiprocessor (SMP) systems. The

Low Voltage Intel Xeon processor with 800 MHz system bus should only be used in SMP

systems which have two or fewer agents.

• Thermal Design Power — Processor/chipset thermal solution should be designed to this

target. It is the highest expected sustainable power while running known power-intensive real

applications. TDP is not the maximum power that the processor/chipset can dissipate.

• Voltage Regulator Module (VRM) — DC-DC converter built onto a module that interfaces

with an appropriate card edge socket that supplies the correct voltage and current to the

processor.

• V — The processor core power supply.

CC

• V — The processor ground.

SS

• V — The system bus termination voltage.

TT

Datasheet

11

1.2

References

Material and concepts available in the following documents may be beneficial when reading this

document:

Intel Document

Document

Number

Intel^®Extended Memory 64 Technology Software Developer's Manual, Volume 1

Intel^®Extended Memory 64 Technology Software Developer's Manual, Volume 2

300834

300835

mPGA604 Socket Design Guidelines

254232

241618

248966

AP-485, Intel^®Processor Identification and CPUID Instruction

IA-32 Intel^®Architecture Optimization Reference Manual

IA-32 Intel^®Architecture Software Developer's Manual, Volume 1: Basic Architecture

253665

253666

IA-32 Intel^®Architecture Software Developer's Manual, Volume 2A: Instruction Set

Reference, A-M

IA-32 Intel^®Architecture Software Developer's Manual, Volume 2B: Instruction Set

Reference, N-Z

IA-32 Intel^®Architecture Software Developer's Manual, Volume 3: System Programming

253667

253668

Guide

ITP700 Debug Port Design Guide

249679

302402

302403

Intel^®Xeon™ Processor with 800 MHz System Bus Specification Update

Intel^®Xeon™ Processor with 800 MHz System Bus Core Boundary Scan Descriptive

Language (BSDL) Model (V1.0) and Cell Descriptor File (V1.0)

Intel^®Xeon™ Processor with 800 MHz System Bus Thermal Models

zip file

304061

Intel^®Xeon™ Processor with 800 MHz System Bus Mechanical Models (IGES)

Intel^®Xeon™ Processor with 800 MHz System Bus Mechanical Models (ProE*)

Low Voltage Intel^®Xeon™ Processor with 800 MHz System Bus in Embedded

Applications Thermal / Mechanical Design Guide

Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.0

Design Guidelines

302731

NOTE: Contact your Intel representative for the latest revision of documents without document numbers.

1.3

State of Data

The data contained within this document is subject to change. It is the most accurate information

available by the publication date of this document.

12

Datasheet

2.0

Electrical Specifications

2.1

Power and Ground Pins

For clean on-chip power distribution, the processor has 181 V_CC(power) and 185 V_SS(ground)

inputs. All V_CCpins must be connected to the processor power plane, while all V_SSpins must be

connected to the system ground plane. The processor V_CCpins must be supplied with the voltage

determined by the processor Voltage IDentification (VID) pins.

Eleven signals are denoted as V_TT, which provide termination for the front side bus and power to

the I/O buffers. The platform must implement a separate supply for these pins, which meets the V_TT

specifications outlined in Table 9.

2.2

Decoupling Guidelines

Due to its large number of transistors and high internal clock speeds, the Low Voltage Intel^®

Xeon™ processor with 800 MHz system bus is capable of generating large average current swings

between low and full power states. This may cause voltages on power planes to sag below their

minimum values if bulk decoupling is not adequate. Larger bulk storage (C_BULK), such as

electrolytic or aluminum-polymer capacitors, supply current during longer lasting changes in

current demand by the component, such as coming out of an idle condition. Similarly, they act as a

storage well for current when entering an idle condition from a running condition. Care must be

taken in the baseboard design to ensure that the voltage provided to the processor remains within

the specifications listed in Table 9. Failure to do so can result in timing violations or reduced

lifetime of the component.

2.2.1

2.2.2

V

Decoupling

CC

Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR)

and the baseboard designer must assure a low interconnect resistance from the voltage regulator

(VRD or VRM pins) to the mPGA604 socket. The power delivery solution must insure the voltage

and current specifications are met (defined in Table 9).

V_TTDecoupling

Decoupling must be provided on the baseboard. Decoupling solutions must be sized to meet the

expected load. To insure optimal performance, various factors associated with the power delivery

solution must be considered including regulator type, power plane and trace sizing, and component

placement. A conservative decoupling solution would consist of a combination of low ESR bulk

capacitors and high frequency ceramic capacitors.

Datasheet

13

2.2.3

Front Side Bus AGTL+ Decoupling

The Low Voltage Intel^®Xeon™ processor with 800 MHz system bus integrates signal termination

on the die, as well as part of the required high frequency decoupling capacitance on the processor

package. However, additional high frequency capacitance must be added to the baseboard to

properly decouple the return currents from the front side bus. Bulk decoupling must also be

provided by the baseboard for proper AGTL+ bus operation.

2.3

Front Side Bus Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the front side bus interface speed as well as the core frequency of the

processor. As in previous processor generations, the Low Voltage Intel^®Xeon™ processor with

800 MHz system bus core frequency is a multiple of the BCLK[1:0] frequency. The processor bus

ratio multiplier will be set during manufacturing. The default setting will be the maximum speed

for the processor. It will be possible to override this setting using software. This will permit

operation at a speed lower than the processor’s tested frequency.

The BCLK[1:0] inputs directly control the operating speed of the front side bus interface. The

processor core frequency is configured during reset by using values stored internally during

manufacturing. The stored value sets the highest bus fraction at which the particular processor can

operate.

Clock multiplying within the processor is provided by the internal phase locked loop (PLL), which

requires a constant frequency BCLK[1:0] input, with exceptions for spread spectrum clocking. The

Low Voltage Intel^®Xeon™ processor with 800 MHz system bus uses differential clocks. Details

regarding BCLK[1:0] driver specifications are provided in the CK409 Clock Synthesizer/Driver

Design Guidelines or CK409B Clock Synthesizer/Driver Design Guidelines. Table 2 contains core

frequency to front side bus multipliers and their corresponding core frequencies.

Table 2.

Core Frequency to Front Side Bus Multiplier Configuration

Core Frequency to

Core Frequency with

Front Side Bus Multiplier

200 MHz Front Side Bus Clock

1/14

2.80 GHz

2.3.1

Front Side Bus Frequency Select Signals (BSEL[1:0])

Upon power up, the front side bus frequency is set to the maximum supported by the individual

processor. BSEL[1:0] are open-drain outputs, which must be pulled up to V , and are used to

TT

select the front side bus frequency. Please refer to Table 12 for DC specifications. Table 3 defines

the possible combinations of the signals and the frequency associated with each combination. The

frequency is determined by the processor(s), chipset, and clock synthesizer. All front side bus

agents must operate at the same core and front side bus frequencies. Individual processors will only

operate at their specified front side bus clock frequency.

14

Datasheet

Table 3.

BSEL[1:0] Frequency Table

BSEL1

BSEL0

Bus Clock Frequency

0

1

0

1

0

1

Reserved

200 MHz

Reserved

2.3.2

Phase Lock Loop (PLL) and Filter

V_CCAand V_CCIOPLLare power sources required by the PLL clock generators on the Low Voltage

Intel^®Xeon™ processor with 800 MHz system bus. Since these PLLs are analog in nature, they

require quiet power supplies for minimum jitter. Jitter is detrimental to the system: it degrades

external I/O timings as well as internal core timings (i.e., maximum frequency). To prevent this

degradation, these supplies must be low pass filtered from V_TT.

The AC low-pass requirements are as follows:

• < 0.2 dB gain in pass band

• < 0.5 dB attenuation in pass band < 1 Hz

• > 34 dB attenuation from 1 MHz to 66 MHz

• > 28 dB attenuation from 66 MHz to core frequency

The filter requirements are illustrated in Figure 1.

Figure 1.

Phase Lock Loop (PLL) Filter Requirements

0.2 dB

0 dB

x dB

–28 dB

–34 dB

DC

1 Hz

fpeak 1 MHz 66 MHz

fcore 1.67 GHz

<50 kHz

500 MHz

High

Frequency

Passband

CS00141

NOTES:

1. Diagram not to scale.

2. No specifications for frequencies beyond f_core(core frequency).

3. f_peak, if existent, should be less than 0.05 MHz.

4. f_corerepresents the maximum core frequency supported by the platform.

Datasheet

15

2.4

Voltage Identification (VID)

The Voltage Identification (VID) specification for the Low Voltage Intel^®Xeon™ processor with

800 MHz system bus is defined by the Voltage Regulator Module (VRM) and Enterprise Voltage

Regulator-Down (EVRD) 10.0 Design Guidelines. The voltage set by the VID signals is the

maximum voltage allowed by the processor (please see Section 2.11.1 for V overshoot

CC

specifications). VID signals are open drain outputs, which must be pulled up to V . Please refer to

TT

Table 12 for the DC specifications for these signals. A minimum voltage is provided in Table 9 and

changes with frequency. This allows processors running at a higher frequency to have a relaxed

minimum voltage specification. The specifications have been set such that one voltage regulator

can operate with all supported frequencies.

Individual processor VID values may be calibrated during manufacturing such that two devices at

the same core speed may have different default VID settings. This is reflected by the VID Range

values provided in Table 9. Refer to the Intel^®Xeon™ Processor with 800 MHz System Bus

Specification Update for further details on specific valid core frequency and VID values of the

processor.

The Low Voltage Intel^®Xeon™ processor with 800 MHz system bus uses six voltage

identification signals, VID[5:0], to support automatic selection of power supply voltages. Table 4

specifies the voltage level corresponding to the state of VID[5:0]. A ‘1’ in this table refers to a high

voltage level and a ‘0’ refers to a low voltage level. If the processor socket is empty (VID[5:0] =

x11111), or the voltage regulation circuit cannot supply the voltage that is requested, it must disable

itself. See the Voltage Regulator Module (VRM) Voltage Regulator-Down (EVRD) 10.0 Design

Guidelines or Voltage Regulator Module (VRM) for further details.

The Low Voltage Intel^®Xeon™ processor with 800 MHz system bus provides the ability to

operate while transitioning to an adjacent VID and its associated processor core voltage (V ).

CC

This will represent a DC shift in the load line. It should be noted that a low-to-high or high-to-low

voltage state change may result in as many VID transitions as necessary to reach the target core

voltage. Transitions above the specified VID are not permitted. Table 9 includes VID step sizes and

DC shift ranges. Minimum and maximum voltages must be maintained as shown in Table 10 and

Figure 3.

The VRM or VRD used must be capable of regulating its output to the value defined by the new

VID. DC specifications for dynamic VID transitions are included in Table 9 and Table 10. Please

refer to the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD)

10.0 Design Guidelines for further details.

Power source characteristics must be guaranteed to be stable whenever the supply to the voltage

regulator is stable.

16

Datasheet

Table 4.

Voltage Identification Definition

VID5

VID4

VID3

VID2

VID1

VID0

V_{CC_MAX}

VID5

VID4

VID3

VID2

VID1

VID0

V_{CC_MAX}

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0.8375

0.8500

0.8625

0.8750

0.8875

0.9000

0.9125

0.9250

0.9375

0.9500

0.9625

0.9750

0.9875

1.0000

1.0125

1.0250

1.0375

1.0500

1.0625

1.0750

1.0875

OFF¹

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1.2125

1.2250

1.2375

1.2500

1.2625

1.2750

1.2875

1.3000

1.3125

1.3250

1.3375

1.3500

1.3625

1.3750

1.3875

1.4000

1.4125

1.4250

1.4375

1.4500

1.4625

1.4750

1.4875

1.5000

1.5125

1.5250

1.5375

1.5500

1.5625

1.5750

1.5875

1.6000

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

OFF¹

1

1.1000

1.1125

1.1250

1.1375

1.1500

1.1625

1.1750

1.1875

1.2000

0

1

0

1

0

1

0

1

NOTES:

1. When this VID pattern is observed, the voltage regulator output should be disabled.

Datasheet

17

2.5

Reserved or Unused Pins

All Reserved pins must remain unconnected. Connection of these pins to V , V , V , or to any

CC

TT SS

other signal (including each other) can result in component malfunction or incompatibility with

future processors. See Section 5.0 for a pin listing of the processor and the location of all Reserved

pins.

For reliable operation, always connect unused inputs or bidirectional signals to an appropriate

signal level. In a system level design, on-die termination has been included by the processor to

allow end agents to be terminated within the processor silicon for most signals. In this context, end

agent refers to the bus agent that resides on either end of the daisy-chained front side bus interface

while a middle agent is any bus agent in between the two end agents. For end agents, most unused

AGTL+ inputs should be left as no connects as AGTL+ termination is provided on the processor

silicon. However, see Table 6 for details on AGTL+ signals that do not include on-die termination.

For middle agents, the on-die termination must be disabled, so the platform must ensure that

unused AGTL+ input signals which do not connect to end agents are connected to V via a pull-

TT

up resistor. Unused active high inputs, should be connected through a resistor to ground (V ).

SS

Unused outputs can be left unconnected, however this may interfere with some TAP functions,

complicate debug probing, and prevent boundary scan testing. A resistor must be used when tying

bidirectional signals to power or ground. When tying any signal to power or ground, a resistor will

also allow for system testability. Resistor values should be within ± 20% of the impedance of the

baseboard trace for front side bus signals. For unused AGTL+ input or I/O signals, use pull-up

resistors of the same value as the on-die termination resistors (R ).

TT

TAP, Asynchronous GTL+ inputs, and Asynchronous GTL+ outputs do not include on-die

termination. Inputs and utilized outputs must be terminated on the baseboard. Unused outputs may

be terminated on the baseboard or left unconnected. Note that leaving unused outputs unterminated

may interfere with some TAP functions, complicate debug probing, and prevent boundary scan

testing. Signal termination for these signal types is discussed in the ITP700 Debug Port Design

Guide (See Section 1.2).

All TESTHI[6:0] pins should be individually connected to V via a pull-up resistor which

TT

matches the nominal trace impedance. TESTHI[3:0] and TESTHI[6:5] may be tied together and

pulled up to V with a single resistor if desired. However, usage of boundary scan test will not be

TT

functional if these pins are connected together. TESTHI4 must always be pulled up independently

from the other TESTHI pins. For optimum noise margin, all pull-up resistor values used for

TESTHI[6:0] pins should have a resistance value within ± 20% of the impedance of the board

transmission line traces. For example, if the nominal trace impedance is 50 Ω, then a value between

40 Ω and 60 Ω should be used.

N/C (no connect) pins of the processor are not used by the processor. There is no connection from

the pin to the die. These pins may perform functions in future processors intended for platforms

using the Low Voltage Intel^®Xeon™ processor with 800 MHz system bus.

18

Datasheet

2.6

Front Side Bus Signal Groups

The front side bus signals have been combined into groups by buffer type. AGTL+ input signals

have differential input buffers, which use GTLREF as a reference level. In this document, the term

“AGTL+ Input” refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving.

Similarly, “AGTL+ Output” refers to the AGTL+ output group as well as the AGTL+ I/O group

when driving. AGTL+ asynchronous outputs can become active anytime and include an active

pMOS pull-up transistor to assist during the first clock of a low-to-high voltage transition.

With the implementation of a source synchronous data bus comes the need to specify two sets of

timing parameters. One set is for common clock signals whose timings are specified with respect to

rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source

synchronous signals which are relative to their respective strobe lines (data and address) as well as

rising edge of BCLK0. Asynchronous signals are still present (A20M#, IGNNE#, etc.) and can

become active at any time during the clock cycle. Table 5 identifies which signals are common

clock, source synchronous and asynchronous.

Datasheet

19

Table 5.

Front Side Bus Signal Groups

Signal Group

Type

Signals¹

AGTL+ Common Clock

Input

Synchronous to BCLK[1:0] BPRI#, BR[3:1]#^2,3, DEFER#, RESET#, RS[2:0]#,

RSP#, TRDY#

AGTL+ Common Clock I/O

Synchronous to BCLK[1:0] ADS#, AP[1:0]#, BINIT#⁴, BNR#⁴, BPM[5:0]#,

BR0#^2,3, DBSY#, DP[3:0]#, DRDY#, HIT#⁴,

HITM#⁴, LOCK#, MCERR#⁴

AGTL+ Source

Synchronous I/O

Synchronous to assoc.

strobe

Signals

Associated Strobe

REQ[4:0]#,A[16:3]#³ADSTB0#

A[35:17]#³

ADSTB1#

D[15:0]#, DBI0#

D[31:16]#, DBI1#

D[47:32]#, DBI2#

D[63:48]#, DBI3#

DSTBP0#, DSTBN0#

DSTBP1#, DSTBN1#

DSTBP2#, DSTBN2#

DSTBP3#, DSTBN3#

AGTL+ Strobe I/O

Synchronous to BCLK[1:0] ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#

AGTL Asynchronous Output Asynchronous

GTL+ Asynchronous Input Asynchronous

FERR#/PBE#, IERR#, PROCHOT#

A20M#, FORCEPR#, IGNNE#, INIT#³, LINT0/

INTR, LINT1/NMI, SMI#³, SLP#, STPCLK#

GTL+ Asynchronous Output Asynchronous

THERMTRIP#

BCLK1, BCLK0

TCK, TDI, TMS, TRST#

TDO

Front Side Bus Clock

TAP Input

Clock

Synchronous to TCK

Power/Other

TAP Output

Power/Other

BOOT_SELECT, BSEL[1:0], COMP[1:0],

GTLREF[3:0], ODTEN, OPTIMIZED/COMPAT#,

PWRGOOD, Reserved, SKTOCC#,

SLEW_CTRL, SMB_PRT, TEST_BUS,

TESTHI[6:0], THERMDA, THERMDC, V_CC, V_CCA

,

V_CCIOPLL,V_CCPLL, VCCSENSE, VID[5:0], V_SS

,

V_SSA, VSSSENSE, V_TT, VIDPWRGD, VTTEN

NOTES:

1. Refer to Section 4.0 for signal descriptions.

2. The Low Voltage Intel^®Xeon™ processor with 800 MHz system bus only uses BR0# and BR1#. BR2# and

BR3# must be terminated to V_TT. For additional details regarding the BR[3:0]# signals, see Section 4.0 and

Section 7.1.

3. The value of these pins during the active-to-inactive edge of RESET# defines the processor configuration

options. See Section 7.1 for details.

4. These signals may be driven simultaneously by multiple agents (wired-OR).

20

Datasheet

Table 6 outlines the signals which include on-die termination (R ) and lists signals which include

TT

additional on-die resistance (R ). Open drain signals are also included. Table 7 provides signal

L

reference voltages

Table 6.

Signal Description Table

Signals with R_TT

Signals with No R_TT

A[35:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#,

BNR#, BOOT_SELECT², BPRI#, D[63:0]#,

DBI[3:0]#, DBSY#, DEFER#, DP[3:0]#, DRDY#,

DSTBN[3:0]#, DSTBP[3:0]#, FORCEPR#, HIT#,

HITM#, LOCK#, MCERR#, OPTIMIZED/

COMPAT#², REQ[4:0]#, RS[2:0]#, RSP#,

SLEW_CTRL, TEST_BUS, TRDY#

A20M#, BCLK[1:0], BPM[5:0]#, BR[3:0]#, BSEL[1:0],

COMP[1:0], FERR#/PBE#, GTLREF[3:0], IERR#,

IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, ODTEN,

PROCHOT#, PWRGOOD, RESET#, SKTOCC#, SLP#,

SMI#, STPCLK#, TCK, TDI, TDO, TESTHI[6:0],

THERMDA, THERMDC, THERMTRIP#, TMS, TRST#,

VID[5:0], VIDPWRGD, VTTEN

Signals with R_L

Signals with No R_L

BINIT#, BNR#, HIT#, HITM#, MCERR#

A20M#, A[35:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#,

BCLK[1:0], BPM[5:0]#, BPRI#, BR[3:0]#, BSEL[1:0],

BOOT_SELECT², COMP[1:0], D[63:0]#, DBI[3:0]#,

DBSY#, DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#,

DSTBP[3:0]#, FERR#/PBE#, FORCEPR#,

GTLREF[3:0], IERR#, IGNNE#, INIT#, LINT0/INTR,

LINT1/NMI, LOCK#, ODTEN, OPTIMIZED/COMPAT#²,

PROCHOT#, PWRGOOD, REQ[4:0]#, RESET#,

RS[2:0]#, RSP#, SKTOCC#, SLEW_CTRL, SLP#, SMI#,

STPCLK#, TCK, TDI, TDO, TEST_BUS, TESTHI[6:0],

THERMDA, THERMDC, THERMTRIP#, TMS, TRDY#,

TRST#, VID[5:0], VIDPWRGD, VTTEN

Open Drain Signals¹

BPM[5:0]#, BR0#, BSEL[1:0], FERR#/PBE#, IERR#, TDO, THERMTRIP#, VID[5:0]

NOTES:

1. Signals that do not have R_TT, nor are actively driven to their high voltage level.

2. The termination for these signals is not R_TT. The OPTIMIZED/COMPAT# and BOOT_SELECT pins have a

500 - 5000 Ω pull-up to V_TT

.

Table 7.

Signal Reference Voltages

GTLREF

0.5 * V_TT

A20M#, A[35:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#,

BINIT#, BNR#, BPM[5:0]#, BPRI#, BR[3:0]#,

D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, DP[3:0]#,

DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, FORCEPR#,

HIT#, HITM#, IGNNE#, INIT#, LINT0/INTR, LINT1/

NMI, LOCK#, MCERR#, ODTEN, RESET#,

REQ[4:0]#, RS[2:0]#, RSP#, SLEW_CTRL, SLP#,

SMI#, STPCLK#, TRDY#

BOOT_SELECT, OPTIMIZED/COMPAT#, PWRGOOD¹,

TCK¹, TDI¹, TMS¹, TRST#¹, VIDPWRGD

NOTES:

1. These signals also have hysteresis added to the reference voltage. See Table 14 for more information.

Datasheet

21

2.7

GTL+ Asynchronous and AGTL+ Asynchronous Signals

The Low Voltage Intel^®Xeon™ processor with 800 MHz system bus does not use CMOS voltage

levels on any signals that connect to the processor silicon. As a result, input signals such as

A20M#, FORCEPR#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#, SLP#, and STPCLK#

use GTL input buffers. Legacy output THERMTRIP# uses a GTL+ output buffers. All of these

Asynchronous GTL+ signals follow the same DC requirements as GTL+ signals, however the

outputs are not driven high (during the logical 0-to-1 transition) by the processor. FERR#/PBE#,

IERR#, and IGNNE# have now been defined as AGTL+ asynchrnous signals as they include an

active p-MOS device. GTL+ asynchronous and AGTL+ asynchronous signals do not have setup or

hold time specifications in relation to BCLK[1:0]. However, all of the GTL+ asynchronous and

AGTL+ asynchronous signals are required to be asserted/deasserted for at least six BCLKs in order

for the processor to recognize them. See Table 15 for the DC specifications for the asynchronous

GTL+ signal groups.

2.8

2.9

Test Access Port (TAP) Connection

Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is

recommended that the processor(s) be first in the TAP chain and followed by any other components

within the system. A translation buffer should be used to connect to the rest of the chain unless one

of the other components is capable of accepting an input of the appropriate voltage. Similar

considerations must be made for TCK, TMS, and TRST#. Two copies of each signal may be

required with each driving a different voltage level.

Mixing Processors

Intel only supports and validates dual processor configurations in which both Low Voltage Intel^®

Xeon™ processor with 800 MHz system bus operate with the same front side bus frequency, core

frequency, and have the same internal cache sizes. Mixing components operating at different

internal clock frequencies is not supported and will not be validated by Intel [Note: Processors

within a system must operate at the same frequency per bits [15:8] of the

IA-32_FLEX_BRVID_SEL MSR; however this does not apply to frequency transitions initiated

due to thermal events, or assertion of the FORCEPR# signal (See Section 6.0)]. Not all operating

systems can support dual processors with mixed frequencies. Intel does not support or validate

operation of processors with different cache sizes. Mixing processors of different steppings but the

same model (as per CPUID instruction) is supported. Please see the Intel^®Xeon™ Processor with

800 MHz System Bus Specification Update for the applicable mixed stepping table. Details

regarding the CPUID instruction are provided in the Intel^®Processor Identification and the

CPUID Instruction application note.

22

Datasheet

2.10

Absolute Maximum and Minimum Ratings

Table 8 specifies absolute maximum and minimum ratings. Within functional operation limits,

functionality and long-term reliability can be expected.

At conditions outside functional operation condition limits, but within absolute maximum and

minimum ratings, neither functionality nor long term reliability can be expected. If a device is

returned to conditions within functional operation limits after having been subjected to conditions

outside these limits, but within the absolute maximum and minimum ratings, the device may be

functional, but with its lifetime degraded depending on exposure to conditions exceeding the

functional operation condition limits.

At conditions exceeding absolute maximum and minimum ratings, neither functionality nor long-

term reliability can be expected. Moreover, if a device is subjected to these conditions for any

length of time then, when returned to conditions within the functional operating condition limits, it

will either not function, or its reliability will be severely degraded.

Although the processor contains protective circuitry to resist damage from static electric discharge,

precautions should always be taken to avoid high static voltages or electric fields.

Table 8.

Absolute Maximum and Minimum Ratings

Symbol

Parameter

Min.

Max.

Unit

Notes^1,2

V_CC

V_TT

Core voltage with respect to VSS

-0.30

1.55

V

System bus termination voltage with

respect to V_SS

T_CASE

Processor case temperature

See

°C

Section 6.0 Section 6.0

T_STORAGEStorage temperature

-40 85

3, 4

NOTES:

1. For functional operation, all processor electrical, signal quality, mechanical and thermal specifications must

be satisfied.

2. Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor.

3. Storage temperature is applicable to storage conditions only. In this scenario, the processor must not receive

a clock, and no pins can be connected to a voltage bias. Storage within these limits will not affect the long-

term reliability of the device. For functional operation, please refer to the processor case temperature

specifications.

4. This rating applies to the processor and does not include any tray or packaging.

Datasheet

23

2.11

Processor DC Specifications

The processor DC specifications in this section are defined at the processor core (pads) unless

noted otherwise. See Section 5.1 for the Low Voltage Intel^®Xeon™ processor with 800 MHz

system bus pin listings and Section 4.1 for signal definitions. Voltage and current specifications are

detailed in Table 9. For platform power delivery planning refer to Table 10, which provides V

static and transient tolerances. This same information is presented graphically in Figure 3.

CC

BSEL[1:0] and VID[5:0] signals are specified in Table 12. The DC specifications for the AGTL+

signals are listed in Table 13. The DC specifications for the PWRGOOD input and TAP signal

group are listed in Table 14 and the Asynchronous GTL+ signal group is listed in Table 15.

Table 9 through Table 15 list the DC specifications for the processor and are valid only while

meeting specifications for case temperature (T_CASEas specified in Section 6.0), clock frequency,

and input voltages. Care should be taken to read all notes associated with each parameter.

24

Datasheet

Table 9.

Voltage and Current Specifications

Symbol

Parameter

Min.

Typ.

Max.

Unit

Notes¹

VID range

VID range for Low Voltage Intel^®

Xeon™ processor with 800 MHz

system bus

1.1125

1.2000

V

2, 3

V_CC

V_TT

V_CCfor Low Voltage Intel^®Xeon™

processor with 800 MHz system bus

See Table 10 and

Figure 3

VID - I_CC(max) * 1.25 mΩ

V

A

3, 4, 5, 6

Front Side Bus termination voltage

(DC specification)

1.176

1.20

1.224

1.260

60

7

7, 8

6, 16

9

Front Side Bus termination voltage

(AC & DC specification)

1.140

1.20

I_CC

I_CCfor Low Voltage Intel^®Xeon™

processor with 800 MHz system bus

I_TT

Front Side Bus end-agent V_TT

current

4.8

I_TT

Front Side Bus mid-agent V_TT

current

1.5

10

I_{CC_VCCA}

I_CCfor PLL power pins

120

100

200

40

mA

µA

A

11

12

13

I_{CC_VCCIOPLL}I_CCfor PLL power pins

I_{CC_GTLREF}

I_CCfor GTLREF pins

I_SGNT

I_SLP

I_CCStop Grant for Low Voltage Intel^®

Xeon™ processor with 800 MHz

system bus

I_TCC

I_CCTCC Active

I_CC

56

A

14

I_{CC_TDC}

I_CCfor Low Voltage Intel^®Xeon™

processor with 800 MHz system bus

Thermal Design Current

15, 16

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processors. These specifications are based on silicon

characterization, however they may be updated as further data becomes available. Listed frequencies are not necessarily

committed production frequencies.

2. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at the manufacturing and

cannot be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same

frequency might have different settings within the VID range. Please note that this differs from the VID employed by the

processor during power management event.

3. These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is

required. See Section 2.4 for more information.

4. The voltage specification requirements are measured across vias on the platform for the VCCSENSE and VSSSENSE pins

close to the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 MΩ minimum

impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system

is not coupled in the scope probe.

5. Refer to Table 10 and corresponding Figure 3. The processor should not be subjected to any static V_CClevel that exceeds the

V

_{CC_MAX}associated with any particular current. Failure to adhere to this specification can shorten processor lifetime.

6. Minimum V_CCand maximum I_CCare specified at the maximum processor case temperature (T_CASE) shown in Table 24.

_{CC_MAX}is specified at the relative V_{CC_MAX}point on the V_CCload line. The processor is capable of drawing I_{CC_MAX}for up to

I

10 ms. Refer to Figure 2 for further details on the average processor current draw over various time durations.

7. V_TTmust be provided via a separate voltage source and must not be connected to V_CC. This specification is measured at the

pin.

8. Baseboard bandwidth is limited to 20 MHz.

9. This specification refers to a single processor with R_TTenabled. Please note the end agent and middle agent may not require

I

_TT(max) simultaneously. This parameter is based on design characterization and not tested.

10.This specification refers to a single processor with R_TTdisabled. Please note the end agent and middle agent may not require

_TT(max) simultaneously. Details will be provided in future revisions of this document.

I

Datasheet

25

11.These specifications apply to the PLL power pins VCCA, VCCIOPLL, and VSSA. See Section 2.3.2 for details. These

parameters are based on design characterization and are not tested.

12.This specification represents a total current for all GTLREF pins.

13.The current specified is also for HALT State.

14.The maximum instantaneous current the processor will draw while the thermal control circuit is active as indicated by the

assertion of the PROCHOT# signal is the maximum I_CCfor the processor.

15.I_{CC_TDC}(Thermal Design Current) is the sustained (DC equivalent) current that the processor is capable of drawing indefinitely

and should be used for the voltage regulator temperature assessment. The voltage regulator is responsible for monitoring its

temperature and asserting the necessary signal to inform the processor of a thermal excursion. Please see the applicable

design guidelines for further details. The processor is capable of drawing I_{CC_TDC}indefinitely. Refer to Figure 2 for further

details on the average processor current draw over various time durations. This parameter is based on design characterization

and is not tested.

16.This specification refers to platforms implementing a power delivery system that complies with VR 10.0 guidelines. Please see

the Voltage Regulator Module (VRM) and Enterprise Voltage-Regulator-Down (EVRD) 10.0 Design Guidelines for further

details.

26

Datasheet

Figure 2.

Low Voltage Intel^®Xeon™ Processor with 800 MHz System Bus Load Current vs.

Time (VRM 10.0)

VRM 10LV Current

62

61

60

59

58

57

56

55

0.01

0.1

1

10

Time Duration (s)

100

1000

NOTES:

1. Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than

I_{CC_TDC}

2. Not 100% tested. Specified by design characterization.

.

Datasheet

27

Table 10.

V

Static and Transient Tolerance

CC

Voltage Deviation from VID Setting (V)1^,2^,3

VCC_Typ

ICC

VCC_Max

VCC_Min

0

VID - 0.000

VID - 0.006

VID - 0.013

VID - 0.019

VID - 0.025

VID - 0.031

VID - 0.038

VID - 0.044

VID - 0.050

VID - 0.056

VID - 0.063

VID - 0.069

VID - 0.075

VID - 0.020

VID - 0.026

VID - 0.033

VID - 0.039

VID - 0.045

VID - 0.051

VID - 0.058

VID - 0.064

VID - 0.070

VID - 0.076

VID - 0.083

VID - 0.089

VID - 0.095

VID - 0.040

VID - 0.046

VID - 0.052

VID - 0.059

VID - 0.065

VID - 0.071

VID - 0.077

VID - 0.084

VID - 0.090

VID - 0.096

VID - 0.103

VID - 0.109

VID - 0.115

5

10

15

20

25

30

35

40

45

50

55

60

NOTES:

1. The V_{CC_MIN}and V_{CC_MAX}loadlines represent static and transient limits. Please see Section 2.11.1 for V_CC

overshoot specifications.

2. This table is intended to aid in reading discrete points on Figure 3.

3. The loadlines specify voltage limits at the die measured at the VCCSENSE and VSSSENSE pins. Voltage

regulation feedback for voltage regulator circuits must be taken from processor V_CCand V_SSpins. Refer to

the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator Down (EVRD) 10.0 Design

Guidelines for socket loadline guidelines and VR implementation.

28

Datasheet

Figure 3.

V

Static and Transient Tolerance

CC

Icc [A]

0

5

10

15

20

25

30

35

40

45

50

55

60

65

70

75

80

85

90

95 100 105 110 115 120

VID - 0.000

VID - 0.020

VID - 0.040

VID - 0.060

VID - 0.080

VID - 0.100

VID - 0.120

VID - 0.140

VID - 0.160

VID - 0.180

VID - 0.200

V_CC

Maximum

V_CC

Typical

V_CC

Minimum

NOTES:

1. The V_{CC_MIN}and V_{CC_MAX}loadlines represent static and transient limits. Please see Section 2.11.1 for V_CC

overshoot specifications.

2. The V_{CC_MIN}and V_{CC_MAX}loadlines are plots of the discrete point found in Table 10.

3. Refer to Table 9 for processor VID information.

4. The loadlines specify voltage limits at the die measured at the VCCSENSE and VSSSENSE pins. Voltage

regulation feedback for voltage regulator circuits must be taken from processor V_CCand V_SSpins. Refer to

the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator Down (EVRD) 10.0 Design

Guidelines for socket loadline guidelines and VR implementation.

Datasheet

29

2.11.1

V

Overshoot Specification

CC

The Low Voltage Intel^®Xeon™ processor with 800 MHz system bus can tolerate short transient

overshoot events where V exceeds the VID voltage when transitioning from a high-to-low

CC

current load condition. This overshoot cannot exceed VID + V

. (V

is the

OS_MAX

maximum allowable overshoot above VID). These specifications apply to the processor die voltage

as measured across the VCCSENSE and VSSSENSE pins.

Table 11.

V

Overshoot Specifications

CC

Symbol

Parameter

Min.

Max.

Units

Figure

Notes

V_{OS_MAX}

T_{OS_MAX}

Magnitude of V_CC

overshoot above VID

0.050

V

4

Time duration of V_CC

overshoot above VID

25

µs

4

Figure 4.

V

Overshoot Example Waveform

CC

V_OS

VID + 0.050

VID - 0.000

T_OS

0

5

10

15

20

25

Time [us]

T_OS: Overshoot time above VID

V_OS: Overshoot above VID

NOTES:

1. V_OSis measured overshoot voltage.

2. T_OSis measured time duration above VID.

30

Datasheet

2.11.2

Die Voltage Validation

Overshoot events from application testing on processor must meet the specifications in Table 11

when measured across the VCCSENSE and VSSSENSE pins. Overshoot events that are < 10 ns in

duration may be ignored. These measurement of processor die level overshoot should be taken with

a 100 MHz bandwidth limited oscilloscope.

Table 12.

BSEL[1:0] and VID[5:0] Signal Group DC Specifications

Symbol

Parameter

Min.

Typ.

Max

Units

Notes¹

R_ON

BSEL[1:0] and VID[5:0]

Buffer On Resistance

N/A

60

W

2

I_OL

I_LO

Maximum Pin Current

N/A

8

mA

µA

W

2

Output Leakage Current

200

2,3

R_{PULL_UP}Pull-Up Resistor

500

V_TT

V_TOL

Voltage Tolerance

0.95 * V_TT

1.05 * V_TT

V

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. These parameters are based on design characterization and are not tested.

3. Leakage to V_SSwith pin held at V_TT

Table 13.

AGTL+ Signal Group DC Specifications

Symbol

Parameter

Min.

Max.

Unit

Notes¹

V_IL

V_IH

Input Low Voltage

Input High Voltage

0.0

GTLREF - (0.10 * V_TT

V_TT

)

V

2,3

GTLREF +

2,4,5

(0.10 * V_TT

0.90 * V_TT

N/A

)

V_OH

I_OL

Output High Voltage

Output Low Current

V_TT

V

2,5

2,6

V_TT

/

mA

(0.50 * R_{TT_MIN}

+

[R_{ON_MIN}|| R_L])

I_LI

Input Leakage Current

Output Leakage Current

Buffer On Resistance

N/A

7

± 200

11

µA

W

7,8

I_LO

R_ON

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. The V_TTrepresented in these specifications refers to instantaneous V_TT

.

3. V_ILis defined as the voltage range at a receiving agent that will be interpreted as a logical low value.

4. V_IHis defined as the voltage range at a receiving agent that will be interpreted as a logical high value.

5. V_IHand V_OHmay experience excursions above V_TT

6. Refer to Table 6 to determine which signals include additional on-die termination resistance (R_L).

7. Leakage to V_SSwith pin held at V_TT

8. Leakage to V_TTwith pin held at 300 mV.

.

Datasheet

31

Table 14.

PWRGOOD Input and TAP Signal Group DC Specifications

Notes

Symbol

Parameter

Min.

Max.

Unit

1,2

V_HYS

V_t+

Input Hysteresis

200

350

mV

V

3

4

Input Low to High

Threshold Voltage

0.5 * (V_TT+ V_{HYS_MIN}

)

0.5 * (V_TT+ V_{HYS_MAX})

V_t-

Input High to Low

Threshold Voltage

0.5 * (V_TT- V_{HYS_MAX}

N/A

0.5 * (V_TT- V_{HYS_MIN}

)

V

4

V_OH

I_OL

I_LI

Output High Voltage

Output Low Current

Input Leakage Current

Output Leakage Current

Buffer On Resistance

V_TT

45

V

mA

µA

W

4

5

N/A

7

± 200

11

I_LO

R_ON

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. All outputs are open drain.

3. V_HYSrepresents the amount of hysteresis, nominally centered about 0.5 * V_TTfor all PWRGOOD and TAP

inputs.

4. The V_TTrepresented in these specifications refers to instantaneous V_TT

.

5. The maximum output current is based on maximum current handling capability of the buffer and is not

specified into the test load.

Table 15.

GTL+ Asynchronous and AGTL+ Asynchronous Signal Group DC Specifications

Symbol

Parameter

Min.

Max.

Unit

Notes¹

V_IL

Input Low Voltage

Input High Voltage

Output High Voltage

Output Low Current

0.0

GTLREF + (0.10 * V_TT

0.90 * V_TT

GTLREF - (0.10 * V_TT

)

V

2,3

2,4,5

2,5

V_IH

V_OH

I_OL

)

V_TT

V

N/A

V_TT

/

mA

2,6

(0.50 * R_{TT_MIN}

+

[R_{ON_MIN}|| R_L])

I_LI

Input Leakage Current

Output Leakage Current

Buffer On Resistance

N/A

7

± 200

11

µA

W

7,8

I_LO

R_on

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. The V_TTrepresented in these specifications refers to instantaneous V_TT

.

3. V_ILis defined as the voltage range at a receiving agent that will be interpreted as a logical low value.

4. V_IHis defined as the voltage range at a receiving agent that will be interpreted as a logical high value.

5. V_IHand V_OHmay experience excursions above V_TT

6. Refer to Table 2-5 to determine which signals include additional on-die termination resistance (R_L).

7. Leakage to V_SSwith pin held at V_TT

8. Leakage to V_TTwith pin held at 300 mV.

.

32

Datasheet

Table 16.

VIDPWRGD DC Specifications

Symbol

Parameter

Min.

Max.

Unit

V_IL

V_IH

Input Low Voltage

Input High Voltage

0.0

0.30

V_TT

V

0.90

Datasheet

33

THIS PAGE INTENTIONALLY LEFT BLANK

34

Datasheet

3.0

Mechanical Specifications

The Low Voltage Intel^®Xeon™ processor with 800 MHz system bus is packaged in Flip Chip

Micro Pin Grid Array (FC-mPGA4) package that interfaces to the baseboard via an mPGA604

socket. The package consists of a processor core mounted on a substrate pin-carrier. An integrated

heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface

for processor component thermal solutions, such as a heat sink. Figure 5 shows a sketch of the

processor package components and how they are assembled together. Refer to the mPGA604

Socket Design Guidelines for complete details on the mPGA604 socket.

The package components shown in Figure 5 include the following:

1. Integrated Heat Spreader (IHS)

2. Processor die

3. Substrate

4. Pin side capacitors

5. Package pin

6. Die Side Capacitors

Figure 5.

Processor Package Assembly Sketch

2

6

1

3

4

5

NOTE: This drawing is not to scale and is for reference only. The mPGA604 socket is not shown.

3.1

Package Mechanical Drawings

The package mechanical drawings are shown in Figure 6 and Figure 7. The drawings include

dimensions necessary to design a thermal solution for the processor. These dimensions include:

1. Package reference and tolerance dimensions (total height, length, width, etc.)

2. IHS parallelism and tilt

3. Pin dimensions

4. Top-side and back-side component keepout dimensions

5. Reference datums

6. All drawing dimensions are in mm [in.].

Datasheet

35

Figure 6.

Processor Package Drawing (Sheet 1 of 2)

36

Datasheet

Figure 7.

Processor Package Drawing (Sheet 2 of 2)

Datasheet

37

3.2

3.3

Processor Component Keepout Zones

The processor may contain components on the substrate that define component keepout zone

requirements. A thermal and mechanical solution design must not intrude into the required keepout

zones. Decoupling capacitors are typically mounted to either the topside or pin-side of the package

substrate. See Figure 7 for keepout zones.

Package Loading Specifications

Table 17 provides dynamic and static load specifications for the processor package. These

mechanical load limits should not be exceeded during heat sink assembly, mechanical stress testing

or standard drop and shipping conditions. The heat sink attach solutions must not include

continuous stress onto the processor with the exception of a uniform load to maintain the heat sink-

to-processor thermal interface. Also, any mechanical system or component testing should not

exceed these limits. The processor package substrate should not be used as a mechanical reference

or load-bearing surface for thermal or mechanical solutions.

Table 17.

Processor Loading Specifications

Parameter

Min.

Max.

Unit

Notes

Static

Compressive Load

44

10

222

50

N

lbf

1,2,3,4

44

10

288

65

N

lbf

1,2,3,5

1,3,4,6,7

1,3,5,6,7

1,3,8

Dynamic

Compressive Load

NA

222 N + 0.45 kg *100 G

50 lbf (static) + 1 lbm * 100 G

N

lbf

NA

288 N + 0.45 kg * 100 G

65 lbf (static) + 1 lbm * 100 G

N

lbf

Transient

NA

445

100

N

lbf

NOTES:

1. These specifications apply to uniform compressive loading in a direction perpendicular to the IHS top

surface.

2. This is the minimum and maximum static force that can be applied by the heat sink and retention solution to

maintain the heat sink and processor interface.

3. These specifications are based on limited testing for design characterization. Loading limits are for the

package only and do not include the limits of the processor socket.

4. This specification applies for thermal retention solutions that allow baseboard deflection.

5. This specification applies either for thermal retention solutions that prevent baseboard deflection or for the

Intel-enabled reference solution (CEK).

6. Dynamic loading is defined as an 11 ms duration average load superimposed on the static load requirement.

7. Experimentally validated test condition used a heat sink mass of 1 lbm (~0.45 kg) with 100 G acceleration

measured at heat sink mass. The dynamic portion of this specification in the product application can have

flexibility in specific values, but the ultimate product of mass times acceleration should not exceed this

validated dynamic load (1 lbm x 100 G = 100 lb). Allowable strain in the dynamic compressive load

specification is in addition to the strain allowed in static loading.

8. Transient loading is defined as a 2 second duration peak load superimposed on the static load requirement,

representative of loads experienced by the package during heat sink installation.

38

Datasheet

3.4

Package Handling Guidelines

Table 18 includes a list of guidelines on a package handling in terms of recommended maximum

loading on the processor IHS relative to a fixed substrate. These package handling loads may be

experienced during heat sink removal.

Table 18.

Package Handling Guidelines

Parameter

Maximum Recommended

Notes

Shear

356 N

80 lbf

1, 4, 5

Tensile

Torque

156 N

35 lbf

2, 4, 5

3, 4, 5

8 N-m

70 lbf-in

NOTES:

1. A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface.

2. A tensile load is defined as a pulling load applied to the IHS in a direction normal to the IHS surface.

3. A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the IHS top

surface.

4. These guidelines are based on limited testing for design characterization and incidental applications (one

time only).

5. Handling guidelines are for the package only and do not include the limits of the processor socket.

3.5

3.6

Package Insertion Specifications

The Low Voltage Intel^®Xeon™ processor with 800 MHz system bus can be inserted and removed

15 times from an mPGA604 socket, which meets the criteria outlined in the mPGA604 Socket

Design Guidelines.

Processor Mass Specifications

The typical mass of the Low Voltage Intel^®Xeon™ processor with 800 MHz system bus is

25 grams [0.88 oz.]. This mass [weight] includes all components which make up the entire

processor product.

3.7

Processor Materials

The Low Voltage Intel^®Xeon™ processor with 800 MHz system bus is assembled from several

components. The basic material properties are described in Table 19.

Table 19.

Processor Materials

Component

Material

Integrated Heat Spreader (IHS)

Substrate

Nickel over copper

Fiber-reinforced resin

Gold over nickel

Substrate Pins

Datasheet

39

3.8

Processor Markings

Figure 8 shows the topside markings and Figure 9 shows the bottom-side markings on the

processor. These diagrams are to aid in the identification of the Low Voltage Intel^®Xeon™

processor with 800 MHz system bus.

Figure 8.

Processor Top-Side Markings (Example)

2D Matrix

Includes ATPO and Serial

Number (front end mark)

Processor Name

i(m) ©’03

ATPO

Serial Number

Pin 1 Indicator

NOTES:

1. All characters will be in upper case.

2. Drawing is not to scale.

Figure 9.

Processor Bottom-Side Markings (Example)

Pin 1 Indicator

Pin Field

Speed/Cache/Bus/Voltage

Cavity

with

Components

3600DP/1MB/800/1.325V

S-Spec

Country of Assy

SL6NY COSTA RICA

C0096109-0021

Text Line1

Text Line2

Text Line3

FPO—Serial #

(13 characters)

NOTES:

1. All characters will be in upper case.

2. Drawing is not to scale.

40

Datasheet

3.9

Processor Pinout Coordinates

Figure 10 and Figure 11 show the top and bottom view of the processor pin coordinates,

respectively. The coordinates are referred to throughout the document to identify processor pins.

Figure 10.

Processor Pinout Coordinates, Top View

COMMON

CLOCK

COMMON

CLOCK

Async /

JTAG

ADDRESS

1

3

5

7

9

11 13

15 17 19

21 23 25

27

29

31

A

B

A

B

C

D

C

D

E

F

G

H

J

G

H

J

K

L

M

N

P

R

K

L

Intel® Xeon™

M

N

P

Processor

(800 MHz)

Top View

R

T

U

V

W

Y

U

V

W

Y

AA

AB

AC

AD

AB

AC

AD

AE

2

4

6

8

10 12 14

16 18

20 22

24 26 28

30

CLOCKS

DATA

= Signal

= Power

= Ground

= GTLREF

= Reserved/No Connect

= V_TT

Datasheet

41

Figure 11.

Processor Pinout Coordinates, Bottom View

Async /

JTAG

COMMON

CLOCK

COMMON

CLOCK

ADDRESS

31 29 27 25

23 21 19 17 15

13 11

9

7

5

3

1

A

B

A

B

C

D

C

D

E

F

G

H

J

G

H

J

K

L

M

N

P

R

K

L

M

Intel® Xeon™

Processor

(800 MHz)

Bottom View

N

P

R

T

U

V

U

V

W

Y

W

Y

AA

AB

AC

AB

AC

AD

AE

AD

AE

30

28 26

24 22

20 18

16 14 12

10

8

6

4

2

CLOCKS

DATA

= Signal

= Power

= Ground

= GTLREF

= Reserved/No Connect

= V_TT

42

Datasheet

4.0

Signal Definitions

4.1

Signal Definitions

Table 20.

Signal Definitions (Sheet 1 of 9)

Name

Type

Description

A[35:3]# (Address) define a 2³⁶-byte physical memory address space. In sub-phase 1 of

Notes

A[35:3]#

I/O

4

the address phase, these pins transmit the address of a transaction. In sub-phase 2,

these pins transmit transaction type information. These signals must connect the

appropriate pins of all agents on the front side bus. A[35:3]# are protected by parity

signals AP[1:0]#. A[35:3]# are source synchronous signals and are latched into the

receiving buffers by ADSTB[1:0]#.

On the active-to-inactive transition of RESET#, the processors sample a subset of the

A[35:3]# pins to determine their power-on configuration. See Section 7.1.

A20M#

I

If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit 20

(A20#) before looking up a line in any internal cache and before driving a read/write

transaction on the bus. Asserting A20M# emulates the 8086 processor's address wrap-

around at the 1 MB boundary. Assertion of A20M# is only supported in real mode.

3

A20M# is an asynchronous signal. However, to ensure recognition of this signal following

an I/O write instruction, it must be valid along with the TRDY# assertion of the

corresponding I/O write bus transaction.

ADS#

I/O

ADS# (Address Strobe) is asserted to indicate the validity of the transaction address on

the A[35:3]# pins. All bus agents observe the ADS# activation to begin parity checking,

protocol checking, address decode, internal snoop, or deferred reply ID match operations

associated with the new transaction. This signal must connect the appropriate pins on all

Low Voltage Intel^®Xeon™ processor with 800 MHz system bus agents.

4

ADSTB[1:0]#

Address strobes are used to latch A[35:3]# and REQ[4:0]# on their rising and falling

edge. Strobes are associated with signals as shown below.

Signals

Associated Strobes

REQ[4:0]#, A[16:3]#

A[35:17]#

ADSTB0#

ADSTB1#

AP[1:0]#

I/O

AP[1:0]# (Address Parity) are driven by the request initiator along with ADS#, A[35:3]#,

and the transaction type on the REQ[4:0]# pins. A correct parity signal is high if an even

number of covered signals are low and low if an odd number of covered signals are low.

This allows parity to be high when all the covered signals are high. AP[1:0]# should

connect the appropriate pins of all Low Voltage Intel^®Xeon™ processor with 800 MHz

system bus agents. The following table defines the coverage model of these signals.

4

Request Signals

Sub-Phase 1

Sub-Phase 2

A[35:24]#

A[23:3]#

AP0#

AP1#

AP0#

BCLK[1:0]

I

The differential bus clock pair BCLK[1:0] determines the front side bus frequency. All

processor front side bus agents must receive these signals to drive their outputs and

latch their inputs.

4

All external timing parameters are specified with respect to the rising edge of BCLK0

crossing V_CROSS

.

Datasheet

43

Table 20.

Signal Definitions (Sheet 2 of 9)

Name

Type

Description

Notes

BINIT#

I/O

BINIT# (Bus Initialization) may be observed and driven by all processor front side bus

4

agents and if used, must connect the appropriate pins of all such agents. If the BINIT#

driver is enabled during power on configuration, BINIT# is asserted to signal any bus

condition that prevents reliable future information.

If BINIT# observation is enabled during power-on configuration (see Figure 7.1) and

BINIT# is sampled asserted, symmetric agents reset their bus LOCK# activity and bus

request arbitration state machines. The bus agents do not reset their I/O Queue (IOQ)

and transaction tracking state machines upon observation of BINIT# assertion. Once the

BINIT# assertion has been observed, the bus agents will re-arbitrate for the front side

bus and attempt completion of their bus queue and IOQ entries.

If BINIT# observation is disabled during power-on configuration, a central agent may

handle an assertion of BINIT# as appropriate to the error handling architecture of the

system.

Since multiple agents may drive this signal at the same time, BINIT# is a wired-OR signal

which must connect the appropriate pins of all processor front side bus agents. In order

to avoid wired-OR glitches associated with simultaneous edge transitions driven by

multiple drivers, BINIT# is activated on specific clock edges and sampled on specific

clock edges

BNR#

I/O

BNR# (Block Next Request) is used to assert a bus stall by any bus agent who is unable

to accept new bus transactions. During a bus stall, the current bus owner cannot issue

any new transactions.

4

Since multiple agents might need to request a bus stall at the same time, BNR# is a

wired-OR signal which must connect the appropriate pins of all processor front side bus

agents. In order to avoid wired-OR glitches associated with simultaneous edge

transitions driven by multiple drivers, BNR# is activated on specific clock edges and

sampled on specific clock edges.

BOOT_

SELECT

I

The BOOT_SELECT input informs the processor whether the platform supports the Low

Voltage Intel^®Xeon™ processor with 800 MHz system bus. The processor will not

operate if this signal is low. This input has a weak pull-up to V_TT

.

BPM[5:0]#

I/O

BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They

are outputs from the processor which indicate the status of breakpoints and

programmable counters used for monitoring processor performance. BPM[5:0]# should

connect the appropriate pins of all front side bus agents.

3

BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. PRDY# is a

processor output used by debug tools to determine processor debug readiness.

BPM5# provides PREQ# (Probe Request) functionality for the TAP port. PREQ# is used

by debug tools to request debug operation of the processors.

BPM[5:4]# must be bussed to all bus agents.

These signals do not have on-die termination and must be terminated at the end agent.

BPRI#

I

BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor front

side bus. It must connect the appropriate pins of all processor front side bus agents.

Observing BPRI# active (as asserted by the priority agent) causes all other agents to

stop issuing new requests, unless such requests are part of an ongoing locked operation.

The priority agent keeps BPRI# asserted until all of its requests are completed, then

releases the bus by deasserting BPRI#.

4

44

Datasheet

Table 20.

Signal Definitions (Sheet 3 of 9)

Name

Type

Description

Notes

BR0#

BR[1:3]#¹

I/O

I

BR[3:0]# (Bus Request) drive the BREQ[3:0]# signals in the system. The BREQ[3:0]#

1,4

signals are interconnected in a rotating manner to individual processor pins. The tables

below provide the rotating interconnect between the processor and bus signals for 2-way

systems.

BR[1:0]# Signals Rotating Interconnect, 2-way system

Bus Signal Agent 0 Pins Agent 1 Pins

BREQ0#

BREQ1#

BR0#

BR1#

BR0#

BR2# and BR3# must not be used in 2-way

platform designs. However, they must still be

terminated.

During power-on configuration, the central agent must assert the BR0# bus signal. All

symmetric agents sample their BR[3:0]# pins on the active-to-inactive transition of

RESET#. The pin which the agent samples asserted determines it’s agent ID.

These signals do not have on-die termination and must be terminated at the end agent.

BSEL[1:0]

O

The BCLK[1:0] frequency select signals BSEL[1:0] are used to select the processor input

clock frequency. Table 3 defines the possible combinations of the signals and the

frequency associated with each combination. The required frequency is determined by

the processors, chipset, and clock synthesizer. All front side bus agents must operate at

the same frequency. The Low Voltage Intel^®Xeon™ processor with 800 MHz system bus

currently operates at a 800 MHz system bus frequency (200 MHz BCLK[1:0] frequency).

COMP[1:0]

D[63:0]#

I

COMP[1:0] must be terminated to V_SSon the baseboard using precision resistors. These

inputs configure the GTL+ drivers of the processor.

I/O

D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between

the processor front side bus agents, and must connect the appropriate pins on all such

agents. The data driver asserts DRDY# to indicate a valid data transfer.

4

D[63:0]# are quad-pumped signals, and will thus be driven four times in a common clock

period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and DSTBN[3:0]#.

Each group of 16 data signals correspond to a pair of one DSTBP# and one DSTBN#.

The following table shows the grouping of data signals to strobes and DBI#.

DSTBN#/

DSTBP#

Data Group

DBI#

D[15:0]#

D[31:16]#

D[47:32]#

D[63:48]#

0

1

2

3

0

1

2

3

Furthermore, the DBI# pins determine the polarity of the data signals. Each group of 16

data signals corresponds to one DBI# signal. When the DBI# signal is active, the

corresponding data group is inverted and therefore sampled active high.

Datasheet

45

Table 20.

Signal Definitions (Sheet 4 of 9)

Name

Type

Description

Notes

DBI[3:0]#

I/O

DBI[3:0]# are source synchronous and indicate the polarity of the D[63:0]# signals. The

4

DBI[3:0]# signals are activated when the data on the data bus is inverted. If more than

half the data bits, within a 16-bit group, would have been asserted electronically low, the

bus agent may invert the data bus signals for that particular sub-phase for that 16-bit

group.

DBI[3:0] Assignment To Data Bus

Bus Signal

Data Bus Signals

DBI0#

DBI1#

DBI2#

DBI3#

D[15:0]#

D[31:16]#

D[47:32]#

D[63:48]#

DBSY#

I/O

I

DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the

processor front side bus to indicate that the data bus is in use. The data bus is released

after DBSY# is deasserted. This signal must connect the appropriate pins on all

processor front side bus agents.

4

DEFER#

DEFER# is asserted by an agent to indicate that a transaction cannot be guaranteed in-

order completion. Assertion of DEFER# is normally the responsibility of the addressed

memory or I/O agent. This signal must connect the appropriate pins of all processor front

side bus agents.

DP[3:0]#

DRDY#

I/O

DP[3:0]# (Data Parity) provide parity protection for the D[63:0]# signals. They are driven

by the agent responsible for driving D[63:0]#, and must connect the appropriate pins of

all processor front side bus agents.

4

DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid

data on the data bus. In a multi-common clock data transfer, DRDY# may be deasserted

to insert idle clocks. This signal must connect the appropriate pins of all processor front

side bus agents.

DSTBN[3:0]#

I/O

Data strobe used to latch in D[63:0]#.

4

Signals

Associated Strobes

D[15:0]#, DBI0#

D[31:16]#, DBI1#

D[47:32]#, DBI2#

D[63:48]#, DBI3#

DSTBN0#

DSTBN1#

DSTBN2#

DSTBN3#

DSTBP[3:0]#

I/O

Data strobe used to latch in D[63:0]#.

4

Signals

Associated Strobes

D[15:0]#, DBI0#

D[31:16]#, DBI1#

D[47:32]#, DBI2#

D[63:48]#, DBI3#

DSTBP0#

DSTBP1#

DSTBP2#

DSTBP3#

46

Datasheet

Table 20.

Signal Definitions (Sheet 5 of 9)

Name

Type

Description

Notes

FERR#/PBE#

O

FERR#/PBE# (floating-point error/pending break event) is a multiplexed signal and its

3

meaning is qualified by STPCLK#. When STPCLK# is not asserted, FERR#/PBE#

indicates a floating-point error and will be asserted when the processor detects an

unmasked floating-point error. When STPCLK# is not asserted, FERR#/PBE# is similar

to the ERROR# signal on the Intel^®387 coprocessor, and is included for compatibility

with systems using MS-DOS*-type floating-point error reporting. When STPCLK# is

asserted, an assertion of FERR#/PBE# indicates that the processor has a pending break

event waiting for service. The assertion of FERR#/PBE# indicates that the processor

should be returned to the Normal state. For additional information on the pending break

event functionality, including the identification of support of the feature and enable/

disable information, refer to Volume 3 of the IA-32 Software Developer’s Manual and the

Intel^®Processor Identification and the CPUID Instruction application note.

This signal does not have on-die termination and must be terminated at the end

agent.

FORCEPR#

GTLREF

I

The FORCEPR# input can be used by the platform to force the Low Voltage Intel^®

Xeon™ processor with 800 MHz system bus to activate the Thermal Control Circuit

(TCC). The TCC will remain active until the system deasserts FORCEPR#.

GTLREF determines the signal reference level for GTL+ input pins. GTLREF is used by

the GTL+ receivers to determine if a signal is a logical 0 or a logical 1.

HIT#

I/O

HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results.

Any front side bus agent may assert both HIT# and HITM# together to indicate that it

requires a snoop stall, which can be continued by reasserting HIT# and HITM# together.

4

HITM#

Since multiple agents may deliver snoop results at the same time, HIT# and HITM# are

wired-OR signals which must connect the appropriate pins of all processor front side bus

agents. In order to avoid wired-OR glitches associated with simultaneous edge

transitions driven by multiple drivers, HIT# and HITM# are activated on specific clock

edges and sampled on specific clock edges.

IERR#

O

IERR# (Internal Error) is asserted by a processor as the result of an internal error.

Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the

processor front side bus. This transaction may optionally be converted to an external

error signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted

until the assertion of RESET#.

3

This signal does not have on-die termination and must be terminated at the end agent.

IGNNE#

I

IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a numeric

error and continue to execute non-control floating-point instructions. If IGNNE# is

deasserted, the processor generates an exception on a non-control floating-point

instruction if a previous floating-point instruction caused an error. IGNNE# has no effect

when the NE bit in control register 0 (CR0) is set.

IGNNE# is an asynchronous signal. However, to ensure recognition of this signal

following an I/O write instruction, it must be valid along with the TRDY# assertion of the

corresponding I/O write bus transaction.

INIT#

I

INIT# (Initialization), when asserted, resets integer registers inside all processors without

affecting their internal caches or floating-point registers. Each processor then begins

execution at the power-on Reset vector configured during power-on configuration. The

processor continues to handle snoop requests during INIT# assertion. INIT# is an

asynchronous signal and must connect the appropriate pins of all processor front side

bus agents.

3

If INIT# is sampled active on the active to inactive transition of RESET#, then the

processor executes its Built-in Self-Test (BIST).

Datasheet

47

Table 20.

Signal Definitions (Sheet 6 of 9)

Name

Type

Description

Notes

LINT[1:0]

I

LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all front side bus

3

agents. When the APIC functionality is disabled, the LINT0/INTR signal becomes INTR,

a maskable interrupt request signal, and LINT1/NMI becomes NMI, a non-maskable

interrupt. INTR and NMI are backward compatible with the signals of those names on the

Pentium^®processor. Both signals are asynchronous.

These signals must be software configured via BIOS programming of the APIC register

space to be used either as NMI/INTR or LINT[1:0]. Because the APIC is enabled by

default after Reset, operation of these pins as LINT[1:0] is the default configuration.

LOCK#

I/O

LOCK# indicates to the system that a transaction must occur atomically. This signal must

connect the appropriate pins of all processor front side bus agents. For a locked

sequence of transactions, LOCK# is asserted from the beginning of the first transaction

to the end of the last transaction.

4

When the priority agent asserts BPRI# to arbitrate for ownership of the processor front

side bus, it will wait until it observes LOCK# deasserted. This enables symmetric agents

to retain ownership of the processor front side bus throughout the bus locked operation

and ensure the atomicity of lock.

MCERR#

I/O

MCERR# (Machine Check Error) is asserted to indicate an unrecoverable error without a

bus protocol violation. It may be driven by all processor front side bus agents.

MCERR# assertion conditions are configurable at a system level. Assertion options are

defined by the following options:

•

Enabled or disabled.

Asserted, if configured, for internal errors along with IERR#.

Asserted, if configured, by the request initiator of a bus transaction after it observes

an error.

•

Asserted by any bus agent when it observes an error in a bus transaction.

For more details regarding machine check architecture, refer to the IA-32 Software

Developer’s Manual, Volume 3: System Programming Guide.

Since multiple agents may drive this signal at the same time, MCERR# is a wired-OR

signal which must connect the appropriate pins of all processor front side bus agents. In

order to avoid wired-OR glitches associated with simultaneous edge transitions driven by

multiple drivers, MCERR# is activated on specific clock edges and sampled on specific

clock edges.

ODTEN

I

ODTEN (On-die termination enable) should be connected to V_TTto enable on-die

termination for end bus agents. For middle bus agents, pull this signal down via a resistor

to ground to disable on-die termination. Whenever ODTEN is high, on-die termination will

be active, regardless of other states of the bus.

OPTIMIZED/

COMPAT#

I

This is an input pin to the processor to determine if the processor is in an optimized

platform or a compatible platform. This signal does includes a weak on-die pull-up to V_TT

.

PROCHOT#

O

PROCHOT# (Processor Hot) will go active when the processor temperature monitoring

sensor detects that the processor die temperature has reached its factory configured trip

point. This indicates that the processor Thermal Control Circuit (TCC) has been

activated, if enabled. See Section 6.2.3 for more details.

PWRGOOD

I

PWRGOOD (Power Good) is an input. The processor requires this signal to be a clean

indication that all processor clocks and power supplies are stable and within their

specifications. “Clean” implies that the signal will remain low (capable of sinking leakage

current), without glitches, from the time that the power supplies are turned on until they

come within specification. The signal must then transition monotonically to a high state.

PWRGOOD can be driven inactive at any time, but clocks and power must again be

stable before a subsequent rising edge of PWRGOOD. It must also meet the minimum

pulse width specification in Table 15, and be followed by a 1-10 ms RESET# pulse.

3

The PWRGOOD signal must be supplied to the processor; it is used to protect internal

circuits against voltage sequencing issues. It should be driven high throughout boundary

scan operation.

48

Datasheet

Table 20.

Signal Definitions (Sheet 7 of 9)

Name

Type

Description

Notes

REQ[4:0]#

I/O

REQ[4:0]# (Request Command) must connect the appropriate pins of all processor front

4

side bus agents. They are asserted by the current bus owner to define the currently

active transaction type. These signals are source synchronous to ADSTB[1:0]#. Refer to

the AP[1:0]# signal description for details on parity checking of these signals.

RESET#

I

Asserting the RESET# signal resets all processors to known states and invalidates their

internal caches without writing back any of their contents. For a power-on Reset,

RESET# must stay active for at least 1 ms after VCC and BCLK have reached their proper

specifications. On observing active RESET#, all front side bus agents will deassert their

outputs within two clocks. RESET# must not be kept asserted for more than 10 ms while

PWRGOOD is asserted.

4

A number of bus signals are sampled at the active-to-inactive transition of RESET# for

power-on configuration. These configuration options are described in the Section 7.1.

This signal does not have on-die termination and must be terminated at the end agent.

RS[2:0]#

RSP#

I

RS[2:0]# (Response Status) are driven by the response agent (the agent responsible for

completion of the current transaction), and must connect the appropriate pins of all

processor front side bus agents.

4

RSP# (Response Parity) is driven by the response agent (the agent responsible for

completion of the current transaction) during assertion of RS[2:0]#, the signals for which

RSP# provides parity protection. It must connect to the appropriate pins of all processor

front side bus agents.

A correct parity signal is high if an even number of covered signals are low and low if an

odd number of covered signals are low. While RS[2:0]# = 000, RSP# is also high, since

this indicates it is not being driven by any agent guaranteeing correct parity.

SKTOCC#

SLEW_CTRL

SLP#

O

I

SKTOCC# (Socket occupied) will be pulled to ground by the processor to indicate that

the processor is present. There is no connection to the processor silicon for this signal.

The front side bus slew rate control input, SLEW_CTRL, is used to establish distinct edge

rates for middle and end agents.

I

SLP# (Sleep), when asserted in Stop-Grant state, causes processors to enter the Sleep

state. During Sleep state, the processor stops providing internal clock signals to all units,

leaving only the Phase-Lock Loop (PLL) still operating. Processors in this state will not

recognize snoops or interrupts. The processor will only recognize the assertion of the

RESET# signal, deassertion of SLP#, and removal of the BCLK input while in Sleep

state. If SLP# is deasserted, the processor exits Sleep state and returns to Stop-Grant

state, restarting its internal clock signals to the bus and processor core units.

3

SMB_PRT

O

The SMBus present (SMB_PRT) pin is defined to inform the platform if the installed

processor includes SMBus components such as the integrated thermal sensor and the

processor information ROM (PIROM). This pin is tied to VSS by the processor if these

features are not present. Platforms using this pin should use a pull up resistor to the

appropriate voltage level for the logic tied to this pin. Because this pin does not connect

to the processor silicon, any platform voltage and termination value is acceptable.

SMI#

I

SMI# (System Management Interrupt) is asserted asynchronously by system logic. On

accepting a System Management Interrupt, processors save the current state and enter

System Management Mode (SMM). An SMI Acknowledge transaction is issued, and the

processor begins program execution from the SMM handler.

3

If SMI# is asserted during the deassertion of RESET# the processor will tristate its

outputs.

STPCLK#

I

STPCLK# (Stop Clock), when asserted, causes processors to enter a low power Stop-

Grant state. The processor issues a Stop-Grant Acknowledge transaction, and stops

providing internal clock signals to all processor core units except the front side bus and

APIC units. The processor continues to snoop bus transactions and service interrupts

while in Stop-Grant state. When STPCLK# is deasserted, the processor restarts its

internal clock to all units and resumes execution. The assertion of STPCLK# has no

effect on the bus clock; STPCLK# is an asynchronous input.

Datasheet

49

Table 20.

Signal Definitions (Sheet 8 of 9)

Name

Type

Description

Notes

TCK

I

TCK (Test Clock) provides the clock input for the processor Test Bus (also known as the

Test Access Port).

TDI

TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial

input needed for JTAG specification support.

TDO

O

TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the

serial output needed for JTAG specification support.

TEST_BUS

TESTHI[6:0]

I

Must be connected to all other processor TEST_BUS signals in the system.

All TESTHI inputs should be individually connected to V_TTvia a pull-up resistor which

matches the trace impedance. TESTHI[3:0] and TESTHI[6:5] may all be tied together

and pulled up to V_TTwith a single resistor if desired. However, usage of boundary scan

test will not be functional if these pins are connected together. TESTHI4 must always be

pulled up independently from the other TESTHI pins. For optimum noise margin, all pull-

up resistor values used for TESTHI[6:0] should have a resistance value within ±20% of

the impedance of the baseboard transmission line traces. For example, if the trace

impedance is 50 Ω, than a value between 40 Ω and 60 Ω should be used.

THERMDA

Other Thermal Diode Anode. See Section 6.2.7.

Other Thermal Diode Cathode. See Section 6.2.7.

THERMDC

THERMTRIP#

O

Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction temperature

has reached a temperature beyond which permanent silicon damage may occur.

Measurement of the temperature is accomplished through an internal thermal sensor.

Upon assertion of THERMTRIP#, the processor will shut off its internal clocks (thus

halting program execution) in an attempt to reduce the processor junction temperature.

To protect the processor its core voltage (V_CC) must be removed following the assertion

of THERMTRIP#.

2

Driving of the THERMTRIP# signals is enabled within 10 ms of the assertion of

PWRGOOD and is disabled on de-assertion of PWRGOOD. Once activated,

THERMTRIP# remains latched until PWRGOOD is de-asserted. While the de-assertion

of the PWRGOOD signal will de-assert THERMTRIP#, if the processor’s junction

temperature remains at or above the trip level, THERMTRIP# will again be asserted

within 10 ms of the assertion of PWRGOOD.

TMS

I

TMS (Test Mode Select) is a JTAG specification support signal used by debug tools.

This signal does not have on-die termination and must be terminated at the end agent.

TRDY#

TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a

write or implicit writeback data transfer. TRDY# must connect the appropriate pins of all

front side bus agents.

TRST#

I

TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low

during power on Reset.

V_CCA

I

V_CCAprovides isolated power for the analog portion of the internal processor core PLLs.

V_CCIOPLLprovides isolated power for digital portion of the internal processor core PLLs.

V_CCIOPLL

V_CCPLL

The on-die PLL filter solution will not be implemented on this platform. The V_CCPLLinput

should left unconnected.

VCCSENSE

VSSSENSE

O

VCCSENSE and VSSSENSE provide an isolated, low impedance connection to the

processor core power and ground. They can be used to sense or measure power near

the silicon with little noise.

VID[5:0]

VID[5:0] (Voltage ID) pins are used to support automatic selection of power supply

voltages (V_CC). These are open drain signals that are driven by the processor and must

be pulled up through a resistor. Conversely, the VR output must be disabled prior to the

voltage supply for these pins becomes invalid. The VID pins are needed to support

processor voltage specification variations. See Table 4 for definitions of these pins. The

VR must supply the voltage that is requested by these pins, or disable itself.

50

Datasheet

Table 20.

Signal Definitions (Sheet 9 of 9)

Name

Type

Description

Notes

VIDPWRGD

I

The processor requires this input to determine that the supply voltage for BSEL[1:0] and

VID[5:0] is stable and within specification.

V_SSA

V_SSAprovides an isolated, internal ground for internal PLL’s. Do not connect directly to

ground. This pin is to be connected to V_CCAand V_CCIOPLLthrough a discrete filter circuit.

V_TT

P

The front side bus termination voltage input pins. Refer to Table 9 for further details.

VTTEN

O

The VTTEN can be used as an output enable for the VTT regulator in the event an

incompatible processor is inserted into the platform. There is no connection to the

processor silicon for this signal and it must be pulled up through a resistor.

NOTES:

1. The Low Voltage Intel^®Xeon™ processor with 800 MHz system bus only supports BR0# and BR1#. However, platforms must

terminate BR2# and BR3# to V_TT

.

2. For this pin on Low Voltage Intel^®Xeon™ processor with 800 MHz system bus, the maximum number of symmetric agents is

one. Maximum number of central agents is zero.

3. For this pin on Low Voltage Intel^®Xeon™ processor with 800 MHz system bus, the maximum number of symmetric agents is

two. Maximum number of central agents is zero.

4. For this pin on Low Voltage Intel^®Xeon™ processor with 800 MHz system bus, the maximum number of symmetric agents is

two. Maximum number of central agents is one.

Datasheet

51

THIS PAGE INTENTIONALLY LEFT BLANK

52

Datasheet

5.0

Pin List

5.1

Low Voltage Intel^®Xeon™ Processor with 800 MHz System

Bus Pin Assignments

This section provides sorted pin lists in Table 21 and Table 22. Table 21 is a listing of all processor

pins ordered alphabetically by pin name. Table 22 is a listing of all processor pins ordered by pin

number.

Datasheet

53

5.1.1

Pin Listing by Pin Name

Table 21.

Pin Listing by Pin Name (Sheet 1 of 8)

No.

Signal

Buffer Type

No.

Signal

Buffer Type

Pin Name

Direction

Pin Name

Direction

A3#

A22

Source Sync I/O

AP1#

D9

Common Clk I/O

A4#

A20

B18

C18

A19

C17

D17

A13

B16

B14

B13

A12

C15

C14

D16

D15

F15

A10

B10

B11

C12

E14

D13

A9

BCLK0

BCLK1

BINIT#

BNR#

Y4

Sys Bus Clk

Input

A5#

W5

F11

F20

G7

A6#

Common Clk I/O

Power/Other Input

Common Clk I/O

Common Clk Input

Common Clk I/O

Common Clk Input

Power/Other Output

A7#

A8#

BOOT_SELECT

BPM0#

BPM1#

BPM2#

BPM3#

BPM4#

BPM5#

BPRI#

BR0#

BR1#

BR2# ¹

BR3# ¹

BSEL0

BSEL1

COMP0

COMP1

D0#

A9#

F6

A10#

A11#

A12#

A13#

A14#

A15#

A16#

A17#

A18#

A19#

A20#

A21#

A22#

A23#

A24#

A25#

A26#

A27#

A28#

A29#

A30#

A31#

A32#

A33#

A34#

A35#

A20M#

ADS#

ADSTB0#

ADSTB1#

AP0#

F8

E7

F5

E8

E4

D23

D20

F12

E11

D10

AA3

AB3

AD16 Power/Other Input

E16

Y26

Power/Other Input

Source Sync I/O

D1#

AA27 Source Sync I/O

Y24 Source Sync I/O

D2#

B8

D3#

AA25 Source Sync I/O

AD27 Source Sync I/O

E13

D12

C11

B7

D4#

D5#

Y23

Source Sync I/O

D6#

AA24 Source Sync I/O

AB26 Source Sync I/O

AB25 Source Sync I/O

AB23 Source Sync I/O

AA22 Source Sync I/O

AA21 Source Sync I/O

AB20 Source Sync I/O

AB22 Source Sync I/O

AB19 Source Sync I/O

AA19 Source Sync I/O

AE26 Source Sync I/O

D7#

A6

D8#

A7

D9#

C9

D10#

C8

D11#

F27

D19

F17

F14

E10

Async GTL+

Input

D12#

Common Clk I/O

Source Sync I/O

Common Clk I/O

D13#

D14#

D15#

D16#

54

Datasheet

Table 21.

Pin Listing by Pin Name (Sheet 2 of 8)

No.

Signal

Buffer Type

No.

Signal

Buffer Type

Pin Name

Direction

Pin Name

Direction

D17#

D18#

D19#

D20#

D21#

D22#

D23#

D24#

D25#

D26#

D27#

D28#

D29#

D30#

D31#

D32#

D33#

D34#

D35#

D36#

D37#

D38#

D39#

D40#

D41#

D42#

D43#

D44#

D45#

D46#

D47#

D48#

D49#

D50#

D51#

D52#

D53#

D54#

D55#

D56#

AC26 Source Sync I/O

AD25 Source Sync I/O

AE25 Source Sync I/O

AC24 Source Sync I/O

AD24 Source Sync I/O

AE23 Source Sync I/O

AC23 Source Sync I/O

AA18 Source Sync I/O

AC20 Source Sync I/O

AC21 Source Sync I/O

AE22 Source Sync I/O

AE20 Source Sync I/O

AD21 Source Sync I/O

AD19 Source Sync I/O

AB17 Source Sync I/O

AB16 Source Sync I/O

AA16 Source Sync I/O

AC17 Source Sync I/O

AE13 Source Sync I/O

AD18 Source Sync I/O

AB15 Source Sync I/O

AD13 Source Sync I/O

AD14 Source Sync I/O

AD11 Source Sync I/O

AC12 Source Sync I/O

AE10 Source Sync I/O

AC11 Source Sync I/O

D57#

D58#

D59#

D60#

D61#

D62#

D63#

AD7

AE7

AC6

AC5

AA8

Y9

Source Sync I/O

Common Clk I/O

Common Clk Input

AB6

F18

C23

DBSY#

DEFER#

DBI0#

AC27 Source Sync I/O

AD22 Source Sync I/O

AE12 Source Sync I/O

DBI1#

DBI2#

DBI3#

AB9

Source Sync I/O

DP0#

AC18 Common Clk I/O

AE19 Common Clk I/O

AC15 Common Clk I/O

AE17 Common Clk I/O

DP1#

DP2#

DP3#

DRDY#

DSTBN0#

DSTBN1#

DSTBN2#

DSTBN3#

DSTBP0#

DSTBP1#

DSTBP2#

DSTBP3#

FERR#/PBE#

FORCEPR#

GTLREF

HIT#

E18

Y21

Y18

Y15

Y12

Y20

Y17

Y14

Y11

E27

A15

W23

W9

Common Clk I/O

Source Sync I/O

Async GTL+

Output

Input

AE9

Source Sync I/O

AD10 Source Sync I/O

Power/Other Input

Common Clk I/O

AD8

AC9

Source Sync I/O

F23

F9

AA13 Source Sync I/O

AA14 Source Sync I/O

AC14 Source Sync I/O

AB12 Source Sync I/O

AB13 Source Sync I/O

AA11 Source Sync I/O

AA10 Source Sync I/O

AB10 Source Sync I/O

E22

A23

E5

HITM#

IERR#

Async GTL+

Output

IGNNE#

INIT#

C26

D6

Input

LINT0/INTR

LINT1/NMI

LOCK#

B24

G23

A17

AC8

Source Sync I/O

Common Clk I/O

Datasheet

55

Table 21.

Pin Listing by Pin Name (Sheet 3 of 8)

No.

Signal

Buffer Type

No.

Signal

Buffer Type

Pin Name

Direction

Pin Name

Direction

MCERR#

N/C

D7

Y29

Common Clk I/O

TCK

TDI

E24

TAP

Input

N/C

C24

E25

A16

W6

Input

N/C

AA28 N/C

AA29 N/C

AB28 N/C

AB29 N/C

AC28 N/C

AC29 N/C

AD28 N/C

AD29 N/C

AE30 N/C

TDO

Output

N/C

TEST_BUS

TESTHI0

TESTHI1

TESTHI2

TESTHI3

TESTHI4

TESTHI5

TESTHI6

THERMDA

THERMDC

THERMTRIP#

TMS

Power/Other Input

Power/Other Output

N/C

W7

N/C

W8

N/C

Y6

N/C

AA7

AD5

AE5

Y27

Y28

F26

A25

E19

F24

A2

N/C

ODTEN

B5

Power/Other Input

OPTIMIZED/COMPAT# C1

PROCHOT#

PWRGOOD

REQ0#

B25

Async GTL+

Output

Input

Async GTL+

TAP

Output

Input

AB7

B19

B21

C21

C20

B22

A26

D25

W3

Source Sync I/O

TRDY#

TRST#

VCC

Common Clk Input

REQ1#

TAP

Input

REQ2#

Power/Other

REQ3#

VCC

A8

REQ4#

VCC

A14

A18

A24

A28

A30

B6

Reserved

RESET#

RS0#

Reserved

VCC

Reserved

VCC

Y3

VCC

AC1

VCC

AE15 Reserved

AE16 Reserved

AE28 Reserved

AE29 Reserved

VCC

B20

B26

B29

B31

C2

VCC

Y8

Common Clk Input

VCC

E21

D22

F21

C6

VCC

C4

RS1#

Common Clk Input

Power/Other Output

VCC

C16

C22

C28

C30

D1

RS2#

VCC

RSP#

VCC

SKTOCC#

SLP#

A3

VCC

AE6

Async GTL+

Input

VCC

SLEW_CTRL

SMB_PRT

SMI#

AC30 Power/Other Input

VCC

D8

AE4

C27

D4

Power/Other Output

VCC

D14

D18

D24

Async GTL+

Input

VCC

STPCLK#

VCC

56

Datasheet

Table 21.

Pin Listing by Pin Name (Sheet 4 of 8)

No.

Signal

Buffer Type

No.

Signal

Buffer Type

Pin Name

Direction

Pin Name

Direction

VCC

D29

D31

E2

Power/Other

VCC

K1

Power/Other

K3

K5

E6

K7

E20

E26

E28

E30

F1

K9

K23

K25

K27

K29

K31

L2

F4

F16

F22

F29

F31

G2

L4

L6

L8

L24

L26

L28

L30

M1

G4

G6

G8

G24

G26

G28

G30

H1

M3

M5

M7

M9

H3

M23

M25

M27

M29

M31

N1

H5

H7

H9

H23

H25

H27

H29

H31

J2

N3

N5

N7

N9

J4

N23

N25

N27

N29

N31

P2

J6

J8

J24

J26

J28

J30

P4

Datasheet

57

Table 21.

Pin Listing by Pin Name (Sheet 5 of 8)

No.

Signal

Buffer Type

No.

Signal

Buffer Type

Pin Name

Direction

Pin Name

Direction

VCC

P6

Power/Other

VCC

VCCA

V28

Power/Other

P8

V30

W1

P24

P26

P28

P30

R1

W25

W27

W29

W31

Y2

R3

R5

Y16

Y22

Y30

AA1

AA4

AA6

R7

R9

R23

R25

R27

R29

R31

T2

AA20 Power/Other

AA26 Power/Other

AA31 Power/Other

T4

AB2

AB8

Power/Other

T6

T8

AB14 Power/Other

AB18 Power/Other

AB24 Power/Other

AB30 Power/Other

T24

T26

T28

T30

U1

AC3

AC4

Power/Other

U3

AC16 Power/Other

AC22 Power/Other

AC31 Power/Other

U5

U7

U9

AD2

AD6

Power/Other

U23

U25

U27

U29

U31

V2

AD20 Power/Other

AD26 Power/Other

AD30 Power/Other

AE3

AE8

Power/Other

V4

AE14 Power/Other

AE18 Power/Other

AE24 Power/Other

V6

V8

V24

V26

AB4

AD4

Power/Other Input

VCCIOPLL

58

Datasheet

Table 21.

Pin Listing by Pin Name (Sheet 6 of 8)

No.

Signal

Buffer Type

No.

Signal

Buffer Type

Pin Name

Direction

Pin Name

Direction

VCCPLL

VCCSENSE

VID0

VID1

VID2

VID3

VID4

VID5

VIDPWRGD

VSS

AD1

B27

F3

Power/Other Input

Power/Other Output

Power/Other Input

Power/Other

VSS

E31

Power/Other

F2

F7

E3

F13

F19

F25

F28

F30

G1

D3

C3

B3

A1

B1

A5

G3

VSS

A11

A21

A27

A29

A31

B2

Power/Other

G5

VSS

Power/Other

G9

VSS

Power/Other

G25

G27

G29

G31

H2

VSS

Power/Other

VSS

Power/Other

VSS

Power/Other

VSS

B9

Power/Other

VSS

B15

B17

B23

B28

B30

C7

Power/Other

H4

VSS

Power/Other

H6

VSS

Power/Other

H8

VSS

Power/Other

H24

H26

H28

H30

J1

VSS

Power/Other

VSS

Power/Other

VSS

C13

C19

C25

C29

C31

D2

Power/Other

VSS

Power/Other

VSS

Power/Other

J3

VSS

Power/Other

J5

VSS

Power/Other

J7

VSS

Power/Other

J9

VSS

D5

Power/Other

J23

J25

J27

J29

J31

K2

VSS

D11

D21

D27

D28

D30

E9

Power/Other

VSS

Power/Other

VSS

Power/Other

VSS

Power/Other

VSS

Power/Other

VSS

Power/Other

K4

VSS

E15

E17

E23

E29

Power/Other

K6

VSS

Power/Other

K8

VSS

Power/Other

K24

K26

VSS

Power/Other

Datasheet

59

Table 21.

Pin Listing by Pin Name (Sheet 7 of 8)

No.

Signal

Buffer Type

No.

Signal

Buffer Type

Pin Name

Direction

Pin Name

Direction

VSS

K28

Power/Other

VSS

R6

Power/Other

K30

L1

R8

R24

R26

R28

R30

T1

L3

L5

L7

L9

L23

L25

L27

L29

L31

M2

M4

M6

M8

M24

M26

M28

M30

N2

T3

T5

T7

T9

T23

T25

T27

T29

T31

U2

U4

U6

U8

U24

U26

U28

U30

V1

N4

N6

N8

N24

N26

N28

N30

P1

V3

V5

V7

V9

P3

V23

V25

V27

V29

V31

W2

W4

W24

W26

W28

W30

P5

P7

P9

P23

P25

P27

P29

P31

R2

R4

60

Datasheet

Table 21.

Pin Listing by Pin Name (Sheet 8 of 8)

No.

Signal

Buffer Type

No.

Signal

Buffer Type

Pin Name

Direction

Pin Name

Direction

VSS

Y1

Power/Other

VSS

VSSA

AD3

AD9

Power/Other

Y5

Y7

AD15 Power/Other

AD17 Power/Other

AD23 Power/Other

AD31 Power/Other

Y13

Y19

Y25

Y31

AA2

AA9

AE2

Power/Other

AE11 Power/Other

AE21 Power/Other

AE27 Power/Other

AA15 Power/Other

AA17 Power/Other

AA23 Power/Other

AA30 Power/Other

AA5

D26

A4

Power/Other Input

Power/Other Output

VSSSENSE

VTT

Power/Other

AB1

AB5

Power/Other

VTT

B4

VTT

C5

AB11 Power/Other

AB21 Power/Other

AB27 Power/Other

AB31 Power/Other

VTT

B12

C10

E12

F10

Y10

VTT

AC2

AC7

Power/Other

VTT

AA12 Power/Other

AC10 Power/Other

AD12 Power/Other

AC13 Power/Other

AC19 Power/Other

AC25 Power/Other

VTT

VTTEN

E1

Power/Other Output

NOTE: In systems using the Low Voltage Intel^®Xeon™ processor with 800 MHz system bus, the system designer must pull-up

these signals to the processor V_TT

.

Datasheet

61

5.1.2

Pin Listing by Pin Number

Table 22.

Pin Listing by Pin Number (Sheet 1 of 8)

No.

Signal

Buffer Type

No.

Signal

Buffer Type

Pin Name

Direction

Pin Name

Direction

A1

VID5

VCC

Power/Other Output

Power/Other

B8

A27#

VSS

A21#

A22#

VTT

Source Sync I/O

Power/Other

A2

B9

A3

SKTOCC#

VTT

Power/Other Output

Power/Other

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

B31

C1

Source Sync I/O

Power/Other

A4

A5

VSS

Power/Other

A6

A32#

Source Sync I/O

Power/Other

A13#

A12#

VSS

A11#

VSS

A5#

Source Sync I/O

Power/Other

A7

A33#

A8

VCC

A9

A26#

Source Sync I/O

Power/Other

Source Sync I/O

Power/Other

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

B1

A20#

VSS

Source Sync I/O

Power/Other

A14#

Source Sync I/O

Power/Other

REQ0#

VCC

A10#

VCC

REQ1#

REQ4#

VSS

Source Sync I/O

Power/Other

FORCEPR#

TEST_BUS

LOCK#

VCC

Async GTL+

Input

Power/Other Input

Common Clk I/O

Power/Other

LINT0/INTR

PROCHOT#

VCC

Async GTL+

Input

Power/Other Output

Power/Other

A7#

Source Sync I/O

Power/Other

A4#

VCCSENSE

VSS

Power/Other Output

Power/Other

VSS

A3#

Source Sync I/O

Common Clk I/O

Power/Other

VCC

Power/Other

HITM#

VCC

VSS

Power/Other

VCC

Power/Other

TMS

TAP

Input

OPTIMIZED/COMPAT# Power/Other Input

Reserved

VSS

Reserved

C2

VCC

VID3

VCC

VTT

Power/Other

C3

Power/Other Output

Power/Other

VCC

C4

VSS

C5

Power/Other

VCC

C6

RSP#

VSS

A35#

A34#

VTT

Common Clk

Power/Other

Input

VSS

C7

VIDPWRGD

VSS

Power/Other Input

Power/Other

C8

Source Sync I/O

Power/Other

B2

C9

B3

VID4

Power/Other Output

Power/Other

C10

C11

C12

C13

C14

B4

VTT

A30#

A23#

VSS

A16#

Source Sync I/O

Power/Other

B5

OTDEN

VCC

Power/Other Input

Power/Other

B6

B7

A31#

Source Sync I/O

62

Datasheet

Table 22.

Pin Listing by Pin Number (Sheet 2 of 8)

No.

Signal

Buffer Type

No.

Signal

Buffer Type

Pin Name

Direction

Pin Name

Direction

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

C25

C26

C27

C28

C29

C30

C31

D1

A15#

Source Sync I/O

Power/Other

D24

VCC

Power/Other

Reserved

VCC

A8#

A6#

VSS

D25

D26

D27

D28

D29

D30

D31

E1

Reserved

VSSSENSE

VSS

Reserved

Source Sync I/O

Power/Other

Power/Other Output

Power/Other

VSS

Power/Other

REQ3#

REQ2#

VCC

Source Sync I/O

Power/Other

VCC

Power/Other

VSS

Power/Other

VCC

Power/Other

DEFER#

TDI

Common Clk Input

VTTEN

VCC

Power/Other Output

Power/Other

TAP

Input

E2

VSS

Power/Other

Async GTL+

Power/Other

E3

VID1

Power/Other Output

Common Clk I/O

IGNNE#

SMI#

VCC

Input

E4

BPM5#

IERR#

VCC

E5

Async GTL+

Power/Other

Output

E6

VSS

E7

BPM2#

BPM4#

VSS

Common Clk I/O

Power/Other

VCC

E8

VSS

E9

VCC

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

E21

E22

E23

E24

E25

E26

E27

E28

E29

E30

E31

F1

AP0#

BR2#¹

VTT

Common Clk I/O

Common Clk Input

Power/Other

D2

VSS

D3

VID2

Power/Other Output

D4

STPCLK#

VSS

Async GTL+

Power/Other

Async GTL+

Input

A28#

Source Sync I/O

Power/Other

D5

A24#

D6

INIT#

MCERR#

VCC

Input

VSS

D7

Common Clk I/O

Power/Other

COMP1

VSS

Power/Other Input

Power/Other

D8

D9

AP1#

BR3# ¹

VSS

Common Clk I/O

Common Clk Input

Power/Other

DRDY#

TRDY#

VCC

Common Clk I/O

Common Clk Input

Power/Other

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

A29#

A25#

VCC

Source Sync I/O

Power/Other

RS0#

HIT#

Common Clk Input

Common Clk I/O

Power/Other

VSS

A18#

A17#

A9#

Source Sync I/O

Power/Other

TCK

TAP

Input

TDO

TAP

Output

VCC

Power/Other

Async GTL+

Power/Other

VCC

FERR#/PBE#

VCC

Output

ADS#

BR0#

VSS

Common Clk I/O

Power/Other

VSS

VCC

RS1#

BPRI#

Common Clk Input

VSS

VCC

Datasheet

63

Table 22.

Pin Listing by Pin Number (Sheet 3 of 8)

No.

Signal

Buffer Type

No.

Signal

Buffer Type

Pin Name

Direction

Pin Name

Direction

F2

VSS

Power/Other

G24

G25

G26

G27

G28

G29

G30

G31

H1

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

Power/Other

F3

VID0

VCC

Power/Other Output

Power/Other

F4

F5

BPM3#

BPM0#

VSS

Common Clk I/O

Power/Other

F6

F7

F8

BPM1#

GTLREF

VTT

Common Clk I/O

Power/Other Input

Power/Other

F9

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

F20

F21

F22

F23

F24

F25

F26

F27

F28

F29

F30

F31

G1

BINIT#

BR1#

Common Clk I/O

Common Clk Input

Power/Other

H2

H3

VSS

H4

ADSTB1#

A19#

Source Sync I/O

Power/Other

H5

H6

VCC

H7

ADSTB0#

DBSY#

VSS

Source Sync I/O

Common Clk I/O

Power/Other

H8

H9

H23

H24

H25

H26

H27

H28

H29

H30

H31

J1

BNR#

RS2#

Common Clk I/O

Common Clk Input

Power/Other

VCC

GTLREF

TRST#

VSS

Power/Other Input

TAP

Input

Power/Other

Async GTL+

Power/Other

THERMTRIP#

A20M#

VSS

Output

Input

VCC

J2

VSS

J3

VCC

J4

VSS

J5

G2

VCC

J6

G3

VSS

J7

G4

VCC

J8

G5

VSS

J9

G6

VCC

J23

J24

J25

J26

J27

G7

BOOT_SELECT

VCC

Power/Other Input

Power/Other

G8

G9

VSS

Power/Other

G23

LINT1/NMI

Async GTL+

Input

64

Datasheet

Table 22.

Pin Listing by Pin Number (Sheet 4 of 8)

No.

Signal

Buffer Type

No.

Signal

Buffer Type

Pin Name

Direction

Pin Name

Direction

J28

J29

J30

J31

K1

VCC

Power/Other

M1

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

Power/Other

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

M2

M3

M4

M5

K2

M6

K3

M7

K4

M8

K5

M9

K6

M23

M24

M25

M26

M27

M28

M29

M30

M31

N1

K7

K8

K9

K23

K24

K25

K26

K27

K28

K29

K30

K31

L1

N2

N3

N4

N5

L2

N6

L3

N7

L4

N8

L5

N9

L6

N23

N24

N25

N26

N27

N28

N29

N30

N31

P1

L7

L8

L9

L23

L24

L25

L26

L27

L28

L29

L30

L31

P2

P3

P4

Datasheet

65

Table 22.

Pin Listing by Pin Number (Sheet 5 of 8)

No.

Signal

Buffer Type

No.

Signal

Buffer Type

Pin Name

Direction

Pin Name

Direction

P5

VSS

Power/Other

T9

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

Power/Other

P6

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

T23

T24

T25

T26

T27

T28

T29

T30

T31

U1

P7

P8

P9

P23

P24

P25

P26

P27

P28

P29

P30

P31

R1

U2

U3

U4

U5

R2

U6

R3

U7

R4

U8

R5

U9

R6

U23

U24

U25

U26

U27

U28

U29

U30

U31

V1

R7

R8

R9

R23

R24

R25

R26

R27

R28

R29

R30

R31

T1

V2

V3

V4

V5

T2

V6

T3

V7

T4

V8

T5

V9

T6

V23

V24

V25

T7

T8

66

Datasheet

Table 22.

Pin Listing by Pin Number (Sheet 6 of 8)

No.

Signal

Buffer Type

No.

Signal

Buffer Type

Pin Name

Direction

Pin Name

DSTBP1#

Direction

V26

V27

V28

V29

V30

V31

W1

VCC

Power/Other

Reserved

Y17

Source Sync I/O

Power/Other

VSS

VCC

VSS

VCC

VSS

VCC

VSS

Y18

Y19

Y20

Y21

Y22

Y23

Y24

Y25

Y26

Y27

Y28

Y29

Y30

Y31

AA1

AA2

AA3

AA4

AA5

AA6

AA7

AA8

AA9

DSTBN1#

VSS

DSTBP0#

DSTBN0#

VCC

Source Sync I/O

Power/Other

D5#

Source Sync I/O

Power/Other

W2

D2#

W3

Reserved

VSS

Reserved

Input

VSS

W4

Power/Other

Sys Bus Clk

D0#

Source Sync I/O

Power/Other Output

W5

BCLK1

TESTHI0

TESTHI1

TESTHI2

GTLREF

VSS

THERMDA

THERMDC

N/C

W6

Power/Other Input

Power/Other

W7

N/C

W8

VCC

Power/Other

W9

VSS

W23

W24

W25

W26

W27

W28

W29

W30

W31

Y1

VCC

VSS

VCC

Power/Other

BSEL0

VCC

Power/Other Output

Power/Other

VSS

Power/Other

VCC

Power/Other

VSSA

VCC

Power/Other Input

Power/Other

VSS

Power/Other

VCC

Power/Other

TESTHI4

D61#

Power/Other Input

Source Sync I/O

Power/Other

VSS

Power/Other

VCC

Power/Other

VSS

Power/Other

AA10 D54#

AA11 D53#

AA12 VTT

AA13 D48#

AA14 D49#

AA15 VSS

AA16 D33#

AA17 VSS

AA18 D24#

AA19 D15#

AA20 VCC

AA21 D11#

AA22 D10#

AA23 VSS

AA24 D6#

AA25 D3#

Source Sync I/O

Power/Other

Y2

VCC

Power/Other

Y3

Reserved

BCLK0

VSS

Reserved

Input

Y4

Sys Bus Clk

Power/Other

Source Sync I/O

Power/Other

Y5

Y6

TESTHI3

VSS

Power/Other Input

Power/Other

Y7

Source Sync I/O

Power/Other

Y8

RESET#

D62#

Common Clk Input

Source Sync I/O

Power/Other

Y9

Source Sync I/O

Power/Other

Y10

Y11

Y12

Y13

Y14

Y15

Y16

VTT

DSTBP3#

DSTBN3#

VSS

Source Sync I/O

Power/Other

Source Sync I/O

Power/Other

DSTBP2#

DSTBN2#

VCC

Source Sync I/O

Power/Other

Source Sync I/O

Datasheet

67

Table 22.

Pin Listing by Pin Number (Sheet 7 of 8)

No.

Signal

Buffer Type

No.

Signal

Buffer Type

Pin Name

Direction

Pin Name

Direction

AA26 VCC

AA27 D1#

AA28 N/C

AA29 N/C

AA30 VSS

AA31 VCC

Power/Other

AC4

AC5

AC6

AC7

AC8

AC9

VCC

D60#

D59#

VSS

Power/Other

Source Sync I/O

Power/Other

N/C

Power/Other

D56#

D47#

Source Sync I/O

Power/Other

AB1

AB2

AB3

AB4

AB5

AB6

AB7

AB8

AB9

VSS

AC10 VTT

AC11 D43#

AC12 D41#

AC13 VSS

AC14 D50#

AC15 DP2#

AC16 VCC

AC17 D34#

AC18 DP0#

AC19 VSS

AC20 D25#

AC21 D26#

AC22 VCC

AC23 D23#

AC24 D20#

AC25 VSS

AC26 D17#

AC27 DBI0#

AC28 N/C

AC29 N/C

VCC

Source Sync I/O

Power/Other

BSEL1

VCCA

VSS

Power/Other Output

Power/Other Input

Power/Other

Source Sync I/O

Common Clk I/O

Power/Other

D63#

Source Sync I/O

PWRGOOD

VCC

Async GTL+

Power/Other

Input

Source Sync I/O

Common Clk I/O

Power/Other

DBI3#

Source Sync I/O

Power/Other

AB10 D55#

AB11 VSS

AB12 D51#

AB13 D52#

AB14 VCC

AB15 D37#

AB16 D32#

AB17 D31#

AB18 VCC

AB19 D14#

AB20 D12#

AB21 VSS

AB22 D13#

AB23 D9#

AB24 VCC

AB25 D8#

AB26 D7#

AB27 VSS

AB28 N/C

AB29 N/C

AB30 VCC

AB31 VSS

Source Sync I/O

Power/Other

Source Sync I/O

Power/Other

Source Sync I/O

Power/Other

Source Sync I/O

Power/Other

Source Sync I/O

Power/Other

N/C

AC30 SLEW_CTRL

AC31 VCC

Power/Other Input

Power/Other

Source Sync I/O

Power/Other

AD1

AD2

AD3

AD4

AD5

AD6

AD7

AD8

AD9

VCCPLL

VCC

Power/Other Input

Power/Other

Source Sync I/O

Power/Other

VSS

Power/Other

VCCIOPLL

TESTHI5

VCC

Power/Other Input

Power/Other

N/C

D57#

Source Sync I/O

Power/Other

Reserved

Power/Other

D46#

VSS

AC1

AC2

AC3

Reserved

AD10 D45#

AD11 D40#

AD12 VTT

Source Sync I/O

Power/Other

VSS

VCC

68

Datasheet

Table 22.

Pin Listing by Pin Number (Sheet 8 of 8)

No.

Signal

Buffer Type

No.

Signal

Buffer Type

Pin Name

Direction

Pin Name

Direction

AD13 D38#

AD14 D39#

AD15 VSS

Source Sync I/O

Power/Other

AE7

AE8

AE9

D58#

VCC

D44#

Source Sync I/O

Power/Other

Source Sync I/O

Power/Other

AD16 COMP0

AD17 VSS

AD18 D36#

AD19 D30#

AD20 VCC

AD21 D29#

AD22 DBI1#

AD23 VSS

AD24 D21#

AD25 D18#

AD26 VCC

AD27 D4#

AD28 N/C

AD29 N/C

AD30 VCC

AD31 VSS

Power/Other Input

Power/Other

AE10 D42#

AE11 VSS

AE12 DBI2#

AE13 D35#

AE14 VCC

Source Sync I/O

Power/Other

Source Sync I/O

Power/Other

Source Sync I/O

Power/Other

AE15 Reserved

AE16 Reserved

AE17 DP3#

AE18 VCC

Reserved

Common Clk I/O

Power/Other

Source Sync I/O

Power/Other

AE19 DP1#

AE20 D28#

AE21 VSS

Common Clk I/O

Source Sync I/O

Power/Other

Source Sync I/O

N/C

AE22 D27#

AE23 D22#

AE24 VCC

Source Sync I/O

Power/Other

N/C

Power/Other

AE25 D19#

AE26 D16#

AE27 VSS

Source Sync I/O

Power/Other

AE2

AE3

AE4

AE5

AE6

VSS

VCC

SMB_PRT

TESTHI6

SLP#

Power/Other Output

Power/Other Input

AE28 Reserved

AE29 Reserved

AE30 N/C

Reserved

N/C

Reserved

Async GTL+

Input

N/C

NOTE: In systems using the Low Voltage Intel^®Xeon™ processor with 800 MHz system bus, the system designer must pull-up

these signals to the processor V_TT

.

Datasheet

69

THIS PAGE INTENTIONALLY LEFT BLANK

70

Datasheet

6.0

Thermal Specifications

6.1

Package Thermal Specifications

The Low Voltage Intel^®Xeon™ processor with 800 MHz system bus requires a thermal solution to

maintain temperatures within operating limits. Any attempt to operate the processor outside these

operating limits may result in permanent damage to the processor and potentially other components

within the system. As processor technology changes, thermal management becomes increasingly

crucial when building computer systems. Maintaining the proper thermal environment is key to

reliable, long-term system operation.

A complete solution includes both component and system level thermal management features.

Component level thermal solutions can include active or passive heat sinks attached to the

processor Integrated Heat Spreader (IHS). Typical system level thermal solutions may consist of

system fans combined with ducting and venting.

For more information on designing a component level thermal solution, refer to the Low Voltage

Intel^®Xeon™ Processor with 800 MHz System Bus in Embedded Applications

Thermal/Mechanical Design Guidelines.

6.1.1

Thermal Specifications

To allow the optimal operation and long-term reliability of Intel processor-based systems, the

processor must remain within the minimum and maximum case temperature (T

) specifications

CASE

as defined by the applicable thermal profile (see Table 23 and Figure 12). Thermal solutions not

designed to provide this level of thermal capability may affect the long-term reliability of the

processor and system. For more details on thermal solution design, please refer to the appropriate

processor thermal/mechanical design guideline.

The Low Voltage Intel^®Xeon™ processor with 800 MHz system bus introduces a new

methodology for managing processor temperatures which is intended to support acoustic noise

reduction through fan speed control and assure processor reliability. Selection of the appropriate

fan speed will be based on the temperature reported by the processor’s Thermal Diode. If the diode

temperature is greater than or equal to Tcontrol (see Section 6.2.6), then the processor case

temperature must remain at or below the temperature as specified by the thermal profile (see

Figure 12). If the diode temperature is less than Tcontrol, then the case temperature is permitted to

exceed the thermal profile, but the diode temperature must remain at or below Tcontrol. Systems

that implement fan speed control must be designed to take these conditions into account. Systems

that do not alter the fan speed only need to guarantee the case temperature meets the thermal profile

specifications.

Intel has developed a thermal profile for the Low Voltage Intel Xeon processor with 800 MHz

system bus, which can be implemented with the Low Voltage Intel Xeon processor with 800 MHz

system bus. It ensures adherence to Intel reliability requirements.

The Low Voltage Intel Xeon processor with 800 MHz system bus thermal specifications are

defined in Table 23. In addition, the thermal profile for the Low Voltage Intel Xeon processor with

800 MHz system bus is shown in Figure 12 and Table 24.

Datasheet

71

The upper point of the thermal profile consists of the Thermal Design Power (TDP) defined in

Table 23 and the associated T value. It should be noted that the upper point associated with the

CASE

Thermal Profile (x = TDP and y = T

@ TDP) represents a thermal solution design point.

CASE_MAX

In actuality the processor case temperature will never reach this value due to TCC activation (see

Figure 12).

Please note that, although Table 24 does not indicate a T

value, production units will be

CONTROL

programmed with a value. Please see Section 6.2.6 for more information on T

.

CONTROL

The case temperature is defined at the geometric top center of the processor IHS. Analysis

indicates that real applications are unlikely to cause the processor to consume maximum power

dissipation for sustained time periods. Intel recommends that complete thermal solution designs

target the Thermal Design Power (TDP) indicated in Table 23, instead of the maximum processor

power consumption. The Thermal Monitor feature is intended to help protect the processor in the

event that an application exceeds the TDP recommendation for a sustained time period. For more

details on this feature, refer to Section 6.2. Thermal Monitor feature must be enabled for the

processor to remain within specification.

Table 23.

Low Voltage Intel^®Xeon™ Processor with 800 MHz System Bus Thermal

Specifications

Core

Frequency

(GHz)

Maximum

Power

(W)

Thermal

Design Power

(W)

Minimum

T_CASE

(°C)

Maximum

T_CASE

(°C)

Notes

See Figure 12;

Table 24

2.80 GHz

62.1

55

5

1, 2, 3, 4, 5

NOTES:

1. These values are specified at V_{CC_MAX}for all processor frequencies. Systems must be designed to ensure

the processor is not to be subjected to any static V_CCand I_CCcombination wherein V_CCexceeds V_{CC_MAX}

at specified I_CC. Please refer to the V_CCstatic and transient tolerance specifications in Section 2.0.

2. Maximum Power is the maximum thermal power that can be dissipated by the processor through the

integrated heat spreader (IHS). Maximum Power is measured at maximum T_CASE

3. Thermal Design Power (TDP) should be used for processor/chipset thermal solution design targets. TDP is

not the maximum power that the processor can dissipate. TDP is measured at maximum T_CASE

.

4. These specifications are based on initial silicon characterization. These specifications may be further

updated as more characterization data becomes available.

5. Power specifications are defined at all VIDs found in Table 9. The Low Voltage Intel^®Xeon™ processor

with 800 MHz system bus may be shipped under multiple VIDs listed for each frequency.

72

Datasheet

Figure 12.

Low Voltage Intel^®Xeon™ Processor with 800 MHz System Bus Thermal Profile

100

90

T_{CASE MAX}

TDP

@

80

70

60

50

40

30

20

10

0

Thermal Profile

Y = 0.56 * x + 55

0

5

10

15

20

25

30

35

40

45

50

55

60

Power [W]

TDP

NOTES:

1. Please refer to Table 24 for discrete points that constitute the thermal profile.

2. Utilization of thermal solutions that do not meet the Thermal Profile do not meet the processor’s thermal

specifications and may result in permanent damage to the processor.

3. Refer to the Low Voltage Nocona Processor (800 MHz) in Embedded Applications Thermal Design

Guidelines for system and environmental implementation details.

Table 24.

Low Voltage Intel^®Xeon™ Processor with 800 MHz System Bus Thermal Profile

Power [W]

T_{CASE_MAX}[°C]

Power [W]

T_{CASE_MAX}[°C]

0

2

4

6

55

56

57

58

59

61

62

63

64

65

66

67

68

70

71

30

32

34

36

38

40

42

44

46

48

50

52

54

55

72

73

74

75

76

77

79

80

81

82

83

84

85

86

8

10

12

14

16

18

20

22

24

26

28

Datasheet

73

6.1.2

Thermal Metrology

The maximum case temperatures (T

) are specified in Table 23 and Table 24, and measured at

CASE

the geometric top center of the processor integrated heat spreader (IHS). Figure 13 illustrates the

location where T temperature measurements should be made. For detailed guidelines on

CASE

temperature measurement methodology, refer to the appropriate thermal/mechanical design guide.

Figure 13.

Case Temperature (T

) Measurement Location

CASE

21.25 mm

[0.837 in]

Measure from edge of processor

21.25 mm

[0.837 in]

Measure T

CASE

at this point.

42.5 mm FC-mPGA4 Package

NOTE: Figure is not to scale and is for reference only.

6.2

Processor Thermal Features

6.2.1

Thermal Monitor

The Thermal Monitor feature helps control the processor temperature by activating the Thermal

Control Circuit (TCC) when the processor silicon reaches its maximum operating temperature. The

TCC reduces processor power consumption as needed by modulating (starting and stopping) the

internal processor core clocks. The Thermal Monitor feature must be enabled for the processor to

be operating within specifications. The temperature at which Thermal Monitor activates the

thermal control circuit is not user configurable and is not software visible. Bus traffic is snooped in

the normal manner, and interrupt requests are latched (and serviced during the time that the clocks

are on) while the TCC is active.

When the Thermal Monitor is enabled, and a high temperature situation exists (i.e. TCC is active),

the clocks will be modulated by alternately turning the clocks off and on at a duty cycle specific to

the processor (typically 30 -50%). Clocks will not be off for more than 3 microseconds when the

TCC is active. Cycle times are processor speed dependent and will decrease as processor core

frequencies increase. A small amount of hysteresis has been included to prevent rapid

active/inactive transitions of the TCC when the processor temperature is near its maximum

operating temperature. Once the temperature has dropped below the maximum operating

temperature, and the hysteresis timer has expired, the TCC goes inactive and clock modulation

ceases.

The duty cycle for the TCC, when activated by the Thermal Monitor, is factory configured and

cannot be modified. The Thermal Monitor does not require any additional hardware, software

drivers, or interrupt handling routines.

74

Datasheet

6.2.2

On-Demand Mode

The processor provides an auxiliary mechanism that allows system software to force the processor

to reduce its power consumption. This mechanism is referred to as “On-Demand” mode and is

distinct from the Thermal Monitor feature. On-Demand mode is intended as a means to reduce

system level power consumption. Systems using the Low Voltage Intel^®Xeon™ processor with

800 MHz system bus must not rely on software usage of this mechanism to limit the processor

temperature.

If bit 4 of the IA-32_CLOCK_MODULATION MSR is written to a ‘1’, the processor will

immediately reduce its power consumption via modulation (starting and stopping) of the internal

core clock, independent of the processor temperature. When using On-Demand mode, the duty

cycle of the clock modulation is programmable via bits 3:1 of the IA-

32_CLOCK_MODULATION MSR. In On-Demand mode, the duty cycle can be programmed

from 12.5% on/ 87.5% off to 87.5% on/12.5% off in 12.5% increments. On-Demand mode may be

used in conjunction with the Thermal Monitor. If the system tries to enable On-Demand mode at

the same time the TCC is engaged, the factory configured duty cycle of the TCC will override the

duty cycle selected by the On-Demand mode.

6.2.3

PROCHOT# Signal Pin

An external signal, PROCHOT# (processor hot) is asserted when the processor die temperature has

reached its factory configured trip point. If Thermal Monitor is enabled (note that Thermal Monitor

must be enabled for the processor to be operating within specification), the TCC will be active

when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the

assertion or de-assertion of PROCHOT#. Refer to the Intel^®Architecture Software Developer’s

Manual(s) for specific register and programming details.

PROCHOT# is designed to assert at or a few degrees higher than maximum T

(as specified by

CASE

Thermal Profile) when dissipating TDP power, and cannot be interpreted as an indication of

processor case temperature. This temperature delta accounts for processor package, lifetime and

manufacturing variations and attempts to ensure the Thermal Control Circuit is not activated below

maximum T

when dissipating TDP power. There is no defined or fixed correlation between

CASE

the PROCHOT# trip temperature, the case temperature or the thermal diode temperature. Thermal

solutions must be designed to the processor specifications and cannot be adjusted based on

experimental measurements of T

, PROCHOT#, or T

on random processor samples.

CASE

diode

6.2.4

FORCEPR# Signal Pin

The FORCEPR# (force power reduction) input can be used by the platform to cause the Low

Voltage Intel^®Xeon™ processor with 800 MHz system bus to activate the TCC. If the Thermal

Monitor is enabled, the TCC will be activated upon the assertion of the FORCEPR# signal. The

TCC will remain active until the system deasserts FORCEPR#. FORCEPR# is an asynchronous

input. FORCEPR# can be used to thermally protect other system components. To use the VR as an

example, when the FORCEPR# pin is asserted, the TCC circuit in the processor will activate,

reducing the current consumption of the processor and the corresponding temperature of the VR.

If should be noted that assertion of the FORCEPR# does not automatically assert PROCHOT#. As

mentioned previously, the PROCHOT# signal is asserted when a high temperature situation is

detected. A minimum pulse width of 500 µs is recommend when the FORCEPR# is asserted by the

system. Sustained activation of the FORCEPR# pin may cause noticeable platform performance

degradation.

Datasheet

75

6.2.5

6.2.6

THERMTRIP# Signal Pin

Regardless of whether or not Thermal Monitor is enabled, in the event of a catastrophic cooling

failure, the processor will automatically shut down when the silicon has reached an elevated

temperature (refer to the THERMTRIP# definition in Table 20). At this point, the system bus

signal THERMTRIP# will go active and stay active as described in Table 20. THERMTRIP#

activation is independent of processor activity and does not generate any bus cycles.

T

and Fan Speed Reduction

CONTROL

T_CONTROLis a temperature specification based on a temperature reading from the thermal diode. The

value for T_CONTROLwill be calibrated in manufacturing and configured for each processor. The

T

_CONTROLtemperature for a given processor can be obtained by reading the IA-

32_TEMPERATURE_TARGET MSR in the processor. The T_CONTROLvalue that is read from the

IA-32_TEMPERATURE_TARGET MSR must be converted from Hexadecimal to Decimal and

added to a base value. The base value is 50 °C.

The value of T_CONTROLmay vary from 0x00h to 0x1Eh. Systems that support the Low Voltage

Intel^®Xeon™ processor with 800 MHz system bus must implement BIOS changes to detect which

processor is present, and then select the appropriate Tcontrol_base value.

When T_DIODEis above T_CONTROL, then T

must be at or below T

as defined by the

CASE_MAX

CASE

thermal profile. The processor temperature can be maintained at T_CONTROL

.

6.2.7

Thermal Diode

The processor incorporates an on-die thermal diode. A thermal sensor located on the system board

may monitor the die temperature of the processor for thermal management/long term die

temperature change purposes. Table 25 and Table 26 provide the diode parameter and interface

specifications. This thermal diode is separate from the Thermal Monitor’s thermal sensor and

cannot be used to predict the behavior of the Thermal Monitor.

Table 25.

Thermal Diode Parameters

Symbol

Min.

Typ.

Max.

Unit

Notes

I

Forward Bias Current

Diode ideality factor

Series Resistance

11

187

µA

1

FW

n

1.0083

3.242

1.011

3.33

1.0183

3.594

2,3,4

2,3,5

R

W

T

NOTES:

1. Intel does not support or recommend operation of the thermal diode under reverse bias.

2. Characterized at 75°C.

3. Not 100% tested. Specified by design characterization.

4. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode

equation: I

= I * (e^qVD/nkT- 1)

FW

S

Where I = saturation current, q = electronic charge, VD = voltage across the diode, k = Boltzmann Constant,

S

and T = absolute temperature (Kelvin).

5. The series resistance, R , is provided to allow for a more accurate measurement of the junction temperature.

T

R , as defined, includes the pins of the processor but does not include any socket resistance or board trace

T

resistance between the socket and external remote diode thermal sensor. R can be used by remote diode

T

thermal sensors with automatic series resistance cancellation to calibrate out this error term. Another

application that a temperature offset can be manually calculated and programmed into an offset register in

the remote diode thermal sensors as exemplified by the equation: T

= [R * (N-1) * I

] / [nk/q *ln N]

error

T

FW_min

Where T

charge.

= sensor temperature error, N =sensor current ratio, k = Boltzmann Constant, q= electronic

error

76

Datasheet

Table 26.

Thermal Diode Interface

Pin Name

Pin Number

Pin Description

THERMDA

THERMDC

Y27

Y28

diode anode

diode cathode

Datasheet

77

THIS PAGE INTENTIONALLY LEFT BLANK

78

Datasheet

7.0

Features

7.1

Power-On Configuration Options

Several configuration options can be configured by hardware. The Low Voltage Intel^®Xeon™

processor with 800 MHz system bus samples its hardware configuration at reset, on the active-to-

inactive transition of RESET#. For specifics on these options, please refer to Table 14.

The sampled information configures the processor for subsequent operation. These configuration

options cannot be changed except by another reset. All resets reconfigure the processor, for reset

purposes, the processor does not distinguish between a “warm” reset and a “power-on” reset.

Table 27.

Power-On Configuration Option Pins

Configuration Option

Notes

Output tristate

SMI#

INIT#

A7#

1,2

Execute BIST (Built-In Self Test)

In Order Queue de-pipelining (set IOQ depth to 1)

Disable MCERR# observation

Disable BINIT# observation

1,2

A9#

1,2

A10#

A15#

BR[3:0]#

A31#

1,2

Disable bus parking

1,2

Symmetric agent arbitration ID

Disable Hyper-Threading Technology

1,2,3

1,2

NOTES:

1. Asserting this signal during RESET# will select the corresponding option.

2. Address pins not identified in this table as configuration options should not be asserted during RESET#.

3. The Low Voltage Intel^®Xeon™ processor with 800 MHz system bus only uses the BR0# and BR1# signals.

Platforms must not use BR2# and BR3# signals.

7.2

Clock Control and Low Power States

The processor allows the use of HALT, Stop-Grant and Sleep states to reduce power consumption

by stopping the clock to internal sections of the processor, depending on each particular state. See

Figure 14 for a visual representation of the processor low power states.

The Stop Grant state requires chipset and BIOS support on multiprocessor systems. In a

multiprocessor system, all the STPCLK# signals are bussed together, thus all processors are

affected in unison. The Hyper-Threading Technology feature adds the conditions that all logical

processors share the same STPCLK# signal internally. When the STPCLK# signal is asserted, the

processor enters the Stop Grant state, issuing a Stop Grant Special Bus Cycle (SBC) for each

processor or logical processor. The chipset needs to account for a variable number of processors

asserting the Stop Grant SBC on the bus before allowing the processor to be transitioned into one

of the lower processor power states. Refer to the applicable chipset specification for more

information.

Datasheet

79

Due to the inability of processors to recognize bus transactions during the Sleep state,

multiprocessor systems are not allowed to simultaneously have one processor in Sleep state and the

other processors in Normal or Stop-Grant state.

7.2.1

7.2.2

Normal State

This is the normal operating state for the processor.

HALT Power-Down State

HALT is a low power state entered when all logical processors have executed the HALT or

MWAIT instruction. When one of the logical processors executes the HALT or MWAIT

instruction, that logical processor is halted; however, the other processor continues normal

operation. The processor will transition to the Normal state upon the occurrence of SMI#, BINIT#,

INIT#, LINT[1:0] (NMI, INTR), or an interrupt delivered over the front side bus. RESET# will

cause the processor to immediately initialize itself.

The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or

the HALT Power Down state. See the IA-32 Intel^®Architecture Software Developer's Manual,

Volume III: System Programming Guide for more information.

The system can generate a STPCLK# while the processor is in the HALT Power Down state. When

the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state.

While in HALT Power Down state, the processor will process front side bus snoops and interrupts.

80

Datasheet

Figure 14.

Stop Clock State Machine

HALT or MWAIT Instruction and

HALT Bus Cycle Generated

HALT State

BCLK running

Snoops and interrupts allowed

Normal State

Normal execution

INIT#, BINIT#, INTR, NMI, SMI#,

RESET#, FSB interrupts

Snoop

Event

Serviced

Snoop

Event

Occurs

STPCLK#

Asserted

STPCLK#

De-asserted

HALT Snoop State

BCLK running

Service snoops to caches

Snoop Event Occurs

Snoop Event Serviced

Stop Grant State

Stop Grant Snoop State

BCLK running

Snoops and interrupts allowed

Service snoops to caches

SLP#

De-asserted

Asserted

Sleep State

BCLK running

No snoops or interrupts

allowed

Datasheet

81

7.2.3

Stop-Grant State

When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20 bus clocks

after the response phase of the processor-issued ° Acknowledge special bus cycle. Once the

STPCLK# pin has been asserted, it may only be deasserted once the processor is in the ° state. For

the Low Voltage Intel^®Xeon™ processor with 800 MHz system bus, both logical processors must

be in the ° state before the deassertion of STPCLK#.

Since the AGTL+ signal pins receive power from the front side bus, these pins should not be driven

(allowing the level to return to VTT) for minimum power drawn by the termination resistors in this

state. In addition, all other input pins on the front side bus should be driven to the inactive state.

BINIT# will not be serviced while the processor is in Stop-Grant state. The event will be latched

and can be serviced by software upon exit from the ° state.

RESET# will cause the processor to immediately initialize itself, but the processor will stay in

Stop-Grant state. A transition back to the Normal state will occur with the de-assertion of the

STPCLK# signal. When re-entering the Stop-Grant state from the Sleep state, STPCLK# should

only be deasserted one or more bus clocks after the deassertion of SLP#.

A transition to the Grant Snoop state will occur when the processor detects a snoop on the front

side bus (see Section 7.2.4). A transition to the Sleep state (see Section 7.2.5) will occur with the

assertion of the SLP# signal.

While in the Stop-Grant state, SMI#, INIT#, BINIT# and LINT[1:0] will be latched by the

processor, and only serviced when the processor returns to the Normal state. Only one occurrence

of each event will be recognized upon return to the Normal state.

While in Stop-Grant state, the processor will process snoops on the front side bus and it will latch

interrupts delivered on the front side bus.

The PBE# signal can be driven when the processor is in Stop-Grant state. PBE# will be asserted if

there is any pending interrupt latched within the processor. Pending interrupts that are blocked by

the EFLAGS.IF bit being clear will still cause assertion of PBE#. Assertion of PBE# indicates to

system logic that it should return the processor to the Normal state.

7.2.4

HALT Snoop State or Snoop State

The processor will respond to snoop or interrupt transactions on the front side bus while in Stop-

Grant state or in HALT Power Down state. During a snoop or interrupt transaction, the processor

enters the HALT/Grant Snoop state. The processor will stay in this state until the snoop on the front

side bus has been serviced (whether by the processor or another agent on the front side bus) or the

interrupt has been latched. After the snoop is serviced or the interrupt is latched, the processor will

return to the Stop-Grant state or HALT Power Down state, as appropriate.

82

Datasheet

7.2.5

Sleep State

The Sleep state is a very low power state in which each processor maintains its context, maintains

the phase-locked loop (PLL), and has stopped most of internal clocks. The Sleep state can only be

entered from Stop-Grant state. Once in the Stop-Grant state, the processor will enter the Sleep state

upon the assertion of the SLP# signal. The SLP# pin has a minimum assertion of one BCLK

period. The SLP# pin should only be asserted when the processor is in the ° state. For Low Voltage

Intel^®Xeon™ processor with 800 MHz system bus, the SLP# pin may only be asserted when all

logical processors are in the Stop-Grant state. SLP# assertions while the processors are not in the

Stop-Grant state are out of specification and may results in illegal operation.

Snoop events that occur while in Sleep state or during a transition into or out of Sleep state will

cause unpredictable behavior.

In the Sleep state, the processor is incapable of responding to snoop transactions or latching

interrupt signals. No transitions or assertions of signals (with the exception of SLP# or RESET#)

are allowed on the front side bus while the processor is in Sleep state. Any transition on an input

signal before the processor has returned to Stop-Grant state will result in unpredictable behavior.

If RESET# is driven active while the processor is in the Sleep state, and held active as specified in

the RESET# pin specification, then the processor will reset itself, ignoring the transition through

Stop-Grant state. If RESET# is driven active while the processor is in the Sleep state, the SLP# and

STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the

processor correctly executes the reset sequence.

When the processor is in Sleep state, it will not respond to interrupts or snoop transactions.

Datasheet

83

THIS PAGE INTENTIONALLY LEFT BLANK

84

Datasheet

8.0

Debug Tools Specifications

Please refer to the ITP700 Debug Port Design Guide for information regarding debug tool

specifications. Section 1.2 provides collateral details.

8.1

Debug Port System Requirements

The Low Voltage Intel^®Xeon™ processor with 800 MHz system bus debug port is the command

and control interface for the In-Target Probe (ITP) debugger. The ITP enables run-time control of

the processors for system debug. The debug port, which is connected to the front side bus, is a

combination of the system, JTAG and execution signals. There are several mechanical, electrical

and functional constraints on the debug port that must be followed. The mechanical constraint

requires the debug port connector to be installed in the system with adequate physical clearance.

Electrical constraints exist due to the mixed high and low speed signals of the debug port for the

processor. While the JTAG signals operate at a maximum of 75 MHz, the execution signals operate

at the common clock front side bus frequency (200 MHz). The functional constraint requires the

debug port to use the JTAG system via a handshake and multiplexing scheme.

In general, the information in this chapter may be used as a basis for including all run-control tools

in Low Voltage Intel^®Xeon™ processor with 800 MHz system bus-based system designs,

including tools from vendors other than Intel.

Note: The debug port and JTAG signal chain must be designed into the processor board in order to use

the ITP for debug purposes.

8.2

Target System Implementation

8.2.1

System Implementation

Specific connectivity and layout guidelines for the Debug Port are provided in the ITP700 Debug

Port Design Guide.

8.3

Logic Analyzer Interface (LAI)

Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use

in debugging Low Voltage Intel^®Xeon™ processor with 800 MHz system bus systems. Tektronix*

and Agilent* should be contacted to obtain specific information about their logic analyzer

interfaces. The following information is general in nature. Specific information must be obtained

from the logic analyzer vendor.

Due to the complexity of Low Voltage Intel^®Xeon™ processor with 800 MHz system bus-based

multiprocessor systems, the LAI is critical in providing the ability to probe and capture front side

bus signals. There are two sets of considerations to keep in mind when designing a Low Voltage

Intel^®Xeon™ processor with 800 MHz system bus-based system that can make use of an LAI:

mechanical and electrical.

Datasheet

85

8.3.1

Mechanical Considerations

The LAI is installed between the processor socket and the processor. The LAI pins plug into the

socket, while the processor pins plug into a socket on the LAI. Cabling that is part of the LAI

egresses the system to allow an electrical connection between the processor and a logic analyzer.

The maximum volume occupied by the LAI, known as the keepout volume, as well as the cable

egress restrictions, should be obtained from the logic analyzer vendor. System designers must

make sure that the keepout volume remains unobstructed inside the system. Note that it is possible

that the keepout volume reserved for the LAI may include different requirements from the space

normally occupied by the heat sink. If this is the case, the logic analyzer vendor will provide a

cooling solution as part of the LAI.

8.3.2

Electrical Considerations

The LAI will also affect the electrical performance of the front side bus, therefore it is critical to

obtain electrical load models from each of the logic analyzer vendors to be able to run system level

simulations to prove that their tool will work in the system. Contact the logic analyzer vendor for

electrical specifications and load models for the LAI solution they provide.

86

Datasheet


型号：	RK80546KG0721M/SL7PD
厂家：	INTEL
描述：	RISC Microprocessor, 32-Bit, 2800MHz, CMOS, PPGA604 外围集成电路
文件：	总86页 (文件大小：1314K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

RK80546KG0721M/SL7PD [INTEL]

相关型号：

RK80546KG0722MM

RK80546KG0801MSL7PE

RK80546KG0802MM

RK80546KG0802MM/SL944

RK80546KG0881M/SL7TD

RK80546KG0882MM/SL8ZP

RK80546KG0961M/SL7DY

RK80546KG0962MM

RK80546KG1041M/SL7VF

RK80546KG1041M/SL8K2

RK80546KG1042MM

RK80546KG1042MM/SL7ZC