N87C196MD [INTEL]
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER; 8XC196MH工业电机控制CHMOS单片机
| 型号： | N87C196MD |
| 厂家： | 
INTEL |
| 描述： | 8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER |
| 文件： | 总41页 (文件大小：1550K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
8XC196MH INDUSTRIAL MOTOR CONTROL
CHMOS MICROCONTROLLER
■ High Performance CHMOS 16-bit CPU
■ 16 MHz Operating Frequency
■ Event Processor Array (EPA) with 2 High-
speed Capture/Compare Modules and 4 High-
speed Compare-only Modules
■ 32 Kbytes of On-chip OTPROM/ROM
■ 744 Bytes of On-chip Register RAM
■ Register-to-register Architecture
■ 16 Prioritized Interrupt Sources
■ Two Programmable 16-bit Timers with
Quadrature Counting Inputs
■ Two Pulse-width Modulator (PWM) Outputs
with High Drive Capability
■ Flexible 8- or 16-bit External Bus
■ Peripheral Transaction Server (PTS) with 15
×
Prioritized Sources
■ 1.75 µs 16 16 Multiply
■ Up to 52 I/O Lines
■ 3 µs 32/16 Divide
■ 3-phase Complementary Waveform Generator
■ Extended Temperature Available
■ Idle and Powerdown Modes
■ Watchdog Timer
■ 8-channel 8- or 10-bit A/D with Sample and
Hold
■ 2-channel UART
®
The 8XC196MH is a member of Intel’s family of 16-bit MCS 96 microcontrollers. It is designed primarily to
control three-phase AC induction and DC brushless motors. It features an enhanced three-phase waveform
generator specifically designed for use in “inverter” motor-control applications. This peripheral provides pulse-
width modulation and three-phase sine wave generation with minimal CPU intervention. It generates three
complementary non-overlapping PWM pulses with resolutions of 0.125 µs (edge triggered) or 0.250 µs
(centered).
The 8XC196MH has two dedicated serial port peripherals, allowing less software overhead. The watchdog timer
can be programmed with one of four time options.
The 8XC196MH is available as the 80C196MH, which does not have on-chip ROM, the 87C196MH,
which contains 32 Kbytes of on-chip OTPROM* or factory programmed ROM, and the 83C196MH, which
contains 32 Kbytes of factory programmed MASK ROM. It is available in 84-lead PLCC, 80-lead Shrink EIAJ/QFP,
and 64-lead SDIP. The 64-lead package does not contain pins for the P5.1/INST and P6.7/PWM1 signals.
Operational characteristics are guaranteed over the temperature range of – 40°C to + 85°C.
*One-Time Programmable Read-Only Memory (OTPROM) is similar to EPROM but comes in an unwindowed package and
cannot be erased. It is user programmable.
Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent
licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel.
© INTEL CORPORATION, 2004
August 2004
Order Number: 272543-003
®
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
32K
On-chip
ROM/
16
CPU
OTPROM
Interrupt
744
Byte
Register
File
RALU
Controller
Port 5
Control
Signals
8
8
Memory
Controller
Port 3
AD7:0
8/10-Bit
A/D
Converter
Peripheral
Transaction
Server
24 Bytes
CPU SFRs
Microcode
Engine
Queue
Port 4
AD15:8
8
Watchdog
Timer
S/H
Event
Processor
Array
Baud
Rate
Generator
3-Phase
Waveform
Generator
SIO 0
SIO 1
Timer 1
Timer 2
PWM0
PWM1
Mux
Port 0
6
4
2
2
6
Port 1
Port 2
Port 6
8
8
8
4
A/D
Port 1
Port 2
EXTINT
Port 6
Port 0
Serial I/O
SIO, EPA
2 Capture/Compare
4 Compare
Waveform
Generator
A2542-01
Figure 1. 8XC196MH Block Diagram
2
®
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
the application. The Intel Packaging Handbook (order
number 240800) describes Intel’s thermal impedance
PROCESS INFORMATION
This device is manufactured on PX29.5, a CHMOS IV
process. Additional process and reliability information
is available in Intel’s Components Quality and
Reliability Handbook (order number 210997).
test methodology.
Table 1. Thermal Characteristics
Package Type
84-lead PLCC
80-lead QFP
θ
θ
JC
JA
All thermal impedance data is approximate for static
air conditions at 1 watt of power dissipation. Values
will change depending on operating conditions and
33°C/W
56°C/W
56°C/W
11°C/W
12°C/W
N/A
64-lead SDIP
X XX 8 X C 196 XX XX
Device Speed:
No Mark = 16 MHz
Kx, Mx, Nx
Product Family:
CHMOS Technology
Program Memory Options:
0 = ROMless, 3 = ROM, 7 = OTPROM
x = SDIP, x = PLCC, x = QFP
Package - Type Options:
Temperature and Burn In Options:
x = –40˚C – +85˚C Ambient
with Intel Standard Burn-In
A2759-01
Figure 2. The 8XC196MH Family Nomenclature
To address the fact that many of the package prefix variables have changed,
all package prefix variables in this document are now indicated with an "x".
NOTE:
3
®
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
Table 2. 8XC196MH Memory Map
Address
Description
(1)
Notes
0FFFFH
External Memory
0A000H
09FFFH
Internal ROM/OTPROM or External Memory
02080H
0207FH
Reserved
0205EH
1, 2
0205DH
PTS Vectors
02040H
0203FH
Interrupt Vectors (upper)
02030H
0202FH
ROM/OTPROM Security Key
02020H
0201FH
Reserved
0201CH
1, 2
0201BH
0201AH
02019H
02018H
Reserved (must contain 20H)
CCB1
Reserved (must contain 20H)
CCB0
02017H
02014H
Reserved
02013H
02000H
Interrupt Vectors (lower)
Internal SFRs
External Memory
Register RAM
CPU SFRs
01FFFH
01F00H
1
1EFFH
300H
2FFH
18H
3
1
17H
00H
NOTES:
1. Unless otherwise noted, write 0FFH to reserved memory locations and write 0 to reserved SFR bits.
2. WARNING: The contents and/or function of reserved locations may change with future revisions of the
device.
3. Code executed in locations 0000H to 02FFH will be forced external.
4
®
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
Table 3. Signals Arranged by Functional Categories
Address & Data
Programming Control
AINC#
Input/Output
P0.0/ACH0
Input/Output (Cont’d)
P2.5/COMP1
P2.6/COMP2
P2.7/SCLK1#/BCLK1
P3.7:0
AD15:0
CPVER
P0.1/ACH1
Bus Control & Status
ALE/ADV#
BHE#/WRH#
BUSWIDTH
INST
PACT#
P0.2/ACH2
PALE#
P0.3/ACH3
PBUS15:0
PMODE.3:0
PROG#
P0.4/ACH4
P4.7:0
P0.5/ACH5
P5.7:0
P0.6/ACH6/T1CLK
P0.7/ACH7/T1DIR
P1.0/TXD0
P6.0/WG1#
P6.1/WG1
READY
PVER
RD#
P6.2/WG2#
P6.3/WG2
WR#/WRL#
Processor Control
EA#
P1.1/RXD0
P1.2/TXD1
P6.4/WG3#
P6.5/WG3
Power & Ground
EXTINT
NMI
P1.3/RXD1
ANGND
VCC
P2.0/EPA0
P6.6/PWM0
P6.7/PWM1
ONCE#
P2.1/SCLK0#/BCLK0
P2.2/EPA1
VPP
RESET#
XTAL1
VREF
VSS
P2.3/COMP3
P2.4/COMP0
XTAL2
NOTE: The following signals are not available in the 64-pin package: P5.1, P6.7, INST, and PWM1.
5
®
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
VSS
P5.0/ALE/ADV#
VPP
1
2
3
4
5
6
7
8
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P5.6/READY
P5.4/ONCE#
EXTINT
P5.3/RD#
VSS
XTAL1
P5.5/BHE#/WRH#
P5.2/WR#/WRL#
P5.7/BUSWIDTH
P4.6/AD14/PBUS.14
P4.5/AD13/PBUS.13
P4.7/AD15/PBUS.15
VCC
P4.4/AD12/PBUS.12
P4.3/AD11/PBUS.11
P4.2/AD10/PBUS.10
P4.1/AD9/PBUS.9
P4.0/AD8/PBUS.8
P3.7/AD7/PBUS.7
P3.6/AD6/PBUS.6
P3.5/AD5/PBUS.5
P3.4/AD4/PBUS.4
P3.3/AD3/PBUS.3
P3.2/AD2/PBUS.2
P3.1/AD1/PBUS.1
P3.0/AD0/PBUS.0
RESET#
XTAL2
P6.6/PWM0
P2.7/SCLK1#/BCLK1
P2.6/COMP2/CPVER
P2.5/COMP1/PACT#
P2.4/COMP0/AINC#
P2.3/COMP3
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P2.2/EPA1/PROG#
P2.1/SCLK0#/BCLK0/PALE#
P2.0/EPA0/PVER
P0.0/ACH0
xx8XC196MH
P0.1/ACH1
P0.2/ACH2
TOP VIEW
(Looking down
on component side of
PC board)
P0.3/ACH3
P0.4/ACH4/PMODE.0
P0.5/ACH5/PMODE.1
VREF
ANGND
P0.6/ACH6/T1CLK/PMODE.2
P0.7/ACH7/T1DIR/PMODE.3
P1.0/TXD0
NMI
EA#
P1.1/RXD0
VSS
VCC
P6.5/WG3
P1.2/TXD1
P1.3/RXD1
P6.0/WG1#
P6.4/WG3#
P6.1/WG1
P6.3/WG2
P6.2/WG2#
A2572-01
Figure 3. 8XC196MH 64-lead Shrink DIP (SDIP) Package
6
®
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
Table 4. 64-lead Shrink DIP (SDIP) Pin Assignment
Pin
Name
Pin
Name
Pin
Name
Pin
Name
1
VSS
17 P3.7/AD7
/PBUS.7
33 P6.2/WG2#
34 P6.1/WG1
35 P6.0/WG1#
36 P1.3/RXD1
37 P1.2/TXD1
38 P1.1/RXD0
39 P1.0/TXD0
49 P0.0/ACH0
2
3
4
5
6
7
8
9
P5.0/ALE/ADV#
VPP
18 P3.6/AD6
/PBUS.6
50 P2.0/EPA0/PVER
19 P3.5/AD5
/PBUS.5
51 P2.1/SCLK0#
/BCLK0/PALE#
P5.3/RD#
20 P3.4/AD4
/PBUS.4
52 P2.2/EPA1
/PROG#
P5.5/BHE#/WRH#
P5.2/WR#/WRL#
P5.7/BUSWIDTH
21 P3.3/AD3
/PBUS.3
53 P2.3/COMP3
22 P3.2/AD2
/PBUS.2
54 P2.4/COMP0
/AINC#
23 P3.1/AD1
/PBUS.1
55 P2.5/COMP1
/PACT#
P4.6/AD14
/PBUS.14
24 P3.0/AD0
/PBUS.0
40 P0.7/ACH7/T1DIR
/PMODE.3
56 P2.6/COMP2
/CPVER
P4.5/AD13
/PBUS.13
25 RESET#
41 P0.6/ACH6
57 P2.7/SCLK1#
/BCLK1
/T1CLK/PMODE.2
10 P4.7/AD15
/PBUS.15
26 NMI
42 ANGND
58 P6.6/PWM0
11 VCC
27 EA#
28 VSS
43 VREF
59 XTAL2
60 XTAL1
12 P4.4/AD12
/PBUS.12
44 P0.5/ACH5
/PMODE.1
13 P4.3/AD11
/PBUS.11
29 VCC
45 P0.4/ACH4
/PMODE.0
61 VSS
14 P4.2/AD10
/PBUS.10
30 P6.5/WG3
46 P0.3/ACH3
62 EXTINT
15 P4.1/AD9/PBUS.9
16 P4.0/AD8/PBUS.8
31 P6.4/WG3#
32 P6.3/WG2
47 P0.2/ACH2
48 P0.1/ACH1
63 P5.4/ONCE#
64 P5.6/READY
7
®
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
P4.7/AD15/PBUS.15
P4.6/AD14/PBUS.14
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
P2.5/COMP1/PACT#
P2.4/COMP0/AINC#
NC
V
CC
P4.5/AD13/PBUS.13
NC
NC
P2.7/SCLK1#/BCLK1
P2.3/COMP3
P2.2/EPA1/PROG#
NC
P4.4/AD12/PBUS.12
P4.3/AD11/PBUS.11
P4.2/AD10/PBUS.10
P4.1/AD9/PBUS.9
P4.0/AD8/PBUS.8
NC
xx8XC196MH
NC
P2.1/SCLK0#/BCLK0/PALE#
P2.0/EPA0/PVER
NC
P0.0/ACH0
P0.1/ACH1
P0.2/ACH2
P0.3/ACH3
P0.4/ACH4/PMODE.0
P0.5/ACH5/PMODE.1
TOP VIEW
(Looking down
on component side of
PC board)
NC
P3.7/AD7/PBUS.7
P3.6/AD6/PBUS.6
P3.5.AD5/PBUS.5
P3.4/AD4/PBUS.4
P3.3/AD3/PBUS.3
P3.2/AD2/PBUS.2
P3.1/AD1/PBUS.1
P3.0/AD0/PBUS.0
NC
V
REF
ANGND
P0.6/ACH6/T1CLK/PMODE.2
A2573-02
Figure 4. 8XC196MH 84-lead PLCC Package
8
®
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
Table 5. 84-lead PLCC Pin Assignment
Pin
1
Name
Pin
Name
Pin
Name
Pin
Name
P5.4/ONCE#
P5.6/READY
22 NC
23 NC
43 VSS
64 P2.0/EPA0/PVER
2
44 P6.2/WG2#
45 P6.1/WG1
46 P6.0/WG1#
47 P1.3/RXD1
48 P1.2/TXD1
49 NC
65 P2.1/SCLK0#
/BCLK0/PALE#
3
4
5
6
7
8
9
P5.1/INST
VSS
24 P3.7/AD7
/PBUS.7
66 NC
25 P3.6/AD6
/PBUS.6
67 NC
P5.0/ALE/ADV#
VPP
26 P3.5/AD5
/PBUS.5
68 P2.2/EPA1
/PROG#
27 P3.4/AD4
/PBUS.4
69 P2.3/COMP3
P5.3/RD#
P5.5/BHE#/WRH#
NC
28 P3.3/AD3
/PBUS.3
70 P2.7/SCLK1#
/BCLK1
29 P3.2/AD2
/PBUS.2
50 NC
71 NC
30 P3.1/AD1
/PBUS.1
51 P1.1/RXD0
52 P1.0/TXD0
53 P0.7/ACH7
72 NC
10 P5.2/WR#/WRL#
11 P5.7/BUSWIDTH
31 P3.0/AD0
/PBUS.0
73 P2.4/COMP0
/AINC#
32 NC
74 P2.5/COMP1
/PACT#
/T1DIR/PMODE.3
54 P0.6/ACH6
/T1CLK/PMODE.2
12 P4.7/AD15
/PBUS.15
33 RESET#
34 NMI
75 P2.6/COMP2
/CPVER
13 P4.6/AD14
/PBUS.14
55 ANGND
76 P6.7/PWM1
14 VCC
35 NC
56 VREF
77 P6.6/PWM0
78 NC
15 P4.5/AD13
/PBUS.13
36 EA#
57 P0.5/ACH5
/PMODE.1
16 NC
37 VSS
58 P0.4/ACH4
/PMODE.0
79 NC
17 P4.4/AD12
/PBUS.12
38 NC
59 P0.3/ACH3
60 P0.2/ACH2
61 P0.1/ACH1
80 NC
18 P4.3/AD11
/PBUS.11
39 VCC
81 XTAL2
82 XTAL1
19 P4.2/AD10
/PBUS.10
40 P6.5/WG3
20 P4.1/AD9/PBUS.9
21 P4.0/AD8/PBUS.8
41 P6.4/WG3#
42 P6.3/WG2
62 P0.0/ACH0
63 NC
83 VSS
84 EXTINT
9
®
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
80
75
68
65
67 66
79 78 77 76
74 73 72 71 70 69
P6.7/PWM1
64
1
P5.2/WR#/WRL#
P5.7/BUSWIDTH
P2.6/COMP2/CPVER
P2.5/COMP1/PACT#
P2.4/COMP0/AINC#
NC
63
62
61
2
3
P4.7/AD15/PBUS.15
P4.6/AD14/PBUS.14
4
60
59
58
57
56
55
54
53
V
5
CC
NC
6
P4.5/AD13/PBUS.13
NC
P2.7/SCLK1#/BCLK1
P2.3/COMP3
P2.2/EPA1/PROG#
NC
7
8
P4.4/AD12/PBUS.12
P4.3/AD11/PBUS.11
9
10
11
12
13
14
15
16
17
18
19
20
P4.2/AD10/PBUS.10
P4.1/AD9/PBUS.9
xx8XC196MH
NC
P2.1/SCLK0#/BCLK0/PALE#
P2.0/EPA0/PVER
NC
P4.0/AD8/PBUS.8
TOP VIEW
(Looking down
on component side of
PC board)
52
51
P3.7/AD7/PBUS.7
P3.6/AD6/PBUS.6
P3.5/AD5/PBUS.5
P0.0/ACH0
50
49
48
47
P0.1/ACH1
P3.4/AD4/PBUS.4
P3.3/AD3/PBUS.3
P0.2/ACH2
P0.3/ACH3
P3.2/AD2/PBUS.2
P3.1/AD1/PBUS.1
P3.0/AD0/PBUS.0
NC
46
45
44
43
P0.4/ACH4/PMODE.0
P0.5/ACH5/PMODE.1
V
21
22
23
REF
ANGND
RESET#
P0.6/ACH6/T1CLK/PMODE.2
P0.7/ACH7/T1DIR/PMODE.3
42
41
NMI
EA#
24
36
38 39
25 26 27 28 29 30 31 32 33 34 35
37
40
A2574-01
Figure 5. 8XC196MH 80-lead Shrink EIAJ/QFP Package
10
®
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
Table 6. 80-lead Shrink EIAJ/QFP Pin Assignment
Pin
Name
Pin
Name
Pin
Name
Pin
Name
1
P5.2/WR#/WRL#
21 NC
41 P0.7/ACH7/T1DIR
/PMODE.3
61 P2.4/COMP0
/AINC#
2
3
4
5
6
P5.7/BUSWIDTH
22 RESET#
23 NMI
24 EA#
25 VSS
42 P0.6/ACH6
62 P2.5/COMP1
/PACT#
/T1CLK/PMODE.2
P4.7/AD15
/PBUS.15
43 ANGND
63 P2.6/COMP2
/CPVER
P4.6/AD14
/PBUS.14
44 VREF
64 P6.7/PWM1
65 P6.6/PWM0
66 NC
VCC
45 P0.5/ACH5
/PMODE.1
P4.5/AD13
/PBUS.13
26 NC
46 P0.4/ACH4
/PMODE.0
7
8
NC
27 VCC
47 P0.3/ACH3
48 P0.2/ACH2
67 NC
68 NC
P4.4/AD12
/PBUS.12
28 P6.5/WG3
9
P4.3/AD11
/PBUS.11
29 P6.4/WG3#
30 P6.3/WG2
49 P0.1/ACH1
50 P0.0/ACH0
69 XTAL2
70 XTAL1
10 P4.2/AD10
/PBUS.10
11 P4.1/AD9/PBUS.9
12 P4.0/AD8/PBUS.8
13 P3.7/AD7/PBUS.7
31 VSS
51 NC
71 VSS
32 P6.2/WG2#
33 P6.1/WG1
52 P2.0/EPA0/PVER
72 EXTINT
73 P5.4/ONCE#
53 P2.1/SCLK0#
/BCLK0/PALE#
14 P3.6/AD6/PBUS.6
15 P3.5/AD5/PBUS.5
16 P3.4/AD4/PBUS.4
34 P6.0/WG1#
35 P1.3/RXD1
36 P1.2/TXD1
54 NC
55 NC
74 P5.6/READY
75 P5.1/INST
76 VSS
56 P2.2/EPA1
/PROG#
17 P3.3/AD3/PBUS.3
18 P3.2/AD2/PBUS.2
37 NC
38 NC
57 P2.3/COMP3
77 P5.0/ALE/ADV#
78 VPP
58 P2.7/SCLK1#
/BCLK1
19 P3.1/AD1/PBUS.1
20 P3.0/AD0/PBUS.0
39 P1.1/RXD0
40 P1.0/TXD0
59 NC
60 NC
79 P5.3/RD#
80 P5.5/BHE#/WRH#
11
®
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
PIN DESCRIPTIONS
Table 7. Signal Descriptions
Signal
Multiplexed
With
Type
Description
Name
ACH7
I
Analog Channels. These pins are analog inputs to the A/D
converter.
P0.7/T1DIR/PMODE.3
P0.6/T1CLK/PMODE.2
P0.5/PMODE.1
P0.4/PMODE.0
P0.3:0
ACH6
ACH5
ACH4
ACH3:0
These pins are multiplexed with the port 0 pins. While it is
possible for the pins to function simultaneously as analog and
digital inputs, this is not recommended because reading the
port while a conversion is in process can produce unreliable
conversion results.
The ANGND and VREF pins must be connected for the A/D
converter and the multiplexed port pins to function.
AD15:8
AD7:0
I/O
O
Address/Data Lines. These pins provide a multiplexed
address and data bus. During the address phase of the bus
cycle, address bits 0–15 are presented on the bus and can
be latched using ALE or ADV#. During the data phase, 8- or
16-bit data is transferred.
P4.7:0/PBUS.15:8
P3.7:0/PBUS.7:0
ADV#
Address Valid. This active-low output signal is asserted only P5.0/ALE
during external memory accesses.
ADV# indicates that valid address information is available on
the system address/data bus. The signal remains low while a
valid bus cycle is in progress and is returned high as soon as
the bus cycle completes.
An external latch can use the ADV# signal to demultiplex the
address from the address/data bus. Used with a decoder,
ADV# can generate chip-selects for external memory.
AINC#
ALE
I
Auto Increment. In slave programming mode, this active-low P2.4/COMP0
input signal enables the autoincrement mode. Auto increment
allows reading from or writing to sequential OTPROM
locations without requiring address transactions across the
programming bus for each read or write.
O
Address Latch Enable. This active-high output signal is
asserted only during external memory cycles.
P5.0/ADV#
ALE signals the start of an external bus cycle and indicates
that valid address information is available on the system
address/data bus. ALE differs from ADV# in that it is not
returned high until a new bus cycle is to begin.
An external latch can use ALE to demultiplex the address
from the address/data bus.
ANGND
GND Analog Ground. Reference ground for the A/D converter
—
and the logic used to read port 0. ANGND must be held at
nominally the same potential as VSS
.
BCLK1
BCLK0
I
Serial Communications Baud Clock 0 and 1. BCLK0 and 1 P2.7/SCLK1#
are alternate clock sources for the serial ports. The maximum P2.1/SCLK0#/PALE#
input frequency is FOSC/4.
12
®
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
Table 7. Signal Descriptions (Continued)
Signal
Name
Multiplexed
Type
Description
With
BHE#
O
Byte High Enable. During 16-bit bus cycles, this active-low
output signal is asserted for word reads and writes and for
high-byte reads and writes to external memory. BHE#
indicates that valid data is being transferred over the upper
half of the system address/data bus.
P5.5/WRH#
BHE#, in conjunction with A0, selects the memory byte to be
accessed:
BHE#
A0
Byte(s) Accessed
0
0
1
0
1
0
both bytes
high byte only
low byte only
BUSWIDTH
I
Bus Width. When enabled in the chip configuration register, P5.7
this active-high input signal dynamically selects the bus width
of the bus cycle in progress. When BUSWIDTH is high, a 16-
bit bus cycle occurs; when BUSWIDTH is low, an 8-bit bus
cycle occurs. BUSWIDTH is active during a CCR fetch.
COMP3
COMP2
COMP1
COMP0
O
O
Event Processor Array (EPA) Compare Pins. These
signals are the output of the EPA compare modules. These
pins are multiplexed with other signals and may be
configured as standard I/O.
P2.3
P2.6/CPVER
P2.5/PACT#
P2.4/AINC#
CPVER
Cumulative Program Verification. This active-high output
signal indicates whether any verify errors have occurred
since the device entered programming mode. CPVER
remains high until a verify error occurs, at which time it is
driven low. Once an error occurs, CPVER remains low until
the device exits programming mode. When high, CPVER
indicates that all locations have programmed correctly since
the device entered programming mode.
P2.6/COMP2
EA#
I
External Access. This active-low input signal directs
memory accesses to on-chip or off-chip memory. If EA# is
low, the memory access is off-chip. If EA# is high and the
memory address is within 2000H–2FFFH, the access is to
on-chip ROM or OTPROM. Otherwise, an access with EA#
high is to off-chip memory.
—
EA# is sampled only on the rising edge of RESET#.
If EA# = VEA on the rising edge of RESET#, the device enters
the programming mode selected by PMODE.3:0.
For devices without ROM, EA# must be tied low.
EPA1
EPA0
I/O
Event Processor Array (EPA) Input/Output pins. These
are the high-speed input/output pins for the EPA
P2.2/PROG#
P2.0/PVER
capture/compare modules. These pins are multiplexed with
other signals and may be configured as standard I/O.
13
®
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
Table 7. Signal Descriptions (Continued)
Signal
Name
Multiplexed
With
Type
Description
EXTINT
I
External Interrupt. This programmable interrupt is controlled
by the WG_PROTECT register. This register controls
whether the interrupt is edge triggered or sampled and
whether a rising edge/high level or falling edge/low level
activates the interrupt. This interrupt vectors through memory
location 203CH. If the chip is in idle mode and if EXTINT is
enabled, a valid EXTINT interrupt brings the chip back to
normal operation, where the first action is to execute the
EXTINT service routine. After completion of the service
routine, execution resumes at the instruction following the
one that put the chip into idle mode.
—
In powerdown mode, a valid EXTINT interrupt causes the
chip to return to normal operating mode. If EXTINT is
enabled, the EXTINT service routine is executed. Otherwise,
execution continues at the instruction following the IDLPD
instruction that put the chip into powerdown mode.
INST
O
Instruction Fetch. This active-high output signal is valid only P5.1
during external memory bus cycles. When high, INST
indicates that an instruction is being fetched from external
memory. The signal remains high during the entire bus cycle
of an external instruction fetch. INST is low for data
accesses, including interrupt vector fetches and chip configu-
ration byte reads. INST is low during internal memory
fetches.
NMI
I
Nonmaskable Interrupt. In normal operating mode, a rising
edge on NMI causes a vector through the NMI interrupt at
location 203EH. NMI must be asserted for greater than one
state time to guarantee that it is recognized.
—
In idle mode, a rising edge on NMI brings the chip back to
normal operation, where the first action is to execute the NMI
service routine. After completion of the service routine,
execution resumes at the instruction following the one that
put the chip into idle mode.
In powerdown mode, NMI causes a return to normal
operating mode only if it is tied to EXTINT.
ONCE#
I
On-circuit Emulation. Holding this pin low while the
RESET# signal transitions from a low to a high places the
device into on-circuit emulation (ONCE) mode. ONCE mode
isolates the device from other components in the system to
allow the use of a clip-on emulator for system debugging.
This mode puts all pins except XTAL1 and XTAL2 into a high-
impedance state. To exit ONCE mode, reset the device by
pulling the RESET# signal low.
P5.4
14
®
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
Table 7. Signal Descriptions (Continued)
Signal
Name
Multiplexed
Type
Description
With
P0.7
I
Port 0. This is a high-impedance, input-only port. Port 0 pins ACH7/T1DIR/PMODE.3
P0.6
P0.5
P0.4
P0.3:0
should not be left floating.
ACH6/T1CLK/PMODE.2
ACH5/PMODE.1
ACH4/PMODE.0
ACH3:0
These pins may individually be used as analog inputs
(ACHx) or digital inputs (P0.x). While it is possible for the pins
to function simultaneously as analog and digital inputs, this is
not recommended because reading port 0 while a conversion
is in process can produce unreliable conversion results.
ANGND and VREF must be connected for port 0 and the A/D
converter to function.
P1.3
P1.2
P1.1
P1.0
I
Port 1. This is a 4-bit, bidirectional, standard I/O port that is
multiplexed with individually selectable special-function
signals. (Used as PBUS.15:12 in Auto-programming Mode.)
RXD1
TXD1
RXD0
TXD0
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
I/O
Port 2. This is an 8-bit, bidirectional, standard I/O port that is SCLK1#/BCLK1
multiplexed with individually selectable special-function COMP2/CPVER
signals. P2.6 is multiplexed with a special test mode function. COMP1/PACT#
To prevent accidental entry into test modes, always configure COMP0/AINC#
P2.6 as an output.
COMP3
EPA1/PROG#
SCLK0#/BCLK0/PALE#
EPA0/PVER
P3.7:0
I/O
I/O
I/O
Port 3. This is an 8-bit, bidirectional, memory-mapped I/O
port with open-drain outputs. The pins are shared with the
multiplexed address/data bus, which has complementary
drivers.
AD7:0/PBUS.7:0
In programming modes, port 3 serves as the low byte of the
programming bus (PBUS).
P4.7:0
Port 4. This is an 8-bit, bidirectional, memory-mapped I/O
port with open-drain outputs. The pins are shared with the
multiplexed address/data bus, which has complementary
drivers.
AD15:8/PBUS.15:8
In programming modes, port 4 serves as the high byte of the
programming bus (PBUS).
P5.7
P5.6
P5.5
P5.4
P5.3
P5.2
P5.1
P5.0
Port 5. This is an 8-bit, bidirectional, standard I/O port that is BUSWIDTH
multiplexed with individually selectable control signals.
Because P5.4 is multiplexed with the ONCE# function,
always configure it as an output to prevent accidental entry
into ONCE mode.
READY
BHE#/WRH#
ONCE#
RD#
WR#/WRL#
INST
ALE/ADV#
15
®
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
Table 7. Signal Descriptions (Continued)
Signal
Name
Multiplexed
With
Type
Description
P6.7
O
Port 6. This is an 8-bit output port that is multiplexed with the PWM1
P6.6
P6.5
P6.4
P6.3
P6.2
P6.1
P6.0
special functions of the waveform generator and PWM
peripherals. The WG_OUT register configures the pins,
PWM0
WG3
establishes the output polarity, and controls whether changes WG3#
to the outputs are synchronized with an event or take effect
immediately.
WG2
WG2#
WG1
WG1#
PACT#
O
I
Programming Active. In auto-programming mode, PACT#
low indicates that programming activity is occurring.
P2.5/COMP1
PALE#
Programming ALE. In slave programming mode, this active- P2.1/SCLK0#/BCLK0
low input indicates that ports 3 and 4 contain a
command/address. When PALE# is asserted, data and
commands on ports 3 and 4 are read into the device.
PBUS.15:8
PBUS.7:0
I/O
Programming Bus. In programming modes, used as a
P4.7:0/AD15:8
bidirectional port with open-drain outputs to pass commands, P3.7:0/AD7:0
addresses, and data to or from the device. Used as a regular
system bus to access external memory during auto-
programming mode. When using slave programming mode,
the PBUS is used in open-drain I/O port mode (not as a
system bus). In slave programming mode, you must add
external pull-up resistors to read data from the device during
the dump word routine.
PMODE.3
PMODE.2
PMODE.1
PMODE.0
I
I
Programming Mode Select. Determines the OTPROM
programming algorithm that is to be performed. PMODE is
sampled after a device reset when EA# = VEA and must be
stable while the device is operating.
P0.7/ACH7/T1DIR
P0.6/ACH6/T1CLK
P0.5/ACH5
P0.4/ACH4
PROG#
Programming Start. This active-low input is valid only in
slave programming mode. The rising edge of PROG# latches
data on the PBUS and begins programming. The falling edge
of PROG# ends programming.
P2.2/EPA1
O
Program Verification. In programming modes, this active-
high output signal is asserted to indicate that the word has
programmed correctly. (PVER low after the rising edge of
PROG# indicates an error.)
P2.0/EPA0
PVER
PWM1:0
RD#
O
O
Pulse Width Modulator Outputs. These are PWM output
pins with high-current drive capability. The duty cycle and
frequency-pulse-widths are programmable.
P6.7:6
P5.3
Read. Read-signal output to external memory. RD# is
asserted only during external memory reads.
16
®
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
Table 7. Signal Descriptions (Continued)
Signal
Name
Multiplexed
Type
Description
With
READY
I
Ready Input. This active-high input signal is used to
lengthen external memory cycles for slow memory by
generating wait states.
P5.6
When READY is high, CPU operation continues in a normal
manner. If READY is low, the memory controller inserts wait
states until the READY signal goes high or until the number
of wait states is equal to the number programmed into the
chip configuration register.
READY is ignored for all internal memory accesses.
RESET#
I/O
Reset. Reset input to and open-drain output from the chip. A
falling edge on RESET# initiates the reset process. When
RESET# is first asserted, the chip turns on a pull-down
transistor connected to the RESET pin for 16 state times.
This function can also be activated by execution of the RST
instruction. In the powerdown and idle modes, asserting
RESET# causes the chip to reset and return to normal
operating mode. RESET# is a level-sensitive input.
—
RXD1
RXD0
I/O
I/O
Receive Serial Data 0 and 1. In modes 1, 2, and 3, RXD0
and 1 are used to receive serial port data. In mode 0, they
function as either inputs or open-drain outputs for data.
P1.3
P1.1
SCLK1#
SCLK0#
Synchronous Clock Pin 0 and 1. In mode 4, these are the
bidrectional, shift clock signals that synchronize the serial
data transfer. Data is transferred 8 bits at a time with the LSB
first. The DIR bit (SP_CONx.7) controls the direction of
SCLKx signal.
P2.7/BCLK1
P2.1/BCLK0
DIR = 0 The internal shift clock is output on SCLKx.
DIR = 1 An external shift clock is input on SCLKx.
T1CLK
T1DIR
I
I
External Clock. External clock for timer 1. Timer 1
increments (or decrements) on both rising and falling edges
of T1CLK. Also used in conjunction with T1DIR for
quadrature counting mode.
P0.6/ACH6/PMODE.2
Timer 1 External Direction. External direction (up/down) for P0.7/ACH7/PMODE.3
timer 1. Timer 1 increments when T1DIR is high and
decrements when it is low. Also used in conjunction with
T1CLK for quadrature counting mode.
TXD1
TXD0
O
Transmit Serial Data 0 and 1. In serial I/O modes 1, 2, and
3, TXD0 and 1 are used to transmit serial port data. In mode P1.0
0, they are used as the serial clock output.
P1.2
VCC
VPP
PWR Digital Supply Voltage. Connect each VCC pin to the digital
—
supply voltage.
PWR Programming Voltage. Set to 12.5 V when programming the
on-chip OTPROM. Also the timing pin for the “return from
power-down” circuit.
—
17
®
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
Table 7. Signal Descriptions (Continued)
Description
Signal
Name
Multiplexed
With
Type
VREF
PWR Reference Voltage for the A/D Converter. VREF is also the
supply voltage to the analog portion of the A/D converter and
the logic used to read Port 0. VREF must be connected for the
A/D and port 0 to function.
—
—
VSS
GND Digital Circuit Ground (0 volts). Connect each VSS pin to
ground.
WG3
WG2
WG1
O
O
O
O
Waveform Generator Phase 1–3 Positive Outputs.
P6.5
P6.3
P6.1
3-phase output signals used in motion-control applications.
WG3#
WG2#
WG1#
Waveform Generator Phase 1–3 Negative Outputs.
Complementary 3-phase output signals used in motion-
control applications.
P6.4
P6.2
P6.0
WR#
Write. This active-low output indicates that an external write
is occurring. This signal is asserted only during external
memory writes.
P5.2/WRL#
WRH#
Write High. During 16-bit bus cycles, this active-low output
signal is asserted for high-byte writes and word writes to
external memory.
P5.5/BHE#
During 8-bit bus cycles, WRH# is asserted for all write
operations.
WRL#
XTAL1
O
I
Write Low. During 16-bit bus cycles, this active-low output
signal is asserted for low-byte writes and word writes.
During 8-bit bus cycles, WRL# is asserted for all write
operations.
P5.2/WR#
—
Clock/Oscillator Input. Input to the on-chip oscillator
inverter and the internal clock generator. Also provides the
clock input for the serial I/O baud-rate generator, timers, and
PWM unit. If an external oscillator is used, connect the
external clock input signal to XTAL1 and ensure that the
XTAL1 VIH specification is met.
XTAL2
O
Oscillator Output. Output of the on-chip oscillator inverter.
When using the on-chip oscillator, connect XTAL2 to an
external crystal or resonator. When using an external clock
source, let XTAL2 float.
—
18
®
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS*
Storage Temperature ................................ – 65°C to + 150°C
Ambient Temperature
NOTICE: This data sheet contains preliminary infor-
mation on new products in production. It is valid for
the devices indicated in the revision history. The
specifications are subject to change without notice.
under Bias.............................................. – 40°C to + 85°C
Voltage from VPP or EA# to
VSS or ANGND (Note 1) ...................... – 0.5 V to + 13.0 V
Voltage with respect to
*WARNING: Stressing the device beyond the “Absolute
Maximum Ratings” may cause permanent damage. These
are stress ratings only. Operation beyond the “Operating
Conditions” is not recommended and extended exposure
beyond the “Operating Conditions” may affect device reli-
ability.
V
SS or ANGND (Note 1) ........................ – 0.5 V to + 7.0 V
(This includes VPP on ROM and CPU devices.)
Power Dissipation .......................................................... 1.5 W
(based on package heat transfer limitations, not device
power consumption)
OPERATING CONDITIONS*
TA (Ambient Temperature Under Bias) .........– 40°C to + 85°C
V
CC (Digital Supply Voltage) .......................... 4.50 V to 5.50 V
V
REF (Analog Supply Voltage) ....................... 4.50 V to 5.50 V
F
OSC (Oscillator Frequency) (Note 2) ........... 8 MHz to 16 MHz
NOTES:
1. ANGND and VSS should be at nominally the same
potential.
2. Testing is performed down to 8 MHz, although
the device is static by design and will typically
operate below 1 Hz.
19
®
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
DC CHARACTERISTICS
Table 8. DC Characteristics over Specified Operating Conditions
Symbol
VIL
Parameter
Min
Typ (4)
Max
Units
Test Conditions
Input Low Voltage
– 0.5
0.3 VCC
V
(standard inputs (1))
VIL
Input Low Voltage
(RESET#, ports 3, 4, and
5)
– 0.5
0.8
V
1
VIH
VIH
Input High Voltage
(standard inputs (1))
0.7 VCC
VCC + 0.5
VCC + 0.5
V
V
Input High Voltage
(RESET#, ports 3, 4, and
5)
0.2 VCC + 1.0
1
VOL
Output Low Voltage
(RESET#, ports 1, 2, 5,
P6.6, P6.7, and XTAL2)
0.3
0.45
1.5
V
V
V
I
OL = 200 µA
IOL = 3.2 mA
IOL = 7.0 mA
VOL
VOL
Output Low Voltage (ports
3, 4)
1.0
V
V
IOL = 7 mA
1
Output Low Voltage
(P6.5:0)
0.45
IOL = 10 mA
2
VOH
Output High Voltage
(output pins and I/O
configured as push/pull
outputs)
VCC – 0.3
VCC – 0.7
VCC – 1.5
V
V
V
IOH = – 200 µA
IOH = – 3.2 mA
IOH = – 7.0 mA
VTH+ – VTH– Hysteresis voltage width
on RESET# pin
0.2
V
ILI
Input Leakage Current
(standard inputs (1))
± 10
± 3
µA
µA
VSS < VIN < VCC – 0.3V
VSS < VIN < VREF
ILI
Input Leakage Current
(port 0 – A/D inputs)
1
IIH
IIL
Input High Current (NMI)
300
µA
µA
VIN = 0.7 VCC
VIN = 0.3 VCC
Input Low Current (port 2,
except P2.6)
− 70
NOTES:
1. Standard input pins include XTAL1, EA#, and Ports 1 and 2 when configured as inputs.
2. Maximum current that an external device must sink to ensure test mode entry.
3. Violating these specifications during reset may cause the device to enter test modes.
4. Typical values are based on a limited number of samples and are not guaranteed. Operating conditions
for typical values are room temperature and VREF = VCC = 5.5 V.
5. Testing is performed down to 8 MHz, although the device is static by design and will typically operate
below 1 Hz.
6. All voltages are referenced relative to VSS. When used, VSS refers to the device pin.
7. Table 9 lists the total current limits during normal (non-transient conditions). The total current listed is the
sum of the pins listed for each specification value.
20
®
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
Table 8. DC Characteristics over Specified Operating Conditions (Continued)
Symbol
Parameter
Min
Typ (4)
Max
Units
Test Conditions
IIL
IIL
IIL
Input Low Current (P5.4
and P2.6 during reset) (2)
– 10
mA
VIN = 0.8 V
1
Input Low Current (ports 3,
4, and 5, except P5.4)
– 300
– 300
µA
VIN = 0.8 V
2
Input Low Current (port 1)
µA
VIN = 0.3 VCC
0.7 VCC
3
IOH
IOH
ICC
Output High Current (P5.4
and P2.6 during reset) (3)
– 0.2
– 6
mA
Output High Current
(P6.5:0 during reset)
– 40
70
µA
0.7 VCC
1
VCC Supply Current
50
2
mA
XTAL1 = 16 MHz
VCC = 5.5 V
VPP = 5.5 V
V
REF = 5.5 V
IREF
A/D Reference Supply
Current
5
mA
IIDLE
IPD
Idle Mode Current
15
5
30
50
mA
µA
Powerdown Mode Current
(4)
RRST
CS
Reset Pull-up Resistor
6
65
10
kΩ
Pin Capacitance (any pin
pF
FTEST = 1.0 MHz
to VSS
)
NOTES:
1. Standard input pins include XTAL1, EA#, and Ports 1 and 2 when configured as inputs.
2. Maximum current that an external device must sink to ensure test mode entry.
3. Violating these specifications during reset may cause the device to enter test modes.
4. Typical values are based on a limited number of samples and are not guaranteed. Operating conditions
for typical values are room temperature and VREF = VCC = 5.5 V.
5. Testing is performed down to 8 MHz, although the device is static by design and will typically operate
below 1 Hz.
6. All voltages are referenced relative to VSS. When used, VSS refers to the device pin.
7. Table 9 lists the total current limits during normal (non-transient conditions). The total current listed is the
sum of the pins listed for each specification value.
21
®
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
ICC Max
70
60
50
40
30
20
ICC Typ
ICC
(mA)
IIDLE Max
IIDLE Typ
10
0
0
4
10
16
Frequency (MHz)
A2711-01
Table 9. Total Current Limits During Normal (Non-transient) Conditions
Signal Names
Port 1
Maximum IOL Limits
25 mA
Maximum IOH Limits
– 25 mA
Port 2, P6.6, P6.7
Port 3
40 mA
– 40 mA
40 mA
– 30 mA
Port 4
40 mA
– 30 mA
Port 5
40 mA
– 30 mA
P6.5:0
40 mA
– 30 mA
Figure 6. ICC, IIDLE versus Frequency
22
®
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
EXPLANATION OF AC SYMBOLS
Each symbol consists of two pairs of letters prefixed by “T” (for time). The characters in a pair indicate a signal
and its condition, respectively. Symbols represent the time between the two signal/condition points. For example,
TRHDZ is the time between signal R (RD#) condition H (high) and signal D (Input Data) condition Z (floating). Table
10 defines the signal and condition codes.
Table 10. AC Timing Symbol Definitions
Signals
Conditions
A
B
D
G
I
Address
BHE#
P
PROG#
H
L
High
Q
R
V
Data Out
RD#
Low
Data In
V
X
Z
Valid
BUSWIDTH
T1DIR/AINC#
T1CLK
PVER
No Longer Valid
Floating
W
X
WR#/WRH#/WRL#
XTAL1
K
L
ALE/ADV#/PALE#
Y
READY
AC CHARACTERISTICS (OVER SPECIFIED OPERATION CONDITIONS)
Table 11 defines the AC timing specifications that the external memory system must meet and those that the
8XC196MH will provide.
Table 11. AC Timing Definitions (1)
Symbol
FOSC
Parameter
Frequency on XTAL1
1/FOSC
Min
8
Max
16
Units
MHz
ns
Notes
4
TOSC
62.5
125
The External Memory System Must Meet These Specifications
TAVYV
TLLYV
Address Valid to READY Setup
ALE/ADV# Low to READY Setup
Non READY Time
2TOSC – 75
TOSC – 70
No Upper Limit
ns
ns
ns
ns
ns
ns
TYLYH
TLLYX
READY Hold after ALE/ADV# Low
Address Valid to BUSWIDTH Setup
ALE/ADV# Low to BUSWIDTH Setup
TOSC – 15
2TOSC – 40
2TOSC – 75
TOSC – 60
2
TAVGV
TLLGV
NOTES:
1. Test Conditions: Capacitive load on all pins = 100 pF, rise and fall times = 10 ns, FOSC = 16 MHz.
2. Exceeding the maximum specification causes additional wait states.
3. If wait states are used, add 2TOSC × n, where n = number of wait states.
4. Testing is performed down to 8 MHz, although the device is static by design and will typically operate
below 1 Hz.
5. Assuming back-to-back bus cycles.
6. 8-bit bus only.
23
®
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
Table 11. AC Timing Definitions (1) (Continued)
Symbol
Parameter
Min
Max
Units
Notes
The External Memory System Must Meet These Specifications (Continued)
TLLGX
TLHDV
TAVDV
TRLDV
TRHDZ
TRXDX
BUSWIDTH Hold after ALE/ADV# Low
ALE/ADV# High to Input Data Valid
Address Valid to Input Data Valid
RD# Active to Input Data Valid
End of RD# to Input Data Float
Data Hold after RD# Inactive
TOSC
ns
ns
ns
ns
ns
ns
3TOSC – 55
3TOSC – 55
TOSC – 30
TOSC
3
3
0
The 8XC196MH will Meet These Specifications
TXHLH
TXHLL
TLHLH
TLHLL
XTAL1 Rising Edge to ALE Rising
20
20
110
110
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XTAL1 Rising Edge to ALE Falling
ALE/ADV# Cycle Time
4TOSC
3
ALE/ADV# High Period
TOSC – 10
TOSC – 17
TOSC – 17
TOSC – 40
TOSC – 30
TOSC – 5
TOSC
TOSC + 10
TAVLH
TAVLL
Address Valid to ALE/ADV# High
Address Valid to ALE/ADV# Low
Address Hold after ALE/ADV# Low
ALE/ADV# Low to RD# Low
RD# Low Period
TLLAX
TLLRL
TRLRH
TRHLH
TRLAZ
TLLWL
TQVWH
TWLWH
TWHQX
TWHLH
TWHBX
TWHAX
TRHBX
TRHAX
NOTES:
TOSC + 25
TOSC + 25
5
3
5
RD# High to ALE/ADV# High
RD# Low to Address Float
ALE/ADV# Low to WR# Low
Data Valid before WR# High
WR# Low Period
TOSC – 10
TOSC – 23
TOSC – 30
TOSC – 25
TOSC – 10
TOSC – 10
TOSC – 30
TOSC – 10
TOSC – 30
3
5
6
6
Data Hold after WR# High
WR# High to ALE/ADV# High
BHE#, INST Hold after WR# High
A15:8 Hold after WR# High
BHE#, INST Hold after RD# High
A15:8 Hold after RD# High
TOSC + 15
1. Test Conditions: Capacitive load on all pins = 100 pF, rise and fall times = 10 ns, FOSC = 16 MHz.
2. Exceeding the maximum specification causes additional wait states.
3. If wait states are used, add 2TOSC × n, where n = number of wait states.
4. Testing is performed down to 8 MHz, although the device is static by design and will typically operate
below 1 Hz.
5. Assuming back-to-back bus cycles.
6. 8-bit bus only.
24
®
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
SYSTEM BUS TIMINGS
T
OSC
XTAL1
ALE
T
T
XHLH
XHLL
T
LHLH
T
LHDV
T
T
T
RHLH
T
LHLL
RLRH
LLRL
RD#
T
T
T
RHDZ
AVLH
T
LLAX
RLDV
T
T
RXDX
AVLL
T
RLAZ
Address Out
BUS
WR#
Data
T
AVDV
T
T
T
WHLH
LLWL
WLWH
T
T
WHQX
QVWH
BUS
Address Out
Data Out
Address Out
T
RHBX
T
WHBX
INST
Valid
T
T
RHAX
WHAX
A15:8
(8-bit Bus)
Address Out
A2543-01
Figure 7. System Bus Timing Diagram
25
®
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
READY TIMING (ONE WAIT STATE)
T
OSC
XTAL1
T
+ 2T
OSC
LHLH
ALE
T
LLYX(Max)
T
LLYX(Min)
T
CLYX(Max)
T
CLYX(Min)
T
LLYV
READY
RD#
16 MHz
8 MHz
T
T
RLRH
+ 2T
AVYV
OSC
T
+ 2T
OSC
RLDV
T
+ 2T
AVDV
OSC
Address Out
Data In
Bus
T
+ 2T
WLWH
OSC
WR#
T
+ 2T
OSC
RLDV
T
+ 2T
QVWH
OSC
Bus
Address Out
Data Out
Address
A2544-01
Figure 8. READY Timing Diagram (One Wait State)
26
®
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
BUSWIDTH TIMING
T
OSC
XTAL1
ALE
Bus
Address Out
Data In
T
AVGV
BUSWIDTH
T
LLGV
T
LLGX
A2545-01
Figure 9. BUSWIDTH Timing Diagram
Table 12. External Clock Drive Timing
EXTERNAL CLOCK DRIVE
Symbol
Parameter
Oscillator Frequency
Min
8
Max
16
Units
MHz
ns
1/TXLXL
TXLXL
Oscillator Period (TOSC
High Time
)
62.5
22
125
TXHXX
TXLXX
TXLXH
TXHXL
ns
Low Time
22
ns
Rise Time
10
10
ns
Fall Time
ns
27
®
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
T
T
XLXH
XHXL
T
XHXX
0.7 VCC
0.7 VCC
0.7 VCC
T
XLXX
0.8 V
0.8 V
XTAL1
T
XLXL
A2578-01
Figure 10. External Clock Drive Waveforms
VCC
4.7kΩ*
External
XTAL1
8XC196 Device
XTAL2
Clock Input
Clock Driver
No Connect
Note:
*Required if TTL driver is used. Not needed if CMOS driver is used.
A0274-01
Figure 11. External Clock Connections
28
®
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
C1
XTAL1
8XC196 Device
XTAL2
VSS
C2
Quartz Crystal
Note:
Keep oscillator components close to the chip and use
short, direct traces to XTAL1, XTAL2, and Vss. When
using crystals, C1=C2≈20pF. When using ceramic
resonators, consult the manufacturer for recommended
oscillator circuitry.
A0273-01
Figure 12. External Crystal Connections
3.5 V
2.0 V
0.8 V
2.0 V
0.8 V
Test Points
0.45 V
AC testing inputs are driven at 3.5 V for a logic "1" and 0.45 V for
a logic "0". Timing measurements are made at 2.0 V for a logic
"1" and 0.8 V for a logic "0".
A2120-02
Figure 13. AC Testing Input, Output Waveforms
29
®
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
VLOAD + 0.1 V
VOH – 0.1 V
Timing Reference
Points
VLOAD
VLOAD – 0.1 V
VOL + 0.1 V
For timing purposes, a port pin is no longer floating when a
100 mV change from load voltage occurs and begins to float
when a 100 mV change from the loading VOH/VOL level occurs
with IOL/IOH ≤15 mA.
A2579-01
Figure 14. Float Waveforms
AC CHARACTERISTICS — SERIAL PORT, SHIFT REGISTER MODE
Table 13. Serial Port Timing — Shift Register Mode (Mode 0)
Symbol
Parameter
Min
Max
Units
Notes
TXLXL
Serial Port Clock Period
(Baud-raten ≥ 8002H)
(Baud-raten = 8001H)
6TOSC
4TOSC
ns
ns
1, 2
1, 2
TXLXH
Serial Port Clock Low Period
(Baud-raten ≥ 8002H)
(Baud-raten = 8001H)
4TOSC – 50
2TOSC – 50
4TOSC + 50
2TOSC + 50
ns
ns
TQVXH
TXHQX
TXHQV
TDVXH
TXHDX
TXHQZ
NOTES:
Output Data Setup to Clock High
Output Data Hold after Clock High
Next Output Data Valid after Clock High
Input Data Setup to Clock High
Input Data Hold after Clock High
Last Clock High to Output Float
2TOSC – 50
2TOSC – 50
ns
ns
ns
ns
ns
ns
2TOSC + 50
TOSC + 50
0
TOSC
1. n for Baud-raten signifies Serial Port 0 or 1.
2. Maximum Serial Port Mode 0 reception is with Baud-raten ≥ 8002H.
30
®
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
T
XLXL
T
TXDn
T
T
XHQV
XLXH
T
T
XHQZ
XHQX
5
QVXH
RXDn
(Out)
0
1
2
7
4
6
3
T
T
DVXH
XHDX
Valid
RXDn
(In)
Valid
Valid
Valid
Valid
Valid
Valid
Valid
A2080-01
Figure 15. Serial Port Waveform — Shift Register Mode (Mode 0)
Table 14. Serial Port Timing — Mode 4
Symbol
TXLXL
Parameter
Min
16TOSC
(TXLXL/2) – 30
(TXLXL/2) – 30
16TOSC
0
Max
Units
ns
Serial Port Clock Period (DIR=0)
Serial Port Clock Low Period (DIR=0/1)
Serial Port Clock High Period (DIR=0/1)
Serial Port Clock Period (DIR=1)
Serial Clock Falling Time (DIR=1)
Serial Clock Rising Time (DIR=1)
Clock Low to Output Data Setup
Output Data Hold after Clock Low
Last Output Data Hold after Clock High (DIR=1)
Input Data Setup to Clock Low Invalid
Input Data Hold after Clock High
131072TOSC
TXLXX
TXHXX
TXLXL
TXHXL
TXLXH
TXLQV
TXLQX
TXHQX
TDVXX
TXHDH
ns
ns
ns
20
20
ns
0
ns
7.5TOSC – 50
ns
0
13.7TOSC
0
ns
ns
ns
6TOSC
ns
31
®
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
T
XLXL
T
T
XLXX
XHXX
SCKn#
T
T
XHDH
DVXX
RXDn
TXDn
T
T
XLQV
XLQX
T
XHQX
A2550-01
Figure 16. Serial Port Waveform — Mode 4
T
T
T
XHXL
XLXH
XHXX
V
IH
T
XLXX
V
IL
SCKn#
T
XLXL
A2582-01
Figure 17. Serial Port Waveform — Clock Drive (DIR = 1)
32
®
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
BAUD-RATE CLOCK DRIVE TABLE
Table 15. Baud Rate Clock Drive
Symbol
TXLXL
Parameter
Baud Rate Clock Period
Min
Max
Units
ns
4TOSC
TXHXX
TXLXX
TXLXH
TXHXL
Baud Rate Clock High Time
Baud Rate Clock Low Time
Baud Rate Clock Rise Time
Baud Rate Clock Fall Time
2TOSC – 30
2TOSC – 30
ns
ns
20
20
ns
ns
T
T
T
XHXL
XHXX
XLXH
V
IH
T
XLXX
V
IL
BCLKn
T
XLXL
A2551-01
Figure 18. Baud-Rate Clock Drive Waveforms
33
®
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
Use the following formulas to determine the SAM and
CONV values:
A/D SAMPLE AND CONVERSION TIMES
Two parameters, sample time and conversion time,
control the time required for an A/D conversion. The
sample time is the length of time that the analog input
voltage is actually connected to the sample capacitor.
If this time is too short, the sample capacitor will not
charge completely. If the sample time is too long, the
input voltage may change and cause conversion
errors. The conversion time is the length of time
required to convert the analog input voltage stored on
TSAM × FOSC – 2
SAM = ----------------------------------------
8
TCONV × FOSC – 3
-------------------------------------------
CONV =
– 1
2 × B
where:
SAM = 1 to 7
the sample capacitor to
a digital value. The
CONV = 2 to 31
TSAM is the sample time, in µsec
conversion time must be long enough for the
comparator and circuitry to settle and resolve the
voltage. Excessively long conversion times allow the
sample capacitor to discharge, degrading accuracy.
(Tables 16 and 18)
TCONV is the conversion time, in µsec
(Tables 16 and 18)
F
OSC is the XTAL1 frequency, in MHz
The AD_TIME register programs the A/D sample and
conversion times. Use the TSAM and TCONV specifica-
tions in Tables 16 and 18 to determine appropriate
values for SAM and CONV; otherwise, erroneous
conversion results may occur.
B is the number of bits to be converted (8 or 10)
When the SAM and CONV values are known, write
them to the AD_TIME register. Do not write to this
register while a conversion is in progress; the results
are unpredictable.
34
®
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
AC CHARACTERISTICS — A/D CONVERTER
Table 16. 10-bit A/D Operating Conditions (1)
Symbol
Description
Ambient Temperature
Digital Supply Voltage
Analog Supply Voltage
Sample Time
Min
– 40
4.50
4.50
1.0
Max
+ 85
5.50
5.50
Units
°C
V
Notes
T
A
VCC
VREF
TSAM
TCONV
FOSC
V
2
3
3
µs
Conversion Time
10.0
8
20.0
16
µs
Oscillator Frequency
MHz
NOTES:
1. ANGND and VSS should nominally be at the same potential.
2. VREF must not exceed VCC by more than + 0.5 V because VREF supplies both the resistor ladder and the
analog portion of the converter and input port pins.
3. Program the AD_TIME register to meet the TSAM and TCONV specifications.
Table 17. 10-bit Mode A/D Characteristics Over Specified Operating Conditions (1)
Parameter
Resolution
Typical (3)
Min
Max
Units (2)
Notes
1024
10
1024
10
Levels
Bits
Absolute Error
0
± 3
LSBs
LSBs
LSBs
LSBs
LSBs
LSBs
LSBs
Full-scale Error
Zero Offset Error
Nonlinearity
0.25 ± 0.5
0.25 ± 0.5
1.0 ± 2.0
± 3
+ 0.75
± 1
Differential Nonlinearity
Channel-to-channel Matching
Repeatability
– 0.75
± 0.1
0
0
± 0.25
NOTES:
1. Testing is performed with VREF = 5.12 V and FOSC = 16 MHz.
2. An LSB, as used here, has a value of approximately 5 mV.
3. Typical values are based on a limited number of samples and are not guaranteed. Operating conditions
for typical values are room temperature and VREF = VCC = 5.5 V.
4. DC to 100 KHz.
5. Multiplexer break-before-make guaranteed.
6. Resistance from device pin, through internal multiplexer, to sample capacitor.
7. These values may be exceeded if the pin current is limited to ± 2mA.
8. Applying voltage beyond these specifications will degrade the accuracy of other channels being con-
verted.
9. All conversions were performed with processor in idle mode.
35
®
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
Table 17. 10-bit Mode A/D Characteristics Over Specified Operating Conditions (1) (Continued)
Parameter
Typical (3)
Min
Max
Units (2)
Notes
Temperature Coefficients:
Offset
0.009
0.009
0.009
LSB/C
LSB/C
LSB/C
Full-scale
Differential Nonlinearity
Off-isolation
Feedthrough
– 60
dB
dB
dB
Ω
4, 5
4
– 60
– 60
V
CC Power Supply Rejection
6
Input Series Resistance
Voltage on Analog Input Pin
Sampling Capacitor
DC Input Leakage
NOTES:
750
1.2K
4
ANGND – 0.5
VREF + 0.5
V
7, 8
3
pF
µA
± 1.0
0
± 3
1. Testing is performed with VREF = 5.12 V and FOSC = 16 MHz.
2. An LSB, as used here, has a value of approximately 5 mV.
3. Typical values are based on a limited number of samples and are not guaranteed. Operating conditions
for typical values are room temperature and VREF = VCC = 5.5 V.
4. DC to 100 KHz.
5. Multiplexer break-before-make guaranteed.
6. Resistance from device pin, through internal multiplexer, to sample capacitor.
7. These values may be exceeded if the pin current is limited to ± 2mA.
8. Applying voltage beyond these specifications will degrade the accuracy of other channels being con-
verted.
9. All conversions were performed with processor in idle mode.
Table 18. 8-bit A/D Operating Conditions (1)
Symbol
Description
Ambient Temperature
Digital Supply Voltage
Analog Supply Voltage
Sample Time
Min
– 40
4.50
4.50
1.0
Max
+ 85
5.50
5.50
Units
°C
V
Notes
T
A
vCC
vREF
V
2
3
3
TSAM
TCONV
FOSC
µs
Conversion Time
7.0
20.0
16
µs
Oscillator Frequency
8
MHz
NOTES:
1. ANGND and VSS should nominally be at the same potential.
2. VREF must not exceed VCC by more than + 0.5 V because VREF supplies both the resistor ladder and the
analog portion of the converter and input port pins.
3. Program the AD_TIME register to meet the TSAM and TCONV specifications.
36
®
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
Table 19. 8-bit Mode A/D Characteristics Over Specified Operating Conditions (1)
Parameter
Typical (3)
Min
Max
Units (2)
Notes
Resolution
256
8
256
8
Levels
Bits
Absolute Error
0
± 1
LSBs
LSBs
LSBs
LSBs
LSBs
LSBs
LSBs
Full-scale Error
± 0.5
Zero Offset Error
Nonlinearity
± 0.5
0
– 0.5
0
± 1
+ 0.5
± 1
Differential Nonlinearity
Channel-to-channel Matching
Repeatability
± 0.25
0
Temperature Coefficients:
Offset
0.003
0.003
0.003
LSB/°C
LSB/°C
LSB/°C
Full-scale
Differential Nonlinearity
Off Isolation
– 60
dB
dB
dB
Ω
4, 5
4
Feedthrough
– 60
– 60
VCC Power Supply Rejection
Input Series Resistance
Voltage on Analog Input Pin
Sampling Capacitor
DC Input Leakage
NOTES:
4
750
1.2K
6
ANGND – 0.5
VREF + 0.5
V
7, 8
3
pF
µA
± 1
0
± 3
1. Testing is performed with VREF = 5.12 V and FOSC = 16 MHz.
2. An LSB, as used here, has a value of approximately 20 mV.
3. Typical values are based on a limited number of samples and are not guaranteed. Operating conditions
for typical values are room temperature and VREF = VCC = 5.5 V.
4. DC to 100 KHz.
5. Multiplexer break-before-make guaranteed.
6. Resistance from device pin, through internal multiplexer, to sample capacitor.
7. These values may be exceeded if the pin current is limited to ± 2mA.
8. Applying voltage beyond these specifications will degrade the accuracy of other channels being con-
verted.
9. All conversions were performed with processor in idle mode.
37
®
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
OTPROM SPECIFICATIONS
Table 20. Programming Operating Conditions
Symbol
Description
Ambient Temperature
Min
20
Max
30
Units
°C
V
Notes
T
A
vCC
Supply Voltage During Programming
4.50
4.50
5.50
5.50
3
3
vREF
Reference Supply Voltage During
Programming
V
VPP
VEA
Programming Voltage
EA Pin Voltage
12.25
12.25
6
12.75
12.75
8
V
V
2
2
FOSC
Oscillator Frequency During Auto and
Slave Mode Programming
Oscillator Frequency During Run-Time
Programming
MHz
6
12
MHz
NOTES:
1. VCC and VREF should be at nominally the same voltage during programming.
2. If VPP and VEA exceed the maximum specification, the device may be damaged.
3.
VSS and ANGND should be at nominally the same potential (0 volts).
4. Load capacitance during auto and slave mode programming = 150 pF.
Table 21. AC OTPROM Programming Characteristics
Symbol
TAVLL
Description
Address Setup Time
Min
0
Max
Units
TOSC
TOSC
TOSC
TOSC
TOSC
TOSC
TOSC
TOSC
TOSC
TOSC
TOSC
TOSC
TOSC
TOSC
TLLAX
TDVPL
TPLDX
TLLLH
TPLPH
TPHLL
TPHDX
TPHPL
TLHPL
TPLDV
TSHLL
TPHIL
Address Hold Time
100
0
Data Setup Time
Data Hold Time
400
50
PALE# Pulse Width
PROG# Pulse Width (1)
PROG# High to Next PALE# Low
Word Dump Hold Time
50
220
50
50
PROG# High to Next PROG# Low
PALE# High to PROG# Low
PROG# Low to Word Dump Valid
RESET# High to First PALE# Low
PROG# High to AINC# Low
AINC# Pulse Width
220
220
1100
0
TILIH
240
NOTE:
1. This specification is for Word Dump Mode. For programming pulses, use the Modified Quick Pulse Algo-
rithm explained in the User’s Manual.
38
®
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
Table 21. AC OTPROM Programming Characteristics (Continued)
Symbol
TILVH
Description
PVER Hold after AINC# Low
AINC# Low to PROG# Low
PROG# High to PVER Valid
Min
50
Max
Units
TOSC
TOSC
TOSC
TILPL
170
TPHVL
220
NOTE:
1. This specification is for Word Dump Mode. For programming pulses, use the Modified Quick Pulse Algo-
rithm explained in the User’s Manual.
Table 22. DC OTPROM Programming Characteristics
Symbol
Parameter
Min
Max
Units
IPP
VPP Supply Current (when
programming)
100
mA
NOTE: Do not apply VPP until VCC is stable and within specifications and the oscillator/clock has stabiliized.
Otherwise, the device may be damaged.
OTPROM PROGRAMMING WAVEFORMS
RESET#
T
AVLL
PORTS 3/4
Address/Command
Data
Address/Command
T
T
SHLL
LLAX
T
T
DVPL PLDX
PALE#
T
PHLL
T
T
T
LLLH
LHPL
PLPH
PROG#
PVER
T
PHVL
A2549-01
Figure 19. Slave Programming Mode Data Program Mode with Single Program Pulse
39
®
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
RESET#
Address
Address + 2
Address/Command
T
Ver Bits/Word Dump
Ver Bits/Word Dump
PORTS 3/4
T
T
T
SHLL
PLDV
PHDX
PLDV
T
PHDX
PALE#
PROG#
AINC#
T
T
ILPL
PHPL
Note: P3.0 must be low ("0")
A2546-01
Figure 20. Slave Programming Mode in Word Dump with Autoincrement Timing
SLAVE PROGRAMMING MODE IN WORD DUMP WITH AUTOINCREMENT
RESET#
Address
Data
Address
Data
Address + 2
Data
Address/Command
PORTS 3/4
PALE#
T
T
PHPL
ILPL
P1
PN
PROG#
T
ILVH
Valid for
PN
Valid for P1
PVER
AINC#
T
ILIH
T
PHIL
A2547-01
Figure 21. Slave Programming Mode in Data Program with Repeated Program Pulse and Autoincrement
40
®
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
8XC196MC/MD TO 8XC196MH DESIGN
CONSIDERATIONS
The 8XC196MH is not pin compatible with the
8XC196MC or the 8XC196MD. Be aware that signal
multiplexing sometimes differs between the
8XC196MH and the 8XC196MC/MD. For example,
P2.7 is multiplexed with COMP3 on the
8XC196MC/MD and with SCLK1# and BCLK1 on the
8XC196MH.
DATA SHEET REVISION HISTORY
The -003 revisions were made due to the changes
required for the lead free initiative. To address the
fact that many of the package prefix variables have
changed, all package prefix variables in this document
are now indicated with an "x".
41
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明