N28F001BX-B120 [INTEL]
1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY; 1兆位（ 128K ×8 ）， BOOT BLOCK FLASH MEMORY
| 型号： | N28F001BX-B120 |
| 厂家： | 
INTEL |
| 描述： | 1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY |
| 文件： | 总33页 (文件大小：437K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1-MBIT (128K x 8)
BOOT BLOCK FLASH MEMORY
28F001BX-T/28F001BX-B/28F001BN-T/28F001BN-B
Y
Y
High-Integration Blocked Architecture
High-Performance Read
Ð 70/75 ns, 90 ns, 120 ns, 150 ns
Maximum Access Time
Ð One 8 KB Boot Block w/Lock Out
Ð Two 4 KB Parameter Blocks
Ð One 112 KB Main Block
g
Ð 5.0V 10% V
CC
Y
Y
Y
Y
Y
100,000 Erase/Program Cycles Per
Block
Hardware Data Protection Feature
Ð Erase/Write Lockout during Power
Transitions
Simplified Program and Erase
Ð Automated Algorithms via On-Chip
Write State Machine (WSM)
Advanced Packaging, JEDEC Pinouts
Ð 32-Pin PDIP
Ð 32-Lead PLCC, TSOP
Y
Y
SRAM-Compatible Write Interface
Deep Power-Down Mode
ETOXTM II Nonvolatile Flash
Technology
Ð EPROM-Compatible Process Base
Ð High-Volume Manufacturing
Experience
Ð 0.05 mA I
Typical
CC
Ð 0.8 mA I Typical
PP
Y
g
12.0V 5% V
PP
Y
Extended Temperature Options
Intel’s 28F001BX-B and 28F001BX-T combine the cost-effectiveness of Intel standard flash memory with
features that simplify write and allow block erase. These devices aid the system designer by combining the
functions of several components into one, making boot block flash an innovative alternative to EPROM and
EEPROM or battery-backed static RAM. Many new and existing designs can take advantage of the
28F001BX’s integration of blocked architecture, automated electrical reprogramming, and standard processor
interface.
The 28F001BX-B and 28F001BX-T are 1,048,576 bit nonvolatile memories organized as 131,072 bytes of
8 bits. They are offered in 32-pin plastic DIP, 32-lead PLCC and 32-lead TSOP packages. Pin assignment
conform to JEDEC standards for byte-wide EPROMs. These devices use an integrated command port and
state machine for simplified block erasure and byte reprogramming. The 28F001BX-T’s block locations pro-
vide compatibility with microprocessors and microcontrollers that boot from high memory, such as Intel’s
MCS -186 family, 80286, i386TM, i486TM, i860TM and 80960CA. With exactly the same memory segmentation,
É
the 28F001BX-B memory map is tailored for microprocessors and microcontrollers that boot from low memory,
such as Intel’s MCS-51, MCS-196, 80960KX and 80960SX families. All other features are identical, and unless
otherwise noted, the term 28F001BX can refer to either device throughout the remainder of this document.
The boot block section includes a reprogramming write lock out feature to guarantee data integrity. It is
designed to contain secure code which will bring up the system minimally and download code to the other
locations of the 28F001BX. Intel’s 28F001BX employs advanced CMOS circuitry for systems requiring high-
performance access speeds, low power consumption, and immunity to noise. Its access time provides
no-WAIT-state performance for a wide range of microprocessors and microcontrollers. A deep-powerdown
mode lowers power consumption to 0.25 mW typical through V , crucial in laptop computer, handheld instru-
CC
mentation and other low-power applications. The RP power control input also provides absolute data protec-
tion during system powerup or power loss.
Ý
Manufactured on Intel’s ETOX process base, the 28F001BX builds on years of EPROM experience to yield the
highest levels of quality, reliability, and cost-effectiveness.
NOTE: The 28F001BN is equivalent to the 28F001BX.
*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
©
COPYRIGHT INTEL CORPORATION, 1995
November 1995
Order Number: 290406-007
28F001BX-T/28F001BX-B
290406–1
Figure 1. 28F001BX Block Diagram
Table 1. Pin Description
Name and Function
Symbol
A –A
Type
INPUT
ADDRESS INPUTS for memory addresses. Addresses are internally latched during
a write cycle.
0
16
DQ –DQ
0
INPUT/ DATA INPUTS/OUTPUTS: Inputs data and commands during memory write
7
cycles; outputs data during memory, Status Register and Identifier read cycles. The
data pins are active high and float to tri-state off when the chip is deselected or the
outputs are disabled. Data is internally latched during a write cycle.
OUTPUT
Ý
Ý
CE
RP
INPUT
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and
Ý
Ý
sense amplifiers. CE is active low; CE high deselects the memory device and
reduces power consumption to standby levels.
Ý
POWERDOWN: Puts the device in deep powerdown mode. RP is active low;
INPUT
e
block. RP also locks out erase or write operations when active low, providing data
Ý
RP high gates normal operation. RP
Ý
V
allows programming of the boot
HH
Ý
protection during power transitions. RP active resets internal automation. Exit
Ý
from deep powerdown sets device to Read Array mode.
Ý
OE
INPUT
INPUT
OUTPUT ENABLE: Gates the device’s outputs through the data buffers during a
e
boot block.
Ý
read cycle. OE is active low. OE
Ý
V
(pulsed) allows programming of the
HH
Ý
Ý
WRITE ENABLE: Controls writes to the Command Register and array blocks. WE
WE
Ý
is active low. Addresses and data are latched on the rising edge of the WE pulse.
V
PP
ERASE/PROGRAM POWER SUPPLY for erasing blocks of the array or
k
programming bytes of each block. Note: With V
cannot be altered.
V
max, memory contents
PPL
PP
g
DEVICE POWER SUPPLY: (5V 10%)
V
CC
GND
GROUND
2
28F001BX-T/28F001BX-B
28F010
28F010
V
PP
V
CC
Ý
A
A
A
WE
NC
16
15
12
A
A
14
A
7
6
5
4
3
2
1
0
13
A
A
8
A
A
A
A
A
A
A
9
A
11
Ý
OE
A
10
Ý
CE
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
DQ
DQ
DQ
0
1
2
GND
290406–2
Figure 2. DIP Pin Configuration
28F010
28F010
Ý
OE
A
11
A
A
A
10
CE
9
8
Ý
A
A
NC
DQ
DQ
DQ
DQ
DQ
13
14
7
6
5
4
3
Ý
WE
V
CC
V
GND
PP
A
A
A
DQ
DQ
DQ
16
2
1
0
15
12
A
A
A
A
A
A
A
A
7
6
5
4
0
1
2
3
290406–3
Figure 3. TSOP Lead Configuration
3
28F001BX-T/28F001BX-B
290406–4
Figure 4. PLCC Lead Configuration
The flexibility of flash memory reduces costs
throughout the life cycle of a design. During the early
stages of a system’s life, flash memory reduces pro-
totype development and testing time, allowing the
system designer to modify in-system software elec-
trically versus manual removal of components. Dur-
ing production, flash memory provides flexible firm-
ware for just-in-time configuration, reducing system
inventory and eliminating unnecessary handling and
less reliable socketed connections. Late in the life
cycle, when software updates or code ‘‘bugs’’ are
often unpredictable and costly, flash memory reduc-
es update costs by allowing the manufacturers to
send floppy updates versus a technician. Alterna-
tively, remote updates over a communication link are
possible at speeds up to 9600 baud due to flash
memory’s fast programming time.
APPLICATIONS
The 28F001BX flash ‘boot block’ memory augments
the non-volatility, in-system electrical erasure and
reprogrammability of Intel’s standard flash memory
by offering four separately erasable blocks and inte-
grating a state machine to control erase and pro-
gram functions. The specialized blocking architec-
ture and automated programming of the 28F001BX
provide a full-function, non-volatile flash memory
ideal for a wide range of applications, including PC
boot/BIOS memory, minimum-chip embedded pro-
gram memory and parametric data storage. The
28F001BX combines the safety of a hardware-pro-
tected 8-KByte boot block with the flexibility of three
separately reprogrammable blocks (two 4-KByte pa-
rameter blocks and one 112-KByte code block) into
one versatile, cost-effective flash memory. Addition-
ally, reprogramming one block does not affect code
stored in another block, ensuring data integrity.
4
28F001BX-T/28F001BX-B
Reprogrammable environments, such as the per-
sonal computer, are ideal applications for the
28F001BX. The internal state machine provides
SRAM-like timings for program and erasure, using
the Command and Status Registers. The blocking
scheme allows BIOS update in the main and param-
eter blocks, while still providing recovery code in the
boot block in the unlikely event a power failure oc-
curs during an update, or where BIOS code is cor-
rupted. Parameter blocks also provide convenient
configuration storage, backing up SRAM and battery
configurations. EISA systems, for example, can
store hardware configurations in a flash parameter
block, reducing system SRAM.
tem power requirements during periods of slow op-
eration or sleep modes.
The 28F001BX gives the embedded system design-
er several desired features. The internal state ma-
chine reduces the size of external code dedicated to
the erase and program algorithms, as well as freeing
the microcontroller or microprocessor to respond to
other system requests during program and erasure.
The four blocks allow logical segmentation of the
entire embedded software: the 8-KByte block for the
boot code, the 112-KByte block for the main pro-
gram code and the two 4-KByte blocks for updatable
parametric data storage, diagnostic messages and
data, or extensions of either the boot code or pro-
gram code. The boot block is hardware protected
against unauthorized write or erase of its vital code
in the field. Further, the powerdown mode also locks
out erase or write operations, providing absolute
data protection during system powerup or power
loss. This hardware protection provides obvious ad-
vantages for safety related applications such as
transportation, military, and medical. The 28F001BX
is well suited for minimum-chip embedded applica-
tions ranging from communications to automotive.
Laptop BIOSs are becoming increasingly complex
with the addition of power management software
and extended system setup screens. BIOS code
complexity increases the potential for code updates
after the sale, but the compactness of laptop de-
signs makes hardware updates very costly. Boot
block flash memory provides an inexpensive update
solution for laptops, while reducing laptop obsoles-
cence. For portable PCs and hand-held equipment,
the deep powerdown mode dramatically lowers sys-
290406–5
Figure 5. 28F001BX-T in a 80C188 System
290406–6
Figure 6. 28F001BX-B in a 80C51 System
5
28F001BX-T/28F001BX-B
PRINCIPLES OF OPERATION
Data Protection
The 28F001BX introduces on-chip write automation
to manage write and erase functions. The write state
machine allows for 100% TTL-level control inputs,
fixed power supplies during erasure and program-
ming, minimal processor overhead with RAM-like
write timings, and maximum EPROM compatiblity.
Depending on the application, the system designer
may choose to make the V power supply switcha-
PP
ble (available only when memory updates are re-
e
quired) or hardwired to V
. When V
V
,
PPH
PP
PPL
memory contents cannot be altered. The 28F001BX
Command Register architecture provides protection
from unwanted program or erase operations even
After initial device powerup, or after return from
deep powerdown mode (see Bus Operations), the
28F001BX functions as a read-only memory. Manip-
ulation of external memory-control pins yield stan-
dard EPROM read, standby, output disable or Intelli-
gent Identifier operations. Both Status Register and
Intelligent Identifiers can be accessed through the
when high voltage is applied to V . Additionally, all
is below the
PP
functions are disabled whenever V
CC
Ý
, or when RP is at V .
IL
write lockout voltage V
LKO
The 28F001BX accommodates either design prac-
tice and encourages optimization of the processor-
memory interface.
e
Command Register when V
V
.
PP
PPL
The two-step program/erase write sequence to the
Command Register provides additional software
write protection.
This same subset of operations is also available
when high voltage is applied to the V pin. In addi-
PP
tion, high voltage on V enables successful erasure
PP
and programming of the device. All functions associ-
ated with altering memory contentsÐprogram,
erase, status, and int ligent IdentifierÐare accessed
1FFFF
e
8-KByte BOOT BLOCK
via the Command Register and verified through the
Status Register.
1E000
1DFFF
Commands are written using standard microproces-
sor write timings. Register contents serve as input to
the WSM, which controls the erase and program-
ming circuitry. Write cycles also internally latch ad-
dresses and data needed for programming or erase
operations. With the appropriate command written to
the register, standard microprocessor read timings
output array data, access the intelligent identifier
codes, or output program and erase status for verifi-
cation.
4-KByte PARAMETER BLOCK
1D000
1CFFF
4-KByte PARAMETER BLOCK
1C000
1BFFF
112-KByte MAIN BLOCK
Interface software to initiate and poll progress of in-
ternal program and erase can be stored in any of the
28F001BX blocks. This code is copied to, and exe-
cuted from, system RAM during actual flash memory
update. After successful completion of program
and/or erase, code execution out of the 28F001BX
is again possible via the Read Array command.
Erase suspend/resume capability allows system
software to suspend block erase and read data/exe-
cute code from any other block.
00000
Figure 7. 28F001BX-T Memory Map
1FFFF
112-KByte MAIN BLOCK
Command Register and Write
Automation
An on-chip state machine controls block erase and
byte program, freeing the system processor for other
tasks. After receiving the erase setup and erase
confirm commands, the state machine controls
block pre-conditioning and erase, returning progress
via the Status Register. Programming is similarly
controlled, after destination address and expected
data are supplied. The program algorithm of past In-
tel Flash Memories is now regulated by the state
machine, including program pulse repetition where
required and internal verification and margining of
data.
04000
03FFF
4-KByte PARAMETER BLOCK
03000
02FFF
4-KByte PARAMETER BLOCK
02000
01FFF
8-KByte BOOT BLOCK
00000
Figure 8. 28F001BX-B Memory Map
6
28F001BX-T/28F001BX-B
BUS OPERATION
Standby
Ý
Flash memory reads, erases and writes in-system
via the local CPU. All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles.
CE at a logic-high level (V ) places the 28F001BX
IH
in standby mode. Standby operation disables much
of the 28F001BX’s circuitry and substantially reduc-
es device power consumption. The outputs (DQ –
0
DQ ) are placed in a high-impedance state indepen-
Ý
7
dent of the status of OE . If the 28F001BX is dese-
lected during erase or program, the device will
continue functioning and consuming normal active
power until the operation is completed.
Read
The 28F001BX has three read modes. The memory
can be read from any of its blocks, and information
can be read from the Intelligent Identifier or the
Status Register. V can be at either V
PP
or V
.
PPH
PPL
Deep Power-Down
The first task is to write the appropriate read mode
command to the Command Register (array, Intelli-
gent Identifier, or Status Register). The 28F001BX
automatically resets to Read Array mode upon initial
device powerup or after exit from deep powerdown.
The 28F001BX has four control pins, two of which
must be logically active to obtain data at the outputs.
The 28F001BX offers a 0.25 mW V
power-down
feature, entered when RP is at V . During read
CC
Ý
modes, RP low deselects the memory, places out-
IL
Ý
put drivers in a high-impedance state and turns off
all internal circuits. The 28F001BX requires time
t
(see AC Characteristics-Read Only Opera-
PHQV
tions) after return from power-down until initial mem-
ory access outputs are valid. After this wakeup inter-
val, normal operation is restored. The Command
Register is reset to Read Array, and the Status Reg-
ister is cleared to value 80H, upon return to normal
operation.
Ý
Chip Enable (CE ) is the device selection control,
and when active enables the selected memory de-
Ý
vice. Output Enable (OE ) is the data input/output
(DQ –DQ ) direction control, and when active
drives data from the selected memory onto the I/O
0
7
Ý
Ý
bus. RP and WE must also be at V . Figure 12
illustrates read bus cycle waveforms.
IH
Ý
During erase or program modes, RP low will abort
either operation. Memory contents of the block be-
ing altered are no longer valid as the data will be
partially programmed or erased. Time t after
PHWL
RP goes to logic-high (V ) is required before an-
Output Disable
Ý
other command can be written.
IH
Ý
With OE at a logic-high level (V ), the device out-
puts are disabled. Output pins (DQ –DQ ) are
IH
0
7
placed in a high-impedance state.
Table 2. 28F001BX Bus Operations
Ý
Ý
Ý
Ý
WE
Mode
Notes
RP
CE
OE
A
A
V
PP
DQ
0–7
9
0
Read
1, 2, 3
V
V
V
V
V
V
V
V
X
X
X
X
X
X
X
X
X
D
OUT
IH
IL
IL
IH
IH
Output Disable
2
V
IH
X
X
X
X
X
X
High Z
High Z
High Z
89H
IH
IH
IL
Standby
2
2
V
X
X
IH
Deep Power Down
Intelligent Identifier (Mfr)
V
X
X
X
IL
IH
IH
IH
2, 3, 4
V
V
V
V
V
V
V
V
V
V
IL
IL
IL
IL
IL
IL
IH
IH
IH
ID
ID
Intelligent Identifier (Device) 2, 3, 4, 5
V
V
V
V
IH
94H, 95H
Write
2, 6, 7, 8
V
V
X
X
D
IN
IL
NOTES:
1. Refer to DC Characteristics. When V
2. X can be V or V for control pins and addresses, and V
IL IH
e
V
, memory contents can be read but not programmed or erased.
for V
PP
PPL
or V
.
PP
PPL
and V voltages.
PPH
3. See DC Characteristics for V
, V
, V
PPL PPH HH
ID
4. Manufacturer and device codes may also be accessed via a Command Register write sequence. Refer to Table 3. A –A ,
1
8
e
V .
IL
A
–A
10
5. Device ID
6. Command writes involving block erase or byte program are successfully executed only when V
16
e
94H for the 28F001BX-T and 95H for the 28F001BX-B.
e
V
PPH
.
PP
7. Refer to Table 3 for valid D during a write operation.
Ý
IN
8. Program or erase the boot block by holding RP at V
operations.
Ý
or toggling OE to V . See AC Waveforms for program/erase
HH
HH
7
28F001BX-T/28F001BX-B
Setup and Erase Confirm commands require both
appropriate command data and an address within
the block to be erased. The Program Setup Com-
mand requires both appropriate command data and
the address of the location to be programmed, while
the Program command consists of the data to be
written and the address of the location to be pro-
grammed.
Ý
The use of RP during system reset is important
with automated write/erase devices. When the sys-
tem comes out of reset it expects to read from the
flash memory. Automated flash memories provide
status information when accessed during write/
erase modes. If a CPU reset occurs with no flash
memory reset, proper CPU initialization would not
occur because the flash memory would be providing
the status information instead of array data. Intel’s
Flash Memories allow proper CPU initialization fol-
Ý
to a logic-low level (V ) while CE is low. Address-
The Command Register is written by bringing WE
Ý
IL
Ý
lowing a system reset through the use of the RP
Ý
input. In this application RP is controlled by the
same RESET signal that resets the system CPU.
Ý
es and data are latched on the rising edge of WE
Standard microprocessor write timings are used.
.
Ý
Refer to AC Write Characteristics and the AC Wave-
form for Write Operations, Figure 13, for specific tim-
ing parameters.
Intelligent Identifier Operation
The Intelligent Identifier operation outputs the manu-
facturer code, 89H; and the device code, 94H for the
28F001BX-T and 95H for the 28F001BX-B. Pro-
gramming equipment or the system CPU can then
automatically match the device with its proper erase
and programming algorithms.
COMMAND DEFINITIONS
When V
is applied to the V
pin, read opera-
PP
PPL
tions from the Status Register, intelligent identifiers,
or array blocks are enabled. Placing V on V
enables successful program and erase operations
as well.
PPH
PP
PROGRAMMING EQUIPMENT
Device operations are selected by writing specific
commands into the Command Register. Table 3 de-
fines these 28F001BX commands.
Ý
Ý
CE and OE at a logic low level (V ), with A at
high voltage V (see DC Characteristics) activates
IL
9
ID
this operation. Data read from locations 00000H and
00001H represent the manufacturer’s code and the
device code respectively.
Read Array Command
Upon initial device powerup and after exit from
deep-powerdown mode, the 28F001BX defaults to
Read Array mode. This operation is also initiated by
writing FFH into the Command Register. Microproc-
essor read cycles retrieve array data. The device re-
mains enabled for reads until the Command Regis-
ter contents are altered. Once the internal write
state machine has started an erase or program op-
eration, the device will not recognize the Read Array
command, until the WSM has completed its opera-
tion. The Read Array command is functional when
IN-SYSTEM PROGRAMMING
The manufacturer- and device-codes can also be
read via the Command Register. Following a write of
90H to the Command Register, a read from address
location 00000H outputs the manufacturer code
(89H). A read from address 00001H outputs the de-
vice code (94H for the 28F001BX-T and 95H for the
28F001BX-B). It is not necessary to have high volt-
e
V
V
PPL
or V
.
PPH
PP
age applied to V to read the Intelligent Identifiers
PP
from the Command Register.
Intelligent Identifier Command for
In-System Programming
Write
The 28F001BX contains an Intelligent Identifier op-
eration to supplement traditional PROM-program-
ming methodology. The operation is initiated by writ-
ing 90H into the Command Register. Following the
command write, a read cycle from address 00000H
retrieves the manufacturer code of 89H. A read cy-
cle from address 00001H returns the device code of
94H (28F001BX-T) or 95H (28F001BX-B). To termi-
nate the operation, it is necessary to write another
valid command into the register. Like the Read Array
command, the Intelligent Identifier command is func-
Writes to the Command Register allow read of de-
vice data and Intelligent Identifiers. They also con-
trol inspection and clearing of the Status Register.
e
Additionally, when V
V
, the Command Reg-
PPH
PP
ister controls device erasure and programming. The
contents of the register serve as input to the internal
state machine.
The Command Register itself does not occupy an
addressable memory location. The register is a latch
used to store the command and address and data
information needed to execute the command. Erase
e
tional when V
V
PPL
or V
.
PPH
PP
8
28F001BX-T/28F001BX-B
Second Bus Cycle
Table 3. 28F001BX Command Definitions
Bus
First Bus Cycle
Command
Cycles Notes
Req’d
Operation Address Data Operation Address Data
Read Array/Reset
1
3
2
1
2
2
2
1
2, 3, 4
3
Write
Write
Write
Write
Write
Write
Write
X
X
FFH
90H
70H
50H
20H
B0H
40H
Intelligent Identifier
Read
Read
IA
X
IID
Read Status Register
Clear Status Register
Erase Setup/Erase Confirm
Erase Suspend/Erase Resume
Program Setup/Program
X
SRD
X
2
BA
X
Write
Write
Write
BA
X
D0H
D0H
PD
2, 3
PA
PA
NOTES:
1. Bus operations are defined in Table 2.
e
2. IA
BA
PA
Identifier Address: 00H for manufacturer code, 01H for device code.
Address within the block being erased.
Address of memory location to be programmed.
e
e
3. SRD
e
Data read from Status Register. See Table 4 for a description of the Status Register bits.
e
e
Ý
Data to be programmed at location PA. Data is latched on the rising edge of WE .
Data read from Intelligent Identifiers.
PD
IID
4. Following the Intelligent Identifier command, two read operations access manufacture and device codes.
5. Commands other than those shown above are reserved by Intel for future device implementations and should not be
used.
reset by the Clear Status Register command. These
bits indicate various failure conditions (see Table 4).
Read Status Register Command
By allowing system software to control the resetting
of these bits, several operations may be performed
(such as cumulatively programming several bytes or
erasing multiple blocks in sequence). The Status
Register may then be polled to determine if an error
occurred during that series. This adds flexibility to
the way the device may be used.
The 28F001BX contains a Status Register which
may be read to determine when a program or erase
operation is complete, and whether that operation
completed successfully. The Status Register may be
read at any time by writing the Read Status Register
command (70H) to the Command Register. After
writing this command, all subsequent read opera-
tions output data from the Status Register, until an-
other valid command is written to the Command
Register. The contents of the Status Register are
Additionally, the V Status bit (SR.3), when set to
PP
‘‘1’’, MUST be reset by system software before fur-
ther byte programs or block erases are attempted.
To clear the Status Register, the Clear Status Regis-
ter command (50H) is written to the Command Reg-
ister. The Clear Status Register command is func-
Ý
latched on the falling edge of OE or CE , which-
ever occurs last in the read cycle. OE or CE
Ý
Ý
Ý
must be toggled to V before further reads to up-
IH
date the Status Register latch. The Read Status
e
e
tional when V
V
PPL
or V
.
PPH
Register command functions when V
.
V
or
PPL
PP
PP
V
PPH
Clear Status Register Command
The Erase Status and Program Status bits are set to
‘‘1’’ by the Write State Machine and can only be
9
28F001BX-T/28F001BX-B
Table 4. 28F001BX Status Register Definitions
WSMS
7
ESS
6
ES
5
PS
4
VPPS
3
R
2
R
1
R
0
e
e
e
SR.7
WRITE STATE MACHINE STATUS
Ready
Busy
NOTES:
1
0
The Write State Machine Status Bit must first be checked
to determine program or erase completion, before the
Program or Erase Status bits are checked for success.
e
e
e
SR.6
ERASE SUSPEND STATUS
Erase Suspended
Erase In Progress/Completed
1
0
If the Program AND Erase Status bits are set to ‘‘1s’’ dur-
ing an erase attempt, an improper command sequence
was entered. Attempt the operation again.
e
e
e
SR.5
ERASE STATUS
Error in Block Erasure
Successful Block Erase
1
0
If V low status is detected, the Status Register must be
PP
cleared before another program or erase operation is at-
tempted.
e
e
e
SR.4
PROGRAM STATUS
Error in Byte Program
Successful Byte Program
1
0
The V Status bit, unlike an A/D converter, does not
PP
provide continuous indication of V level. The WSM in-
PP
terrogates the V level only after the program or erase
PP
command sequences have been entered and informs the
system if V has not been switched on. The V Status
PP PP
e
e
e
SR.3
V
PP
V
PP
V
PP
STATUS
Low Detect; Operation Abort
OK
1
0
bit is not guaranteed to report accurate feedback be-
tween V and V
.
PPH
PPL
e
SR.2–SR.0
MENTS
RESERVED FOR FUTURE ENHANCE-
These bits are reserved for future use and should be
masked out when polling the Status Register.
the V Status bit will be set to ‘‘1’’. Erase attempts
PP
while V
Erase Setup/Erase Confirm
Commands
k
k
and should not be attempted.
V
V
produce spurious results
PPL
PP
PPH
Erase is executed one block at a time, initiated by a
two-cycle command sequence. An Erase Setup
command (20H) is first written to the Command
Register, followed by the Erase Confirm command
(D0H). These commands require both appropriate
command data and an address within the block to
be erased. Block preconditioning, erase and verify
are all handled internally by the Write State Machine,
invisible to the system. After receiving the two-com-
mand erase sequence, the 28F001BX automatically
outputs Status Register data when read (see Figure
10; Block Erase Flowchart). The CPU can detect the
completion of the erase event by checking the WSM
Status bit of the Status Register (SR.7).
Erase Suspend/Erase Resume
Commands
The Erase Suspend Command allows erase se-
quence interruption in order to read data from anoth-
er block of memory. Once the erase sequence is
started, writing the Erase Suspend command (B0H)
to the Command Register requests that the WSM
suspend the erase sequence at a predetermined
point in the erase algorithm. The 28F001BX contin-
ues to output Status Register data when read, after
the Erase Suspend command is written to it. Polling
the WSM Status and Erase Suspend Status bits will
determine when the erase operation has been sus-
pended (both will be set to ‘‘1s’’).
When the Status Register indicates that erase is
complete, the Erase Status bit should be checked. If
erase error is detected, the Status Register should
be cleared. The Command Register remains in Read
Status Register Mode until further commands are is-
sued to it.
At this point, a Read Array command can be written
to the Command Register to read data from blocks
other than that which is suspended. The only oth-
er valid commands at this time are Read Status Reg-
ister (70H) and Erase Resume (D0H), at which time
the WSM will continue with the erase sequence. The
Erase Suspend Status and WSM Status bits of the
Status Register will be cleared. After the Erase Re-
sume command is written to it, the 28F001BX auto-
matically outputs Status Register data when read
(see Figure 11; Erase Suspend/Resume Flowchart).
This two-step sequence of set-up followed by execu-
tion ensures that memory contents are not acciden-
tally erased. Also, block erasure can only occur
e
age, memory contents are protected against era-
when V
V . In the absence of this high volt-
PPH
PP
e
sure. If block erase is attempted while V
10
V
,
PPL
PP
28F001BX-T/28F001BX-B
The 28F001BX-B and 28F001BX-T are capable of
100,000 program/erase cycles on each parameter
block, main block and boot block.
Program Setup/Program Commands
Programming is executed by a two-write sequence.
The program Setup command (40H) is written to the
Command Register, followed by a second write
specifying the address and data (latched on the ris-
ON-CHIP PROGRAMMING
ALGORITHM
Ý
ing edge of WE ) to be programmed. The WSM
then takes over, controlling the program and verify
algorithms internally. After the two-command pro-
gram sequence is written to it, the 28F001BX auto-
matically outputs Status Register data when read
(see Figure 9; Byte Program Flowchart). The CPU
can detect the completion of the program event by
analyzing the WSM Status bit of the Status Register.
Only the Read Status Register command is valid
while programming is active.
The 28F001BX integrates the Quick Pulse program-
ming algorithm of prior Intel Flash Memory devices
on-chip, using the Command Register, Status Regis-
ter and Write State Machine (WSM). On-chip inte-
gration dramatically simplifies system software and
provides processor-like interface timings to the
Command and Status Registers. WSM operation, in-
ternal program verify and V high voltage presence
PP
are monitored and reported via appropriate Status
Register bits. Figure 9 shows a system software
flowchart for device programming. The entire se-
When the Status Register indicates that program-
ming is complete, the Program Status bit should be
checked. If program error is detected, the Status
Register should be cleared. The internal WSM verify
only detects errors for ‘‘1s’’ that do not successfully
program to ‘‘0s’’. The Command Register remains in
Read Status Register mode until further commands
are issued to it. If byte program is attempted while
quence is performed with V
at V
abort occurs when RP transitions to V , or V
. Program
PP
PPH
Ý
. Although the WSM is halted, byte
IL
PP
drops to V
PPL
data is partially programmed at the location where
programming was aborted. Block erasure or a re-
peat of byte programming will initialize this data to a
known value.
e
Program attempts while V
V
PP
V
, the V Status bit will be set to ‘‘1’’.
PPL PP
k
k
V
duce spurious results and should not be attempted.
V
PP
pro-
PPH
PPL
ON-CHIP ERASE ALGORITHM
As above, the Quick Erase algorithm of prior Intel
Flash Memory devices is now implemented internal-
ly, including all preconditioning of block data. WSM
EXTENDED ERASE/PROGRAM
CYCLING
operation, erase success and V high voltage pres-
PP
EEPROM cycling failures have always concerned
users. The high electrical field required by thin oxide
EEPROMs for tunneling can literally tear apart the
oxide at defect regions. To combat this, some sup-
pliers have implemented redundancy schemes, re-
ducing cycling failures to insignificant levels. Howev-
er, redundancy requires that cell size be doubled; an
expensive solution.
ence are monitored and reported through the Status
Register. Additionally, if a command other than
Erase Confirm is written to the device after Erase
Setup has been written, both the Erase Status and
Program Status bits will be set to ‘‘1’’. When issuing
the Erase Setup and Erase Confirm commands, they
should be written to an address within the address
range of the block to be erased. Figure 10 shows a
system software flowchart for block erase.
Intel has designed extended cycling capability into
its ETOX flash memory technology. Resulting im-
provements in cycling reliability come without in-
creasing memory cell size or complexity. First, an
advanced tunnel oxide increases the charge carry-
ing ability ten-fold. Second, the oxide area per cell
subjected to the tunneling electrical field is one-
tenth that of common EEPROMs, minimizing the
probability of oxide defects in the region. Finally, the
peak electric field during erasure is approximately 2
Mv/cm lower than EEPROM. The lower electric field
greatly reduces oxide stress and the probability of
failure.
Erase typically takes 1–4 seconds per block. The
Erase Suspend/Erase Resume command sequence
allows interrupt of this erase operation to read data
from a block other than that in which erase is
being performed. A system software flowchart is
shown in Figure 11.
The entire sequence is performed with V at V
PP PPH
Abort occurs when RP transitions to V or V
.
Ý
, while erase is in progress. Block data is
IL
PP
falls to V
PPL
partially erased by this operation, and a repeat of
erase is required to obtain a fully erased block.
11
28F001BX-T/28F001BX-B
tion being attempted and indicating boot block lock.
k
produce spurious results and should not be attempt-
ed.
BOOT BLOCK PROGRAM AND
ERASE
k
Ý
Program/erase attempts while V
RP
V
HH
IH
The boot block is intended to contain secure code
which will minimally bring up a system and control
programming and erase of other blocks of the de-
vice, if needed. Therefore, additional ‘‘lockout’’ pro-
tection is provided to guarantee data integrity. Boot
block program and erase operations are enabled
In-System Operation
Ý
For on-board programming, the RP pin is the most
convenient means of altering the boot block. Before
Ý
Ý
,
through high voltage V
on either RP or OE
Ý
must transition to V . Hold RP at this high volt-
HH
issuing Program or Erase confirms commands, RP
Ý
and the normal program and erase command se-
quences are used. Reference the AC Waveforms for
Program/Erase.
HH
age throughout the program or erase interval (until
after Status Register confirm of successful comple-
tion). At this time, it can return to V or V
IH
.
IL
If boot block program or erase is attempted while
Ý
RP is at V , either the Program Status or Erase
Status bit will be set to ‘‘1’’, reflective of the opera-
IH
Bus
Operation
Command
Comments
e
Write
Program
Setup
Data
Address
Programmed
40H
e
Byte to be
Write
Program
Data to be programmed
e
Programmed
Address
Byte to be
Read
Status Register Data.
Ý
Ý
Toggle OE or CE to
update Status Register
Check SR.7
Standby
e
e
Busy
1
Ready, 0
Repeat for subsequent bytes.
Full status check can be done after each byte or after a
sequence of bytes.
Write FFH after the last byte programming operation to
reset the device to Read Array Mode.
Bus
Operation
Command
Comments
Standby
Check SR.3
e
1
V
Low Detect
PP
Standby
Check SR.4
e
1
Byte Program Error
SR.3 MUST be cleared, if set during a program attempt,
before further attempts are allowed by the Write State
Machine.
290406–7
SR.4 is only cleared by the Clear Status Register
Command, in cases where multiple bytes are
programmed before full status is checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.
Figure 9. 28F001BX Byte Programming Flowchart
12
28F001BX-T/28F001BX-B
Bus
Command
Comments
Operation
e
20H
Write
Write
Erase
Setup
Data
e
Address
Within Block to be erased
e
Address
Erase
Data
D0H
e
Within Block to be erased
Read
Status Register Data.
Ý
Ý
Toggle OE or CE to update Status
Register
Standby
Check SR.7
e
e
Busy
1
Ready, 0
Repeat for subsequent blocks.
Full status check can be done after each block or after a sequence of
blocks.
Write FFH after the last block erase operation to reset the device to
Read Array Mode.
Bus
Command
Comments
Operation
Standby
Check SR.3
e
1
V
Low Detect
PP
Standby
Standby
Check SR.4, 5
e
Both 1
Command Sequence Error
Check SR.5
e
1
Block Erase Error
SR.3 MUST be cleared, if set during an erase attempt, before further
attempts are allowed by the Write State Machine.
SR.5 is only cleared by the Clear Status Register Command, in cases
where multiple blocks are erased before full status is checked.
290406–8
If error is detected, clear the Status Register before attempting retry or
other error recovery.
Figure 10. 28F001BX Block Erase Flowchart
13
28F001BX-T/28F001BX-B
Bus
Command
Comments
Operation
e
Write
Write
Erase
Data
Data
B0H
70H
Suspend
e
Erase
Status Register
Standby/
Read
Read Status Register
Check SR.7
e
Toggle OE or CE to
e
Busy
1
Ready, 0
Ý
Ý
Update Status Register
Standby
Write
Check SR.6
e
1
Suspended
e
FFH
Read Array
Data
Read
Write
Read array data from
block other than that
being erased.
e
Erase Resume Data
D0H
290406–9
Figure 11. 28F001BX Erase Suspend/Resume Flowchart
date multiple memory connections. Three-line con-
trol provides for:
Programming Equipment
For PROM programming equipment that cannot
Ý
a) lowest possible memory power dissipation
Ý
bring RP to high voltage, OE provides an alter-
Ý
b) complete assurance that data bus contention will
not occur
nate boot block access mechanism. OE must tran-
sition to V a minimum of 480 ns before the initial
HH
program/erase setup command and held at V
at
HH
To efficiently use these control inputs, an address
Ý
least 480 ns after program or erase confirm com-
mands are issued to the device. After this interval,
Ý
OE can return to normal TTL levels.
Ý
decoder should enable CE , while OE should be
connected to all memory devices and the system’s
Ý
READ control line. This assures that only selected
memory devices have active outputs while deselect-
ed memory devices are in Standby Mode. RP
should be connected to the system POWERGOOD
signal to prevent unintended writes during system
power transitions. POWERGOOD should also toggle
during system reset.
DESIGN CONSIDERATIONS
Three-Line Output Control
Flash memories are often used in larger memory ar-
rays. Intel provides three control inputs to accommo-
Ý
14
28F001BX-T/28F001BX-B
After program or erase is complete, even after V
transitions down to V
PP
, the Command Register
Power Supply Decoupling
PPL
must be reset to read array mode via the Read Array
command if access to the memory array is desired.
Flash memory power switching characteristics re-
quire careful device coupling. System designers are
interested in 3 supply current issues; standby current
levels (I ), active current levels (I ) and transient
Ý
SB
CC
peaks producted by falling and rising edges of CE
.
Power Up/Down Protection
Transient current magnitudes depend on the device
outputs’ capacitive and inductive loading. Two-line
control and proper decoupling capacitor selection
will suppress transient voltage peaks. Each device
should have a 0.1 mF ceramic capacitor connected
The 28F001BX is designed to offer protection
against accidental erasure or programming during
power transitions. Upon power-up, the 28F001BX is
indifferent as to which power supply, V
or V
,
PP
CC
powers up first. Power supply sequencing is not re-
quired. Internal circuitry in the 28F001BX ensures
that the Command Register is reset to Read Array
mode on power up.
between its V and GND, and between its V and
PP
CC
GND. These high frequency, low inherent-induc-
tance capacitors should be placed as close as pos-
sible to the device. Additionally, for every 8 devices,
a 4.7 mF electrolytic capacitor should be placed at
the array’s power supply connection between V
CC
and GND. The bulk capacitor will overcome voltage
slumps caused by PC board trace inductances.
A system designer must guard against spurious
when V
writes for V
voltages above V
Ý
is
CC
LKO
PP
Ý
active. Since both WE and CE must be low for a
command write, driving either to V will inhibit
IH
writes. The Command Register architecture provides
an added level of protection since alteration of mem-
ory contents only occurs after successful completion
of the two-step command sequences.
V
Trace on Printed Circuit Boards
PP
Programming flash memories, while they reside in
the target system, requires that the printed circuit
board designer pay attention to the V power sup-
ply trace. The V pin supplies the memory cell cur-
PP
rent for programming. Use similar trace widths and
Ý
Finally, the device is disabled, until RP is brought
to V , regardless of the state of its control inputs.
PP
IH
This provides an additional level of protection.
layout considerations given to the V
power bus.
Adequate V supply traces and decoupling will de-
CC
PP
crease V voltage spikes and overshoots.
PP
28F001BX Power Dissipation
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash nonvolatility increases us-
able battery life because the 28F001BX does not
consume any power to retain code or data when the
system is off.
Ý
, V , RP Transitions and the
Command/Status Registers
V
CC PP
Programming and erase completion are not guaran-
. If the V Status bit of
teed if V drops below V
PP
PPH
PP
the Status Register (SR.3) is set to ‘‘1’’, a Clear
Status Register command MUST be issued before
further program/erase attempts are allowed by the
WSM. Otherwise, the Program (SR.4) or Erase
(SR.5) Status bits of the Status Register will be set
In addition, the 28F001BX’s Deep-Powerdown mode
ensures extremely low power dissipation even when
system power is applied. For example, laptop and
other PC applications, after copying BIOS to DRAM,
Ý
to ‘‘1’’ if error is detected. RP transitions to V
IL
Ý
can lower RP to V , producing negligible power
consumption. If access to the boot code is again
IL
during program and erase also abort the operations.
Data is partially altered in either case, and the com-
mand sequence must be repeated after normal op-
Ý
needed, as in case of a system RESET , the part
can again be accessed, following the t wakeup
Ý
eration is restored. Device poweroff, or RP tran-
sitions to V , clear the Status Register to initial val-
PHAV
cycle required after RP is first raised back to V
Ý
The first address presented to the device while in
.
IH
IL
ue 80H.
Ý
, after RP tran-
powerdown requires time t
PHAV
sitions high, before outputs are valid. Further ac-
cesses follow normal timing. See AC Characteris-
ticsÐRead-Only Operations and Figure 12 for more
information.
The Command Register latches commands as is-
sued by system software and is not altered by V
PP
Ý
or CE transitions or WSM actions. Its state upon
powerup, after exit from Deep-Powerdown or after
V transitions below V
CC
Mode.
, is FFH, or Read Array
LKO
15
28F001BX-T/28F001BX-B
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This is a production data sheet. The specifi-
cations are subject to change without notice.
Operating Temperature
During Read ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0 C to 70 C
*WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and ex-
tended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.
(1)
(1)
§
§
During Erase/Program ÀÀÀÀÀÀÀÀÀÀÀ0 C to 70 C
§
§
Operating Temperature
During Read ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 40 C to 85 C
(2)
(2)
b
a
§
§
b
a
During Erase/Program ÀÀÀÀÀÀ 40 C to 85 C
§
Temperature under Bias ÀÀÀÀÀÀÀÀÀ 10 C to 80 C
§
(1)
(2)
b
§
Temperature under Bias ÀÀÀÀÀÀÀ 20 C to 90 C
§
b
a
§
§
b
Storage TemperatureÀÀÀÀÀÀÀÀÀÀÀÀÀ 65 C to 125 C
§
§
Voltage on Any Pin
Ý
Ý
(except A , RP , OE , V
with Respect to GND ÀÀÀÀÀÀÀÀÀÀ 2.0V to 7.0V
and V
)
PP
9
CC
(3)
b
Ý
Ý
with Respect to GND ÀÀÀÀÀÀÀ 2.0V to 13.5V
Voltage on A , RP , and OE
9
(3, 4)
b
V
PP
Program Voltage
with Respect to GND
During Erase/Program ÀÀÀÀÀÀ 2.0V to 14.0V
Supply Voltage
(3, 4)
(3)
b
V
CC
b
with Respect to GND ÀÀÀÀÀÀÀÀÀÀ 2.0V to 7.0V
(5)
Output Short Circuit CurrentÀÀÀÀÀÀÀÀÀÀÀÀÀ100 mA
OPERATING CONDITIONS
Symbol
Parameter
Operating Temperature
Operating Temperature
Supply Voltage
Min
Max
Unit
(1)
(2)
T
A
0
70
85
C
§
b
40
4.50
T
A
C
§
V
CC
5.50
V
NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Operating temperature is for extended temperature product defined by this specification.
b
b
3. Minimum DC voltage is 0.5V on input/output pins. During transitions, this level may undershoot to 2.0V for periods
a
k
for periods 20 ns.
a
20 ns. Maximum DC voltage on input/output pins is V
k
4. Maximum DC voltage on A or V may overshoot to 14.0V for periods 20 ns.
0.5V which, during transitions, may overshoot to V
2.0V
CC
CC
k
5. Output shorted for no more than one second. No more than one output shorted at a time.
a
9
PP
DC CHARACTERISTICS
e
e a
g
5.0V 10%, T
V
0 C to 70 C
§
§
Parameter
CC
A
Symbol
Notes Min Typ Max Unit
Test Conditions
e
g
I
I
I
Input Load Current
1
1.0 mA
V
V
V
Max
or GND
IL
CC
CC
e
V
IN
CC
e
g
Output Leakage Current
1
10 mA
V
V
V
CC
Max
LO
CCS
CC
e
V
or GND
OUT
CC
e
V
Standby Current
1.2
30
2.0
mA
V
CC
CE
V
CC
Max
e
CC
CC
e
Ý
Ý
RP
V
V
IH
e
100
mA
V
CC
CE
V
Max
CC
e
Ý
e
Ý
g
0.2V
RP
CC
e
Ý
g
GND 0.2V
I
V
Deep Power-Down Current
1
0.05 1.0
mA RP
CCD
16
28F001BX-T/28F001BX-B
DC CHARACTERISTICS (Continued)
e
e a
g
5.0V 10%, T
V
CC
0 C to 70 C
§
§
A
Symbol
Parameter
Read Current
Notes Min Typ
Max
Unit
Test Conditions
e
8 MHz, I
e
V
Ý
I
V
1
13
30
mA V
f
V
Max, CE
CCR
CC
CC
e
CC
IL
e
0 mA
OUT
I
I
I
V
V
V
Programming Current
Erase Current
1
1
5
6
5
20
20
10
mA Programming in Progress
mA Erase in Progress
CCP
CC
CC
CC
CCE
Erase Suspend Current
1, 2
mA Erase Suspended
e
CCES
Ý
CE
V
IH
s
g
g
10
I
V
Standby Current
1
1
mA V
V
V
PPS
PP
PP
PP
CC
CC
l
90
0.80
6
200
1.0
30
mA V
e
g
GND 0.2V
Ý
I
I
V
V
Deep Power-Down Current
Programming Current
1
1
mA RP
PPD
PPP
PP
PP
e
Programming in Progress
mA V
V
PPH
PP
e
V
PPH
I
I
I
V
V
A
Erase Current
1
1
1
6
30
mA V
PPE
PPES
ID
PP
PP
Erase in Progress
e
V
PPH
Erase Suspend Current
90
90
300
mA V
PP
PP
Erase Suspended
e
V
ID
Intelligent Identifier Current
500
0.8
a
mA A
9
9
b
V
V
V
Input Low Voltage
Input High Voltage
Output Low Voltage
0.5
V
V
IL
2.0
V
0.5
IH
OL
CC
e
e
0.45
V
V
V
5.8 mA
Min
CC
CC
I
OL
e
e
V
Output High Voltage
2.4
V
V
V Min
CC
2.5 mA
OH
CC
I
OH
V
V
V
V
V
A
V
V
V
Intelligent Identifier Voltage
11.5
0.0
13.0
6.5
V
V
V
V
V
ID
9
during Normal Operations
during Prog/Erase Operations
Erase/Write Lock Voltage
3
PPL
PPH
LKO
HH
PP
PP
CC
11.4 12.0
2.5
12.6
Ý
Ý
RP , OE Unlock Voltage
11.4
12.6
Boot Block Prog/Erase
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at V
are valid for all product versions (packages and speeds).
e
e
e
12.0V, T 25 C. These currents
A
5.0V, V
§
CC
PP
2. I
CCES
sum of I
is specified with the device deselected. If the 28F001BX is read while in Erase Suspend mode, current draw is the
.
CCR
and I
CCES
3. Erase/Programs are inhibited when V
e
V
PPL
and not guaranteed in the range between V
and V
.
PPL
PP
PPH
17
28F001BX-T/28F001BX-B
DC CHARACTERISTICS
e
e b a
g
5.0V 10%, T
V
CC
40 C to 85 C
§
§
A
Symbol
Parameter
Input Load Current
Notes Min
Typ Max Unit
Test Conditions
e
g
I
I
I
1
1.0 mA V
V
CC
Max
IL
CC
IN
e
V
V
or GND
CC
e
g
Output Leakage Current
1
10
mA V
V
CC
Max
LO
CCS
CC
e
V
OUT
V
CC
or GND
e
e
V
CC
Standby Current
1.2
30
2.0
mA V
CC
CE
V
Max
e
CC
Ý
Ý
RP
V
V
IH
e
e
150
mA V
V
Max
CC
e
Ý
CC
Ý
g
0.2V
CE
RP
CC
e
Ý
g
GND 0.2V
I
I
V
V
Deep Power-Down Current
Read Current
1
1
0.05
13
2.0
35
mA RP
CCD
CCR
CC
e
8 MHz, I
e
Ý
mA V
f
V
Max, CE
V
IL
CC
CC
e
CC
e
0 mA
OUT
I
I
I
V
CC
V
CC
V
CC
Programming Current
Erase Current
1
1
5
6
5
20
20
10
mA Programming in Progress
mA Erase in Progress
CCP
CCE
Erase Suspend Current
1, 2
mA Erase Suspended
e
CCES
Ý
CE
V
IH
s
g
g
15
I
V
Standby Current
1
1
mA V
V
V
PPS
PP
PP
PP
CC
CC
l
90
0.80
6
400
1.0
30
mA V
e
g
GND 0.2V
Ý
I
I
V
V
Deep Power-Down Current
Programming Current
1
1
mA RP
PPD
PPP
PP
e
Programming in Progress
mA V
V
PPH
PP
PP
e
V
PPH
I
I
I
V
V
A
Erase Current
1
1
1
6
30
mA V
PPE
PPES
ID
PP
PP
PP
Erase in Progress
e
V
PPH
Erase Suspend Current
90
90
400
mA V
PP
Erase Suspended
e
V
ID
Intelligent Identifier Current
500
0.8
mA A
9
9
b
V
V
V
Input Low Voltage
Input High Voltage
Output Low Voltage
0.5
V
V
IL
a
CC
2.0
V
0.5
IH
OL
e
e
0.45
V
V
V
V
V
Min
CC
CC
5.8 mA
I
OL
e
e
V
V
Output High Voltage (TTL)
2.4
V
V
Min
OH1
OH2
CC
CC
2.5 mA
I
OH
e
Output High Voltage (CMOS)
0.85 V
V
V
Min
2.5 mA
CC
CC
CC
e b
I
OH
b
e
V
V
CC
0.4
V
Min
100 mA
CC
CC
e b
I
OH
V
V
V
V
V
A
V
V
V
Intelligent Identifier Voltage
11.5
0.0
13.0
6.5
V
V
V
V
V
ID
9
during Normal Operations
during Prog/Erase Operations
Erase/Write Lock Voltage
3
PPL
PPH
LKO
HH
PP
PP
CC
11.4 12.0 12.6
2.5
Ý
Ý
RP , OE Unlock Voltage
11.4
12.6
Boot Block Prog/Erase
18
28F001BX-T/28F001BX-B
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at V
are valid for all product versions (packages and speeds).
e
e
e
25 C. These currents
5.0V, V
12.0V, T
§
CC
PP
A
2. I
is specified with the device deselected. If the 28F001BX is read while in Erase Suspend mode, current draw is the
CCES
sum of I
3. Erase/Programs are inhibited when V
and I
.
CCES
CCR
e
V
PPL
and not guaranteed in the range between V
and V
.
PPL
PP
PPH
(1)
e
e
CAPACITANCE
T
A
25 C, f
§
1 MHz
Symbol
Parameter
Max
8
Unit
pF
Conditions
e
C
C
Input Capacitance
Output Capacitance
V
V
0V
IN
IN
e
0V
12
pF
OUT
OUT
NOTE:
1. Sampled, not 100% tested.
AC INPUT/OUTPUT REFERENCE WAVEFORM
290406–10
) for a Logic ‘‘0’’. Input timing begins at
TTL
A.C. test inputs are driven at V
) and V (0.8 V
TTL IL
(2.4 V
) for a Logic ‘‘1’’ and V (0.45 V
TTL OL
OH
k
V
(2.0 V
). Output timing ends at V and V . Input rise and fall times (10% to 90%)
IH
10 ns.
IH
TTL
IL
STANDARD TEST CONFIGURATION
AC TESTING LOAD CIRCUIT
HIGH SPEED TEST CONFIGURATION
AC TESTING LOAD CIRCUIT
290406–11
290406–23
e
C
C
R
100 pF
Includes Jig Capacitance
3.3 kX
L
L
e
C
C
R
30 pF
Includes Jig Capacitance
3.3 kX
L
L
e
L
e
L
19
28F001BX-T/28F001BX-B
(1)
AC CHARACTERISTICSÐRead-Only Operations
28F001BX-70
28F001BX-90
e
5%
e
e
CC
g
V
5V
V
5V
10%
100 pF
V
5V
10%
100 pF
CC
g
CC
g
Symbol
Parameter
Notes
Units
30 pF
Min
Max
Min
Max
Min
Max
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
RC
70
75
90
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
AVQV ACC
Address to Output Delay
70
70
75
75
90
90
Ý
CE to Output Delay
t
2
ELQV
CE
Ý
RP to Output Delay
t
PHQV PWH
600
27
600
30
600
35
Ý
OE to Output Delay
t
GLQV OE
2
3
3
3
3
3
Ý
CE to Output in Low Z
t
0
0
0
0
0
0
0
0
0
ELQX
EHQZ
LZ
Ý
CE to Output in High Z
t
55
30
55
30
35
30
HZ
Ý
OE to Output in Low Z
t
GLQX OLZ
Ý
OE to Output in High Z
t
GHQZ DF
t
Output Hold from
Ý
OH
Ý
Address CE , or OE
Change, Whichever
Occurs First
NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
Ý
Ý
after the falling edge of CE without impact on t
2. OE may be delayed up to t –t
.
CE
CE OE
3. Sampled, but not 100% tested.
4. See High Speed Test Configuration.
5. See Standard Test Configuration.
20
28F001BX-T/28F001BX-B
(1)
AC CHARACTERISTICSÐRead-Only Operations
E28F001BX-150
TE28F001BX-150
N28F001BX-150
E28F001BX-120
N28F001BX-120
P28F001BX-120
(2)
g
10%
Versions
V
CC
Unit
TN28F001BX-150
P28F001BX-150
Symbol
Parameter
Read Cycle Time
Address to Output Delay
Notes
Min
Max
Min
Max
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
120
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
AVQV
ELQV
PHQV
GLQV
ELQX
EHQZ
GLQX
GHQZ
RC
120
120
600
50
150
150
600
55
ACC
CE
Ý
CE to Output Delay
3
Ý
RP High to Output Delay
PWH
OE
Ý
OE to Output Delay
3
4
4
4
4
4
Ý
CE to Output Low Z
0
0
0
0
0
0
LZ
Ý
CE High to Output High Z
55
30
55
30
HZ
Ý
OE to Output Low Z
OLZ
DF
Ý
OE High to Output High Z
Output Hold from
Ý
OH
Ý
Addresses, CE or OE
Change, Whichever is First
NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
e
e
e
e
PDIP, T Extended Temperature. Refer to
2. Model Number Prefixes: E
standard test configuration.
TSOP (Standard Pinout), N
PLCC, P
Ý
3. OE may be delayed up to t –t
4. Sampled, not 100% tested.
Ý
after the falling edge of CE without impact on t
.
CE
CE OE
21
28F001BX-T/28F001BX-B
Figure 12. AC Waveform for Read Operations
22
28F001BX-T/28F001BX-B
(1, 9)
AC CHARACTERISTICSÐWrite/Erase/Program Operations
28F001BX-70
28F001BX-90
e
5%
30 pF
e
10%
100 pF
e
10%
100 pF
V
g
5V
(10)
V
g
5V
(11)
V
CC
g
5V
(11)
CC
CC
Symbol
Parameter
Notes
Units
Min Max Min Max
Min
Max
t
t
t
t
Write Cycle Time
70
75
90
ns
ns
AVAV
PHWL
WC
PS
Ý
RP High Recovery to WE
Going Low
Ý
2
480
480
480
Ý
Ý
CE Setup to WE Going Low
t
t
t
t
t
10
35
10
40
10
40
ns
ns
ns
ELWL
CS
Ý
WE Pulse Width
WLWH
WP
Ý
RP
High
Ý
Setup to WE Going
t
PHHWH PHS
V
2
100
100
100
HH
Ý
Setup to WE Going High
t
t
t
t
V
PP
2
3
100
35
100
40
100
40
ns
ns
VPWH
AVWH
VPS
AS
Ý
Address Setup to WE Going
High
Ý
Data Setup to WE Going High
t
t
t
t
t
t
t
t
t
t
t
4
35
10
10
10
35
40
10
10
10
35
15
40
10
10
10
35
15
ns
ns
ns
ns
ns
ms
DVWH
WHDX
WHAX
WHEH
WHWL
WHQV1
DS
Ý
Data Hold from WE High
DH
Ý
Address Hold from WE High
AH
Ý
Ý
CE Hold from WE High
CH
Ý
WE Pulse Width High
WPH
Duration of Programming
Operation
5, 6, 7 15
5, 6, 7 1.3
5, 6, 7 1.3
5, 6, 7 3.0
0
t
t
t
Duration of Erase Operation
(Boot)
1.3
1.3
3.0
1.3
1.3
3.0
sec
sec
sec
WHQV2
WHQV3
WHQV4
Duration of Erase Operation
(Parameter)
Duration of Erase Operation
(Main)
t
t
t
t
Write Recovery before Read
0
0
0
0
0
0
ms
ns
ns
ns
WHGL
QVVL
QVPH
PHBR
t
t
V
Hold from Valid SRD
PP
2, 6
2, 7
2
0
0
VPH
PHH
Ý
RP
V
Hold from Valid SRD
HH
Boot-Block Relock Delay
100
100
100
NOTES:
1. Read timing characteristics during erase and program operations are the same as during read-only operations. Refer to
AC Characteristics for Read-Only Operations.
2. Sampled, not 100% tested.
3. Refer to Table 3 for valid A for byte programming or block erasure.
IN
4. Refer to Table 3 for valid D for byte programming or block erasure.
IN
5. The on-chip Write State Machine incorporates all program and erase system functions and overhead of standard Intel
Flash Memory, including byte program and verify (programming) and block precondition, precondition verify, erase and erase
verify (erasing).
e
6. Program and erase durations are measured to completion (SR.7
1). V should be held at V
PP
until determination of
PPH
e
7. For boot block programming and erasure, RP should be held at V
program/erase success (SR.3/4/5
0).
Ý
until determination of program/erase success
HH
e
8. Alternate boot block access method.
(SR.3/4/5
0).
9. Erase/Program Cycles on extended temperature products is 10,000 cycles.
10. See high speed test configuration.
11. See standard test configuration.
23
28F001BX-T/28F001BX-B
(1, 9)
AC CHARACTERISTICSÐWrite/Erase/Program Operations
(10)
10%
g
Versions
V
28F001BX-120 28F001BX-150
CC
Unit
Symbol
Parameter
Write Cycle Time
Notes Min
Max
Min
150
480
10
50
100
100
50
50
10
10
10
50
15
1.3
1.3
3.0
0
Max
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
120
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
sec
sec
sec
ms
ns
ns
ns
AVAV
PHWL
ELWL
WLWH
WC
PS
Ý
Ý
RP High Recovery to WE Going Low
2
480
10
50
100
100
50
50
10
10
10
50
15
1.3
1.3
3.0
0
Ý
Ý
CE Setup to WE Going Low
CS
WP
Ý
WE Pulse Width
Ý
Ý
Setup to WE Going High
t
PHHWH PHS
RP
V
HH
2
2
3
4
Ý
V Setup to WE Going High
PP
t
t
t
t
t
t
t
VPWH
AVWH
DVWH
WHDX
WHAX
WHEH
WHWL
WHQV1
WHQV2
WHQV3
WHQV4
WHGL
QVVL
VPS
AS
Ý
Address Setup to WE Going High
Ý
Data Setup to WE Going High
DS
Ý
Data Hold from WE High
DH
Ý
Address Hold from WE High
AH
Ý
Ý
CE Hold from WE High
CH
Ý
WE Pulse Width High
WPH
Duration of Programming Operation
Duration of Erase Operation (Boot)
5, 6, 7
5, 6, 7
Duration of Erase Operation (Parameter) 5, 6, 7
Duration of Erase Operation (Main)
Write Recovery before Read
5, 6, 7
t
t
V
PP
Hold from Valid SRD
2, 6
2, 7
2
0
0
VPH
PHH
Ý
RP
V
HH
Hold from Valid SRD
0
0
QVPH
Boot-Block Relock Delay
100
100
PHBR
PROM Programmer Specifications
g
Versions
V
10%
28F001BX-120 28F001BX-150
CC
Unit
Symbol
Parameter
Notes Min
Max
Min
480
480
Max
Ý
Ý
Ý
Setup to WE Going Low
t
t
OE
OE
V
V
2, 8
2, 8
480
480
ns
ns
GHHWL
WHGH
HH
HH
Ý
Hold from WE High
NOTES:
1. Read timing characteristics during erase and program operations are the same as during read-only operations. Refer to
AC Characteristics for Read-Only Operations.
2. Sampled, not 100% tested.
3. Refer to Table 3 for valid A for byte programming or block erasure.
IN
4. Refer to Table 3 for valid D for byte programming or block erasure.
IN
5. The on-chip Write State Machine incorporates all program and erase system functions and overhead of standard Intel
Flash Memory, including byte program and verify (programming) and block precondition, precondition verify, erase and erase
verify (erasing).
e
6. Program and erase durations are measured to completion (SR.7
1). V should be held at V
PP
until determination of
PPH
e
7. For boot block programming and erasure, RP should be held at V
program/erase success (SR.3/4/5
0).
Ý
until determination of program/erase success
HH
e
8. Alternate boot block access method.
(SR.3/4/5
0).
9. Erase/Program Cycles on extended temperature products is 10,000 cycles.
10. See standard test configuration.
24
28F001BX-T/28F001BX-B
ERASE AND PROGRAMMING PERFORMANCE
28F001BX-120
(1)
28F001BX-150
Parameter
Notes
Unit
(1)
Min
Typ
Max
Min
Typ
2.10
Max
14.9
0.52
14.6
0.26
20.9
7.34
65
Boot Block Erase Time
Boot Block Program Time
Parameter Block Erase Time
Parameter Block Program Time
Main Block Erase Time
Main Block Program Time
Chip Erase Time
2
2
2
2
2
2
2
2
2.10
14.9
0.52
14.6
0.26
20.9
7.34
65
Sec
Sec
Sec
Sec
Sec
Sec
Sec
Sec
0.15
2.10
0.07
3.80
2.10
10.10
2.39
0.15
2.10
0.07
3.80
2.10
10.10
2.39
Chip Program Time
8.38
8.38
NOTES:
1. 25 C, 12.0 V
.
§
PP
2. Excludes System-Level Overhead.
25
28F001BX-T/28F001BX-B
290406–20
290406–19
Figure 14. 28F001BX Typical
Programming Time at 12V
Figure 13. 28F001BX Typical
Programming Capability
290406–21
290406–22
Figure 15. 28F001BX Typical Erase Capability
26
Figure 16. 28F001BX Typical Erase Time at 12V
28F001BX-T/28F001BX-B
Figure 17. AC Waveform for Write Operations
27
28F001BX-T/28F001BX-B
290406–15
Ý
Figure 18. Alternate Boot Block Access Method Using OE
28
28F001BX-T/28F001BX-B
(1)
Ý
AC CHARACTERISTICS FOR CE -CONTROLLED WRITES
28F001BX-70
28F001BX-90
e
(8)
5%
e
10%
100 pF
e
5V
CC
V
5V
V
5V
(9)
V
CC
CC
(9)
Symbol
Parameter
Notes
g
g
g
Units
10%
100 pF
30 pF
Min Max Min Max
Min
90
Max
t
t
t
t
Write Cycle Time
70
75
ns
ns
AVAV
PHEL
WC
PS
Ý
RP High Recovery to CE
Going Low
Ý
2
2
480
480
480
Ý
Ý
WE Setup to CE Going Low
t
t
t
t
t
0
0
0
ns
ns
ns
WLEL
ELEH
WS
CP
Ý
CE Pulse Width
50
55
55
Ý
RP
High
Ý
Setup to CE Going
t
PHHEH PHS
V
HH
100
100
100
Ý
Setup to CE Going High
t
t
t
t
V
PP
2
3
100
35
100
40
100
40
ns
ns
VPEH
AVEH
VPS
AS
Ý
Address Setup to CE Going
High
Ý
Data Setup to CE Going High
t
t
t
t
t
t
t
t
t
t
t
4
35
10
10
0
40
10
10
0
40
10
10
0
ns
ns
ns
ns
ns
ms
DVEH
EHDX
EHAX
EHWH
EHEL
DS
Ý
Data Hold from CE High
DH
AH
Ý
Address Hold from CE High
Ý
Ý
WE Hold from CE High
WH
EPH
Ý
CE Pulse Width High
20
15
20
15
20
15
Duration of Programming
Operation
5, 6
5, 6
5, 6
5, 6
EHQV1
t
t
t
Duration of Erase Operation
(Boot)
1.3
1.3
3.0
1.3
1.3
3.0
1.3
1.3
3.0
sec
sec
sec
EHQV2
EHQV3
EHQV4
Duration of Erase Operation
(Parameter)
Duration of Erase Operation
(Main)
t
t
t
t
Write Recovery before Read
0
0
0
0
0
0
0
0
0
ms
ns
ns
ns
EHGL
QVVL
QVPH
PHBR
t
t
V
PP
Hold from Valid SRD
2, 5
2, 6
2
VPH
PHH
Ý
RP
V
HH
Hold from Valid SRD
Boot-Block Relock Delay
100
100
100
NOTES:
1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of CE and WE . In systems where
Ý
Ý
CE defines the write pulse width (within a longer WE timing waveform), all set-up, hold and inactive WE times should
Ý
be measured relative to the CE waveform.
Ý
Ý
Ý
2. Sampled, not 100% tested.
3. Refer to Table 3 for valid A for byte programming or block erasure.
IN
4. Refer to Table 3 for valid D for byte programming or block erasure.
IN
e
5. Program and erase durations are measured to completion (SR.7
1). V should be held at V
PP
until determination of
PPH
e
6. For boot block programming and erasure, RP should be held at V
program/erase success (SR.3/4/5
0).
Ý
until determination of program/erase success
HH
e
(SR.3/4/5
0).
7. Alternate boot block access method.
8. See high speed test configuration.
9. See standard text configuration.
29
28F001BX-T/28F001BX-B
(1)
Ý
AC CHARACTERISTICS FOR CE -CONTROLLED WRITES
g
Versions
V
10%
28F001BX-120 28F001BX-150
CC
Unit
Symbol
Parameter
Write Cycle Time
Notes
Min
120
480
0
Max
Min
150
480
0
Max
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
sec
sec
sec
ms
ns
ns
ns
AVAV
PHEL
WC
Ý
Ý
RP High Recovery to CE Going Low
2
PS
Ý
Ý
WE Setup to CE Going Low
WLEL
ELEH
WS
CP
Ý
CE Pulse Width
70
100
100
50
50
10
15
0
70
100
100
50
50
10
15
0
Ý
Ý
V Setup to CE Going High
RP
2
2
3
4
PHHEH
VPEH
AVEH
DVEH
EHDX
EHAX
EHWH
EHEL
PHS
VPS
AS
HH
Ý
Setup to CE Going High
V
PP
Ý
Address Setup to CE Going High
Ý
Data Setup to CE Going High
DS
Ý
Data Hold from CE High
DH
Ý
Address Hold from CE High
AH
Ý
Ý
WE Hold from CE High
WH
EPH
Ý
CE Pulse Width High
25
15
1.3
1.3
3.0
0
25
15
1.3
1.3
3.0
0
Duration of Programming Operation
Duration of Erase Operation (Boot)
Duration of Erase Operation (Parameter)
Duration of Erase Operation (Main)
Write Recovery before Read
5, 6
5, 6
5, 6
5, 6
EHQV1
EHQV2
EHQV3
EHQV4
EHGL
QVVL
QVPH
PHBR
t
t
V
PP
Hold from Valid SRD
2, 5
2, 6
2
0
0
VPH
Ý
RP
V
HH
Hold from Valid SRD
0
0
PHH
Boot-Block Relock Delay
100
100
PROM Programmer Specifications
g
Versions
V
10%
Notes
28F001BX-120
28F001BX-150
CC
Unit
Symbol
Parameter
Min
480
480
Max
Min
480
480
Max
Ý
Ý
Ý
Setup to CE Going Low
t
t
OE
OE
V
V
2, 7
2, 7
ns
ns
GHHEL
EHGH
HH
HH
Ý
Hold from CE High
NOTES:
1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of CE and WE . In systems where
Ý
Ý
CE defines the write pulse width (within a longer WE timing waveform), all set-up, hold and inactive WE times should
Ý
be measured relative to the CE waveform.
Ý
Ý
Ý
2. Sampled, not 100% tested.
3. Refer to Table 3 for valid A for byte programming or block erasure.
IN
4. Refer to Table 3 for valid D for byte programming or block erasure.
IN
e
5. Program and erase durations are measured to completion (SR.7
1). V should be held at V
PP
until determination of
PPH
e
6. For boot block programming and erasure, RP should be held at V
program/erase success (SR.3/4/5
0).
Ý
until determination of program/erase success
HH
e
7. Alternate boot block access method.
(SR.3/4/5
0).
30
28F001BX-T/28F001BX-B
Figure 19. Alternate AC Waveform for Write Operations
31
28F001BX-T/28F001BX-B
ORDERING INFORMATION
290406–18
VALID COMBINATIONS:
32-Lead TSOP
32-Lead PLCC
N28F001BX-T70
N28F001BX-T90
N28F001BX-T120
N28F001BX-T150
32-Pin PDIP
Commercial
E28F001BX-T70
E28F001BX-T90
E28F001BX-T120
E28F001BX-T150
P28F001BX-T70
P28F001BX-T90
P28F001BX-T120
P28F001BX-T150
E28F001BX-B70
E28F001BX-B90
E28F001BX-B120
E28F001BX-B150
N28F001BX-B70
N28F001BX-B90
N28F001BX-B120
N28F001BX-B150
P28F001BX-B70
P28F001BX-B90
P28F001BX-B120
P28F001BX-B150
Extended
TE28F001BX-T90
TE28F001BX-T150
TN28F001BX-T90
TN28F001BX-T150
TP28F001BX-T90
TP28F001BX-B90
TE28F001BX-B90
TE28F001BX-B150
TN28F001BX-B90
TN28F001BX-B150
ADDITIONAL INFORMATION
References
Order Number
Document
292046
292077
292161
292178
294005
AP-316 ‘‘Using Flash Memory for In-System Reprogrammable Nonvolatile Storage’’
AP-341 ‘‘Designing an Updateable BIOS Using Flash Memory’’
AP-608 ‘‘Implementing a Plug and Play BIOS Using Intel’s Boot Block Flash Memory’’
AP-623 ‘‘Multi-Site Layout Planning Using Intel’s Boot Block Flash Memory’’
ER-20
‘‘ETOX II Flash Memory Technology’’
32
28F001BX-T/28F001BX-B
Revision History
Number
Description
-004
Removed Preliminary classification.
Latched address A in Figure 5.
16
Updated Boot Block Program and Erase section: ‘‘If boot block program or erase is attempted
Ý
while RP is at V , either the Program Status or Erase Status bit will be set to ‘‘1’’,
IH
reflective of the operation being attempted and indicating boot block lock.’’
Updated Figure 11, 28F001BX Erase Suspend/Resume Flowchart
Added DC Characteristics typical current values
Combined V Standby current and V Read current into one V Standby current spec with
PP PP PP
two test conditions (DC Characteristics table)
Added maximum program/erase times to Erase and Programming Performance table.
Added Figures 13–16
Added Extended Temperature proliferations
Ý
PWD changed to RP for JEDEC standardization compatibility
-005
Ý
Ý
Revised symbols, i.e.; CE, OE, etc. to CE , OE , etc.
-006
-007
Added specifications for -90 and -70 product versions.
Added V
CMOS Specification.
OH
Added reference to 28F001BN.
33
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