M82380 [INTEL]
HIGH PERFORMANCE 32-BIT DMA CONTROLLER WITH INTEGRATED SYSTEM SUPPORT PERIPHERALS; 具有集成系统支持外设高性能32位DMA控制器
| 型号： | M82380 |
| 厂家： | 
INTEL |
| 描述： | HIGH PERFORMANCE 32-BIT DMA CONTROLLER WITH INTEGRATED SYSTEM SUPPORT PERIPHERALS |
| 文件： | 总134页 (文件大小：1626K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M82380
HIGH PERFORMANCE 32-BIT DMA CONTROLLER WITH
INTEGRATED SYSTEM SUPPORT PERIPHERALS
Y
Y
High Performance 32-Bit DMA
Controller
Ð 40 Mbytes/sec Maximum Data
Transfer Rate at 20 MHz
Ð 8 Independently Programmable
Channels
i386TM Processor Shutdown Detect and
Reset Control
Ð Software/Hardware Reset
Y
Y
High Speed CHMOS III Technology
132-Pin PGA Package and 164-Pin Quad
Flat Pack
Y
20-Source Interrupt Controller
Ð Individually Programmable Interrupt
Vectors
Ð 15 External, 5 Internal Interrupts
Ð M8259A Superset
Ý
(See Packaging Specification Order
231369)
Optimized for use with the i386TM
Microprocessor
Ð Resides on Local Bus for Maximum
Bus Bandwidth
Y
Y
Y
Y
Y
Four 16-Bit Programmable Interval
Timers
Ð M82C54 Compatible
Available in Three Product Grades:
b
a
Ð MIL-STD-883, 55 C to 125 C (T )
Ð Military Temperature Only,
§
§
C
Programmable Wait State Generator
Ð 0 to 15 Wait States Pipelined
Ð 1 to 16 Wait States Non-Pipelined
b
a
55 C to 125 C (T )
Ð Extended Temperature,
§
§
C
b
a
40 C to 110 C (T )
§
§
C
DRAM Refresh Controller
The M82380 is a multi-function support peripheral that integrates system functions necessary in an i386
processor environment. It has eight channels of high performance 32-bit DMA with the most efficient transfer
rates possible on the i386 microprocessor bus. System support peripherals integrated into the M82380 provide
Interrupt Control, Timers, Wait State generation, DRAM Refresh Control, and System Reset logic.
The M82380’s DMA Controller can transfer data between devices of different data path widths using a single
channel. Each DMA channel operates independently in any of several modes. Each channel has a temporary
data storage register for handling non-aligned data without the need for external alignment logic.
271070–1
M82380 Internal Block Diagram
November 1992
Order Number: 271070-006
M82380
M82380
HIGH PERFORMANCE 32-BIT DMA CONTROLLER
WITH INTEGRATED SYSTEM SUPPORT PERIPHERALS
CONTENTS
PAGE
1.0 FUNCTIONAL OVERVIEW ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6
1.1 M82380 Architecture ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6
1.1.1 DMA Controller ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7
1.1.2 Programmable Interval Timers ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8
1.1.3 Interrupt Controller ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 9
1.1.4 Wait State Generator ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 10
1.1.5 DRAM Refresh Controller ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 10
1.1.6 CPU Reset Function ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 11
1.1.7 Register Map Relocation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 11
1.2 Host Interface ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 11
2.0 i386TM PROCESSOR HOST INTERFACE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 12
2.1 Master and Slave Modes ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 13
2.2 M80386 Interface Signals ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 13
2.2.1 Clock (CLK2) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 13
2.2.2 Data Bus (D0–D31) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 13
2.2.3 Address Bus (A31–A2) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 14
2.2.4 Byte Enable (BE3–BE0) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 14
2.2.5 Bus Cycle Definition Signals (D/C, W/R, M/IO) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 15
2.2.6 Address Status (ADS) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 15
2.2.7 Transfer Acknowledge (READY) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 15
2.2.8 Next Address Request (NA) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 15
2.2.9 Reset (RESET, CPURST) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 15
2.2.10 Interrupt Out (INT) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 17
2.3 M82380 Bus Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 17
2.3.1 Address Pipelining ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 17
2.3.2 Master Mode Bus Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 17
2.3.3 Slave Mode Bus Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 20
3.0 DMA CONTROLLER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 21
3.1 Functional Description ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22
3.2 Interface Signals ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 23
3.2.1 DREQn and EDACK (0–2) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 24
3.2.2 HOLD and HLDA ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 24
3.2.3 EOP ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 24
3.3 Modes of Operation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 24
3.3.1 Target/Requester Definition ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 25
3.3.2 Buffer Transfer Processes ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 25
3.3.3 Data Transfer Modes ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 26
3.3.4 Channel Priority Arbitration ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 30
3.3.5 Combining Priority Modes ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 32
3.3.6 Bus Operation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 33
3.4 Bus Arbitration and Handshaking ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 34
3.4.1 Synchronous and Asynchronous Sampling of DREQn and EOP ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 37
3.4.2 Arbitration of Cascaded Master Requests ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 39
3.4.3 Arbitration of Refresh Requests ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 41
2
M82380
CONTENTS
PAGE
3.0 DMA CONTROLLER (Continued)
3.5 DMA Controller Register Overview ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 41
3.5.1 Control/Status Registers ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 41
3.5.2 Channel Registers ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 42
3.5.3 Temporary Registers ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 43
3.6 DMA Controller Programming ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 44
3.6.1 Buffer Processes ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 44
3.6.2 Data Transfer Modes ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 45
3.6.3 Cascaded Bus Masters ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 45
3.6.4 Software Commands ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 45
3.7 Register Definitions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 46
4.0 PROGRAMMABLE INTERRUPT CONTROLLER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 53
4.1 Functional Description ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 53
4.1.1 Internal Block Diagram ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 53
4.1.2 Interrupt Controller Banks ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 54
4.2 Interface Signals ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 55
4.2.1 Interrupt Inputs ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 55
4.2.2 Interrupt Output (INT) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 56
4.3 Bus Functional Description ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 56
4.4 Mode of Operation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 57
4.4.1 End-Of-Interrupt ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 57
4.4.2 Interrupt Priorities ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 58
4.4.3 Interrupt Masking ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 61
4.4.4 Edge Or Level Interrupt Triggering ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 61
4.4.5 Interrupt Cascading ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 61
4.4.6 Reading Interrupt Status ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 62
4.5 Register Set Overview ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 62
4.5.1 Initialization Command Words (ICW) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 64
4.5.2 Operation Control Words (OCW) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 64
4.5.3 Poll/Interrupt Request/In-Service Status Register ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 65
4.5.4 Interrupt Mask Register (IMR) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 65
4.5.5 Vector Register (VR) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 65
4.6 Programming ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 65
4.6.1 Initialization (ICW) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 65
4.6.2 Vector Registers (VR) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 66
4.6.3 Operation Control Words (OCW) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 66
4.7 Register Bit Definition ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 67
4.8 Register Operational Summary ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 70
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M82380
CONTENTS
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5.0 PROGRAMMABLE INTERVAL TIMER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 71
5.1 Functional Description ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 71
5.1.1 Internal Architecture ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 72
5.2 Interface Signals ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 73
5.2.1 CLKIN ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 73
5.2.2 TOUT1, TOUT2, TOUT3 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 73
5.2.3 GATE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 73
5.3 Modes of Operation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 74
5.3.1 Mode 0ÐInterrupt on Terminal Count ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 74
5.3.2 Mode 1ÐGate Retriggerable One-Shot ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 74
5.3.3 Mode 2ÐRate Generator ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 76
5.3.4 Mode 3ÐSquare Wave Generator ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 77
5.3.5 Mode 4ÐInitial Count Triggered Strobe ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 79
5.3.6 Mode 5ÐGate Retriggerable Strobe ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 80
5.3.7 Operation Common to All Modes ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 81
5.4 Register Set Overview ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 81
5.4.1 Counter 0, 1, 2, 3 Registers ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 82
5.4.2 Control Word Register I & II ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 82
5.5 Programming ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 82
5.5.1 Initialization ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 82
5.5.2 Read Operation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 82
5.6 Register Bit Definitions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 84
6.0 WAIT STATE GENERATOR ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 86
6.1 Functional Description ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 86
6.2 Interface Signals ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 87
6.2.1 READY ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 87
6.2.2 READYO ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 87
6.2.3 WSC(0–1) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 87
6.3 Bus Function ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 88
6.3.1 Wait States in Non-Pipelined Cycle ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 88
6.3.2 Wait States in Pipelined Cycle ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 89
6.3.3 Extending and Early Terminating Bus Cycle ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 90
6.4 Register Set Overview ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 91
6.5 Programming ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 92
6.6 Register Bit Definition ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 92
6.7 Application Issues ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 92
6.7.1 External ‘READY’ Control Logic ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 92
7.0 DRAM REFRESH CONTROLLER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 94
7.1 Functional Description ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 94
7.2 Interface Signals ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 94
7.2.1 TOUT1/REF ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 94
7.3 Bus Function ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 95
7.3.1 Arbitration ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 95
7.4 Modes of Operation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 95
7.4.1 Word Size and Refresh Address Counter ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 95
7.5 Register Set Overview ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 96
7.6 Programming ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 96
7.7 Register Bit Definition ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 96
4
M82380
CONTENTS
PAGE
8.0 RELOCATION REGISTER AND ADDRESS DECODE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 96
8.1 Relocation Register ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 96
8.1.1 I/O-Mapped M82380 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 97
8.1.2 Memory-Mapped M82380 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 97
8.2 Address Decoding ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 97
9.0 CPU RESET AND SHUTDOWN DETECT ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 97
9.1 Hardware Reset ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 97
9.2 Software Reset ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 97
9.3 Shutdown Detect ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 98
10.0 INTERNAL CONTROL AND DIAGNOSTIC PORTS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 98
10.1 Internal Control Port ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 98
10.2 Diagnostic Ports ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 98
11.0 INTEL RESERVED I/O PORTS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 99
12.0 MECHANICAL DATA ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 100
12.1 Pin Assignment ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 100
12.2 Package Dimensions and Mounting ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 102
13.0 ELECTRICAL DATA ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 104
13.1 Power and Grounding ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 104
13.2 Power Decoupling ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 104
13.3 Unused Pin Recommendations ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 104
13.4 ICETM-386 Support ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 104
13.5 Maximum Ratings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 105
13.6 DC Specifications ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 106
13.7 AC Specifications ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 107
APPENDIX AÐPorts Listed by Address ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ A-1
APPENDIX BÐPorts Listed by Function ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ B-1
APPENDIX CÐPin Descriptions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ C-1
APPENDIX DÐM82380 System Notes ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ D-1
5
M82380
state of the processor at all times and acts or idles
according to the commands of the host. It monitors
the address pipeline status and generates the pro-
grammed number of wait states for the device being
accessed. The M82380 also has logic to reset the
i386 microprocessor via hardware or software reset
requests and processor shutdown status.
1.0 FUNCTIONAL OVERVIEW
The M82380 contains several independent function-
al modules. The following is a brief discussion of the
components and features of the M82380. Each
module has a corresponding detailed section later in
this data sheet. Those sections should be referred
to for design and programming information.
After a system reset, the M82380 is in the Slave
Mode. It appears to the system as an I/O device. It
becomes a bus master when it is performing DMA
transfers.
1.1 M82380 Architecture
The M82380 is comprised of several computer sys-
tem functions that are normally found in separate
LSI and VLSI components. These include: a high-
performance, eight-channel, 32-bit Direct Memory
Access Controller; a 20-level Programmable Inter-
rupt Controller which is a superset of the M8259A;
four 16-bit Programmable Interval Timers which are
functionally equivalent to the M82C54 timers; a
DRAM Refresh Controller; a Programmable Wait
State Generator; and system reset logic. The inter-
face to the M82380 is optimized for high-perform-
ance operation with the i386 microprocessor.
To maintain compatibility with existing software, the
registers within the M82380 are accessed as bytes.
If the internal logic of the M82380 requires a delay
before another access by the processor, wait states
are automatically inserted into the access cycle.
This allows the programmer to write initialization rou-
tines, etc. without regard to hardware recovery
times.
Figure 1 shows the basic architectural components
of the M82380. The following sections briefly dis-
cuss the architecture and function of each of the
distinct sections of the M82380.
The M82380 operates directly on the i386 micro-
processor bus. In the Slave Mode, it monitors the
271070–2
Figure 1. Architecture of the M82380
6
M82380
Byte Count RegisterÐNumber of bytes to trans-
fer. (24-bits)
1.1.1 DMA CONTROLLER
The M82380 contains a high-performance, 8-chan-
nel, 32-bit DMA controller. It is capable of transfer-
ring any combination of bytes, words, and double
words. The addresses of both source and destina-
tion can be independently incremented, decrement-
ed or held constant, and cover the entire 32-bit
physical address space of the i386 microprocessor.
It can disassemble and assemble misaligned data
via a 32-bit internal temporary data storage register.
Data transferred between devices of different data
path widths can also be assembled and disassem-
bled using the internal temporary data storage regis-
ter. The DMA Controller can also transfer aligned
data between I/O and memory on the fly, allowing
data transfer rates up to 32 megabytes per second
for an M82380 operating at 16 MHz. Figure 2 illus-
trates the functional components of the DMA Con-
troller.
Requester RegisterÐAddress of memory or pe-
ripheral which is requesting DMA service. (32-
bits)
Target RegisterÐAddress of peripheral or mem-
ory which will be accessed. (32-bits)
There are also port addresses which, when ac-
cessed, cause the M82380 to perform specific func-
tions. The actual data written does not matter, the
act of writing to the specific address causes the
command to be executed. The commands which op-
erate in this mode are: Master Clear, Clear Terminal
Count Interrupt Request, Clear Mask Register, and
Clear Byte Pointer Flip-Flop.
DMA transfers can be done between all combina-
tions of memory and I/O; memory-to-memory, mem-
ory-to-I/O, I/O-to-memory, and I/O-to-I/O. DMA
service can be requested through software and/or
hardware. Hardware DMA acknowledge signals are
available for all channels (except channel 4) through
an encoded 3-bit DMA acknowledge bus
(EDACK0–2).
There are twenty-four general status and command
registers in the M82380 DMA Controller. Through
these registers any of the channels may be pro-
grammed into any of the possible modes. The oper-
ating modes of any one channel are independent of
the operation of the other channels.
Each channel has three programmable registers
which determine the location and amount of data to
be transferred:
271070–3
Figure 2. M82380 DMA Controller
7
M82380
The M82380 DMA controller transfers blocks of data
(buffers) in three modes: Single Buffer, Buffer Auto-
Initialize, and Buffer Chaining. In the Single Buffer
Process, the M82380 DMA Controller is pro-
grammed to transfer one particular block of data.
Successive transfers then require reprogramming of
the DMA channel. Single Buffer transfers are useful
in systems where it is known at the time the transfer
begins what quantity of data is to be transferred, and
there is a contiguous block of data area available.
lows the user to reset or manually rotate the priority
schedule without reprogramming the command reg-
isters.
1.1.2 PROGRAMMABLE INTERVAL TIMERS
Four 16-bit programmable interval timers reside
within the M82380. These timers are identical in
function to the timers in the M82C54 Programmable
Interval Timer. All four of the timers share a common
clock input which can be independent of the system
clock. The timers are capable of operating in six dif-
ferent modes. In all of the modes, the current count
can be latched and read by the i386 processor at
any time, making these very versatile event timers.
Figure 3 shows the functional components of the
Programmable Interval Timers.
The Buffer Auto-Initialize Process allows the same
data area to be used for successive DMA transfers
without having to reprogram the channel.
The Buffer Chaining Process allows a program to
specify a list of buffer transfers to be executed. The
M82380 DMA Controller, through interrupt routines,
is reprogrammed from the list. The channel is repro-
grammed for a new buffer before the current buffer
transfer is complete. This pipelining of the channel
programming process allows the system to allocate
non-contiguous blocks of data storage space, and
transfer all of the data with one DMA process. The
buffers that make up the chain do not have to be in
contiguous locations.
The outputs of the timers are directed to key system
functions, making system design simpler. Timer 0 is
routed directly to an interrupt input and is not avail-
able externally. This timer would typically be used to
generate time-keeping interrupts.
Timers 1 and 2 have outputs which are available for
general timer/counter purposes as well as special
functions. Timer 1 is routed to the refresh control
logic to provide refresh timing. Timer 2 is connected
to an interrupt request input to provide other timer
functions. Timer 3 is a general purpose timer/coun-
ter whose output is available to external hardware. It
is also connected internally to the interrupt request
which defaults to the highest priority (IRQ0).
Channel priority can be fixed or rotating. Fixed priori-
ty allows the programmer to define the priority of
DMA channels based on hardware or other fixed pa-
rameters. Rotating priority is used to provide periph-
erals access to the bus on a shared basis.
With fixed priority, the programmer can set any
channel to have the current lowest priority. This al-
271070–4
Figure 3. Programmable Interval TimersÐBlock Diagram
8
M82380
made to program the vectors in the method of the
M8259A. This provides compatibility of existing soft-
ware that used the M8259A with new designs using
the M82380.
1.1.3 INTERRUPT CONTROLLER
The M82380 has the equivalent of three enhanced
M8259A Programmable Interrupt Controllers. These
controllers can all be operated in the Master mode,
but the priority is always as if they were cascaded.
There are 15 interrupt request inputs provided for
the user, all of which can be inputs from external
slave interrupt controllers. Cascading M8259As to
these request inputs allows a possible total of 120
external interrupt requests. Figure 4 is a block dia-
gram of the M82380 Interrupt Controller.
In the event of an unrequested or otherwise errone-
ous interrupt acknowledge cycle, the M82380 Inter-
rupt Controller issues a default vector. This vector,
programmed by the system software, will alert the
system of unsolicited interrupts of the M80386.
The functions of the M82380 Interrupt Controller are
identical to the M8259A, except in regards to pro-
gramming the interrupt vectors as mentioned above.
Interrupt request inputs are programmable as either
edge or level triggered and are software maskable.
Priority can be either fixed or rotating and interrupt
requests can be nested.
Each of the interrupt request inputs can be individu-
ally programmed with its own interrupt vector, allow-
ing more flexibility in interrupt vector mapping than
was available with the M8259A. An interrupt is pro-
vided to alert the system that an attempt is being
271070–5
Figure 4. M82380 Interrupt ControllerÐBlock Diagram
9
M82380
Enhancements are added to the M82380 for cas-
cading external interrupt controllers. Master to Slave
handshaking takes place on the data bus, instead of
dedicated cascade lines.
viously mentioned, deselecting the Wait State Gen-
erator does not disable its ability to determine the
proper number of wait states due to pipeline status
in subsequent bus cycles.
The number of wait states inserted into a pipelined
bus cycle is the value in the selected wait state reg-
ister. If the bus master is operating in the non-pipe-
lined mode, the Wait State Generator will increase
the number of wait states inserted into the bus cycle
by one.
1.1.4 WAIT STATE GENERATOR
The Wait State Generator is
a programmable
READY generation circuit for the i386 processor
bus. A peripheral requiring wait states can request
the Wait State Generator to hold the processor’s
READY input inactive for a predetermined number of
bus states. Six different wait state counts can be
programmed into the Wait State Generator by soft-
ware; three for memory accesses and three for I/O
accesses. A block diagram of the M82380 Wait
State Generator is shown in Figure 5.
On reset, the Wait State Generator’s registers are
loaded with the value FFH, giving the maximum
number of wait states for any access in which the
wait state select inputs are active.
1.1.5 DRAM REFRESH CONTROLLER
The peripheral being accessed selects the required
wait state count by placing a code on a 2-bit wait
state select bus. This code along with the M/IO sig-
nal from the bus master is used to select one of six
internal 4-bit wait state registers which has been
programmed with the desired number of wait states.
From zero to fifteen wait states can be programmed
into the wait state registers. The Wait State Genera-
tor tracks the state of the processor or current bus
master at all times, regardless of which device is the
current bus master and regardless of whether or not
the Wait State Generator is currently active.
The M82380 DRAM Refresh Controller consists of a
24-bit refresh address counter and bus arbitration
logic. The output of Timer 1 is used to periodically
request a refresh cycle. When the controller re-
ceives the request, it requests access to the system
bus through the HOLD signal. When bus control is
acknowledged by the processor or current bus mas-
ter, the refresh controller executes a memory read
operation at the address currently in the Refresh Ad-
dress Register. At the same time, it activates a re-
fresh signal (REF) that the memory uses to force a
refresh instead of a normal read. Control of the bus
is transferred to the processor at the completion of
this cycle. Typically a refresh cycle will take six clock
cycles to execute on an i386 processor bus.
The M82380 Wait State Generator is disabled by
making the select inputs both high. This allows hard-
ware which is intelligent enough to generate its own
ready signal to be accessed without penalty. As pre-
271070–6
Figure 5. M82380 Wait State GeneratorÐBlock Diagram
10
M82380
The M82380 DRAM Refresh Controller has the high-
est priority when requesting bus access and will in-
terrupt any active DMA process. This allows large
blocks of data to be moved by the DMA controller
without affecting the refresh function. Also the DMA
controller is not required to completely relinquish the
bus, the refresh controller simply steals a bus cycle
between DMA accesses.
signals of the M82380 are identical in function to
those of the i386 processor. As a slave, the M82380
operates with all of the features available on the
i386 processor bus. When the M82380 is in the Mas-
ter Mode, it looks identical to the i386 processor to
the connected devices.
The M82380 monitors the bus at all times, and de-
termines whether the current bus cycle is a pipelined
or non-pipelined access. All of the status signals of
the processor are monitored.
The amount by which the refresh address is incre-
mented is programmable to allow for different bus
widths and memory bank arrangements.
The control, status, and data registers within the
M82380 are located at fixed addresses relative to
each other, but the group can be relocated to either
memory or I/O space and to different locations with-
in those spaces.
1.1.6 CPU RESET FUNCTION
The M82380 contains a special reset function which
can respond to hardware reset signals from the
M82384, as well as a software reset command. The
circuit will hold the i386 processor’s RESET line ac-
tive while an external hardware reset signal is pres-
ent at its RESET input. It can also reset the i386
processor as the result of a software command. The
software reset command causes the M82380 to
hold the processor’s RESET line active for a mini-
mum of 62 CLK2 cycles; enough time to allow an
M80386 to re-initialize.
As a Slave device, the M82380 monitors the con-
trol/status lines of the CPU. The M82380 will gener-
ate all of the wait states it needs whenever it is ac-
cessed. This allows the programmer the freedom of
accessing M82380 registers without having to insert
NOPs in the program to wait for slower M82380 in-
ternal registers.
The M82380 can determine if a current bus cycle is
a pipelined or a non-pipelined cycle. It does this by
monitoring the ADS and READY signals and thereby
keeping track of the current state of the i386 proces-
sor.
The M82380 can be programmed to sense the shut-
down detect code on the status lines from the
M80386. If the Shutdown Detect function is enabled,
the M82380 will automatically reset the processor. A
diagnostic register is available which can be used to
determine the cause of reset.
As a bus master, the M82380 looks like an i386
processor to the rest of the system. This enables the
designer greater flexibility in systems which include
the M82380. The designer does not have to alter the
interfaces of any peripherals designed to operate
with the i386 processor to accommodate the
M82380. The M82380 will access any peripherals on
the bus in the same manner as the i386 processor,
including recognizing pipelined bus cycles.
1.1.7 REGISTER MAP RELOCATION
After a hardware reset, the internal registers of the
M82380 are located in I/O space beginning at port
address 0000H. The map of the M82380’s registers
is relocatable via a software command. The default
mapping places the M82380 between I/O address-
es 0000H and 00DBH. The relocation register allows
this map to be moved to any even 256-byte bounda-
ry in the processor’s 16-bit I/O address space or any
even 16-Mbyte boundary in the 32-bit memory ad-
dress space.
The M82380 is accessed as an 8-bit peripheral. This
is done to maintain compatibility with existing system
architectures and software. The i386 processor
places the data of all 8-bit accesses either on D (0–
7) or D (8–15). The M82380 will only accept data on
these lines when in the Slave Mode. When in the
Master Mode, the M82380 is a full 32-bit machine,
sending and receiving data in the same manner as
the i386 processor.
1.2 Host Interface
The M82380 is designed to operate efficiently on the
local bus of an M80386 microprocessor. The control
11
M82380
that the transceiver should be controlled so that
contention between the data bus transceiver and
the M82380 will not occur. In order to do this, port
address decoding logic should be included in the di-
rection and enable control logic of the transceiver.
When any of the M82380 internal registers is read,
the data bus transceiver should be disabled so that
only the M82380 will drive the local bus.
2.0 i386TM PROCESSOR HOST
INTERFACE
The M82380 contains a set of interface signals to
operate efficiently with the i386 host processor.
These signals were designed so that minimal hard-
ware is needed to connect the M82380 to the i386
processor.
This section describes the basic bus functions of the
M82380 to show how this device interacts with the
i386 processor. Other signals which are not directly
related to the host interface will be discussed in their
associated functional block description.
Figure 6 depicts a typical system configuration with
the i386 processor. As shown in the diagram, the
M82380 is designed to interface directly with the
i386 bus.
Since the M82380 is residing on the opposite side of
the data bus transceiver (with respect to the rest of
the peripherals in the system), it is important to note
271070–7
Figure 6. i386TM/M82380 System Configuration
12
M82380
2.2.1 CLOCK (CLK2)
2.1 Master and Slave Modes
The CLK2 input provides fundamental timing for the
M82380. It is divided by two internally to generate
the M82380 internal clock. Therefore, CLK2 should
be driven with twice the i386’s frequency. In order to
maintain synchronization with the i386 host proces-
sor, the M82380 and the i386 processor should
share a common clock source.
At any time, the M82380 acts as either a Slave de-
vice or a Master device in the system. Upon reset,
the M82380 will be in the Slave Mode. In this mode,
the i386 processor can read/write into the M82380
internal registers. Initialization information may be
programmed into the M82380 during Slave Mode.
When DMA service (including DRAM Refresh Cycles
generated by the M82380) is requested, the M82380
will request and subsequently get control of the i386
processor local bus. This is done through the HOLD
and HLDA (Hold Acknowledge) signals. When the
i386 processor responds by asserting the HLDA sig-
nal, the M82380 will switch into Master Mode and
perform DMA transfers. In this mode, the M82380 is
the bus master of the system. It can read/write data
from/to memory and peripheral devices. The
M82380 will return to the Slave Mode upon comple-
tion of DMA transfers, or when HLDA is negated.
The internal clock consists of two phases: PHI1 and
PHI2. Each CLK2 period is a phase of the internal
clock. PHI2 is usually used to sample input and set
up internal signals and PHI1 is for latching internal
data. Figure 7 illustrates the relationship of CLK2
and the M82380 internal clock signals. The CPURST
signal generated by the M82380 guarantees that the
i386 processor will wake up in phase with PHI1.
2.2.2 DATA BUS (D0–D31)
This 32-bit three-state bidirectional bus provides a
general purpose data path between the M82380 and
the system. These pins are tied directly to the corre-
sponding Data Bus pins of the i386 processor local
bus. The Data Bus is also used for interrupt vectors
generated by the M82380 in the Interrupt Acknowl-
edge cycle.
2.2 M80386 INTERFACE SIGNALS
As mentioned in the Architecture section, the Bus
Interface module of the M82380 (see Figure 1) con-
tains signals that are directly connected to the i386
host processor. This module has separate 32-bit
Data and Address busses. Also, it has additional
control signals to support different bus operations
on the system. By residing on the i386 processor
local bus, the M82380 shares the same address,
data and control lines with the processor. The fol-
lowing subsections discuss the signals which inter-
face to the i386 host processor.
During Slave I/O operations, the M82380 expects a
single byte to be written or read. When the i386 host
processor writes into the M82380, either D0–D7 or
D8–D15 will be latched into the M82380, depending
upon how the Byte Enable (BE0–BE3) signals are
driven. The M82380 does not need to look at D16–
D31 since the i386 processor duplicates
271070–8
Figure 7. CLK2 and M82380 Internal Clock
13
M82380
the single byte data on both halves of the bus. When
the M80386 host processor reads from the M82380,
the single byte data will be duplicated four times on
the Data Bus; i.e., on D0–D7, D8–D15, D16–D23
and D24–D31.
(00000000H to FFFFFFFFH), and 64 K-bytes of I/O
addresses (00000000H to 0000FFFFH).
2.2.4 BYTE ENABLE (BE3–BE0)
These bidirectional pins select specific byte(s) in the
double word addressed by A31–A2. Similar to the
Address Bus function, these signals are used as in-
puts to address internal M82380 registers during
Slave Mode operation. During Master Mode opera-
tion, they are used as outputs by the M82380 to ad-
dress memory and I/O locations.
During Master Mode, the M82380 can transfer 32-,
16-, and 8-bit data between memory (or I/O devices)
and I/O devices (or memory) via the Data Bus.
2.2.3 ADDRESS BUS (A31–A2)
These three-state bidirectional signals are connect-
ed directly to the i386 Address Bus. In the Slave
Mode, they are used as input signals so that the
processor can address the M82380 internal ports/
registers. In the Master Mode, they are used as out-
put signals by the M82380 to address memory and
peripheral devices. The Address Bus is capable of
addressing 4 G-bytes of physical memory space
In addition to the above function, BE3 is used to
enable a production test mode and must be LOW
during reset. The i386 processor will automatically
hold BE3 LOW during RESET.
The definitions of the Byte Enable signals depend
upon whether the M82380 is in the Master or Slave
Mode. These definitions are depicted in Table 1.
Table 1. Byte Enable Signals
As INPUTS (Slave Mode):
Data Bits Written
BE3–BE0
Implied A1, A0
to M82380*
XXX0
XX01
X011
00
01
10
11
D0–D7
D8–D15
D0–D7
D8–D15
X111
X–DON’T CARE
*During READ, data will be duplicated on D0–D7, D8–D15, D16–D23, and D24–D31.
During WRITE, the M80386 host processor duplicates data on D0–D15, and D16–D31, so that the
M82380 is concerned only with the lower half of the Data Bus.
As OUTPUTS (Master Mode):
Logical Byte Presented On
Byte to be Accessed
Relative to A31–A2
BE3–BE0
Data Bus During WRITE Only*
D24–31 D16–23 D8–15
D0–7
1110
1101
1011
0111
1001
1100
0011
1000
0001
0000
0
U
U
U
A
U
U
B
U
C
D
U
U
A
U
B
U
A
C
B
C
U
A
U
A
A
B
B
B
A
B
A
A
A
A
A
A
A
A
A
A
1
2
3
1, 2
0, 1
2, 3
0, 1, 2
1, 2, 3
0, 1, 2, 3
e
e
e
e
e
U
A
B
C
D
Undefined
Logical D0–D7
Logical D8–D15
Logical D16–D23
Logical D24–D31
*Actual number of bytes accessed depends upon the programmed data path width.
14
M82380
2.2.5 BUS CYCLE DEFINITION SIGNALS (D/C,
W/R, M/IO)
2.2.7 TRANSFER ACKNOWLEDGE (READY)
This input indicates that the current bus cycle is
complete. In the Master Mode, assertion of this sig-
nal indicates the end of a DMA bus cycle. In the
Slave Mode, the M82380 monitors this input and
ADS to detect a pipelined address cycles. This sig-
nal should be tied directly to the READY input of the
i386 host processor.
These three-state bidirectional signals define the
type of bus cycle being performed. W/R distin-
guishes between write and read cycles. D/C distin-
guishes between processor data and control cycles.
M/IO distinguishes between memory and I/O cy-
cles.
During Slave Mode, these signals are driven by the
i386 host processor; during Master Mode, they are
driven by the M82380. In either mode, these signals
will be valid when the Address Status (ADS) is driven
LOW. Exact bus cycle definitions are given in Table
2. Note that some combinations are recognized as
inputs, but not generated as outputs. In the Master
Mode, D/C is always HIGH.
2.2.8 NEXT ADDRESS REQUEST (NA)
This input is used to indicate to the M82380 in the
Master Mode that the system is requesting address
pipelining. When driven LOW by either memory or
peripheral devices during Master Mode, it indicates
that the system is prepared to accept a new address
and bus cycle definition signals from the M82380
before the end of the current bus cycle. If this input
is active when sampled by the M82380, the next ad-
dress is driven onto the bus, provided a bus request
is already pending internally.
2.2.6 ADDRESS STATUS (ADS)
This bidirectional signal indicates that a valid ad-
dress (A2–A31, BE0–BE3) and bus cycle definition
(W/R, D/C, M/IO) is being driven on the bus. In the
Master Mode, it is driven by the M82380 as an out-
put. In the Slave Mode, this signal is monitored as an
input by the M82380. By the current and past status
of ADS and the READY input, the M82380 is able to
determine, during Slave Mode, if the next bus cycle
is a pipelined address cycle. ADS is asserted during
T1 and T2P bus states (see Bus State Definition).
This input pin is monitored only in the Master Mode.
In the Slave Mode, the M82380 uses the ADS and
READY signals to determine address pipelining cy-
cles, and NA will be ignored.
2.2.9 RESET (RESET, CPURST)
RESET
Note that during the idle states at the beginning and
the end of a DMA process, neither the i386 proces-
sor nor the M82380 is driving the ADS signal; i.e.,
the signal is left floated. Therefore, it is important to
use a pull-up resistor (approximately 10 KX) on the
ADS signal.
This synchronous input suspends any operation in
progress and places the M82380 in a known initial
state. Upon reset, the M82380 will be in the Slave
Mode waiting to be initialized by the i386 host
Table 2. Bus Cycle Definition
M/IO
D/C
W/R
As INPUTS
Interrupt
As OUTPUTS
0
0
0
NOT GENERATED
Acknowledge
UNDEFINED
I/O Read
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
NOT GENERATED
I/O Read
I/O Write
I/O Write
UNDEFINED
HALT if
NOT GENERATED
NOT GENERATED
e
SHUTDOWN if
BE(3–0)
X011
e
BE (3–0)
XXX0
1
1
1
1
0
1
Memory Read
Memory Write
Memory Read
Memory Write
15
M82380
Table 3. Output Signals Following RESET
Signal
Level
A2–A31, D0–D31, BE0–BE3
D/C, W/R, M/IO, ADS
Float
Float
‘1’
READYO
EOP
‘1’ (Weak Pull-UP)
‘100’
‘0’
EDACK2–EDACK0
HOLD
INT
TOUT1/REF, TOUT2/IRQ3, TOUT3
CPURST
UNDEFINED*
UNDEFINED*
‘0’
*The Interrupt Controller and Programmable Interval Timer are initialized by software commands.
processor. The M82380 is reset by asserting RESET
for 15 or more CLK2 periods. When RESET is as-
serted, all other input pins are ignored, and all other
bus pins are driven to an idle bus state as shown in
Table 3. The M82380 will determine the phase of its
internal clock following RESET going inactive.
CPURST
This output signal is used to reset the i386 host
processor. It will go active (HIGH) whenever one of
the following events occurs: a) M82380’s RESET in-
put is active; b) a software RESET command is is-
sued to the M82380; or c) when the M82380 detects
a processor Shutdown cycle and when this detec-
tion feature is enabled (see CPU Reset and Shut-
down Detect). When activated, CPURST will be held
active for 62 CLK2 periods. The timing of CPURST is
such that the i386 processor will be in synchroniza-
tion with the M82380. This timing is shown in
Figure 9.
RESET is level-sensitive and must be synchronous
to the CLK2 signal. Therefore, this RESET input
should be tied to the RESET output of the Clock
Generator. The RESET setup and hold time require-
ments are shown in Figure 8.
271070–9
T30-RESET Hold Time
T31-RESET Setup Time
Figure 8. RESET Timing
271070–10
T33-CPU Reset from CLK2
Figure 9. CPURST Timing
16
M82380
16 MHz interleaved memory designs with 100 ns ac-
cess time DRAMs, zero wait state memory accesses
can be achieved when pipelined addressing is se-
lected.
2.2.10 INTERRUPT OUT (INT)
This output pin is used to signal the i386 host proc-
essor that one or more interrupt requests (either in-
ternal or external) are pending. The processor is ex-
pected to respond with an Interrupt Acknowledge
cycle. This signal should be connected directly to
the Maskable Interrupt Request (INTR) input of the
i386 host processor.
In the Master Mode, the M82380 is capable of initiat-
ing, on a cycle-by-cycle basis, either a pipelined or
non-pipelined access depending upon the state of
the NA input. If a pipelined cycle is requested (indi-
cated by NA being driven LOW), the M82380 will
drive the address and bus cycle definition of the next
cycle as soon as there is an internal bus request
pending.
2.3 M82380 Bus Timing
The M82380 internally divides the CLK2 signal by
two to generate its internal clock. Figure 7 shows the
relationship of CLK2 and the internal clock. The in-
ternal clock consists of two phases: PHI1 and PHI2.
Each CLK2 period is a phase of the internal clock. In
Figure 7, both PHI1 and PHI2 of the M82380 internal
clock are shown.
In the Slave Mode, the M82380 is constantly moni-
toring the ADS and READY signals on the processor
local bus to determine if the current bus cycle is a
pipelined cycle. If a pipelined cycle is detected, the
M82380 will request one less wait state from the
processor if the Wait State Generator feature is se-
lected. On the other hand, during an M82380 inter-
nal register access in a pipelined cycle, it will make
use of the advance address and bus cycle informa-
tion. In all cases, Address Pipelining will result in a
savings of one wait state.
In the M82380, whether it is in the Master or Slave
Mode, the shortest time unit of bus activity is a bus
state. A bus state, which is also referred as a
‘T-state’, is defined as one M82380 PHI2 clock peri-
od (i.e., two CLK2 periods). Recall in Table 2, there
are six different types of bus cycles in the M82380
as defined by the M/IO, D/C and W/R signals. Each
of these bus cycles is composed of two or more bus
states. The length of a bus cycle depends on when
the READY input is asserted (i.e., driven LOW).
2.3.2 MASTER MODE BUS TIMING
When the M82380 is in the Master Mode, it will be in
one of six bus states. Figure 10 shows the complete
bus state diagram of the Master Mode, including
pipelined address states. As seen in the figure, the
M82380 state diagram is very similar to that of the
i386 processor. The major difference is that in the
M82380, there is no Hold state. Also, in the M82380,
the conditions for some state transitions depend
upon whether it is the end of a DMA process.
2.3.1 ADDRESS PIPELINING
The M82380 supports Address Pipelining as an op-
tion in both the Master and Slave Mode. This feature
typically allows a memory or peripheral device to op-
erate with one less wait state than would otherwise
be required. This is possible because during a pipe-
lined cycle, the address and bus cycle definition of
the next cycle will be generated by the bus master
while waiting for the end of the current cycle to be
acknowledged. The pipelined bus is especially well
suited for interleaved memory environment. For
NOTE:
The term ‘end of a DMA process’ is loosely defined
here. It depends on the DMA modes of operation
as well as the state of the EOP and DREQ inputs.
This is explained in detail in section 3ÐDMA Con-
troller.
17
M82380
The M82380 will enter the idle state, Ti, upon RE-
SET and whenever the internal address is not avail-
able at the end of a DMA cycle or at the end of a
DMA process. When address pipelining is not used
(NA is not asserted), a new bus cycle always begins
with state T1. During T1, address and bus cycle defi-
nition signals will be driven on the bus. T1 is always
followed by T2.
Use of the address pipelining feature allows the
M82380 to enter three additional bus states: T1P,
T2P, and T2i. T1P is the first bus state of a pipelined
bus cycle. T2P follows T1P (or T2) if NA is asserted
when sampled. The M82380 will drive the bus with
the address and bus cycle definition signals of the
next cycle during T2P. From the state diagram, it can
be seen that after an idle state Ti, the first bus cycle
must begin with T1, and is therefore a non-pipelined
bus cycle. The next bus cycle can be pipelined if NA
is asserted and the previous bus cycle ended in a
T2P state. Once the M82380 is in a pipelined cycle
and provided that NA is asserted in subsequent cy-
cles, the M82380 will be switching between T1P and
T2P states. If the end of the current bus cycle is not
acknowledged by the READY input, the M82380 will
extend the cycle by adding T2P states. The fastest
pipelined cycle will consist of one T1P and one T2P
state.
If a bus cycle is not acknowledged (with READY)
during T2 and NA is negated, T2 will be repeated.
When the end of the bus cycle is acknowledged dur-
ing T2, the following state will be T1 of the next bus
cycle (if the internal address latch is loaded and if
this is not the end of the DMA process). Otherwise,
the Ti state will be entered. Therefore, if the memory
or peripheral accessed is fast enough to respond
within the first T2, the fastest non-pipelined cycle will
take one T1 and one T2 state.
271070–11
NOTE:
ADAVÐInternal Address Available
Figure 10. Master Mode State Diagram
18
M82380
The M82380 will enter state T2i when NA is assert-
ed and when one of the following two conditions
occurs. The first condition is when the M82380 is in
state T2. T2i will be entered if READY is not assert-
ed and there is no next address available. This situa-
tion is similar to a wait state. The M82380 will stay in
T2i for as long as this condition exists. The second
condition which will cause the M82380 enter T2i is
when the M82380 is in state T1P. Before going to
state T2P, the M82380 needs to wait in state T2i
until the next address is available. Also, in both cas-
es, if the DMA process is complete, the M82380 will
enter the T2i state in order to finish the current DMA
cycle.
Figure 11 is a timing diagram showing non-pipelined
bus accesses in the Master Mode. Figure 12 shows
the timing of pipelined accesses in the Master Mode.
271070–12
Figure 11. Non-Pipelined Bus Cycles
271070–13
Figure 12. Pipelined Bus Cycles
19
M82380
dress and bus cycle signals one bus state earlier
than in a non-pipelined cycle.
2.3.3 SLAVE MODE BUS TIMING
Figure 13 shows the Slave Mode bus timing in both
pipelined and non-pipelined cycles when the
M82380 is being accessed. Recall that during Slave
Mode, the M82380 will constantly monitor the ADS
and READY signals to determine if the next cycle is
pipelined. In Figure 13, the first cycle is non-pipe-
lined and the second cycle is pipelined. In the pipe-
lined cycle, the M82380 will start decoding the ad-
The READY input signal is sampled by the M80386
host processor to determine the completion of a bus
cycle. This occurs during the end of every T2 and
T2P state. Normally, the output of the M82380 Wait
State Generator, READYO, is directly connected to
the READY input of the i386 host processor and the
M82380. In such case, READYO and READY will be
identical (see Wait State Generator).
271070–14
NOTE:
NA is shown here only for timing reference. It is not sampled by the M82380 during Slave Mode.
When the M82380 registers are accessed, it will take one or more wait states in pipelined and two or more wait states in
non-pipelined cycle to complete the internal access.
Figure 13. Slave Read/Write Timing
20
M82380
source. Figure 14 is a block diagram of the M82380
DMA Controller.
3.0 DMA CONTROLLER
The M82380 DMA Controller is capable of transfer-
ring data between any combination of memory and/
or I/O, with any combination (8-, 16-, or 32-bits) of
data path widths. Bus bandwidth is optimized
through the use of an internal temporary register
which can disassemble or assemble data to or from
either an aligned or a non-aligned destination or
The M82380 has eight channels of DMA. Each
channel operates independently of the others. With-
in the operation of the individual channels, there are
many different modes of data transfer available.
Many of the operating modes can be intermixed to
provide a very versatile DMA controller.
271070–15
Figure 14. M82380 DMA Controller Block Diagram
21
M82380
respectively. These registers have two parts: one
which contains the current address being used in the
DMA process (Current Address Register), and one
which holds the programmed base address (Base
Address Register). The contents of the Base Regis-
ters are never changed by the M82380 DMA Con-
troller. The Current Registers are incremented or
decremented according to the progress of the DMA
process.
3.1 Functional Description
In describing the operation of the M82380’s DMA
Controller, close attention to terminology is required.
Before entering the discussion of the function of the
M82380 DMA Controller, the following explanations
of some of the terminology used herein may be of
benefit. First, a few terms for clarification:
DMA PROCESSÐA DMA process is the execution
of a programmed DMA task from beginning to end.
Each DMA process requires initial programming by
the host M80386 microprocessor.
The Byte Count is the component of the DMA pro-
cess which dictates the amount of data which must
be transferred. Current and Base Byte Count Regis-
ters are provided. The Current Byte Count Register
is decremented once for each byte transferred by
the DMA process. When the register is decremented
past zero, the Byte Count is considered ‘expired’
and the process is terminated or restarted, depend-
ing on the mode of operation of the channel. The
point at which the Byte Count expires is called ‘Ter-
minal Count’ and several status signals are depen-
dent on this event.
BUFFERÐA contiguous block of data.
BUFFER TRANSFERÐThe action required by the
DMA to transfer an entire buffer.
DATA TRANSFERÐThe DMA action in which a
group of bytes, words, or double words are moved
between devices by the DMA Controller. A data
transfer operation may involve movement of one or
many bytes.
Each channel of the M82380 DMA Controller also
contains a 32-bit Temporary Register for use in as-
sembling and disassembling non-aligned data. The
operation of this register is transparent to the user,
although the contents of it may affect the timing of
some DMA handshake sequences. Since there is
data storage available for each channel, the DMA
Controller can be interrupted without loss of data.
BUS CYCLEÐAccess by the DMA to a single byte,
word, or double word.
Each DMA channel consists of three major compo-
nents. These components are identified by the con-
tents of programmable registers which define the
memory or I/O devices being serviced by the DMA.
They are the Target, the Requester, and the Byte
Count. They will be defined generically here and in
greater detail in the DMA register definition section.
The M82380 DMA Controller is a slave on the bus
until a request for DMA service is received via either
a software request command or a hardware request
signal. The host processor may access any of the
control/status or channel registers at any time the
M82380 is a bus slave. Figure 15 shows the flow of
operations that the DMA Controller performs.
The Requester is the device which requires service
by the M82380 DMA Controller, and makes the re-
quest for service. All of the control signals which the
DMA monitors or generates for specific channels
are logically related to the Requester. Only the Re-
quester is considered capable of initiating or termi-
nating a DMA process.
At the time a DMA service request is received, the
DMA Controller issues a bus hold request to the
host processor. The M82380 becomes the bus mas-
ter when the host relinquishes the bus by asserting a
hold acknowledge signal. The channel to be serv-
iced will be the one with the highest priority at the
time the DMA Controller becomes the bus master.
The DMA Controller will remain in control of the bus
until the hold acknowledge signal is removed, or un-
til the current DMA transfer is complete.
The Target is the device with which the Requester
wishes to communicate. As far as the DMA process
is concerned, the Target is a slave which is incapa-
ble of control over the process.
The direction of data transfer can be either from Re-
quester to Target or from Target to Requester; i.e.,
each can be either a source or a destination.
While the M82380 DMA Controller has control of the
bus, it will perform the required data transfer(s). The
type of transfer, source and destination addresses,
and amount of data to transfer are programmed in
the control registers of the DMA channel which re-
ceived the request for service.
The Requester and Target may each be either I/O
or memory. Each has an address associated with it
that can be incremented, decremented, or held con-
stant. The addresses are stored in the Requester
Address Registers and Target Address Registers,
22
M82380
At completion of the DMA process, the M82380 will
remove the bus hold request. At this time the
M82380 becomes a slave again, and the host re-
turns to being a master. If there are other DMA
channels with requests pending, the controller will
again assert the hold request signal and restart the
bus arbitration and switching process.
3.2 Interface Signals
There are fourteen control signals dedicated to the
DMA process. They include eight DMA Channel Re-
quests (DREQn), three Encoded DMA Acknowledge
signals (EDACKn), Processor Hold and Hold Ac-
knowledge (HOLD, HLDA), and End-Of-Process
(EOP). The DREQn inputs and EDACK(0–2) outputs
are handshake signals to the devices requiring DMA
service. The HOLD output and HLDA input are hand-
shake signals to the host processor. Figure 16
shows these signals and how they interconnect be-
tween the M82380 DMA Controller, and the Re-
quester and Target devices.
271070–16
Figure 15. Flow of DMA Controller Operation
271070–17
Figure 16. Requester, Target, and DMA Controller Interconnection
23
M82380
the DMA Controller and the host processor. HOLD is
an output from the M82380 and HLDA is an input.
HOLD is asserted by the DMA Controller when there
is a pending DMA request, thus requesting the proc-
essor to give up control of the bus so the DMA pro-
cess can take place. The M80386 responds by as-
serting HLDA when it is ready to relinquish control of
the bus.
3.2.1 DREQn and EDACK(0–2)
These signals are the handshake signals between
the peripheral and the M82380. When the peripheral
requires DMA service, it asserts the DREQn signal
of the channel which is programmed to perform the
service. The M82380 arbitrates the DREQn against
other pending requests and begins the DMA pro-
cess after finishing other higher priority processes.
The M82380 will begin operations on the bus one
clock cycle after the HLDA signal goes active. For
this reason, other devices on the bus should be in
the slave mode when HLDA is active.
When the DMA service for the requested channel is
in progress, the EDACK(0–2) signals represent the
DMA channel which is accessing the Requester.
The 3-bit code on the EDACK(0–2) lines indicates
the number of the channel presently being serviced.
Table 4 shows the encoding of these signals. Note
that Channel 4 does not have a corresponding hard-
ware acknowledge.
HOLD and HLDA should not be used to gate or se-
lect peripherals requesting DMA service. This is be-
cause of the use of DMA-like operations by the
DRAM Refresh Controller. The Refresh Controller is
arbitrated with the DMA Controller for control of the
bus, and refresh cycles have the highest priority. A
refresh cycle will take place between DMA cycles
without relinquishing bus control. See the Arbitration
of Refresh Requests for a more detailed discussion
of the interaction between the DMA Controller and
the DRAM Refresh Controller.
The DMA acknowledge (EDACK) signals indicate
the active channel only during DMA accesses to the
Requester. During accesses to the Target,
EDACK(0–2) has the idle code (100). EDACK(0–2)
can thus be used to select a Requester device dur-
ing a transfer.
Table 4. EDACK Encoding
During a DMA Transfer
3.2.3 EOP
EOP is a bidirectional signal used to indicate the end
of a DMA process. The M82380 activates this as an
output during the T2 states of the last Requester bus
cycle for which a channel is programmed to execute.
The Requester should respond by either withdraw-
ing its DMA request, or interrupting the host proces-
sor to indicate that the channel needs to be pro-
grammed with a new buffer. As an input, this signal
is used to tell the DMA Controller that the peripheral
being serviced does not require any more data to be
transferred. This indicates that the current buffer is
to be terminated.
EDACK2 EDACK1 EDACK0 Active Channel
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
Target Access
5
6
7
DREQn can be programmed as either an Asynchro-
nous or Synchronous input.
EOP can be programmed as either an Asynchro-
nous or a Synchronous input. Details on synchro-
nous versus asynchronous operation of this pin are
described later in this data sheet.
The EDACKn signals are always active. They either
indicate ‘no acknowledge’ or they indicate a bus ac-
cess to the requester. The acknowledge code is ei-
ther 100, for an idle DMA or during a DMA access to
the Target, or ‘n’ during a Requester access, where
n is the binary value representing the channel. A
simple 3-line to 8-line decoder can be used to pro-
vide discrete acknowledge signals for the peripher-
als.
3.3 Modes of Operation
The M82380 DMA Controller has many independent
operating functions. When designing peripheral in-
terfaces for the M82380 DMA Controller, all of the
functions or modes must be considered. All of the
channels are independent of each other (except in
priority of operation) and can operate in any of the
modes. Many of the operating modes, though inde-
pendently programmable, affect the operation of
other modes. Because of the large number of com-
3.2.2 HOLD and HLDA
The Hold Request (HOLD) and Hold Acknowledge
(HLDA) signals are the handshake signals between
24
M82380
binations possible, each programmable mode is dis-
cussed here with its affects on the operation of other
modes. The entire list of possible combinations will
not be presented.
the data. In a Write transfer, the Requester is the
source and the Target in the destination.
The Requester and Target addresses can each be
independently programmed to be incremented, dec-
remented, or held constant. As an example, the
M82380 is capable of reversing a string or data by
having a Requester address increment and the Tar-
get address decrement in a memory-to-memory
transfer.
Table 5 shows the categories of DMA features avail-
able in the M82380. Each of the five major
categories is independent of the others. The sub-
categories are the available modes within the major
function or mode category. The following sections
explain each mode or function and its relation to oth-
er features.
3.3.2 BUFFER TRANSFER PROCESSES
Table 5. DMA Operating Modes
The M82380 DMA Controller allows three program-
mable Buffer Transfer Processes. These processes
define the logical way in which a buffer of data is
accessed by the DMA.
I. Target/Requester Definition
a. Data Transfer Direction
b. Device Type
The three Buffer Transfer Processes include the Sin-
gle Buffer Process, the Buffer Auto-Initialize Pro-
cess, and the Buffer Chaining Process. These pro-
cesses require special programming considerations.
See the DMA Programming section for more details
on setting up the Buffer Transfer Processes.
c. Increment/Decrement/Hold
II. Buffer Processes
a. Single Buffer Process
b. Buffer Auto-Initialize Process
c. Buffer Chaining Process
III. Data Transfer/Handshake Modes
a. Single Transfer Mode
b. Demand Transfer Mode
c. Block Transfer Mode
d. Cascade Mode
SINGLE BUFFER PROCESS
The Single Buffer Process allows the DMA channel
to transfer only one buffer of data. When the buffer
has been completely transferred (Current Byte
Count decremented past zero or EOP input active),
the DMA process ends and the channel becomes
idle. In order for that channel to be used again, it
must be reprogrammed.
IV. Priority Arbitration
a. Fixed
b. Rotating
The single Buffer Process is usually used when the
amount of data to be transferred is known exactly,
and it is also known that there is not likely to be any
data to follow before the operating system can
reprogram the channel.
c. Programmable Fixed
V. Bus Operation
a. Fly-By (Single-Cycle)/Two-Cycle
b. Data Path Width
c. Read, Write, or Verify Cycles
BUFFER AUTO-INITIALIZE PROCESS
3.3.1 TARGET/REQUESTER DEFINITION
The Buffer Auto-Initialize Process allows multiple
groups of data to be transferred to or from a single
buffer. This process does not require reprogram-
ming. The Current Registers are automatically repro-
grammed from the Base Registers when the current
process is terminated, either by an expired Byte
Count or by an external EOP signal. The data trans-
ferred will always be between the same Target and
Requester.
All DMA transfers involve three devices: the DMA
Controller, the Requester, and the Target. Since the
devices to be accessed by the DMA Controller vary
widely, the operating characteristics of the DMA
Controller must be tailored to the Requester and
Target devices.
The Requester can be defined as either the source
or the destination of the data to be transferred. This
is done by specifying a Write or a Read transfer,
respectively. In a Read transfer, the Target is the
data source and the Requester is the destination for
The auto-initialization/process-execution cycle is re-
peated, with a HOLD/HLDA re-arbitration, until the
channel is either disabled or re-programmed.
25
M82380
loading process this way is that, for most applica-
tions, the Byte Count and the Requester will not
change from one buffer to the next, and therefore do
not need to be reprogrammed. The details of pro-
gramming the channel for the Buffer Chaining Pro-
cess can be found in the section of DMA program-
ming.
BUFFER CHAINING PROCESS
The Buffer Chaining Process is useful for transfer-
ring large quantities of data into non-contiguous
buffer areas. In this process, a single channel is
used to process data from several buffers, while
having to program the channel only once. Each new
buffer is programmed in a pipelined operation that
provides the new buffer information while the old
buffer is being processed. The chain is created by
loading new buffer information while the M82380
DMA Controller is processing the Current Buffer.
When the Current Buffer expires, the M82380 DMA
Controller automatically restarts the channel using
the new buffer information.
3.3.3 DATA TRANSFER MODES
Three Data Transfer modes are available in the
M82380 DMA Controller. They are the Single Trans-
fer, Block Transfer, and Demand Transfer Modes.
These transfer modes can be used in conjunction
with any one of three Buffer Transfer modes: Single
Buffer, Auto-Initialized Buffer, and Buffer Chaining.
Any Data Transfer Modes can be used under any of
the Buffer Transfer Modes. These modes are inde-
pendently available for all DMA channels.
Loading the new buffer information is done by an
interrupt routine which is requested by the M82380.
Interrupt Request 1 (IRQ1) is tied internally to the
M82380 DMA Controller for this purpose. IRQ1 is
generated by the M82380 when the new buffer infor-
mation is loaded into the channel’s Current Regis-
ters, leaving the Base Registers ‘empty’. The inter-
rupt service routine loads new buffer information into
the Base Registers. The host processor is required
to load the information for another buffer before the
current Byte Count expires. The process repeats un-
til the host programs the channel back to single buff-
er operation, or until the channel runs out of buffers.
Different devices being serviced by the DMA Con-
troller require different handshaking sequences for
data transfers to take place. Three handshaking
modes are available on the M82380, giving the de-
signer the opportunity to use the DMA Controller as
efficiently as possible. The speed at which data can
be presented or read by a device can affect the way
a DMA controller uses the host’s bus, thereby affect-
ing not only data throughput during the DMA pro-
cess, but also affecting the host’s performance by
limiting its access to the bus.
The channel runs out of buffers when the Current
Buffer expires and the Base Registers have not yet
been loaded with new buffer information. When this
occurs, the channel must be reprogrammed.
SINGLE TRANSFER MODE
In the Single Transfer Mode, one data transfer to or
from the Requester is performed by the DMA Con-
troller at a time. The DREQn input is arbitrated and
the HOLD/HLDA sequence is executed for each
transfer. Transfers continue in this manner until the
Byte Count expires, or until EOP is sampled active. If
the DREQn input is held active continuously, the en-
tire DREQ-HOLD-HLDA-DACK sequence is repeat-
ed over and over until the programmed number of
bytes has been transferred. Bus control is released
to the host between each transfer. Figure 17 shows
the logical flow of events which make up a buffer
transfer using the Single Transfer Mode.
If an external EOP is encountered while executing a
Buffer Chaining Process, the current buffer is con-
sidered expired and the new buffer information is
loaded into the Current Registers. If the Base Regis-
ters are ‘empty’, the chain is terminated.
The channel uses the Base Target Address Register
as an indicator of whether or not the Base Registers
are full. When the most significant byte of the Base
Target Register is loaded, the channel considers all
of the Base Registers loaded, and removes the in-
terrupt request. This requires that the other Base
Registers (Base Requester Address, Last Byte
Count) must be loaded before the Base Target Ad-
dress Register. The reason for implementing the re-
26
M82380
The Single Transfer Mode is used for devices which
require complete handshake cycles with each data
access. Data is transferred to or from the Requester
only when the Requester is ready to perform the
transfer. Each transfer requires the entire DREQ-
HOLD-HLDA-DACK handshake cycle. Figure 18
shows the timing of the Single Transfer Mode cy-
cles.
BLOCK TRANSFER MODE
In the Block Transfer Mode, the DMA process is ini-
tiated by a DMA request and continues until the Byte
count expires, or until EOP is activated by the Re-
quester. The DREQn signal need only be held active
until the first Requester access. Only a refresh cycle
will interrupt the block transfer process.
Figure 19 illustrates the operation of the DMA during
the Block Transfer Mode. Figure 20 shows the tim-
ing of the handshake signals during Block Mode
Transfers.
271070–18
Figure 17. Buffer Transfer in
Single Transfer Mode
271070–19
Figure 18. DMA Single Transfer Mode
27
M82380
DEMAND TRANSFER MODE
The Demand Transfer Mode provides the most flex-
ible handshaking procedures during the DMA pro-
cess. A Demand Transfer is initiated by a DMA re-
quest. The process continues until the Byte Count
expires, or an external EOP is encountered. If the
device being serviced (Requester) desires, it can in-
terrupt the DMA process by de-activating the
DREQn line. Action is taken on the condition of
DREQn during Requester accesses only. The ac-
cess during which DREQn is sampled inactive is the
last Requester access which will be performed dur-
ing the current transfer. Figure 21 shows the flow of
events during the transfer of a buffer in the Demand
Mode.
271070–20
Figure 19. Buffer Transfer in
Block Transfer Mode
271070–21
Figure 20. Block Mode Transfers
28
M82380
The Requester can restart the transfer process by
reasserting DREQn. The M82380 will arbitrate the
request with other pending requests and begin the
process where it left off. Figure 22 shows the timing
of handshake signals during Demand Transfer Mode
operation.
Using the Demand Transfer Mode allows peripherals
to access memory in small, irregular bursts without
wasting bus control time. The M82380 is designed to
give the best possible bus control latency in the De-
mand Transfer Mode. Bus control latency is defined
here as the time from the last active bus cycle of the
previous bus master to the first active bus cycle of
the new bus master. The M82380 DMA Controller
will perform its first bus access cycle two bus states
after HLDA goes active. In the typical configuration,
bus control is returned to the host one bus state
after the DREQn goes inactive.
271070–22
There are two cases where there may be more than
one bus state of bus control latency at the end of a
transfer. The first is at the end of an Auto-Initialize
process, and the second is at the end of a process
where the source is the Requester and Two-Cycle
transfers are used.
Figure 21. Buffer Transfer in
Demand Transfer Mode
When the DREQn line goes inactive, the DMA con-
troller will complete the current transfer, including
any necessary accesses to the Target, and relin-
quish control of the bus to the host. The current pro-
cess information is saved (byte count, Requester
and Target addresses, and Temporary Register).
When a Buffer Auto-Initialize Process is complete,
the M82380 requires seven bus states to reload the
271070–23
Figure 22. Demand Mode Transfers
29
M82380
Current Registers from the Base Registers of the
Auto-Initialized channel. The reloading is done while
the M82380 is still the bus master so that it is pre-
pared to service the channel immediately after relin-
quishing the bus, if necessary.
after the mode switch are determined by the current
setting of the Programmable Priority.
Programmable Priority is available for fixing the prior-
ity of the DMA channels within a group to levels oth-
er than the default. Through a software command,
the channel to have the lowest priority in a group
can be specified. Each of the two groups of four
channels can have the priority fixed in this way. The
other channels in the group will follow the natural
Fixed Priority sequence. This mode affects only the
priority levels while operating with Fixed Priority.
In the case where the Requester is the source, and
Two-Cycle transfers are being used, there are two
extra idle states at the end of the transfer process.
This occurs due to housekeeping in the DMA’s inter-
nal pipeline. These two idle states are present only
after the very last Requester access, before the
DMA Controller de-activates the HOLD signal.
For example, if channel 2 is programmed to have the
lowest priority in its group, channel 3 has the highest
priority. In descending order, the other channels
would have the following priority: (3, 0, 1, 2), 4, 5, 6,
7 (channel 2 lowest, channel 3 highest). If the upper
group were programmed to have channel 5 as the
lowest priority channel, the priority would be (again,
highest to lowest): 6, 7, (3, 0, 1, 2), 4, 5. Figure 24
shows this example pictorially. The lower group is
always prioritized as a fifth channel of the upper
group (between channels 4 and 7).
3.3.4 CHANNEL PRIORITY ARBITRATION
DMA channel priority can be programmed into one
of two arbitration methods: Fixed or Rotating. The
four lower DMA channels and the four upper DMA
channels operate as if they were two separate DMA
controllers operating in cascade. The lower group of
four channels (0–3) is always prioritized between
channels 7 and 4 of the upper group of channels (4–
7). Figure 23 shows a pictorial representation of the
priority grouping.
High Priority
The priority can thus be set up as rotating for one
group of channels and fixed for the other, or any
other combination. While in Fixed Priority, the pro-
grammer can also specify which channel has the
lowest priority.
Low Priority
271070–25
Figure 24. Example of Programmed Priority
The DMA Controller will only accept Programmable
Priority commands while the addressed group is op-
erating in Fixed Priority. Switching from Fixed to Ro-
tating Priority preserves the current priority levels.
Switching from Rotating to Fixed Priority returns the
priority levels to those which were last programmed
by use of Programmable Priority.
Rotating Priority allows the devices using DMA to
share the system bus more evenly. An individual
channel does not retain highest priority after being
serviced, priority is passed to the next highest priori-
ty channel in the group. The channel which was
most recently serviced inherits the lowest priority.
This rotation occurs each time a channel is serviced.
Figure 25 shows the sequence of events as priority
is passed between channels. Note that the lower
group rotates within the upper group, and that serv-
icing a channel within the lower group causes rota-
tion within the group as well as rotation of the upper
group.
271070–24
Figure 23. DMA Priority Grouping
The M82380 DMA Controller defaults to Fixed Priori-
ty. Channel 0 has the highest priority, then 1, 2, 3, 4,
5, 6, 7. Channel 7 has the lowest priority. Any time
the DMA Controller arbitrates DMA requests, the re-
questing channel with the highest priority will be
serviced next.
Fixed Priority can be entered into at any time by a
software command. The priority levels in effect
30
M82380
0
1
2
3
4
5
6
7
Ðdefault (highest to lowest)
DREQ2 and DREQ6Ðprocess channel 2
4
5
6
7
3
0
1
2
Ðchannel 2 drops to lowest priority within group.
Lower group drops to lowest priority within upper group.
2(Double Rotation)
DREQ6 (still) and DREQ7Ðprocess channel 6
Ðchannel 6 drops to lowest priority within group
DREQ7 (still) and DREQ0Ðprocess channel 7
Ðchannel 7 drops to lowest priority within group
DREQ0 (still) and DREQ1Ðprocess channel 0
Ðchannel 0 drops to lowest priority within group (Double Rotation)
7
3
0
1
2
4
5
6
3
0
1
2
4
5
6
7
4
5
6
7
1
2
3
0
DREQ1 (still)Ðprocess channel 1
4
5
6
7
2
3
0
1
Ðchannel 1 drops to lowest priority within group
Figure 25. Rotating Channel Priority.
Lower and Upper groups are programmed for the Rotating Priority Mode.
31
M82380
ity modes between the two groups of channels:
Fixed Priority only (default), Fixed Priority upper
group/Rotating Priority lower group, Rotating Priority
upper group/Fixed Priority lower group, and Rotating
Priority only. Figure 26 illustrates the operation of the
two combined priority methods.
3.3.5 COMBINING PRIORITY MODES
Since the DMA Controller operates as two four-
channel controllers in cascade, the overall priority
scheme of all eight channels can take on a variety of
forms. There are four possible combinations of prior-
High
Low
0
1
5
2
6
3
7
4
0
5
1
6
7
3
ÐDefault priority
High
Low
4
2
After servicing channel 2
ÐAfter servicing channel 6
ÐAfter servicing channel 1
High
Low
7
0
1
2
3
4
5
6
High
Low
4
5
6
7
0
1
2
3
CASE 1 0–3 Fixed Priority, 4–7 Rotating Priority
High
Low
0
1
0
0
3
2
1
1
0
3
2
2
1
4
4
4
4
5
5
5
5
6
6
6
6
7
Default priority
High
Low
3
7
After servicing channel 2
After servicing channel 6
After servicing channel 1
High
Low
3
7
High
Low
2
7
CASE 2 0–3 Rotating Priority, 4–7 Fixed Priority
Figure 26. Combining Priority Modes
32
M82380
If the addresses of the data being transferred are
not word or doubleword aligned, the M82380 will
recognize the situation and read and write the data
in groups of bytes, placing them always at the proper
destination. This process of collecting the desired
bytes and putting them together is called ‘byte as-
sembly’. The reverse process (reading from aligned
locations and writing to non-aligned locations) is
called ‘byte disassembly’.
3.3.6 BUS OPERATION
Data may be transferred by the DMA Controller us-
ing two different bus cycle operations: Fly-By (one-
cycle) and Two-Cycle. These bus handshake meth-
ods are selectable independently for each channel
through
a command register. Device data path
widths are independently programmable for both
Target and Requester. Also selectable through soft-
ware is the direction of data transfer. All of these
parameters affect the operation of the M82380 on a
bus-cycle by bus-cycle basis.
The assembly/disassembly process takes place
transparent to the software, but can only be done
while using the Two-Cycle transfer method. The
M82380 will always perform the assembly/disas-
sembly process as necessary for the current data
transfer. Any data path widths for either the Re-
quester or Target can be used in the Two-Cycle
Mode. This is very convenient for interfacing existing
8- and 16-bit peripherals to the i386 processor’s
32-bit bus.
FLY-BY TRANSFERS
The Fly-By Transfer Mode is the fastest and most
efficient way to use the M82380 DMA Controller to
transfer data. In this method of transfer, the data is
written to the destination device at the same time it
is read from the source. Only one bus cycle is used
to accomplish the transfer.
The M82380 DMA Controller always attempts to fill
the Temporary Register from the source before writ-
ing any data to the destination. If the process is ter-
minated before the Temporary Register is filled (TC
or EOP), the M82380 will write the partial data to the
destination. If a process is temporarily suspended
(such as when DREQn is de-activated during a de-
mand transfer), the contents of a partially filled Tem-
porary Register will be stored within the M82380 un-
til the process is restarted.
In the Fly-By Mode, the DMA acknowledge signal is
used to select the Requester. The DMA Controller
simultaneously places the address of the Target on
the address bus. The state of M/IO and W/R during
the Fly-By transfer cycle indicate the type of Target
and whether the target is being written to or read
from. The Target’s Bus Size is used as an incremen-
ter for the Byte Count. The Requester address regis-
ters are ignored during Fly-By transfers.
For example, if the source is specified as an 8-bit
device and the destination as a 32-bit device, there
will be four reads as necessary from the 8-bit source
to fill the Temporary Register. Then the M82380 will
write the 32-bit contents to the destination. This cy-
cle will repeat until the process is terminated or sus-
pended.
Note that memory-to-memory transfers cannot be
done using the Fly-By Mode. Only one memory or
I/O address is generated by the DMA Controller at a
time during Fly-By transfers. Only one of the devices
being accessed can be selected by an address.
Also, the Fly-By method of data transfer limits the
hardware to accesses of devices with the same data
bus width. The Temporary Registers are not affect-
ed in the Fly-By Mode.
Note that for a Single-Cycle transfer mode of opera-
tion, the internal circuitry of the DMA Controller actu-
ally executes single transfers by removing the DREQ
from the internal arbitration. Thus single transfers
from an 8-bit requester to a 32-bit target will consist
of four complete and independent 8-bit requester cy-
cles, between which bus control is released and re-
requested. Finally, the 32-bit data will be transferred
to the target device from the temporary register be-
fore the fifth requester cycle.
Fly-By transfers also require that the data paths of
the Target and Requester be directly connected.
This requires that successive Fly-By accesses be to
doubleword boundaries, or that the Requester be
capable of switching its connections to the data bus.
TWO-CYCLE TRANSFERS
Two-Cycle transfers can also be performed by the
M82380 DMA Controller. These transfers require at
least two bus cycles to execute. The data being
transferred is read into the DMA Controller’s Tempo-
rary Register during the first bus cycle(s). The sec-
ond bus cycle is used to write the data from the
Temporary Register to the destination.
With Two-Cycle transfers, the devices that the
M82380 accesses can reside at any address within
I/O or memory space. The device must be able to
decode the byte-enables (BEn). Also, if the device
cannot accept data in byte quantities, the program-
mer must take care not to allow the DMA Controller
to access the device on any address other than the
device boundary.
33
M82380
starts when the Requester asserts a DREQn (or
DMA service is requested by software). Figure 28
shows the timing of the sequence of events follow-
ing a DMA request. This sequence is executed for
each channel that is activated. The DREQn signal
can be replaced by a software DMA channel request
with no change in the sequence.
DATA PATH WIDTH AND DATA TRANSFER
RATE CONSIDERATIONS
The number of bus cycles used to transfer a single
‘word’ of data is affected by whether the Two-Cycle
or the Fly-By (Single-Cycle) transfer method is used.
The number of bus cycles used to transfer data di-
rectly affects the data transfer rate. Inefficient use of
bus cycles will decrease the effective data transfer
rate that can be obtained. Generally, the data trans-
fer rate is halved by using Two-Cycle transfers in-
stead of Fly-By transfers.
The choice of data path widths of both Target and
Requester affects the data transfer rate also. During
each bus cycle, the largest pieces of data possible
should be transferred.
The data path width of the devices to be accessed
must be programmed into the DMA controller. The
M82380 defaults after reset to 8-bit-to-8-bit data
transfers, but the Target and Requester can have
different data path widths, independent of each oth-
er and independent of the other channels. Since this
is a software programmable function, more discus-
sion of the uses of this feature are found in the sec-
tion on programming.
READ, WRITE, AND VERIFY CYCLES
Three different bus cycle types may be used in a
data transfer. They are the Read, Write, and Verify
cycles. These cycle types dictate the way in which
the M82380 operates on the data to be transferred.
271070–26
Figure 27. Bus Arbitration and DMA Sequence
A Read Cycle transfers data from the Target to the
Requester. A Write Cycle transfers data from the
Requester to the target. In a Fly-By transfer, the ad-
dress and bus status signals indicate the access
(read or write) to the Target; the access to the Re-
quester is assumed to be the opposite.
After the Requester asserts the service request, the
M82380 will request control of the bus via the HOLD
signal. The M82380 will always assert the HOLD sig-
nal one bus state after the service request is assert-
ed. The i386 processor responds by asserting the
HLDA signal, thus releasing control of the bus to the
M82380 DMA Controller.
The Verify Cycle is used to perform a data read only.
No write access is indicated or assumed in a Verify
Cycle. The Verify Cycle is useful for validating block
fill operations. An external comparator must be pro-
vided to do any comparisons on the data read.
Priority of pending DMA service requests is arbitrat-
ed during the first state after HLDA is asserted by
the i386 processor. The next state will be the begin-
ning of the first transfer access of the highest priority
process.
3.4 Bus Arbitration and Handshaking
Figure 27 shows the flow of events in the DMA re-
quest arbitration process. The arbitration sequence
34
M82380
When the M82380 DMA Controller is finished with its
current bus activity, it returns control of the bus to
the host processor. This is done by driving the
HOLD signal inactive. The M82380 does not drive
any address or data bus signals after HOLD goes
low. It enters the Slave Mode until another DMA pro-
cess is requested. The processor acknowledges
that it has regained control of the bus by forcing the
HLDA signal inactive. Note that the M82380’s DMA
Controller will not re-request control of the bus until
the entire HOLD/HLDA handshake sequence is
complete.
An expired byte count indicates that the current pro-
cess is complete as programmed and the channel
has no further transfers to process. The channel
must be restarted according to the currently pro-
grammed Buffer Transfer Mode, or reprogrammed
completely, including a new Buffer Transfer Mode.
If the peripheral activates the EOP signal, it is indi-
cating that it will not accept or deliver any more data
for the current buffer. The M82380 DMA Controller
considers this as a completion of the channel’s cur-
rent process and interprets the condition the same
way as if the byte count expired.
The M82380 DMA Controller will terminate a current
DMA process for one of three reasons: expired byte
count, end-of-process command (EOP activated)
from a peripheral, or de-activated DMA request sig-
nal. In each case, the controller will de-assert HOLD
immediately after completing the data transfer in
progress. These three methods of process termina-
tion are illustrated in Figures 29, 32, and 31, respec-
tively.
The action taken by the M82380 DMA Controller in
response to a de-activated DREQn signal depends
on the Data Transfer Mode of the channel. In the
Demand Mode, data transfers will take place as long
as the DREQn is active and the byte count has not
expired. In the Block Mode, the controller will com-
plete the entire block transfer without relinquishing
271070–27
NOTE:
Channel priority resolution takes place during the bus state before HLDA is asserted, allowing the DMA Controller to
respond to HLDA without extra idle bus states.
Figure 28. Beginning of a DMA Process
35
M82380
the bus, even if DREQn goes inactive before the
transfer is complete. In the Single Mode, the control-
ler will execute single data transfers, relinquishing
the bus between each transfer, as long as DREQn is
active.
in Figure 29. The condition of DREQn is ignored until
after the process is terminated. If the channel is pro-
grammed to auto-initialize, HOLD will be held active
for an additional seven clock cycles while the auto-
initialization takes place.
Normal termination of a DMA process due to expira-
tion of the byte count (Terminal Count-TC) is shown
Table 6 shows the DMA channel activity due to EOP
or Byte Count expiring (Terminal Count).
Table 6. DMA Channel Activity Due to Terminal Count or External EOP
Single
Auto-
Chaining-
Buffer Process:
or Chaining-
Base Empty
Initialize
Base Loaded
Event
Terminal Count
EOP Input
True
X
X
0
True
X
X
0
True
X
X
0
Results
Current Registers
Channel Mask
EOP Output
Ð
Set
0
Ð
Set
X
Load
Ð
Load
Ð
Load
Ð
Load
Ð
0
X
1
X
Terminal Count Status
Software Request
Set
CLR
Set
CLR
Set
CLR
Set
CLR
Ð
Ð
Ð
Ð
271070–28
Figure 29. Termination of a DMA Process Due to Expiration of Current Byte Count
36
M82380
The M82380 always relinquishes control of the bus
between channel services. This allows the hardware
designer the flexibility to externally arbitrate bus hold
requests, if desired. If another DMA request is pend-
ing when a higher priority channel service is com-
pleted, the M82380 will relinquish the bus until the
hold acknowledge is inactive. One bus state after
the HLDA signal goes inactive, the M82380 will as-
sert HOLD again. This is illustrated in Figure 30.
The timing relationships of the DREQn and EOP sig-
nals to the termination of a DMA transfer are shown
in Figures 31 and 32. Figure 31 shows the termina-
tion of a DMA transfer due to inactive DREQn. Fig-
ure 32 shows the termination of a DMA process due
to an active EOP input.
In the Synchronous Mode, DREQn and EOP are
sampled at the end of the last state of every Re-
quester data transfer cycle. If EOP is active or
DREQn is inactive at this time, the M82380 recog-
nizes this access to the Requester as the last trans-
fer. At this point, the M82380 completes the transfer
in progress, if necessary, and returns bus control to
the host.
3.4.1 SYNCHRONOUS AND ASYNCHRONOUS
SAMPLING OF DREQn AND EOP
As an indicator that a DMA service is to be started,
DREQn is always sampled asynchronously. It is
sampled at the beginning of a bus state and acted
upon at the end of the state. Figure 28 illustrates the
start of a DMA process due to a DREQn input.
In the asynchronous mode, the inputs are sampled
at the beginning of every state of a Requester ac-
cess. The M82380 waits until the end of the state to
act on the input.
The DREQn and EOP inputs can be programmed to
be sampled either synchronously or asynchronously
to signal the end of a transfer.
DREQn and EOP are sampled at the latest possible
time when the M82380 can determine if another
transfer is required. In the Synchronous Mode,
DREQn and EOP are sampled on the trailing edge of
the last bus state before another data access cycle
begins. The Asynchronous Mode requires that the
signals be valid one clock cycle earlier.
The synchronous mode affords the Requester one
bus state of extra time to react to an access. This
means the Requester can terminate a process on
the current access, without losing any data. The
asynchronous mode requires that the input signal be
presented prior to the beginning of the last state of
the Requester access.
271070–29
Figure 30. Switching between Active DMA Channels
37
M82380
271070–30
Figure 31. Termination of a DMA Process Due to De-Asserting DREQn
271070–31
Figure 32. Termination of a DMA Process Due to an External EOP
38
M82380
While in the Pipeline Mode, if the NA signal is sam-
pled active during a transfer, the end of the state
where NA was sampled active is when the M82380
decides whether to commit to another transfer. The
device must de-assert DREQn or assert EOP before
NA is asserted, otherwise the M82380 will commit to
another, possibly undesired, transfer.
through the first bus state of a transfer, and the
Asynchronous Mode requires that DREQn be active
before the end of the state, the peripheral being ac-
cessed is required to present DREQn only a few
nanoseconds after the control information is avail-
able. This means that the peripheral’s control logic
must be extremely fast (practically non-causal). An
alternative is the Synchronous Mode.
Synchronous DREQn and EOP sampling allows the
peripheral to prevent the next transfer from occur-
ring by de-activating DREQn or asserting EOP dur-
ing the current Requester access, before the
M82380 DMA Controller commits itself to another
transfer. The DMA Controller will not perform the
next transfer if it has not already begun the bus cy-
cle. Asynchronous sampling allows less stringent
timing requirements than the Synchronous Mode,
but requires that the DREQn signal be valid at the
beginning of the next to last bus state of the current
Requester access.
3.4.2 ARBITRATION OF CASCADED MASTER
REQUESTS
The Cascade Mode allows another DMA-type de-
vice to share the bus by arbitrating its bus accesses
with the M82380’s. Seven of the eight DMA chan-
nels (0–3 and 5–7) can be connected to a cascaded
device. The cascaded device requests bus control
through the DREQn line of the channel which is pro-
grammed to operate in Cascade Mode. Bus hold ac-
knowledge is signaled to the cascaded device
through the EDACK lines. When the EDACK lines
are active with the code for the requested cascade
channel, the bus is available to the cascaded master
device.
Using the Asynchronous Mode with zero wait states
can be very difficult. Since the addresses and con-
trol signals are driven by the M82380 near half-way
271070–32
Figure 33. Cascaded Bus Master
39
M82380
A Cascade cycle begins the same way a regular
DMA cycle begins. The requesting bus master as-
serts the DREQn line on the M82380. This bus con-
trol request arbitrated as any other DMA request
would be. If any channel receives a DMA request,
the M82380 requests control of the bus. When the
host acknowledges that it has released bus control,
the M82380 acknowledges to the requesting master
that it may access the bus. The M82380 enters an
idle state until the new master relinquishes control.
is for the cascaded master to drop the DREQn sig-
nal. Figure 34 shows the two cascade cycle termina-
tion sequences.
The Refresh Controller may interrupt the cascaded
master to perform a refresh cycle. If this occurs, the
M82380 DMA Controller will de-assert the EDACK
signal (hold acknowledge to cascaded master) and
wait for the cascaded master to remove its hold re-
quest. When the M82380 regains bus control, it will
perform the refresh cycle in its normal fashion. After
the refresh cycle has been completed, and if the
cascaded device has re-asserted its request, the
M82380 will return control to the cascaded master
which was interrupted.
A cascade cycle will be terminated by one of two
events: DREQn going inactive, or HLDA going inac-
tive. The normal way to terminate the cascade cycle
271070–33
Cascade cycle termination by DREQn inactive
271070–34
Cascade cycle termination by HLDA inactive
Figure 34. Cascade Cycle Termination
40
M82380
The M82380 assumes that it is the only device moni-
toring the HLDA signal. If the system designer
wishes to place other devices on the bus as bus
masters, the HLDA from the processor must be in-
tercepted before presenting it to the M82380. Using
the Cascade capability of the M82380 DMA Control-
ler offers a much better solution.
Table 7. DMA Controller Registers
Register Name Access
Control/Status RegisterÐOne Each Per
Group
Command Register I
Command Register II
Mode Register I
Write Only
Write Only
Write Only
Write Only
Read/Write
Write Only
Read/Write
Read Only
Write Only
Read/Write
3.4.3 ARBITRATION OF REFRESH REQUESTS
Mode Register II
Software Request Register
Mask Set-Reset Register
Mask Read-Write Register
Status Register
The arbitration of refresh requests by the DRAM Re-
fresh Controller is slightly different from normal DMA
channel request arbitration. The M82380 DRAM Re-
fresh Controller always has the highest priority of
any DMA process. It also can interrupt a process in
progress. Two types of processes in progress may
be encountered: normal DMA, and bus master cas-
cade.
Bus Size Register
Chaining Register
Channel RegistersÐOne Each Per Channel
Base Target Address
Current Target Address
Base Requester Address
Current Requester Address
Base Byte Count
Write Only
Read Only
Write Only
Read Only
Write Only
Read Only
In the event of a refresh request during a normal
DMA process, the DMA Controller will complete the
data transfer in progress and then execute the re-
fresh cycle before continuing with the current DMA
process. The priority of the interrupted process is
not lost. If the data transfer cycle interrupted by the
Refresh Controller is the last of a DMA process, the
refresh cycle will always be executed before control
of the bus is transferred back to the host.
Current Byte Count
3.5.1 CONTROL/STATUS REGISTERS
The following registers are available to the host
processor for programming the M82380 DMA Con-
troller into its various modes and for checking the
operating status of the DMA processes. Each set of
four DMA channels has one of each of these regis-
ters associated with it.
When the Refresh Controller request occurs during
a cascade cycle, the Refresh Controller must be as-
sured that the cascaded master device has relin-
quished control of the bus before it can execute the
refresh cycle. To do this, the DMA Controller drops
the EDACK signal to the cascaded master and waits
for the corresponding DREQn input to go inactive.
By dropping the DREQn signal, the cascaded mas-
ter relinquishes the bus. The Refresh Controller then
performs the refresh cycle. Control of the bus is re-
turned to the cascaded master if DREQn returns to
an active state before the end of the refresh cycle,
otherwise control is passed to the processor and the
cascaded master loses its priority.
Command Register I
Enables or disables the DMA channels as a group.
Sets the Priority Mode (Fixed or Rotating) of the
group. This write-only register is cleared by a hard-
ware reset, defaulting to all channels enabled and
Fixed Priority Mode.
Command Register II
3.5 DMA Controller Register Overview
Sets the sampling mode of the DREQn and EOP
inputs. Also sets the lowest priority channel for the
group in the Fixed Priority Mode. The functions pro-
grammed through Command Register II default after
a hardware reset to: asynchronous DREQn and
EOP, and channels 3 and 7 lowest priority.
The M82380 DMA Controller contains 44 registers
which are accessable to the host processor. Twen-
ty-four of these registers contain the device ad-
dresses and data counts for the individual DMA
channels (three per channel). The remaining regis-
ters are control and status registers for initiating and
monitoring the operation of the M82380 DMA Con-
troller. Table 7 lists the DMA Controller’s registers
and their accessability.
Mode Register I
Mode Register I programs the following functions for
an individually selected channel:
41
M82380
Type of TransferÐread, write, verify
The mask bits of a group may be cleared in one step
by executing the Clear Mask Command. See the
DMA Programming section for details. A hardware
reset sets all of the channel mask bits, disabling all
channels.
AutoÐInitializeÐenable or disable
Target Address CountÐincrement or
decrement
Data Transfer ModeÐdemand, single, block,
cascade
Status Register
Mode Register I functions default to the following
after reset: verify transfer, Auto-Initialize disabled, In-
crement Target address, Demand Mode.
The Status register is a read-only register which con-
tains the Terminal Count (TC) and Service Request
status for a group. Four bits indicate the TC status
and four bits indicate the hardware request status
for the four channels in the group. The TC bits are
set when the Byte Count expires, or when an exter-
nal EOP is asserted. These bits are cleared by read-
ing from the Status Register. The Service Request
bit for a channel indicates when there is a hardware
DMA request (DREQn) asserted for that channel.
When the request has been removed, the bit is
cleared.
Mode Register II
Programs the following functions for an individually
selected channel:
Target Address HoldÐenable or disable
Requester Address CountÐincrement
or decrement
Requester Address HoldÐenable or disable
Target Device TypeÐI/O or Memory
Requester Device TypeÐI/O or Memory
Transfer CyclesÐTwo-Cycle or Fly-By
Bus Size Register
This write-only register is used to define the bus size
of the Target and Requester of a selected channel.
The bus sizes programmed will be used to dictate
the sizes of the data paths accessed when the DMA
channel is active. The values programmed into this
register affect the operation of the Temporary Regis-
ter. Any byte-assembly required to make the trans-
fers using the specified data path widths will be done
in the Temporary Register. The Bus Size register of
the Target is used as an increment/decrement value
for the Byte Counter and Target Address when in
the Fly-By Mode. Upon reset, all channels default to
8-bit Targets and 8-bit Requesters.
Mode Register II functions are defined as follows
after a hardware reset: Disable Target Address Hold,
Increment Requester Address, Target (and Re-
quester) in memory, Fly-By Transfer Cycles. Note:
Requester Device Type ignored in Fly-By Transfers.
Software Request Register
The DMA Controller can respond to service requests
which are initiated by software. Each channel has an
internal request status bit associated with it. The
host processor can write to this register to set or
reset the request bit of a selected channel.
Chaining Register
The status of the group’s software DMA service re-
quests can be read from this register as well. Each
request bit is cleared upon Terminal Count or exter-
nal EOP.
As a command or write register, the Chaining regis-
ter is used to enable or disable the Chaining Mode
for a selected channel. Chaining can either be dis-
abled or enabled for an individual channel, indepen-
dently of the Chaining Mode status of other chan-
nels. After a hardware reset, all channels default to
Chaining disabled.
The software DMA requests are non-maskable and
subject to priority arbitration with all other software
and hardware requests. The entire register is
cleared by a hardware reset.
When read by the host, the Chaining Register pro-
vides the status of the Chaining Interrupt of each of
the channels. These interrupt status bits are cleared
when the new buffer information has been loaded.
Mask Registers
Each channel has associated with it a mask bit
which can be set/reset to disable/enable that chan-
nel. Two methods are available for setting and clear-
ing the mask bits. The Mask Set/Reset Register is a
write-only register which allows the host to select an
individual channel and either set or reset the mask
bit for that channel only. The Mask Read/Write Reg-
ister is available for reading the mask bit status and
for writing mask bits in groups of four.
3.5.2 CHANNEL REGISTERS
Each channel has three individually programmable
registers necessary for the DMA process; they are
the Base Byte Count, Base Target Address, and
Base Requester Address registers. The 24-bit Base
42
M82380
Byte Count register contains the number of bytes to
be transferred by the channel. The 32-bit Base Tar-
get Address Register contains the beginning ad-
dress (memory or I/O) of the Target device. The 32-
bit Base Requester Address register contains the
base address (memory or I/O) of the device which is
to request DMA service.
3.5.3 TEMPORARY REGISTERS
Each channel has a 32-bit Temporary Register used
for temporary data storage during two-cycle DMA
transfers. It is this register in which any necessary
byte assembly and disassembly of non-aligned data
is performed. Figure 35 shows how a block of data
will be moved between memory locations with differ-
ent boundaries. Note that the order of the data does
not change.
Three more registers for each DMA channel exist
within the DMA Controller which are directly related
to the registers mentioned above. These registers
contain the current status of the DMA process. They
are the Current Byte Count register, the Current Tar-
get Address, and the Current Requester Address. It
is these registers which are manipulated (increment-
ed, decremented, or held constant) by the M82380
DMA Controller during the DMA process. The Cur-
rent registers are loaded from the Base registers.
SOURCE
20H
DESTINATION
50H
A
B
C
D
E
F
21H
22H
23H
24H
25H
26H
27H
51H
52H
53H
54H
55H
56H
57H
58H
59H
5AH
A
B
C
D
E
F
The Base registers are loaded when the host proc-
essor writes to the respective channel register ad-
dresses. Depending on the mode in which the chan-
nel is operating, the Current registers are typically
loaded in the same operation. Reading from the
channel register addresses yields the contents of
the corresponding Current register.
G
G
To maintain compatibility with software which ac-
cesses an 8237A, a Byte Pointer Flip-Flop is used to
control access to the upper and lower bytes of some
words of the Channel Registers. These words are
accessed as byte pairs at single port addresses. The
Byte Pointer Flip-Flop acts as a one-bit pointer
which is toggled each time a qualifying Channel
Register byte is accessed. It always points to the
next logical byte to be accessed of a pair of bytes.
e
e
Target
source
e
e
00000020H
e
00000053H
Requester
Byte Count
destination
000006H
Figure 35. Transfer of Data between Memory
Locations with Different Boundaries. This will be
the result, independent of data path width.
If the destination is the Requester and an early pro-
cess termination has been indicated by the EOP sig-
nal or DREQn inactive in the Demand Mode, the
Temporary Register is not affected. If data remains
in the Temporary Register due to differences in data
path widths of the Target and Requester, it will not
be transferred or otherwise lost, but will be stored for
later transfer.
The Channel registers are arranged as pairs of
words, each pair with its own port address. Address-
ing the port with the Byte Pointer Flip-Flop reset ac-
cesses the least significant byte of the pair. The
most significant byte is accessed when the Byte
Pointer is set.
For compatibility with existing 8237A designs, there
is one exception to the above statements about the
Byte Pointer Flip-Flop. The third byte (bits 16–23) of
the Target Address is accessed through its own port
address. The Byte Pointer Flip-Flop is not affected
by any accesses to this byte.
If the destination is the Target and the EOP signal is
sensed active during the Requester access of a
transfer, the DMA Controller will complete the trans-
fer by sending to the Target whatever information is
in the Temporary Register at the time of process
termination. This implies that the Target could be
accessed with partial data. For this reason it is ad-
visable to have an I/O device designated as a Re-
quester, unless it is capable of handling partial data
transfers.
The upper eight bits of the Byte Count Register are
cleared when the least significant byte of the regis-
ter is loaded. This provides compatibility with soft-
ware which accesses an 8237A. The 8237A has
16-bit Byte Count Registers.
43
M82380
Register is always changed and must be repro-
grammed. A Target or Requester Address Register
which is incremented or decremented should be re-
programmed also.
3.6 DMA Controller Programming
Programming a DMA Channel to perform a needed
DMA function is in general a four step process. First
the global attributes of the DMA Controller are pro-
grammed via the two Command Registers. These
global attributes include: priority levels, channel
group enables, priority mode, and DREQn/EOP in-
put sampling.
3.6.1 BUFFER PROCESSES
The Buffer Process is determined by the Auto-Initial-
ize bit of Mode Register I and the Chaining Register.
If Auto-Initialize is enabled, Chaining should not be
used.
The second step involves setting the operating
modes of the particular channel. The Mode Regis-
ters are used to define the type of transfer and the
handshaking modes. The Bus Size Register and
Chaining Register may also need to be programmed
in this step.
SINGLE BUFFER PROCESS
The Single Buffer Process is programmed by dis-
abling Chaining via the Chaining Register and pro-
gramming Mode Register I for non-Auto-Initialize.
The third step is setting up the channel is to load the
Base Registers in accordance with the needs of the
operating modes chosen in step two. The Current
Registers are automatically loaded from the Base
Registers, if required by the Buffer Transfer Mode in
effect. The information loaded and the order in
which it is loaded depends on the operating mode. A
channel used for cascading, for example, needs no
buffer information and this step can be skipped en-
tirely.
BUFFER AUTO-INITIALIZE PROCESS
Setting the Auto-Initialize bit in Mode Register I is all
that is necessary to place the channel in this mode.
Buffer Auto-Initialize must not be enabled simulta-
neous to enabling the Buffer Chaining Mode as this
will have unpredictable results.
Once the Base Registers are loaded, the channel is
ready to be enabled. The channel will reload its Cur-
rent Registers from the Base Registers each time
the Current Buffer expires, either by an expired Byte
Count or an external EOP.
The last step is to enable the newly programmed
channel using one of the Mask Registers. The chan-
nel is then available to perform the desired data
transfer. The status of the channel can be observed
at any time through the Status Register, Mask Reg-
ister, Chaining Register, and Software Request reg-
ister.
BUFFER CHAINING PROCESS
The Buffer Chaining Process is entered into from the
Single Buffer Process. The Mode Registers should
be programmed first, with all of the Transfer Modes
defined as if the channel were to operate in the Sin-
gle Buffer Process. The channel’s Base and Current
Registers are then loaded. When the channel has
been set up in this way, and the chaining interrupt
service routine is in place, the Chaining Process can
be entered by programming the Chaining Register.
Figure 36 illustrates the Buffer Chaining Process.
Once the channel is programmed and enabled, the
DMA process may be initiated in one of two ways,
either by a hardware DMA request (DREQn) or a
software request (Software Request Register).
Once programmed to a particular Process/Mode
configuration, the channel will operate in that config-
uration until programmed otherwise. For this reason,
restarting a channel after the current buffer expires
does not require complete reprogramming of the
channel. Only those parameters which have
changed need to be reprogrammed. The Byte Count
44
M82380
An interrupt (IRQ1) will be generated immediately af-
ter the Chaining Process is entered, as the channel
then perceives the Base Registers as empty and in
need of reloading. It is important to have the inter-
rupt service routine in place at the time the Chaining
Process is entered into. The interrupt request is re-
moved when the most significant byte of the Base
Target Address is loaded.
Exiting the Chaining Process can be done by reset-
ting the Chaining Mode Register. If an interrupt is
pending for the channel when the Chaining Register
is reset, the interrupt request will be removed. The
Chaining Process can be temporarily disabled by
setting the channel’s Mask bit in the Mask Register.
The interrupt service routine for IRQ1 has the re-
sponsibility of reloading the Base Register as neces-
sary. It should check the status of the channel to
determine the cause of channel expiration, etc. It
should also have access to operating system infor-
mation regarding the channel, if any exists. The
IRQ1 service routine should be capable of determin-
ing whether the chain should be continued or termi-
nated and act on that information.
The interrupt will occur again when the first buffer
expires and the Current Registers are loaded from
the Base Registers. The cycle continues until the
Chaining Process is disabled, or the host fails to re-
spond to IRQ1 before the Current Buffer expires.
3.6.2 DATA TRANSFER MODES
The Data Transfer Modes are selected via Mode
Register I. The Demand, Single, and Block Modes
are selected by bits D6 and D7. The individual trans-
fer type (Fly-By vs Two-Cycle, Read-Write-Verify,
and I/O vs Memory) is programmed through both of
the Mode registers.
3.6.3 CASCADED BUS MASTERS
The Cascade Mode is set by writing ones to D7 and
D6 of Mode Register I. When a channel is pro-
grammed to operate in the Cascade Mode, all of the
other modes associated with Mode Registers I and II
are ignored. The priority and DREQn/EOP defini-
tions of the Command Registers will have the same
effect on the channel’s operation as any other
mode.
3.6.4 SOFTWARE COMMANDS
There are five port addresses which, when written
to, command certain operations to be performed by
the M82380 DMA Controller. The data written to
these locations is not of consequence, writing to the
location is all that is necessary to command the
M82380 to perform the indicated function. Following
are descriptions of the command function.
271070–35
Figure 36. Flow of Events in the
Buffer Chaining Process
45
M82380
Clear Byte Pointer Flip-FlopÐlocation 000CH
This command simultaneously clears the Mask Bits
of all channels in the addressed group, enabling all
of the channels in the group.
Resets the Byte Pointer Flip-Flop. This command
should be performed at the beginning of any access
to the channel registers in order to be assured of
beginning at a predictable place in the register pro-
gramming sequence.
Clear TC Interrupt RequestÐlocation 001EH
This command resets the Terminal Count Interrupt
Request Flip-Flop. It is provided to allow the pro-
gram which made a software DMA request to ac-
knowledge that it has responded to the expiration of
the requested channel(s).
Master ClearÐlocation 000DH
All DMA functions are set to their default states. This
command is the equivalent of a hardware reset to
the DMA Controller. Functions other than those in
the DMA Controller section of the M82380 are not
affected by this command.
3.7 Register Definitions
The following diagrams outline the bit definitions and
functions of the M82380 DMA Controller’s Status
and Control Registers. The function and program-
ming of the registers is covered in the previous sec-
tion on DMA Controller Programming. An entry of ‘X’
as a bit value indicates ‘‘don’t care.’’
Clear Mask
Register ÐChannels 0–3Ðlocation 000EH
Channels 4–7Ðlocation 00CEH
(Read Current, Write Base)
Channel Registers
Register Name
Channel
Address
(Hex)
Byte
Bits
Pointer
Accessed
Channel 0
Target Address
00
0
1
x
0–7
8–15
16–23
24–31
0–7
87
10
01
0
0
1
0
0
1
0
1
Byte Count
8–15
16–23
0-7
11
90
Requester Address
8–15
16–23
24–31
91
02
Channel 1
Target Address
0
1
x
0–7
8–15
16–23
24–31
0–7
83
12
03
0
0
1
0
0
1
0
1
Byte Count
8–15
16–23
0-7
13
92
Requester Address
8–15
16–23
24–31
93
46
M82380
(Read Current, Write Base)
Channel Registers
Channel
Register Name
Address
(Hex)
Byte
Bits
Pointer
Accessed
Channel 2
Channel 3
Channel 4
Channel 5
Target Address
04
0
1
x
0–7
8–15
16–23
24–31
0–7
81
14
05
0
0
1
0
0
1
0
1
Byte Count
8–15
16–23
0-7
15
94
Requester Address
8–15
16–23
24–31
95
06
Target Address
0
1
x
0–7
8–15
16–23
24–31
0–7
82
16
07
0
0
1
0
0
1
0
1
Byte Count
8–15
16–23
0-7
17
96
Requester Address
8–15
16–23
24–31
97
Target Address
C0
0
1
x
0–7
8–15
16–23
24–31
0–7
8F
D0
C1
0
0
1
0
0
1
0
1
Byte Count
8–15
16–23
0-7
D1
98
Requester Address
8–15
16–23
24–31
99
Target Address
C2
0
1
x
0–7
8–15
16–23
24–31
0–7
8B
D2
C3
0
0
1
0
0
1
0
1
Byte Count
8–15
16–23
0-7
D3
9A
Requester Address
8–15
16–23
24–31
9B
47
M82380
(Read Current, Write Base)
Address
(Hex)
Channel Registers
Channel
Register Name
Byte
Pointer
Bits
Accessed
Channel 6
Target Address
C4
0
1
x
0–7
8–15
16–23
24–31
0–7
8–15
16–23
0-7
89
D4
C5
0
0
1
0
0
1
0
1
Byte Count
D5
9C
Requester Address
8–15
16–23
24–31
9D
C6
Channel 7
Target Address
0
1
x
0–7
8–15
16–23
24–31
0–7
8–15
16–23
0-7
8A
D6
C7
0
0
1
0
0
1
0
1
Byte Count
D7
9E
Requester Address
8–15
16–23
24–31
9F
Command Register I
(Write Only)
Port AddressÐChannels 0–3Ð0008H
Channels 4–7Ð00C8H
271070–36
Command Register II
(Write Only)
Port AddressesÐChannels 0–3Ð-001AH
Channels 4–7Ð00DAH
271070–37
48
M82380
Mode Register I
(Write Only)
Port AddressesÐChannels 0–3Ð000BH
Channels 4–7Ð00CBH
271070–38
* Target and Requester DECREMENT is allowed only for byte transfers.
Mode Register II
(Write Only)
Port AddressesÐChannels 0–3Ð001BH
Channels 4–7Ð00DBH
271070–39
* Target and Requester DECREMENT is allowed only for byte transfers.
49
M82380
Software Request Register
(Read/Write)
Port AddressesÐChannels 0–3Ð0009H
Channels 4–7Ð00C9H
Write Format:
Software DMA Service Request
271070–40
Read Format:
Software Requests Pending
271070–41
Mask Set/Reset Register
Individual Channel Mask (Write Only)
Port AddressesÐChannels 0–3Ð000AH
Channels 4–7Ð00CAH
271070–42
50
M82380
Mask Read/Write Register
Group Channel Mask (Read/Write)
Port AddressesÐChannels 0–3Ð000FH
Channels 4–7Ð00CFH
271070–43
Status Register
Channel Process Status (Read Only)
Port AddressesÐChannels 0–3Ð0008H
Channels 4–7Ð00C8H
271070–44
Bus Size Register
Set Data Path Width (Write Only)
Port AddressesÐChannels 0–3Ð0018H
Channels 4–7Ð00D8H
271070–45
Bus Size Encoding:
e
e
e
e
00
01
Reserved by Intel 10
32-bit Bus 11
16-bit Bus
8-bit Bus
51
M82380
Chaining Register
(Read/Write)
Port AddressesÐChannels 0–3Ð0019H
Channels 4–7Ð00D9H
Write Format:
Set Chaining Mode
271070–46
Read Format:
Channel Interrupt Status
271070–47
52
M82380
can be individually programmed with its own inter-
rupt vector, allowing more flexibility in interrupt vec-
tor mapping.
4.0 PROGRAMMABLE INTERRUPT
CONTROLLER
4.1 Functional Description
4.1.1 INTERNAL BLOCK DIAGRAM
The M82380 Programmable Interrupt Controller
(PIC) consists of three enhanced M8259A Interrupt
Contollers. These three controllers together provide
15 external and 5 internal interrupt request inputs.
Each external request input can be cascaded with
an additional M8259A slave collector. This scheme
allows the M82380 to support a maximum of 120
(15 x 8) external interrupt request inputs.
The block diagram of the M82380 Programmable In-
terrupt Controller is shown in Figure 37. Internally,
the PIC consists of three M8259A banks: A, B and
C. The three banks are cascaded to one another: C
is cascaded to B, B is cascaded to A. The INT output
of Bank A is used externally to interrupt the i386
processor.
Bank A has nine interrupt request inputs (two are
unused), and Banks B and C have eight interrupt
request inputs. Of the fifteen external interrupt re-
quest inputs, two are shared by other functions. Spe-
cifically, the Interrupt Request 3 input (IRQ3) can be
used as the Timer 2 output (TOUT2). This pin can be
used in three different ways: IRQ3 input only,
TOUT2 output only, or using TOUT2 to generate an
IRQ3 interrupt request. Also, the Interrupt Request 9
input (IRQ9) can be used as DMA Request 4 input
(DREQ4). Typically, only IRQ9 or DREQ4 can be
used at a time.
Following one or more interrupt requests, the
M82380 PIC issues an interrupt signal to the i386
processor. When the i386 host processor responds
with an interrupt acknowledge signal, the PIC will ar-
bitrate between the pending interrupt requests and
place the interrupt vector associated with the high-
est priority pending request on the data bus.
The major enhancement in the M82380 PIC over the
M8259A is that each of the interrupt request inputs
271070–48
NOTE:
Masking IRQ1.5 also masks IRQ2.
Figure 37. Interrupt Controller Block Diagram
53
M82380
Ð The cascade address is provided on the Data
Bus (D0–D7). (In the M8259A, three dedicated
control signals (CAS0, CAS1, CAS2) are used for
master/slave cascading.)
4.1.2 INTERRUPT CONTROLLER BANKS
All three banks are identical, with the exception of
the IRQ1.5 on Bank A. Therefore, only one bank will
be discussed. In the M82380 PIC, all external re-
quests can be cascaded into and each interrupt con-
troller bank behaves like a master. As compared to
the M8259A, the enhancements in the banks are:
The block diagram of a bank is shown in Figure 38.
As can be seen from this figure, the bank consists of
six major blocks: the Interrupt Request Register
(IRR), the In-Service Register (ISR), the Interrupt
Mask Register (IMR), the Priority Resolver (PR), the
Vector Register (VR), and the Control Logic. The
functional description of each block follows.
Ð All interrupt vectors are individually programma-
ble. (In the M8259A, the vectors must be pro-
grammed in eight consecutive interrupt vector lo-
cations.)
271070–49
Figure 38. Interrupt Bank Block Diagram
54
M82380
INTERRUPT REQUEST (IRR) AND IN-SERVICE
REGISTER (ISR)
4.2 Interface Signals
4.2.1 INTERRUPT INPUTS
The interrupts at the Interrupt Request (IRQ) input
lines are handled by two registers in cascade, the
Interrupt Request Register (IRR) and the In-Service
Register (ISR). The IRR is used to store all interrupt
levels which are requesting service; and the ISR is
used to store all interrupt levels which are being
serviced.
There are 15 external Interrupt Request inputs and 5
internal Interrupt Requests. The external request in-
puts are: IRQ3, IRQ9, IRQ11 to IRQ23. They are
shown in bold arrows in Figure 37. All IRQ inputs are
active LOW and they can be programmed (via a con-
trol bit in the Initialization Command Word 1 (ICW1))
to be either edge-triggered or level-triggered. In or-
der to be recognized as a valid interrupt request, the
interrupt input must be active (LOW) until the first
INTA cycle (see Bus Functional Description). Note
that all 15 external Interrupt Request inputs have
weak internal pull-up resistors.
PRIORITY RESOLVER (PR)
This logic block determines the priorities of the bits
set in the IRR. The highest priority is selected and
strobed into the corresponding bit of the ISR during
an Interrupt Acknowledge cycle.
As mentioned earlier, an M8259A can be cascaded
to each external interrupt input to expand the inter-
rupt capacity to a maximum of 120 levels. Also, two
of the interrupt inputs are dual functions: IRQ3 can
be used as Timer 2 output (TOUT2) and IRQ9 can
be used as DREQ4 input. IRQ3 is a bidirectional dual
function pin. This interrupt request input is wired-OR
with the output of Timer 2 (TOUT2). If only IRQ3
function is to be used, Timer 2 should be pro-
grammed so that OUT2 is LOW. Note that TOUT2
can also be used to generate an interrupt request to
IRQ3 input.
INTERRUPT MASK REGISTER (IMR)
The IMR stores the bits which mask the interrupt
lines to be masked (disabled). The IMR operates on
the IRR. Masking of a higher priority input will not
affect the interrupt request lines of lower priority.
VECTOR REGISTERS (VR)
This block contains a set of Vector Registers, one
for each interrupt request line, to store the pre-pro-
grammed interrupt vector number. The correspond-
ing vector number will be driven onto the Data Bus
of the M82380 during the Interrupt Acknowledge cy-
cle.
The five internal interrupt requests serve special
system functions. They are shown in Table 8. The
following paragraphs describe these interrupts.
CONTROL LOGIC
Table 8. M82380 Internal Interrupt Requests
The Control Logic coordinates the overall operations
of the other internal blocks within the same bank.
This logic will drive the Interrupt Output signal (INT)
HIGH when one or more unmasked interrupt inputs
are active (LOW). The INT output signal goes direct-
ly to the i386 processor (in Bank A) or to another
bank to which this bank is cascaded (see Figure 37).
Also, this logic will recognize an Interrupt Acknowl-
edge cycle (via M/IO, D/C and W/R signals). During
this bus cycle, the Control Logic will enable the cor-
responding Vector Register to drive the interrupt
vector onto the Data Bus.
Interrupt Request
Interrupt Source
IRQ0
IRQ8
IRQ1
IRQ4
IRQ1.5
Timer 3 Output (TOUT3)
Timer 0 Output (TOUT0)
DMA Chaining Request
DMA Terminal Count
ICW2 Written
TIMER 0 AND TIMER 3 INTERRUPT REQUESTS
IRQ8 and IRQ0 interrupt requests are initiated by the
output of Timers 0 and 3, respectively. Each of these
requests is generated by an edge-detector flip-flop.
The flip-flops are activated by the following condi-
tions:
In Bank A, the Control Logic is also responsible for
handling the special ICW2 interrupt request input
(IRQ1.5).
SetÐ Rising edge of timer output (TOUT);
ClearÐ Interrupt acknowledge for this request;
OR Request is masked (disabled); OR
Hardware Reset.
55
M82380
CHAINING AND TERMINAL COUNT INTERRUPTS
generate a default vector. This vector corresponds
to the IRQ7 vector in Bank A.
These interrupt requests are generated by the
M82380 DMA Controller. The chaining request
(IRQ1) indicates that the DMA Base Register is not
loaded. The Terminal Count request (IRQ4) indi-
cates that a software DMA request was cleared.
4.2.2 INTERRUPT OUTPUT (INT)
The INT output pin is taken directly from bank A.
This signal should be tied to the Maskable Interrupt
Request (INTR) of the i386 processor. When this
signal is active (HIGH), it indicates that one or more
internal/external interrupt requests are pending. The
i386 processor is expected to respond with an inter-
rupt acknowledge cycle.
ICW2 INTERRUPT REQUEST
Whenever an Initialization Control Word 2 (ICW2) is
written to a Bank, a special ICW2 interrupt request is
generated. The interrupt will be cleared when the
newly programmed ICW2 Register is read. This in-
terrupt request is in Bank A at level 1.5. This inter-
rupt request is internally ORed with the Cascaded
Request from Bank B and is always assigned a high-
er priority than the Cascaded Request.
4.3 Bus Functional Description
The INT output of bank A will be activated as a result
of any unmasked interrupt request. This may be a
non-cascaded or cascaded request. After the PIC
has driven the INT signal HIGH, i386 processor will
respond by performing two interrupt acknowledge
cycles. The timing diagram in Figure 39 shows a typi-
cal interrupt acknowledge process between the
M82380 and the i386 CPU.
This special interrupt is provided to support compati-
bility with the original M8259A. A detailed description
of this interrupt is discussed in the Programming
section.
DEFAULT INTERRUPT
During an Interrupt Acknowledge cycle, if there is no
active pending request, the PIC will automatically
271070–50
NOTE:
What is actually driven on the Data Bus depends on if the current interrupt request is a Slave Request.
INTA Cycle 1
00H
Slave Address
INTA Cycle 2
Vector
High Impedance*
NON-SLAVE REQUEST
SLAVE REQUEST
*Slave will place a vector at this time.
Figure 39. Interrupt Acknowledge Cycle
56
M82380
After activating the INT signal, the M82380 monitors
the status lines (M/IO, D/C, W/R) and waits for the
i386 processor to initiate the first interrupt acknowl-
edge cycle. In the i386 processor environment, two
successive interrupt acknowledge cycles (INTA)
possible configurations are conceivable, giving the
user enough versatility for almost any interrupt con-
trolled application.
This section is not intended to show how the
M82380 PIC can be programmed. Rather, it de-
scribes the operation in different modes.
e
e
e
marked by M/IO
LOW, D/C
LOW, and W/R
LOW are performed. During the first INTA cycle, the
PIC will determine the highest priority request. As-
suming this interrupt input has no external Slave
Controller cascaded to it, the M82380 will drive the
Data Bus with 00H in the first INTA cycle. During the
second INTA cycle, the M82380 PIC will drive the
Data Bus with the corresponding preprogrammed in-
terrupt vector.
4.4.1 END-OF-INTERRUPT
Upon completion of an interrupt service routine, the
interrupted bank needs to be notified so its ISR can
be updated. This allows the PIC to keep track of
which interrupt levels are in the process of being
serviced and their relative priorities. Three different
End-Of-Interrupt (EOI) formats are available. They
are: Non-Specific EOI Command, Specific EOI Com-
mand, and Automatic EOI Mode. Selection of which
EOI to use is dependent upon the interrupt opera-
tions the user wishes to perform.
If the PIC determines (from the ICW3) that this inter-
rupt input has an external Slave Controller cascaded
to it, it will drive the Data Bus with the specific Slave
Cascade Address (instead of 00H) during the first
INTA cycle. This Slave Cascade Address is the pre-
programmed content in the corresponding Vector
Register. This means that no Slave Address should
be chosen to be 00H. Note that the Slave Address
and Interrupt Vector are different interpretations of
the same thing. They are both the contents of the
programmable Vector Register. During the second
INTA cycle, the Data Bus will be floated so that the
external Slave Controller can drive its interrupt vec-
tor on the bus. Since the Slave Interrupt Controller
resides on the system bus, bus transceiver enable
and direction control logic must take this into consid-
eration.
If the M82380 is NOT programmed in the Automatic
EOI Mode, an EOI command must be issued by the
i386 processor to the specific M82380 PIC Control-
ler Bank. Also, if this controller bank is cascaded to
another internal bank, an EOI command must also
be sent to the bank to which this bank is cascaded.
For example, if an interrupt request of Bank C in the
M82380 PIC is serviced, an EOI should be written
into Bank C, Bank B and Bank A. If the request
comes from an external interrupt controller cascad-
ed to Bank C, then an EOI should be written into the
external controller as well.
In order to have a successful interrupt service, the
interrupt request input must be held active (LOW)
until the beginning of the first interrupt acknowledge
cycle. If there is no pending interrupt request when
the first INTA cycle is generated, the PIC will gener-
ate a default vector, which is the IRQ7 vector (bank
A level 7).
NON-SPECIFIC EOI COMMAND
A Non-Specific EOI command sent from the i386
processor lets the M82380 PIC bank know when a
service routine has been completed, without specifi-
cation of its exact interrupt level. The respective in-
terrupt bank automatically determines the interrupt
level and resets the correct bit in the ISR.
According to the Bus Cycle definition of the i386
processor, there will be four Bus Idle States be-
tween the two interrupt acknowledge cycles. These
idle bus cycles will be initiated by the i386 processor.
Also, during each interrupt acknowledge cycle, the
internal Wait State Generator of the M82380 will au-
tomatically generate the required number of wait
states for internal delays.
To take advantage of the Non-Specific EOI, the in-
terrupt bank must be in a mode of operation in which
it can predetermine its in-service routine levels. For
this reason, the Non-Specific EOI command should
only be used when the most recent level acknowl-
edged and serviced is always the highest priority lev-
el (i.e., in the Fully Nested Mode structure to be de-
scribed below). When the interrupt bank receives a
Non-Specific EOI command, it simply resets the
highest priority ISR bit to indicate that the highest
priority routine in service is finished.
4.4 Mode of Operation
A variety of modes and commands are available for
controlling the M82380 PIC. All of them are pro-
grammable; that is, they may be changed dynamical-
ly under software control. In fact, each bank can be
programmed individually to operate in different
modes. With these modes and commands, many
Special consideration should be taken when decid-
ing to use the Non-Specific EOI command. Here are
two operating conditions in which it is best NOT
57
M82380
used since the Fully Nested Mode structure will be
destroyed:
Therefore, when using this mode, the M80386
should keep its interrupt request input disabled dur-
ing execution of a service routine. By doing this,
higher priority interrupt levels will be serviced only
after the completion of a routine in service. This
guideline restores the Fully Nested Mode structure.
However, in this scheme, a routine in service cannot
be interrupted since the host’s interrupt request in-
put is disabled.
Ð Using the Set Priority command within an inter-
rupt service routine.
Ð Using a Special Mask Mode.
These conditions are covered in more detail in their
own sections, but are listed here for reference.
SPECIFIC EOI COMMAND
4.4.2 INTERRUPT PRIORITIES
Unlike a Non-Specific EOI command which automat-
ically resets the highest priority ISR bit, a Specific
EOI command specifies an exact ISR bit to be reset.
Any one of the IRQ levels of an interrupt bank can
be specified in the command.
The M82380 PIC provides various methods for ar-
ranging the interrupt priorities of the interrupt re-
quest inputs to suit different applications. The follow-
ing sub-sections explain these methods in detail.
The Specific EOI command is needed to reset the
ISR bit of a completed service routine whenever the
interrupt bank is not able to automatically determine
it. The Specific EOI command can be used in all
conditions of operation, including those that prohibit
Non-Specific EOI command usage mentioned
above.
FULLY NESTED MODE
The Fully Nested Mode of operation is a general pur-
pose priority mode. This mode supports a multi-level
interrupt structure in which all of the Interrupt Re-
quest (IRQ) inputs within one bank are arranged
from highest to lowest.
AUTOMATIC EOI MODE
Unless otherwise programmed, the Fully Nested
Mode is entered by default upon initialization. At this
When programmed in the Automatic EOI Mode, the
M80386 no longer needs to issue a command to
notify the interrupt bank it has completed an inter-
rupt routine. The interrupt bank accomplishes this by
performing a Non-Specific EOI automatically at the
end of the second INTA cycle.
e
time, IRQ0 is assigned the highest priority (priority
7). This default
e
priority can be changed, as will be explained later in
0) and IRQ7 the lowest (priority
the Rotating Priority Mode.
When an interrupt is acknowledged, the highest pri-
ority request is determined from the Interrupt Re-
quest Register (IRR) and its vector is placed on the
bus. In addition, the corresponding bit in the In-Serv-
ice Register (ISR) is set to designate the routine in
service. This ISR bit will remain set until the M80386
issues an End Of Interrupt (EOI) command immedi-
ately before returning from the service routine; or
alternately, if the Automatic End Of Interrupt (AEOI)
bit is set, the ISR bit will be reset at the end of the
second INTA cycle.
Special consideration should be taken when decid-
ing to use the Automatic EOI Mode because it may
disturb the Fully Nested Mode structure. In the Auto-
matic EOI Mode, the ISR bit of a routine in service is
reset right after it is acknowledged, thus leaving no
designation in the ISR that a service routine is being
executed. If any interrupt request within the same
bank occurs during this time and interrupts are en-
abled, it will get serviced regardless of its priority.
58
M82380
While the ISR bit is set, all further interrupts of the
same or lower priority are inhibited. Higher level in-
terrupts can still generate an interrupt, which will be
acknowledged only if the i386 processor internal in-
terrupt enable flip-flop has been re-enabled (through
software inside the current service routine).
the Automatic EOI mode. These two methods are
discussed below.
ROTATE ON NON-SPECIFIC EOI COMMAND
When the Rotate On Non-Specific EOI command is
issued, the highest ISR bit is reset as in a normal
Non-Specific EOI command. However, after it is re-
set, the corresponding Interrupt Request (IRQ) level
is assigned the lowest priority. Other IRQ priorities
rotate to conform to the Fully Nested Mode based
on the newly assigned low priority.
AUTOMATIC ROTATIONÐEQUAL PRIORITY
DEVICES
Automatic rotation of priorities serves in applications
where the interrupting devices are of equal priority
within an interrupt bank. In this kind of environment,
once a device is serviced, all other equal priority pe-
ripherals should be given a chance to be serviced
before the original device is serviced again. This is
accomplished by automatically assigning a device
the lowest priority after being serviced. Thus, in the
worst case, the device would have to wait until all
other peripherals connected to the same bank are
serviced before it is serviced again.
Figure 40 shows how the Rotate On Non-Specific
EOI command affects the interrupt priorities. As-
sume the IRQ priorities were assigned with IRQ0 the
highest and IRQ7 the lowest. IRQ6 and IRQ4 are
already in service but neither is completed. Being
the higher priority routine, IRQ4 is necessarily the
routine being executed. During the IRQ4 routine, a
rotate on Non-Specific EOI command is executed.
When this happens, Bit 4 in the ISR is reset. IRQ4
then becomes the lowest priority and IRQ5 becomes
the highest.
There are two methods of accomplishing automatic
rotation. One is used in conjunction with the Non-
Specific EOI command and the other is used with
271070–51
271070–52
Figure 40. Rotate On Non-Specific EOI Command
59
M82380
ROTATE ON AUTOMATIC EOI MODE
program or within interrupt routines. Two specific ro-
tation commands are available to the user: Set Prior-
ity Command and Rotate On Specific EOI Com-
mand.
The Rotate On Automatic EOI Mode works much
like the Rotate On Non-Specific EOI Command. The
main difference is that priority rotation is done auto-
matically after the second INTA cycle of an interrupt
request. To enter or exit this mode, a Rotate-On-Au-
tomatic-EOI Set Command and Rotate-On-Automat-
ic-EOI Clear Command is provided. After this mode
is entered, no other commands are needed as in the
normal Automatic EOI Mode. However, it must be
noted again that when using any form of the Auto-
matic EOI Mode, special consideration should be
taken. The guideline presented in the Automatic EOI
Mode also applies here.
SET PRIORITY COMMAND
The Set Priority Command allows the programmer to
assign an IRQ level the lowest priority. All other in-
terrupt levels will conform to the Fully Nested Mode
based on the newly assigned low priority.
ROTATE ON SPECIFIC EOI COMMAND
The Rotate On Specific EOI Command is literally a
combination of the Set Priority Command and the
Specific EOI Command. Like the Set Priority Com-
mand, a specified IRQ level is assigned lowest priori-
ty. Like the Specific EOI Command, a specified level
will be reset in the ISR. Thus, this command accom-
plishes both tasks in one single command.
SPECIFIC ROTATIONÐSPECIFIC PRIORITY
Specific rotation gives the user versatile capabilities
in interrupt controlled operations. It serves in those
applications in which a specific device’s interrupt pri-
ority must be altered. As opposed to Automatic Ro-
tation which will automatically set priorities after
each interrupt request is serviced, specific rotation is
completely user controlled. That is, the user selects
which interrupt level is to receive the lowest or the
highest priority. This can be done during the main
INTERRUPT PRIORITY MODE SUMMARY
In order to simplify understanding the many modes
of interrupt priority, Table 9 is provided to bring out
their summary of operations.
Table 9. Interrupt Priority Mode Summary
Interrupt
Operation
Summary
Effect On Priority After EOI
Priority Mode
Non-Specific/Automatic
Specific
Fully-Nested Mode
IRQ0-Highest Priority
IRQ7-Lowest Priority
No change in priority.
Highest ISR bit is reset.
Not Applicable.
Automatic Rotation
(Equal Priority Devices)
Interrupt level just serviced Highest ISR bit is reset and the Not Applicable.
is the lowest priority. Other
priorities rotate to conform
to Fully-Nested Mode.
corresponding level becomes the
lowest priority.
Specific Rotation
(Specific Priority
Devices)
User specifies the lowest
priority level. Other priorities
rotate to conform to Fully-
Nested Mode.
Not Applicable.
As described under
‘Operation Summary’.
60
M82380
4.4.3 INTERRUPT MASKING
4.4.4 EDGE OR LEVEL INTERRUPT
TRIGGERING
VIA INTERRUPT MASK REGISTER
Each bank in the M82380 PIC can be programmed
independently for either edge or level sensing for the
interrupt request signals. Recall that all IRQ inputs
are active LOW. Therefore, in the edge triggered
mode, an active edge is defined as an input tran-
sition from an inactive (HIGH) to active (LOW) state.
The interrupt input may remain active without gener-
ating another interrupt. During level triggered mode,
an interrupt request will be recognized by an active
(LOW) input, and there is no need for edge detec-
tion. However, the interrupt request must be re-
moved before the EOI Command is issued, or the
i386 processor must be disabled to prevent a sec-
ond false interrupt from occurring.
Each bank in the M82380 PIC has an Interrupt Mask
Register (IMR) which enhances interrupt control ca-
pabilities. This IMR allows individual IRQ masking.
When an IRQ is masked, its interrupt request is dis-
abled until it is unmasked. Each bit in the 8-bit IMR
disables one interrupt channel if it is set (HIGH). Bit
0 masks IRQ0, Bit 1 masks IRQ1 and so forth.
Masking an IRQ channel will only disable the corre-
sponding channel and does not affect the others op-
erations.
The IMR acts only on the output of the IRR. That is,
if an interrupt occurs while its IMR bit is set, this
request is not ‘forgotten’. Even with an IRQ input
masked, it is still possible to set the IRR. Therefore,
when the IMR bit is reset, an interrupt request to the
i386 processor will then be generated, providing that
the IRQ request remains active. If the IRQ request is
removed before the IMR is reset, the Default Inter-
rupt Vector (Bank A, level 7) will be generated during
the interrupt acknowledge cycle.
In either modes, the interrupt request input must be
active (LOW) during the first INTA cycle in order to
be recognized. Otherwise, the Default Interrupt Vec-
tor will be generated at level 7 of Bank A.
4.4.5 INTERRUPT CASCADING
As mentioned previously, the M82380 allows for ex-
ternal Slave interrupt controllers to be cascaded to
any of its external interrupt request pins. The
M82380 PIC indicates that a external Slave Control-
ler is to be serviced by putting the contents of the
Vector Register associated with the particular re-
quest on the i386 Data Bus during the first INTA
cycle (instead of 00H during a non-slave service).
The external logic should latch the vector on the
Data Bus using the INTA status signals and use it to
select the external Slave Controller to be serviced
(see Figure 41). The selected Slave will then re-
spond to the second INTA cycle and place its vector
on the Data Bus. This method requires that if exter-
nal Slave Controllers are used in the system, no vec-
tor should be programmed to 00H.
SPECIAL MASK MODE
In the Fully Nested Mode, all IRQ levels of lower
priority than the routine in service are inhibited. How-
ever, in some applications, it may be desirable to let
a lower priority interrupt request to interrupt the rou-
tine in service. One method to achieve this is by
using the Special Mask Mode. Working in conjunc-
tion with the IMR, the Special Mask Mode enables
interrupts from all levels except the level in service.
This is usually done inside an interrupt service rou-
tine by masking the level that is in service and then
issuing the Special Mask Mode Command. Once the
Special Mask Mode is enabled, it remains in effect
until it is disabled.
271070–53
Figure 41. Slave Cascade Address Capturing
61
M82380
Since the external Slave Cascade Address is provid-
ed on the Data Bus during INTA cycle 1, an external
latch is required to capture this address for the Slave
Controller. A simple scheme is depicted in Figure 41.
pending interrupt request with the highest priority
can be determined. To use this command, the INT
output is not used, or the i386 processor interrupt is
disabled. Service to devices is achieved by software
using the Poll Command.
SPECIAL FULLY NESTED MODE
This mode is useful if there is a routine command
common to several levels so that the INTA se-
quence is not needed. Another application is to use
the Poll Command to expand the number of priority
levels.
This mode will be used where cascading is em-
ployed and the priority is to be conserved within
each Slave Controller. The Special Fully Nested
Mode is similar to the ‘regular’ Fully Nested Mode
with the following exceptions:
Notice that the ICW2 mechanism is not supported
for the Poll Command. However, if the Poll Com-
mand is used, the programmable Vector Registers
are of no concern since no INTA cycle will be gener-
ated.
Ð When an interrupt request from a Slave Control-
ler is in service, this Slave Controller is not
locked out from the Master’s priority logic. Fur-
ther interrupt requests from the higher priority
logic within the Slave Controller will be recog-
nized by the M82380 PIC and will initiate inter-
rupts to the i386 processor. In comparing to the
‘regular’ Fully Nested Mode, the Slave Controller
is masked out when its request is in service and
no higher requests from the same Slave Control-
ler can be serviced.
READING INTERRUPT REGISTERS
The contents of each interrupt register (IRR, ISR,
and IMR) can be read to update the user’s program
on the present status of the M82380 PIC. This can
be a versatile tool in the decision making process of
a service routine, giving the user more control over
interrupt operations.
Ð Before exiting the interrupt service routine, the
software has to check whether the interrupt serv-
iced was the only request from the Slave Con-
troller. This is done by sending a Non-Specific
EOI Command to the Slave Controller and then
reading its In Service Register. If there are no
requests in the Slave Controller, a Non-Specific
EOI can be sent to the corresponding M82380
PIC bank also. Otherwise, no EOI should be
sent.
The reading of the IRR and ISR contents can be
performed via the Operation Control Word 3 by us-
ing a Read Status Register Command and the con-
tent of IMR can be read via a simple read operation
of the register itself.
4.5 Register Set Overview
4.4.6 READING INTERRUPT STATUS
Each bank of the M82380 PIC consists of a set of
8-bit registers to control its operations. The address
map of all the registers is shown in Table 10. Since
all three register sets are identical in functions, only
one set will be described.
The M82380 PIC provides several ways to read dif-
ferent status of each interrupt bank for more flexible
interrupt control operations. These include polling
the highest priority pending interrupt request and
reading the contents of different interrupt status reg-
isters.
Functionally, each register set can be divided into
five groups. They are: the four Initialization Com-
mand Words (ICW’s), the three Operation Control
Words (OCW’s), the Poll/Interrupt Request/In-Serv-
ice Register, the Interrupt Mask Register, and the
Vector Registers. A description of each group fol-
lows.
POLL COMMAND
The M82380 PIC supports status polling operations
with the Poll Command. In a Poll Command, the
62
M82380
Table 10. Interrupt Controller Register Address Map
Port
Access
Write
Read
Register Description
Address
20H
21H
Bank B ICW1, OCW2, or OCW3
Bank B Poll, Request or In-Service
Status Register
Write
Read
Read
Bank B ICW2, ICW3, ICW4, OCW1
Bank B Mask Register
Bank B ICW2
22H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
IRQ8 Vector Register
IRQ9 Vector Register
Reserved
IRQ11 Vector Register
IRQ12 Vector Register
IRQ13 Vector Register
IRQ14 Vector Register
IRQ15 Vector Register
A0H
A1H
Write
Read
Bank C ICW1, OCW2, or OCW3
Bank C Poll, Request or In-Service
Status Register
Write
Read
Read
Bank C ICW2, ICW3, ICW4, OCW1
Bank C Mask Register
Bank C ICW2
A2H
A8H
A9H
AAH
ABH
ACH
ADH
AEH
AFH
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
IRQ16 Vector Register
IRQ17 Vector Register
IRQ18 Vector Register
IRQ19 Vector Register
IRQ20 Vector Register
IRQ21 Vector Register
IRQ22 Vector Register
IRQ23 Vector Register
30H
31H
Write
Read
Bank A ICW1, OCW2, or OCW3
Bank A Poll, Request or In-Service
Status Register
Write
Read
Read
Bank A ICW2, ICW3, ICW4, OCW1
Bank A Mask Register
Bank ICW2
32H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
IRQ0 Vector Register
IRQ1 Vector Register
IRQ1.5 Vector Register
IRQ3 Vector Register
IRQ4 Vector Register
Reserved
Reserved
IRQ7 Vector Register
63
M82380
Ð To select either the Automatic EOI mode or soft-
ware EOI mode;
4.5.1 INITIALIZATION COMMAND WORDS (ICW)
Before normal operation can begin, the M82380 PIC
must be brought to a known state. There are four
8-bit Initialization Command Words in each interrupt
bank to setup the necessary conditions and modes
for proper operation. Except for the second common
word (ICW2) which is a read/write register, the other
three are write-only registers. Without going into de-
tail of the bit definitions of the command words, the
following subsections give a brief description of what
functions each command word controls.
Ð To select if the Special Nested mode is to be
used in conjunction with the cascade mode.
4.5.2 OPERATION CONTROL WORDS (OCW)
Once initialized by the ICW’s, the interrupt banks will
be operating in the Fully Nested Mode by default
and they are ready to accept interrupt requests.
However, the operations of each interrupt bank can
be further controlled or modified by the use of
OCW’s. Three OCW’s are available for programming
various modes and commands. Note that all OCW’s
are 8-bit write-only registers.
ICW1
The ICW1 has three major functions. They are:
Ð To select between the two IRQ input triggering
modes (edge-or level-triggered);
The modes and operations controlled by the OCW’s
are:
Ð To designate whether or not the interrupt bank is
to be used alone or in the cascade mode. If the
cascade mode is desired, the interrupt bank will
accept ICW3 for further cascade mode program-
ming. Otherwise, no ICW3 will be accepted;
Ð Fully Nested Mode;
Ð Rotating Priority Mode;
Ð Special Mask Mode;
Ð Poll Mode;
Ð EOI Commands;
Ð Read Status Commands.
Ð To determine whether or not ICW4 will be issued;
that is, if any of the ICW4 operations are to be
used.
OCW1
ICW2
OCW1 is used solely for masking operations. It pro-
vides a direct link to the Interrupt Mask Register
(IMR). The M80386 can write to this OCW register to
enable or disable the interrupt inputs. Reading the
pre-programmed mask can be done via the Interrupt
Mask Register which will be discussed shortly.
ICW2 is provided for compatibility with the M8259A
only. Its contents do not affect the operation of the
interrupt bank in any way. Whenever the ICW2 of
any of the three banks is written into, an interrupt is
generated from Bank A at level 1.5. The interrupt
request will be cleared after the ICW2 register has
been read by the M80386. The user is expected to
program the corresponding vector register or to use
it as an indicator that an attempt was made to alter
the contents. Note that each ICW2 register has dif-
ferent addresses for read and write operations.
OCW2
OCW2 is used to select End-Of-Interrupt, Automatic
Priority Rotation, and Specific Priority Rotation oper-
ations. Associated commands and modes of these
operations are selected using the different combina-
tions of bits in OCW2.
ICW3
Specifically, the OCW2 is used to:
The interrupt bank will only accept an ICW3 if pro-
grammed in the external cascade mode (as indicat-
ed in ICW1). ICW3 is used for specific programming
within the cascade mode. The bits in ICW3 indicate
which interrupt request inputs have a Slave cascad-
ed to them. This will subsequently affect the inter-
rupt vector generation during the interrupt acknowl-
edge cycles as described previously.
Ð Designate an interrupt level (0–7) to be used to
reset a specific ISR bit or to set a specific priori-
ty. This function can be enabled or disabled;
Ð Select which software EOI command (if any) is to
be executed (i.e., Non-Specific or Specific EOI);
Ð Enable one of the priority rotation operations
(i.e., Rotate On Non-Specific EOI, Rotate On Au-
tomatic EOI, or Rotate on Specific EOI).
ICW4
OCW3
The ICW4 is accepted only if it was selected in
ICW1. This command word register serves two func-
tions:
There are three main categories of operation that
OCW3 controls. That are summarized as follows:
64
M82380
Ð To select and execute the Read Status Register
Commands, either reading the Interrupt Request
Register (IRR) or the In-Service Register (ISR);
All three interrupt banks are programmed in a similar
way. Therefore, only a single bank will be described.
4.6.1 INITIALIZATION (ICW)
Ð To issue the Poll Command. The Poll Command
will override a Read Register Command if both
functions are enabled simultaneously;
Before normal operation can begin, each bank must
be initialized by programming a sequence of two to
four bytes written into the ICW’s.
Ð To set or reset the Special Mask Mode.
Figure 42 shows the initialization flow for an interrupt
bank. Both ICW1 and ICW2 must be issued for any
form of operation. However, ICW3 and ICW4 are
used only if designated in ICW1. Once initialized, if
any programming changes within the ICW’s are to
be made, the entire ICW sequence must be repro-
grammed, not just an individual ICW.
4.5.3 POLL/INTERRUPT REQUEST/IN-SERVICE
STATUS REGISTER
As the name implies, this 8-bit read-only register has
multiple functions. Depending on the command is-
sued in the OCW3, the content of this register re-
flects the result of the command executed. For a
Poll Command, the register read contains the binary
code of the highest priority level requesting service
(if any). For a Read IRR Command, the register con-
tent will show the current pending interrupt re-
quest(s). Finally, for a Read ISR Command, this reg-
ister will specify all interrupt levels which are being
serviced.
Note that although the ICW2’s in the M82380 PIC do
not affect the Bank’s operation, they still must be
programmed in order to preserve the compatibility
with the M8259A. The contents programmed are not
relevant to the overall operations of the interrupt
banks. Also, whenever one of the three ICW2’s is
programmed, an interrupt level 1.5 in Bank A will be
generated. This interrupt request will be cleared
upon reading of the ICW2 registers. Since the three
ICW2’s share the same interrupt level and the sys-
tem may not know the origin of the interrupt, all three
ICW2’s must be read.
4.5.4 INTERRUPT MASK REGISTER (IMR)
This is a read-only 8-bit register which, when read,
will specify all interrupt levels within the same bank
that are masked.
However, it is not necessary to provide an interrupt
service routine for the ICW2 interrupt. One way to
avoid this is as follows. At the beginning of the initial-
ization of the interrupt banks, the i386 processor in-
terrupt should be disabled. After each ICW2 register
write operation is performed during the initialization,
the corresponding ICW2 register is read. This read
operation will clear the interrupt request of the
M82380. At the end of the initialization, the i386
processor interrupt is re-enabled. With this method,
the i386 processor will not detect the ICW2 interrupt
request, thus eliminating the need of an interrupt
service routine.
4.5.5 VECTOR REGISTER (VR)
Each interrupt request input has an 8-bit read/write
programmable vector register associated with it. The
registers should be programmed to contain the inter-
rupt vector for the corresponding request. The con-
tents of the Vector Register will be placed on the
Data Bus during the INTA cycles as described previ-
ously.
4.6 Programming
Programming the M82380 PIC is accomplished by
using two types of command words: ICW’s and
OCW’s. All modes and commands explained in the
previous sections are programmable using the
ICW’s and OCW’s. The ICW’s are issued from the
M80386 in a sequential format and are used to set-
up the banks in the M82380 PIC in an initial state of
operation. The OCW’s are issued as needed to vary
and control the M82380 PIC’s operations.
Certain internal setup conditions occur automatically
within the interrupt bank after the first ICW (ICW1)
has been issued. They are:
Ð The edge sensitive circuit is reset, which means
that following initialization, an interrupt request
input must make a HIGH-to-LOW transition to
generate an interrupt;
Ð The Interrupt Mask Register (IMR) is cleared;
that is, all interrupt inputs are enabled;
Both ICW’s and OCW’s are sent by the i386 proces-
sor to the interrupt banks via the Data Bus. Each
bank distinguishes between the different ICW’s and
OCW’s by the I/O address map, the sequence they
are issued (ICW’s only), and by some dedicated bits
among the ICW’s and OCW’s.
Ð IRQ7 input of each bank is assigned priority 7
(lowest);
Ð Special Mask Mode is cleared and Status Read
is set to IRR;
Ð If no ICW4 is needed, then no Automatic-EOI is
selected.
65
M82380
271070–54
*ICW2 vector address must be programmed now.
Other vector addresses may be programmed via ICW2 interrupt service routine.
Figure 42. Initialization Sequence
4.6.2 VECTOR REGISTERS (VR)
4.6.3 OPERATION CONTROL WORDS (OCW)
Each interrupt request input has a separate Vector
Register. These Vector Registers are used to store
the pre-programmed vector number corresponding
to their interrupt sources. In order to guarantee prop-
er interrupt handling, all Vector Registers must be
programmed with the predefined vector numbers.
Since an interrupt request will be generated whenev-
er an ICW2 is written during the initialization se-
quence, it is important that the Vector Register of
IRQ1.5 in Bank A should be initialized and the inter-
rupt service routine of this vector is set up before the
ICW’s are written.
After the ICW’s are programmed, the operations of
each interrupt controller bank can be changed by
writing into the OCW’s as explained before. There is
no special programming sequence required for the
OCW’s. Any OCW may be written at any time in or-
der to change the mode of or to perform certain op-
erations on the interrupt banks.
READ STATUS AND POLL COMMANDS (OCW3)
Since the reading of IRR and ISR status as well as
the result of a Poll Command are available on the
66
M82380
same read-only Status Register, a special Read
Status/Poll Command must be issued before the
Poll/Interrupt Request/In-Service Status Register is
read. This command can be specified by writing the
required control word into OCW3. As mentioned ear-
lier, if both the Poll Command and the Status Read
Command are enabled simultaneously, the Poll
Command will override the Status Read. That is, af-
ter the command execution, the Status Register will
contain the result of the Poll Command.
‘remembers’ which register is selected. However,
this is not true when the Poll Command is used.
In the Poll Command, after the OCW3 is written, the
M82380 PIC treats the next read to the Status Reg-
ister as an interrupt acknowledge. This will set the
appropriate IS bit if there is a request and read the
priority level. Interrupt Request input status remains
unchanged from the Poll Command to the Status
Read.
Note that for reading IRR and ISR, there is no need
to issue a Read Status Command to the OCW3 ev-
ery time the IRR or ISR is to be read. Once a Read
Status Command is received by the interrupt bank, it
In addition to the above read commands, the Inter-
rupt Mask Register (IMR) can also be read. When
read, this register reflects the contents of the pre-
programmed OCW1 which contains information on
which interrupt request(s) is(are) currently disabled.
4.7 Register Bit Definition
INITIALIZATION COMMAND WORD 1 (ICW1)
271070–55
INITIALIZATION COMMAND WORD 2 (ICW2)
271070–56
67
M82380
INITIALIZATION COMMAND WORD 3 (ICW3)
ICW3 for Bank A:
271070–57
ICW3 for Bank B:
271070–58
ICW3 for Bank C:
271070–59
INITIALIZATION COMMAND WORD 4 (ICW4)
271070–60
OPERATION CONTROL WORD 1 (OCW1)
271070–61
68
M82380
OPERATION CONTROL WORD 2 (OCW2)
271070–62
OPERATION CONTROL WORD 3 (OCW3)
271070–63
ESMMÐEnable Special Mask Mode. When this bit is set to 1, it enables the SMM bit to set or reset the Special Mask
Mode. When this bit is set to 0, SMM bit becomes don’t care.
e
e
1, the interrupt controller bank will enter Special Mask Mode. If
SMMÐSpecial Mask Mode. If ESMM
1 and SMM
e
0, the bank will revert to normal mask mode. When ESMM 0, SMM has no effect.
e
e
ESMM
1 and SMM
Poll/Interrupt Request/In-Service Status Register
POLL COMMAND STATUS
271070–64
69
M82380
INTERRUPT REQUEST STATUS
271070–65
NOTE:
Although all Interrupt Request inputs are active LOW, the internal logical will invert the state of the pins so that when
there is a pending interrupt request at the input, the corresponding IRQ bit will be set to HIGH in the Interrupt Request
Status register.
IN-SERVICE STATUS
VECTOR REGISTER (VR)
271070–66
271070–67
4.8 Register Operational Summary
For ease of reference, Table 11 gives a summary of the different operating modes and commands with their
corresponding registers.
Table 11. Register Operational Summary
Operational
Description
Command
Words
Bits
Fully Nested Mode
Non-specific EOI Command
Specific EOI Command
OCW-Default
OCW2
OCW2
Ð
EOI
SL, EOI,
LO–L2
IC4, AEOI
EOI
Automatic EOI Mode
Rotate On Non-Specific
EOI Command
ICW1, ICW4
OCW2
Rotate On Automatic
EOI Mode
OCW2
R, SL, EOI
Set Priority Command
Rotate On Specific
EOI Command
OCW2
OCW2
L0–L2
R, SL, EOI
Interrupt Mask Register
Special Mask Mode
Level Triggered Mode
Edge Triggered Mode
Read Register Command, IRR
Read Register Command, ISR
Red IMR
OCW1
OCW3
ICW1
M0–M7
ESMM, SMM
LTIM
ICW1
LTIM
OCW3
OCW3
IMR
RR, RIS
RR, RIS
M0–M7
P
Poll Command
Special Fully Nested Mode
OCW3
ICW2, ICW4
IC4, SFNM
70
M82380
TIMER 0Ð Event Based IRQ8 Generator
5.0 PROGRAMMABLE INTERVAL
TIMER
Timer 0 is intended to be used as an Event Counter.
The output of this timer will generate an Interrupt
Request 8 (IRQ8) upon a rising edge of the timer
output (TOUT0). Typically, this timer is used to im-
plement a time-of-day clock or system tick. The Tim-
er 0 output is not available as an external signal.
5.1 Functional Description
The M82380 contains four independently Program-
mable Interval Timers: Timer 0–3. All four timers are
functionally compatible to the Intel M82C54. The
first three timers (Timer 0–2) have specific func-
tions. The fourth timer, Timer 3, is a general purpose
timer. Table 12 depicts the functions of each timer.
A brief description of each timer’s function follows.
TIMER 1Ð General Purpose/DRAM Refresh
Request
The output of Timer 1, TOUT1, can be used as a
general purpose timer or as a DRAM Refresh Re-
quest signal. The rising edge of this output creates a
DRAM refresh request to the M82380 DRAM Re-
fresh Controller. Upon reset, the Refresh Request
function is disabled, and the output pin is the Timer 1
output.
Table 12. Programmable
Interval Timer Functions
Timer
Output
IRQ8
Function
Event Based
0
TIMER 2ÐGeneral Purpose/Speaker Out/IRQ3
IRQ8 Generator
Gen. Purpose/DRAM
Refresh Req.
1
2
3
TOUT1/REF
The Timer 2 output, TOUT2, could be used to sup-
port tone generation to an external speaker. This pin
is a bidirectional signal. When used as an input, a
logic LOW asserted at this pin will generate an Inter-
rupt Register 3 (IRQ3) (see Programmable Interrupt
Controller).
TOUT2/IRQ3 Gen. Purpose/Speaker
Out/IRQ3
TOUT3
Gen. Purpose/IRQ0
Generator
271070–68
Figure 43. Block Diagram of Programmable Interval Timer
71
M82380
TIMER 3ÐGeneral Purpose/Interrupt Request 0
Generator
CONTROL WORD REGISTERS I & II
The Control Word Registers are write-only registers.
They are used to control the operating modes of the
timers. Control Word Register I controls Timers 0, 1
and 2, and Control Word Register II controls Timer
3. Detailed description of the Control Word Regis-
ters will be included in the Register Set Overview
section.
The output of Timer 3 is fed to an edge detector and
generates an Interrupt Request 0 (IRQ0) in the
M82380. The inverted output of this timer (TOUT3)
is also available as an external signal for general
purpose use.
5.1.1 INTERNAL ARCHITECTURE
COUNTER 0, COUNTER 1,
COUNTER 2, COUNTER 3
The functional block diagram of the Programmable
Interval Timer section is shown in Figure 43. Follow-
ing is a description of each block.
Counters 0, 1, 2, and 3 are the major parts of Timers
0, 1, 2, and 3, respectively. These four functional
blocks are identical in operation, so only a single
counter will be described. The internal block dia-
gram of one counter is shown in Figure 44.
DATA BUFFER & READ/WRITE LOGIC
This part of the Programmable Interval Timer is used
to interface the four timers to the M82380 internal
bus. The Data Buffer is for transferring commands
and data between the 8-bit internal bus and the
timers.
The four counters share a common clock input
(CLKIN), but otherwise are fully independent. Each
counter is programmable to operate in a different
Mode.
The Read/Write Logic accepts inputs from the inter-
nal bus and generates signals to control other func-
tional blocks within the timer section.
Although the Control Word Register is shown in the
Figure 44, it is not part of the counter itself. Its pro-
grammed contents are used to control the opera-
tions of the counters.
271070–69
Figure 44. Internal Block Diagram of A Counter
72
M82380
The Status Register, when latched, contains the cur-
rent contents of the Control Word Register and
status of the output and Null Count Flag (see Read
Back Command).
pendent of the M82380 system clock, CLK2. In the
following discussion, each ‘CLK Pulse’ is defined as
the time period between a rising edge and a falling
edge, in that order, of CLKIN.
The Counting Element (CE) is the actual counter. It
is a 16-bit presettable synchronous down counter.
During the rising edge of CLKIN, the state of GATE
is sampled. All new counts are loaded and counters
are decremented on the falling edge of CLKIN.
The Output Latches (OL) contain two 8-bit latches
(OLM and OLL). Normally, these latches ‘follow’ the
content of the CE. OLM contains the most signifi-
cant byte of the counter and OLL contains the least
significant byte. If the Counter Latch Command is
sent to the counter, OL will latch the present count
until read by the i386 processor and then return to
follow the CE. One latch at a time is enabled by the
timer’s Control Logic to drive the internal bus. This is
how the 16-bit Counter communicates over the 8-bit
internal bus. Note that CE cannot be read. Whenev-
er the count is read, it is one of the OL’s that is being
read.
Please note that there are no restrictions on the
CLKIN signal during WRITE cycles to the M82380
timer unit. Refer to Appendix D for details on this
issue.
5.2.2 TOUT1, TOUT2, TOUT3
TOUT1, TOUT2 and TOUT3 are the external output
signals of Timer 1, Timer 2 and Timer 3, respective-
ly. TOUT2 and TOUT3 are the inverted signals of
their respective counter outputs, OUT. There is no
external output for Timer 0.
When a new count is written into the counter, the
value will be stored in the Count Registers (CR), and
transferred to CE. The transferring of the contents
from CR’s to CE is defined as ‘loading’ of the coun-
ter. The Count Register contains two 8-bit registers:
CRM (which contains the most significant byte) and
CRL (which contains the least significant byte). Simi-
lar to the OL’s, the Control Logic allows one register
at a time to be loaded from the 8-bit internal bus.
However, both bytes are transferred from the CR’s
to the CE simultaneously. Both CR’s are cleared
when the Counter is programmed. This way, if the
Counter has been programmed for one byte count
(either the most significant or the least significant
byte only), the other byte will be zero. Note that CE
cannot be written into directly. Whenever a count is
written, it is the CR that is being written.
If Timer 2 is to be used as a tone generator of a
speaker, external buffering must be used to provide
sufficient drive capability.
The Outputs of Timer 2 and 3 are dual function pins.
The output pin of Timer 2 (TOUT2/IRQ3), which is a
bidirectional open-collector signal, can also be used
as interrupt request input. When the interrupt func-
tion is enabled (through the Programmable Interrupt
Controller), a LOW on this input will generate an In-
terrupt Request 3 (IRQ3) to the M82380 Program-
mable Interrupt Controller. This pin has a weak inter-
nal pull-up resistor. To use the IRQ3 function, Timer
2 should be programmed so that OUT2 is LOW. Ad-
ditionally, OUT3 of Timer 3 is connected to an edge
detector which will generate an Interrupt Request 0
(IRQ0) to the M82380 after the rising edge of OUT3
(see Figure 43).
As shown in the diagram, the Control Logic consists
of three signals: CLKIN, GATE, and OUT. CLKIN
and GATE will be discussed in detail in the section
that follows. OUT is the internal output of the coun-
ter. The external outputs of some timers (TOUT) are
the inverted version of OUT (see TOUT1, TOUT2,
TOUT3). The state of OUT depends on the mode of
operation of the timer.
5.2.3 GATE
GATE is not an externally controllable signal. Rath-
er, it can be software controlled with the Internal
Control Port. The state of GATE is always sampled
on the rising edge of CLKIN. Depending on the
mode of operation, GATE is used to enable/disable
counting or trigger the start of an operation.
5.2 Interface Signals
For Timer 0 and 1, GATE is always enabled (HIGH).
For Timer 2 and 3, GATE is connected to Bit 0 and
6, respectively, of an Internal Control Port (at ad-
dress 61H) of the M82380. After a hardware reset,
the state of GATE of Timer 2 and 3 is disabled
(LOW).
5.2.1 CLKIN
CLKIN is an input signal used by all four timers for
internal timing reference. This signal can be inde-
73
M82380
from the new count. If a two-byte count is written,
the following happens:
5.3 Modes of Operation
Each timer can be independently programmed to
operate in one of six different modes. Timers are
programmed by writing a Control Word into the con-
trol Word Register followed by an Initial Count (see
Programming).
1. Writing the first byte disables counting, OUT is set
LOW immediately (i.e., no CLK pulse required).
2. Writing the second byte allows the new count to
be loaded on the next CLK pulse.
This allows the counting sequence to be synchroniz-
ed by software. Again, OUT does not go HIGH until
The following are defined for use in describing the
different modes of operation.
a
N
ten.
1 CLK pulses after the new count of N is writ-
CLK PulseÐA rising edge, then a falling edge, in
that order of CLKIN.
TriggerÐA rising edge of a timer’s GATE input.
Timer/Counter LoadingÐThe transfer of a count
from Count Register (CR) to Count Element
(CE).
If an initial count is written while GATE is LOW, the
counter will be loaded on the next CLK pulse. When
GATE goes HIGH, OUT will go HIGH N CLK pulses
later; no CLK pulse is needed to load the counter as
this has already been done.
5.3.1 MODE 0ÐINTERRUPT ON TERMINAL
COUNT
5.3.2 MODE 1ÐGATE RETRIGGERABLE
ONE-SHOT
Mode 0 is typically used for event counting. After the
Control Word is written, OUT is initially LOW, and will
remain LOW until the counter reaches zero. OUT
then goes HIGH and remains HIGH until a new
count or a new Mode 0 Control Word is written into
the counter.
In this mode, OUT will be initially HIGH. OUT will go
LOW on the CLK pulse following a trigger to start the
one-shot operation. The OUT signal will then remain
LOW until the timer reaches zero. At this point, OUT
will stay HIGH until the next trigger comes in. Since
the state of GATE signals of Timer 0 and 1 are inter-
nally set to HIGH.
e
LOW disables counting. However, GATE
In this mode, GATE
HIGH enables counting;
e
GATE
has no effect on OUT.
After writing the Control Word and initial count, the
timer is considered ‘armed’. A trigger results in load-
ing the timer and setting OUT LOW on the next CLK
pulse. Therefore, an initial count of N will result in a
one-shot pulse width of N CLK cycles. Note that this
one-shot operation is retriggerable; i.e., OUT will re-
main LOW for N CLK pulses after every trigger. The
one-shot operation can be repeated without rewrit-
ing the same count into the timer.
After the Control Word and initial count are written to
a timer, the initial count will be loaded on the next
CLK pulse. This CLK pulse does not decrement the
count, so for an initial count of N, OUT does not go
a
HIGH until N
written.
1 CLK pulses after the initial count is
If a new count is written to the timer, it will be loaded
on the next CLK pulse and counting will continue
If a new count is written to the timer during a one-
shot operation, the current one-shot pulse width will
not be affected until the timer is retriggered. This is
because loading of the new count to CE will occur
only when the one-shot is triggered.
74
M82380
271070–70
NOTES:
The following conventions apply to all mode timing diagrams.
1. Counters are programmed for binary (not BCD) counting and for reading/writing least significant byte (LSB) only.
2. The counter is always selected (CS always low).
e
3. CW stands for ‘‘Control Word’’; CW
10 means a control word of 10, Hex is written to the counter.
4. LSB stands for ‘‘least significant byte’’ of count.
5. Numbers below diagrams are count values.
The lower number is the least significant byte.
The upper number is the most significant byte. Since the counter is programmed to read/write LSB only, the
most significant byte cannot be read.
N stands for an undefined count.
Vertical lines show transitions between count values.
Figure 43. Mode 0
75
M82380
271070–71
Figure 44. Mode 1
count of N, the sequence repeats every N CLK cy-
cles.
5.3.3 MODE 2ÐRATE GENERATOR
This mode is a divide-by-N counter. It is typically
used to generate a Real Time Clock interrupt. OUT
will initially be HIGH. When the initial count has dec-
remented to 1, OUT goes LOW for one CLK pulse,
then OUT goes HIGH again. Then the timer reloads
the initial count and the process is repeated. In other
words, this mode is periodic since the same se-
quence is repeated itself indefinitely. For an initial
e
LOW disables counting. If GATE
Similar to Mode 0, GATE
e
HIGH enables counting,
where GATE
goes LOW during an output pulse (LOW), OUT is set
HIGH immediately. A trigger (rising edge on GATE)
will reload the timer with the initial count on the next
CLK pulse. Then, OUT will go LOW (for one CLK
pulse) N CLK pulses after the new trigger. Thus,
GATE can be used to synchronize the timer.
76
M82380
271070–72
NOTE:
A GATE transition should not occur one clock prior to terminal count.
Figure 45. Mode 2
After writing a Control Word and initial count, the
timer will be loaded on the next CLK pulse. OUT
goes LOW (for the CLK pulse) N CLK pulses after
the initial count is written. This is another way the
timer may be synchronized by software.
the timer will be loaded with the new count on the
next CLK pulse after the trigger, and counting will
continue with the new count.
5.3.4 MODE 3ÐSQUARE WAVE GENERATOR
Writing a new count while counting does not affect
the current counting sequence because the new
count will not be loaded until the end of the current
counting cycle. If a trigger is received after writing a
new count but before the end of the current period,
Mode 3 is typically used for Baud Rate generation.
Functionally, this mode is similar to Mode 2 except
for the duty cycle of OUT. In this mode, OUT will be
initially HIGH. When half of the initial count has ex-
pired, OUT goes low for the remainder of the count.
77
M82380
The counting sequence will be repeated, thus this
mode is also periodic. Note that an initial count of N
results in a square wave with a period of N CLK
pulses.
pulse and counting will continue from the new count.
Otherwise, the new count will be loaded at the end
of the current half-cycle.
There is a slight difference in operation depending
on whether the initial count is EVEN or ODD. The
following description is to show exactly how this
mode is implemented.
The GATE input can be used to synchronize the tim-
e
disables counting. If GATE goes LOW while OUT is
LOW, OUT is set HIGH immediately (i.e., no CLK
pulse is required). A trigger reloads the timer with the
initial count on the next CLK pulse.
e
er. GATE
HIGH enables counting; GATE
LOW
EVEN COUNTS:
OUT is initially HIGH. The initial count is loaded on
one CLK pulse and is decremented by two on suc-
ceeding CLK pulses. When the count expires (decre-
mented to 2), OUT changes to LOW and the timer is
reloaded with the initial count. The above process is
repeated indefinitely.
After writing a Control Word and initial count, the
timer will be loaded on the next CLK pulse. This al-
lows the timer to be synchronized by software.
Writing a new count while counting does not affect
the current counting sequence. If a trigger is re-
ceived after writing a new count but before the end
of the current half-cycle of the square wave, the tim-
er will be loaded with the new count on the next CLK
ODD COUNTS:
OUT is initially HIGH. The initial count minus one
(which is an even number) is loaded on one CLK
271070–73
NOTE:
A-GATE transition should not occur one clock prior to terminal count.
Figure 46. Mode 3
78
M82380
pulse and is decremented by two on succeeding
CLK pulses. One CLK pulse after the count expires
(decremented to 2), OUT goes LOW and the timer is
loaded with the initial count minus one again. Suc-
ceeding CLK pulses decrement the count by two.
When the count expires, OUT goes HIGH immedi-
ately and the timer is reloaded with the initial count
minus one. The above process is repeated indefi-
nitely. So for ODD counts, OUT will be HIGH for (N
be HIGH. When a new initial count is written into the
timer, the counting sequence will begin. When the
initial count expires (decremented to 1), OUT will go
LOW for one CLK pulse and then go HIGH again.
e
LOW disables counting. GATE has no effect on
Again, GATE
e
OUT.
HIGH enables counting while GATE
a
b
1)/2 counts and LOW for (N
1)/2 counts.
After writing the Control Word and initial count, the
timer will be loaded on the next CLK pulse. This CLK
pulse does not decrement the count, so for an initial
5.3.5 MODE 4ÐINITIAL COUNT TRIGGERED
STROBE
a
count of N, OUT does not strobe LOW until N
CLK pulses after initial count is written.
1
This mode allows a strobe pulse to be generated by
writing an initial count to the timer. Initially, OUT will
If a new count is written during counting, it will be
loaded in the next CLK pulse and counting will con-
tinue from the new count.
271070–74
Figure 47. Mode 4
79
M82380
If a two-byte count is written, the following will occur:
1. Writing the first byte has no effect on counting.
by writing an initial count. Initially, OUT will be HIGH.
Counting is triggered by a rising edge of GATE.
When the initial count has expired (decremented to
1), OUT will go LOW for one CLK pulse and then go
HIGH again.
2. Writing the second byte allows the new count to
be loaded on the next CLK pulse.
a
OUT will strobe LOW N
1 CLK pulses after the
After loading the Control Word and initial count, the
Count Element will not be loaded until the CLK pulse
after a trigger. This CLK pulse does not decrement
the count. Therefore, for an initial count of N, OUT
new count of N is written. Therefore, when the
strobe pulse will occur after a trigger depends on the
value of the initial count loaded.
a
does not strobe LOW until N
trigger.
1 CLK pulses after a
5.3.6 MODE 5ÐGATE RETRIGGERABLE
STROBE
Mode 5 is very similar to Mode 4 except the count
sequence is triggered by the GATE signal instead of
271070–75
Figure 48. Mode 5
80
M82380
SUMMARY OF GATE OPERATIONS
GATE LOW or
GATE
HIGH
Mode
GATE Rising
No Effect
Going LOW
0
1
Disable Count
No Effect
Enable Count
No Effect
1. Initiate Count
2. Reset Output
After Next Clock
Initiate Count
2
3
1. Disable Count
2. Sets Output HIGH
Immediately
Enable Count
Enable Count
1. Disable Count
2. Sets Output HIGH
Immediately
Initiate Count
4
5
Disable Count
No Effect
No Effect
Initiate Count
Enable Count
No Effect
The counting sequence is retriggerable. Every trig-
ger will result in the timer being loaded with the initial
count on the next CLK pulse.
around’ to the highest count: either FFFF Hex for
binary counting or 9999 for BCD counting, and con-
tinues counting. Modes 2 and 3 are periodic. The
counter reloads itself with the initial count and con-
tinues counting from there.
If the new count is written during counting, the cur-
rent counting sequence will not be affected. If a trig-
ger occurs after the new count is written but before
the current count expires, the timer will be loaded
with the new count on the next CLK pulse and a new
count sequence will start from there.
The minimum and maximum initial count in each
counter depends on the mode of operation. They
are summarized below.
Mode
Min
Max
5.3.7 OPERATION COMMON TO ALL MODES
GATE
0
1
2
3
4
5
1
1
2
2
1
1
0
0
0
0
0
0
The GATE input is always sampled on the rising
edge of CLKIN. In Modes 0, 2, 3 and 4, the GATE
input is level sensitive. The logic level is sampled on
the rising edge of CLKIN. In Modes 1, 2, 3 and 5, the
GATE input is rising edge sensitive. In these modes,
a rising edge of GATE (trigger) sets an edge sensi-
tive flip-flop in the timer. The flip-flop is reset imme-
diately after it is sampled. This way, a trigger will be
detected no matter when it occurs; i.e., a HIGH logic
level does not have to be maintained until the next
rising edge of CLKIN. Note that in Modes 2 and 3,
the GATE input is both edge and level sensitive.
5.4 Register Set Overview
The Programmable Interval Timer module of the
M82380 contains a set of six registers. The port ad-
dress map of these registers is shown in Table 13.
Table 13. Timer Register Port Address Map
Port Address
Description
40H
41H
42H
43H
Counter 0 Register (read/write)
Counter 1 Register (read/write)
Counter 2 Register (read/write)
Control Word Register I
COUNTER
New counts are loaded and counters are decre-
mented on the falling edge of CLKIN. The largest
possible initial count is 0. This is equivalent to 2**16
for binary counting and 10**4 for BCD counting.
(Counter 0, 1 & 2) (write-only)
44H
45H
46H
47H
Counter 3 Register (read/write)
Reserved
Reserved
Control Word Register II
(Counter 3) (write-only)
Note that the counter does not stop when it reaches
zero. In Modes 0, 1, 4, and 5, the counter ‘wraps
81
M82380
ing Count Register. In general, the programming pro-
cedure is very flexible. Only two conventions need to
be remembered:
5.4.1 COUNTER 0, 1, 2, 3 REGISTERS
These four 8-bit registers are functionally identical.
They are used to write the initial count value into the
respective timer. Also, they can be used to read the
latched count value of a timer. Since they are 8-bit
registers, reading and writing of the 16-bit initial
count must follow the count format specified in the
Control Word Registers; i.e., least significant byte
only, most significant byte only, or least significant
byte then most significant byte (see Programming).
1. For each timer, the Control Word must be written
before the initial count is written.
2. The 16-bit initial count must follow the count for-
mat specified in the Control Word (least signifi-
cant byte only, most significant byte only, or least
significant byte first, followed by most significant
byte).
Since the two Control Word Registers and the four
Counter Registers have separate addresses, and
each timer can be individually selected by the appro-
priate Control Word Register, no special instruction
sequence is required. Any programming sequence
that follows the conventions above is acceptable.
5.4.2 CONTROL WORD REGISTER I & II
There are two Control Word Registers associated
with the Timer section. One of the two registers
(Control Word Register I) is used to control the oper-
ations of Counters 0, 1, and 2 and the other (Control
Word Register II) is for Counter 3. The major func-
tions of both Control Word Registers are listed be-
low:
A new initial count may be written to a timer at any
time without affecting the timer’s programmed mode
in any way. Count sequence will be affected as de-
scribed in the Modes of Operation section. Note that
the new count must follow the programmed count
format.
Ð Select the timer to be programmed.
Ð Define which mode the selected timer is to oper-
ate in.
Ð Define the count sequence; i.e., if the selected
timer is to count as a Binary Counter or a Binary
Coded Decimal (BCD) Counter.
If a timer is previously programmed to read/write
two-byte counts, the following precaution applies. A
program must not transfer control between writing
the first and second byte to another routine which
also writes into the same timer. Otherwise, the
read/write will result in incorrect count.
Ð Select the byte access sequence during timer
read/write operations; i.e., least significant byte
only, most significant byte only, or least signifi-
cant byte first, then most significant byte.
Whenever a Control Word is written to a timer, all
control logic for that timer(s) is immediately reset
(i.e., no CLK pulse is required). Also, the corre-
sponding output pin, TOUT), goes to a known initial
state.
Also, the Control Word Registers can be pro-
grammed to perform a Counter Latch Command or a
Read Back Command which will be described later.
5.5 Programming
5.5.2 READ OPERATION
Three methods are available to read the current
count as well as the status of each timer. They are:
Read Counter Registers, Counter Latch Command
and Read Back Command. Following is a descrip-
tion of these methods.
5.5.1 INITIALIZATION
Upon power-up or reset, the state of all timers is
undefined. The mode, count value, and output of all
timers are random. From this point on, how each
timer operates is determined solely by how it is pro-
grammed. Each timer must be programmed before it
can be used. Since the outputs of some timers can
generate interrupt signals to the M82380, all timers
should be initialized to a known state.
READ COUNTER REGISTERS
The current count of a timer can be read by perform-
ing a read operation on the corresponding Counter
Register. The only restriction of this read operation
is that the CLKIN of the timers must be inhibited by
Timers are programmed by writing a Control Word
into their respective Control Word Registers. Then,
an Initial Count can be written into the correspond-
82
M82380
using external logic. Otherwise, the count may be in
the process of changing when it is read, giving an
undefined result. Note that since all four timers are
sharing the same CLKIN signal, inhibiting CLKIN to
read a timer will unavoidably disable the other timers
also. This may prove to be impractical. Therefore, it
is suggested that either the Counter Latch Com-
mand or the Read Back Command be used to read
the current count of a timer.
Another feature of this Counter Latch Command is
that read and write operations of the same timer
may be interleaved. For example, if the timer is pro-
grammed for two-byte counts, the following se-
quence is valid.
1. Read least significant byte.
2. Write new least significant byte.
3. Read most significant byte.
4. Write new most significant byte.
Another alternative is to temporarily disable a timer
before reading its Counter Register by using the
GATE input. Depending on the mode of operation,
If a timer is programmed to read/write two-byte
counts, the following precaution applies. A program
must not transfer control between reading the first
and second byte to another routine which also reads
from that same timer. Otherwise, an incorrect count
will be read.
e
GATE
LOW will disable the counting operation.
However, this option is available on Timer 2 and 3
only, since the GATE signals of the other two timers
are internally enabled all the time.
COUNTER LATCH COMMAND
READ BACK COMMAND
A Counter Latch Command will be executed when-
ever a special Control Word is written into a Control
Word Register. Two bits written into the Control
Word Register distinguish this command from a ‘reg-
ular’ Control Word (see Register Bit Definition). Also,
two other bits in the Control Word will select which
counter is to be latched.
The Read Back Command is another special Com-
mand Word operation which allows the user to read
the current count value and/or the status of the se-
lected timer(s). Like the Counter Latch Command,
two bits in the Command Word identify this as a
Read Back Command (see Register Bit Definition).
The Read Back Command may be used to latch
multiple counter Output Latches (OL’s) by selecting
more than one timer within a Command Word. This
single command is functionally equivalent to several
Counter Latch Commands, one for each counter to
be latched. Each counter’s latched count will be
held until it is read by the M80386 or until the timer is
reprogrammed. The counter is automatically un-
latched when read, but other counters remain
latched until they are read. If multiple Read Back
commands are issued to the same timer without
reading the count, all but the first are ignored; i.e.,
the count read will correspond to the very first Read
Back Command issued.
Upon execution of this command, the selected
counter’s Output Latch (OL) latches the count at the
time the Counter Latch Command is received. This
count is held in the latch until it is read by the
M80386, or until the timer is reprogrammed. The
count is then unlatched automatically and the OL
returns to ‘following’ the Counting Element (CE).
This allows reading the contents of the counters ‘on
the fly’ without affecting counting in progress. Multi-
ple Counter Latch Commands may be used to latch
more than one counter. Each latched count is held
until it is read. Counter Latch Commands do not af-
fect the programmed mode of the timer in any way.
If a counter is latched, and at some time later, it is
latched again before the prior latched count is read,
the second Counter Latch Command is ignored. The
count read will then be the count at the time the first
command was issued.
As mentioned previously, the Read Back Command
may also be used to latch status information of the
selected timer(s). When this function is enabled, the
status of a timer can be read from the Counter Reg-
ister after the Read Back Command is issued. The
status information of a timer includes the following:
In any event, the latched count must be read ac-
cording to the programmed format. Specifically, if
the timer is programmed for two-byte counts, two
bytes must be read. However, the two bytes do not
have to be read right after the other. Read/write or
programming operations of other timers may be per-
formed between them.
1. Mode of timer:
This allows the user to check the mode of opera-
tion of the timer last programmed.
2. State of TOUT pin of the timer:
This allows the user to monitor the counter’s out-
put pin via software, possibly eliminating some
hardware from a system.
83
M82380
3. Null Count/Count available:
If both count and status of a timer are latched, the
first read operation of that timer will return the
latched status, regardless of which was latched first.
The next one or two (if two count bytes are to be
read) read operations return the latched count. Note
that subsequent read operations on the Counter
Register will return the unlatched count (like the first
read method discussed).
The Null Count Bit in the status byte indicates if
the last count written to the Count Register (CR)
has been loaded into the Counting Element (CE).
The exact time this happens depends on the
mode of the timer and is described in the Pro-
gramming section. Until the count is loaded into
the Counting Element (CE), it cannot be read from
the timer. If the count is latched or read before
this occurs, the count value will not reflect the
new count just written.
5.6 Register Bit Definitions
COUNTER 0, 1, 2, 3 REGISTER (READ/WRITE)
If multiple status latch operations of the timer(s) are
performed without reading the status, all but the first
command are ignored; i.e., the status read in will
correspond to the first Read Back Command issued.
Port Address
Description
40H
41H
42H
44H
45H
46H
Counter 0 Register (read/write)
Counter 1 Register (read/write)
Counter 2 Register (read/write)
Counter 3 Register (read/write)
Reserved
Both the current count and status of the selected
timer(s) may be latched simultaneously by enabling
both functions in a single Read Back Command.
This is functionally the same as issuing two separate
Read Back Commands at once. Once again, if multi-
ple read commands are issued to latch both the
count and status of a timer, all but the first command
will be ignored.
Reserved
271070–76
84
M82380
Note that these 8-bit registers are for writing and
reading of one byte of the 16-bit count value, either
the most significant or the least significant byte.
CONTROL WORD REGISTER II
CONTROL WORD REGISTER I & II (WRITE-ONLY)
Port Address
Description
43H
Control Word Register I
(Counter 0, 1, 2) (write-only)
Control Word Register II
(Counter 3) (write-only)
47H
CONTROL WORD REGISTER I
271070–78
COUNTER LATCH COMMAND FORMAT
(Write to Control Word Register)
271070–77
271070–79
Gate
Timer
Mode
Trigger
0
1
2
3
Edge Level
0
1
2
3
4
5
X
Interrupt on Terminal Count
Gate Retriggerable One Shot
Rate Generator
NA NA
j
j
X
X
X
X
X
X
Square Wave Generator
Initial Count Triggered Strobe
Gate Retriggerable Strobe
NA NA
j
j
X
e
e
j
NA
Must use Port 61 to generate L edge.
Not Applicable
85
M82380
READ BACK COMMAND FORMAT
(Write to Control Word Register)
271070–80
STATUS FORMAT
(Returned from Read Back Command)
271070–81
mode. Depending on the bus cycle type and the two
Wait State Control inputs (WSC 0–1), a pre-pro-
grammed number of wait states in the selected Wait
State Register will be generated.
6.0 WAIT STATE GENERATOR
6.1 Functional Description
The M82380 contains a programmable Wait State
Generator which can generate a pre-programmed
number of wait states during both CPU and DMA
initiated bus cycles. This Wait State Generator is ca-
pable of generating 1 to 16 wait states in non-pipe-
lined mode, and 0 to 15 wait states in pipelined
The Wait State Generator can also be disabled to
allow the use of devices capable of generating their
own READY signals. Figure 49 is a block diagram of
the Wait State Generator.
86
M82380
handled for access to the M82380 internal registers
and for the Refresh cycles. For M82380 internal reg-
ister access, READYO will be delayed to take into
account the command recovery time of the register.
One or more wait states will be generated in a pipe-
lined cycle. During refresh, the number of wait states
will be determined by the preprogrammed value in
the Refresh Wait State Register.
6.2 Interface Signals
The following describes the interface signals which
affect the operation of the Wait State Generator.
The READY, WSC0 and WSC1 signals are inputs.
READYO is the ready output signal to the host proc-
essor.
6.2.1 READY
In the simplest configuration, READYO can be con-
nected to the READY input of the M82380 and the
i386 CPU. This is, however, not always the case. If
external circuitry is to control the READY inputs as
well, additional logic will be required (see Application
Issues).
READY is an active LOW input signal which indi-
cates to the M82380 the completion of a bus cycle.
In the Master mode (e.g., M82380 initiated DMA
transfer), this signal is monitored to determine
whether a peripheral or memory needs wait states
inserted in the current bus cycle. In the Slave mode,
it is used (together with the ADS signal) to trace CPU
bus cycles to determine if the current cycle is pipe-
lined.
6.2.3 WSC(0–1)
These two Wait State Control inputs select one of
the three pre-programmed 8-bit Wait State Registers
which determines the number of wait states to be
generated. The most significant half of the three
Wait State Registers corresponds to memory ac-
cesses, the least significant half to I/O accesses.
6.2.2 READYO
READYO (Ready Out) is an active LOW output sig-
nal and is the output of the Wait State Generator.
The number of wait states generated depends on
the WSC(0–1) inputs. Note that special cases are
e
The combination WSC(0–1)
State Generator.
11 disables the Wait
271070–82
Figure 49. Wait State Generator Block Diagram
87
M82380
271070–83
Figure 50. Wait States in Non-Pipelined Cycles
rising edge of the next clock (M82384 CLK) after the
last state when ADS (Address Status) is asserted.
6.3 Bus Function
6.3.1 WAIT STATES IN NON-PIPELINED CYCLE
The number of wait states generated depends on
the type of bus cycle, and the number of wait states
requested. The various combinations are discussed
below.
The timing diagram of two typical non-pipelined cy-
cles with M82380 generated wait states is shown in
Figure 50. In this diagram, it is assumed that the
internal registers of the M82380 are not addressed.
During the first T2 state of each bus cycle, the Wait
State Control and the M/IO inputs are sampled to
determine which Wait State Register (if any) is se-
lected. If the WSC inputs are active (i.e., not both are
driven HIGH), the pre-programmed number of wait
states corresponding to the selected Wait State
Register will be requested. This is done by driving
the READYO output HIGH during the end of each T2
state.
1. Access the M82380 internal registers: 2 to 5 wait
states, depending upon the specific register ad-
dressed. Some back-to-back sequences to the In-
terrupt Controller will require 7 wait states.
2. Interrupt Acknowledge to the M82380: 5 wait
states.
3. Refresh: As programmed in the Refresh Wait
State Register (see Register Set Overview). Note
e
that if WSC(0–1)
tive.
11, READYO will stay inac-
4. Other bus cycles: Depending on WSC(0–1) and
M/IO inputs, these inputs select a Wait State
Register in which the number of wait states will be
equal to the pre-programmed wait state count in
the register plus 1. The Wait State Register selec-
tion is defined as follows (Table 14).
The WSC(0–1) inputs need only be valid during the
very first T2 state of each non-pipelined cycle. As a
general rule, the WSC inputs are sampled on the
88
M82380
Note that during HALT and SHUTDOWN, the num-
ber of wait states will depend on the WSC(0–1) in-
puts, which will select the memory half of one of the
Wait State Registers (see CPU Reset and Shutdown
Detect).
Table 14. Wait State Register Selection
Ý
M/IO
WSC(1–0)
Register Selected
0
0
0
1
1
1
X
00
01
10
00
01
10
11
WAIT REG 0 (I/O half)
WAIT REG 1 (I/O half)
WAIT REG 2 (I/O half)
WAIT REG 0 (MEM half)
WAIT REG 1 (MEM half)
WAIT REG 2 (MEM half)
Wait State Gen. Disabled
6.3.2 WAIT STATES IN PIPELINED CYCLE
The timing diagram of two typical pipelined cycles
with M82380 generated wait states is shown in Fig-
ure 52. Again, in this diagram, it is assumed that the
M82380 internal registers are not addressed. As de-
fined in the timing of the i386 processor, the Ad-
dress (A 2–31), Byte Enable (BE 0–3), and other
control signals (M/IO, ADS) are asserted one
T state earlier than in a non-pipelined cycle; i.e., they
are asserted at T2P. Similar to the non-pipelined
case, the Wait State Control (WSC) inputs are sam-
pled in the middle of the state after the last state
when the ADS signal is asserted. Therefore, the
WSC inputs should be asserted during the T1P state
of each pipelined cycle (which is one T state earlier
than in the non-pipelined cycle).
The Wait State Control signals, WSC(0–1), can be
generated with the address decode and the Read/
Write control signals as shown in Figure 51.
271070–84
Figure 51. WSC(0–1) Generation
271070–85
Figure 52. Wait State in Pipelined Cycles
89
M82380
The number of wait states generated in a pipelined
cycle is selected in a similar manner as in the non-
pipelined case discussed in the previous section.
The only difference here is that the actual number of
wait states generated will be one less than that of
the non-pipelined cycle. This is done automatically
by the Wait State Generator.
output is fed to the READY input of the M80386 and
the M82380 to indicate the completion of the current
bus cycle.
Similarly, the EXT. NOT READY (External Not
Ready) signal is used to delay the READY input of
the processor and the M82380. As long as this sig-
nal is driven HIGH, the output of the circuit will drive
the READY input HIGH. This will effectively extend
the duration of a bus cycle. However, it is important
to note that if the two-level logic is not fast enough
to satisfy the READY setup time, the OR gate should
be eliminated. Instead, the M82380 Wait State Gen-
erator can be disabled by driving both WSC(0–1)
HIGH. In this case, the addressed memory or I/O
device should activate the external READY input
whenever it is ready to terminate the current bus
cycle.
6.3.3 EXTENDING AND EARLY TERMINATING
BUS CYCLE
The M82380 allows external logic to either add wait
states or cause early termination of a bus cycle by
controlling the READY input to the M82380 and the
host processor. A possible configuration is shown in
Figure 53.
The EXTERNAL READY signal of Figure 53 allows
external devices to cause early termination of a bus
cycle. When this signal is asserted LOW, the output
of the circuit will also go LOW (even though the
READYO of the M82380 may still be HIGH). This
Figure 54 and 55 show the timing relationships of
the ready signals for the early termination and exten-
sion of the bus cycles. The Application Issues sec-
tion of this data sheet contains a detailed timing
analysis of the external circuit.
271070–86
Figure 53. External ‘READY’ Control Logic
271070–87
Figure 54. Early Termination of Bus Cycle by ‘READY’
90
M82380
271070–88
Figure 55. Extending Bus Cycle by ‘READY’
Due to the following implications, it should be noted WAIT STATE REGISTER 0, 1, 2
that early termination of bus cycles in which M82380
internal registers are accessed is not recommended.
These three 8-bit read/write registers are functional-
ly identical. They are used to store the pre-pro-
grammed wait state count. One half of each register
contains the wait state count for I/O accesses while
the other half contains the count for memory ac-
cesses. The total number of wait states generated
will depend on the type of bus cycle. For a non-pipe-
lined cycle, the actual number of wait states request-
ed is equal to the wait state count plus 1. For a
pipelined cycle, the number of wait states will be
equal to the wait state count in the selected register.
Therefore, the Wait State Generator is capable of
generating 1 to 16 wait states in non-pipelined
mode, and 0 to 15 wait states in pipelined mode.
1. Erroneous data may be read from or written into
the addressed register.
2. The M82380 must be allowed to recover either
before HLDA (Hold Acknowledge) is asserted or
before another bus cycle into an M82380 internal
register is initiated.
The recovery time, in bus periods, equals the re-
maining wait states that were avoided plus 4.
6.4 Register Set Overview
Altogether, there are four 8-bit internal registers as-
sociated with the Wait State Generator. The port ad-
dress map of these registers is shown below in Ta-
ble 15. A detailed description of each follows.
Note that the minimum wait state count in each reg-
ister is 0. This is equivalent to 0 wait states for a
pipelined cycle and 1 wait state for a non-pipelined
cycle.
Table 15. Register Address Map
REFRESH WAIT STATE REGISTER
Port Address
Description
72H
73H
74H
75H
Wait State Reg 0 (read/write)
Wait State Reg 1 (read/write)
Wait State Reg 2 (read/write)
Ref. Wait State Reg (read/write)
Similar to the Wait State Registers discussed above,
this 4-bit register is used to store the number of wait
states to be generated during the DRAM refresh cy-
cle. Note that the Refresh Wait State Register is not
selected by the WSC inputs. It will automatically be
91
M82380
chosen whenever a DRAM refresh cycle occurs. If
the Wait State Generator is disabled during the re-
e
inactive and the Refresh Wait State Register is ig-
fresh cycle (WSC(0–1)
11), READYO will stay
nored.
271070–89
6.5 Programming
REFRESH WAIT STATE REGISTER
Port Address: 75H (Read/Write)
Using the Wait State Generator is relatively straight-
forward. No special programming sequence is re-
quired. In order to ensure the expected number of
wait states will be generated when a register is se-
lected, the registers to be used must be pro-
grammed after power-up by writing the appropriate
wait state count into each register. Note that upon
hardware reset, all Wait State Registers are initial-
ized with the value FFH, giving the maximum num-
ber of wait states possible. Also, each register can
be read to check the wait state count previously
stored in the register.
271070–90
6.7 Application Issues
6.6 Register Bit Definition
WAIT STATE REGISTER 0, 1, 2
6.7.1 EXTERNAL ‘READY’ CONTROL LOGIC
Port Address
Description
As mentioned previously, wait state cycles generat-
ed by the M82380 can be terminated early or ex-
tended longer by means of additional external logic
(see Figure 53). In order to ensure that the READY
input timing requirement of the i386 processor and
the M82380 is satisfied, special care must be taken
when designing this external control logic. This sec-
tion addresses the design requirements.
72H
73H
74H
Wait State Register 0 (read/write)
Wait State Register 1 (read/write)
Wait State Register 2 (read/write)
92
M82380
A simplified block diagram of the external logic along
with the READY timing diagram is shown in Figure
56. The purpose is to determine the maximum delay
time allowed in the external control logic in order to
satisfy the READY setup time.
tions of the M82380, the maximum delay time for
valid READYO signal is 31 ns after the rising edge of
CLK2 in the beginning of T2 (for non-pipelined cycle)
or T2P (for pipelined cycle). Also, the minimum
READY setup time of the i386 processor and the
M82380 should be 20 ns before the rising edge of
CLK2 at the beginning of the next bus state. This
limits the total delay time for the external READY
First, it will be assumed that the i386 processor is
running at 16 MHz (i.e., CLK2 and 32 MHz). There-
fore, one bus state (two CLK2 periods) will be equiv-
alent to 62.5 nsec. According to the AC specifica-
b
b
to meet the READY setup timing requirement.
control logic to be 11 ns (62.5
31
21) in order
271070–91
e
e
e
e
a
e
62.5 ns
Maximum READYO Valid Delay
A
B
C
D
PHI1
PHI2
e
31 ns
e
READY Setup Time
Maximum Ready Control Logic Delay
21 ns
e
b
b
e
C 11 ns
A
B
Figure 56. ‘READY’ Timing Consideration
93
M82380
7.0 DRAM REFRESH CONTROLLER
7.1 Functional Description
7.2 Interface Signals
7.2.1 TOUT1/REF
The dual function output pin of TIMER 1 (TOUT1/
REF) can be programmed to generate DRAM Re-
fresh signal. If this feature is enabled, the rising edge
of TIMER 1 output (TOUT1) will trigger the DRAM
Refresh Request logic. After some delay for gaining
access of the bus, the M82380 DRAM Controller will
generate a DRAM Refresh signal by driving REF
output LOW. This signal is cleared after the refresh
cycle has taken place, or by a hardware reset.
The M82380 DRAM Refresh Controller consists of a
24-bit Refresh Address Counter and Refresh Re-
quest logic for DRAM refresh operations (see Figure
57). TIMER 1 can be used as a trigger signal to the
DRAM Refresh Request logic. The Refresh Bus Size
can be programmed to be 8-, 16-, or 32-bit wide.
Depending on the Refresh Bus Size, the Refresh
Address Counter will be incremented with the appro-
priate value after every refresh cycle. The internal
logic of the M82380 will give the Refresh operation
the highest priority in the bus control arbitration pro-
cess. Bus control is not released and re-requested if
the M82380 is already a bus master.
If the DRAM Refresh feature is disabled, the
TOUT1/REF output pin is simply the TIMER 1 out-
put. Detailed information of how TIMER 1 operates
is discussed in section 6ÐProgrammable Interval
Timer, and will not be repeated here.
271070–92
Figure 57. DRAM Refresh Controller
94
M82380
LOW. Then, the M82380 will relinquish the bus by
de-asserting HOLD. Typically, a Refresh Cycle with-
out wait states will take five bus states to execute. If
‘n’ wait states are added, the Refresh Cycle will last
for five plus ‘n’ bus states.
7.3 Bus Function
7.3.1 ARBITRATION
In order to ensure data integrity of the DRAMs, the
M82380 gives the DRAM Refresh signal the highest
priority in the arbitration logic. It allows DRAM Re-
fresh to interrupt a DMA in progress in order to per-
form the DRAM Refresh cycle. The DMA service will
be resumed after the refresh is done.
How often the Refresh Generation will initiate a re-
fresh cycle depends on the frequency of CLKIN as
well as TIMER1’s programmed mode of operation.
For this specific application, TIMER1 should be pro-
grammed to operate in Mode 2 or 3 to generate a
constant clock rate. See the section titled Program-
mable Interval Timer for more information on pro-
gramming the timer. One DRAM Refresh Cycle will
be generated each time TIMER 1 expires (when
TOUT1 changes to LOW to HIGH).
In case of a DRAM Refresh during a DMA process,
the cascaded device will be requested to get off the
bus. This is done by deasserting the EDACK signal.
Once DREQn goes inactive, the M82380 will per-
form the refresh operation. Note that the DMA con-
troller does not completely relinquish the system bus
during refresh. The Refresh Generator simply
‘steals’ a bus cycle between DMA accesses.
The Wait State Generator can be used to insert wait
states during a refresh cycle. The M82380 will auto-
matically insert the desired number of wait states as
programmed in the Refresh Wait State Register (see
Wait State Generator).
Figure 58 shows the timing diagram of a Refresh
Cycle. Upon expiration of TIMER 1, the M82380 will
try to take control of the system bus by asserting
HOLD. As soon as the M82380 see HLDA go active,
the DRAM Refresh Cycle will be carried out by acti-
vating the REF signal as well as the refresh address
and control signals on the system bus (Note that
REF will not be active until two CLK periods after
HLDA is asserted). The address bus will contain the
24-bit address currently in the Refresh Address
Counter. The control signals are driven the same
way as in a Memory Read cycle. This ‘read’ opera-
tion is complete when the READY signal is driven
7.4 Modes of Operation
7.4.1 WORD SIZE AND REFRESH
ADDRESS COUNTER
The M82380 supports 8-, 16- and 32-bit refresh cy-
cle. The bus width during a refresh cycle is program-
mable (see Programming). The bus size can be pro-
grammed via the Refresh Control Register (see Reg-
ister Overview). If the DRAM bus size is 8-, 16-, or
271070–93
*NOTE:
A24–A31
e
1 during Refresh cycle.
Figure 58. M82380 Refresh Cycle
95
M82380
32-bits, the Refresh Address Counter will be incre-
mented by 1, 2, or 4, respectively.
In addition to the above programming steps, it
should be noted that after reset, although the
TOUT1/REF becomes the Timer 1 output, the state
of this pin is undefined. This is because the Timer
module has not been initialized yet. Therefore, if this
output is used as a DRAM Refresh signal, this pin
should be disqualified by external logic until the Re-
fresh function is enabled. One simple solution is to
logically AND this output with HLDA, since HLDA
should not be active after reset.
The Refresh Address Counter is cleared by a hard-
ware reset.
7.5 Register Set Overview
The Refresh Generator has two internal registers to
control its operation. They are the Refresh Control
Register and the Refresh Wait State Register. Their
port address map is shown in Table 16 below.
7.7 Register Bit Definition
Table 16. Register Address Map
REFRESH CONTROL REGISTER
1CH
Port Address:
(Read/Write)
Port Address
Description
1CH
75H
Refresh Control Reg. (read/write)
Ref. Wait State Reg. (read/write)
The Refresh Wait State Register is not part of the
Refresh Generator. It is only used to program the
number of wait states to be inserted during a refresh
cycle. This register is discussed in detail in section 7
(Wait State Generator) and will not be repeated
here.
271070–94
REFRESH CONTROL REGISTER
8.0 RELOCATION REGISTER AND
ADDRESS DECODE
This 2-bit register serves two functions. First, it is
used to enable/disable the DRAM Refresh function
output. If disabled, the output of TIMER 1 is simply
used as a general purpose timer. The second func-
tion of this register is to program the DRAM bus size
for the refresh operation. The programmed bus size
also determines how the Refresh Address Counter
will be incremented after each refresh operation.
8.1 Relocation Register
All the integrated peripheral devices in the M82380
are controlled by a set of internal registers. These
registers span a total of 256 consecutive address
locations (although not all the 256 locations are
used). The M82380 provides a Relocation Register
which allows the user to map this set of internal reg-
isters into either the memory or I/O address space.
The function of the Relocation Register is to define
the base address of the internal register set of the
M82380 as well as if the registers are to be memory-
or I/O-mapped. The format of the Relocation Regis-
ter is depicted in Figure 59.
7.6 Programming
Upon hardware reset, the DRAM Refresh function is
disabled (the Refresh Control Register is cleared).
The following programming steps are needed before
the Refresh Generator can be used. Since the rate
of refresh cycles depends on how TIMER 1 is pro-
grammed, this timer must be initialized with the de-
sired mode of operation as well as the correct re-
fresh interval (see Programming Interval Timer).
Whether or not wait states are to be generated dur-
ing a refresh cycle, the Refresh Wait State Register
must also be programmed with the appropriate val-
ue. Then, the DRAM Refresh feature must be en-
abled and the DRAM bus width should be defined.
These can be done in one step by writing the appro-
priate control word into the Refresh Control Register
(see Register Bit Definition). After these steps are
done, the refresh operation will automatically be in-
voked by the Refresh Generator upon expiration of
Timer 1.
271070–95
Figure 59. Relocation Register
96
M82380
Note that the Relocation Register is part of the inter-
nal register set of the M82380. It has a port address
of 7FH. Therefore, any time the content of the Relo-
cation Register is changed, the physical location of
this register will also be moved. Upon reset of the
M82380, the content of the Relocation Register will
be cleared. This implies that the M82380 will re-
spond to its I/O addresses in the range of 0000H to
00FFH.
The M82380 will respond to memory addresses
in the range of 0A6XXXX00H to 0A6XXXXFFH
(where ‘X’ is don’t care).
This scheme implies that the internal register can be
located in any even, contiguous, 2**24 byte page of
the memory space.
8.2 Address Decoding
8.1.1 I/O-MAPPED M82380
As mentioned previously, the M82380 internal regis-
ters do not occupy the entire contiguous 256 ad-
dress locations. Some of the locations are ‘unoccu-
pied’. The M82380 always decodes the lower 8 ad-
dress bits (A0–A7) to determine if any one of its
registers is being accessed. If the address does not
correspond to any of its registers, the M82380 will
not respond. This allows external devices to be lo-
cated within the ‘holes’ in the M82380 address
space. Note that there are several unused address-
es reserved for future Intel peripheral devices.
As shown in Figure 59, Bit 0 of the Relocation Regis-
ter determines whether the M82380 registers are to
be memory-mapped or I/O-mapped. When Bit 0 is
set to ‘0’, the M82380 will respond to I/O Address-
es. Address signals BE0–BE3, A2–A7 will be used
to select one of the internal registers to be ac-
cessed. Bit 1 to Bit 7 of the Relocation Register will
correspond to A9 to A15 of the Address bus, respec-
tively. Together with A8 implied to be ‘0’, A15 to A8
will be fully decoded by the M82380. The following
shows how the M82380 is mapped into the I/O ad-
dress space.
9.0 CPU RESET AND SHUTDOWN
DETECT
Example
The M82380 will activate the CPURST signal to re-
set the host processor when one of the following
conditions occurs:
e
Relocation Register
11001110 (0CEH)
M82380 will respond to I/O address range
from 0CE00H to 0CEFFH.
Ð M82380 RESET is active;
Ð M82380 detects a i386 processor Shutdown cy-
cle (this feature can be disabled);
Therefore, this I/O mapping mechanism allows the
M82380 internal registers to be located on any even,
contiguous, 256 byte boundary of the system I/O
space.
Ð CPURST software command is issued to i386
processor.
Whenever the CPURST signal is activated, the
M82380 will reset its own internal Slave-Bus state
machine.
Port Address: 7FH
(Read/Write)
8.1.2 MEMORY-MAPPED M82380
When Bit 0 of the Relocation Register is set to ‘1’,
the M82380 will respond to memory addresses.
Again, Address signals BE0–BE3, A2–A7 will be
used to select one of the internal registers to be
accessed. Bit 1 to Bit 7 of the Relocation Register
will correspond to A25–A31, respectively. A24 is as-
sumed to be ‘0’, and A8–A23 are ignored. Consider
the following example.
9.1 Hardware Reset
Following a hardware reset, the M82380 will assert
its CPURST output to reset the host processor. This
output will stay active for as long as the RESET input
is active. During a hardware reset, the M82380 inter-
nal registers will be initialized as defined in the corre-
sponding functional descriptions.
Example
9.2 Software Reset
e
Relocation Register
10100111 (0A7H)
CPURST can be generated by writing the following
bit pattern into M82380 register location 64H.
D7
D0
1
e
1
Don’t Care
1
1
X
X
X
0
X
97
M82380
The Write operation into this port is considered as
an M82380 access and the internal Wait State Gen-
erator will automatically determine the required num-
ber of wait states. The CPURST will be active follow-
ing the completion of the Write cycle to this port.
This signal will last for 62 CLK2 periods. The
M82380 should not be accessed until the CPURST
is deactivated.
ware Reset, the M82380 will reset its Slave-Bus
state machine but will not change any of its internal
register contents.
10.0 INTERNAL CONTROL AND
DIAGNOSTIC PORTS
This internal port is Write-Only and the M82380 will
not respond to a Read operation to this location.
Also, during a CPU software reset command, the
M82380 will reset its Slave-Bus state machine. How-
ever, its internal registers remain unchanged. This
allows the operating system to distinguish a ‘warm’
reset by reading any M82380 internal register previ-
ously programmed for an non-default value. The Di-
agnostic registers can be used or this purpose (see
Internal Control and Diagnostic Ports).
10.1 Internal Control Port
The format of the Internal Control Port of the
M82380 is shown in Figure 60. This Control Port is
used to enable/disable the Processor Shutdown De-
tect mechanism as well as controlling the Gate in-
puts of the Timer 2 and 3. Note that this is a Write-
Only port. Therefore, the M82380 will not respond to
a read operation to this port. Upon hardware reset,
this port will be cleared; i.e., the Shutdown Detect
feature and the Gate inputs of Timer 2 and 3 are
disabled.
9.3 Shutdown Detect
The M82380 is constantly monitoring the Bus Cycle
Definition signals (M/IO, D/C, R/W) and is able to
detect when the i386 processor executes a Shut-
down bus cycle. Upon detection of a processor shut-
down, the M82380 will activate the CPURST output
for 62 CLK2 periods to reset the host processor.
This signal is generated after the Shutdown cycle is
terminated by the READY signal.
10.2 Diagnostic Ports
Two 8-bit read/write Diagnostic Ports are provided
in the M82380. These are two storage registers and
have no effect on the operation of the M82380. They
can be used to store checkpoint data or error codes
in the power-on sequence and in the diagnostic
service routines. As mentioned in CPU RESET AND
SHUTDOWN DETECT section, these Diagnostic
Ports can be used to distinguish between ‘cold’ and
‘warm’ reset. Upon hardware reset, both Diagnostic
Ports are cleared. The address map of these Diag-
nostic Ports is shown in Figure 61.
Although the M82380 Wait State Generator will not
automatically respond to a Shutdown (or Halt) cycle,
the Wait State Control inputs (WSC0, WSC1) can be
used to determine the number of wait states in the
same manner as other non-M82380 bus cycle.
Port
Address
This Shutdown Detect feature can be enabled or dis-
abled by writing a control bit in the Internal Control
Port at address 61H (see Internal Control and Diag-
nostic Ports). This feature is disabled upon a hard-
ware reset of the M82380. As in the case of Soft-
Diagnostic Port 1 (Read/Write)
Diagnostic Port 2 (Read/Write)
80H
88H
Figure 61. Address Map of Diagnostic Ports
Port Address: 61H (Write Only)
271070–96
Figure 60. Internal Control Port
98
M82380
and CDH. These addresses should not be used in
the system since the M82380 may respond to read/
write operations to these locations and bus conten-
tion may occur if any peripheral is assigned to the
same address location.
11.0 INTEL RESERVED I/O PORTS
There are eleven I/O ports in the M82380 address
space which are reserved for Intel future peripheral
device use only. Their address locations are: 2AH,
3DH, 3EH, 45H, 46H, 76H, 77H, 7DH, 7EH, CCH
271070–97
Figure 62. M82380 PGA PinoutÐView from TOP side
99
M82380
V
ple V
and GND connections must be made to multi-
CC
12.0 MECHANICAL DATA
12.1 Pin Assignment
and V
(GND) pins. Each V
MUST be connected to the appropriate voltage lev-
and V
CC
SS
CC SS
el. The circuit board should include V
planes for power distribution and all V
be connected to the appropriate plane.
and GND
pins must
CC
CC
The M82380 pinout as viewed from the top side of
the PGA component is shown in Figure 62. Its pinout
as viewed from the pin side of the component is
shown in Figure 63. The M82380 pinout as viewed
from the topside of the Quad Flat Pack component
is shown in Figure 64.
Table 17 shows the pin assignments for the PGA
component while Table 18 shows the pin assign-
ments for the Quad Flat Pack.
271070–98
Figure 63. M82380 PGA PinoutÐView from PIN side
100
M82380
Table 17. M82380 PGA PinoutÐFunctional Grouping
Pin
A7
C7
B7
A6
B6
C6
A5
B5
C5
B4
B3
C4
B2
C3
C2
D3
D2
E3
E2
E1
F3
F2
F1
G1
G2
G3
H1
H2
J1
Signal
A31
A30
A29
A28
A27
A26
A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
Pin
A8
Signal
D31
Pin
P12
M14
P1
Signal
Pin
L14
A1
Signal
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
CC
SS
B9
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
SS
SS
SS
SS
SS
SS
SS
SS
SS
A11
C11
D12
E13
F14
J13
B8
P13
N1
P2
P14
D1
N2
C1
C14
B1
A3
B14
A13
N14
A2
C9
A4
B11
B13
D13
E14
G12
H13
C8
A12
A14
P6
IRQ23
IRQ22
IRQ21
IRQ20
IRQ19
IRQ18
IRQ17
IRQ16
IRQ15
IRQ14
IRQ13
IRQ12
IRQ11
INT
N6
M7
N7
P7
G14
L12
K12
L13
K2
CLK2
D/C
W/R
M/IO
P8
A10
C10
C12
D14
F12
G13
K14
A9
ADS
M8
N8
P9
N4
NA
J12
M3
M6
P5
HOLD
HLDA
N9
M9
N10
P10
M2
DREQ0
DREQ1
DREQ2
DREQ3
DREQ4/IRQ9
DREQ5
DREQ6
DREQ7
A8
D8
N5
A7
D7
P4
A6
B10
B12
C13
E12
F13
H14
J14
D6
M5
P3
A5
D5
N11
K13
N13
M13
M11
H12
P11
M10
CLKIN
A4
D4
M4
N3
TOUT1/REF
TOUT2/IRQ3
TOUT3
A3
D3
H3
J2
A2
D2
BE3
BE2
BE1
BE0
D1
K3
L3
M1
L2
EOP
READY
J3
D0
EDACK0
EDACK1
EDACK2
READYO
WSC0
K1
L1
N12
M12
RESET
WSC1
CPURST
101
M82380
A wide variety of available sockets allow low inser-
tion force or zero insertion force mountings, and a
choice of terminals such as soldertail, surface
mount, or wire wrap.
12.2 Package Dimensions and
Mounting
The M82380 package is in a 132-pin ceramic Pin
Grid Array (PGA) (Figures 62 and 63) and 164-Lead
CQFP (Figure 64). The pins are arranged 0.100 inch
(2.54 mm) center-to-center, in a 14 x 14 matrix, three
rows around.
271070–B5
(Staggered pin arrangement is shown for clarity only. Actual package has pins of equal length.)
Figure 64. M8238 164-Lead CQFP Pinout (View from Top Side)
102
M82380
Table 18. M82380 CQFP Pin Cross-Reference
Pin
1
Signal
Pin
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
Signal
D23
D15
D7
Pin
83
Signal
D24
Pin
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
Signal
IRQ19
A4
2
V
V
84
D16
D8
IRQ20
IRQ21
IRQ22
IRQ23
CC
3
85
SS
4
A5
A6
A7
A8
A9
D30
86
D0
5
V
V
87
V
V
SS
CC
SS
CC
6
88
V
V
CC
7
D22
D14
D6
89
READYO
TOUT1/REF
HOLD
SS
8
90
DREQ0
DREQ1
DREQ2
DREQ3
DREQ4/IRQ9
DREQ5
NA
9
V
V
91
CC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
V
V
92
M/IO
SS
SS
CC
A10
A11
A12
A13
93
V
V
SS
CC
D29
D21
D13
D5
94
95
NC
96
NC
V
V
97
W/R
DREQ6
DREQ7
CC
SS
D28
D20
D12
98
D/C
A14
A15
A16
A17
NC
99
TOUT3
TOUT2/IRQ3
CPURST
NC
V
V
CC
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
SS
V
V
NC
CC
SS
NC
NC
NC
V
V
V
NC
CC
SS
CC
NC
NC
V
V
HLDA
INT
CC
CC
A18
A19
A20
A21
A22
D4
NC
D27
D19
D11
D3
V
V
NC
SS
CC
NC
READY
RESET
WSC1
WSC0
EDACU0
EDACU1
EDACU2
V
V
D26
D18
D10
D2
SS
CC
V
V
CC
A23
A24
A25
A26
A27
A28
A29
A30
A31
V
SS
SS
CLKIN
EOP
ADS
BE0
BE1
BE2
BE3
V
V
V
CC
SS
CC
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
IRQ16
IRQ17
IRQ18
D25
D17
D9
V
V
V
SS
CC
CLK2
SS
V
V
A2
A3
CC
SS
D31
D1
103
M82380
connects are recommended for the best reliability at
high frequencies. Low inductance capacitors are
available specifically for Pin Grid Array packages.
13.0 ELECTRICAL DATA
13.1 Power and Grounding
The large number of output buffers (address, data
and control) can cause power surges as multiple
output buffers drive new signal levels simultaneous-
13.3 Unused Pin Recommendations
For reliable operation, ALWAYS connect unused in-
puts to a valid logic level. As is the case with most
other CMOS processes, a floating input will increase
the current consumption of the component and give
an indeterminate state to the component.
ly. The 22 V
and V
pins of the M82380 each
CC
SS
feed separate functional units to minimize switching
induced noise effects. All V pins of the M82380
must be connected on the circuit board.
CC
13.4 ICETM-386 Support
13.2 Power Decoupling
The M82380 specifications provide sufficient drive
capability to support the ICE386. On the pins that
are generally shared between the i386 processor
and the M82380, the additional loading represented
by the ICE386 was allowed for in the design of the
M82380.
Liberal decoupling capacitance should be placed
close to the M82380. The M82380 driving its 32-bit
parallel address and data buses at high frequencies
can cause transient power surges when driving large
capacitiveloads.Lowinductancecapacitorsandinter-
104
M82380
only and functional operation at these or any other
conditions above those listed in the operational
sections of this specification is not implied.
13.5 Maximum Ratings
b
a
Storage Temperature ÀÀÀÀÀÀÀÀÀÀ 65 C to 150 C
§
§
Supply Voltage with Respect
to V ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 0.5V to 6.5V
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Al-
though the M82380 contains protective circuitry to
reset damage from static electric discharges, always
take precautions against high static voltages or elec-
tric fields.
b
a
SS
b
Voltage on any other Pin ÀÀÀÀÀ 0.5V to V
a
0.5V
CC
NOTE:
Stress above those listed above may cause perma-
nent damage to the device. This is a stress rating
OPERATING CONDITIONS
MIL-STD-883
Symbol
Description
Min
Max
Units
b
a
125
T
C
Case Temperature (Instant On)
Digital Supply Voltage
55
C
§
V
4.75
5.25
V
CC
Extended Temperature
Symbol
Description
Min
Max
Units
b
a
110
T
Case Temperature (Instant On)
Digital Supply Voltage
40
C
§
C
V
4.75
5.25
V
CC
Military Temperature Only (MTO)
Symbol
Description
Min
Max
Units
b
a
125
T
C
Case Temperature (Instant On)
Digital Supply Voltage
55
C
§
V
4.75
5.25
V
CC
105
M82380
13.6 DC Specifications (Over Specified Operating Conditions)
Symbol
Parameter
Input Low Voltage
Min
Max
0.8
a
Unit
V
Notes
b
V
V
V
V
V
0.3
IL
Input High Voltage
2.0
V
V
0.3
0.3
V
IH
CC
b
CLK2 Input Low Voltage
CLK2 Input High Voltage
Output Low Voltage
0.3
0.8
ILC
IHC
OL
a
2.0
V
CC
e
I
4 mA: A2–A31,
D0–D31
5 mA: All Others
OL
0.45
0.45
V
V
e
I
OL
V
Output High Voltage
e
OH
I
1 mA: A2–A31,
D0–D31
OH
2.4
2.4
V
V
e b
I
0.9 mA: All Others
OH
I
I
Input Leakage Current for
all inputs except:
LI
IRQ11–IRQ23, TOUT2/IRQ3,
EOP, DREQ4/IRQ9
k
k
k
k
g
15
mA
mA
0V
0V
V
V
V
V
IN
CC
CC
b
Input Leakage Current for
pins: IRQ11–IRQ23,
TOUT2/IRQ3, EOP,
DREQ4/IRQ9
10
10
300
LI1
IN
@
(Note 1) 16 MHz and 20 MHz
k
k
V
CC
b
325
mA
0V
V
IN
@
(Note 1) 25 MHz
k
k
V
g
I
I
Output Leakage Current
Supply Current
15
mA
0
V
LO
CC
IN
CC
e
CLK2
(Note 2)
375
mA
32 MHz
e
e
C
Capacitance (Input/IO)
CLK2 Capacitance
12
20
pF
pF
f
f
1 MHz
1 MHz
I
c
c
CCLK
NOTES:
1. These pins have internal pullups on them.
2. I is specified with inputs driven to CMOS levels. I
may be higher if driven to TTL levels.
CC
CC
106
M82380
AC spec measurement is defined in Figure 65. In-
puts must be driven to the levels shown when AC
specifications are measured. M82380 output delays
are specified with minimum and maximum limits,
which are measured as shown. The minimum
M82380 output delay times are hold times for exter-
nal circuitry. M82380 input setup and hold times are
specified as minimums and define the smallest ac-
ceptable sampling window. Within the sampling win-
dow, a synchronous input signal must be stable for
correct M82380 operation.
13.7 AC Specifications
The AC specifications given in the following tables
consist of output delays and input setup require-
ments. The AC diagram’s purpose is to illustrate the
clock edges from which the timing parameters are
measured. The reader should not infer any other tim-
ing relationships from them. For specific information
on timing relationships between signals, refer to the
appropriate functional section.
271070–A6
LEGEND:
A Ðmaximum output delay spec
B Ðminimum output delay spec
C Ðminimum input setup spec
D Ðminimum input hold spec
NOTES:
1. Input waveforms have tr
s
2.0 ns from 0.8V to 2.0V.
2. Under rated loading (120 pF) 386 output tr, tf is typically
s
4.0 ns from 0.8V to 2.0V.
Figure 65. Drive Levels and Measurement Points for AC Specification
107
M82380
AC SPECIFICATION TABLES (Over Specified Operating Conditions)
M82380-16
Min Max
Operating Frequency 4 MHz 16 MHz 4 MHz 20 MHz 4 MHz 25 MHz Half CLK2 Frequency
M82380-20
M82380-25
Symbol
Parameter
Notes
Min Max
Min Max
t1
CLK2 Period
31 ns 125 ns 25 ns 125 ns 20 ns 125 ns
t2a
t2b
t3a
t3b
t4
CLK2 High Time
CLK2 High Time
CLK2 Low Time
CLK2 Low Time
CLK2 Fall Time
CLK2 Rise Time
9
5
9
7
8
5
8
6
7
4
7
4
at 2.0V
at (V –0.8)V
CC
at 2.0V
at 0.8V
8
8
8
8
7
7
(V –0.8)V to 0.8V
CC
t5
0.8V to (V –0.8)V
CC
A (2–31), BE(0–3),
EDACK (0–2)
Valid Delay
e
(Note 1)
t6
t7
4
4
36
40
4
4
30
32
4
4
20
27
C
120 pF
L
Float Delay
A (2–31), BE(0–3)
Setup Time
Hold Time
t8
t9
6
4
6
4
6
4
W/R, M/IO, D/C,
Valid Delay
Float Delay
Setup Time
Hold Time
e
(Note 1)
t10
t11
t12
t13
6
4
6
4
33
35
6
4
6
4
28
30
4
4
6
4
20
29
C
75 pF
L
e
C
75 pF
L
e
e
t14
t15
t16
t17
ADS Valid Delay
Float Delay
Setup Time
Hold Time
6
4
33
35
6
4
28
30
4
4
19
29
C
C
75 pF
75 pF
L
L
21
4
15
4
12
4
Slave ModeÐ
D(0–31) Read
Valid Delay
e
(Note 1)
t18
t19
3
6
46
35
4
6
46
29
4
6
31
21
C
120 pF
L
Float Delay
Slave ModeÐ
D(0–31) Write
Setup Time
Hold Time
t20
t21
31
26
29
26
20
20
108
M82380
AC SPECIFICATION TABLES (Over Specified Operating Conditions) (Continued)
M82380-16
M82380-20
M82380-25
Symbol
Parameter
Notes
Min
Max
Min
Max
Min
Max
Master ModeÐ
D(0–31) Write
Valid Delay
e
(Note 1)
t22
t23
4
4
48
35
4
4
38
27
8
4
27
19
C
120 pF
L
Float Delay
Master ModeÐ
D(0–31) Read
Setup Time
t24
t25
11
6
11
6
7
4
Hold Time
t26
t27
READY Setup Time
Hold Time
21
4
12
4
9
4
t28
t29
WSC (0–1) Setup
Hold
6
21
6
21
6
15
t31
t30
RESET Setup Time
Hold Time
13
4
12
4
9
4
e
e
e
t32
t33
t34
READYO Valid Delay
CPU Reset From CLK2
HOLD Valid Delay
4
2
5
31
18
33
4
2
5
28
16
30
3
2
4
21
14
22
C
L
C
L
C
L
25 pF
50 pF
100 pF
t35
t36
HLDA Setup Time
Hold Time
21
6
17
6
17
4
t37a
t38a
t37b
t38b
t39
EOP Setup Time
EOP Hold Time
EOP Setup Time
EOP Hold Time
EOP Valid Delay
EOP Float Delay
21
4
17
4
13
4
Synch. EOP
Asynch. EOP
11
11
5
11
11
5
10
10
4
e
e
38
40
30
32
21
21
C
C
100 pF
100 pF
L
L
t40
5
5
4
t41a
t42a
DREQ Setup Time
Hold Time
21
4
19
4
17
4
Synchronous DREQ
Asynchronous DREQ
From IRQ Input
t41b
t42b
DREQ Setup Time
Hold Time
11
11
11
11
10
10
t43
INT Valid Delay
500
500
500
e
75 pF
15
C
L
t44
t45
NA Setup Time
Hold Time
11
15
10
15
7
8
t46
t47
t48
CLKIN Frequency
CLKIN High Time
CLKIN Low Time
0 MHz 10 MHz 0 MHz 10 MHz 0 MHz 10 MHz
30
50
30
50
30
50
At 2.0V
At 0.8V
NOTE:
1. Float conditions occur when the maximum output current becomes less than ILO in magnitude. Float delay is not tested.
For testing purposes, the float condition occurs when the dynamic output driven voltage changes with current loads.
109
M82380
AC SPECIFICATION TABLES (Over Specified Operating Conditions) (Continued)
M82380-16
M82380-20
M82380-25
Symbol
Parameter
Notes
Min
Max
10
Min
Max
10
Min
Max
10
b
t49
t50
t51
t52
t53
CLKIN Rise Time
CLKIN Fall Time
TOUT1/REF Valid
TOUT1/REF Valid
TOUT2 Valid Delay
0.8V to V
0.8V
CC
b
10
10
10
V
CC
0.8V to 0.8V
e
25 pF
4
3
3
36
4
3
3
30
4
3
3
20
From CLK2, C
From CLKIN
From CLKIN
L
93
93
90
93
93
90
(Falling Edge Only)
t54
t55
TOUT2 Float Delay
TOUT3 Valid Delay
3
3
40
93
3
3
40
93
3
3
37
90
From CLKIN
From CLKIN
NOTE:
1. Float conditions occur when the maximum output current becomes less than ILO in magnitude. Float delay is not tested.
For testing purposes, the float condition occurs when the dynamic output driven voltage changes with current loads.
271070–A7
Figure 66. AC Test Load
271070–A8
Figure 67. CLK2 Timing
All outputs loaded to 120 pF unless otherwise noted.
All AC Timings are tested at 1.5V threshold, except as noted.
110
M82380
271070–A9
Figure 68. Input Setup and Hold Timing
271070–B0
Figure 69. Reset Timing
111
M82380
271070–B1
Figure 70. Address Output Delays
271070–B2
Figure 71. Data Bus Output Delays
112
M82380
271070–B3
Figure 72. Control Output Delays
271070–B4
Figure 73. Timer Output Delays
113
M82380
APPENDIX A
Ports Listed by Address
Port Address (HEX)
Description
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1E
20
Read/Write DMA Channel 0 Target Address, A0–A15
Read/Write DMA Channel 0 Byte Count, B0–B15
Read/Write DMA Channel 1 Target Address, A0–A15
Read/Write DMA Channel 1 Byte Count, B0–B15
Read/Write DMA Channel 2 Target Address, A0–A15
Read/Write DMA Channel 2 Byte Count, B0–B15
Read/Write DMA Channel 3 Target Address, A0–A15
Read/Write DMA Channel 3 Byte Count, B0–B15
Read/Write DMA Channel 0–3 Status/Command I Register
Read/Write DMA Channel 0–3 Software Request Register
Write DMA Channel 0–3 Set-Reset Mask Register
Write DMA Channel 0–3 Mode Register I
Write Clear Byte-Pointer FF
Write DMA Master-Clear
Write DMA Channel 0–3 Clear Mask Register
Read/Write DMA Channel 0–3 Mask Register
Read/Write DMA Channel 0 Target Address, A24–A31
Read/Write DMA Channel 0 Byte Count, B16–B23
Read/Write DMA Channel 1 Target Address, A24–A31
Read/Write DMA Channel 1 Byte Count, B16–B23
Read/Write DMA Channel 2 Target Address, A24–A31
Read/Write DMA Channel 2 Byte Count, B16–B23
Read/Write DMA Channel 3 Target Address, A24–A31
Read/Write DMA Channel 3 Byte Count, B16–B23
Write DMA Channel 0–3 Bus Size Register
Read/Write DMA Channel 0–3 Chaining Register
Write DMA Channel 0–3 Command Register II
Write DMA Channel 0–3 Mode Register II
Read/Write Refresh Control Register
Reset Software Request Interrupt
Write Bank B ICW1, OCW2, or OCW3
Read Bank B Poll, Interrupt Request or In-Service
Status Register
21
Write Bank B ICW2, ICW3, ICW4 or OCW1
Read Bank B Interrupt Mask Register
Read Bank B ICW2
22
28
29
2A
2B
2C
2D
2E
2F
Read/Write IRQ8 Vector Register
Read/Write IRQ9 Vector Register
Reserved
Read/Write IRQ11 Vector Register
Read/Write IRQ12 Vector Register
Read/Write IRQ13 Vector Register
Read/Write IRQ14 Vector Register
Read/Write IRQ15 Vector Register
A-1
M82380
APPENDIX AÐPorts Listed by Address (Continued)
Port Address (HEX)
Description
30
Write Bank A ICW1, OCW2 or OCW3
Read Bank A Poll, Interrupt Request or In-Service
Status Register
31
Write Bank A ICW2, ICW3, ICW4 or OCW1
Read Bank A Interrupt Mask Register
Read Bank A ICW2
32
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
61
64
72
73
74
75
76
77
7D
7E
7F
80
81
82
83
87
88
89
8A
8B
8F
Read/Write IRQ0 Vector Register
Read/Write IRQ1 Vector Register
Read/Write IRQ1.5 Vector Register
Read/Write IRQ3 Vector Register
Read/Write IRQ4 Vector Register
Reserved
Reserved
Read/Write IRQ7 Vector Register
Read/Write Counter 0 Register
Read/Write Counter 1 Register
Read/Write Counter 2 Register
Write Control Word Register IÐCounter 0, 1, 2
Read/Write Counter 3 Register
Reserved
Reserved
Write Word Register IIÐCounter 3
Write Internal Control Port
Write CPU Reset Register (Data-1111XXX0H)
Read/Write Wait State Register 0
Read/Write Wait State Register 1
Read/Write Wait State Register 2
Read/Write Refresh Wait State Register
Reserved
Reserved
Reserved
Reserved
Read/Write Relocation Register
Read/Write Internal Diagnostic Port 0
Read/Write DMA Channel 2 Target Address, A16–A23
Read/Write DMA Channel 3 Target Address, A16–A23
Read/Write DMA Channel 1 Target Address, A16–A23
Read/Write DMA Channel 0 Target Address, A16–A23
Read/Write Internal Diagnostic Port 1
Read/Write DMA Channel 6 Target Address, A16–A23
Read/Write DMA Channel 7 Target Address, A16–A23
Read/Write DMA Channel 5 Target Address, A16–A23
Read/Write DMA Channel 4 Target Address, A16–A23
A-2
M82380
APPENDIX AÐPorts Listed by Address (Continued)
Port Address (HEX)
Description
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
Read/Write DMA Channel 0 Requester Address, A0–A15
Read/Write DMA Channel 0 Requester Address, A16–A31
Read/Write DMA Channel 1 Requester Address, A0–A15
Read/Write DMA Channel 1 Requester Address, A16–A31
Read/Write DMA Channel 2 Requester Address, A0–A15
Read/Write DMA Channel 2 Requester Address, A16–A31
Read/Write DMA Channel 3 Requester Address, A0–A15
Read/Write DMA Channel 3 Requester Address, A16–A31
Read/Write DMA Channel 4 Requester Address, A0–A15
Read/Write DMA Channel 4 Requester Address, A16–A31
Read/Write DMA Channel 5 Requester Address, A0–A15
Read/Write DMA Channel 5 Requester Address, A16–A31
Read/Write DMA Channel 6 Requester Address, A0–A15
Read/Write DMA Channel 6 Requester Address, A16–A31
Read/Write DMA Channel 7 Requester Address, A0–A15
Read/Write DMA Channel 7 Requester Address, A16–A31
Write Bank C ICW1, OCW2 or OCW3
Read Bank C Poll, Interrupt Request or In-Service
Status Register
A1
Write Bank C ICW2, ICW3, ICW4 or OCW1
Read Bank C Interrupt Mask Register
Read Bank C ICW2
A2
A8
A9
AA
AB
AC
AD
AE
AF
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
Read/Write IRQ16 Vector Register
Read/Write IRQ17 Vector Register
Read/Write IRQ18 Vector Register
Read/Write IRQ19 Vector Register
Read/Write IRQ20 Vector Register
Read/Write IRQ21 Vector Register
Read/Write IRQ22 Vector Register
Read/Write IRQ23 Vector Register
Read/Write DMA Channel 4 Target Address, A0–A15
Read/Write DMA Channel 4 Byte Count, B0–B15
Read/Write DMA Channel 5 Target Address, A0–A15
Read/Write DMA Channel 5 Byte Count, B0–B15
Read/Write DMA Channel 6 Target Address, A0–A15
Read/Write DMA Channel 6 Byte Count, B0–B15
Read/Write DMA Channel 7 Target Address, A0–A15
Read/Write DMA Channel 7 Byte Count, B0–B15
Read DMA Channel 4–7 Status/Command I Register
Read/Write DMA Channel 4–7 Software Request Register
Write DMA Channel 4–7 SetÐReset Mask Register
Write DMA Channel 4–7 Mode Register I
Reserved
Reserved
Write DMA Channel 4–7 Clear Mask Register
Read/Write DMA Channel 4–7 Mask Register
A-3
M82380
APPENDIX AÐPorts Listed by Address (Continued)
Port Address (HEX)
Description
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
Read/Write DMA Channel 4 Target Address, A24–A31
Read/Write DMA Channel 4 Byte Count, B16–B23
Read/Write DMA Channel 5 Target Address, A24–A31
Read/Write DMA Channel 5 Byte Count, B16–B23
Read/Write DMA Channel 6 Target Address, A24–A31
Read/Write DMA Channel 6 Byte Count, B16–B23
Read/Write DMA Channel 7 Target Address, A24–A31
Read/Write DMA Channel 7 Byte Count, B16–B23
Write DMA Channel 4–7 Bus Size Register
Read/Write DMA Channel 4–7 Chaining Register
Write DMA Channel 4–7 Command Register II
Write DMA Channel 4–7 Mode Register II
A-4
M82380
APPENDIX B
Ports Listed by Function
Port Address (HEX)
Description
DMA CONTROLLER
Write DMA Master-Clear
Write DMA Clear Byte-Pointer FF
0D
0C
08
C8
1A
DA
Read/Write DMA Channel 0–3 Status/Command I Register
Read/Write DMA Channel 4–7 Status/Command I Register
Write DMA Channel 0–3 Command Register II
Write DMA Channel 4–7 Command Register II
0B
CB
1B
DB
Write DMA Channel 0–3 Mode Register I
Write DMA Channel 4–7 Mode Register I
Write DMA Channel 0–3 Mode Register II
Write DMA Channel 4–7 Mode Register II
09
C9
1E
Read/Write DMA Channel 0–3 Software Request Register
Read/Write DMA Channel 4–7 Software Request Register
Reset Software Request Interrupt
0E
CE
0F
CF
0A
CA
Write DMA Channel 0–3 Clear Mask Register
Write DMA Channel 4–7 Clear Mask Register
Read/Write DMA Channel 0–3 Mask Register
Read/Write DMA Channel 4–7 Mask Register
Write DMA Channel 0–3 Set-Reset Mask Register
Write DMA Channel 4–7 Set-Reset Mask Register
18
D8
Write DMA Channel 0–3 Bus Size Register
Write DMA Channel 4–7 Bus Size Register
19
D9
Read/Write DMA Channel 0–3 Chaining Register
Read/Write DMA Channel 4–7 Chaining Register
00
87
10
01
11
90
91
Read/Write DMA Channel 0 Target Address, A0–A15
Read/Write DMA Channel 0 Target Address, A16–A23
Read/Write DMA Channel 0 Target Address, A24–A31
Read/Write DMA Channel 0 Byte Count, B0–B15
Read/Write DMA Channel 0 Byte Count, B16–B23
Read/Write DMA Channel 0 Requester Address, A0–A15
Read/Write DMA Channel 0 Requester Address, A16–A31
02
83
12
03
13
92
93
Read/Write DMA Channel 1 Target Address, A0–A15
Read/Write DMA Channel 1 Target Address, A16–A23
Read/Write DMA Channel 1 Target Address, A24–A31
Read/Write DMA Channel 1 Byte Count, B0–B15
Read/Write DMA Channel 1 Byte Count, B16–B23
Read/Write DMA Channel 1 Requester Address, A0–A15
Read/Write DMA Channel 1 Requester Address, A16–A31
B-1
M82380
APPENDIX BÐPorts Listed by Function (Continued)
Port Address (HEX)
Description
DMA CONTROLLER
04
81
14
05
15
94
95
Read/Write DMA Channel 2 Target Address, A0–A15
Read/Write DMA Channel 2 Target Address, A16–A23
Read/Write DMA Channel 2 Target Address, A24–A31
Read/Write DMA Channel 2 Byte Count, B0–B15
Read/Write DMA Channel 2 Byte Count, B16–B23
Read/Write DMA Channel 2 Requester Address, A0–A15
Read/Write DMA Channel 2 Requester Address, A16–A31
06
82
16
07
17
96
97
Read/Write DMA Channel 3 Target Address, A0–A15
Read/Write DMA Channel 3 Target Address, A16–A23
Read/Write DMA Channel 3 Target Address, A24–A31
Read/Write DMA Channel 3 Byte Count, B0–B15
Read/Write DMA Channel 3 Byte Count, B16–B23
Read/Write DMA Channel 3 Requester Address, A0–A15
Read/Write DMA Channel 3 Requester Address, A16–A31
C0
8F
D0
C1
D1
98
99
Read/Write DMA Channel 4 Target Address, A0–A15
Read/Write DMA Channel 4 Target Address, A16–A23
Read/Write DMA Channel 4 Target Address, A24–A31
Read/Write DMA Channel 4 Byte Count, B0–B15
Read/Write DMA Channel 4 Byte Count, B16–B23
Read/Write DMA Channel 4 Requester Address, A0–A15
Read/Write DMA Channel 4 Requester Address, A16–A31
C2
8B
D2
C3
D3
9A
9B
Read/Write DMA Channel 5 Target Address, A0–A15
Read/Write DMA Channel 5 Target Address, A16–A23
Read/Write DMA Channel 5 Target Address, A24–A31
Read/Write DMA Channel 5 Byte Count, B0–B15
Read/Write DMA Channel 5 Byte Count, B16–B23
Read/Write DMA Channel 5 Requester Address, A0–A15
Read/Write DMA Channel 5 Requester Address, A16–A31
C4
89
Read/Write DMA Channel 6 Target Address, A0–A15
Read/Write DMA Channel 6 Target Address, A16–A23
Read/Write DMA Channel 6 Target Address, A24–A31
Read/Write DMA Channel 6 Byte Count, B0–B15
Read/Write DMA Channel 6 Byte Count, B16–B23
Read/Write DMA Channel 6 Requester Address, A0–A15
Read/Write DMA Channel 6 Requester Address, A16–A31
D4
C5
D5
9C
9D
C6
8A
D6
C7
D7
9E
9F
Read/Write DMA Channel 7 Target Address, A0–A15
Read/Write DMA Channel 7 Target Address, A16–A23
Read/Write DMA Channel 7 Target Address, A24–A31
Read/Write DMA Channel 7 Byte Count, B0–B15
Read/Write DMA Channel 7 Byte Count, B16–B23
Read/Write DMA Channel 7 Requester Address, A0–A15
Read/Write DMA Channel 7 Requester Address, A16–A31
B-2
M82380
APPENDIX BÐPorts Listed by Function (Continued)
Port Address (HEX)
Description
INTERRUPT CONTROLLER
20
Write Bank B ICW1, OCW2, or OCW3
Read Bank B Poll, Interrupt Request or In-Service
Status Register
21
Write Bank B ICW2, ICW3, ICW4 or OCW1
Read Bank B Interrupt Mask Register
Read Bank B ICW2
22
28
29
2A
2B
2C
2D
2E
2F
Read/Write IRQ8 Vector Register
Read/Write IRQ9 Vector Register
Reserved
Read/Write IRQ11 Vector Register
Read/Write IRQ12 Vector Register
Read/Write IRQ13 Vector Register
Read/Write IRQ14 Vector Register
Read/Write IRQ15 Vector Register
A0
Write Bank C ICW1, OCW2 or OCW3
Read Bank C Poll, Interrupt Request or In-Service
Status Register
A1
Write Bank C ICW2, ICW3, ICW4 or OCW1
Read Bank C Interrupt Mask Register
Read Bank C ICW2
A2
A8
A9
AA
AB
AC
AD
AE
AF
Read/Write IRQ16 Vector Register
Read/Write IRQ17 Vector Register
Read/Write IRQ18 Vector Register
Read/Write IRQ19 Vector Register
Read/Write IRQ20 Vector Register
Read/Write IRQ21 Vector Register
Read/Write IRQ22 Vector Register
Read/Write IRQ23 Vector Register
30
Write Bank A ICW1, OCW2 or OCW3
Read Bank A Poll, Interrupt Request oor In-Service
Status Register
31
Write Bank A ICW2, ICW3, ICW4 or OCW1
Read Bank A Interrupt Mask Register
Read Bank A ICW2
32
38
39
3A
3B
3C
3D
3E
3F
Read/Write IRQ0 Vector Register
Read/Write IRQ1 Vector Register
Read/Write IRQ1.5 Vector Register
Read/Write IRQ3 Vector Register
Read/Write IRQ4 Vector Register
Reserved
Reserved
Read/Write IRQ7 Vector Register
B-3
M82380
APPENDIX BÐPorts Listed by Function (Continued)
Port Address (HEX)
Description
PROGRAMMABLE INTERVAL TIMER
Read/Write Counter 0 Register
40
41
42
43
44
47
Read/Write Counter 1 Register
Read/Write Counter 2 Register
Write Control Word Register IÐCounter 0, 1, 2
Read/Write Counter 3 Register
Write Word Register IIÐCounter 3
CPU RESET
Write CPU Reset Register (Data-1111XXX0H)
64
WAIT STATE GENERATOR
72
73
74
75
Read/Write Wait State Register 0
Read/Write Wait State Register 1
Read/Write Wait State Register 2
Read/Write Refresh Wait State Register
DRAM REFRESH CONTROLLER
Read/Write Refresh Control Register
INTERNAL CONTROL AND DIAGNOSTIC PORTS
1C
61
80
88
Write Internal Control Port
Read/Write Internal Diagnostic Port 0
Read/Write Internal Diagnostic Port 1
RELOCATION REGISTER
Read/Write Relocation Register
INTEL RESERVED PORTS
7F
2A
3D
3E
45
46
76
77
7D
7E
CC
CD
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
B-4
M82380
APPENDIX C
Pin Descriptions
The M82380 provides all of the signals necessary to
D0–D31
I/O
DATA BUS
interface it to an i386 processor. It has separate
32-bit address and data buses. It also has a set of
control signals to support operation as a bus master
or a bus slave. Several special function signals exist
on the M82380 for interfacing the system support
peripherals to their respective system counterparts.
Following are the definitions of the individual pins of
the M82380. These brief descriptions are provided
as a reference. Each signal is further defined within
the sections which describe the associated M82380
function.
This is the 32-bit data bus. These pins are active
outputs during interrupt acknowledges, during Slave
accesses, and when the M82380 is in the Master
mode.
CLK2
I
PROCESSOR CLOCK
This pin must be connected to CLK2. The M82380
monitors the phase of this clock in order to remain
synchronized with the i386 processor. This clock
drives all of the internal synchronous circuitry.
A2-A31
I/O
ADDRESS BUS
D/C
I/O
DATA/CONTROL
This is the 32-bit address bus. The addresses are
doubleword memory and I/O addresses. These are
three-state signals which are active only during Mas-
ter mode. The address lines should be connected
directly to the i386’s local bus.
D/C is used to distinguish between i386 processor
control cycles and DMA or i386 processor data ac-
cess cycles. It is active as an output only in the Mas-
ter mode.
BE0
I/O
BYTE-ENABLE 0
W/R
I/O
WRITE/READ
BE0 active indicates that data bits D0–D7 are being
accessed or are valid. It is connected directly to the
i386’s BE0. The byte enable signals are active out-
puts when the M82380 is in the Master mode.
W/R is used to distinguish between write and read
cycles. It is active as an output only in the Master
mode.
M/IO
I/O
MEMORY/IO
BE1
I/O
BYTE-ENABLE 1
M/IO is used to distinguish between memory and IO
accesses. It is active as an output only in the Master
mode.
BE1 active indicates that data bits D8–D15 are be-
ing accessed or are valid. It is connected directly to
the i386’s BE1. The byte enable signals are active
only when the M82380 is in the Master mode.
ADS
I/O
ADDRESS STATUS
BE2
I/O
BYTE-ENABLE 2
This signal indicates presence of a valid address on
the address bus. It is active as output only in the
Master mode. ADS is active during the first T-state
where addresses and control signals are valid.
BE2 active indicates that data bits D15–D23 are be-
ing accessed or are valid. It is connected directly to
the i386’s BE2. The byte enable signals are active
only when the M82380 is in the Master mode.
NA
I
NEXT ADDRESS
BE3
I/O
BYTE-ENABLE 3
Asserted by a peripheral or memory to begin a pipe-
lined address cycle. This pin is monitored only while
the M82380 is in the Master mode. In the Slave
mode, pipelining is determined by the current and
past status of the ADS and READY signals.
BE3 active indicates that data bits D24–D31 are be-
ing accessed or are valid. The byte enable signals
are active only when the M82380 is in the Master
mode. This pin should be connected directly to the
i386’s BE3. This pin is used for factory testing and
must be low during reset. The M80386 drives BE3
low during reset.
C-1
M82380
HOLD
O
HOLD REQUEST
EOP must be connected to a pull-up resistor. This
will prevent erroneous external requests for termina-
tion of a DMA process.
This is an active-high signal to the i386 processor to
request control of the system bus. When control is
granted, the i386 processor activates the hold ac-
knowledge signal (HLDA).
EDACK (0–2)
EDGE
O
ENCODED DMA ACKNOWL-
HLDA
I
HOLD ACKNOWLEDGE
These signals contain the encoded acknowledge-
ment of a request for DMA service by a peripheral.
The binary code formed by the three signals indi-
cates which channel is active. Channel 4 does not
have a DMA acknowledge. The inactive state is indi-
cated by the code 100. During a Requester access,
EDACK presents the code for the active DMA chan-
nel. During a Target access, EDACK presents the
inactive code 100.
This input signal tells the DMA controller that the
i386 processor has relinquished control of the sys-
tem bus to the DMA controller.
DREQ (0–3, 5–7)
I
DMA REQUEST
The DMA Request inputs monitor requests from pe-
ripherals requiring DMA service. Each of the eight
DMA channels has one DREQ input. These active-
high inputs are internally synchronized and priori-
tized. Upon reset, channel 0 has the highest priority
and channel 7 the lowest.
IRQ (11–23)
I
INTERRUPT REQUEST
These are active low interrupt request inputs. The
inputs can be programmed to be edge or level sensi-
tive. Interrupt priorities are programmable as either
fixed or rotating. These inputs have weak internal
pull-up resistors. Unused interrupt request inputs
should be tied inactive externally.
DREQ4/IRQ9
QUEST
I
DMA/INTERRUPT
RE-
This is the DMA request input for channel 4. It is also
connected to the interrupt controller via interrupt re-
quest 9. This internal connection is available for
DMA channel 4 only. The interrupt input is active low
and can be programmed as either edge of level trig-
gered. Either function can be masked by the appro-
priate mask register. Priorities of the DMA channel
and the interrupt request are not related but follow
the rules of the individual controllers.
INT
O
INTERRUPT OUT
INT signals the i386 processor that an interrupt re-
quest is pending.
CLKIN
I
TIMER CLOCK INPUT
This is the clock input signal to all of the M82380’s
programmable timers. It is independent of the sys-
tem clock input (CLK2).
Note that this pin has a weak internal pull-up. This
causes the interrupt request to be inactive, but the
DMA request will be active if there is no external
connection made. Most applications will require that
either one or the other of these functions be used,
but not both. For this reason, it is advised that DMA
channel 4 be used for transfers where a software
request is more appropriate (such as memory-to-
memory transfers). In such an application, DREQ4
can be masked by software, freeing IRQ9 for other
purposes.
TOUT1/REF
O
TIMER 1 OUTPUT/REFRESH
This pin is software programmable as either the di-
rect output of Timer 1, or as the indicator of a refresh
cycle in progress. As REF, this signal is active during
the memory read cycle which occurs during refresh.
TOUT2/IRQ3 I/O TIMER
RUPT REQUEST3
2 OUTPUT/INTER-
EOP
I/O
END OF PROCESS
This is the inverted output of Timer 2. It is also con-
nected directly to interrupt request 3. External hard-
ware can use IRQ3 if Timer 2 is programmed as
As an output, this signal indicates that the current
Requester access is the last access of the currently
operating DMA channel. It is activated when Termi-
nal Count is reached. As an input, it signals the DMA
channel to terminate the current buffer and proceed
to the next buffer, if one is available. This signal may
be programmed as an asynchronous or synchro-
nous input.
e
e
OUT 0 (TOUT2 1)
TOUT3
This is the inverted output of Timer 3.
O
TIMER 3 OUTPUT
C-2
M82380
READY
I
READY INPUT
RESET
I
RESET
This active-low input indicates to the M82380 that
the current bus cycle is complete. READY is sam-
pled by the M82380 both while it is in the Master
mode, and while it is in the Slave mode.
This synchronous input serves to initialize the state
of the M82380 and provides basis for the CPURST
output. RESET must be held active for at least 15
CLK2 cycles in order to guarantee the state of the
M82380. After Reset, the M82380 is in the Slave
mode with all outputs except timers and interrupts in
their inactive states. The state of the timers and in-
terrupt controller must be initialized through soft-
ware. This input must be active for the entire time
required by the i386 processor to guarantee proper
reset.
WSC (0–1)
I
WAIT STATE CONTROL
WSC0 AND WSC1 are inputs used by the Wait-State
Generator to determine the number of wait states
required by the currently accessed memory or I/O.
The binary code on these ins, combined with the
M/IO signal, selects an internal register in which a
e
wait-state count is stored. The combination WSC
11 disables the wait-state generator.
CPURST
O
CPU RESET
CPURST provides a synchronized reset signal for
the CPU. It is activated in the event of a software
reset command, an i386 processor shut-down de-
tect, or a hardware reset via the RESET pin. The
M82380 holds CPURST active for 62 clocks in re-
sponse to either a software reset command or a
shut-down detection. Otherwise CPURST reflects
the RESET input.
READYO
O
READY OUTPUT
This is the synchronized output of the wait-state
generator. It is also valid during i386 processor ac-
cesses to the M82380 in the Slave Mode when the
M82380 requires wait states. READYO should feed
directly the i386 processor’s READY input.
a
V
CC
V
SS
5V input power
Ground
Table 18. Wait-State Select Inputs
Wait-State Registers
Port
Select Inputs
Address
D7
D4
D3
D0
WSC1
WSC0
72H
73H
74H
Memory 0
Memory 1
Memory 2
I/O 0
I/O 1
I/O 2
0
0
1
1
0
1
1
1
DISABLED
M/IO
1
0
C-3
M82380
APPENDIX D
M82380 System Notes
M82380 TIMER UNIT SYSTEM NOTES
Solution
The M82380 DMA controller with Integrated System
Peripherals is functionally inconsistent with the data
sheet. This document explains the behavior of the
M82380 Timer Unit and outlines subsequent limita-
tions of the timer unit. This document also provides
recommended workarounds.
As long as software algorithms are aware of this be-
havior, there should be no problems, as the external
signal behaves correctly.
Long Term Plans
Currently, Intel has no plans to fix this behavior of
the M82380 timer unit.
Overview
There are two areas in which the M82380 timer unit
exhibits non-specified behavior:
WRITE CYCLES TO THE M82380
TIMER UNIT
1. Mode 0 operation
2. Write Cycles to the M82380 Timer Unit
This errata applies only to SLAVE WRITE cycles to
the M82380 timer unit. During these cycles, the data
being written into the M82380 timer unit may be cor-
rupted if CLKIN is not inhibited during a certain ‘‘win-
dow’’ of the write cycle.
MODE 0 OPERATION
Description
Description
For Mode 0 operation, the M82380 timer is specified
as follows:
Please refer to Figure 1.
‘‘1. Writing the first byte disables counting,
OUT is set LOW immediately . . . ’’
During write cycles to the M82380 timer unit, the
M82380 translates the 386DX interface signals such
as ADS, W/R, M/IO, and D/C into several internal
signals that control the operation of the internal sub-
blocks (e.g., Timer Unit).
Due to mode 0 errata, this should read as follows:
‘‘1. Writing the first byte sets OUT LOW imme-
diately. If the counter has not yet expired, writ-
ing the first byte also disables counting. How-
ever, if the counter has expired, writing the first
count does not disable counting, although
OUT still behaves correctly (set LOW immedi-
ately).’’
The M82380 timer unit is controlled by such internal
signals. These internal signals are generated and
sampled with respect to two separate clock signals:
CLK2 (the system clock) and CLKIN (the M82380
timer unit clock).
Since the CLKIN and CLK2 clock signals are used
internally to generate control signals for the inter-
face to the timer unit, some timing parameters must
be met in order for the interface logic to function
properly.
Consequences
Software errors will occur if algorithms depend on
the M82380 timer unit to stop counting after writing
the first byte. Thus, software that is based on the
M8254 core will not function reliably on the M82380
timer unit.
Those timing parameters are met by inhibiting the
CLKIN signal for a specific window during Write Cy-
cles to the M82380 Timer Unit.
Note, however, that the external signal of the timer
behaves correctly.
The CLKIN signal must be inhibited using external
logic, as the GATE function of the M82380 timer unit
is not guaranteed to totally inhibit CLKIN.
D-1
M82380
The proposed solution provides a certain amount of
system ‘‘guardband’’ to make sure that this window
is avoided.
Consequences
This CLKIN inhibit circuitry guarantees proper write
cycles to the M82380 timer unit.
PAL equations for a suggested workaround are also
included. Please refer to the comments in the PAL
codes for stated assumptions of this particular work-
around. A state diagram (Figure 3) is provided to
help clarify how this PAL is designed.
Without this solution, write cycles to the M82380 tim-
er unit could place corrupted data into the timer unit
registers. This, in turn, could yield inaccurate results
and improper timer operation.
Figure 4 shows how this PAL would fit into a system
workaround. In order to show the effect of this work-
around on the CLKIN signal, Figure 5 shows how
CLKIN is inhibited. Note that you must still meet the
The proposed solution would involve a hardware
modification for existing systems.
CLKIN AC timing parameters (e.g., t
(min), t
(min)) in order for the timer unit to function properly.
47
48
Solution
A timing waveform (Figure 2) shows the specific win-
dow during which CLKIN must be inhibited. Please
note that CLKIN must only be inhibited during the
window shown in Figure 2. This window is defined by
two AC timing parameters:
Please note that this workaround has not been test-
ed. It is provided as a suggested solution. Actual
solutions will vary from system to system.
e
e
t
9 ns
a
b
Long Term Plans
t
28 ns
Intel has no plans to fix this behavior in the M82380
timer unit.
module Timer 82380 Fix
flag ’-r2’,’-q2’,’-f1’, ’-t4’, ’-w1,3,6,5,4,16,7,12,17,18,15,14’
title ’M82380 Timer Unit CLKIN
INHIBIT signal PAL Solution ’
Timer Unit Fix device ’P16R6’;
‘This PAL inhibits the CLKIN signal (that comes from an oscillator)
‘during Slave Writes to the M82380 Timer unit.
‘
‘ASSUMPTION:
‘
‘
‘
‘
‘
‘
‘
This PAL assumes that an external system address
decoder provides a signal to indicate that an 82380
Timer Unit access is taking place. This input
signal is called TMR in this PAL. This PAL also
assumes that this TMR signal occurs during a
specific T-State. Please see Figure 3 of this
document to see when this signal is expected to
be active by this PAL.
‘
‘
‘NOTE:
‘
‘
This PAL does not support pipelined 82380 SLAVE
cycles.
‘(c) Intel Corporation 1989. This PAL is provided as a proposed
‘method of solving a certain M82380 Timer Unit problem. This PAL
‘has not been tested or validated. Please validate this solution
‘for your system and application.
‘
D-2
M82380
‘Input Pins‘
CLK2
RESET
TMR
pin
pin
pin
1; ‘System Clock
2; ‘Microprocessor RESET signal
3; ‘Input from Address Decoder, indicating
‘an access to the timer unit of the
‘82380.
!RDY
!ADS
CLK
W R
nc1
pin
pin
pin
pin
pin
pin
pin
pin
pin
4; ‘End of Cycle indicator
5; ‘Address and control strobe
6; ‘PHI2 clock
7; ‘Write/Read Signal‘
8; ‘No Connect 0‘
9; ‘No Connect 1‘
10; ‘Tied to ground, documentation only
11; ‘Output enable, documentation only
12; ‘Input–CLKIN directly from oscillator
nc3
GNDa
GNDb
CLKIN IN
‘Output Pins‘
Q 0
pin
18; ‘Internal signal only, fed back to
‘PAL logic‘
CLKIN OUT
INHIBIT
S0
pin
pin
pin
pin
17; ‘CLKIN signal fed to 82380 Timer Unit
16; ‘CLKIN Inhibit signal
15; ‘Unused State Indicator Pin
14; ‘Unused State Indicator Pin
S1
‘Declarations‘
Valid ADS 4 ADS & CLK
Valid RDY 4 RDY & CLK
Timer Acc 4 TMR & CLK
; ‘ADS# sampled in PHI1 of 386DX T-State
; ‘RDY# sampled in PHI1 of 386DX T-State
; ‘Timer Unit Access, as provided by
‘external Address Decoder ‘
State Diagram [INHIBIT, S1, S0]
state 000:
if RESET then 000
else if Valid ADS & W R then 001
else 000;
state 001:
if RESET then 000
else if Timer Acc then 010
else if !Timer Acc then 000
else 001;
state 010:
state 110:
if RESET then 000
else if CLK then 110
else 010;
if RESET then 000
else if CLK then 111
else 110;
D-3
M82380
state 111:
if RESET then 000
else if CLK then 011
else 111;
state 011:
if RESET then 000
else if Valid RDY then 000
else 011;
state 100:
state 101:
EQUATIONS
if RESET then 000
else 000;
if RESET then 000
else 000;
Q 0 :4 CLKIN IN ; ‘Latched incoming clock. This signal is used
‘internally to feed into the MUX-ing logic‘
CLKIN OUT :4 (INHIBIT & CLKIN OUT & !RESET)
0(!INHIBIT & Q 0 & !RESET);
‘Equation for CLKIN OUT. This
‘feeds directly to the 82380 Timer Unit.‘
END
Page 1
ABEL(tm) 3.10 - Document Generator 30-June 89 03:17
PM
82380 Timer Unit CLKIN
INHIBIT signal PAL Solution
Equations for Module Timer 82380 Fix
Device Timer Unit Fix
- Reduced Equations:
!INHIBIT :4 (!CLK & !INHIBIT # CLK & S0 # RESET # !S1);
!S1 :4 (RESET
# INHIBIT & !S1
# CLK & !INHIBIT & ! RDY & S0 & S1
E
# !CLK & !S1
# !S1 & !TMR
# !S0 & !S1);
!S0 :4 (RESET
# INHIBIT & !S1
E
# CLK & !INHIBIT & ! RDY & S1
# !CLK & !S0
# !INHIBIT & !S0 & S1
# S0 & !S1
# !S1 & !W R
E
#
ADS & !S1);
D-4
M82380
!Q 0 :4 (!CLKIN IN);
!CLKIN OUT :4 (RESET # !CLKIN OUT & INHIBIT # !INHIBIT & !Q 0);
Page 2
ABEL(tm) 3.10 - Document Generator 30-June 89 03:17
PM
82380 Timer Unit CLKIN
INHIBIT signal PAL Solution
Chip diagram for Module Timer 82380 Fix
Device Timer Unit Fix
P16R6
271070–B6
end of module Timer 82380 Fix
271070–B7
Figure 1. Translation of i386TM DX Signals to Internal M82380 Timer Unit Signals
D-5
M82380
Figure 2. M82380 Timer Unit Write Cycle
D-6
M82380
[
]
INHIBIT, S1, S0
271070–B9
Figure 3. State Diagram for Inhibit Signal
271070–C0
NOTE:
This solution does not support pipelined M82380 SLAVE Cycles.
Figure 4. System with M82380 Timer Unit ‘‘Inhibit’’ Circuitry
D-7
M82380
271070–C1
Figure 5(a). Inhibited CLKIN in an M82380 Timer Unit and CLKIN Minimum HIGH Time
271070–C2
Figure 5(b). Inhibited CLKIN in an M82380 Timer Unit and CLKIN Minimum LOW Time
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