GT28F800F3T120_技术文档

PRODUCT PREVIEW

E

FAST BOOT BLOCK

FLASH MEMORY FAMILY

8 AND 16 MBIT

28F800F3, 28F160F3

Includes Extended and Automotive Temperature Specifications

High Performance

Supports Code Plus Data Storage

Optimized for Flash Data Integrator

(FDI) Software

54 MHz Effective Zero Wait-State

Performance

Synchronous Burst-Mode Reads

Asynchronous Page-Mode Reads

Fast Program Suspend Capability

Fast Erase Suspend Capability

SmartVoltage Technology

Flexible Blocking Architecture

Eight 4-Kword Blocks for Data

32-Kword Main Blocks for Code

Top or Bottom Configurations

Available

2.7 V−3.6 V Read and Write

Operations for Low Power Designs

12 V V_PPFast Factory Programming

Flexible I/O Voltage

1.65 V I/O Reduces Overall System

Power Consumption

5 V-Safe I/O Enables Interfacing to

5 V Devices

Extended Cycling Capability

Minimum 10,000 Block Erase Cycles

Guaranteed

Low Power Consumption

Enhanced Data Protection

Absolute Write Protection with

V_PP= GND

Automatic Power Savings Mode

Decreases Power Consumption

Automated Program and Block Erase

Algorithms

Block Locking

Block Erase/Program Lockout

during Power Transitions

Command User Interface for

Automation

Density Upgrade Path

8- and 16-Mbit

Status Register for System

Feedback

Manufactured on ETOX™ V Flash

Technology

Industry-Standard Packaging

56-Lead SSOP

µBGA* CSP

Intel’s Fast Boot Block memory family renders high performance asynchronous page-mode and synchronous

burst reads making it an ideal memory solution for burst CPUs. Combining high read performance with the

intrinsic non-volatility of flash memory, this flash memory family eliminates the traditional redundant memory

paradigm of shadowing code from a slow nonvolatile storage source to a faster execution memory for

improved system performance. Therefore, it reduces the total memory requirement which helps increase

reliability and reduce overall system power consumption and cost.

This family of products is manufactured on Intel’s 0.4 µm ETOX™ V process technology. They are available

in industry-standard packages: the µBGA* CSP, ideal for board-constrained applications, and the rugged

56-lead SSOP.

May 1998

Order Number: 290644-001

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or

otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of

Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to

sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or

infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life

saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

The 28F800F3, 28F160F3 may contain design defects or errors known as errata which may cause the product to deviate from

published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be

obtained from:

Intel Corporation

P.O. Box 5937

Denver, CO 80217-9808

or call 1-800-548-4725

or visit Intel’s Website at http://www.intel.com

CG-041493

*Third-party brands and names are the property of their respective owners

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FAST BOOT BLOCK DATASHEET

CONTENTS

PAGE

1.0 INTRODUCTION .............................................5

5.0 DATA PROTECTION.....................................26

5.1 V_PP= V_ILfor Complete Protection ..............26

5.2 WP# = V_ILfor Block Locking ......................26

5.3 WP# = V_IHfor Block Unlocking...................26

1.2 Product Overview.........................................5

2.0 PRODUCT DESCRIPTION..............................6

2.1 Pinouts.........................................................6

2.2 Pin Description.............................................6

2.3 Memory Blocking Organization.....................9

2.3.1 Parameter Blocks..................................9

2.3.2 Main Blocks...........................................9

6.0 V_PPVOLTAGES ............................................26

7.0 POWER CONSUMPTION..............................26

7.1 Active Power ..............................................26

7.2 Automatic Power Savings ..........................26

7.3 Standby Power...........................................27

7.4 Power-Up/Down Operation.........................27

7.4.1 RST# Connection ................................27

7.4.2 V_CC, V_PPand RST# Transitions...........27

7.5 Power Supply Decoupling ..........................27

7.5.1 V_PPTrace on Printed Circuit Boards....27

3.0 PRINCIPLES OF OPERATION .....................12

3.1 Bus Operations ..........................................12

3.1.1 Read....................................................12

3.1.2 Output Disable.....................................12

3.1.3 Standby...............................................12

3.1.4 Write....................................................12

3.1.5 Reset...................................................13

8.0 ELECTRICAL SPECIFICATIONS .................28

4.0 COMMAND DEFINITIONS ............................13

4.1 Read Array Command................................15

4.2 Read Identifier Codes Command ...............15

4.3 Read Status Register Command................15

4.4 Clear Status Register Command................15

4.5 Block Erase Command ..............................15

4.6 Program Command....................................17

4.7 Block Erase Suspend/Resume Command .17

4.8 Program Suspend/Resume Command.......17

4.9 Set Read Configuration Command.............19

4.9.1 Read Configuration..............................19

4.9.2 Frequency Configuration .....................20

4.9.3 Data Output Configuration...................20

4.9.4 WAIT# Configuration ...........................20

4.9.5 Burst Sequence...................................20

4.9.6 Clock Configuration .............................20

4.9.7 Burst Length........................................20

8.1 Absolute Maximum Ratings........................28

8.2 Extended Temperature Operating

Conditions.................................................28

8.3 Capacitance...............................................29

8.4 DC Characteristics—Extended

Temperature..............................................30

8.5 AC Characteristics—Read-Only

—

Operations Extended Temperature.........32

8.6 AC Characteristics—Write Operations—

Extended Temperature..............................38

8.7 AC Characteristics—Reset Operation—

Extended Temperature..............................40

8.8 Extended Temperature Block Erase and

Program Performance...............................41

8.9 Automotive Temperature Operating

Conditions.................................................41

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9.0 ORDERING INFORMATION..........................46

10.0 ADDITIONAL INFORMATION.....................47

8.10 Capacitance.............................................42

8.11 DC Characteristics—Automotive

Temperature..............................................43

8.12 AC Characteristics—Read-Only

Operations—Automotive Temperature......44

8.13 Automotive Temperature Frequency

Configuration Settings...............................45

8.14 Automotive Temperature Block Erase and

Program Performance...............................45

REVISION HISTORY

Date of

Revision

Version

Description

05/12/98

-001

Original version

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FAST BOOT BLOCK DATASHEET

block erase and program operations at 2.7 V

1.0 INTRODUCTION

(3.3 V for automotive temperature) and 12 V V_PP

.

The 12 V V_PPoption renders the fastest program

performance to increase factory programming

throughput. With the 2.7 V (3.3 V for automotive

temperature) V_PPoption, V_CCand V_PPcan be tied

together for a simple, low power design. In addition

to the voltage flexibility, the dedicated V_PPpin gives

This datasheet contains 8- and 16-Mbit Fast Boot

Block memory information. Section 1.0 provides a

flash memory overview. Sections 2.0 through 8.0

describe the memory functionality and electrical

specifications for extended and automotive

temperature product offerings.

complete data protection when V_PP≤ V_PPLK

.

The flexible input/output (I/O) voltage capability

helps reduce system power consumption and

simplify interfacing to sub 2.7 V and 5 V CPUs.

Powered by V_CCQpins, the I/O buffers can operate

at a lower voltage than the flash memory core. With

V_CCQvoltage at 1.65 V, the I/Os swing between

GND and 1.65 V, reducing I/O power consumption

by 65% over standard 3 V flash memory

components. The low voltage and 5 V-safe feature

also helps ease CPU interfacing by adapting to the

CPU’s bus voltage.

1.2

Product Overview

The Fast Boot Block flash memory family provides

density upgrades with pinout compatibility for 8- and

16-Mbit densities. This family of products are high

performance, low voltage memories with a 16-bit

data bus and individually erasable blocks. These

blocks are optimally sized for code and data

storage. Eight 4-Kword parameter blocks are

positioned at either the top (denoted by -T suffix) or

bottom (denoted by -B suffix) of the address map.

The rest of the device is grouped into

32-Kword main blocks. The upper two (or lower

two) parameter and all main blocks can be locked

for complete code protection.

The device’s Command User Interface (CUI) serves

as the interface between the system processor and

internal flash memory operation. A valid command

sequence written to the CUI initiates device

automation. This automation is controlled by an

internal Write State Machine (WSM) which

automatically executes the algorithms and timings

necessary for block erase and program operations.

The status register provides WSM feedback by

signifying block erase or program completion and

status.

The device’s optimized architecture and interface

dramatically increases read performance beyond

previously

attainable

levels.

It

supports

asynchronous page-mode and synchronous burst

reads from main blocks (parameter blocks support

single asynchronous and synchronous reads).

Upon initial power-up or return from reset, the

device defaults to a page-mode read configuration.

Page-mode read configuration is ideal for non-clock

memory systems and is compatible with page-

mode ROM. Synchronous burst reads are enabled

by writing to the read configuration register. In

synchronous burst mode, the CLK input increments

an internal burst address generator, synchronizes

the flash memory with the host CPU, and outputs

data on every rising (or falling) CLK edge up to

54 MHz (25 MHz for automotive temperature). An

output signal, WAIT#, is also provided to ease CPU

Block erase and program automation allows erase

and program operations to be executed using an

industry-standard two-write command sequence. A

block erase operation erases one block at a time,

and data is programmed in word increments. Erase

suspend allows system software to suspend an

ongoing block erase operation in order to read from

or program data to any other block. Program

suspend allows system software to suspend an

ongoing program operation in order to read from

any other location.

to

flash

memory

communication

and

synchronization during continuous burst operations.

Fast Boot Block flash memory devices offer two low

power savings features: Automatic Power Savings

(APS) and standby mode. The device automatically

enters APS mode following the completion of a read

cycle. Standby mode is initiated when the system

deselects the device by driving CE# inactive or

RST# active. RST# also resets the device to read

array, provides write protection, and clears the

status register. Combined, these two features

significantly reduce power consumption.

In addition to the enhanced architecture and

interface, this family of products incorporates

SmartVoltage technology which enables fast factory

programming and low power designs. Specifically

designed for low voltage systems, Fast Boot Block

flash memory components support read operations

at 2.7 V (3.3 V for automotive temperature) V_CCand

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2.0 PRODUCT DESCRIPTION

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to the 16-Mbit density. The family is available in

µBGA CSP and 56-lead SSOP packages. Pinouts

for the 8- and 16-Mbit components are illustrated in

Figures 1 and 2.

This section describes the pinout and block

architecture of the device family.

2.2

Pin Description

2.1

Pinouts

The pin description table describes pin usage.

Intel’s Fast Boot Block flash memory family

provides upgrade paths in each package pinout up

1

2

3

4

5

6

7

8

9

10

A

B

C

D

E

F

A₁₅

A₁₄

A₁₂

A₁₁

GND CLK

V_CC

V_PP

A₄

A₅

A₁

A₂

32M

16M

A₈

A₉

A₂₀

ADV# WE#

RST# WP#

A₁₉

A₁₇

A₇

64M

A₁₃

A₁₀

A₂₁

A₁₈

A₆

A₃

V_CCQ

DQ₇

DQ₁₅

DQ₁₃DQ₁₂

DQ₄

V_CC

DQ₁₁DQ₁₀

DQ₉

DQ₁

DQ₈

DQ₀

OE#

GND

CE#

A₀

A₁₆

DQ₆

DQ₅

DQ₃

DQ₂

WAIT# GND DQ₁₄GND

V_CCQ

NOTES:

1. Shaded connections indicate upgrade address connections. Lower density devices will not have upper address solder

balls. Routing is not recommended in this area.

2. A₂₀and A₂₁are the upgrade address for potential 32-Mbit and 64-Mbit devices (currently not on road map).

3. Reference the Micro Ball Grid Array Package Mechanical Specification and Media Informationon Intel’s World Wide Web

home page for detailed package specifications.

Figure 1. 56-Ball µBGA* Package Pinout (Top View, Ball Down)

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FAST BOOT BLOCK DATASHEET

16-Mbit 8-Mbit

8-Mbit 16-Mbit

V_CC

CLK

ADV#

GND

NC

V_CC

CLK

ADV#

GND

NC

1

2

3

4

5

6

7

8

56

55

54

53

52

51

50

49

WE#

RST#

V_PP

WP#

NC

A₁

A₂

A₃

WE#

RST#

V_PP

WP#

A₁₉

A₁

A₂

A₃

A₁₅

A₁₄

A₁₃

A₁₅

A₁₄

A₁₃

A₁₂

A₁₁

A₁₀

A₉

A₈

9

A₁₂

A₁₁

A₁₀

A₉

A₈

NC

GND

DQ₆

DQ₁₄

DQ₇

DQ₁₅

GND

V_CCQ

A₁₆

WAIT#

DQ₁₃

DQ₅

DQ₁₂

DQ₄

V_CC

A₄

A₅

A₆

A₇

A₁₇

A₁₈

DQ₉

DQ₁

DQ₈

DQ₀

OE#

GND

CE#

A₀

A₄

A₅

A₆

A₇

A₁₇

A₁₈

DQ₉

DQ₁

DQ₈

DQ₀

OE#

GND

CE#

A₀

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

56-Lead SSOP

16 mm x 23.7 mm

NC

GND

DQ₆

DQ₁₄

DQ₇

DQ₁₅

GND

V_CCQ

A₁₆

WAIT#

DQ₁₃

DQ₅

DQ₁₂

DQ₄

V_CC

TOP VIEW

NC

V_CCQ

DQ₂

DQ₁₀

DQ₃

DQ₁₁

V_CCQ

DQ₂

DQ₁₀

DQ₃

DQ₁₁

Figure 2. SSOP Pinout

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Table 1. Pin Descriptions

Name and Function

Sym

Type

A₀–A₁₉

INPUT

ADDRESS INPUTS: Inputs for addresses during read and write operations.

Addresses are internally latched during read and write cycles.

8-Mbit: A_0–18, 16-Mbit: A_0–19

DQ₀–

DQ₁₅

INPUT/ DATA INPUT/OUTPUTS: Inputs data and commands during write cycles, outputs

OUTPUT data during memory array, status register (DQ₀–DQ₇), and identifier code read

cycles. Data pins float to high-impedance when the chip is deselected or outputs

are disabled. Data is internally latched during a write cycle.

CLK

INPUT

CLOCK: Synchronizes the flash memory to the system operating frequency during

synchronous burst-mode read operations. When configured for synchronous burst-

mode reads, address is latched on the first rising (or falling, depending upon the

read configuration register setting) CLK edge when ADV# is active or upon a rising

ADV# edge, whichever occurs first. CLK is ignored during asynchronous page-

mode read and write operations.

ADV#

INPUT

ADDRESS VALID: Indicates that a valid address is present on the address inputs.

Addresses are latched on the rising edge of ADV# during read and write

operations. ADV# may be tied active during asynchronous read and write

operations.

CE#

INPUT

CHIP ENABLE: Activates the device’s control logic, input buffers, decoders, and

sense amplifiers. CE#-high deselects the device and reduces power consumption

to standby levels.

RST#

RESET: When driven low, RST# inhibits write operations which provides data

protection during power transitions, and it resets internal automation. RST#-high

enables normal operation. Exit from reset sets the device to asynchronous read

array mode.

OE#

WE#

INPUT

OUTPUT ENABLE: Gates data outputs during a read cycle.

WRITE ENABLE: Controls writes to the CUI and array. Addresses and data are

latched on the rising edge of the WE# pulse.

WP#

INPUT

WRITE PROTECTION: Provides a method for locking and unlocking all main

blocks and two parameter blocks.

When WP# is at logic low, lockable blocks are locked. If a program or erase

operation is attempted on a locked block, SR.1 and either SR.4 [program] or SR.5

[block erase] will be set to indicate the operation failed.

When WP# is at logic high, the lockable blocks are unlocked and can be

programmed or erased.

WAIT#

OUTPUT WAIT: Provides data valid feedback when configured for synchronous burst-mode

and the burst length is set to continuous. This signal is gated by OE# and CE# and

is internally pull-up to V_CCQvia a resistor. WAIT# from several components can be

tied together to form one system WAIT# signal.

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FAST BOOT BLOCK DATASHEET

Table 1. Pin Descriptions

Name and Function

Sym

Type

V_PP

SUPPLY BLOCK ERASE AND PROGRAM POWER SUPPLY (2.7 V–3.6 V,

11.4 V–12.6 V): For erasing array blocks or programming data, a valid voltage

must be applied to this pin. With V_PP≤ V_PPLK, memory contents cannot be altered.

Block erase and program with an invalid V_PPvoltage should not be attempted.

Applying 11.4 V–12.6 V to V_PPcan only be done for a maximum of 1000 cycles on

main blocks and 2500 cycles on the parameter blocks. V_PPmay be connected to

12 V for a total of 80 hours maximum (see Section 6.0 for details).

V_CC

SUPPLY DEVICE POWER SUPPLY (2.7 V–3.6 V): With V_CC≤ V_LKO, all write attempts to

the flash memory are inhibited. Device operations at invalid V_CCvoltages should

not be attempted.

V_CCQ

SUPPLY OUTPUT POWER SUPPLY (1.65 V–2.5 V, 2.7 V–3.6 V): Enables all outputs to be

driven to 1.65 V to 2.5 V or 2.7 V to 3.6 V. When V_CCQequals 1.65 V–2.5 V, V_CC

voltage must not exceed 3.3 V and should be regulated to 2.7 V–2.85 V to achieve

lowest power operation (see DC Characteristics for detailed information).

This input may be tied directly to V_CC

.

GND

NC

SUPPLY GROUND: Do not float any ground pins.

NO CONNECT: Lead is not internally connected; it may be driven or floated.

normally be stored in an EEPROM. By using

software techniques, the word-rewrite functionality

2.3

Memory Blocking Organization

of EEPROMs can be emulated. Each 8- and

16-Mbit device contains eight 4-Kwords

(4,096-words) parameter blocks.

The Fast Boot Block flash memory family is an

asymmetrically-blocked architecture that enables

system integration of code and data within a single

flash device. For the address locations of each

block, see the memory maps in Figure 3 (top boot

blocking) and Figure 4 (bottom boot blocking).

2.3.2

MAIN BLOCKS

After the parameter blocks, the remainder of the

array is divided into equal size main blocks for code

and/or data storage. The 8-Mbit device contains

fifteen 32-Kword (32,768-word) main blocks, and

the 16-Mbit device contains thirty-one 32-Kword

(32,768-word) main blocks.

2.3.1

PARAMETER BLOCKS

The Fast Boot Block flash memory architecture

includes parameter blocks to facilitate storage of

frequently updated small parameters that would

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8-Mbit

16-Mbit

Address Range

Block 38

Block 37

Block 36

Block 35

Block 34

Block 33

Block 32

Block 31

4-KWord

FF000h - FFFFFh

FE000h - FEFFFh

FD000h - FDFFFh

FC000h - FCFFFh

FB000h - FBFFFh

FA000h - FAFFFh

F9000h - F9FFFh

F8000h - F8FFFh

Block 22

Block 21

4-KWord

7F000h - 7FFFFh

7E000h - 7EFFFh

Block 20

Block 19

Block 18

Block 17

Block 16

Block 15

4-KWord

7D000h - 7DFFFh

7C000h - 7CFFFh

7B000h - 7BFFFh

7A000h - 7AFFFh

79000h - 79FFFh

78000h - 78FFFh

32-KWord

70000h - 77FFFh

68000h - 6FFFFh

60000h - 67FFFh

58000h - 5FFFFh

50000h - 57FFFh

48000h - 4FFFFh

40000h - 47FFFh

38000h - 3FFFFh

30000h - 37FFFh

28000h - 2FFFFh

20000h - 27FFFh

18000h - 1FFFFh

10000h - 17FFFh

08000h - 0FFFFh

00000h - 07FFFh

32-KWord

F0000h - F7FFFh

E8000h - EFFFFh

E0000h - E7FFFh

D8000h - DFFFFh

D0000h - D7FFFh

C8000h - CFFFFh

C0000h - C7FFFh

B8000h - BFFFFh

B0000h - B7FFFh

A8000h - AFFFFh

A0000h - A7FFFh

98000h - 9FFFFh

90000h - 97FFFh

88000h - 8FFFFh

80000h - 87FFFh

78000h - 7FFFFh

70000h - 77FFFh

68000h - 6FFFFh

60000h - 67FFFh

58000h - 5FFFFh

50000h - 57FFFh

48000h - 4FFFFh

40000h - 47FFFh

38000h - 3FFFFh

30000h - 37FFFh

28000h - 2FFFFh

20000h - 27FFFh

18000h - 1FFFFh

10000h - 17FFFh

08000h - 0FFFFh

00000h - 07FFFh

Block 14

Block 13

Block 12

Block 11

Block 10

Block 9

Block 30

Block 29

Block 28

Block 27

Block 26

Block 25

Block 24

Block 8

Block 7

Block 6

Block 5

Block 4

Block 3

Block 2

Block 1

Block 0

Block 23

Block 22

Block 21

Block 20

Block 19

Block 18

Block 17

Block 16

Block 15

Block 14

Block 13

Block 12

Block 11

Block 10

Block 9

Block 8

Block 7

Block 6

Block 5

Block 4

Block 3

Block 2

Block 1

Block 0

Figure 3. 8- and 16-Mbit Top Boot Memory Map

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FAST BOOT BLOCK DATASHEET

16-Mbit

Address Range

32-KWord

F8000h - FFFFFh

Block 38

Block 37

Block 36

Block 35

Block 34

F0000h - F7FFFh

E8000h - EFFFFh

E0000h - E7FFFh

D8000h - DFFFFh

D0000h - D7FFFh

C8000h - CFFFFh

C0000h - C7FFFh

B8000h - BFFFFh

B0000h - B7FFFh

A8000h - AFFFFh

A0000h - A7FFFh

98000h - 9FFFFh

90000h - 97FFFh

88000h - 8FFFFh

80000h - 87FFFh

78000h - 7FFFFh

70000h - 77FFFh

68000h - 6FFFFh

60000h - 67FFFh

58000h - 5FFFFh

50000h - 57FFFh

48000h - 4FFFFh

40000h - 47FFFh

38000h - 3FFFFh

30000h - 37FFFh

28000h - 2FFFFh

20000h - 27FFFh

18000h - 1FFFFh

10000h - 17FFFh

08000h - 0FFFFh

Block 33

Block 32

Block 31

Block 30

Block 29

Block 28

Block 27

Block 26

Block 25

Block 24

8-Mbit

Block 23

Block 22

Block 21

Block 20

Block 19

Block 18

Address Range

Block 22

Block 21

Block 20

Block 19

Block 18

Block 17

Block 16

Block 15

Block 14

Block 13

Block 12

Block 11

Block 10

Block 9

32-KWord

78000h - 7FFFFh

70000h - 77FFFh

68000h - 6FFFFh

60000h - 67FFFh

58000h - 5FFFFh

50000h - 57FFFh

48000h - 4FFFFh

40000h - 47FFFh

38000h - 3FFFFh

30000h - 37FFFh

28000h - 2FFFFh

20000h - 27FFFh

18000h - 1FFFFh

10000h - 17FFFh

08000h - 0FFFFh

Block 17

Block 16

Block 15

Block 14

Block 13

Block 12

Block 11

Block 10

Block 9

Block 8

Block 7

Block 6

Block 5

Block 4

Block 3

Block 2

Block 1

Block 0

4-KWord

07000h - 07FFFh

06000h - 06FFFh

05000h - 05FFFh

04000h - 04FFFh

03000h - 03FFFh

02000h - 02FFFh

01000h - 01FFFh

00000h - 00FFFh

Block 7

Block 6

Block 5

Block 4

Block 3

Block 2

Block 1

Block 0

4-KWord

07000h - 07FFFh

06000h - 06FFFh

05000h - 05FFFh

04000h - 04FFFh

03000h - 03FFFh

02000h - 02FFFh

01000h - 01FFFh

00000h - 00FFFh

Figure 4. 8- and 16-Mbit Bottom Boot Memory Map

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Read operations from the parameter blocks,

identifier codes and status register transpire as

single asynchronous or synchronous read cycles.

The read configuration register setting determines

whether or not read operations are asynchronous or

synchronous.

3.0 PRINCIPLES OF OPERATION

The Fast Boot Block flash memory components

include an on-chip WSM to manage block erase

and program. It allows for CMOS-level control

inputs, fixed power supplies, and minimal processor

overhead with RAM-like interface timings.

For all read operations, CE# must be driven active

to enable the devices, ADV# must be driven low to

open the internal address latch, and OE# must be

driven low to activate the outputs. In asynchronous

mode, the address is latched when ADV# is driven

high. In synchronous mode, the address is latched

by ADV# going high or ADV# low in conjunction

with a rising (falling) clock edge, whichever occurs

first. WE# must be at V_IH. Figures 14 through 19

illustrate different read cycles.

3.1

Bus Operations

All bus cycles to and from flash memory conform to

standard microprocessor bus cycles.

3.1.1

READ

The flash memory has three read modes available:

read array, identifier codes, and status register.

These modes are accessible independent of the

V_PPvoltage. The appropriate read command (Read

Array, Read Identifier Codes, or Read Status

Register) must be written to the CUI to enter the

requested read mode. Upon initial power-up or exit

from reset, the device defaults to read array mode.

3.1.2

OUTPUT DISABLE

With OE# at a logic-high level (V_IH), the device

outputs are disabled. Output pins DQ₀–DQ₁₅are

placed in a high-impedance state.

3.1.3

STANDBY

When reading information from main blocks in read

array mode, the device supports two high-

performance read configurations: asynchronous

Deselecting the device by bringing CE# to a logic-

high level (V_IH) places the device in standby mode,

which substantially reduces device power

consumption. In standby, outputs are placed in a

high-impedance state independent of OE#. If

deselected during program or erase operation, the

device continues to consume active power until the

program or erase operation is complete.

page-mode

and

synchronous

burst-mode.

Asynchronous page-mode is the default state and

provides high data transfer rate for non-clocked

memory subsystems. In this state, data is internally

read and stored in a high-speed page buffer. A_1:0

addresses data in the page buffer. The page size is

four words. The other read configuration,

synchronous burst-mode, is enabled by writing to

read configuration register. This register sets the

read configuration, burst order, frequency

configuration, and burst length. In synchronous

burst-mode, the device latches the initial address

then outputs a sequence of data with respect to the

input CLK and read configuration setting.

3.1.4

WRITE

Commands are written to the CUI using standard

microprocessor write timings when ADV#, WE#,

and CE# are active and OE# inactive. The CUI

does not occupy an addressable memory location.

The address is latched on the rising edge of ADV#,

WE#, or CE# (whichever occurs first) and data

needed to execute a command is latched on the

rising edge of WE# or CE# (whichever goes high

first). Write operations are asynchronous.

Therefore, CLK is ignored during write operations.

Figure 20 illustrates a write operation.

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3.1.5

RESET

If RP# is taken low during a block erase or program

operation, the operation will be aborted and the

memory contents at the aborted location are no

longer valid. See Figure 21 for detailed information

regarding reset timings.

The device enters a reset mode when RST# is

driven low. In reset mode, internal circuitry is turned

off and outputs are placed in a high-impedance

state.

After return from reset, a time t_PHQVis required until

outputs are valid, and a delay (t_PHWLor t_PHEL) is

required before a write sequence can be initiated.

After this wake-up interval, normal operation is

restored. The device defaults to read array mode,

the status register is set to 80H, and the read

configuration register defaults to asynchronous

page-mode reads.

4.0 COMMAND DEFINITIONS

Device operations are selected by writing specific

commands into the CUI. Table 3 defines these

commands.

Table 2. Bus Operations

Mode

Reset

Notes RST#

CE#

X

ADV#

X

OE#

X

WE# Address

V_PP

X

DQ_0–15

High Z

D_OUT

V_IL

V_IH

X

Standby

V_IH

V_IL

X

Output Disable

Read

X

V_IH

V_IL

V_IH

X

1,2

3,4

V_IH

V_IL

X

Read Identifier

Codes

See

X

See

Table 4

Write

V_IH

V_IL

V_IH

V_IL

X

D_IN

NOTES:

1. Refer to DC Characteristics. When V_PP≤ V_PPLK, memory contents can be read, but not altered.

2. X can be V_ILor V_IHfor control and address input pins and V_PPLKor V_PPH1/2for V_PP. See DC Characteristics for V_PPLKand

V_PPH1/2voltages.

3. Command writes involving block erase or program are reliably executed when V_PP= V_PPH1/2and V_CC= V_CC1/2

(see Section 8 for operating conditions at different temperatures).

4. Refer to Table 3 for valid D_INduring a write operation.

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Table 3. Command Definitions⁽¹⁾

Bus Cycles

First Bus Cycle

Second Bus Cycle

Command

Read Array/Reset

Req’d.

Notes Oper⁽²⁾Addr⁽³⁾Data⁽⁴⁾Oper⁽²⁾Addr⁽³⁾Data⁽⁴⁾

1

≥ 2

2

Write

X

FFH

90H

70H

50H

20H

Read Identifier Codes

Read Status Register

Clear Status Register

Block Erase

5

Read

IA

ID

X

SRD

1

2

6,7

Write

BA

D0H

WD

Program

2

6,7,8

40H

or

WA

10H

Block Erase and Program

Suspend

1

2

6

Write

X

B0H

D0H

60H

Block Erase and Program

Resume

Set Read Configuration

Write

RCD

03H

NOTES:

1. Commands other than those shown above are reserved by Intel for future device implementations and should not be used.

2. Bus operations are defined in Table 2.

3. X = Any valid address within the device.

IA = Identifier Code Address.

BA = Address within the block being erased.

WA = Address of memory location to be written.

RCD = Data to be written to the read configuration register. This data is presented to the device on A_15-0; set all other

address inputs to “0.”

4. SRD = Data read from status register. See Table 5 for a description of the status register bits.

WD = Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first).

ID = Data read from identifier codes. See Table 4 for manufacturer and device codes.

RCD = Data to be written to read configuration register. SeeTable 6 for a description of the read configuration register bits.

5. Following the Read Identifier Codes command, read operations access manufacturer, device codes, and read

configuration register.

6. Following a block erase, program, and suspend operation, read operations access the status register.

7. To issue a block erase, program, or suspend operation to a lockable block, hold WP# at V .

IH

8. Either 40H or 10H are recognized by the WSM as the program setup.

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another valid command is written. Page-mode and

burst reads are not supported in this read mode.

The status register content is updated and latched

on the rising edge of ADV# or rising (falling) CLK

edge when ADV# is low during synchronous burst-

mode or the falling edge of OE# or CE#, whichever

occurs first. The Read Status Register command

functions independently of the V_PPvoltage.

4.1

Read Array Command

Upon initial device power-up or exit from reset, the

device defaults to read array mode. The read

configuration register defaults to asynchronous

page-mode. The Read Array command also causes

the device to enter read array mode. The device

remains enabled for reads until another command

is written. Once the internal WSM has started a

block erase or program, the device will not

recognize the Read Array command until the WSM

completes its operation or unless the WSM is

suspended via an Erase or Program Suspend

command. The Read Array command functions

independently of the V_PPvoltage.

4.4

Clear Status Register

Command

Status register bits SR.5, SR.4, SR.3, and SR.1 are

set to “1”s by the WSM and can only be cleared by

issuing the Clear Status Register command. These

bits indicate various error conditions. By allowing

system software to reset these bits, several

operations may be performed (such as cumulatively

erasing or writing several bytes in sequence). The

status register may be polled to determine if a

problem occurred during the sequence. The Clear

Status Register command functions independently

of the applied V_PPvoltage. After executing this

command, the device returns to read array mode.

4.2

Read Identifier Codes

Command

The identifier code operation is initiated by writing

the Read Identifier Codes command. After writing

the command, read cycles retrieve the

manufacturer and device codes (see Table 4 for

identifier code values). Page-mode and burst reads

are not supported in this read mode. To terminate

the operation, write another valid command, like the

Read Array command. The Read Identifier Codes

command functions independently of the V_PP

voltage.

4.5

Block Erase Command

Erase is executed one block at a time and initiated

by a two-cycle command. A block erase setup is

written first, followed by a block erase confirm. This

Table 4. Identifier Codes

command

sequence

requires

appropriate

Address

(Hex)

Data

sequencing and address within the block to be

erased (erase changes all block data to FFH).

Block preconditioning, erase, and verify are handled

internally by the WSM. After the two-cycle block

erase sequence is written, the device automatically

outputs status register data when read (see

Figure 7, Automated Block Erase Flowchart). The

CPU can detect block erase completion by

analyzing status register bit SR.7.

Code

(Hex)

Manufacturer Code

00000

00001

0089

88F1

88F2

88F3

88F4

Device Code 8 Mbit

-T

-B

16 Mbit -T

-B

When the block erase completes, check status

register bit SR.5 for an error flag (“1”). If an error is

detected, check status register bits SR.4, SR.3, and

SR.1 to understand what caused the failure. After

examining the status register, it should be cleared if

4.3

Read Status Register

Command

The status register can be read at any time by

writing the Read Status Register command to the

CUI. After writing this command, all subsequent

read operations output status register data until

an error was detected before issuing

a new

command. The device will remain in status register

read mode until another command is written to the

CUI.

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Table 5. Status Register Definition

WSMS

7

ESS

6

ES

5

PS

4

VPPS

3

PSS

2

DPS

1

R

0

NOTES:

SR.7 = WRITE STATE MACHINE STATUS (WSMS) Check SR.7 to determine block erase or program

completion. SR.6–0 are invalid while SR.7 = “0.”

1 = Ready

0 = Busy

SR.6 = ERASE SUSPEND STATUS (ESS)

When an Erase Suspend command is issued, the

WSM halts execution and sets both SR.7 and SR.6

to “1.” SR.6 remains set until an Erase Resume

command is written to the CUI.

1 = Block Erase Suspended

0 = Block Erase in Progress/Completed

SR.5 = ERASE STATUS (ES)

If both SR.5 and SR.4 are “1”s after a block erase or

program attempt, an improper command sequence

was entered.

1 = Error in Block Erasure

0 = Successful Block Erase

SR.4 = PROGRAM STATUS (PS)

1 = Error in Program

0 = Successful Program

SR.3 = V_PPSTATUS (VPPS)

SR.3 does not provide a continuous V_PPfeedback.

The WSM interrogates and indicates the V_PPlevel

only after a block erase or program operation. SR.3

is not guaranteed to reports accurate feedback

1 = V_PPLow Detect, Operation Abort

0 = V_PPOK

when V_PP≠ V_PPH1/2or V_PPLK

.

SR.2 = PROGRAM SUSPEND STATUS (PSS)

When an Program Suspend command is issued, the

WSM halts execution and sets both SR.7 and SR.2

to “1.” SR.2 remains set until an Program Resume

command is written to the CUI.

1 = Program Suspended

0 = Program in Progress/Completed

SR.1 = DEVICE PROTECT STATUS (DPS)

If a block erase or program operation is attempted to

a locked block, SR.1 is set by the WSM and aborts

the operation if WP# = V_IL.

1 = Block Erase or Program Attempted on a

Locked Block, Operation Abort

0 = Unlocked

SR.0 = RESERVED FOR FUTURE

ENHANCEMENTS (R)

SR.0 is reserved for future use and should be

masked out when polling the status register.

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During a block erase suspend, the chip can go into

a pseudo-standby mode by taking CE# to V_IH,

which reduces active current draw. V_PPmust

remain at V_PPH1/2while block erase is suspended.

WP# must also remain at V_ILor V_IH.

4.6

Program Command

Program operation is executed by a two-cycle

command sequence. Program setup (standard 40H

or alternate 10H) is written, followed by a second

write that specifies the address and data. The WSM

then takes over, controlling the internal program

algorithm. After the program sequence is written,

the device automatically outputs status register

data when read (see Figure 8, Automated Program

Flowchart). The CPU can detect the completion of

the program event by analyzing status register bit

SR.7.

To resume the block erase operation, write the

Block Erase Resume command to the CUI. This will

automatically clear status register bits SR.6 and

SR.7. After the Erase Resume command is written,

the device automatically outputs status register

data when read (see Figure 9, Block Erase

Suspend/Resume Flowchart). Block erase cannot

resume until program operations initiated during

block erase suspend have completed.

When the program operation completes, check

status register bit SR.4 for an error flag (“1”). If an

error is detected, check status register bits SR.5,

SR.3, and SR.1 to understand what caused the

problem. After examining the status register, it

should be cleared if an error was detected before

issuing a new command. The device will remain in

status register read mode until another command is

written to the CUI.

4.8

Program Suspend/Resume

Command

The Program Suspend command allows program

interruption to read data in other flash memory

locations. Once the program process starts, writing

the Program Suspend command requests that the

WSM suspend the program operation after a certain

latency period. The device continues to output

status register data when read after issuing

Program Suspend command. Status register bits

SR.7 and SR.2 indicate when the block erase

operation has been suspended (both will be set to

“1”). Specification t_WHRH1defines the program

suspend latency.

4.7

Block Erase Suspend/Resume

Command

The Block Erase Suspend command allows block

erase interruption to read or program data in

another blocks. Once the block erase process

starts, writing the Block Erase Suspend command

requests that the WSM suspend the block erase

operation after a certain latency period. The device

continues to output status register data when read

after the Block Erase Suspend command is issued.

Status Register bits SR.7 and SR.6 indicate when

the block erase operation has been suspended

(both will be set to “1”). Specification t_WHRH2defines

the block erase suspend latency.

At this point, a Read Array command can be written

to read data from blocks other than that which is

suspended. The only other valid commands while

block erase is suspended are Read Status Register

and Program Resume.

During a program suspend, the chip can go into a

pseudo-standby mode by taking CE# to V_IH, which

reduces active current draw. V_PPmust remain at

V_PPH1/2while program is suspended. WP# must

also remain at V_ILor V_IH.

At this point, a Read Array command can be written

to read data from blocks other than that which is

suspended. A Program command sequence can

also be issued during erase suspend to program

data in other blocks. Using the Program Suspend

command (see Section 4.8), a program operation

can be suspended during an erase suspend. The

only other valid commands while block erase is

suspended are Read Status Register and Block

Erase Resume.

To resume the program, write the Program Resume

command to the CUI. This will automatically clear

status register bits SR.7 and SR.2. After the Erase

Resume command is written, the device

automatically outputs status register data when

read (see Figure 10, Program Suspend/Resume

Flowchart).

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Table 6. Read Configuration Register Definition

RM

15

R

FC2

13

FC1

12

FC0

11

R

DOC

9

WC

8

14

10

BS

7

CC

6

R

5

R

4

R

BL2

2

BL1

1

BL0

3

0

NOTES:

RCR.15 = READ MODE (RM)

Read mode configuration effects reads from

main blocks. Parameter block, status register,

and identifier reads support single read cycles.

0 = Synchronous Burst Reads Enabled

1 = Page-Mode Reads Enabled (Default)

RCR.14 = RESERVED FOR FUTURE

ENHANCEMENTS (R)

These bits are reserved for future use. Set

these bits to “0.”

RCR.13–11 = FREQUENCY CONFIGURATION (FC2-0) See Section 4.9.2 for information about the

frequency configuration and its effect on the

initial read.

001 = Code 1 reserved for future use

010 = Code 2

011 = Code 3

100 = Code 4

101 = Code 5

110 = Code 6

Undocumented combinations of bits

RCR.14–11 are reserved by Intel Corporation

for future implementations and should not be

used.

RCR.10 = RESERVED FOR FUTURE

ENHANCEMENTS (R)

These bits are reserved for future use. Set

these bits to “0.”

RCR.9 = DATA OUTPUT CONFIGURATION (DOC)

Undocumented combinations of bits RCR.10–9

are reserved by Intel Corporation for future

implementations and should not be used.

0 = Hold Data for One Clock

1 = Hold Data for Two Clocks

RCR.8 = WAIT CONFIGURATION (WC)

0 = WAIT# Asserted During Delay

1 = WAIT# Asserted One Data Cycle Before Delay

RCR.7 = BURST SEQUENCE (BS)

0 = Intel Burst Order

1 = Linear Burst Order

RCR.6 = CLOCK CONFIGURATION (CC)

0 = Burst Starts and Data Output on Falling

Clock Edge

1 = Burst Starts and Data Output on Rising

Clock Edge

RCR.5–3 = RESERVED FOR FUTURE

ENHANCEMENTS (R)

These bits are reserved for future use. Set

these bits to “0.”

RCR.2–0 = BURST LENGTH (BL2–0)

In the asynchronous page mode, the burst

length always equals four words.

Undocumented combinations of bits RCR.2–0

are reserved by Intel Corporation for future

implementations and should not be used

001 = 4 Word Burst

010 = 8 Word Burst

111 = Continuous Burst

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CLK (C)

A_19-0(A)

Valid

Address

ADV# (V)

Code 2

Code 3

Code 4

Code 5

Code 6

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

DQ_15-0(D/Q)

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Figure 5. Frequency Configuration

Table 7. Frequency Configuration Settings⁽¹⁾

Input CLK Frequency

Frequency

Configuration

Product = -90

Product = -120

V_CC= 2.7 V-3.6 V

Reserved

Code

V_CC= 3.0 V-3.6 V

V_CC= 2.7 V-3.6 V

Reserved

1

2

3

4

5

6

Reserved

≤ 27 MHz

≤ 40 MHz

≤ 54 MHz

≤ 66 MHz

-

≤ 25 MHz

≤ 20 MHz

≤ 33 MHz

≤ 28 MHz

≤ 50 MHz

≤ 40 MHz

≤ 60 MHz

≤ 50 MHz

≤ 66 MHz

≤ 60 MHz

NOTES:

1. Reference Section 4.1. Automotive Temperature Frequency Configuration Settings for the corresponding frequency

configuration codes to different input CLK frequencies.

first). The read configuration data sets the device’s

4.9

Set Read Configuration

Command

read configuration, burst order, frequency

configuration, and burst length. The command

functions independently of the applied V_PPvoltage.

After executing this command, the device returns to

read array mode.

The Set Read Configuration command writes data

to the read configuration register. This operation is

initiated by a two-cycle command sequence. Read

configuration setup is written, followed by a second

write that specifies the data to be written to the read

configuration register. This data is placed on the

address bus, A_15:0, and is latched on the rising

edge of ADV#, CE#, or WE# (whichever occurs

4.9.1

READ CONFIGURATION

The device supports two high performance read

configurations: asynchronous page-mode and

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The burst sequence specifies the order in which

data is addressed in synchronous burst-mode. This

order is programmable as either linear or Intel burst

order. The continuous burst length only supports

linear burst order. The order chosen will depend on

the CPU characteristic. See Table 8 for more

details.

synchronous burst-mode. Bit RCR.15 in the read

configuration register sets the read configuration.

Asynchronous page-mode is the default read

configuration state.

length is enabled. Its setting will depend on the

system and CPU characteristic.

4.9.5

BURST SEQUENCE

Parameter blocks, status register, and identifier

only support single asynchronous and synchronous

read operations.

4.9.2

FREQUENCY CONFIGURATION

The frequency configuration informs the device of

the number of clocks that must elapse after ADV#

is driven active before data will be available. This

value is determined by the input clock frequency.

See Table 7 for the specific input CLK frequency

configuration code

4.9.6

CLOCK CONFIGURATION

The clock configuration configures the device to

start a burst cycle, output data, and assert WAIT#

on the rising or falling edge of the clock. CLK

flexibility helps ease Fast Boot Block flash memory

interface to wide range of burst CPUs.

Figure 5 illustrates data output latency from ADV#

going active for different frequency configuration

codes.

4.9.7

BURST LENGTH

4.9.3

DATA OUTPUT CONFIGURATION

The burst length is the number of words that the

device will output. The device supports burst

lengths of four and eight words. It also supports a

continuous burst mode. In continuous burst mode,

the device will linearly output data until the internal

burst counter reaches the end of the device’s

burstable address space. Bits RCR.2–0 in the read

configuration register set the burst length.

The output configuration determines how many

clocks data will be held valid. The data hold time is

configurable as either one or two clocks.

The data output configuration must be set to hold

data valid for two clock cycles when the frequency

configuration value 4 and burst length is greater

than four words. Otherwise, its setting will depend

on the system CPU’s data setup requirement.

4.9.7.1

Continuous Burst Length

When operating in the continuous burst mode, the

flash memory may incur an output delay when the

burst sequence crosses the first sixteen word

boundary. The starting address dictates whether or

not a delay will occur. If the starting address is

aligned to a four word boundary, the delay will not

be seen. If the starting address is the end of a four

word boundary, the output delay will be equal to the

frequency configuration setting; this is the worst

case delay. The delay will only take place once

during a continuous burst access, and if the burst

sequence never crosses a sixteen word boundary,

the delay will never happen. Using the WAIT#

output pin in the continuous burst configuration, the

system is informed if this output delay occurs.

CLK (C)

1 CLK

Data Hold

Valid

Output

Valid

Output

Valid

Output

DQ_15-0(D/Q)

2 CLK

Data hold

Valid

Output

Figure 6. Output Configuration

WAIT# CONFIGURATION

4.9.4

The WAIT# configuration bit controls the behavior

of the WAIT# output signal. This output signal can

be set to be asserted during or one CLK cycle

before an output delay when continuous burst

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Table 8. Sequence and Burst Length

Burst Addressing Sequence (Dec)

Starting

Addr.

4 Word

Burst Length

8 Word

Burst Length

Continuous

Burst

(Dec)

Linear

Intel

Linear

Intel

Linear

0

0-1-2-3

1-2-3-0

2-3-0-1

3-0-1-2

0-1-2-3

0-1-2-3-

4-5-6-7

0-1-2-3-

4-5-6-7

0-1-2-3-4-5-6-...

1

2

3

1-0-3-2

2-3-0-1

3-2-1-0

1-2-3-4-

5-6-7-0

1-0-3-2-

5-4-7-6

1-2-3-4-5-6-7-...

2-3-4-5-6-7-8-...

3-4-5-6-7-8-9-...

2-3-4-5-

6-7-0-1

2-3-0-1-

6-7-4-5

3-4-5-6-

7-0-1-2

3-2-1-0-

7-6-5-4

6

7

6-7-0-1-

2-3-4-5

6-7-4-5-

2-3-0-1

6-7-8-9-10-11-12-...

7-8-9-10-11-12-13...

7-0-1-2-

3-4-5-6

7-6-5-4-

3-2-1-0

14

15

14-15-16-17-18-19-20-...

15-16-17-18-19-20-21-...

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Start

Bus Operation

Command

Comments

Data = 20H

Addr = Within Block to Be

Erased

Write 20H,

Block Address

Write

Erase Setup

Data = D0H

Write

Read

Erase Confirm

Addr = Within Block to Be

Erased

Write D0H,

Block Address

Status Register Data

Suspend

Blk. Erase

Loop

Check SR.7

1 = WSM Ready

0 = WSM Busy

Read Status Register

No

Standby

Repeat for subsequent block erasures.

0

Suspend

SR.7 =

Block Erase

Full status check can be done after each block erase or after a

sequence of block erasures.

Yes

1

Write FFH after the last operation to place device in read array mode.

Full Status

Check if Desired

Block Erase Complete

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (See Above)

Bus Operation

Command

Comments

Check SR.3

Standby

1

1 = V_PPError Detect

SR.3 =

V_PPRange Error

Check SR.1

Standby

1 = Device Protect Detect

WP# = V_IL

0

SR.1 =

0

1

Check SR.4, 5

Both 1 = Command Sequence

Error

Standby

Device Protect Error

Check SR.5

1 = Block Erase Error

1

Command Sequence

Error

SR.4, 5 =

0

SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Staus

Register command, in cases where multiple blocks are erased before

full status is checked.

If an error is detected, clear the status register before attempting retry

or other error recovery.

SR.5 =

0

Block Erase Error

Block Erase

Successful

Figure 7. Automated Block Erase Flowchart

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Bus Operation

Command

Comments

Data = 40H

Start

Write

Program Setup Addr = Location to Be

Written

Write 40H,

Address

Data = Data to Be Written

Write

Read

Data

Addr = Location to Be

Written

Write Data and

Address

Status Register Data

Suspend

Program

Loop

Check SR.7

1 = WSM Ready

0 = WSM Busy

Read Status Register

Standby

No

Repeat for subsequent byte writes.

0

Suspend

Program

SR.7 =

1

SR full status check can be done after each byte write or after a

sequence of program operations.

Yes

Write FFH after the last byte write operation to place device in read

array mode.

Full Status

Check if Desired

Program Complete

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (See Above)

Bus Operation

Command

Comments

Check SR.3

1

Standby

SR.3 =

V_PPRange Error

1 = V_PPError Detect

Check SR.1

1 = Device Protect Detect

WP# = V_IL

0

SR.1 =

0

Standby

1

Device Protect Error

Check SR.4

1 = Data Write Error

SR.4, SR.3 and SR.1 are only cleared by the Clear Staus Register

command, in cases where multiple locations are written before full

status is checked.

SR.4 =

Program Error

0

If an error is detected, clear the status register before attempting retry

or other error recovery.

Program Successful

Figure 8. Automated Program Flowchart

23

PRODUCT PREVIEW

FAST BOOT BLOCK DATASHEET

E

Bus Operation

Write

Command

Comments

Start

Data = B0H

Erase Suspend

Addr = X

Write B0H

Status Register Data

Addr = X

Read

Check SR.7

Standby

1 = WSM Ready

0 = WSM Busy

Read Status Register

Check SR.6

Standby

Write

1 = Block Erase Suspended

0 = Block Erase Completed

0

SR.7 =

Data = D0H

Addr = X

Erase Resume

1

0

Block Erase

Completed

SR.6 =

1

Read

Program

Read or Byte

Write?

Read Array

Data

Program

Loop

No

Done

Yes

Write D0H

Write FFH

Block Erase Resumed

Read Array Data

Figure 9. Block Erase Suspend/Resume Flowchart

24

PRODUCT PREVIEW

E

FAST BOOT BLOCK DATASHEET

Bus Operation

Command

Comments

Data = B0H

Start

Program

Suspend

Write

Addr = X

Write B0H

Status Register Data

Addr = X

Read

Read Status Register

Check SR.7

Standby

1 = WSM Ready

0 = WSM Busy

0

Check SR.2

1 = Program Suspended

0 = Program Completed

SR.7 =

Standby

Write

1

Data = FFH

Addr = X

Read Array

SR.2 =

Program Completed

Read array locations from

block other than that being

written

Read

1

Data = D0H

Addr = X

Write FFH

Write

Program Resume

Read Array Data

Done

No

Reading

Yes

Write D0H

Write FFH

Program Resumed

Read Array Data

Figure 10. Program Suspend/Resume Flowchart

25

PRODUCT PREVIEW

FAST BOOT BLOCK DATASHEET

5.0 DATA PROTECTION

E

6.0

V

VOLTAGES

PP

The Fast Boot Block flash memory architecture

features hardware-lockable main blocks and two

parameter blocks, so critical code can be kept

secure while other parameter blocks are

programmed or erased as necessary.

Intel’s Fast Boot Block flash memory family

provides in-system programming and erase at

2.7 V–3.6 V

temperature) V_PP. For customers requiring fast

programming in their manufacturing environment,

this family of products includes an additional low-

cost, high-performance 12 V programming feature.

(3.0 V–3.6 V

for

automotive

5.1

V

≤ V

for Complete

PP

PPLK

The 12 V V_PPmode enhances programming

performance during short period of time typically

found in manufacturing processes; however, it is

not intended for extended use. 12 V may be applied

to V_PPduring block erase and program operations

for a maximum of 1000 cycles on the main blocks

and 2500 cycles on the parameter blocks. V_PPmay

be connected to 12 V for a total of 80 hours

maximum. Stressing the device beyond these limits

may cause permanent damage.

Protection

The V_PPprogramming voltage can be held low for

complete write protection of all blocks in the flash

device. When V_PPis below V_PPLK, any block erase

or program operation will result in a error, prompting

the corresponding status register bit (SR.3) to be

set.

5.2

WP# = V for Block Locking

IL

7.0 POWER CONSUMPTION

The lockable blocks are locked when WP# = V_IL;

any block erase or program operation to a locked

block will result in an error, which will be reflected in

the status register. For top configuration, the top

two parameter and all main blocks (blocks #37,

#38, and #0 through 30 for the 16-Mbit, blocks #21,

#22, and #0 through #14 for the 8-Mbit) are

lockable. For the bottom configuration, the bottom

two parameter and all main blocks (blocks #0, #1,

and #8 through #38 for the 16-Mbit, blocks #0, #1,

and #8 through #22 for the 8-Mbit) are lockable.

Unlocked blocks can be programmed or erased

normally (unless V_PPis below V_PPLK).

While in operation, the flash device consumes

active power. However, Intel Flash devices have

power savings that can significantly reduce overall

system power consumption. The Automatic Power

Savings (APS) feature reduces power consumption

when the device is idle. If CE# is deasserted, the

flash enters its standby mode, where current

consumption is even lower. The combination of

these features minimizes overall memory power

and system power consumption.

7.1

Active Power

5.3

WP# = V for Block Unlocking

IH

With CE# at a logic-low level and RST# at a logic-

high level, the device is in active mode. Active

power is the largest contributor to overall system

power consumption. Minimizing active current has a

profound effect on system power consumption,

especially for battery-operated devices.

WP# controls all block locking and V_PPprovides

protection against spurious writes. Table 9 defines

the write protection methods.

Table 9. Write Protection Truth Table

Write Protection

V_PP

WP#

RST#

Provided

7.2

Automatic Power Savings

X

V_IL

All Blocks Locked

Automatic Power Savings (APS) provides low-

power operation during active mode, allowing the

flash to put itself into a low current state when not

being accessed. After data is read from the memory

array, the device’s power consumption enters the

APS mode where typical I_CCcurrent is comparable

to I_CCS. The flash stays in this static state with

outputs valid until a new location is read.

V_IL

X

V_IH

Lockable

Blocks Locked

≥ V_PPLK

26

V_IL

V_IH

All

Blocks Unlocked

PRODUCT PREVIEW

E

FAST BOOT BLOCK DATASHEET

_CC, V_PPAND RST# TRANSITIONS

7.4.2

V

7.3

Standby Power

The CUI latches commands as issued by system

software and is not altered by V_PPor CE#

transitions or WSM actions. Its default state upon

power-up, after exit from deep power-down mode or

after V_CCtransitions above V_LKO(Lockout voltage),

is read array mode.

With CE# at a logic-high level (V_IH) and the CUI in

read mode, the flash memory is in standby mode,

which disables much of the device’s circuitry and

substantially reduces power consumption. Outputs

(DQ₀–DQ₁₅) are placed in a high-impedance state

independent of the status of the OE# signal. If CE#

transitions to a logic-high level during erase or

program operations, the device will continue to

perform the operation and consume corresponding

active power until the operation is completed.

After any block erase or program operation is

complete (even after V_PPtransitions down to

V_PPLK), the CUI must be reset to read array mode

via the Read Array command if access to the flash

memory array is desired.

System engineers should analyze the breakdown of

standby time versus active time and quantify the

respective power consumption in each mode for

their specific application. This will provide a more

accurate measure of application-specific power and

energy requirements.

7.5

Power Supply Decoupling

Flash memory’s power switching characteristics

require careful device decoupling. System

designers should consider three supply current

issues:

7.4

Power-Up/Down Operation

1. Standby current levels (I_CCS

)

The device is protected against accidental block

erasure or programming during power transitions.

Power supply sequencing is not required, since the

2. Active current levels (I_CCR

)

3. Transient peaks produced by falling and rising

edges of CE#.

device is indifferent as to which power supply, V_PP

,

V

_CC, or V_CCQ, powers-up first.

Transient current magnitudes depend on the device

outputs’ capacitive and inductive loading. Two-line

control and proper decoupling capacitor selection

will suppress these transient voltage peaks. Each

7.4.1

RST# CONNECTION

The use of RST# during system reset is important

with automated program/erase devices since the

system expects to read from the flash memory

when it comes out of reset. If a CPU reset occurs

flash device should have

a 0.1 µF ceramic

capacitor connected between each V_CCand GND,

and between its V_PPand GND. These high-

frequency, inherently low-inductance capacitors

should be placed as close as possible to the

package leads.

without

a

flash memory reset, proper CPU

initialization will not occur because the flash

memory may be providing status information

instead of array data. Intel recommends connecting

RST# to the system reset signal to allow proper

CPU/flash initialization following system reset.

7.5.1

V

_PPTRACE ON PRINTED CIRCUIT

BOARDS

System designers must guard against spurious

writes when V_CCvoltages are above V_LKOand V_PP

is active. Since both WE# and CE# must be low for

a command write, driving either signal to V_IHwill

inhibit writes to the device. The CUI architecture

provides additional protection since alteration of

memory contents can only occur after successful

completion of the two-step command sequences.

The device is also disabled until RST# is brought to

V_IH, regardless of the state of its control inputs. By

holding the device in reset during power-up/down,

invalid bus conditions during power-up can be

masked, providing yet another level of memory

protection.

Designing for in-system writes to the flash memory

requires special consideration of the V_PPpower

supply trace by the printed circuit board designer.

The V_PPpin supplies the flash memory cells current

for programming and erasing. V_PPtrace widths and

layout should be similar to that of V_CC. Adequate

V_PPsupply traces, and decoupling capacitors

placed adjacent to the component, will decrease

spikes and overshoots.

27

PRODUCT PREVIEW

FAST BOOT BLOCK DATASHEET

E

8.0 ELECTRICAL SPECIFICATIONS

NOTICE: This datasheet contains preliminary

information on products in the design phase of

development. The specifications are subject to

change without notice. Verify with your local Intel

Sales office that you have the latest datasheet

before finalizing a design.

8.1

Absolute Maximum Ratings*

Temperature under Bias ............ –40 °C to +125 °C

Storage Temperature................. –65 °C to +125 °C

*WARNING: Stressing the device beyond the

“Absolute Maximum Ratings” may cause permanent

damage. These are stress ratings only. Operation

beyond the “Operating Conditions” is not

recommended and extended exposure beyond the

“Operating Conditions” may affect device reliability.

Voltage On Any Pin

(except V_CC, V_CCQ, and V_PP)–0.5 V to +5.5 V⁽¹⁾

V_PPVoltage .........................–0.5 V to +13.5 V^(1,2,4)

V_CCand V_CCQVoltage............... –0.2 V to +5.0 V⁽¹⁾

Output Short Circuit Current.....................100 mA⁽³⁾

NOTES:

1. All specified voltages are with respect to GND. Minimum DC voltage is–0.5 V on input/output pins and –0.2 V on V_CCand

V_PPpins. During transitions, this level may undershoot to–2.0 V for periods <20 ns. Maximum DC voltage on input/output

pins and V_CCis V_CC+0.5 V which, during transitions, may overshoot to V_CC+2.0 V for periods <20 ns.

2. Maximum DC voltage on V_PPmay overshoot to +14.0 V for periods <20 ns.

3. Output shorted for no more than one second. No more than one output shorted at a time.

4. V_PPProgram voltage is normally 2.7 V–3.6 V. Connection to supply of 11.4 V–12.6 V can only be done for 1000 cycles on

the main blocks and 2500 cycles on the parameter blocks during program/erase. V may be connected to 12 V for a total

PP

of 80 hours maximum.

8.2

Extended Temperature Operating Conditions

Symbol

Parameter

Operating Temperature

V_CCSupply Voltage

I/O Voltage

Notes

Min

–40

2.7

Max

+85

2.85

3.3

Unit

T_A

°C

V_CC1

V_CC2

V_CC3

V_CCQ1

V_CCQ2

V_CCQ3

V_PPH1

V_PPH2

1

V

2.7

V

1,4

1,2

1,2,4

1

2.7

3.6

V

1.65

1.8

2.5

V

I/O Voltage

2.5

V

I/O Voltage

2.7

3.6

V

V_PPSupply Voltage

Block Erase Cycling

2.7

3.6

1,4

3

11.4

10,000

12.6

V

Cycling

Cycles

NOTES:

1. See DC Characteristics tables for voltage range-specific specifications.

2. The voltage swing on the inputs, V_INis required to match V_CCQ

.

3. Applying V_PP= 11.4 V–12.6 V during a program or erase can only be done for a maximum of 1000 cycles on the main

blocks and 2500 cycles on the parameter blocks. A hard connection to V_PP= 11.4 V–12.6 V is not allowed and can cause

damage to the device.

4. V_CC, V_CCQ, and V_PP1must share the same supply when all three are between 2.7V and 3.6 V.

28

PRODUCT PREVIEW

E

FAST BOOT BLOCK DATASHEET

(1)

8.3

Capacitance

T_A= +25 °C, f = 1 MHz

Sym

Parameter

Typ

6

Max

8

Unit

pF

Condition

V_IN= 0.0 V

C_IN

Input Capacitance

Output Capacitance

C_OUT

8

12

pF

V_OUT= 0.0 V

NOTE:

1. Sampled, not 100% tested.

V_CCQ

Input

0V

V_CCQ/2

Test Points

V_CCQ/2

Output

AC test inputs are driven at V_CCQmin. for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends, at

V_CCQ/2. Input rise and fall times (10% to 90%) < 5 ns. Worst case speed conditions are when V_CCQ= 2.7 V.

Figure 11. Transient Input/Output Reference Waveform for V_CC= 2.7 V−3.6 V

Test Configuration Component Value

for Worst Case Speed Conditions

V_CCQ

Test Configuration C_L(pF) R₁(Ω) R₂(Ω)

R₁

2.7 V Standard Test

1.65 V Standard Test

50

25K

Device

Under Test

Out

16.7K

C_L

R₂

NOTE:

C_Lincludes jig capacitance.

NOTE:

See table for component values.

Figure 12. Transient Equivalent Testing

Load Circuit

29

PRODUCT PREVIEW

FAST BOOT BLOCK DATASHEET

8.4 DC Characteristics—Extended Temperature

E

(1)

V_CC

2.7 V–3.6 V 2.7 V–2.85 V 2.7 V–3.3 V

V_CCQ2.7 V–3.6 V 1.65 V–2.5 V 1.65 V–2.5 V

Sym

Parameter

Input Load

Note Typ Max

Typ Max

Typ Max Unit

Test Conditions

I_LI

6

± 1

± 1 µA V_CC= V_CCMax

Current

V

_CCQ= V_CCQMax

_IN= V_CCQor GND

I_LO

Output Leakage

Current

6

± 10

± 25

± 10

± 25

± 10 µA V_CC= V_CCMax

_CCQ= V_CCQMax

V

V_IN= V_CCQor GND

Output Leakage

Current for

WAIT#

± 25

I_CCS

V_CCStandby

Current

6

30

50

20

50

150

250

µA V_CC= V_CCMax

CE# = RP# = V_CC

or during Program/

Erase Suspend

I_CCR

V_CCRead

Current

4,6

45

60

30

45

40

55

mA

Asynchronous

_AVAV= Min

_IN= V_IHor V_IL

t

V

Synchronous

CLK = 33 MHz

CE# = V_IL

OE# = V_IH

Burst length = 1

I_CCWV_CCProgram

Current

3,6

8

2

20

8

2

20

8

2

20

mA V_PP= V_{PP1, 2}

Program in Progress

V_CCErase

Current

mA V_PP= V_{PP1, 2}

Erase in Progress

_PP≤ V_CC

I_CCE

I_PPR

V_PPRead

Current

±15

µA

V

3

50

10

200

35

50

10

200

35

50

10

200

35

µA V_PP> V_CC

mA _PP=V_PP1

Program in Progress

mA V_PP= V_PP2

Program in Progress

mA V_PP= V_PP1

Program in Progress

mA V_PP= V_PP2

Program in Progress

µA V_PP= V_{PP1, 2}

Program or Erase

Suspend in Progress

V_PPProgram

Current

I_PPW

V

2

12

8

10

25

2

13

8

10

25

2

13

8

10

25

I_PPE

V_PPErase

Current

3

25

I_PPESV_PPErase

Suspend Current

50

200

50

200

50

200

I_PPWS

30

PRODUCT PREVIEW

E

FAST BOOT BLOCK DATASHEET

8.4

DC Characteristics—Extended Temperature (Continued)

V_CC

2.7 V–3.6 V 2.7 V–2.85 V 2.7 V–3.3 V

V_CCQ2.7 V–3.6 V 1.65 V–2.5 V 1.8 V–2.5 V

Sym

Parameter

Note Min

Max

Min

Max

Min

Max Unit

Test Conditions

V_IL

Input Low

–0.4

0.4

–0.2

0.2

–0.2

0.2

V

Voltage

V_CCQ

–

0.4V

V_CCQ

–

0.2V

V_CCQ

–

0.2V

V_IH

Input High

Voltage

V

V_OL

Output Low

Voltage

0.10 -0.10 0.10 -0.10 0.10

V

V_CC= V_CCMin

V

_CCQ= V_CCQMin

I

_OL= 100 µA

V_OH

Output High

Voltage

V_CCQ

–

0.1V

V_CCQ

–

V_CCQ

–

V_CC= V_CCMin

_CCQ= V_CCQMin

V

0.1V

I_OH= –100 µA

V_PPLKV_PPLock-Out

Voltage

2

1.5

2.7

1.5

3.6

1.5

3.3

Complete Write

Protection

V_PP1V_PPduring

V_PP2Program and

V_PP3Erase Operations

V_PP4

2

V

2.7

2.85

2.7

2,5 11.4 12.6 11.4 12.6 11.4 12.6

V_LKOV_CCProg/Erase

Lock Voltage

1.5

V_LKO2V_CCQProg/Erase

Lock Voltage

1.2

V

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at normal V_CC, T = +25 °C.

2. I_CCESis specified with device deselected. If device is read while in erase suspend, current draw is sum of I_CCESand I_CCR

3. Erases and program operations are inhibited when V_PP≤ V_PPLK, and not guaranteed outside the valid V_PPranges of V_PPH1

and V_PPH2

.

4. Sampled, not 100% tested.

5. Automatic Power Savings (APS) reduces I_CCRto approximately standby levels, in static operation.

6. Applying V_PP= 11.4 V–12.6 V during program/erase can only be done for a maximum of 1000 cycles on the main blocks

and 2500 cycles on the parameter blocks. V may be connected to 12 V for a total of 80 hours maximum.

PP

7. The specification is the sum of V_CCand V_CCQcurrents.

31

PRODUCT PREVIEW

FAST BOOT BLOCK DATASHEET

E

(1,6)_—

8.5

AC Characteristics—Read-Only Operations

Extended Temperature

Product

–95

3.0 V–3.6 V 2.7 V–3.6 V 2.7 V–3.6 V

Notes Min Max Min Max Min Max Unit

–120

V_CC

#

Sym

Parameter

CLK Period

R1 t_CLK

R2 t_CH(t_CL

R3 t_CHCL

R4 t_AVCH

R5 t_VLCH

R6 t_ELCH

R7 t_CHQV

R8 t_CHQX

R9 t_CHAX

R10 t_CHTL

R11 t_AVVH

R12 t_ELVH

R13 t_AVQV

R14 t_ELQV

R15 t_VLQV

R16 t_VLVH

R17 t_VHVL

R18 t_VHAX

R19 t_APA

R20 t_GLQV

R21 t_RHQV

15

ns

)

CLK High (Low) Time

2.5

CLK Fall (Rise) Time

5

Address Valid Setup to CLK

ADV# Low Setup to CLK

CE# Low Setup to CLK

CLK to Output Delay

7

14

13

16

23

Output Hold from CLK

5

Address Hold from CLK

CLK to WAIT# delay

3

5

10

Address Setup to ADV# High

CE# Low to ADV# High

Address to Output Delay

CE# Low to Output Delay

ADV# Low to Output Delay

ADV# Pulse Width Low

ADV# Pulse Width High

Address Hold from ADV# High

Page Address Access Time

OE# Low to Output Delay

RST# High to Output Delay

10

90

95

120 ns

ns

2

10

3

10

3

10

3

4

3

ns

21

25

23

25

30

ns

600

25

600

25

600 ns

R22 t_EHQZ

t_GHQZ

CE# or OE# High to Output in

High Z, Whichever Occurs First

4

25

ns

R23 t_OH

Output Hold from Address,

CE#, or OE# Change,

Whichever Occurs First

0

ns

NOTES:

1. See AC Input/Output Reference Waveform for timing measurements and maximum allowable input slew rate.

2. OE# may be delayed up to t_ELQV–t_GLQVafter the falling edge of CE# without impact on t_ELQV

.

3. Address hold in synchronous burst-mode is defined as t_CHAXor t_VHAX, whichever timing specification is satisfied first.

4. Sampled, not 100% tested.

5. Output loading on WAIT# equals 15 pF.

6. Data bus voltage must be less than or equal to V_CCQwhen a read operation is initiated to guarantee AC specifications.

32

PRODUCT PREVIEW

E

FAST BOOT BLOCK DATASHEET

R3

CLK (C)

R2

R1

Figure 13. AC Waveform for CLK Input

V_IH

A_19-0(A)

V_IL

Valid

Address

R18

R13

R11

R17

V_IH

ADV# (V)

V_IL

R16

R22

R15

R14

V_IH

CE# (E)

V_IL

R12

V_IH

OE# (G)

V_IL

V_IH

WE# (W)

V_IL

V_OH

WAIT# (T)

V_OL

R23

R20

V_OH

High Z

Valid

DQ_15-0(D/Q)

V_OL

Output

R21

V_IH

RST# (R)

V_IL

Figure 14. AC Waveform for Single Asynchronous Read Operation

from Parameter Blocks, Status Register, Identifier Codes

33

PRODUCT PREVIEW

FAST BOOT BLOCK DATASHEET

E

V_IH

A_19-2(A)

V_IL

Valid

Address

V_IH

A_1-0(A)

V_IL

Valid

Address

Valid

Address

Valid

Address

Valid

Address

R13

R18

R11

R17

V_IH

V_IL

ADV# (V)

R16

R15

R14

R22

V_IH

V_IL

CE# (E)

OE# (G)

V_IH

V_IL

V_IH

WE# (W)

V_IL

V_OH

WAIT# (T)

V_OL

R20

R19

R23

V_OH

V_OL

High Z

Valid

Output

Valid

Output

Valid

Output

Valid

Output

DQ_15-0(D/Q)

RST# (R)

R21

V_IH

V_IL

Figure 15. AC Waveform for Asynchronous Page-Mode Read Operations

from Main Blocks

34

PRODUCT PREVIEW

E

FAST BOOT BLOCK DATASHEET

V_IH

CLK (C)

Note 1

V_IL

R4

V_IH

Valid

Address

A_19-0(A)

V_IL

R9

R18

R11

R17

V_IH

V_IL

ADV# (V)

R16

R5

R22

V_IH

V_IL

CE# (E)

R12

R6

V_IH

OE# (G)

V_IL

V_IH

WE# (W)

V_IL

V_OH

WAIT# (T)

V_OL

R20

R7

R23

V_OH

V_OL

High Z

Valid

Output

DQ_15-0(D/Q)

NOTE:

1. Depending upon the frequency configuration code value in the read configuration register, insert clock cycles:

• Frequency Configuration 2 insert two clock cycles

• Frequency Configuration 3 insert three clock cycles

• Frequency Configuration 4 insert four clock cycles

• Frequency Configuration 5 insert five clock cycles

• Frequency Configuration 6 insert six clock cycles

See Section 4.9.2 for further information about the frequency configuration and its effect on the initial read.

Figure 16. AC Waveform for Single Synchronous Read Operations

from Parameter Blocks, Status Register, Identifier Codes

35

PRODUCT PREVIEW

FAST BOOT BLOCK DATASHEET

E

V_IH

CLK (C)

V_IL

Note 1

R4

V_IH

Valid

A_19-0(A)

Address

V_IL

R9

R18

R11

R17

V_IH

ADV# (V)

V_IL

R16

R22

R5

V_IH

CE# (E)

V_IL

R12

R6

V_IH

OE# (G)

V_IL

V_IH

WE# (W)

V_IL

V_OH

WAIT# (T)

V_OL

R20

R7

R8

R23

V_OH

High Z

Valid

DQ_15-0(D/Q)

Output

V_OL

NOTE:

1. Depending upon the frequency configuration code value in the read configuration register, insert clock cycles:

• Frequency Configuration 2 insert two clock cycles

• Frequency Configuration 3 insert three clock cycles

• Frequency Configuration 4 insert four clock cycles

• Frequency Configuration 5 insert five clock cycles

• Frequency Configuration 6 insert six clock cycles

See Section 4.9.2 for further information about the frequency configuration and its effect on the initial read.

Figure 17. AC Waveform for Synchronous Burst Read Operations, Four Word Burst Length,

from Main Blocks

36

PRODUCT PREVIEW

E

FAST BOOT BLOCK DATASHEET

V_IH

CLK (C)

Note 1

V_IL

V_IH

A_19-0(A)

ADV# (V)

CE# (E)

V_IL

V_IH

V_IL

V_IH

V_IL

V_IH

OE# (G)

V_IL

V_IH

WE# (W)

R10

V_IL

V_OH

WAIT# (T)

Note 2

V_OL

R7

V_OH

V_OL

High Z

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

DQ_15-0(D/Q)

NOTE:

1. This delay will only occur when burst length is configured as continuous. See Section 4.9.7 for further information about

the behavior of WAIT#.

2. WAIT# is configurable. It can be set to assert during or one CLK cycle before an output delay. See Section 4.9.4 for further

information.

Figure 18. AC Waveform for Continuous Burst Read, Showing an Output Delay

with Data Output Configuration Set to One Clock

V_IH

CLK (C)

Note 1

V_IL

V_IH

A_19-0(A)

ADV# (V)

CE# (E)

V_IL

V_IH

V_IL

V_IH

V_IL

V_IH

OE# (G)

V_IL

V_IH

WE# (W)

R10

V_IL

V_OH

WAIT# (T)

Note 2

V_OL

R7

V_OH

V_OL

High Z

Valid

Output

DQ_15-0(D/Q)

Output

NOTE:

1. This delay will only occur when burst length is configured as continuous. See Section 4.9.7 for further information about

the behavior of WAIT#.

2. WAIT# is configurable. It can be set to assert during or one CLK cycle before an output delay. See Section 4.9.4 for further

information.

Figure 19. AC Waveform for Continuous Burst Read, Showing an Output Delay

with Data Output Configuration Set to One Clock

37

PRODUCT PREVIEW

FAST BOOT BLOCK DATASHEET

8.6 AC Characteristics—Write Operations

E

Max Unit

(1, 2)

—Extended Temperature

Valid for All Speed and

Voltage Combinations

#

Sym

Parameter

Notes

Min

W1

t_PHWL(t_PHEL

)

RST# High Recovery to WE# (CE#) Going

Low

3

600

µs

W2

W3

W4

W5

W6

W7

W8

W9

t_ELWL(t_WLEL

)

CE# (WE#) Setup to WE# (CE#) Going Low

Write Pulse Width

6

0

75

10

70

75

10

0

ns

t_WP

t_VLVH

ADV# Pulse Width

t_DVWH(t_DVEH

t_AVWH(t_AVEH

t_VLEH(t_VLWH

t_AVVH

t_WHEH(t_EHWH

)

Data Setup to WE# (CE#) Going High

Address Setup to WE# (CE#) Going High

ADV# Setup to WE# (CE#) Going High

Address Setup to ADV# Going High

CE# (WE#) Hold from WE# (CE#) High

Data Hold from WE# (CE#) High

Address Hold from WE# (CE#) High

Address Hold from ADV# Going High

Write Pulse Width High

4

)

W10 t_WHDX(t_EHDX

)

0

W11 t_WHAX(t_EHAX

)

0

W12 t_VHAX

3

W13 t_WPH

7

3

20

200

0

W14 t_PHWH(t_PHHEH

)

WP# Setup to WE# (CE#) Going High

V_PPSetup to WE# (CE#) Going High

Write Recovery before Read

W15 t_VPWH(t_VPEH

)

W16 t_WHGL(t_EHGL

)

W17 t_QVBH

WP# Hold from Valid SRD

3,5

0

W18 t_QVVL

V_PPHold from Valid SRD

0

NOTES:

1. Read timing characteristics during block erase and program operations are the same as during read-only operations. Refer

to AC Characteristics —Read-Only Operations.

2. A write operation can be initiated and terminated with either CE# or WE#.

3. Sampled, not 100% tested.

4. Refer to Table 3 for valid A_INand D_INfor block erase or program.

5. V_PPshould be held at V_PPH1/2until determination of block erase or program success.

6. Write pulse width (t_WP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high

(whichever goes high first). Hence, t_WP= t_WLWH= t_ELEH= t_WLEH= t_ELWH

7. Write pulse width high (t_WPH) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low

(whichever goes low last). Hence, t_WPH= t_WHWL= t_EHEL= t_WHEL= t_EHWL

.

38

PRODUCT PREVIEW

E

FAST BOOT BLOCK DATASHEET

Note 1

Note 2

Note 3

Note 4

Note 5

V_IH

V_IL

Valid Address

A_20-0(A)

W12

W11

W6

W8

V_IH

V_IL

ADV# (V)

W4

W7

Note 6

V_IH

V_IL

CE# (WE#) [E(W)]

OE# [G]

W2

W9

W16

V_IH

V_IL

W1

W13

V_IH

V_IL

WE# (CE#) [W(E)]

Note 6

W3

W5

W10

W19

V_IH

V_IL

Valid

SRD

Data In

DATA [D/Q]

RST# [P]

WP# [B]

V_IH

V_IL

W14

W15

W17

W18

V_IH

V_IL

V_PPH1/2

V_PPLK

V_IL

V_PP[V]

NOTES:

1.

2. Write block erase or program setup.

V

power-up and standby.

CC

3. Write block erase confirm or valid address and data.

4. Automated erase or program delay.

5. Read status register data.

6. For read operations, OE# and CE# must be driven active, and WE# de-asserted.

Figure 20. AC Waveform for Write Operations

39

PRODUCT PREVIEW

FAST BOOT BLOCK DATASHEET

E

8.7

AC Characteristics—Reset Operation—Extended Temperature

R20

V_IH

RST# (R)

V_IL

P1

(A) Reset while device is in read mode

Abort

Complete

P2

R20

V_IH

V_IL

RST# (R)

P1

(B) Reset during program or block erase, P1

≤ P2

Abort

Complete

P2

R20

V_IH

RST# (R)

V_IL

P1

(C) Reset during program or block erase, P1

≥ P2

Figure 21. AC Waveform for Reset Operation

Table 10. Reset Specifications

#

Symbol

Parameter

Notes

Min

Max

Unit

P1

t_PLPH

RST# Low to Reset During Read

(If RST# is tied to V_CC, this specification is not

applicable)

2,4

100

ns

P2

t_PLRH

RST# Low to Reset during Block Erase or

Program

3,4

22

µs

NOTES:

1. These specifications are valid for all product versions (packages and speeds).

2. If t_PLPHis < 100 ns the device may still reset but this is not guaranteed.

3. If RST# is asserted while a block erase orword program operation is not executing, the reset will complete within 100 ns.

4. Sampled, but not 100% tested.

40

PRODUCT PREVIEW

E

FAST BOOT BLOCK DATASHEET

(3, 4, 5)

8.8

Extended Temperature Block Erase And Program Performance

2.7 V V_PP

Notes Typ⁽¹⁾

Max

12 V V_PP

#

Sym

W19 t_WHRH1, Program Time

t_EHRH1Block Program Time (Parameter)

Parameter

Typ⁽¹⁾

Max

Unit

2

23.5

0.10

0.8

1

200

0.30

2.4

4

8

185

0.10

0.8

4

µs

sec

µs

0.03

0.24

0.8

1.1

5

Block Program Time (Main)

t_WHRH2, Block Erase Time (Parameter)

t_EHRH2Block Erase Time (Main)

1.8

6

5

t_WHRH5, Program Suspend Latency

t_EHRH5

10

t_WHRH6, Erase Suspend Time

t_EHRH6

13

20

10

12

µs

NOTES:

1. Typical values measured at T_A= +25 °C and nominal voltages. Subject to change based on device characterization.

2. Excludes system-level overhead.

3. These performance numbers are valid for all speed versions.

4. Sampled, but not 100% tested.

5. Reference the AC Waveform for Write Operations Figure 20.

8.9

Automotive Temperature Operating Conditions

Except for the specifications given in this section, all DC and AC characteristics are identical to those listed in

the extended temperature specifications. See Section 7.2 for extended temperature specifications.

Symbol

T_A

Parameter

Operating Temperature

V_CCSupply Voltage

I/O Voltage

Notes

Min

-40

Max

+125

3.6

Unit

°C

V_CC1

1

3.0

V

V_CCQ1

V_PPH1

V_PPH2

Cycling

1,2

1

3.0

3.6

V_PPSupply Voltage

3.0

3.6

V

V_PPSupply Voltage

1,3

11.4

30,000

1,000

12.6

V

Parameter Block Erase Cycling

Main Block Erase Cycling

Cycles

NOTES:

1. See DC Characteristics tables for voltage range-specific specifications.

2. The voltage swing on the inputs, V_INis required to match V_CCQ

.

3. Applying V_PP= 11.4 V–12.6 V during a program/erase can only be done for a maximum of 1000 cycles on the main and

parameter blocks. A hard connection to V_PP= 11.4 V–12.6 V is not allowed and can cause damage to the device.

41

PRODUCT PREVIEW

FAST BOOT BLOCK DATASHEET

E

(1)

8.10 Capacitance

T_A= +25°C, f = 1 MHz

Sym

Parameter

Input Capacitance

Output Capacitance

Typ

6

Max

8

Unit

pF

Condition

V_IN= 0.0 V

C_IN

C_OUT

8

12

pF

V_OUT= 0.0 V

NOTE:

1. Sampled, not 100% tested.

V_CCQ

Input

0V

V

_CCQ/2

Test Points

V_CCQ/2

Output

AC test inputs are driven at 3.0 V for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends, at

V_CCQ/2. Input rise and fall times (10% to 90%) < 5 ns. Worst case speed conditions are when V_CCQ= 3.0 V.

Figure 22. Transient Input/Output Reference Waveform for V_CC= 3.3 V ± 0.3 V

Test Configuration Component Value

for Worst Case Speed Conditions

V_CCQ

Test Configuration C_L(pF) R₁(Ω) R₂(Ω)

R₁

3 V Standard Test

80

25K

NOTE:

Device

Under Test

Out

C_Lincludes jig capacitance.

C_L

R₂

NOTE:

See table for component values.

Figure 23. Transient Equivalent Testing

Load Circuit

42

PRODUCT PREVIEW

E

FAST BOOT BLOCK DATASHEET

(1) _—

8.11 DC Characteristics

Automotive Temperature

Sym

Parameter

Note Typ Max Unit

Test Condition

I_CCSV_CCStandby Current

2,6

40

60

75

µA V_CC= V_CCMax

V_CCQ= V_CCQMax

CE# = RST# = V_IH

I_CCRV_CCRead Current

4,6

mA Asynchronous V_CC= V_CCMax

t_AVAV= Min

V_CCQ= V_CCQMax

V_IN= V_IHor V_IL

mA Synchronous

CE# = V_IL

CLK = 22 MHz OE# = V_IH

Burst length = 1

I_CCWV_CCProgram Current

3,5,7

8

20

40

25

mA V_PP= V_PPH1(3.0 V–3.6 V)

Program in progress

mA V_PP= V_PPH2(11.4 V–12.6 V)

Program in progress

I_CCEV_CCBlock Erase

Current

mA V_PP= V_PPH1(3.0 V–3.6 V)

Block erase in progress

mA V_PP= V_PPH2(11.4 V–12.6 V)

Block erase in progress

I_PPWV_PPProgram Current

3,5,7 15

mA V_PP= V_PPH1(3.0 V–3.6 V)

Program in progress

10

3,5,7 13

8

mA V_PP= V_PPH2(11.4 V–12.6 V)

Program in progress

I_PPE

V_PPBlock Erase

Current

mA V_PP= V_PPH1(3.0 V–3.6 V)

Block erase in progress

mA V_PP= V_PPH2(11.4 V–12.6 V)

Block erase in progress

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at normal V_CC, T = +25 °C.

2. Erases and program operations are inhibited when V_PP≤ V_PPLK, and not guaranteed outside the valid V_PPranges of V_PPH1

and V_PPH2

.

3. Sampled, not 100% tested.

4. Automatic Power Savings (APS) reduces I_CCRto approximately standby levels, in static operation.

5. 12 V (11.4 V–12.6 V) can only be applied to V for a maximum of 80 hours over the lifetime of the device. V should not

PP PP

be permanently tied to 12 V.

6. The specification is the sum of V_CCand V_CCQcurrents.

PRODUCT PREVIEW

43

FAST BOOT BLOCK DATASHEET

E

(1) _—

8.12 AC Characteristics—Read-Only Operations

Automotive Temperature

#

Sym

Parameter

Notes

Min

15

Max

Unit

ns

R1 t_CLK

CLK Period

R2 t_CH(t_CL

)

CLK High (Low) Time

2.5

R3 t_CHCL(t_CLCH

R4 t_AVCH

R5 t_VLCH

R6 t_ELCH

R7 t_CHQV

R8 t_CHQX

R9 t_CHAX

)

CLK Fall (Rise) Time

5

Address Valid Setup to CLK

ADV# Low Setup to CLK

CE# Low Setup to CLK

CLK to Output Delay

17

30

Output Hold from CLK

5

Address Hold from CLK

CLK to WAIT# delay

3

5

10

R10 t_CHTL(t_CHTH

R11 t_AVVH

R12 t_ELVH

R13 t_AVQV

R14 t_ELQV

R15 t_VLQV

R16 t_VLVH

R17 t_VHVL

R18 t_VHAX

R19 t_APA

)

30

Address Setup to ADV# Going High

CE# Low to ADV# Going High

Address to Output Delay

CE# Low to Output Delay

ADV# Low to Output Delay

ADV# Pulse Width

19

150

2

3

19

3

ADV# Pulse Width

Address Hold from ADV# Going High

Page Address Access Time

OE# Low to Output Delay

RST# High to Output Delay

35

50

R20 t_GLQV

R21 t_RHQV

600

40

R22 t_EHQZ

t_GHQZ

CE# or OE# High to Output in High Z,

Whichever Occurs First

4

R23 t_OH

Output Hold from Address, CE#, or OE#

Change, Whichever Occurs First

0

ns

NOTES:

1. See AC Input/Output Reference Waveform for timing measurements and maximum allowable input slew rate.

2. OE# may be delayed up to t_ELQV-t_GLQVafter the falling edge of CE# without impact on t_ELQV

.

3. Sampled, not 100% tested.

4. Output loading on WAIT# equals 15 pF.

PRODUCT PREVIEW

44

E

FAST BOOT BLOCK DATASHEET

8.13 Automotive Temperature Frequency Configuration Settings

Table 11. Frequency Configuration Settings for Automotive Temperature Components

Frequency Configuration Code

Input CLK Frequency

Reserved

1

2

3

4

5

6

≤ 22 MHz

≤ 33 MHz

≤ 40 MHz

≤ 50 MHz

≤ 66 MHz

(3,4,5)

Max

8.14 Automotive Temperature Block Erase and Program Performance

3.3 V V_PP

Notes Typ⁽¹⁾

Max

12 V V_PP

#

Sym

W19 t_WHRH1, Program Time

t_EHRH1Block Program Time (Parameter)

Parameter

Typ⁽¹⁾

Unit

2

23.5

0.10

0.8

1

TDB

8

TDB

µs

sec

µs

0.03

0.24

0.8

1.1

5

Block Program Time (Main)

t_WHRH2, Block Erase Time (Parameter)

t_EHRH2Block Erase Time (Main)

1.8

6

t_WHRH5, Program Suspend Latency

t_EHRH5

t_WHRH6, Erase Suspend Time

t_EHRH6

13

TDB

10

TDB

µs

NOTES:

1. Typical values measured at T_A= +25°C and nominal voltages. Subject to change based on device characterization.

2. Excludes system-level overhead.

3. These performance numbers are validfor all speed versions.

4. Sampled, but not 100% tested.

5. Reference the AC Waveform for Write Operations Figure 20.

PRODUCT PREVIEW

45

FAST BOOT BLOCK DATASHEET

9.0 ORDERING INFORMATION

E

D T 2 8 F 1 6 0 F 3 T 1 2 0

Package

DT = Extended temp.,

56-Lead SSOP

DE = Automotive temp.,

56-Lead SSOP

Access Speed (ns)

(95,120,150)

GT = Extended temp.,

56-Ball µBGA* CSP

T = Top Blocking

B = Bottom Blocking

Product line designator

for all Intel Flash products

Product Family

F3 = Fast Boot Block

V_CC= 2.7V - 3.6V

Device Density

160 = x16 (16-Mbit)

800 = x16 (8-Mbit)

V_PP= 2.7V - 3.6V or 11.4V - 12.6V

VALID COMBINATIONS

56-Lead SSOP

56-Ball µBGA CSP⁽¹⁾

GT28F160F3T120

GT28F160F3B120

GT28F160F3T95

GT28F160F3B95

Extended

16M

8M

DT28F160F3T120

DT28F160F3B120

DT28F160F3T95

DT28F160F3B95

DT28F800F3T120

DT28F800F3B120

DT28F800F3T95

DT28F800F3B95

GT28F800F3T120

GT28F800F3B120

GT28F800F3T95

GT28F800F3B95

Automotive

NOTE:

8M

DE28F800B3T150

DE28F800B3B150

1.

The 56-Ball µBGA package top side mark reads F160F3 [or F800F3]. All product shipping boxes or trays provide the

correct information regarding bus architecture.

PRODUCT PREVIEW

46

E

FAST BOOT BLOCK DATASHEET

(1,2)

10.0 ADDITIONAL INFORMATION

Order Number

Document/Tool

210830

292213

Flash Memory Databook

AP-655 Fast Boot Block Design Guide

Fast Boot Block CPU Design Guide

Contact

Intel/Distribution

Sales Office

297846

Comprehensive User’s Guide for µBGA* Package

See Intel’s

World Wide Web

Home Page

Micro Ball Grid Array Package Mechanical Specification and Media Information

NOTES:

1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should

contact their local Intel or distribution sales office.

2. Visit Intel’s World Wide Web home page at http://www.intel.com for technical documentation and tools.

PRODUCT PREVIEW

47


型号：	GT28F800F3T120
厂家：	INTEL
描述：	FAST BOOT BLOCK FLASH MEMORY FAMILY 8 AND 16 MBIT FAST BOOT BLOCK闪存系列8位和16 MBIT 闪存存储内存集成电路
文件：	总47页 (文件大小：274K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

GT28F800F3T120 [INTEL]

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