EP4SGX360NF45I2N [INTEL]
Field Programmable Gate Array, 141440 CLBs, PBGA1932, LEAD FREE, FBGA-1932;
| 型号： | EP4SGX360NF45I2N |
| 厂家： | 
INTEL |
| 描述： | Field Programmable Gate Array, 141440 CLBs, PBGA1932, LEAD FREE, FBGA-1932 栅 |
| 文件： | 总82页 (文件大小：1455K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
101 Innovation Drive
San Jose, CA 95134
www.altera.com
SIV5V4-5.7
© 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
ISO
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and 9001:2008
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service Registered
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Contents
Chapter Revision Dates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
Section I. Device Datasheet and Addendum for Stratix IV Devices
Chapter 1. DC and Switching Characteristics for Stratix IV Devices
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–7
Internal Weak Pull-Up Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–11
I/O Standard Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–12
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–15
Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–15
Transceiver Performance Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–16
Transceiver Datapath PCS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–47
Core Performance Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–47
Clock Tree Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–47
PLL Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–48
DSP Block Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–50
TriMatrix Memory Block Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–51
Configuration and JTAG Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–52
Temperature Sensing Diode Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–53
Chip-Wide Reset (Dev_CLRn) Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–54
Periphery Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–54
High-Speed I/O Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–54
OCT Calibration Block Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–61
Duty Cycle Distortion (DCD) Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–62
I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–62
Programmable IOE Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–63
Programmable Output Buffer Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–63
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–64
Chapter 2. Addendum to the Stratix IV Device Handbook
Additional Information
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
iv
Contents
Stratix IV Device Handbook
January 2014 Altera Corporation
Volume 4: Device Datasheet and Addendum
Chapter Revision Dates
The chapters in this document, Stratix IV Device Handbook, were revised on the
following dates. Where chapters or groups of chapters are available separately, part
numbers are listed.
Chapter 1. DC and Switching Characteristics for Stratix IV Devices
Revised:
January 2014
Part Number: SIV54001-5.7
Chapter 2. Addendum to the Stratix IV Device Handbook
Revised:
February 2011
Part Number: SIV54002-1.5
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
vi
Chapter Revision Dates
Stratix IV Device Handbook
January 2014 Altera Corporation
Volume 4: Device Datasheet and Addendum
Section I. Device Datasheet and
Addendum for Stratix IV Devices
This section includes the following chapters:
■
Chapter 1, DC and Switching Characteristics for Stratix IV Devices
Chapter 2, Addendum to the Stratix IV Device Handbook
■
Revision History
Refer to each chapter for its own specific revision history. For information on when
each chapter was updated, refer to the Chapter Revision Dates section, which appears
in the full handbook.
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
I–2
Section I: Device Datasheet and Addendum for Stratix IV Devices
Stratix IV Device Handbook
January 2014 Altera Corporation
Volume 4: Device Datasheet and Addendum
1. DC and Switching Characteristics for
Stratix IV Devices
January 2014
SIV54001-5.7
SIV54001-5.7
This chapter contains the following sections:
■
■
■
■
“Electrical Characteristics”
“Switching Characteristics”
“I/O Timing”
“Glossary”
Electrical Characteristics
This chapter covers the electrical and switching characteristics for Stratix® IV devices.
Electrical characteristics include operating conditions and power consumption.
Switching characteristics include transceiver specifications, core, and periphery
performance. This chapter also describes I/O timing, including programmable I/O
element (IOE) delay and programmable output buffer delay.
f
For information regarding the densities and packages of devices in the Stratix IV
family, refer to the Stratix IV Device Family Overview chapter.
Operating Conditions
When you use Stratix IV devices, they are rated according to a set of defined
parameters. To maintain the highest possible performance and reliability of the
Stratix IV devices, you must consider the operating requirements described in this
chapter.
Stratix IV devices are offered in commercial, industrial, and military grades.
Commercial devices are offered in –2 (fastest), –2×, –3, and –4 speed grades. Industrial
devices are offered in –1, –2, –3, and –4 speed grades. Military devices are offered in –3
speed grade.
For the Stratix IV GT –1 and –2 speed grade specifications, refer to the –2/–2× speed
grade column. For the Stratix IV GT –3 speed grade specification, refer to the –3 speed
grade column, unless otherwise specified.
Absolute Maximum Ratings
Absolute maximum ratings define the maximum operating conditions for Stratix IV
devices. The values are based on experiments conducted with the devices and
theoretical modeling of breakdown and damage mechanisms. The functional
operation of the device is not implied for these conditions.
© 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
January 2014
Feedback Subscribe
1–2
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Electrical Characteristics
c Conditions other than those listed in Table 1–1, Table 1–2, and Table 1–3 may cause
permanent damage to the device. Additionally, device operation at the absolute
maximum ratings for extended periods of time may have adverse effects on the
device.
Table 1–1. Absolute Maximum Ratings for Stratix IV Devices
Symbol
VCC
Description
Core voltage and periphery circuitry power supply
Power supply for programmable power technology
Configuration pins power supply
Auxiliary supply for the programmable power technology
Battery back-up power supply for design security volatile key register
I/O pre-driver power supply
Minimum
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-25
Maximum
1.35
1.8
Unit
V
VCCPT
VCCPGM
VCCAUX
VCCBAT
VCCPD
VCCIO
V
3.75
3.75
3.75
3.75
3.9
V
V
V
V
I/O power supply
V
VCC_CLKIN
VCCD_PLL
VCCA_PLL
VI
Differential clock input power supply
PLL digital power supply
3.75
1.35
3.75
4.0
V
V
PLL analog power supply
V
DC input voltage
V
IOUT
DC output current per pin
40
mA
°C
°C
TJ
Operating junction temperature
-55
125
TSTG
Storage temperature (No bias)
-65
150
Table 1–2. Transceiver Power Supply Absolute Maximum Ratings for Stratix IV GX Devices
Symbol
VCCA_L
Description
Transceiver high voltage power (left side)
Transceiver high voltage power (right side)
Transceiver HIP digital power (left side)
Transceiver HIP digital power (right side)
Receiver power (left side)
Minimum
-0.5
Maximum
3.75
3.75
1.35
1.35
1.35
1.35
1.35
1.35
1.35
1.35
1.8
Unit
V
VCCA_R
-0.5
V
VCCHIP_L
VCCHIP_R
VCCR_L
-0.5
V
-0.5
V
-0.5
V
VCCR_R
Receiver power (right side)
-0.5
V
VCCT_L
Transmitter power (left side)
-0.5
V
VCCT_R
Transmitter power (right side)
-0.5
V
(1)
(1)
(1)
(1)
VCCL_GXBLn
VCCL_GXBRn
VCCH_GXBLn
VCCH_GXBRn
Transceiver clock power (left side)
Transceiver clock power (right side)
Transmitter output buffer power (left side)
Transmitter output buffer power (right side)
-0.5
V
-0.5
V
-0.5
V
-0.5
1.8
V
Note to Table 1–2:
(1) n = 0, 1, 2, or 3.
Stratix IV Device Handbook
January 2014 Altera Corporation
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–3
Electrical Characteristics
Table 1–3. Transceiver Power Supply Absolute Maximum Ratings for Stratix IV GT Devices (1)
Symbol
VCCA_L
Description
Transceiver high voltage power (left side)
Transceiver high voltage power (right side)
Transceiver HIP digital power (left side)
Transceiver HIP digital power (right side)
Receiver power (left side)
Minimum
-0.5
Maximum
3.75
3.75
1.35
1.35
1.35
1.35
1.35
1.35
1.35
1.35
1.8
Unit
V
V
V
V
V
V
V
V
V
V
V
V
VCCA_R
-0.5
VCCHIP_L
VCCHIP_R
VCCR_L
-0.5
-0.5
-0.5
VCCR_R
Receiver power (right side)
-0.5
VCCT_L
Transmitter power (left side)
-0.5
VCCT_R
Transmitter power (right side)
-0.5
(2)
(2)
(2)
(2)
VCCL_GXBLn
VCCL_GXBRn
VCCH_GXBLn
VCCH_GXBRn
Transceiver clock power (left side)
Transceiver clock power (right side)
Transmitter output buffer power (left side)
Transmitter output buffer power (right side)
-0.5
-0.5
-0.5
-0.5
1.8
Notes to Table 1–3:
(1) For the absolute maximum ratings for Stratix IV GT engineering sample (ES1) devices, contact your local Altera sales representative.
(2) n = 0, 1, 2, or 3.
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–4
Electrical Characteristics
Maximum Allowed Overshoot and Undershoot Voltage
During transitions, input signals may overshoot to the voltage shown in Table 1–4 and
undershoot to –2.0 V for input currents less than 100 mA and periods shorter than
20 ns.
Table 1–4 lists the maximum allowed input overshoot voltage and the duration of the
overshoot voltage as a percentage of device lifetime. The maximum allowed
overshoot duration is specified as a percentage of high time over the lifetime of the
device. A DC signal is equivalent to 100% duty cycle. For example, a signal that
overshoots to 4.3 V can only be at 4.3 V for ~5% over the lifetime of the device; for a
device lifetime of 10 years, this amounts to half of a year.
Table 1–4. Maximum Allowed Overshoot During Transitions
Overshoot Duration as
Symbol
Description
Condition (V)
Unit
% of High Time
100.000
79.330
46.270
27.030
15.800
9.240
4.0
4.05
4.1
%
%
%
%
%
%
%
%
%
%
%
%
%
4.15
4.2
4.25
4.3
Vi (AC)
AC input voltage
5.410
4.35
4.4
3.160
1.850
4.45
4.5
1.080
0.630
4.55
4.6
0.370
0.220
Temperature Overshoot Above Maximum Allowed Temperature
The maximum allowed operating temperature for Stratix IV industrial grade devices
is 100 °C. It is recommended that the operating temperature of the device is
maintained below 100 °C at all times. The temperature excursions over 100 °C due to
internal heating of the device should not exceed the number of cycles as specified in
the Table 1–5. Exceeding the recommended number of cycles may cause solder
interconnect failures. Altera® recommends using the Stratix IV military grade devices
if the application requires operating temperatures over 100 °C.
Table 1–5. Temperature Overshoot Above Maximum Allowed Temperature
Description
Operating Temperature (°C)
Number of Cycles Over 100 °C
100
105
110
115
120
125
3200
768
640
480
320
160
Device operating
temperature (°C)
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–5
Electrical Characteristics
Recommended Operating Conditions
This section lists the functional operation limits for AC and DC parameters for
Stratix IV devices. Table 1–6 lists the steady-state voltage and current values expected
from Stratix IV devices. Power supply ramps must all be strictly monotonic, without
plateaus.
f
For power supply ripple requirements, refer to the Device-Specific Power Delivery
Network (PDN) Tool User Guide.
Table 1–6. Recommended Operating Conditions for Stratix IV Devices (Part 1 of 2)
Symbol
CC (Stratix IV GX Core voltage and periphery circuitry power
and Stratix IV E) supply
Description
Condition
Minimum
Typical
Maximum Unit
V
—
0.87
0.90
0.93
0.98
V
V
V
V
VCC
Core voltage and periphery circuitry power
supply
—
—
—
0.92
1.45
0.95
1.5
(Stratix IV GT)
Power supply for programmable power
technology
VCCPT
1.55
Auxiliary supply for the programmable
power technology
VCCAUX
2.375
2.5
2.625
I/O pre-driver (3.0 V) power supply
I/O pre-driver (2.5 V) power supply
I/O buffers (3.0 V) power supply
—
—
—
—
—
—
—
—
—
—
—
2.85
2.375
2.85
3.0
2.5
3.0
2.5
1.8
1.5
1.2
3.0
2.5
1.8
2.5
3.15
2.625
3.15
V
V
V
V
V
V
V
V
V
V
V
(2)
VCCPD
I/O buffers (2.5 V) power supply
2.375
1.71
2.625
1.89
VCCIO
I/O buffers (1.8 V) power supply
I/O buffers (1.5 V) power supply
1.425
1.14
1.575
1.26
I/O buffers (1.2 V) power supply
Configuration pins (3.0 V) power supply
Configuration pins (2.5 V) power supply
Configuration pins (1.8 V) power supply
PLL analog voltage regulator power supply
2.85
3.15
VCCPGM
2.375
1.71
2.625
1.89
VCCA_PLL
2.375
2.625
VCCD_PLL
(Stratix IV GX
and Stratix IV E)
PLL digital voltage regulator power supply
—
0.87
0.90
0.93
V
VCCD_PLL
(Stratix IV GT)
PLL digital voltage regulator power supply
Differential clock input power supply
—
—
—
0.92
2.375
1.2
0.95
2.5
—
0.98
2.625
3.3
V
V
V
VCC_CLKIN
Battery back-up power supply (For design
security volatile key register)
(1)
VCCBAT
VI
DC input voltage
Output voltage
—
–0.5
0
—
—
—
—
—
—
3.6
VCCIO
85
V
VO
—
V
Commercial
Industrial
Military
Industrial
0
°C
°C
°C
°C
TJ (Stratix IV GX
and Stratix IV E)
Operating junction temperature
–40
–55
0
100
125
100
TJ (Stratix IV GT) Operating junction temperature
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–6
Electrical Characteristics
Table 1–6. Recommended Operating Conditions for Stratix IV Devices (Part 2 of 2)
Symbol
Description
Condition
Minimum
Typical
Maximum Unit
Normal POR
(PORSEL=0)
0.05
—
100
4
ms
ms
tRAMP
Power supply ramp time
Fast POR
(PORSEL=1)
0.05
—
Notes to Table 1–6:
(1) If you do not use the volatile security key, you may connect the VCCBAT to either GND or a 3.0-V power supply.
(2) VCCPD must be 2.5 V when VCCIO is 2.5, 1.8, 1.5, or 1.2 V. VCCPD must be 3.0 V when VCCIO is 3.0 V.
Table 1–7 lists the transceiver power supply recommended operating conditions for
Stratix IV GX devices.
(1)
Table 1–7. Transceiver Power Supply Operating Conditions for Stratix IV GX Devices
Symbol
VCCA_L
Description
Transceiver high voltage power (left side)
Transceiver high voltage power (right side)
Transceiver HIP digital power (left side)
Transceiver HIP digital power (right side)
Receiver power (left side)
Minimum
Typical
Maximum
Unit
2.85/2.375 3.0/2.5 (2) 3.15/2.625
V
VCCA_R
VCCHIP_L
VCCHIP_R
VCCR_L
0.87
0.87
0.9
0.9
1.1
1.1
1.1
1.1
1.1
1.1
0.93
0.93
V
V
V
V
V
V
V
V
1.045
1.045
1.045
1.045
1.05
1.155
1.155
1.155
1.155
1.15
VCCR_R
Receiver power (right side)
VCCT_L
Transmitter power (left side)
VCCT_R
Transmitter power (right side)
(3)
(3)
(3)
(3)
VCCL_GXBLn
VCCL_GXBRn
VCCH_GXBLn
VCCH_GXBRn
Transceiver clock power (left side)
Transceiver clock power (right side)
Transmitter output buffer power (left side)
Transmitter output buffer power (right side)
1.05
1.15
1.33/1.425 1.4/1.5 (4) 1.47/1.575
V
Notes to Table 1–7:
(1) Transceiver power supplies do not have power-on-reset (POR) circuitry. After initial power-up, violating the transceiver power supply operating
conditions could lead to unpredictable link behavior.
(2) VCCA_L/R must be connected to a 3.0-V supply if the clock multiplier unit (CMU) phase-locked loop (PLL), receiver clock data recovery (CDR),
or both, are configured at a base data rate > 4.25 Gbps. For data rates up to 4.25 Gbps, you can connect VCCA_L/R to either 3.0 V or 2.5 V.
(3) n = 0, 1, 2, or 3.
(4) VCCH_GXBL/R must be connected to a 1.4-V supply if the transmitter channel data rate is > 6.5 Gbps. For data rates up to 6.5 Gbps, you can
connect VCCH_GXBL/R to either 1.4 V or 1.5 V.
Table 1–8 lists the recommended operating conditions for the Stratix IV GT
transceiver power supply.
(2)
Table 1–8. Transceiver Power Supply Operating Conditions for Stratix IV GT Devices (Part 1 of 2) (1)
,
Symbol
VCCA_L
Description
Minimum
3.17
Typical
3.3
Maximum
3.43
Unit
V
Transceiver high voltage power (left side)
Transceiver high voltage power (right side)
Transceiver HIP digital power (left side)
Transceiver HIP digital power (right side)
Receiver power (left side)
VCCA_R
3.17
3.3
3.43
V
VCCHIP_L
VCCHIP_R
VCCR_L
0.92
0.95
0.95
1.2
0.98
V
0.92
0.98
V
1.15
1.25
V
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–7
Electrical Characteristics
(2)
Table 1–8. Transceiver Power Supply Operating Conditions for Stratix IV GT Devices (Part 2 of 2) (1)
,
Symbol
VCCR_R
Description
Receiver power (right side)
Minimum
1.15
Typical
1.2
Maximum Unit
1.25
1.25
1.25
1.25
1.25
1.47
1.47
V
V
V
V
V
V
V
VCCT_L
Transmitter power (left side)
1.15
1.2
VCCT_R
Transmitter power (right side)
1.15
1.2
(3)
(3)
(3)
(3)
VCCL_GXBLn
VCCL_GXBRn
VCCH_GXBLn
VCCH_GXBRn
Transceiver clock power (left side)
Transceiver clock power (right side)
Transmitter output buffer power (left side)
Transmitter output buffer power (right side)
1.15
1.2
1.15
1.2
1.33
1.4
1.33
1.4
Notes to Table 1–8:
(1) For the recommended operating conditions for Stratix IV GT engineering sample (ES1) devices, contact your local Altera sales representative.
(2) Transceiver power supplies do not have power-on-reset circuitry. After initial power-up, violating the transceiver power supply operating
conditions could lead to unpredictable link behavior.
(3) n = 0, 1, 2, or 3.
DC Characteristics
This section lists the supply current, I/O pin leakage current, bus hold, on-chip
termination (OCT) tolerance, input pin capacitance, and hot socketing specifications.
Supply Current
Standby current is the current drawn from the respective power rails used for power
budgeting. Use the Excel-based Early Power Estimator (EPE) to get supply current
estimates for your design because these currents vary greatly with the resources you
use.
f
For more information about power estimation tools, refer to the PowerPlay Early Power
Estimator User Guide and the PowerPlay Power Analysis chapter in the Quartus II
Handbook.
I/O Pin Leakage Current
Table 1–9 lists the Stratix IV I/O pin leakage current specifications.
(1)
Table 1–9. I/O Pin Leakage Current for Stratix IV Devices
Symbol
II
IOZ
Description
Input pin
Tri-stated I/O pin
Conditions
VI = 0V to VCCIOMAX
VO = 0V to VCCIOMAX
Min
-20
-20
Typ
—
Max
20
Unit
µA
—
20
µA
Note to Table 1–9:
(1) VREF current refers to the input pin leakage current.
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–8
Electrical Characteristics
Bus Hold Specifications
Table 1–10 lists the Stratix IV device family bus hold specifications.
Table 1–10. Bus Hold Parameters
VCCIO
Parameter Symbol Conditions
1.2 V
1.5 V
1.8 V
2.5 V
3.0 V
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Low
sustaining
current
VIN > VIL
ISUSL
ISUSH
IODL
22.5
-22.5
—
—
25.0
-25.0
—
—
30.0
-30.0
—
—
50.0
-50.0
—
—
70.0
-70.0
—
—
µA
µA
µA
(maximum)
High
sustaining
current
VIN < VIH
—
—
—
—
—
(minimum)
Low
overdrive
current
0V < VIN
VCCIO
<
120
-120
160
-160
200
-200
300
-300
500
High
overdrive
current
0V < VIN
VCCIO
<
IODH
—
—
—
—
—
-500 µA
Bus-hold
trip point
VTRIP
—
0.45 0.95 0.50 1.00 0.68 1.07 0.70 1.70 0.80 2.00
V
On-Chip Termination (OCT) Specifications
If you enable OCT calibration, calibration is automatically performed at power-up for
I/Os connected to the calibration block. Table 1–11 lists the Stratix IV OCT
termination calibration accuracy specifications.
(1)
Table 1–11. OCT Calibration Accuracy Specifications for Stratix IV Devices (Part 1 of 2)
Calibration Accuracy
Symbol
Description
Conditions
Unit
%
C2
C3,I3, M3
C4,I4
Internal series termination
with calibration (25-
setting)
(2)
25- RS
VCCIO = 3.0, 2.5, 1.8,
1.5, 1.2 V
8
8
8
8
3.0, 2.5, 1.8, 1.5, 1.2
Internal series termination
with calibration (50-
setting)
50- RS
V
V
CCIO = 3.0, 2.5, 1.8,
1.5, 1.2 V
8
8
%
3.0, 2.5, 1.8, 1.5, 1.2
Internal parallel termination
with calibration (50-
setting)
50- RT
CCIO = 2.5, 1.8, 1.5,
1.2 V
10
10
10
%
2.5, 1.8, 1.5, 1.2
Expanded range for internal
series termination with
calibration (20- , 40- and
60- RS setting)
20- , 40- , and
60- RS
VCCIO = 3.0, 2.5, 1.8,
1.5, 1.2 V
(3)
10
10
10
%
3.0, 2.5, 1.8, 1.5, 1.2
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–9
Electrical Characteristics
(1)
Table 1–11. OCT Calibration Accuracy Specifications for Stratix IV Devices (Part 2 of 2)
Calibration Accuracy
Symbol
Description
Conditions
Unit
C2
C3,I3, M3
C4,I4
Internal left shift series
termination with calibration
(25- RS_left_shift setting)
25- RS_left_shift
VCCIO = 3.0, 2.5, 1.8,
1.5, 1.2 V
10
10
10
%
3.0, 2.5, 1.8, 1.5, 1.2
Notes to Table 1–11:
(1) OCT calibration accuracy is valid at the time of calibration only.
(2) 25- RS is not supported for 1.5 V and 1.2 V in Row I/O.
(3) 20- RS is not supported for 1.5 V and 1.2 V in Row I/O.
The calibration accuracy for calibrated series and parallel OCTs are applicable at the
moment of calibration. When process, voltage, and temperature (PVT) conditions
change after calibration, the tolerance may change. Table 1–12 lists the Stratix IV OCT
without calibration resistance tolerance to PVT changes.
Table 1–12. OCT Without Calibration Resistance Tolerance Specifications for Stratix IV Devices
Resistance Tolerance
Symbol
Description
Conditions
Unit
%
C2
C3,I3, M3
C4,I4
Internal series termination
without calibration (25-
setting)
25- RS
VCCIO = 3.0 and 2.5 V
30
40
40
3.0 and 2.5
Internal series termination
without calibration (25-
setting)
25- RS
V
CCIO = 1.8 and 1.5 V
30
35
30
30
40
50
40
40
40
50
40
40
%
1.8 and 1.5
Internal series termination
without calibration (25-
setting)
25- RS
VCCIO = 1.2 V
%
1.2
Internal series termination
without calibration (50-
setting)
50- RS
VCCIO = 3.0 and 2.5 V
%
3.0 and 2.5
Internal series termination
without calibration (50-
setting)
50- RS
V
CCIO = 1.8 and 1.5 V
%
1.8 and 1.5
Internal series termination
without calibration (50-
setting)
50- RS
V
CCIO = 1.2 V
CCIO = 2.5 V
35
25
50
25
50
25
%
%
1.2
100- RD
Internal differential
termination (100- setting)
V
2.5
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–10
Electrical Characteristics
OCT calibration is automatically performed at power-up for OCT-enabled I/Os.
Table 1–13 lists OCT variation with temperature and voltage after power-up
calibration. Use Table 1–13 to determine the OCT variation after power-up calibration
and Equation 1–1 to determine the OCT variation without re-calibration.
(2) (3) (4) (5) (6)
Equation 1–1. OCT Variation Without Re-Calibration (1)
,
,
,
,
,
dR
dT
dR
dV
------
-------
V
ROCT = R
1 +
T
SCAL
Notes to Equation 1–1:
(1) The ROCT value calculated from Equation 1–1 shows the range of OCT resistance with the variation of temperature
and VCCIO
.
(2) RSCAL is the OCT resistance value at power-up.
(3) T is the variation of temperature with respect to the temperature at power-up.
(4) V is the variation of voltage with respect to the VCCIO at power-up.
(5) dR/dT is the percentage change of RSCAL with temperature.
(6) dR/dV is the percentage change of RSCAL with voltage.
Table 1–13 lists the OCT variation after the power-up calibration.
(1)
Table 1–13. OCT Variation after Power-Up Calibration
Symbol
Description
VCCIO (V)
3.0
Typical
0.0297
0.0344
0.0499
0.0744
0.1241
0.189
Unit
2.5
OCT variation with voltage without
re-calibration
dR/dV
1.8
%/mV
1.5
1.2
3.0
2.5
0.208
OCT variation with temperature
without re-calibration
dR/dT
1.8
0.266
%/°C
1.5
0.273
1.2
0.317
Note to Table 1–13:
(1) Valid for VCCIO range of 5% and temperature range of 0° to 85°C.
Pin Capacitance
Table 1–14 lists the Stratix IV device family pin capacitance.
Table 1–14. Pin Capacitance for Stratix IV Devices (Part 1 of 2)
Symbol
Description
Value
Unit
pF
CIOTB
Input capacitance on the top and bottom I/O pins
4
4
4
4
CIOLR
Input capacitance on the left and right I/O pins
pF
CCLKTB
CCLKLR
Input capacitance on the top and bottom non-dedicated clock input pins
Input capacitance on the left and right non-dedicated clock input pins
pF
pF
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–11
Electrical Characteristics
Table 1–14. Pin Capacitance for Stratix IV Devices (Part 2 of 2)
Symbol
Description
Value
Unit
COUTFB
Input capacitance on the dual-purpose clock output and feedback pins
5
pF
CCLK1, CCLK3, CCLK8
and CCLK10
,
Input capacitance for dedicated clock input pins
2
pF
Hot Socketing
Table 1–15 lists the hot socketing specifications for Stratix IV devices.
Table 1–15. Hot Socketing Specifications for Stratix IV Devices
Symbol
IIOPIN (DC)
Description
DC current per I/O pin
Maximum
300 A
(1)
IIOPIN (AC)
AC current per I/O pin
8 mA
IXCVR-TX (DC)
DC current per transceiver TX pin
DC current per transceiver RX pin
100 mA
50 mA
IXCVR-RX (DC)
Note to Table 1–15:
(1) The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C dv/dt, in which C is the I/O pin
capacitance and dv/dt is the slew rate.
Internal Weak Pull-Up Resistor
Table 1–16 lists the weak pull-up resistor values for Stratix IV devices.
(1) (3)
Table 1–16. Internal Weak Pull-Up Resistor for Stratix IV Devices
,
(4)
Symbol
Description
Conditions (V)
CCIO = 3.0 5%
CCIO = 2.5 5%
Value
25
Unit
k
k
k
k
k
(2)
(2)
(2)
(2)
(2)
V
V
Value of the I/O pin pull-up resistor before
and during configuration, as well as user
mode if the programmable pull-up resistor
option is enabled.
25
RPU
VCCIO = 1.8 5%
VCCIO = 1.5 5%
25
25
V
CCIO = 1.2 5%
25
Notes to Table 1–16:
(1) All I/O pins have an option to enable weak pull-up except configuration, test, and JTAG pins.
(2) Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO
.
(3) The internal weak pull-down feature is only available for the JTAG TCKpin. The typical value for this internal weak pull-down resistor is
approximately 25 k
(4) These specifications are valid with 10% tolerances to cover changes over PVT.
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–12
Electrical Characteristics
I/O Standard Specifications
Table 1–17 through Table 1–22 list the input voltage (VIH and VIL), output voltage
(VOH and VOL), and current drive characteristics (IOH and IOL) for various I/O
standards supported by Stratix IV devices. These tables also show the Stratix IV
device family I/O standard specifications. VOL and VOH values are valid at the
corresponding IOH and IOL, respectively.
For an explanation of terms used in Table 1–17 through Table 1–22, refer to “Glossary”
on page 1–64.
Table 1–17. Single-Ended I/O Standards
VCCIO (V)
VIL (V)
Max
VIH (V)
VOL (V)
VOH (V)
I/O
IOL
IOH
Standard
(mA)
(mA)
Min
2.85
2.85
2.375
Typ
3
Max
3.15
Min
-0.3
-0.3
-0.3
Min
1.7
1.7
1.7
Max
3.6
3.6
3.6
Max
0.4
0.2
0.4
Min
2.4
LVTTL
LVCMOS
2.5 V
0.8
0.8
0.7
2
0.1
1
-2
-0.1
-1
3
3.15
V
CCIO - 0.2
2
2.5
2.625
0.35 *
VCCIO
0.65 * VCCIO
VCCIO 0.3
+
+
+
VCCIO
0.45
-
1.8 V
1.71
1.425
1.14
2.85
2.85
1.8
1.5
1.2
3
1.89
1.575
1.26
3.15
3.15
-0.3
-0.3
-0.3
—
0.45
2
2
-2
-2
0.35 *
VCCIO
0.65 * VCCIO
VCCIO 0.3
0.25 *
VCCIO
0.75 *
VCCIO
1.5 V
0.35 *
VCCIO
0.65 * VCCIO
0.25 *
VCCIO
0.75 *
VCCIO
1.2 V
2
-2
VCCIO
0.3
0.3 *
VCCIO
0.5 *
VCCIO
0.1 *
VCCIO
3.0-V PCI
3.6
0.9 * VCCIO
0.9 * VCCIO
1.5
1.5
-0.5
-0.5
3.0-V
PCI-X
0.35 *
VCCIO
0.5 *
VCCIO
0.1 *
VCCIO
3
—
—
Table 1–18. Single-Ended SSTL and HSTL I/O Reference Voltage Specifications
VCCIO (V)
Typ
VREF (V)
Typ
VTT (V)
I/O Standard
Min
Max
Min
Max
Min
Typ
Max
VREF
0.04
SSTL-2
Class I, II
0.49 *
VCCIO
0.5 *
VCCIO
0.51 *
VCCIO
VREF
0.04
-
+
2.375
2.5
1.8
1.5
1.8
1.5
1.2
2.625
VREF
SSTL-18
Class I, II
VREF
0.04
-
VREF
+
1.71
1.425
1.71
1.89
1.575
1.89
0.833
0.9
0.969
VREF
0.04
SSTL-15
Class I, II
0.47 *
VCCIO
0.5 *
VCCIO
0.53 *
VCCIO
0.47 *
VCCIO
0.53 *
VCCIO
VREF
HSTL-18
Class I, II
0.85
0.68
0.9
0.95
0.9
—
—
—
V
CCIO/2
CCIO/2
—
—
—
HSTL-15
Class I, II
1.425
1.14
1.575
1.26
0.75
V
HSTL-12
Class I, II
0.47 *
VCCIO
0.5 *
VCCIO
0.53 *
VCCIO
VCCIO/2
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–13
Electrical Characteristics
Table 1–19. Single-Ended SSTL and HSTL I/O Standards Signal Specifications
VIL(AC)
(V)
VIH(AC)
(V)
V
IL(DC) (V)
VIH(DC) (V)
VOL (V)
Max
VOH (V)
Min
I/O Standard
Iol (mA) Ioh (mA)
Min
Max
VREF
0.15
Min
VREF
0.15
Max
Max
Min
SSTL-2
Class I
-
+
VCCIO
0.3
+
+
+
+
VREF
-
VREF
+
VTT
-
VTT
+
-0.3
-0.3
-0.3
-0.3
—
8.1
16.2
6.7
13.4
8
-8.1
0.31
0.31
0.57
0.57
SSTL-2
Class II
VREF
0.15
-
VREF
0.15
+
VCCIO
0.3
VREF
-
VREF
+
VTT
-
VTT +
0.76
-16.2
-6.7
-13.4
-8
0.31
0.31
0.76
SSTL-18
Class I
VREF
0.125
-
VREF
0.125
+
VCCIO
0.3
VREF
-
VREF
+
VTT
-
VTT +
0.475
0.25
0.25
0.475
SSTL-18
Class II
VREF
0.125
-
VREF
0.125
+
VCCIO
0.3
VREF
-
VREF
+
VCCIO
0.28
-
0.28
0.25
0.25
SSTL-15
Class I
VREF
0.1
-
-
VREF
0.1
+
+
+
+
+
+
+
VREF
-
VREF
+
0.2 *
VCCIO
0.8 *
VCCIO
—
—
—
—
—
—
0.175
0.175
SSTL-15
Class II
VREF
0.1
VREF
0.1
VREF
-
VREF
+
0.2 *
VCCIO
0.8 *
VCCIO
—
16
8
-16
-8
0.175
0.175
HSTL-18
Class I
VREF
0.1
VREF
0.2
-
-
-
-
-
VREF
0.2
+
+
+
+
+
VCCIO
0.4
-
—
VREF -0.1
0.4
0.4
0.4
0.4
HSTL-18
Class II
VREF
0.1
-
-
-
VREF
0.1
VREF
0.2
VREF
0.2
VCCIO
0.4
-
-
-
—
16
8
-16
-8
HSTL-15
Class I
VREF
0.1
VREF
0.1
VREF
0.2
VREF
0.2
VCCIO
0.4
—
HSTL-15
Class II
VREF
0.1
VREF
0.1
VREF
0.2
VREF
0.2
VCCIO
0.4
—
16
8
-16
-8
HSTL-12
Class I
VREF
0.08
-
-
VREF
VCCIO
+
+
VREF
VREF
0.25*
VCCIO
0.75*
VCCIO
-0.15
-0.15
0.08
0.15
0.15
0.15
HSTL-12
Class II
VREF
0.08
VREF
+
0.08
VCCIO
0.15
VREF
-
VREF
+
0.25*
VCCIO
0.75*
VCCIO
16
-16
0.15
0.15
Table 1–20. Differential SSTL I/O Standards
VCCIO (V)
Typ Max
VSWING(DC) (V)
Min Max
VX(AC) (V)
VSWING(AC) (V)
Min Max
VOX(AC) (V)
Typ
I/O
Standard
Min
Min
Typ
Max
Min
Max
SSTL-2
Class I, II
VCCIO
0.6
+
VCCIO/2
- 0.2
VCCIO/2
+ 0.2
VCCIO VCCIO/2
+ 0.6 - 0.15
VCCIO/2
+ 0.15
2.375 2.5 2.625 0.3
—
0.62
—
VCCIO/2
-
0.175
VCCIO/2
VCCIO/2
+
0.125
SSTL-18
Class I, II
VCCIO
0.6
+
V
CCIO/2
VCCIO
1.71
1.8
1.89 0.25
—
0.5
-
—
+ 0.175
+ 0.6
0.125
SSTL-15
Class I, II
1.425 1.5 1.575 0.2
—
—
V
CCIO/2
—
0.35
—
—
VCCIO/2
—
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–14
Electrical Characteristics
Table 1–21. Differential HSTL I/O Standards
VCCIO (V)
Typ
VDIF(DC) (V)
VX(AC) (V)
Typ
VCM(DC) (V)
Typ
VDIF(AC) (V)
Min Max
I/O
Standard
Min
Max
Min
Max
Min
Max
Min
Max
HSTL-18
Class I
1.71
1.8
1.5
1.2
1.89
0.2
0.2
—
0.78
—
—
1.12
0.78
—
—
1.12
0.4
0.4
0.3
—
—
HSTL-15
Class I, II
1.425
1.14
1.575
1.26
—
0.68
—
0.9
—
0.68
0.9
HSTL-12
Class I, II
VCCIO
+ 0.3
0.5*
VCCIO
0.4*
VCCIO
0.5*
VCCIO
0.6*
VCCIO
VCCIO
+ 0.48
0.16
(1) (2)
Table 1–22. Differential I/O Standard Specifications
,
(Part 1 of 2)
VICM(DC) (V)
Min Typ Max Min Condition Max Min Condition Max
VCCIO (V) (3)
VID (mV)
VOD (V)
VOCM (V)
(4)
(4)
I/O
Standard
Min Typ Max Min Typ Max
Transmitter, receiver, and input reference clock pins of high-speed transceivers use PCML I/O standard. For
transmitter, receiver, and reference clock I/O pin specifications, refer to Table 1–23 on page 1–16 and Table 1–24 on
page 1–25.
PCML
0.05
D
MAX
1.8
—
—
—
—
—
—
0.247
0.247
—
—
—
—
0.6 1.125 1.25 1.375
0.6 1.125 1.25 1.375
(5)
(5)
700 Mbps
2.5 V LVDS
(HIO)
VCM
1.25 V
=
2.375 2.5 2.625 100
2.375 2.5 2.625 100
1.05
DMAX
700 Mbps
>
1.55 (
(5)
5)
D
MAX
0.05
1.05
0.3
1.8 0.247
1.55 0.247
0.6
0.6
1
1
1.25 1.5
1.25 1.5
700 Mbps
2.5 V LVDS
(VIO)
VCM
1.25 V
=
DMAX
700 Mbps
>
RSDS
(HIO)
VCM
1.25 V
=
2.375 2.5 2.625 100
2.375 2.5 2.625 100
2.375 2.5 2.625 200
2.375 2.5 2.625 200
2.375 2.5 2.625 300
2.375 2.5 2.625 300
—
1.4
1.4
0.1 0.2 0.6
0.1 0.2 0.6
0.5
0.5
1
1.2
1.2
1.2
1.2
—
1.4
1.5
1.4
1.5
—
RSDS
(VIO)
VCM =
1.25 V
0.3
—
—
—
Mini-LVDS
(HIO)
—
600 0.4
1.325 0.25
—
—
—
—
0.6
0.6
—
Mini-LVDS
(VIO)
—
—
—
600 0.4
0.6
1.325 0.25
1.8
1
D
MAX
—
—
—
—
(6)
(6)
700 Mbps
LVPECL (7)
1
DMAX
700 Mbps
>
1.6
—
—
—
—
—
(6)
(6)
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–15
Switching Characteristics
(1) (2)
Table 1–22. Differential I/O Standard Specifications
,
(Part 2 of 2)
VICM(DC) (V)
Min Typ Max Min Condition Max Min Condition Max
2.375 2.5 2.625 100
VCCIO (V) (3)
VID (mV)
VOD (V)
VOCM (V)
(4)
(4)
I/O
Standard
Min Typ Max Min Typ Max
BLVDS (8)
—
—
—
—
—
—
—
—
—
—
—
Notes to Table 1–22:
(1) Vertical I/O (VIO) is top and bottom I/Os; horizontal I/O (HIO) is left and right I/Os.
(2) 1.4-V/1.5-V PCML transceiver I/O standard specifications are described in “Transceiver Performance Specifications” on page 1–16.
(3) Differential clock inputs in column I/O are powered by VCC_CLKIN which requires 2.5 V. Differential inputs that are not on clock pins in column I/O are
powered by VCCPD which requires 2.5 V. All differential inputs in row I/O banks are powered by VCCPD which requires 2.5V.
(4) RL range: 90 RL 110 .
(5) The receiver voltage input range for the data rate when DMAX > 700 Mbps is 1.0 V VIN 1.6 V.
The receiver voltage input range for the data rate when DMAX 700 Mbps is zero V VIN 1.85 V.
(6) The receiver voltage input range for the data rate when DMAX > 700 Mbps is 0.85 V VIN 1.75 V.
The receiver voltage input range for the data rate when DMAX 700 Mbps is 0.45 V VIN 1.95 V.
(7) Column and row I/O banks support LVPECL I/O standards for input operation only on dedicated clock input pins.
(8) For more information about BLVDS interface support in Altera devices, refer to AN522: Implementing Bus LVDS Interfaces in Supported Altera Device
Families.
Power Consumption
Altera offers two ways to estimate power consumption for a design the Excel-based
Early Power Estimator and the Quartus® II PowerPlay Power Analyzer feature.
1
You typically use the interactive Excel-based Early Power Estimator before designing
the FPGA to get a magnitude estimate of the device power. The Quartus II PowerPlay
Power Analyzer provides better quality estimates based on the specifics of the design
after you complete place-and-route. The PowerPlay Power Analyzer can apply a
combination of user-entered, simulation-derived, and estimated signal activities that,
when combined with detailed circuit models, yields very accurate power estimates.
f
For more information about power estimation tools, refer to the PowerPlay Early Power
Estimator User Guide and the PowerPlay Power Analysis chapter in the Quartus II
Handbook.
Switching Characteristics
This section provides performance characteristics of Stratix IV core and periphery
blocks for commercial, industrial, and military grade devices.
The final numbers are based on actual silicon characterization and testing. The
numbers reflect the actual performance of the device under worst-case silicon process,
voltage, and junction temperature conditions. There are no designations on finalized
tables.
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–16
Switching Characteristics
Transceiver Performance Specifications
This section describes transceiver performance specifications.
Table 1–23 lists the Stratix IV GX transceiver specifications.
Table 1–23. Transceiver Specifications for Stratix IV GX Devices (Part 1 of 9)
–3 Commercial/
–3 Military (2)
and –4
Commercial/Industrial
Speed Grade
–2 Commercial
Speed Grade
Industrial and
Symbol/
–2× Commercial
Conditions
Unit
(1)
Description
Speed Grade
Min
Typ
Max Min
Typ
Max
Min
Typ
Max
Reference Clock
Supported I/O
Standards
1.2 V PCML, 1.4 V PCML 1.5 V PCML, 2.5 V PCML, Differential LVPECL (4), LVDS, HCSL
Input frequency
from REFCLKinput
pins
—
—
50
50
—
—
697
425
50
50
—
—
697
325
50
50
—
—
637.5
325
MHz
MHz
Phase frequency
detector (CMU PLL
and receiver CDR)
Absolute VMAX for a
REFCLKpin
—
—
—
—
—
—
—
—
1.6
1.5
—
—
—
—
—
—
1.6
1.5
—
—
—
—
—
—
1.6
1.5
—
V
V
V
Operational VMAX for
a
REFCLKpin
Absolute VMIN for a
REFCLKpin
-0.4
-0.4
-0.4
(21)
Rise/fall time
—
—
—
45
—
—
0.2
55
—
45
—
—
0.2
55
—
45
—
—
0.2
55
UI
%
Duty cycle
Peak-to-peak
differential input
voltage
—
200
30
—
—
1600 200
—
—
1600
33
200
30
—
—
1600
33
mV
Spread-spectrum
modulating clock
frequency
PCIe
PCIe
33
30
kHz
—
0 to
0 to
0 to
Spread-spectrum
downspread
—
—
—
—
—
—
—
—
—
—
—
—
-0.5%
-0.5%
-0.5%
On-chip termination
resistors
—
—
100
100
100
VICM (AC coupled)
1100 10%
1100 10%
1100 10%
mV
HCSL I/O
standard for
PCIe reference
clock
VICM (DC coupled)
250
—
550
250
—
550
250
—
550
mV
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–17
Switching Characteristics
Table 1–23. Transceiver Specifications for Stratix IV GX Devices (Part 2 of 9)
–3 Commercial/
–3 Military (2)
and –4
Commercial/Industrial
Speed Grade
–2 Commercial
Speed Grade
Industrial and
Symbol/
Description
–2× Commercial
Conditions
Unit
(1)
Speed Grade
Min
Typ
—
—
—
—
—
—
Max Min
Typ
—
—
—
—
—
—
Max
Min
—
—
—
—
—
—
Typ
—
—
—
—
—
—
Max
-50
-80
10 Hz
100 Hz
1 KHz
—
—
—
—
—
—
-50
-80
—
—
—
—
—
—
-50
-80
dBc/Hz
dBc/Hz
-110
-120
-120
-130
-110
-120
-120
-130
-110 dBc/Hz
-120 dBc/Hz
-120 dBc/Hz
-130 dBc/Hz
Transmitter REFCLK
Phase Noise
10 KHz
100 KHz
1 MHz
Transmitter REFCLK
Phase Jitter (rms)
for 100 MHz
10 KHz to
20 MHz
—
—
—
3
—
—
—
3
—
—
—
3
ps
(3)
REFCLK
2000
1%
2000
1%
2000
1%
RREF
—
—
—
—
Transceiver Clocks
Calibration block
clock frequency
—
10
—
125
—
10
—
125
—
10
—
125
—
MHz
MHz
fixedclkclock
frequency
PCIe Receiver
Detect
—
125
—
125
—
125
Dynamic
reconfiguration 37.5
clock frequency
2.5/
2.5/
2.5/
reconfig_clk
clock frequency
—
—
50
2
37.5
—
—
50
2
37.5
—
—
50
2
—
(5)
(5)
(5)
Delta time between
reconfig_clks
—
—
—
1
—
1
—
1
ms
(19)
Transceiver block
minimum
power-down
—
—
—
—
—
—
µs
(gxb_powerdown)
pulse width
Receiver
Supported I/O
Standards
1.4 V PCML, 1.5 V PCML, 2.5 V PCML, LVPECL, LVDS
Data rate (Single
width, non-PMA
Direct) (23)
—
—
—
600
1000
600
—
—
—
3750 600
8500 1000
3250 600
—
—
—
3750
600
—
—
—
3750
Mbps
Mbps
Mbps
Data rate (Double
width, non-PMA
Direct) (23)
6375
6500 1000
(22)
Data rate (Single
width, PMA Direct)
3250
600
3250
(23)
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–18
Switching Characteristics
Table 1–23. Transceiver Specifications for Stratix IV GX Devices (Part 3 of 9)
–3 Commercial/
–3 Military (2)
and –4
Commercial/Industrial
Speed Grade
–2 Commercial
Speed Grade
Industrial and
Symbol/
Description
–2× Commercial
Conditions
Unit
(1)
Speed Grade
Min
Typ
Max Min
Typ
Max
Min
Typ
Max
Data rate (Double
width, PMA
—
1000
—
6500 1000
—
6500 1000
—
6375
Mbps
Direct) (23)
Absolute VMAX for a
receiver pin
—
—
—
—
—
—
—
—
1.6
1.5
—
—
—
—
—
—
1.6
1.5
—
—
—
—
—
—
1.6
1.5
—
V
V
V
(6)
Operational VMAX for
a receiver pin
Absolute VMIN for a
receiver pin
-0.4
-0.4
-0.4
Maximum
peak-to-peak
differential input
voltage VID (diff p-p)
before device
configuration
—
—
—
1.6
—
—
1.6
—
—
1.6
V
Maximum peak-to-
peak differential
input voltage VID
(diff p-p) after
VICM = 0.82 V
setting
—
—
—
—
2.7
1.6
—
—
—
—
2.7
1.6
—
—
—
—
2.7
1.6
V
V
V
ICM =1.1 V
(7)
setting
device configuration
Data Rate =
600 Mbps to
5 Gbps
100
165
—
—
—
100
165
—
—
—
—
165
165
—
—
—
—
mV
mV
Equalization = 0
DC gain = 0 dB
Minimum
differential eye
opening at receiver
Data Rate
> 5 Gbps
(20)
serial input pins
—
Equalization = 0
DC gain = 0 dB
V
ICM = 0.82 V
setting
820 10%
820 10%
820 10%
mV
mV
VICM
V
ICM = 1.1 V
1100 10%
1100 10%
1100 10%
(7)
setting
Receiver DC
Coupling Support
For more information about receiver DC coupling support, refer to the “DC-
Coupled Links” section in the Transceiver Architecture in Stratix IV Devices chapter.
—
85 setting
100 setting
120 setting
150- setting
85 20%
100 20%
120 20%
150 20%
85 20%
100 20%
120 20%
150 20%
85 20%
100 20%
120 20%
150 20%
Differential on-chip
termination
resistors
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–19
Switching Characteristics
Table 1–23. Transceiver Specifications for Stratix IV GX Devices (Part 4 of 9)
–3 Commercial/
–3 Military (2)
and –4
Commercial/Industrial
Speed Grade
–2 Commercial
Speed Grade
Industrial and
Symbol/
Description
–2× Commercial
Conditions
Unit
(1)
Speed Grade
Min
Typ
Max Min
Typ
Max
Min
Typ
Max
PCIe (Gen 1
and Gen 2),
XAUI,
HiGig+,
Differential and
common mode
return loss
CEI SR/LR,
Serial RapidIO
SR/LR,
Compliant
—
CPRI LV/HV,
OBSAI,
SATA
62.5, 100, 125, 200,
250, 300, 500, 1000
Programmable PPM
detector
—
ppm
(8)
Run length
—
—
—
—
—
—
200
16
—
—
200
—
—
—
—
200
16
UI
Programmable
equalization
—
—
16
dB
(18)
(9)
tLTR
—
—
—
15
—
—
—
—
75
—
—
15
—
75
—
—
15
—
—
—
—
75
—
µs
µs
(10)
tLTR_LTD_Manual
—
(11)
tLTD_Manual
—
—
4000
—
—
—
4000
—
—
4000
—
ns
(12)
tLTD_Auto
—
4000
4000
—
4000
ns
PCIe Gen1
PCIe Gen2
20 - 35
40 - 65
MHz
MHz
(OIF) CEI PHY
at 6.375 Gbps
20 - 35
10 - 18
10 - 18
MHz
MHz
MHz
XAUI
Serial RapidIO
1.25 Gbps
Receiver CDR
3 dB Bandwidth in
lock-to-data (LTD)
mode
Serial RapidIO
2.5 Gbps
10 - 18
6 - 10
MHz
MHz
Serial RapidIO
3.125 Gbps
GIGE
6 - 10
3 - 6
MHz
MHz
MHz
SONET OC12
SONET OC48
14 - 19
Receiver buffer and
CDR offset
cancellation time
(per channel)
recon
fig_
clk
1850
0
—
—
—
1850
0
—
—
—
—
18500
cycles
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–20
Switching Characteristics
Table 1–23. Transceiver Specifications for Stratix IV GX Devices (Part 5 of 9)
–3 Commercial/
–3 Military (2)
and –4
Commercial/Industrial
Speed Grade
–2 Commercial
Speed Grade
Industrial and
Symbol/
Description
–2× Commercial
Conditions
Unit
(1)
Speed Grade
Min
Typ
Max Min
Typ
Max
Min
Typ
Max
DC Gain Setting
= 0
—
—
—
—
0
—
—
—
—
—
—
—
—
—
—
0
—
—
—
—
—
0
—
dB
dB
dB
dB
DC Gain Setting
= 1
3
6
9
3
6
9
—
—
—
3
6
9
—
—
—
Programmable DC
gain
DC Gain Setting
= 2
DC Gain Setting
= 3
DC Gain Setting
= 4
—
12
—
12
—
—
—
12
—
—
dB
EyeQ Data Rate
AEQ Data Rate
—
600
3250 600
3250
600
3250
Mbps
min VID
(diff p-p)
outer envelope
= 600 mV
8B/10B
encoded data
2500
3125
—
—
6500 2500
—
—
6500
6500
—
—
—
—
—
—
Mbps
Mbps
min VID
(diff p-p)
outer envelope
= 500 mV
Decision Feedback
Equalizer (DFE) Data
Rate
6500 3125
Transmitter
Supported I/O
Standards
1.4 V PCML, 1.5 V PCML
Data rate (Single
width, non-PMA
Direct)
—
600
—
600
—
3750
600
—
3750 Mbps
6375
3750
Data rate (Double
width, non-PMA
Direct)
—
—
—
—
—
—
1000
600
—
—
—
6500 1000
—
—
—
Mbps
(22)
1000
600
8500
3250
Data rate (Single
width, PMA Direct)
3250
600
3250 Mbps
6375 Mbps
Data rate (Double
width, PMA Direct)
1000
—
6500 1000
1000
—
6500
—
(13)
VOCM
0.65 V setting
85 setting
100 setting
120 setting
150- setting
650
650
—
—
650
—
mV
85 15%
100 15%
120 15%
150 15%
85 15%
100 15%
120 15%
150 15%
85 15%
100 15%
120 15%
150 15%
Differential on-chip
termination
resistors
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–21
Switching Characteristics
Table 1–23. Transceiver Specifications for Stratix IV GX Devices (Part 6 of 9)
–3 Commercial/
–3 Military (2)
and –4
Commercial/Industrial
Speed Grade
–2 Commercial
Speed Grade
Industrial and
Symbol/
Description
–2× Commercial
Conditions
Unit
(1)
Speed Grade
Min
Typ
Max Min
Typ
Max
Min
Typ
Max
PCIe Gen1 and
Gen2 (TX
V
OD=4),
XAUI (TX
OD=6),
V
HiGig+
(TX VOD=6),
CEI SR/LR
(TX VOD=8),
Serial RapidIO
SR (VOD=6),
Serial RapidIO
LR (VOD=8),
CPRI LV
Differential and
common mode
return loss
Compliant
—
(VOD=6),
CPRI HV
(VOD=2),
OBSAI (VOD=6),
SATA (VOD=4),
(14)
Rise time
—
—
—
—
50
50
60
60
—
—
—
—
200
200
130
130
50
50
60
60
—
—
—
—
200
200
130
130
50
50
60
60
—
—
—
—
200
200
130
130
ps
ps
ps
ps
(14)
Fall time
XAUI rise time
XAUI fall time
Intra-differential pair
skew
—
—
—
15
—
—
15
—
—
15
ps
×4 PMA and
PCS bonded
mode Example:
XAUI, PCIe ×4,
Basic ×4
Intra-transceiver
block transmitter
channel-to-channel
skew
—
—
120
—
—
120
—
—
120
ps
×8 PMA and
PCS bonded
mode Example:
PCIe ×8,
Inter-transceiver
block transmitter
channel-to-channel
skew
—
—
500
—
—
500
—
—
500
ps
Basic ×8
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–22
Switching Characteristics
Table 1–23. Transceiver Specifications for Stratix IV GX Devices (Part 7 of 9)
–3 Commercial/
–3 Military (2)
and –4
Commercial/Industrial
Speed Grade
–2 Commercial
Speed Grade
Industrial and
Symbol/
Description
–2× Commercial
Conditions
Unit
(1)
Speed Grade
Min
Typ
Max Min
Typ
Max
Min
Typ
Max
N < 18 channels
located across
three
transceiver
blocks with the
source CMU
PLL located in
the center
—
—
400
—
—
400
—
—
400
ps
transceiver
block
Inter-transceiver
block skew in Basic
(PMA Direct) ×N
N 18 channels
located across
four transceiver
blocks with the
source CMU
PLL located in
one of the two
center
(15)
mode
—
—
650
—
—
—
650
—
—
650
ps
transceiver
blocks
CMU0 PLL and CMU1 PLL
Supported Data
Range
—
—
600
—
—
8500 600
6500
100
600
—
—
6375
100
Mbps
pll_powerdown
minimum pulse
width
1
s
(tpll_powerdown)
CMU PLL lock time
from
pll_powerdown
—
—
100
—
—
—
s
de-assertion
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–23
Switching Characteristics
Table 1–23. Transceiver Specifications for Stratix IV GX Devices (Part 8 of 9)
–3 Commercial/
–3 Military (2)
and –4
Commercial/Industrial
Speed Grade
–2 Commercial
Speed Grade
Industrial and
Symbol/
Description
–2× Commercial
Conditions
Unit
(1)
Speed Grade
Min
Typ
Max Min
Typ
Max
Min
Typ
Max
PCIe Gen1
PCIe Gen2
2.5 - 3.5
6 - 8
MHz
MHz
(OIF) CEI PHY
at 4.976 Gbps
7 - 11
MHz
(OIF) CEI PHY
at 6.375 Gbps
5 - 10
2 - 4
MHz
MHz
MHz
XAUI
Serial RapidIO
1.25 Gbps
-3 dB Bandwidth
3 - 5.5
Serial RapidIO
2.5 Gbps
3 - 5.5
2 - 4
MHz
MHz
Serial RapidIO
3.125 Gbps
GIGE
2.5 - 4.5
1.5 - 2.5
3.5 - 6
MHz
MHz
MHz
SONET OC12
SONET OC48
ATX PLL (6G)
4800-5400 and
6000-6500
4800-5400 and
6000-6500
4800-5400 and
6000-6375
/L = 1
/L = 2
Mbps
Mbps
Supported Data
2400-2700 and
3000-3250
2400-2700 and
3000-3250
2400-2700 and
3000-3187.5
(16)
Range
1200-1350 and
1500-1625
1200-1350 and
1500-1625
1200-1350 and
1500-1593.75
/L = 4
Mbps
MHz
MHz
PCIe Gen 2
1.5
1.5
—
-3 dB Bandwidth
(OIF) CEI PHY
at 6.375 Gbps
3 - 4.5
3 - 4.5
—
Transceiver-FPGA Fabric Interface
Interface speed
—
25
—
—
325
25
50
—
—
325
25
50
—
—
250
MHz
MHz
(non-PMA Direct)
Interface speed
—
50
325
325
325
(PMA Direct)
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–24
Switching Characteristics
Table 1–23. Transceiver Specifications for Stratix IV GX Devices (Part 9 of 9)
–3 Commercial/
–3 Military (2)
and –4
Commercial/Industrial
Speed Grade
–2 Commercial
Speed Grade
Industrial and
Symbol/
Description
–2× Commercial
Conditions
Unit
(1)
Speed Grade
Min
Typ
Max Min
Typ
Max
Min
Typ
Max
Digital reset pulse
width
—
Minimum is two parallel clock cycles
—
Notes to Table 1–23:
(1) The –2× speed grade is the fastest speed grade offered in the following Stratix IV GX devices: EP4SGX70DF29, EP4SGX110DF29,
EP4SGX110FF35, EP4SGX230DF29, EP4SGX110FF35, EP4SGX180DF29, EP4SGX230FF35, EP4SGX290FF35, EP4SGX180FF35,
EP4SGX290FH29, EP4SGX360FF35, and EPSGX360FH29.
(2) Stratix IV GX devices in military speed grade only support selected transceiver configuration up to 3125 Mbps. For more information, contact
Altera sales representative.
(3) To calculate the REFCLK rms phase jitter requirement at reference clock frequencies other than 100 MHz, use the following formula: REFCLK
rms phase jitter at f (MHz) = REFCLK rms phase jitter at 100 MHz * 100/f.
(4) Differential LVPECL signal levels must comply to the minimum and maximum peak-to-peak differential input voltage specified in this table.
(5) The minimum reconfig_clkfrequency is 2.5 MHz if the transceiver channel is configured in Transmitter only mode. The minimum
reconfig_clkfrequency is 37.5 MHz if the transceiver channel is configured in Receiver only or Receiver and Transmitter mode. For more
information, refer to the Dynamic Reconfiguration in Stratix IV Devices chapter.
(6) The device cannot tolerate prolonged operation at this absolute maximum.
(7) You must use the 1.1-V RX VICM setting if the input serial data standard is LVDS.
(8) The rate matcher supports only up to 300 parts per million (ppm).
(9) Time taken to rx_pll_lockedgoes high from rx_analogresetde-assertion. Refer to Figure 1–2 on page 1–33.
(10) Time for which the CDR must be kept in lock-to-reference (LTR) mode after rx_pll_lockedgoes high and before rx_locktodatais asserted
in manual mode. Refer to Figure 1–2 on page 1–33.
(11) Time taken to recover valid data after the rx_locktodatasignal is asserted in manual mode. Refer to Figure 1–2 on page 1–33.
(12) Time taken to recover valid data after the rx_freqlockedsignal goes high in automatic mode. Refer to Figure 1–3 on page 1–33.
(13) A GPLL may be required to meet the PMA-FPGA fabric interface timing above certain data rates. For more information, refer to the “Left/Right
PLL Requirements in Basic (PMA Direct) Mode” section in the Transceiver Clocking in Stratix IV Devices chapter.
(14) The Quartus II software automatically selects the appropriate slew rate depending on the configured data rate or functional mode.
(15) For applications that require low transmit lane-to-lane skew, use Basic (PMA Direct) xN to achieve PMA-Only bonding across all channels in the
link. You can bond all channels on one side of the device by configuring them in Basic (PMA Direct) xN mode. For more information about
clocking requirements in this mode, refer to the “Basic (PMA Direct) Mode Clocking” section in the Transceiver Clocking in Stratix IV Devices
chapter.
(16) The Quartus II software automatically selects the appropriate /L divider depending on the configured data.
(17) The maximum transceiver-FPGA fabric interface speed of 265.625 MHz is allowed only in Basic low-latency PCS mode with a 32-bit interface
width. For more information, refer to the “Basic Double-Width Mode Configurations” section in the Transceiver Architecture in Stratix IV Devices
chapter.
(18) Figure 1–1 shows the AC gain curves for each of the 16 available equalization settings.
(19) If your design uses more than one dynamic reconfiguration controller (altgx_reconfig) instances to control the transceiver (altgx) channels
physically located on the same side of the device AND if you use different reconfig_clksources for these altgx_reconfiginstances, the
delta time between any two of these reconfig_clksources becoming stable must not exceed the maximum specification listed.
(20) The differential eye opening specification at the receiver input pins assumes that Receiver Equalization is disabled. If you enable Receiver
Equalization, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level. Use H-Spice simulation to
derive the minimum eye opening requirement with Receiver Equalization enabled.
(21) The rise and fall time transition is specified from 20% to 80%.
(22) Stratix IV GX devices in -4 speed grade support Basic mode and deterministic latency mode transceiver configurations up to 6375 Mbps. These
configurations are shown in the figures 1-90, 1-92, 1-94, 1-96, and 1-101 in the Transceiver Architecture in Stratix IV Devices chapter.
(23) To support data rates lower than 600-Mbps specification through oversampling, use the CDR in LTR mode only.
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–25
Switching Characteristics
Figure 1–1 shows the top-to-bottom AC gain curve for equalization settings 0 to 15.
Figure 1–1. AC Gain Curves for Equalization Settings 0 to 15 (Bottom to Top)
Table 1–24 lists the Stratix IV GT transceiver specifications.
Table 1–24. Transceiver Specifications for Stratix IV GT Devices (Part 1 of 8)
–1 Industrial Speed
Grade
–2 Industrial Speed
Grade
–3 Industrial Speed
Grade
Symbol/
Description
Conditions
Unit
Min
Typ
Max
Min Typ
Max
Min Typ
Max
Reference Clock
Supported I/O
Standards
1.2 V PCML, 1.4 V PCML, 1.5 V PCML, 2.5 V PCML, Differential LVPECL (3), LVDS
Input frequency
from REFCLKinput
pins
—
—
50
50
—
—
706.25 50
—
—
706.25
425
50
50
—
—
706.25
425
MHz
MHz
Phase frequency
detector (CMU PLL
and receiver CDR)
425
50
Absolute VMAX for a
REFCLKpin
—
—
—
—
—
—
—
—
1.6
1.5
—
—
—
—
—
—
1.6
1.5
—
—
—
—
—
—
1.6
1.5
—
V
V
V
Operational VMAX for
a
REFCLKpin
Absolute VMIN for a
REFCLKpin
-0.3
-0.3
-0.3
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–26
Switching Characteristics
Table 1–24. Transceiver Specifications for Stratix IV GT Devices (Part 2 of 8)
–1 Industrial Speed
Grade
–2 Industrial Speed
Grade
–3 Industrial Speed
Grade
Symbol/
Conditions
Unit
Description
Min
—
Typ
—
Max
0.2
55
Min Typ
Max
0.2
55
Min Typ
Max
0.2
55
Rise/fall time
—
—
—
45
—
—
—
45
—
—
UI
%
Duty cycle
45
—
Peak-to-peak
differential input
voltage
—
200
—
1200
200
—
—
1200
200
—
—
1200
mV
On-chip termination
resistors
—
—
100
—
100
—
100
—
VICM
—
1200 10%
1200 10%
1200 10%
mV
10 Hz
—
—
—
—
—
—
—
—
-50
-80
—
—
—
—
—
—
—
—
—
—
—
—
-50
—
—
—
—
—
—
—
—
—
—
—
—
-50
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
100 Hz
1 KHz
-80
-80
—
—
—
—
-110
-120
-120
-130
-110
-120
-120
-130
-110
-120
-120
-130
Transmitter REFCLK
Phase Noise
10 KHz
100 KHz
1 MHz
Transmitter REFCLK
Phase Jitter (rms)
for 100 MHz
10 KHz to
20 MHz
—
—
—
—
3
—
—
—
3
—
—
—
3
ps
REFCLK (2)
2000
1%
2000
1%
2000
1%
RREF
—
—
—
Transceiver Clocks
Calibration block
clock frequency
—
10
—
—
125
—
—
2
10
—
—
125
50
—
2
10
—
—
125
50
—
2
MHz
MHz
MHz
ms
Dynamic
reconfiguration
clock frequency
2.5/
2.5/
2.5/
reconfig_clk
clock frequency
37.5
37.5
37.5
(1)
(1)
(1)
fixedclkclock
frequency
PCIe Receiver
Detect
—
—
125
—
—
—
125
—
—
—
125
—
Delta time between
reconfig_clks
—
(15)
Transceiver block
minimum
(gxb_powerdown
)
—
—
1
—
—
1
—
—
1
—
µs
power-down pulse
width
Receiver
Supported I/O
Standards
1.4 V PCML, 1.5 V PCML, 2.5 V PCML, LVPECL, LVDS
Data rate (Single
width,
—
600
—
3750
600
—
3750
600
—
3750
Mbps
non-PMA Direct) (16)
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–27
Switching Characteristics
Table 1–24. Transceiver Specifications for Stratix IV GT Devices (Part 3 of 8)
–1 Industrial Speed
Grade
–2 Industrial Speed
Grade
–3 Industrial Speed
Grade
Symbol/
Description
Conditions
Unit
Min
Typ
Max
Min Typ
Max
Min Typ
Max
Data rate (Double
width,
—
—
—
1000
—
11300 1000
-
-
-
10312.5 1000
—
—
—
8500
Mbps
Mbps
Mbps
non-PMA Direct) (16)
Data rate (Single
width,
600
-
-
3250
600
3250
6500
600
3250
6500
(16)
PMA Direct)
Data rate (Double
width,
1000
6500 1000
1000
PMA Direct) (16)
Absolute VMAX for a
receiver pin
—
—
—
—
—
—
—
—
1.6
1.5
—
—
—
—
—
—
1.6
1.5
—
—
—
—
—
—
1.6
1.5
—
V
V
V
(4)
Operational VMAX for
a receiver pin
Absolute VMIN for a
receiver pin
-0.4
-0.4
-0.4
Maximum
peak-to-peak
differential input
voltage VID (diff p-p)
before device
configuration
—
—
—
1.6
—
—
1.6
—
—
1.6
V
Maximum
VICM = 0.82 V
setting
—
—
—
—
2.7
1.2
—
—
—
—
2.7
1.2
—
—
—
—
2.7
1.2
V
V
peak-to-peak
differential input
voltage VID (diff p-p)
after device
V
ICM = 1.2 V
(5)
setting
configuration
Minimum
differential eye
opening at the
receiver serial input
pins for data rates
10.3125 Gbps.
Equalization = 0
(6)
85
—
—
—
85
—
—
—
—
—
85
—
—
—
—
—
mV
mV
DC gain = 0 dB
Minimum
differential eye
opening at the
receiver serial input
pins for data rates
> 10.3125 Gbps.
Equalization = 0
(6)
165
—
DC gain = 0 dB
V
ICM = 0.82 V
setting
820 10%
820 10%
820 10%
mV
mV
VICM
VICM = 1.2 V
1200 10%
1200 10%
1200 10%
(5)
setting
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–28
Switching Characteristics
Table 1–24. Transceiver Specifications for Stratix IV GT Devices (Part 4 of 8)
–1 Industrial Speed
Grade
–2 Industrial Speed
Grade
–3 Industrial Speed
Grade
Symbol/
Conditions
Unit
Description
Min
Typ
Max
Min Typ
85 20%
Max
Min Typ
85 20%
Max
85 setting
100 setting
120 setting
150- setting
85 20%
100 20%
120 20%
150 20%
Differential on-chip
termination
resistors
100 20%
120 20%
150 20%
100 20%
120 20%
150 20%
PCIe (Gen 1
and Gen 2),
XAUI,
HiGig+,
Differential and
common mode
return loss
CEI SR/LR,
Serial RapidIO
SR/LR,
Compliant
—
CPRI LV/HV,
OBSAI,
SATA
62.5, 100, 125, 200,
250, 300, 500, 1000
Programmable PPM
detector
—
—
ppm
(7)
Run length
—
—
—
—
—
—
200
16
—
—
—
200
—
—
—
200
16
UI
Programmable
equalization
—
16
—
dB
(8)
tLTR
—
—
—
—
—
15
—
—
—
—
75
—
—
15
—
—
—
—
75
—
—
15
—
—
75
—
µs
µs
ns
ns
(9)
tLTR_LTD_Manual
(10)
tLTD_Manual
—
4000
—
—
4000
—
—
—
—
4000
—
(11)
tLTD_Auto
4000
4000
4000
Receiver buffer and
CDR offset
cancellation time
(per channel)
reconfig_clk
—
—
—
17000
—
—
17000
—
—
17000
cycles
DC Gain Setting
= 0
—
—
—
—
0
3
6
9
—
—
—
—
—
—
—
—
0
3
6
9
—
—
—
—
—
—
—
—
0
3
6
9
—
—
—
—
dB
dB
dB
dB
DC Gain Setting
= 1
Programmable DC
gain
DC Gain Setting
= 2
DC Gain Setting
= 3
DC Gain Setting
= 4
—
—
12
—
—
—
—
12
—
—
—
—
12
—
—
dB
EyeQ Max Data Rate
—
4.0
4.0
4.0
Gbps
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–29
Switching Characteristics
Table 1–24. Transceiver Specifications for Stratix IV GT Devices (Part 5 of 8)
–1 Industrial Speed
Grade
–2 Industrial Speed
Grade
–3 Industrial Speed
Grade
Symbol/
Description
Conditions
Unit
Min
Typ
Max
Min Typ
Max
Min Typ
Max
min VID
(diff p-p)
outer envelope
= 600 mV
8B/10B
encoded data
AEQ Data Rate
2500
—
6500 2500
—
—
6500
—
—
—
—
—
Mbps
Mbps
min VID
(diff p-p)
outer envelope
= 600 mV
Decision Feedback
Equalizer (DFE) Data
Rate
3125
—
6500 3125
6500
3750
—
Transmitter
Supported I/O
Standards
1.4 V PCML
Data rate (Single
width,
non-PMA Direct)
—
—
—
—
600
1000
600
—
—
—
—
3750
600
—
—
—
—
600
—
—
—
—
3750
8500
3250
Mbps
Mbps
Mbps
Mbps
Data rate (Double
width,
non-PMA Direct)
11300 1000
10312.5 1000
Data rate (Single
width,
PMA Direct)
3250
600
3250
600
Data rate (Double
width,
1000
—
6500 1000
6500
—
1000
—
6500
—
(12)
PMA Direct)
VOCM
0.65 V setting
85 setting
100 setting
120 setting
150- setting
650
—
—
650
650
mV
85 15%
100 15%
120 15%
150 15%
85 15%
85 15%
Differential on-chip
termination
resistors
100 15%
120 15%
150 15%
100 15%
120 15%
150 15%
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–30
Switching Characteristics
Table 1–24. Transceiver Specifications for Stratix IV GT Devices (Part 6 of 8)
–1 Industrial Speed
Grade
–2 Industrial Speed
Grade
–3 Industrial Speed
Grade
Symbol/
Description
Conditions
Unit
Min
Typ
Max
Min Typ
Max
Min Typ
Max
PCIe Gen1 and
Gen2 (TX
V
OD=4),
XAUI
(TX VOD=6),
HiGig+
(TX VOD=6),
CEI SR/LR
(TX VOD=8),
Serial RapidIO
SR (VOD=6),
Serial RapidIO
LR (VOD=8),
CPRI LV
Differential and
common mode
return loss
Compliant
—
(VOD=6),
CPRI HV
(VOD=2),
OBSAI (VOD=6),
SATA (VOD=4),
(13)
Rise time
—
—
—
—
50
50
60
60
—
—
—
—
200
200
130
130
50
50
60
60
—
—
—
—
200
200
130
130
50
50
60
60
—
—
—
—
200
200
130
130
ps
ps
ps
ps
(13)
Fall time
XAUI rise time
XAUI fall time
Intra-differential
pair skew
—
—
—
15
—
—
15
—
—
15
ps
×4 PMA and
PCS bonded
mode Example:
XAUI, PCIe, ×4,
Basic ×4
Intra-transceiver
block transmitter
channel-to-channel
skew
—
—
120
—
—
120
—
—
120
ps
×8 PMA and
PCS bonded
mode Example:
PCIe ×8,
Inter-transceiver
block transmitter
channel-to-channel
skew
—
—
500
—
—
500
—
—
500
ps
Basic ×8
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–31
Switching Characteristics
Table 1–24. Transceiver Specifications for Stratix IV GT Devices (Part 7 of 8)
–1 Industrial Speed
Grade
–2 Industrial Speed
Grade
–3 Industrial Speed
Grade
Symbol/
Description
Conditions
Unit
Min
Typ
Max
Min Typ
Max
Min Typ
Max
N < 18 channels
located across
three
transceiver
blocks with the
source CMU
PLL located in
the center
—
—
400
—
—
400
—
—
400
ps
transceiver
block
Inter-transceiver
block skew in Basic
(PMA Direct) ×N
N 18
channels
(14)
mode
located across
four transceiver
blocks with the
source CMU
PLL located in
one of the two
center
—
—
650
—
—
650
—
—
650
ps
transceiver
blocks
CMU PLL0 and CMU PLL1
Supported data
range
—
—
600
—
—
—
11300 600
—
—
10312.5 600
—
—
8500
100
Mbps
CMU PLL lock time
from
pll_powerdown
100
—
100
—
s
de-assertion
ATX PLL (6G)
4800-5400 and
6000-6500
4800-5400 and
6000-6500
4800-5400 and
6000-6500
/L = 1
/L = 2
/L = 4
Mbps
Mbps
Mbps
Supported Data
Range
2400-2700 and
3000-3250
2400-2700 and
3000-3250
2400-2700 and
3000-3250
1200-1350 and
1500-1625
1200-1350 and
1500-1625
1200-1350 and
1500-1625
ATX PLL (10G)
Supported Data
Range
—
9900
—
11300 9900
—
10312.5
—
Mbps
Transceiver-FPGA Fabric Interface
Interface speed
—
25
50
—
—
325
325
25
50
—
—
325
325
25
50
—
—
265.625
MHz
MHz
(non-PMA Direct)
Interface speed
—
325
(PMA Direct)
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–32
Switching Characteristics
Table 1–24. Transceiver Specifications for Stratix IV GT Devices (Part 8 of 8)
–1 Industrial Speed
Grade
–2 Industrial Speed
Grade
–3 Industrial Speed
Grade
Symbol/
Description
Conditions
Unit
Min
Typ
Max
Min Typ
Max
Min Typ
Max
Digital reset pulse
width
—
Minimum is two parallel clock cycles
—
Notes to Table 1–24:
(1) The minimum reconfig_clkfrequency is 2.5 MHz if the transceiver channel is configured in Transmitter Only mode. The minimum reconfig_clk
frequency is 37.5 MHz if the transceiver channel is configured in Receiver only or Receiver and Transmitter mode. For more information, refer to the
Dynamic Reconfiguration in Stratix IV Devices chapter.
(2) To calculate the REFCLK rms phase jitter requirement at reference clock frequencies other than 100 MHz, use the following formula: REFCLK rms phase
jitter at f (MHz) = REFCLK rms phase jitter at 100 MHz * 100/f.
(3) Differential LVPECL signal levels must comply to the minimum and maximum peak-to-peak differential input voltage specified in this table.
(4) The device cannot tolerate prolonged operation at this absolute maximum.
(5) You must use the 1.2-V RXVICM setting if the input serial data standard is LVDS.
(6) The differential eye opening specification at the receiver input pins assumes that Receiver Equalization is disabled. If you enable Receiver
Equalization, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level. Use H-Spice simulation to derive
the minimum eye opening requirement with Receiver Equalization enabled.
(7) The rate matcher supports only up to 300 ppm.
(8) Time taken to rx_pll_lockedgoes high from rx_analogresetde-assertion. Refer to Figure 1–2 on page 1–33.
(9) Time for which the CDR must be kept in lock-to-reference mode after rx_pll_lockedgoes high and before rx_locktodatais asserted in manual
mode. Refer to Figure 1–2 on page 1–33.
(10) Time taken to recover valid data after the rx_locktodatasignal is asserted in manual mode. Refer to Figure 1–2 on page 1–33.
(11) Time taken to recover valid data after the rx_freqlockedsignal goes high in automatic mode. Refer to Figure 1–3 on page 1–33.
(12) A GPLL may be required to meet the PMA-FPGA fabric interface timing above certain data rates. For more information, refer to the “Left/Right PLL
Requirements in Basic (PMA Direct) Mode” section in the Transceiver Clocking in Stratix IV Devices chapter.
(13) The Quartus II software automatically selects the appropriate slew rate depending on the configured data rate or functional mode.
(14) For applications that require low transmit lane-to-lane skew, use Basic (PMA Direct) xN to achieve PMA-Only bonding across all channels in the link.
You can bond all channels on one side of the device by configuring them in Basic (PMA Direct) xN mode. For more information about clocking
requirements in this mode, refer to the “Basic (PMA Direct) Mode Clocking” section in the Transceiver Clocking in Stratix IV Devices chapter.
(15) If your design uses more than one dynamic reconfiguration controller (altgx_reconfig) instances to control the transceiver (altgx) channels
physically located on the same side of the device AND if you use different reconfig_clksources for these altgx_reconfiginstances, the delta
time between any two of these reconfig_clksources becoming stable must not exceed the maximum specification listed.
(16) To support data rates lower than 600-Mbps specification through oversampling, use the CDR in LTR mode only.
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–33
Switching Characteristics
Figure 1–2 shows the lock time parameters in manual mode.
LTD = Lock-To-Data; LTR = Lock-To-Reference
1
Figure 1–2. Lock Time Parameters for Manual Mode
r x_analogreset
CDR status
LTR
LTD
r x_pl
l_lock
ed
r x_locktodata
r x_dataout
Invalid Data
Valid data
t
t
LTR
LTD_Manual
t
LTR_LTD_Manual
Figure 1–3 shows the lock time parameters in automatic mode.
Figure 1–3. Lock Time Parameters for Automatic Mode
LTR
LTD
CDR status
r x_freqlocked
r x_dataout
Valid
data
Invalid
data
t
LTD_Auto
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–34
Switching Characteristics
Table 1–25 through Table 1–28 lists the typical differential VOD termination settings for
Stratix IV GX and GT devices.
Table 1–25. Typical VOD Setting, TX Term = 85
V
OD Setting (mV)
Symbol
OD differential
0
1
2
3
4
5
6
7
V
170
340
510
595
680
765
20%
850
20%
1020
20%
peak-to-peak Typical (mV) 20%
20%
20%
20%
20%
Table 1–26. Typical VOD Setting, TX Term = 100
V
OD Setting (mV)
Symbol
0
1
2
3
4
5
6
7
V
OD differential
200
400
20%
600
20%
700
20%
800
20%
900
20%
1000
20%
1200
20%
peak-to-peak Typical (mV) 20%
Table 1–27. Typical VOD Setting, TX Term = 120
VOD Setting (mV)
3
Symbol
0
1
2
4
5
6
V
OD differential
240
20%
480
20%
720
20%
840
20%
960
20%
1080
20%
1200
20%
peak-to-peak Typical (mV)
Table 1–28. Typical VOD Setting, TX Term = 150
VOD Setting (mV)
Symbol
0
1
2
3
4
5
V
OD differential
300
20%
600
20%
900
20%
1050
20%
1200
20%
1350
20%
peak-to-peak Typical (mV)
Table 1–29 lists typical transmitter pre-emphasis levels in dB for the first post tap
under the following conditions (low-frequency data pattern [five 1s and five 0s] at
6.25 Gbps). The levels listed in Table 1–29 are a representation of possible
pre-emphasis levels under the specified conditions only and that the pre-emphasis
levels may change with data pattern and data rate.
f
To predict the pre-emphasis level for your specific data rate and pattern, run
simulations using the Stratix IV HSSI HSPICE models.
Table 1–29. Transmitter Pre-Emphasis Levels for Stratix IV Devices (Part 1 of 2)
VOD Setting
Pre-Emphasis1st
Post-Tap Setting
0
1
0
2
0
3
0
0
0
0
4
0
0
0
0
5
0
0
0
0
6
0
0
0
0
7
0
0
0
0
0
1
2
3
0
N/A
N/A
N/A
0.7
1
0
0.3
0.6
1.5
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–35
Switching Characteristics
Table 1–29. Transmitter Pre-Emphasis Levels for Stratix IV Devices (Part 2 of 2)
V
OD Setting
Pre-Emphasis1st
Post-Tap Setting
0
1
2
0.7
1.2
1.3
1.8
2.1
2.4
2.8
3.2
3.5
3.8
4.2
4.5
4.9
5.3
5.7
6.1
6.6
7
3
4
5
6
7
0
4
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
2
0.3
0.5
0.8
1.1
1.3
1.6
1.9
2.2
2.6
2.8
3.1
3.4
3.7
4
0
0
0
5
2.7
3.1
3.7
4.2
4.9
5.4
6
0.3
0.5
0.7
0.9
1.2
1.4
1.7
1.9
2.1
2.3
2.6
2.9
3.1
3.4
3.6
4
0
0
0
6
0.2
0.4
0.6
0.8
1
0
0
7
0.2
0.3
0.5
0.7
0.9
1.1
1.2
1.3
1.5
1.7
1.8
2
0
8
0
9
0.2
0.3
0.4
0.6
0.6
0.7
0.8
0.9
1.1
1.2
1.4
1.5
1.7
2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
1.2
1.4
1.6
1.7
1.9
2.2
2.4
2.6
2.8
3.1
3.3
3.8
4.3
4.8
5.4
5.9
6.4
7.1
7.7
9
6.8
7.5
8.1
8.8
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
4.4
4.7
5.1
5.4
6.1
6.8
7.6
8.4
9.4
10.3
11.3
12.5
N/A
N/A
2.2
2.4
2.7
3
4.3
4.8
5.4
6
8
9
3.4
3.9
4.4
4.9
5.3
5.8
6.3
7.4
8.2
2.3
2.6
3
10
11.4
12.6
N/A
N/A
N/A
N/A
N/A
6.8
7.4
8.1
8.8
9.6
11.4
12.9
3.3
3.6
4
4.3
N/A
N/A
10
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–36
Switching Characteristics
Table 1–30 lists the Stratix IV GX transceiver jitter specifications for all supported
protocols. For protocols supported by Stratix IV GT industrial speed grade devices,
refer to the Stratix IV GX –2 commercial speed grade column in Table 1–30.
(2)
Table 1–30. Transceiver Block Jitter Specifications for Stratix IV GX Devices (1)
,
(Part 1 of 9)
–3 Commercial/
Industrial
–3 Military (3) and
–4 Commercial/
–2 Commercial
Speed Grade
Symbol/
Description
and –2× Commercial Industrial Speed
Conditions
Unit
Speed Grade
Grade
Min Typ Max Min Typ
Max Min Typ Max
(4)
SONET/SDH Transmit Jitter Generation
Peak-to-peak jitter at
622.08 Mbps
Pattern = PRBS15
—
—
—
—
—
—
—
—
0.1
0.01
0.1
—
—
—
—
—
—
—
—
0.1
0.01
0.1
—
—
—
—
—
—
—
—
0.1
0.01
0.1
UI
UI
UI
UI
RMS jitter at
622.08 Mbps
Pattern = PRBS15
Pattern = PRBS15
Peak-to-peak jitter at
2488.32 Mbps
RMS jitter at
2488.32 Mbps
Pattern = PRBS15
0.01
0.01
0.01
(4)
SONET/SDH Receiver Jitter Tolerance
Jitter frequency =
0.03 KHz
> 15
> 1.5
> 0.15
> 15
> 15
> 1.5
> 0.15
> 15
> 15
> 1.5
> 0.15
> 15
UI
UI
UI
UI
Pattern = PRBS15
Jitter frequency =
25 KHZ
Jitter tolerance at
622.08 Mbps
Pattern = PRBS15
Jitter frequency =
250 KHz
Pattern = PRBS15
Jitter frequency =
0.06 KHz
Pattern = PRBS15
Jitter frequency =
100 KHZ
> 1.5
> 0.15
> 0.15
> 1.5
> 0.15
> 0.15
> 1.5
> 0.15
> 0.15
UI
UI
UI
Jitter tolerance at
2488.32 Mbps
Pattern = PRBS15
Jitter frequency = 1 MHz
Pattern = PRBS15
Jitter frequency =
10 MHz
Pattern = PRBS15
(5) (13)
Fibre Channel Transmit Jitter Generation
Total jitter FC-1 Pattern = CRPAT
Deterministic jitter FC-1 Pattern = CRPAT
Total jitter FC-2 Pattern = CRPAT
,
—
—
—
—
—
—
—
—
0.23
0.11
0.33
0.2
—
—
—
—
—
—
—
—
0.23
0.11
0.33
0.2
—
—
—
—
—
—
—
—
0.23
0.11
0.33
0.2
UI
UI
UI
UI
Deterministic jitter FC-2 Pattern = CRPAT
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–37
Switching Characteristics
(2)
Table 1–30. Transceiver Block Jitter Specifications for Stratix IV GX Devices (1)
,
(Part 2 of 9)
–3 Commercial/
Industrial
–3 Military (3) and
–4 Commercial/
–2 Commercial
Speed Grade
Symbol/
Description
and –2× Commercial Industrial Speed
Conditions
Unit
Speed Grade
Grade
Min Typ Max Min Typ
Max Min Typ Max
Total jitter FC-4
Pattern = CRPAT
—
—
—
—
0.52
0.33
—
—
—
—
0.52
0.33
—
—
—
—
0.52
0.33
UI
UI
Deterministic jitter FC-4 Pattern = CRPAT
(5) (14)
Fibre Channel Receiver Jitter Tolerance
,
Deterministic jitter FC-1 Pattern = CJTPAT
> 0.37
> 0.31
> 1.5
> 0.37
> 0.31
> 1.5
> 0.37
> 0.31
> 1.5
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
Random jitter FC-1
Pattern = CJTPAT
Fc/25000
Sinusoidal jitter FC-1
Fc/1667
> 0.1
> 0.1
> 0.1
Deterministic jitter FC-2 Pattern = CJTPAT
> 0.33
> 0.29
> 1.5
> 0.33
> 0.29
> 1.5
> 0.33
> 0.29
> 1.5
Random jitter FC-2
Pattern = CJTPAT
Fc/25000
Sinusoidal jitter FC-2
Fc/1667
> 0.1
> 0.1
> 0.1
Deterministic jitter FC-4 Pattern = CJTPAT
> 0.33
> 0.29
> 1.5
> 0.33
> 0.29
> 1.5
> 0.33
> 0.29
> 1.5
Random jitter FC-4
Pattern = CJTPAT
Fc/25000
Fc/1667
Sinusoidal jitter FC-4
> 0.1
> 0.1
> 0.1
(6)
XAUI Transmit Jitter Generation
Total jitter at 3.125 Gbps Pattern = CJPAT
—
—
—
—
0.3
—
—
—
—
0.3
—
—
—
—
0.3
UI
UI
Deterministic jitter at
Pattern = CJPAT
3.125 Gbps
0.17
0.17
0.17
(6)
XAUI Receiver Jitter Tolerance
Total jitter
—
—
> 0.65
> 0.37
> 0.65
> 0.37
> 0.65
> 0.37
UI
UI
Deterministic jitter
Jitter frequency =
22.1 KHz
Peak-to-peak jitter
Peak-to-peak jitter
Peak-to-peak jitter
> 8.5
> 0.1
> 0.1
> 8.5
> 0.1
> 0.1
> 8.5
> 0.1
> 0.1
UI
UI
UI
Jitter frequency =
1.875 MHz
Jitter frequency =
20 MHz
(7)
PCIe Transmit Jitter Generation
Total jitter at 2.5 Gbps
(Gen1)
Compliance pattern
—
—
—
—
0.25
0.25
—
—
—
—
0.25
0.25
—
—
—
—
0.25
—
UI
UI
Total jitter at 5 Gbps
(Gen2) (15)
Compliance pattern
(7)
PCIe Receiver Jitter Tolerance
Total jitter at 2.5 Gbps
(Gen1)
Compliance pattern
> 0.6
> 0.6
> 0.6
UI
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–38
Switching Characteristics
(2)
Table 1–30. Transceiver Block Jitter Specifications for Stratix IV GX Devices (1)
,
(Part 3 of 9)
–3 Commercial/
Industrial
–3 Military (3) and
–4 Commercial/
–2 Commercial
Speed Grade
Symbol/
Description
and –2× Commercial Industrial Speed
Conditions
Unit
Speed Grade
Grade
Min Typ Max Min Typ
Compliant Compliant
Max Min Typ Max
Total jitter at 5 Gbps
(Gen2)
Compliance pattern
—
UI
UI
PCIe (Gen 1) Electrical Idle Detect Threshold
(16)
VRX-IDLE-DETDIFFp-p
Compliance pattern
65
—
175
65
—
175
65
—
175
(8)
Serial RapidIO Transmit Jitter Generation
Data Rate = 1.25, 2.5,
3.125 Gbps
Deterministic jitter
(peak-to-peak)
—
—
—
—
0.17
0.35
—
—
—
—
0.17
0.35
—
—
—
—
0.17
0.35
UI
UI
Pattern = CJPAT
Data Rate = 1.25, 2.5,
3.125 Gbps
Total jitter
(peak-to-peak)
Pattern = CJPAT
(8)
Serial RapidIO Receiver Jitter Tolerance
Data Rate = 1.25, 2.5,
3.125 Gbps
Deterministic jitter
tolerance (peak-to-peak)
> 0.37
> 0.55
> 0.37
> 0.55
> 0.37
> 0.55
UI
UI
Pattern = CJPAT
Data Rate = 1.25, 2.5,
3.125 Gbps
Combined deterministic
and random jitter
tolerance (peak-to-peak)
Pattern = CJPAT
Jitter Frequency = 22.1
KHz Data Rate = 1.25,
2.5, 3.125 Gbps
> 8.5
> 0.1
> 8.5
> 0.1
> 8.5
> 0.1
UI
UI
Pattern = CJPAT
Jitter Frequency = 1.875
MHz
Data Rate = 1.25, 2.5,
3.125 Gbps
Sinusoidal jitter
tolerance (peak-to-peak)
Pattern = CJPAT
Jitter Frequency =
20 MHz
Data Rate = 1.25, 2.5,
3.125 Gbps
> 0.1
> 0.1
> 0.1
UI
Pattern = CJPAT
(9)
GIGE Transmit Jitter Generation
Deterministic jitter
(peak-to-peak)
Pattern = CRPAT
Pattern = CRPAT
—
—
—
—
0.14
—
—
—
—
0.14
—
—
—
—
0.14
UI
UI
Total jitter
(peak-to-peak)
0.279
0.279
0.279
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–39
Switching Characteristics
(2)
Table 1–30. Transceiver Block Jitter Specifications for Stratix IV GX Devices (1)
,
(Part 4 of 9)
–3 Commercial/
Industrial
–3 Military (3) and
–4 Commercial/
–2 Commercial
Speed Grade
Symbol/
Description
and –2× Commercial Industrial Speed
Conditions
Unit
Speed Grade
Grade
Min Typ Max Min Typ
Max Min Typ Max
(9)
GIGE Receiver Jitter Tolerance
Deterministic jitter
tolerance (peak-to-peak)
Pattern = CJPAT
> 0.4
> 0.4
> 0.4
UI
UI
Combined deterministic
and random jitter
Pattern = CJPAT
> 0.66
> 0.66
> 0.66
tolerance (peak-to-peak)
(10)
HiGig Transmit Jitter Generation
Data Rate = 3.75 Gbps
Deterministic jitter
(peak-to-peak)
—
—
—
—
0.17
0.35
—
—
—
—
—
—
—
—
—
—
—
—
UI
UI
Pattern = CJPAT
Data Rate = 3.75 Gbps
Pattern = CJPAT
(10)
Total jitter
(peak-to-peak)
HiGig Receiver Jitter Tolerance
Data Rate = 3.75 Gbps
Deterministic jitter
tolerance (peak-to-peak)
> 0.37
> 0.65
—
—
—
—
—
—
—
—
—
—
—
—
UI
UI
Pattern = CJPAT
Combined deterministic
and random jitter
tolerance (peak-to-peak)
Data Rate = 3.75 Gbps
Pattern = CJPAT
Jitter Frequency = 22.1
KHz
> 8.5
> 0.1
> 0.1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UI
UI
UI
Data Rate = 3.75 Gbps
Pattern = CJPAT
Jitter Frequency =
1.875MHz
Sinusoidal jitter
tolerance (peak-to-peak) Data Rate = 3.75 Gbps
Pattern = CJPAT
Jitter Frequency =
20 MHz
Data Rate = 3.75 Gbps
Pattern = CJPAT
(11)
(OIF) CEI Transmitter Jitter Generation
Data Rate = 6.375 Gbps
Total jitter
—
—
0.3
—
—
0.3
—
—
—
—
0.3
UI
Pattern = PRBS15 BER =
(peak-to-peak)
10-12
(11)
(OIF) CEI Receiver Jitter Tolerance
Data Rate = 6.375 Gbps
Deterministic jitter
> 0.675
> 0.675
>0.675 UI
Pattern = PRBS31 BER =
tolerance (peak-to-peak)
10-12
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
1–40
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
(2)
Table 1–30. Transceiver Block Jitter Specifications for Stratix IV GX Devices (1)
,
(Part 5 of 9)
–3 Commercial/
Industrial
–3 Military (3) and
–4 Commercial/
–2 Commercial
Speed Grade
Symbol/
Description
and –2× Commercial Industrial Speed
Conditions
Unit
Speed Grade
Grade
Min Typ Max Min Typ
Max Min Typ Max
Data Rate = 6.375 Gbps
Pattern=PRBS31
BER = 10-12
Combined deterministic
and random jitter
tolerance (peak-to-peak)
> 0.988
> 0.988
—
—
—
>0.988 UI
Jitter Frequency = 38.2
KHz
Data Rate = 6.375 Gbps
> 5
> 5
—
> 5
UI
Pattern = PRBS31 BER =
10-12
Jitter Frequency = 3.82
MHz
Sinusoidal jitter
tolerance (peak-to-peak)
Data Rate = 6.375 Gbps
> 0.05
> 0.05
> 0.05
> 0.05
—
—
—
—
> 0.05 UI
Pattern = PRBS31 BER =
10-12
Jitter Frequency =
20 MHz
Data Rate= 6.375 Gbps
> 0.05 UI
Pattern = PRBS31 BER =
10-12
(12)
SDI Transmitter Jitter Generation
Data Rate = 1.485 Gbps
(HD) Pattern = Color Bar
Low-Frequency Roll-Off
= 100 KHz
0.2
0.3
—
—
—
—
0.2
0.3
—
—
—
—
0.2
0.3
—
—
—
—
UI
UI
Alignment jitter
(peak-to-peak)
Data Rate = 2.97 Gbps
(3G) Pattern = Color Bar
Low-Frequency Roll-Off
= 100 KHz
Stratix IV Device Handbook
January 2014 Altera Corporation
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–41
Switching Characteristics
(2)
Table 1–30. Transceiver Block Jitter Specifications for Stratix IV GX Devices (1)
,
(Part 6 of 9)
–3 Commercial/
Industrial
–3 Military (3) and
–4 Commercial/
–2 Commercial
Speed Grade
Symbol/
Description
and –2× Commercial Industrial Speed
Conditions
Unit
Speed Grade
Grade
Min Typ Max Min Typ
Max Min Typ Max
(12)
SDI Receiver Jitter Tolerance
Jitter Frequency =
15 KHz
> 2
> 2
> 2
UI
UI
UI
Data Rate = 2.97 Gbps
(3G) Pattern = Single
Line Scramble Color Bar
Jitter Frequency =
100 KHz
Sinusoidal jitter
tolerance (peak-to-peak)
> 0.3
> 0.3
> 0.3
> 0.3
> 0.3
> 0.3
Data Rate = 2.97 Gbps
(3G) Pattern = Single
Line Scramble Color Bar
Jitter Frequency =
148.5 MHz
Data Rate = 2.97 Gbps
(3G) Pattern = Single
Line Scramble Color Bar
Jitter Frequency =
20 KHz
> 1
> 1
> 1
UI
UI
UI
Data Rate = 1.485 Gbps
(HD) Pattern = 75%
Color Bar
Jitter Frequency = 100
KHz Data Rate = 1.485
tolerance (peak-to-peak) Gbps (HD) Pattern =
75% Color Bar
Sinusoidal jitter
> 0.2
> 0.2
> 0.2
> 0.2
> 0.2
> 0.2
Jitter Frequency = 148.5
MHz
Data Rate = 1.485 Gbps
(HD) Pattern = 75%
Color Bar
(17)
SAS Transmit Jitter Generation
Total jitter at 1.5 Gbps
Pattern = CJPAT
(G1)
—
—
—
—
—
—
—
—
—
—
0.55
0.35
0.55
0.35
0.25
—
—
—
—
—
—
—
—
—
—
0.55
0.35
0.55
0.35
0.25
—
—
—
—
—
—
—
—
—
—
0.55
0.35
0.55
0.35
0.25
UI
UI
UI
UI
UI
Deterministic jitter at
Pattern = CJPAT
1.5 Gbps (G1)
Total jitter at 3.0 Gbps
Pattern = CJPAT
(G2)
Deterministic jitter at
Pattern = CJPAT
3.0 Gbps (G2)
Total jitter at 6.0 Gbps
Pattern = CJPAT
(G3)
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
1–42
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
(2)
Table 1–30. Transceiver Block Jitter Specifications for Stratix IV GX Devices (1)
,
(Part 7 of 9)
–3 Commercial/
Industrial
–3 Military (3) and
–4 Commercial/
–2 Commercial
Speed Grade
Symbol/
Description
and –2× Commercial Industrial Speed
Conditions
Unit
Speed Grade
Grade
Min Typ Max Min Typ
Max Min Typ Max
Random jitter at
6.0 Gbps (G3)
Pattern = CJPAT
—
—
0.15
—
—
0.15
—
—
0.15
UI
(17)
SAS Receiver Jitter Tolerance
Total Jitter tolerance at
1.5 Gbps (G1)
Pattern = CJPAT
> 0.65
> 0.35
> 0.65
> 0.35
> 0.65
> 0.35
UI
UI
Deterministic Jitter
tolerance at 1.5 Gbps
(G1)
Pattern = CJPAT
Jitter Frequency = 900
KHz to 5 MHz
Sinusoidal Jitter
tolerance at 1.5 Gbps
(G1)
> 0.1
> 0.1
> 0.1
UI
Pattern = CJTPAT BER =
1E-12
(18)
CPRI Transmit Jitter Generation
E.6.HV, E.12.HV
—
—
—
—
—
—
—
—
0.279
0.35
0.14
0.17
—
—
—
—
—
—
—
—
0.279
0.35
0.14
0.17
—
—
—
—
—
—
—
—
0.279
0.35
0.14
0.17
UI
UI
UI
UI
Pattern = CJPAT
Total Jitter
E.6.LV, E.12.LV, E.24.LV,
E.30.LV
Pattern = CJTPAT
E.6.HV, E.12.HV
Pattern = CJPAT
Deterministic Jitter
E.6.LV, E.12.LV, E.24.LV,
E.30.LV
Pattern = CJTPAT
(18)
CPRI Receiver Jitter Tolerance
E.6.HV, E.12.HV
Total jitter tolerance
> 0.66
> 0.4
> 0.66
> 0.4
> 0.66
> 0.4
UI
UI
Pattern = CJPAT
E.6.HV, E.12.HV
Pattern = CJPAT
Deterministic jitter
tolerance
E.6.LV, E.12.LV, E.24.LV,
E.30.LV
Total jitter tolerance
> 0.65
> 0.37
> 0.55
> 0.65
> 0.37
> 0.55
> 0.65
> 0.37
> 0.55
UI
UI
UI
Pattern = CJTPAT
E.6.LV, E.12.LV, E.24.LV,
E.30.LV
Deterministic jitter
tolerance
Pattern = CJTPAT
E.6.LV, E.12.LV, E.24.LV,
E.30.LV
Combined deterministic
and random jitter
tolerance
Pattern = CJTPAT
Stratix IV Device Handbook
January 2014 Altera Corporation
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–43
Switching Characteristics
(2)
Table 1–30. Transceiver Block Jitter Specifications for Stratix IV GX Devices (1)
,
(Part 8 of 9)
–3 Commercial/
Industrial
–3 Military (3) and
–4 Commercial/
–2 Commercial
Speed Grade
Symbol/
Description
and –2× Commercial Industrial Speed
Conditions
Unit
Speed Grade
Grade
Min Typ Max Min Typ
Max Min Typ Max
(19)
OBSAI Transmit Jitter Generation
Total jitter at 768 Mbps,
1536 Mbps, and
3072 Mbps
REFCLK = 153.6MHz
Pattern = CJPAT
—
—
—
—
0.35
0.17
—
—
—
—
0.35
0.17
—
—
—
—
0.35
0.17
UI
UI
Deterministic jitter at
768 Mbps, 1536 Mbps,
and 3072 Mbps
REFCLK = 153.6MHz
Pattern = CJPAT
(19)
OBSAI Receiver Jitter Tolerance
Deterministic jitter
tolerance at 768 Mbps,
1536 Mbps, and
3072 Mbps
Pattern = CJPAT
> 0.37
> 0.55
> 0.37
> 0.55
> 0.37
> 0.55
UI
UI
Combined deterministic
and random jitter
tolerance at 768 Mbps,
1536 Mbps, and
Pattern = CJPAT
3072 Mbps
Jitter Frequency =
5.4 KHz
> 8.5
> 0.1
> 8.5
> 0.1
> 8.5
> 0.1
> 8.5
> 0.1
> 8.5
> 0.1
> 8.5
> 0.1
UI
UI
UI
UI
Pattern = CJPAT
Sinusoidal Jitter
tolerance at 768 Mbps
Jitter Frequency =
460 MHz to 20 MHz
Pattern = CJPAT
Jitter Frequency =
10.9 KHz
Pattern = CJPAT
Sinusoidal Jitter
tolerance at 1536 Mbps
Jitter Frequency =
921.6 MHz to 20 MHz
Pattern = CJPAT
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
1–44
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
(2)
Table 1–30. Transceiver Block Jitter Specifications for Stratix IV GX Devices (1)
,
(Part 9 of 9)
–3 Commercial/
Industrial
–3 Military (3) and
–4 Commercial/
–2 Commercial
Speed Grade
Symbol/
Description
and –2× Commercial Industrial Speed
Conditions
Unit
Speed Grade
Grade
Min Typ Max Min Typ
Max Min Typ Max
Jitter Frequency = 21.8
KHz
> 8.5
> 0.1
> 8.5
> 8.5
> 0.1
UI
UI
Pattern = CJPAT
Sinusoidal Jitter
tolerance at 3072 Mbps
Jitter Frequency =
1843.2 MHz to 20 MHz
> 0.1
Pattern = CJPAT
Notes to Table 1–30:
(1) Dedicated refclkpins were used to drive the input reference clocks.
(2) The Jitter numbers are valid for the stated conditions only.
(3) Stratix IV GX devices in military speed grade only support selected transceiver configuration up to 3125 Mbps. For more information, contact
Altera sales representative.
(4) The jitter numbers for SONET/SDH are compliant to the GR-253-CORE Issue 3 Specification.
(5) The jitter numbers for Fibre Channel are compliant to the FC-PI-4 Specification revision 6.10.
(6) The jitter numbers for XAUI are compliant to the IEEE802.3ae-2002 Specification.
(7) The jitter numbers for PCI Express (PIPE) (PCIe) are compliant to the PCIe Base Specification 2.0.
(8) The jitter numbers for Serial RapidIO are compliant to the RapidIO Specification 1.3.
(9) The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification.
(10) The jitter numbers for HiGig are compliant to the IEEE802.3ae-2002 Specification.
(11) The jitter numbers for (OIF) CEI are compliant to the OIF-CEI-02.0 Specification.
(12) The HD-SDI and 3G-SDI jitter numbers are compliant to the SMPTE292M and SMPTE424M Specifications.
(13) The fibre channel transmitter jitter generation numbers are compliant to the specification at T interoperability point.
(14) The fibre channel receiver jitter tolerance numbers are compliant to the specification at R interoperability point.
(15) You must use the ATX PLL adjacent to the transceiver channels to meet the transmitter jitter generation compliance in PCIe Gen2 ×8 modes.
(16) Stratix IV PCIe receivers are compliant to this specification provided the VTX-CM-DC-ACTIVEIDLE-DELTA of the upstream transmitter is less than 50mV.
(17) The jitter numbers for Serial Attached SCSI (SAS) are compliant to the SAS-2.1 Specification.
(18) The jitter numbers for CPRI are compliant to the CPRI Specification V3.0.
(19) The jitter numbers for OBSAI are compliant to the OBSAI RP3 Specification V4.1.
Stratix IV Device Handbook
January 2014 Altera Corporation
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–45
Switching Characteristics
Table 1–31 lists the transceiver jitter specifications for protocols supported by
Stratix IV GT devices.
Table 1–31. Transceiver Jitter Specifications for Protocols by Stratix IV GT Devices (Part 1 of 2)
–1 IndustrialSpeed –2 IndustrialSpeed –3 IndustrialSpeed
Symbol/
Description
Grade
Grade
Grade
Conditions
Unit
Min
Typ Max Min Typ Max Min Typ Max
(1) (3)
XLAUI/CAUI Transmit Jitter Generation
,
Total Jitter
Pattern = PRBS-31
OD = 800 mV
—
—
—
0.30
0.17
—
—
—
—
0.30
0.17
—
—
—
—
0.30
0.17
UI
UI
V
REFCLK= 644.53 MHz
Deterministic
Jitter
—
4 (XLAUI)/
10 (CAUI) channels in
Basic ×1 mode
(1)
XLAUI/CAUI Receiver Jitter Tolerance
Total Jitter
Pattern = PRBS-31
tolerance
> 0.62
> 5
> 0.62
> 5
—
—
UI
UI
Jitter Frequency = 40 KHz
Pattern = PRBS-31
Equalization = Disabled
BER = 1E-12
Sinusoidal Jitter
tolerance
Jitter Frequency 4 MHz
Pattern = PRBS-31
Equalization = Disabled
> 0.05
> 0.05
—
—
UI
UI
BER = 1E-12
(2) (3)
XFI Transmitter Jitter Generation
,
Pattern =
PRBS-31
Vod = 800 mV
Total jitter at
10.3125 Gbps
—
—
0.3
—
—
0.3
—
—
REFCLK =
644.53 MHz
10 channels in Basic ×1 mode
(1) (3)
OTL 4.10
,
Total Jitter at
11.18 Gbps
Pattern = PRBS-31
VOD = 800 mV
—
—
—
—
0.30
0.17
—
—
—
—
0.30
0.17
—
—
—
—
0.30
0.17
UI
UI
Deterministic
Jitter
REFCLK= 698.75 MHz
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
1–46
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Table 1–31. Transceiver Jitter Specifications for Protocols by Stratix IV GT Devices (Part 2 of 2)
–1 IndustrialSpeed –2 IndustrialSpeed –3 IndustrialSpeed
Symbol/
Description
Grade
Grade
Grade
Conditions
Unit
Min
Typ Max Min Typ Max Min Typ Max
Jitter Frequency = 40 KHz
Pattern = PRBS-31
Equalization = Disabled
BER = 1E-12
> 5
> 5
—
—
UI
Sinusoidal Jitter
tolerance
Jitter Frequency 4 MHz
Pattern = PRBS-31
Equalization = Disabled
BER = 1E-12
> 0.05
> 0.05
UI
Notes to Table 1–31:
(1) The jitter numbers for XLAUI/CAUI are compliant to the IEEE P802.3ba specification.
(2) Stratix IV GT transceivers are compliant to the XFI datacom transmitter jitter specifications in Table 9 of XFP Revision 4.1.
(3) Contact Altera for board and link best practices at BER = 1E-15.
Table 1–32 lists the SFI-S transmitter jitter specifications for Stratix IV GT devices.
(1) (2)
Table 1–32. SFI-S Transmitter Jitter Specifications for Stratix IV GT Devices
,
-1 Industrial
Speed Grade
-2 Industrial
Speed Grade
-3 Industrial
Speed Grade
Symbol/Description
Conditions
Unit
Mean
Mean
Mean
Pattern = PRBS-31
Vod = 800 mV
Total Transmitter jitter at
11.3 Gbps
(3)
0.23 UI
—
—
UI
(4)
REFCLK = 706.25 MHz
12 channels in Basic ×1 mode
Notes to Table 1–32:
(1) Dedicated refclkpins were used to drive the input reference clocks.
(2) The jitter numbers are valid for stated conditions only.
(3) Two hundred channels were characterized to derive the mean transmitter jitter specification of 0.23 UI. The maximum jitter across the 200 units
characterized was 0.30 UI.
(4) Contact Altera for board and link best practices at BER = 1E-15.
Stratix IV Device Handbook
January 2014 Altera Corporation
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–47
Switching Characteristics
Transceiver Datapath PCS Latency
f
For more information about:
■
■
■
■
■
■
■
Basic mode PCS latency, refer to Figure 1-90 through Figure 1-97 in the Transceiver
Architecture in Stratix IV Devices chapter.
PCIe mode PCS latency, refer to Figure 1-102 in the Transceiver Architecture in
Stratix IV Devices chapter.
XAUI mode PCS latency, refer to Figure 1-119 in the Transceiver Architecture in
Stratix IV Devices chapter.
GIGE mode PCS latency, refer to Figure 1-128 in the Transceiver Architecture in
Stratix IV Devices chapter.
SONET/SDH mode PCS latency, refer to Figure 1-136 in the Transceiver
Architecture in Stratix IV Devices chapter.
SDI mode PCS latency, refer to Figure 1-141 in the Transceiver Architecture in Stratix
IV Devices chapter.
(OIF) CEI PHY mode PCS latency, refer to Figure 1-143 in the Transceiver
Architecture in Stratix IV Devices chapter.
Core Performance Specifications
This section describes the clock tree, phase-locked loop (PLL), digital signal
processing (DSP), TriMatrix, configuration, JTAG, and chip-wide reset (Dev_CLRn
)
specifications.
For the Stratix IV GT –1 and –2 speed grade specifications, refer to the –2/–2× speed
grade column. For the Stratix IV GT –3 speed grade specification, refer to the –3 speed
grade column, unless otherwise specified.
Clock Tree Specifications
Table 1–33 lists the clock tree specifications for Stratix IV devices.
Table 1–33. Clock Tree Performance for Stratix IV Devices
Performance
Unit
Symbol
–2/–2× Speed Grade
–3 Speed Grade
–4 Speed Grade
Global clock and
Regional clock
800
550
700
500
500
500
MHz
MHz
Periphery clock
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
1–48
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
PLL Specifications
Table 1–34 lists the Stratix IV PLL specifications when operating in the commercial
(0° to 85°C), industrial (–40° to 100°C), and military (–55°C to 125°C) junction
temperature ranges.
Table 1–34. PLL Specifications for Stratix IV Devices (Part 1 of 2)
Symbol
Parameter
Min
5
Typ
—
—
—
—
—
—
—
—
Max
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
%
(1)
Input clock frequency (–2/–2x speed grade)
Input clock frequency (–3 speed grade)
Input clock frequency (–4 speed grade)
Input frequency to the PFD
800
717
717
(1)
(1)
fIN
5
5
fINPFD
5
325
PLL VCO operating range (–2 speed grade)
PLL VCO operating range (–3 speed grade)
PLL VCO operating range (–4 speed grade)
Input clock or external feedback clock input duty cycle
600
600
600
40
1600
1300
1300
60
(2)
fVCO
tEINDUTY
Output frequency for internal global or regional clock
(–2/–2x speed grade)
(3)
—
—
—
—
—
—
800
717
717
MHz
MHz
MHz
Output frequency for internal global or regional clock
(–3 speed grade)
(3)
(3)
fOUT
Output frequency for internal global or regional clock
(–4 speed grade)
(3)
(3)
(3)
Output frequency for external clock output (–2 speed grade)
Output frequency for external clock output (–3 speed grade)
Output frequency for external clock output (–4 speed grade)
Duty cycle for external clock output (when set to 50%)
External feedback clock compensation time
—
—
—
45
—
—
—
—
50
—
800
717
717
MHz
MHz
MHz
%
fOUT_EXT
tOUTDUTY
tFCOMP
55
10
ns
scanclk
cycles
tCONFIGPLL
Time required to reconfigure scan chain
—
3.5
—
scanclk
cycles
tCONFIGPHASE
fSCANCLK
tLOCK
Time required to reconfigure phase shift
scanclk frequency
—
—
—
1
—
—
—
100
1
MHz
Time required to lock from end-of-device configuration or
de-assertion of areset
ms
Time required to lock dynamically (after switchover or
reconfiguring any non-post-scale counters/delays)
tDLOCK
—
—
1
ms
PLL closed-loop low bandwidth
—
—
—
—
10
—
—
—
—
0.3
1.5
4
—
—
MHz
MHz
fCLBW
PLL closed-loop medium bandwidth
(8)
PLL closed-loop high bandwidth
—
MHz
tPLL_PSERR
tARESET
Accuracy of PLL phase shift
—
—
—
—
—
—
50
ps
Minimum pulse width on the aresetsignal
Input clock cycle to cycle jitter (FREF ≥ 100 MHz)
Input clock cycle to cycle jitter (FREF < 100 MHz)
Period Jitter for dedicated clock output (FOUT ≥ 100 MHz)
Period Jitter for dedicated clock output (FOUT < 100 MHz)
—
ns
0.15
750
175
17.5
UI (p-p)
ps (p-p)
ps (p-p)
mUI (p-p)
(4) (5)
tINCCJ
,
(6)
tOUTPJ_DC
Stratix IV Device Handbook
January 2014 Altera Corporation
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–49
Switching Characteristics
Table 1–34. PLL Specifications for Stratix IV Devices (Part 2 of 2)
Symbol
Parameter
Min
Typ
Max
Unit
Cycle to Cycle Jitter for dedicated clock output
(FOUT ≥ 100 MHz)
—
—
175
ps (p-p)
mUI (p-p)
ps (p-p)
mUI (p-p)
ps (p-p)
mUI (p-p)
ps (p-p)
mUI (p-p)
%
(6)
tOUTCCJ_DC
Cycle to Cycle Jitter for dedicated clock output
(FOUT < 100 MHz)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
17.5
600
60
Period Jitter for clock output on regular I/O
(FOUT ≥ 100 MHz)
(6)
tOUTPJ_IO
,
(9)
Period Jitter for clock output on regular I/O
(FOUT < 100 MHz)
Cycle to Cycle Jitter for clock output on regular I/O
(FOUT ≥ 100 MHz)
600
60
(6)
tOUTCCJ_IO
,
(9)
Cycle to Cycle Jitter for clock output on regular I/O
(FOUT < 100 MHz)
Period Jitter for dedicated clock output in cascaded PLLs
(FOUT ≥100MHz)
250
25
tCASC_OUTPJ_DC
(6) (7)
,
Period Jitter for dedicated clock output in cascaded PLLs
(FOUT < 100MHz)
Frequency drift after PFDENA is disabled for duration of
100 us
fDRIFT
10
Notes to Table 1–34:
(1) This specification is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O
standard.
(2) The VCO frequency reported by the Quartus II software in the PLL summary section of the compilation report takes into consideration the VCO
post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the fVCO specification.
(3) This specification is limited by the lower of the two: I/O FMAX or FOUT of the PLL.
(4) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source that is less
than 120 ps.
(5) FREF is fIN/N when N = 1.
(6) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies
to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a
different measurement method and are available in Table 1–51 on page 1–62.
(7) The cascaded PLL specification is only applicable with the following condition:
A. Upstream PLL: 0.59Mhz Upstream PLL BW < 1 MHz
B. Downstream PLL: Downstream PLL BW > 2 MHz
(8) High bandwidth PLL settings are not supported in external feedback mode.
(9) External memory interface clock output jitter specifications use a different measurement method, which is available in Table 1–49 on
page 1–61.
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
1–50
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
DSP Block Specifications
Table 1–35 lists the Stratix IV DSP block performance specifications.
(1)
Table 1–35. Block Performance Specifications for Stratix IV DSP Devices
Resources
Used
Performance
–3
–1 Industrial
–3
–4
–4
Mode
Unit
and–2/–2×
Commercial/
Industrial
Number of
Multipliers
Commercial Industrial Commercial Industrial
Speed
Grade
Speed
Grade
Speed
Grade
Speed
Grade
Speed Grade
9×9-bit multiplier (A, C, E, G) (2)
9×9-bit multiplier (B, D, F, H) (2)
12×12-bit multiplier (A, E) (3)
12×12-bit multiplier (B, D, F, H) (3)
18×18-bit multiplier
1
1
1
1
1
1
4
4
520
520
540
540
600
480
490
510
460
460
500
500
550
440
440
470
460
460
500
500
550
440
440
470
400
400
440
440
480
380
380
410
400
400
440
430
480
380
380
400
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
36×36-bit multiplier
18×18-bit multiply accumulator
18×18-bit multiply adder
18×18-bit multiply adder-signed full
precision
2
2
490
390
450
350
440
350
390
310
390
300
MHz
MHz
18×18-bit multiply adder with
(4)
loopback
36-bit shift (32-bit data)
Double mode
1
1
490
480
440
440
440
440
380
380
380
370
MHz
MHz
Notes to Table 1–35:
(1) Maximum is for fully pipelined block with Round and Saturation disabled.
(2) The DSP block implements eight independent 9b´9b multiplies using A, B, C, D for the top DSP half block and E, F, G, H for the bottom DSP half block
multipliers.
(3) The DSP block implements six independent 12b´12b multiplies using A, B, D for the top DSP half block and E, F, H for the bottom DSP half block
multipliers.
(4) Maximum for loopback input registers disabled, Round and Saturation disabled, and pipeline and output registers enabled.
Stratix IV Device Handbook
January 2014 Altera Corporation
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–51
Switching Characteristics
TriMatrix Memory Block Specifications
Table 1–36 lists the Stratix IV TriMatrix memory block specifications.
Table 1–36. TriMatrix Memory Block Performance Specifications for Stratix IV Devices (1) (Part 1 of 2)
Resources Used
Performance
–3
–1Industrial
–3
–4
–4
Industrial/
and –2 /–2× Commercial/
Commercial/ Industrial/
Industrial
Speed
Memory
Mode
TriMatrix
ALUTs
Commercial/ Military
Unit
Memory
Industrial
SpeedGrade
Speed
Industrial
SpeedGrade Speed Grade
Military
Grade
Grade
(2)
(2)
Single port
64×10
0
0
0
1
1
1
600
600
600
500
500
500
450
450
450
500
500
500
450
450
450
MHz
MHz
MHz
Simple dual-port
32×20
MLAB
(3)
Simple dual-port
64×10
ROM 64×10
ROM 32×20
0
0
1
1
600
600
500
500
450
450
500
500
450
450
MHz
MHz
Single-port
256×36
0
0
1
1
600
550
540
490
475
420
540
490
475
420
MHz
MHz
Simple dual-port
256×36
Simple dual-port
256×36, with the
read-during-write
option set to Old
Data
0
0
0
1
1
1
375
490
375
340
430
335
300
370
290
340
430
335
300
370
290
MHz
MHz
MHz
True dual port
512×18
M9K
Block
True dual-port
512×18, with the
read-during-write
option set to Old
Data
(3)
ROM 1 Port
ROM 2 Port
0
0
1
1
600
600
540
540
475
475
540
540
475
475
MHz
MHz
Min Pulse Width
(clock high time)
—
—
—
—
750
500
800
625
850
690
800
625
850
690
ps
ps
Min Pulse Width
(clock low time)
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
1–52
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Table 1–36. TriMatrix Memory Block Performance Specifications for Stratix IV Devices (1) (Part 2 of 2)
Resources Used
Performance
–3
–1Industrial
–3
–4
–4
Industrial/
and –2 /–2× Commercial/
Commercial/ Industrial/
Industrial
Speed
Memory
Mode
TriMatrix
ALUTs
Commercial/ Military
Unit
Memory
Industrial
SpeedGrade
Speed
Industrial
SpeedGrade Speed Grade
Military
Grade
Grade
(2)
(2)
Single-port
4K×36
0
0
1
1
475
465
440
435
380
385
400
375
350
325
MHz
MHz
Simple dual-port
2K×72
Simple dual-port
2K×72, with the
read-during-write
option set to Old
Data
0
1
260
240
205
225
200
MHz
Simple dual-port
2K×64 (with
ECC)
0
0
1
1
335
400
300
375
255
330
295
350
250
310
MHz
MHz
M144K
True dual-port
4K×36
Block
(3)
True dual-port
4K×36, with the
read-during-write
option set to Old
Data
0
1
245
230
205
225
200
MHz
ROM 1 Port
ROM 2 Port
0
0
1
1
540
500
500
465
435
400
450
425
420
400
MHz
MHz
Min Pulse Width
(clock high time)
—
—
—
—
700
500
755
625
860
690
860
690
950
690
ps
ps
Min Pulse Width
(clock low time)
Notes to Table 1–36:
(1) To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL set
to 50% output duty cycle. Use the Quartus II software to report timing for this and other memory block clocking schemes.
(2) This is only applicable to the Stratix IV E and GX devices.
(3) When you use the error detection CRC feature, there is no degradation in FMAX
.
Configuration and JTAG Specifications
Table 1–37 lists the Stratix IV configuration mode specifications.
Table 1–37. Configuration Mode Specifications for Stratix IV Devices
DCLK FMAX
Programming Mode
Unit
Min
—
Typ
—
—
26
Max
125
125
40
Passive serial
MHz
MHz
MHz
(1)
Fast passive parallel
Fast active serial
—
17
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
January 2014 Altera Corporation
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–53
Switching Characteristics
Table 1–37. Configuration Mode Specifications for Stratix IV Devices
DCLK FMAX
Programming Mode
Unit
Min
Typ
Max
Remote update only in fast AS mode
4.3
5.3
10
MHz
Note to Table 1–37:
(1) This denotes the maximum frequency supported in the FPP configuration scheme. The frequency supported for
each device may vary depending on device density. For more information, refer to the Configuration, Design
Security, and Remote System Upgrades in Stratix IV Devices chapter.
Table 1–38 lists the JTAG timing parameters and values for Stratix IV devices.
Table 1–38. JTAG Timing Parameters and Values for Stratix IV Devices
Symbol
Description
TCK clock period
Min
30
14
14
1
Max
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
tJCP
tJCH
tJCL
TCK clock high time
—
TCK clock low time
—
tJPSU (TDI)
tJPSU (TMS)
tJPH
TDI JTAG port setup time
TMS JTAG port setup time
JTAG port hold time
—
3
—
5
—
(1)
tJPCO
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
—
—
—
11
14
14
(1)
(1)
tJPZX
tJPXZ
Note to Table 1–38:
(1) A 1 ns adder is required for each VCCIO voltage step down from 3.0 V. For example, tJPCO = 12 ns if VCCIO of the TDO
I/O bank = 2.5 V, or 13 ns if it equals 1.8 V.
Temperature Sensing Diode Specifications
Table 1–39 lists the specifications for the Stratix IV temperature sensing diode.
Table 1–39. External Temperature Sensing Diode Specifications for Stratix IV Devices
Description
Min
8
Typ
—
Max
500
0.9
Unit
A
V
I
bias, diode source current
Vbias, voltage across diode
Series resistance
0.3
—
—
—
< 5
Diode ideality factor
1.026
1.028
1.030
—
Table 1–40 lists the specifications for the Stratix IV internal temperature sensing diode.
Table 1–40. Internal Temperature Sensing Diode Specifications for Stratix IV Devices
Temperature
Range
Offset Calibrated
Option
Conversion
Time
Minimum Resolution
with No Missing Codes
Accuracy
Sampling Rate
Resolution
Frequency:
500 kHz, 1 MHz
–40 to 100 °C
8 °C
No
< 100 ms
8 bits
8 bits
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
1–54
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Chip-Wide Reset (Dev_CLRn) Specifications
Table 1–41 lists the specifications for the Stratix IV chip-wide reset (Dev_CLRn). This
specifications denote the minimum pulse width of the Dev_CLRnsignal required to
clear all the device registers.
Table 1–41. Chip-Wide Reset (DEV_CLRn) Specifications
Description
Min
Typ
Max
Unit
Dev_CLRn
500
—
—
s
Periphery Performance
This section describes periphery performance, including high-speed I/O and external
memory interface.
I/O performance supports several system interfaces, such as the LVDS high-speed
I/O interface, external memory interface, and the PCI/PCI-X bus interface.
General-purpose I/O standards such as 3.3-, 2.5-, 1.8-, and 1.5-LVTTL/LVCMOS are
capable of typical 167 MHz and 1.2 LVCMOS at 100 MHz interfacing frequency with
10 pF load.
For the Stratix IV GT –1 and –2 speed grade specifications, refer to the –2/–2× speed
grade column. For the Stratix IV GT –3 speed grade specification, refer to the –3 speed
grade column, unless otherwise specified.
1
Actual achievable frequency depends on design- and system-specific factors. You
must perform HSPICE/IBIS simulations based on your specific design and system
setup to determine the maximum achievable frequency in your system.
High-Speed I/O Specification
Table 1–42 lists the high-speed I/O timing for Stratix IV devices.
(1), (2)
Table 1–42. High-Speed I/O Specifications
(Part 1 of 3)
–2/–2× Speed Grade
–3 Speed Grade
Min Typ Max
–4 Speed Grade
Min Typ Max
Symbol
Conditions
Unit
Min Typ
Max
f
HSCLK_in (input
clock frequency)
True Differential I/O
Standards
Clock boost factor W = 1 to 40
800
5
5
—
—
5
5
—
—
717
717
420
5
5
—
—
717
717
420
MHz
(3)
(4)
fHSCLK_in (input
clock frequency)
Single Ended I/O
Clock boost factor W = 1 to 40
800
520
MHz
(3)
(12)
Standards
f
HSCLK_in (input
clock frequency)
Single Ended I/O
Clock boost factor W = 1 to 40
5
5
—
—
5
5
—
—
5
5
—
—
MHz
MHz
(3)
(13)
Standards
fHSCLK_OUT (output
clock frequency)
800
717
717
—
(9)
(9)
(9)
Stratix IV Device Handbook
January 2014 Altera Corporation
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–55
Switching Characteristics
(1), (2)
Table 1–42. High-Speed I/O Specifications
(Part 2 of 3)
–2/–2× Speed Grade
–3 Speed Grade
–4 Speed Grade
Symbol
Conditions
Unit
Min Typ
Max
Min Typ
Max
Min Typ
Max
Transmitter
SERDES factor J = 3 to 10
(5)
(5)
(5)
—
1600
—
1250
—
1250 Mbps
(10), (11)
True Differential I/O
Standards - fHSDR
(data rate)
SERDES factor J = 2,
Uses DDR Registers
(5)
(6)
(5)
(6)
(5)
(6)
—
—
—
Mbps
SERDES factor J = 1,
Uses an SDR Register
(5)
(6)
(5)
(6)
(5)
(6)
—
—
—
Mbps
Emulated
Differential I/O
Standards with
Three External
Output Resistor
Networks - fHSDR
(5)
(5)
(5)
—
1250
—
1152
—
800 Mbps
(7)
(data rate)
SERDES factor J = 4 to 10
Emulated
Differential I/O
Standards with One
External Output
Resistor - fHSDR
(data rate)
(5)
(5)
(5)
—
311
—
200
—
200 Mbps
Total Jitter for Data Rate,
600 Mbps to 1.6 Gbps
—
—
—
—
—
—
160
0.1
—
—
—
—
—
—
160
0.1
—
—
—
—
—
—
160
0.1
ps
UI
ps
tx Jitter - True
Differential I/O
Standards
Total Jitter for Data Rate,
< 600 Mbps
tx Jitter - Emulated
Differential I/O
Standards with
Three External
Output Resistor
Network
Total Jitter for Data Rate,
600 Mbps to 1.25 Gbps
300
300
325
Total Jitter for Data Rate
< 600 Mbps
—
—
—
—
0.2
—
—
—
—
0.2
—
—
—
—
0.25
0.15
UI
UI
tx Jitter - Emulated
Differential I/O
Standards with One
External Output
Resistor Network
—
0.125
0.15
Tx output clock duty cycle for
both True and Emulated
Differential I/O Standards
tDUTY
45
—
—
50
—
—
55
45
—
—
50
—
—
55
45
—
—
50
—
—
55
%
ps
ps
True Differential I/O Standards
160
250
200
250
200
300
Emulated Differential I/O
Standards with Three External
Output Resistor Networks
tRISE & tFALL
Emulated Differential I/O
Standards with One External
Output Resistor
—
—
460
—
—
500
—
—
500
ps
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
1–56
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
(1), (2)
Table 1–42. High-Speed I/O Specifications
(Part 3 of 3)
–2/–2× Speed Grade
–3 Speed Grade
Min Typ Max
–4 Speed Grade
Min Typ Max
Symbol
Conditions
Unit
Min Typ
Max
True Differential I/O Standards
—
—
100
—
—
—
—
100
250
—
—
—
—
100
250
ps
ps
TCCS
Emulated Differential I/o
Standards
—
—
250
Receiver
True Differential I/O
Standards -
SERDES factor J = 3 to 10 (11) 150
—
1600 150
—
1250 150
—
1250 Mbps
fHSDRDPA (data rate)
(5)
(8)
(6)
(5)
(5)
(8)
(6)
(5)
(5)
(8)
SERDES factor J = 3 to 10
—
—
—
—
—
—
Mbps
SERDES factor J = 2,
Uses DDR Registers
(5)
(6)
Mbps
fHSDR (data rate)
SERDES factor J = 1,
Uses an SDR Register
(5)
(6)
(5)
(6)
(5)
(6)
—
—
—
—
—
—
—
—
—
—
—
—
Mbps
DPA Mode
DPA run length
—
—
—
—
—
—
10000
300
—
—
—
10000
300
—
—
—
10000
300
UI
Soft CDR mode
Soft-CDR PPM
tolerance
PPM
ps
Non DPA Mode
Sampling Window
Notes to Table 1–42:
300
300
300
(1) When J = 3 to 10, use the serializer/deserializer (SERDES) block.
(2) When J = 1 or 2, bypass the SERDES block.
(3) Clock Boost Factor (W) is the ratio between input data rate to the input clock rate.
(4) For 820, 530, 360, and 290 density devices, the frequency is 762 MHz.
(5) The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional, or local)
that you use. The I/O differential buffer and input register do not have a minimum toggle rate.
(6) The maximum ideal frequency is the SERDES factor (J) x the PLL maximum output frequency (fOUT) provided you can close the design timing and the
signal integrity simulation is clean.
(7) You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin,
transmitter channel-to-channel skew, and receiver sampling margin to determine leftover timing margin.
(8) You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board skew
margin, transmitter delay margin, and the receiver sampling margin to determine the maximum data rate supported.
(9) This is achieved by using the LVDS and DPA clock network.
(10) If the receiver with DPA enabled and transmitter are using shared PLLs, the minimum data rate is 150 Mbps.
(11) The fMAX specification is based on the fast clock used for serial data. The interface fMAX also depends on the parallel clock domain, which is design
dependent and requires timing analysis.
(12) This only applies to DPA and soft-CDR modes.
(13) This only applies to LVDS source synchronous mode.
Stratix IV Device Handbook
January 2014 Altera Corporation
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–57
Switching Characteristics
Table 1–43 lists the DPA lock time specifications for Stratix IV ES devices.
(1) (2) (3)
Table 1–43. DPA Lock Time Specifications—Stratix IV ES Devices Only
,
,
Number of
Number of Data
repetitions
Transitions in
per 256
Standard
Training Pattern
one repetition
of training
pattern
Condition
Maximum
data
transitions
(4)
without DPA PLL
calibration
256 data transitions
SPI-4
00000000001111111111
00001111
2
2
4
8
8
128
128
64
with DPA PLL
calibration
3x256 data transitions +
2x96 slow clock cycles
(5)
without DPA PLL
calibration
256 data transitions
with DPA PLL
calibration
3x256 data transitions +
2x96 slow clock cycles
(5)
Parallel Rapid
I/O
without DPA PLL
calibration
256 data transitions
10010000
with DPA PLL
calibration
3x256 data transitions +
2x96 slow clock cycles
(5)
without DPA PLL
calibration
256 data transitions
10101010
32
with DPA PLL
calibration
3x256 data transitions +
2x96 slow clock cycles
(5)
Miscellaneous
without DPA PLL
calibration
256 data transitions
01010101
32
with DPA PLL
calibration
3x256 data transitions +
2x96 slow clock cycles
(5)
Notes to Table 1–43:
(1) The DPA lock time is for one channel.
(2) One data transition is defined as a 0-to-1 or 1-to-0 transition.
(3) The DPA lock time applies to commercial, industrial, and military speed grades.
(4) This is the number of repetition for the stated training pattern to achieve 256 data transitions.
(5) Slow clock = Data rate (Mbps)/Deserialization factor.
Figure 1–4 shows the DPA lock time specifications with DPA PLL calibration enabled.
Figure 1–4. DPA Lock Time Specification with DPA PLL Calibration Enabled
rx_reset
DPA Lock Time
rx_dpa_locked
256 data
transitions
96 slow
clock cycles
256 data
transitions
96 slow
clock cycles
256 data
transitions
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
1–58
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Table 1–44 lists the DPA lock time specifications for Stratix IV GX and GT devices.
(1) (2) (3)
Table 1–44. DPA Lock Time Specifications—Stratix IV GX and GT Devices Only
Number of Data
,
,
Number of Repetitions
Transitions in One
Repetition of the
Training Pattern
Standard
Training Pattern
per 256 Data Transitions
Maximum
(4)
SPI-4
00000000001111111111
00001111
2
2
4
8
8
128
128
64
640 data transitions
640 data transitions
640 data transitions
640 data transitions
640 data transitions
Parallel Rapid
I/O
10010000
10101010
32
Miscellaneous
01010101
32
Notes to Table 1–44:
(1) The DPA lock time is for one channel.
(2) One data transition is defined as a 0-to-1 or 1-to-0 transition.
(3) The DPA lock time stated in the table applies to commercial, industrial, and military speed grades.
(4) This is the number of repetitions for the stated training pattern to achieve the 256 data transitions.
Figure 1–5 shows the LVDS soft-CDR/DPA sinusoidal jitter tolerance specification for
a data rate equal to or higher than 1.25 Gbps. Table 1–45 lists this information in table
form.
Figure 1–5. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification for a Data Rate Equal to or Higher Than
1.25 Gbps
LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification
25
8.5
0.35
0.1
F3
F2
F1
F4
Jitter Frequency (Hz)
Stratix IV Device Handbook
January 2014 Altera Corporation
Volume 4: Device Datasheet and Addendum
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–59
Switching Characteristics
Table 1–45 lists the LVDS soft-CDR/DPA sinusoidal jitter tolerance specification for a
data rate equal to or higher than 1.25 Gbps.
Table 1–45. LVDS Soft-CDR/DPA Sinusoidal Jitter Mask Values for a Data Rate Equal to or Higher
than 1.25 Gbps
Jitter Frequency (Hz)
Sinusoidal Jitter (UI)
25.000
F1
F2
F3
F4
10,000
17,565
25.000
1,493,000
50,000,000
0.350
0.350
Figure 1–6 shows the LVDS soft-CDR/DPA sinusoidal jitter tolerance specification for
a data rate less than 1.25 Gbps.
Figure 1–6. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification for a Data Rate Less than 1.25 Gbps
Sinusoidal Jitter Amplitude
20db/dec
0.1 UI
P-P
Frequency
20 MHz
baud/1667
When the data rate is equals to 800 Mbps, the LVDS soft-CDR/DPA sinusoidal jitter
tolerance allows up to 0.1 UI (125 ps) for jitter frequencies between 479.9 kHz and
20 MHz.
DLL and DQS Logic Block Specifications
Table 1–46 lists the DLL frequency range specifications for Stratix IV devices.
Table 1–46. DLL Frequency Range Specifications for Stratix IV Devices (Part 1 of 2)
Frequency Range (MHz)
Number of
Delay
Chains
Frequency
Mode
DQS Delay Buffer
Available Phase Shift
(1)
–2/–2×
–3
–4
Mode
Speed Grade
Speed Grade Speed Grade
0
1
2
3
90-140
90-130
120-170
150-210
180-260
90-120
120-160
150-200
180-240
22.5°, 45°, 67.5°, 90°
30°, 60°, 90°, 120°
36°, 72°, 108°, 144°
45°, 90°,135°, 180°
Low
Low
Low
Low
16
12
10
8
120-180
150-220
180-280
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
1–60
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Table 1–46. DLL Frequency Range Specifications for Stratix IV Devices (Part 2 of 2)
Frequency Range (MHz)
Number of
Delay
Chains
Frequency
DQS Delay Buffer
Available Phase Shift
(1)
–2/–2×
–3
–4
Mode
Mode
Speed Grade
Speed Grade Speed Grade
4
240-350
290-430
360-540
470-700
240-320
290-380
360-450
470-630
240-290
290-360
360-450
470-590
30°, 60°, 90°, 120°
36°, 72°, 108°, 144°
45°, 90°, 135°, 180°
60°, 120°, 180°, 240°
High
High
High
High
12
10
8
5
6
7
6
Note to Table 1–46:
(1) Low indicates a 6-bit DQS delay setting; high indicates a 5-bit DQS delay setting.
Table 1–47 lists the DQS phase offset delay per stage for Stratix IV devices.
(2) (3)
Table 1–47. DQS Phase Offset Delay Per Setting for Stratix IV Devices (1)
,
,
Speed Grade
Min
7
Max
13
Unit
–2/–2×
–3
ps
ps
ps
7
15
–4
7
16
Notes to Table 1–47:
(1) The valid settings for phase offset are -64 to +63 for frequency modes 0 to 3 and -32 to +31 for frequency modes
4 to 6.
(2) The typical value equals the average of the minimum and maximum values.
(3) The delay settings are linear, with a cumulative delay variation of 40 ps for all speed grades. For example, when
using a –2 speed grade and applying a 10 phase offset settings to a 90° phase shift at 400 MHz, the expected
average cumulative delay is [625 ps + (10 × 10.5 ps) 20 ps] = 730 ps 20 ps.
Table 1–48 lists the DQS phase shift error for Stratix IV devices.
Table 1–48. DQS Phase Shift Error Specification for DLL-Delayed Clock (tDQS_PSERR) for Stratix IV
Devices (1)
Number of DQS Delay
Buffer
–2/–2X
Speed Grade
–3
–4
Unit
Speed Grade
Speed Grade
1
2
3
26
52
28
56
30
60
ps
ps
ps
ps
78
84
90
4
104
112
120
Note to Table 1–48:
(1) This error specification is the absolute maximum and minimum error. For example, skew on three DQS delay
buffers in a –2/–2x speed grade is 78 ps or 39 ps.
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
January 2014 Altera Corporation
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–61
Switching Characteristics
Table 1–49 lists the memory output clock jitter specifications for Stratix IV devices.
(2) (3)
Table 1–49. Memory Output Clock Jitter Specification for Stratix IV Devices (1)
–2/–2X
,
,
–3
–4
Clock
Speed Grade
Speed Grade
Speed Grade
Parameter
Symbol
Unit
Network
Min
-50
Max
50
Min
-55
Max
55
Min
-55
Max
55
Clock period jitter
Regional
Regional
Regional
Global
tJIT(per)
tJIT(cc)
ps
ps
ps
ps
ps
ps
Cycle-to-cycle period jitter
Duty cycle jitter
-100
-50
100
50
-110
-82.5
-82.5
-165
-90
110
82.5
82.5
165
90
-110
-82.5
-82.5
-165
-90
110
82.5
82.5
165
90
tJIT(duty)
tJIT(per)
tJIT(cc)
Clock period jitter
-75
75
Cycle-to-cycle period jitter
Global
-150
-75
150
75
Duty cycle jitter
Global
tJIT(duty)
Notes to Table 1–49:
(1) The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2/DDR3 SDRAM standard.
(2) The clock jitter specification applies to memory output clock pins generated using differential signal-splitter and DDIO circuits clocked by a PLL
output routed on a regional or global clock network as specified. Altera recommends using regional clock networks whenever possible.
(3) The memory output clock jitter stated in Table 1–49 is applicable when an input jitter of 30 ps is applied.
OCT Calibration Block Specifications
Table 1–50 lists the OCT calibration block specifications for Stratix IV devices.
Table 1–50. OCT Calibration Block Specifications for Stratix IV Devices
Symbol
Description
Min
Typ
Max
Unit
OCTUSRCLK
Clock required by OCT calibration blocks
—
—
20
MHz
Number of OCTUSRCLK clock cycles required for OCT RS/RT
calibration
TOCTCAL
—
—
1000
28
—
—
Cycles
Cycles
Number of OCTUSRCLK clock cycles required for OCT code
to shift out
TOCTSHIFT
Time required between the dyn_term_ctrland oesignal
transitions in a bidirectional I/O buffer to dynamically switch
between OCT RS and RT
TRS_RT
—
2.5
—
ns
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
1–62
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
I/O Timing
Figure 1–7 shows the timing diagram for the oeand dyn_term_ctrlsignals.
Figure 1–7. Timing Diagram for the oe and dyn_term_ctrl Signals
Tristate
Tristate
T
X
R
R
X
X
oe
dyn_term_ctrl
T
RS_RT
T
RS_RT
Duty Cycle Distortion (DCD) Specifications
Table 1–51 lists the worst-case DCD for Stratix IV devices.
Table 1–51. Worst-Case DCD on Stratix IV I/O Pins (1)
–2/–2×
Speed Grade
–3
–4
Speed Grade
Speed Grade
Symbol
Unit
Min
45
Max
Min
Max
Min
Max
Output Duty Cycle
55
45
55
45
55
%
Note to Table 1–51:
(1) The listed specification is only applicable to the output buffer across different I/O standards.
I/O Timing
Altera offers two ways to determine I/O timing—the Excel-based I/O Timing and the
Quartus II Timing Analyzer.
Excel-based I/O Timing provides pin timing performance for each device density and
speed grade. The data is typically used prior to designing the FPGA to get an estimate
of the timing budget as part of the link timing analysis. The Quartus II Timing
Analyzer provides a more accurate and precise I/O timing data based on the specifics
of the design after you complete place-and-route.
f
The Excel-based I/O Timing spreadsheet is downloadable from the Literature:
Stratix IV Devices webpage.
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
January 2014 Altera Corporation
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–63
I/O Timing
Programmable IOE Delay
Table 1–52 lists the Stratix IV IOE programmable delay settings.
Table 1–52. IOE Programmable Delay for Stratix IV Devices
Fast Model
Slow Model
Parameter Available Min Offset
(1)
(2)
Industrial/ Commercial
Military
Settings
(3)
C2
C3
C4
I3/M3
I4
Unit
(3)
D1
D2
D3
D4
D5
D6
16
8
0
0
0
0
0
0
0.462
0.234
1.700
0.508
0.472
0.186
0.505
0.232
1.769
0.554
0.500
0.195
0.732
0.337
2.695
0.813
0.747
0.294
0.795
0.372
2.927
0.882
0.799
0.319
0.857
0.407
3.157
0.952
0.875
0.345
0.801
0.371
2.948
0.889
0.817
0.321
0.864
0.405
3.178
0.959
0.882
0.347
ns
ns
ns
ns
ns
ns
8
16
16
8
Notes to Table 1–52:
(1) You can set this value in the Quartus II software by selecting D1, D2, D3, D4, D5, and D6 in the Assignment Name column.
(2) Minimum offset does not include the intrinsic delay.
(3) For the EP4SGX530 device density, the IOE programmable delays have an additional 5% maximum offset.
Programmable Output Buffer Delay
Table 1–53 lists the delay chain settings that control the rising and falling edge delays
of the output buffer. The default delay is 0 ps.
(1)
Table 1–53. Programmable Output Buffer Delay
Symbol
Parameter
Typical
0 (default)
50
Unit
ps
ps
Rising and/or falling edge
delay
DOUTBUF
100
ps
150
ps
Note to Table 1–53:
(1) You can set the programmable output buffer delay in the Quartus II software by setting the Output Buffer Delay
Control assignment to either positive, negative, or both edges, with the specific values stated here (in ps) for the
Output Buffer Delay assignment.
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
1–64
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Glossary
Glossary
Table 1–54 lists the glossary for this chapter.
Table 1–54. Glossary Table (Part 1 of 4)
Letter
Subject
Definitions
A, B, C
—
—
Receiver Input Waveforms
Single-Ended Waveform
Positive Channel (p) = V
IH
V
ID
Negative Channel (n) = V
IL
V
CM
Ground
Differential Waveform
V
ID
p − n = 0 V
V
ID
Differential I/O
Standards
D
Transmitter Output Waveforms
Single-Ended Waveform
Positive Channel (p) = V
OH
V
OD
Negative Channel (n) = V
OL
V
CM
Ground
Differential Waveform
V
OD
p − n = 0 V
V
OD
E
F
—
—
fHSCLK
Left/right PLL input clock frequency.
High-speed I/O block: Maximum/minimum LVDS data transfer rate
(fHSDR = 1/TUI), non-DPA.
fHSDR
High-speed I/O block: Maximum/minimum LVDS data transfer rate
(fHSDRDPA = 1/TUI), DPA.
fHSDRDPA
—
G, H, I
—
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
January 2014 Altera Corporation
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–65
Glossary
Table 1–54. Glossary Table (Part 2 of 4)
Letter
Subject
Definitions
High-speed I/O block: Deserialization factor (width of parallel data bus).
JTAG Timing Specifications:
J
TMS
TDI
tJCP
J
JTAG Timing
Specifications
tJCH
t JCL
tJPH
tJPSU
TCK
TDO
tJPXZ
tJPZX
tJPCO
K, L,
M, N, O
—
—
(1)
Diagram of PLL Specifications
Switchover
CLKOUT Pins
fOUT_EXT
CLK
fIN
fINPFD
N
GCLK
RCLK
Counters
C0..C9
fVCO
VCO
fOUT
PFD
CP
LF
Core Clock
PLL
Specifications
P
M
Key
External Feedback
Reconfigurable in User Mode
Note:
(1) Core Clockcan only be fed by dedicated clock input pins or PLL outputs.
Q
R
—
—
RL
Receiver differential input discrete resistor (external to Stratix IV device).
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
1–66
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Glossary
Table 1–54. Glossary Table (Part 3 of 4)
Letter
Subject
Definitions
Timing Diagram—the period of time during which the data must be valid in order to capture
it correctly. The setup and hold times determine the ideal strobe position within the sampling
window, as shown:
SW (sampling
window)
Bit Time
Sampling Window
(SW)
RSKM
RSKM
0.5 x TCCS
0.5 x TCCS
The JEDEC standard for SSTl and HSTL I/O defines both the AC and DC input signal values.
The AC values indicate the voltage levels at which the receiver must meet its timing
specifications. The DC values indicate the voltage levels at which the final logic state of the
receiver is unambiguously defined. After the receiver input has crossed the AC value, the
receiver changes to the new logic state.
The new logic state is then maintained as long as the input stays beyond the AC threshold.
This approach is intended to provide predictable receiver timing in the presence of input
waveform ringing, as shown:
S
Single-Ended Voltage Referenced I/O Standard
Single-ended
voltage
VCCIO
referenced I/O
standard
VOH
VIH AC
(
)
VIH(DC)
VREF
VIL(DC)
VIL(AC
)
VOL
VSS
tC
High-speed receiver/transmitter input and output clock period.
The timing difference between the fastest and slowest output edges, including tCO variation
and clock skew, across channels driven by the same PLL. The clock is included in the TCCS
measurement (refer to the Timing Diagram figure under SW in this table).
TCCS (channel-
to-channel-skew)
High-speed I/O block: Duty cycle on high-speed transmitter output clock.
Timing Unit Interval (TUI)
tDUTY
The timing budget allowed for skew, propagation delays, and data sampling window.
T
(TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w)
tFALL
Signal high-to-low transition time (80-20%)
Cycle-to-cycle jitter tolerance on the PLL clock input
Period jitter on the general purpose I/O driven by a PLL
Period jitter on the dedicated clock output driven by a PLL
Signal low-to-high transition time (20-80%)
—
tINCCJ
tOUTPJ_IO
tOUTPJ_DC
tRISE
U
—
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
January 2014 Altera Corporation
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–67
Glossary
Table 1–54. Glossary Table (Part 4 of 4)
Letter
Subject
VCM(DC)
Definitions
DC Common mode input voltage.
VICM
Input Common mode voltage—The common mode of the differential signal at the receiver.
Input differential voltage swing—The difference in voltage between the positive and
complementary conductors of a differential transmission at the receiver.
VID
VDIF(AC)
VDIF(DC)
AC differential input voltage—Minimum AC input differential voltage required for switching.
DC differential input voltage— Minimum DC input differential voltage required for switching.
Voltage input high—The minimum positive voltage applied to the input which is accepted by
the device as a logic high.
VIH
VIH(AC)
VIH(DC)
High-level AC input voltage
High-level DC input voltage
V
Voltage input low—The maximum positive voltage applied to the input which is accepted by
the device as a logic low.
VIL
VIL(AC)
VIL(DC)
Low-level AC input voltage
Low-level DC input voltage
Output Common mode voltage—The common mode of the differential signal at the
transmitter.
VOCM
VOD
Output differential voltage swing—The difference in voltage between the positive and
complementary conductors of a differential transmission at the transmitter.
VSWING
VX
Differential input voltage
Input differential cross point voltage
Output differential cross point voltage
High-speed I/O block: Clock Boost Factor
—
VOX
W
W
X, Y, Z
—
Document Revision History
Table 1–55 lists the revision history for this chapter.
Table 1–55. Document Revision History (Part 1 of 3)
Date
Version
5.7
Changes
January 2014
December 2013
November 2013
November 2013
■ Updated Table 1–42.
5.6
■ Updated Table 1–23 and Table 1–24.
■ Updated Table 1–23 and Table 1–24.
5.5
5.4
■ Updated Table 1–42, Table 1–23, and Table 1–24.
■ Added Table 1–5 and Table 1–40.
■ Updated Table 1–15, Table 1–22, Table 1–23, Table 1–30, Table 1–33, Table 1–35,
July 2012
5.3
5.2
Table 1–36, Table 1–39, Table 1–42 and Table 1–51.
■ Removed “Schmitt Trigger Input” section.
■ Added Figure 1–7.
December 2011
■ Updated Table 1–22 and Table 1–41.
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
1–68
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Glossary
Table 1–55. Document Revision History (Part 2 of 3)
Date
Version
Changes
■ Added military speed grade information.
■ Updated Table 1–1 and Table 1–30.
June 2011
5.1
■ Updated (Note 3) in Table 1–42 and (Note 3) in Table 1–43.
■ Added military speed grade to Table 1–5, Table 1–10, Table 1–11, Table 1–23, Table 1–30,
Table 1–36, and Table 1–51.
■ Updated Table 1–1, Table 1–5, Table 1–6, Table 1–13, Table 1–16, Table 1–23, and
April 2011
5.0
Table 1–24.
March 2011
March 2011
February 2011
4.9
4.8
4.7
■ Updated Table 1–24.
■ Removed (Note 17) in Table 1-24.
■ Added (Note 17) to Table 1–24.
■ Updated Table 1–1, Table 1–5, Table 1–23, Table 1–24, Table 1–30, Table 1–31, Table
1–32, Table 1–34, Table 1–37, Table 1–41, and Table 1–51.
■ Updated the “Recommended Operating Conditions” section.
■ Added the “Schmitt Trigger Input” section.January
■ Minor text edits.
February 2011
4.6
■ Updated Table 1–29.
November 2010
September 2010
4.5
4.4
■ Updated chapter title.
■ Minor text edits.
■ Applied new template.
■ Updated Table 1–1 and Table 1–5.
■ Updated Table 1–7, Table 1–22, Table 1–23, Table 1–33, Table 1–35, Table 1–36, and
Table 1–40.
■ Added Table 1–39.
July 2010
4.3
4.2
■ Changed “PCI Express” to “PCIe” throughout.
■ Minor text edits
■ Updated Table 1–22, Table 1–23, Table 1–30, Table 1–46, and Table 1–49.
■ Added Table 1–31.
March 2010
■ Minor text edits.
■ Updated Table 1–11, Table 1–22, Table 1–23, Table 1–24, Table 1–25, Table 1–26,
Table 1–27, Table 1–29, Table 1–32, Table 1–33, Table 1–34, Table 1–35, Table 1–39,
Table 1–40, Table 1–43, Table 1–46, and Table 1–49.
■ Added Stratix IV GT speed grade note to Table 1–32, Table 1–35, Table 1–39, Table 1–43,
February 2010
4.1
Table 1–44, Table 1–45, and Table 1–46.
■ Added Table 1–28 and Table 1–30.
■ Minor text edits.
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
January 2014 Altera Corporation
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–69
Glossary
Table 1–55. Document Revision History (Part 3 of 3)
Date
Version
Changes
■ Added Table 1–9, Table 1–15, Table 1–38, and Table 1–39.
■ Added Figure 1–5 and Figure 1–6.
■ Added the “Transceiver Datapath PCS Latency” section.
■ Updated the “Electrical Characteristics”, “Operating Conditions”, and “I/O Timing”
sections.
November 2009
4.0
■ All tables updated except Table 1–16, Table 1–24, Table 1–25, Table 1–26, Table 1–27,
Table 1–33, Table 1–34, and Table 1–45.
■ Updated Figure 1–2 and Figure 1–3.
■ Updated Equation 1–1.
■ Deleted Table 1-28, Table 1-29, Table 1-30, Table 1-42, Table 1-43, and Table 1-44.
■ Minor text edits.
■ Added “Preliminary Specifications” to the footer of each page.
■ Updated Table 1–1, Table 1–2, Table 1–7, Table 1–10, Table 1–11, Table 1–12,
Table 1–21, Table 1–22, Table 1–23, Table 1–25, Table 1–37, Table 1–38, Table 1–39,
Table 1–40, and Table 1–44.
June 2009
3.1
3.0
■ Minor text edits.
■ Replaced Table 1–31 and Table 1–37.
■ Updated Table 1–1, Table 1–2, Table 1–5, Table 1–19, Table 1–41, Table 1–44,
Table 1–45, Table 1–49, and Table 1–51.
March 2009
■ Added Table 1–21, Table 1–46, and Table 1–47
■ Added Figure 1–3.
■ Removed “Timing Model”, “Preliminary and Final Timing”, “I/O Timing Measurement
Methodology”, “I/O Default Capacitive Loading”, and “Referenced Documents” sections.
December 2008
November 2008
2.1
2.0
Minor changes.
■ Minor text edits.
■ Updated Table 1–19, Table 1–32, Table 1–34 - Table 1–39.
■ Minor text edits.
■ Updated Table 1–1, Table 1–2, Table 1–4, Table 1–5, and Table 1–26.
■ Removed figures from “Transceiver Performance Specifications” on page 1–10 that are
August 2008
May 2008
1.1
1.0
repeated in the glossary.
■ Minor text edits and an additional note to Table 1–26.
Initial release.
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
1–70
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Glossary
Stratix IV Device Handbook
January 2014 Altera Corporation
Volume 4: Device Datasheet and Addendum
2. Addendum to the Stratix IV Device
Handbook
February 2011
SIV54002-1.5
SIV54002-1.5
This chapter describes changes to the published version of the Stratix IV Device
Handbook. All changes from Revision 1.4 of this chapter are now incorporated in the
main handbook chapters or in AN 612: Decision Feedback Equalization in Stratix IV
Devices.
Adaptive Equalization (AEQ)
f
This AEQ information is now located in the Dynamic Reconfiguration in Stratix IV
Devices chapter.
Decision Feedback Equalization (DFE)
f
For more information about the DFE feature, refer to AN 612: Decision Feedback
Equalization in Stratix IV Devices.
Power-On Reset Circuitry
The Power-On Reset Circuitry information is now located in the Hot Socketing and
Power-On Reset in Stratix IV Devices chapter.
Power-On Reset Specifications
f
The Power-On Reset Specification information is now located in the Hot Socketing and
Power-On Reset in Stratix IV Devices chapter.
© 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
February 2011
Feedback Subscribe
2–2
Chapter 2: Addendum to the Stratix IV Device Handbook
Document Revision History
Table 2–1 lists the revision history for this chapter.
Table 2–1. Document Revision History
Date
Version
Changes
■ Removed the “Decision Feedback Equalization (DFE)” section now that AN 612: Decision
Feedback Equalization in Stratix IV Devices is published.
■ Moved the “Adaptive Equalization (AEQ)” sections to the Dynamic Reconfiguration in
Stratix IV Devices chapter.
February 2011
1.5
■ Moved the “Power-On Reset Circuitry” and “Power-On Reset Specifications” sections to
the Hot Socketing and Power-On Reset in Stratix IV Devices chapter.
■ Minor text edits.
■ Added corrections for the Adaptive Equalization (AEQ) section of the Stratix IV Dynamic
Reconfiguration chapter.
September 2010
April 2010
1.4
1.3
■ Added new information for the Decision Feedback Equalization (DFE) feature.
■ Added corrections for the “Power-On Reset Circuitry” and “Power-On Reset
Specifications” sections to of the Hot Socketing and Power-On Reset in Stratix IV Devices
chapter.
■ Moved the “Power-On Reset Circuitry”, “Power-On Reset Specifications”, “Correct
Power-Up Sequence for Production Devices”, and “Correct Power-Up Sequence for
Production Devices” sections to the Hot Socketing and Power-On Reset in Stratix IV
Devices chapter.
March 2010
1.2
■ Moved the “Power-On Reset Circuit” and “JTAG TMS and TDI Pin Pull-Up Resistor Value
Specification” sections to the Configuration, Design Security, Remote System Upgrades
with Stratix IV Devices chapter.
■ Moved the “Summary of OCT Assignments” section to the I/O Features in Stratix IV
Devices chapter.
■ Added the “Power-On Reset Circuitry”, “Power-On Reset Specifications”, “Correction to
POR Signal Pulse Width Delay Times”, “Correct Power-Up Sequence for Production
Devices”, “Power-On Reset Circuit”, “Summary of OCT Assignments”, and “JTAG TMS
and TDI Pin Pull-Up Resistor Value Specification” sections.
February 2010
1.1
1.0
■ Minor text edits.
■ Stratix IV GX enhanced transceiver data rate specifications in –4 commercial speed grade.
■ Initial release.
November 2009
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
February 2011 Altera Corporation
Additional Information
This chapter provides additional information about the document and Altera.
About this Handbook
This handbook provides comprehensive information about the Altera® Stratix® IV
family of devices.
How to Contact Altera
To locate the most up-to-date information about Altera products, refer to the
following table.
Contact (1)
Technical support
Contact Method
Website
Website
Email
Address
www.altera.com/support
www.altera.com/training
custrain@altera.com
Technical training
Product literature
Website
Email
www.altera.com/literature
nacomp@altera.com
Nontechnical support (general)
(software licensing)
Note to Table:
Email
authorization@altera.com
(1) You can also contact your local Altera sales office or sales representative.
Typographic Conventions
The following table shows the typographic conventions this document uses.
Visual Cue
Meaning
Indicate command names, dialog box titles, dialog box options, and other GUI
labels. For example, Save As dialog box. For GUI elements, capitalization matches
the GUI.
Bold Type with Initial Capital
Letters
Indicates directory names, project names, disk drive names, file names, file name
extensions, software utility names, and GUI labels. For example, \qdesigns
directory, D: drive, and chiptrip.gdf file.
bold type
Italic Type with Initial Capital Letters Indicate document titles. For example, Stratix IV Design Guidelines.
Indicates variables. For example, n + 1.
italic type
Variable names are enclosed in angle brackets (< >). For example, <file name> and
<project name>.pof file.
Indicate keyboard keys and menu names. For example, the Delete key and the
Options menu.
Initial Capital Letters
“Subheading Title”
Quotation marks indicate references to sections in a document and titles of
Quartus II Help topics. For example, “Typographic Conventions.”
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
2–2
Additional Information
Typographic Conventions
Visual Cue
Meaning
Indicates signal, port, register, bit, block, and primitive names. For example, data1
tdi, and input. The suffix denotes an active-low signal. For example, resetn
Indicates command line commands and anything that must be typed exactly as it
appears. For example, c:\qdesigns\tutorial\chiptrip.gdf
,
n
.
Courier type
.
Also indicates sections of an actual file, such as a Report File, references to parts of
files (for example, the AHDL keyword SUBDESIGN), and logic function names (for
example, TRI).
r
An angled arrow instructs you to press the Enter key.
1., 2., 3., and
Numbered steps indicate a list of items when the sequence of the items is important,
such as the steps listed in a procedure.
a., b., c., and so on
■
■
■
Bullets indicate a list of items when the sequence of the items is not important.
The hand points to information that requires special attention.
1
h
The question mark directs you to a software help system with related information.
The feet direct you to another document or website with related information.
The multimedia icon directs you to a related multimedia presentation.
f
m
A caution calls attention to a condition or possible situation that can damage or
destroy the product or your work.
c
A warning calls attention to a condition or possible situation that can cause you
injury.
w
The envelope links to the Email Subscription Management Center page of the Altera
website, where you can sign up to receive update notifications for Altera documents.
Stratix IV Device Handbook
January 2014 Altera Corporation
Volume 4: Device Datasheet and Addendum
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