E28F008BVB120_技术文档

PRODUCT PREVIEW

E

8-MBIT (512K X 16, 1024K X 8)

SmartVoltage BOOT BLOCK

FLASH MEMORY FAMILY

28F800BV-T/B, 28F800CV-T/B, 28F008BV-T/B

28F800CE-T/B, 28F008BE-T/B

Intel SmartVoltage Technology

Extended Cycling Capability

¾

5V or 12V Program/Erase

2.7V, 3.3V or 5V Read Operation

Program Time Reduced 60% at

12V V_PP

¾

100,000 Block Erase Cycles

(Commercial Temperature)

10,000 Block Erase Cycles

(Extended Temperature)

¾

Very High Performance Read

Automated Word/Byte Write and Block

Erase

¾

5V: 70/120 ns Max. Access Time,

30/40 ns Max. Output Enable Time

3V: 120/150 ns Max Access

65 ns Max. Output Enable Time

2.7V: 120 ns Max Access

¾

Industry-Standard Command User

Interface

¾

Status Registers

Erase Suspend Capability

65 ns Max. Output Enable Time

SRAM-Compatible Write Interface

Low Power Consumption

Automatic Power Savings Feature

¾

Max 60 mA Read Current at 5V

¾

1 mA Typical I_CCActive Current in

Static Operation

¾

Max 30 mA Read Current at 2.7–3.6V

x8/x16-Selectable Input/Output Bus

Reset/Deep Power-Down Input

¾

28F800 for High Performance 16- or

32-bit CPUs

¾

0.2 µA I_CCTypical

¾

Provides Reset for Boot Operations

x8-Only Input/Output Architecture

Hardware Data Protection Feature

¾

28F008B for Space-Constrained

8-bit Applications

¾

Erase/Write Lockout during Power

Transitions

Optimized Array Blocking Architecture

Industry-Standard Surface Mount

Packaging

¾

One 16-KB Protected Boot Block

Two 8-KB Parameter Blocks

One 96-KB Main Block

Seven 128-KB Main Blocks

Top or Bottom Boot Locations

¾

40-Lead TSOP

¾

44-Lead PSOP: JEDEC ROM

Compatible

¾

48-Lead TSOP

Absolute Hardware-Protection for Boot

Block

Footprint Upgradeable from 2-Mbit and

4-Mbit Boot Block Flash Memories

Software EEPROM Emulation with

Parameter Blocks

ETOX™ IV Flash Technology

Extended Temperature Operation

¾ –40°C to +85°C

Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any

patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Information

contained herein supersedes previously published specifications on these devices from Intel.

September 1995

Order Number: 290539-002

8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY

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CONTENTS

PAGE

1.0 PRODUCT FAMILY OVERVIEW . 3

3.5 Power Consumption....................... 33

3.5.1 Active Power............................33

3.5.2 Automatic Power Savings........ 33

3.5.3 Standby Power.........................33

3.5.4 Deep Power-Down Mode......... 33

3.6 Power-Up/Down Operation............ 34

3.6.1 RP# Connected to System Reset34

3.6.2 V_CC, V_PPand RP# Transtions... 34

3.7 Power Supply Decoupling.............. 34

1.1 New Features in the

SmartVoltage Products.....................3

1.2 Main Features................................... 4

1.3 Applications ..................................... 7

1.4 Pinouts..............................................8

1.5 Pin Descriptions.............................10

2.0 PRODUCT DESCRIPTION ........... 13

2.1 Memory Organization....................13

2.1.1 Blocking................................... 13

3.0 PRODUCT FAMILY PRINCIPLES

OF OPERATION............................. 12

3.7.1 V_PPTrace on Printed Circuit

Boards ...................................... 35

4.0 ABSOLUTE MAXIMUM RATINGS 36

5.0 COMMERCIAL OPERATING

CONDITIONS ................................. 37

3.1 Bus Operations...............................16

3.2 Read Operations.............................16

3.2.1 Read Array...............................16

3.2.2 Intelligent Identifiers................14

3.3 Write Operations............................19

3.3.1 Command User Interface..........19

3.3.2 Status Register..........................17

3.3.3 Program Mode..........................18

3.3.4 Erase Mode ..............................27

3.4 Boot Block Locking.......................19

5.1 Applying V_CCVoltages .................. 37

5.2 DC Characteristics..........................38

5.3 AC Characteristics..........................32

6.0 EXTENDED OPERATING

CONDITIONS ................................. 57

6.1 Applying V_CCVoltages .................. 57

6.2 DC Characteristics..........................58

6.3 AC Characteristics..........................67

7.0 ADDITIONAL INFORMATION ... 75

3.4.1 V_PP= V_ILfor Complete

7.1 Ordering Information..................... 75

7.2 References...................................... 77

7.3 Revision History............................77

Protection.................................. 28

3.4.2 WP# = V_ILfor Boot Block

Locking..................................... 28

3.4.3 RP# = V_HHor WP# = V_IHfor

Boot Block Unlocking..............29

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PRODUCT PREVIEW

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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY

1.0

PRODUCT FAMILY

OVERVIEW

To upgrade from lower density -BX/BL-

suffix 12V program products, please note

This datasheet contains the specifications

for the two branches of products in the

SmartVoltage 8-Mbit boot block flash

memory family: the -BE/CE suffix

products feature a low V_CCoperating range

of 2.7–3.6V; the -BV/CV suffix products

offer

the following differences and guidelines:

·

WP# pin has replaced DU (Don’t Use)

pin #12 in the 40-lead TSOP package.

In the 44-lead PSOP, DU pin #2 is

replaced with A₁₈(see Figure 1 and

Section 3.4 for details). Connect the

3.0–3.6V operation. Both BE/CE and

BV/CV products also operate at 5V for

high-speed access times. Throughout this

datasheet, the 28F800 refers to all x8/x16

8-Mbit products, while 28F008B refers to

all x8 8-Mbit boot block products (but not

to the 28F008SA FlashFile™ Memory).

Also, the term “2.7V” generally means the

full voltage range 2.7–3.6V. Section 1

provides an overview of the flash memory

family including applications, pinouts and

pin descriptions. Sections 2 and 3 describe

the memory organization and operation for

these products. Finally, Sections 4, 5 and 6

contain the family’s operating

WP# pin to control signal or to V or

CC

GND (in this case, a logic-level signal

can be placed on DU pin #12 for 40-

lead TSOP). See Tables 2 and 9 to see

how the WP# pin works.

·

5V program/erase operation has been

added. If switching V_PPfor write

protection, switch to GND (not 5V) for

complete write protection. To take

advantage of 5V write-capability, allow

for connecting 5V to V and

PP

disconnecting 12V from V line.

PP

·

Enhanced circuits optimize low V

CC

performance, allowing operation down

to V_CC= 2.7V (using the BE/CE

products).

specifications.

To upgrade from lower density

1.1

New Features in the

SmartVoltage boot block products, the

similar pinouts in the 40-lead and 48-lead

TSOP packages provide easy upgrades by

adding extra address lines (see Figures1

and 3). In the 44-lead TSOP, the WP# pin

on the 2-Mbit and 4-Mbit BV parts

becomes A₁₈, removing the capability to

unlock the boot block with a logic-level

signal in this package only. The boot block

can still be unlocked with 12V on RP# (see

Figure 2 and Section 3.4 for details).

SmartVoltage Products

The new 8-Mbit SmartVoltage boot block

flash memory family provides a

convenient density upgrade path from the

2-Mbit and 4-Mbit boot block products.

The 8-Mbit boot block functions similarly

to lower density boot block products in

both command sets and operation,

providing similar pinouts to ease density

upgrades.

3

PRODUCT PREVIEW

8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY

Table 1. SmartVoltage Provides Total Voltage Flexibility

E

Product

Name

Bus

V_CC

V_PP

Width

2.7–3.6V 3.3 ± 0.3V 5V ± 5% 5 ± 10%V 12 ± 5%V

5V ± 10%

28F008BV-

T/B

x8

Ö

28F800BV- x8 or x16

T/B

28F800CV- x8 or x16

T/B

28F008BE-

T/B

x8

Ö

28F800CE- x8 or x16

T/B

4

PRODUCT PREVIEW

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for program and erase operation. Discrete

supply pins allow system designers to use

the optimal voltage levels for their design.

All products (28F800BV/CV, 28F008BV,

28F800CE and 28F008BE) provide

program/erase capability at 5V or 12V. The

28F800BV/CV and 28F008BV allows reads

with V_CCat 3.3 ± 0.3V or 5V, while the

28F800CE and 28F008BE allows reads

with V_CCat 2.7–3.6V or 5V. Since many

designs read from the flash memory a large

8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY

1.2

Main Features

architecture. See Figures4 and 5 for

memory maps. Each block can be

Intel’s SmartVoltage technology is the most

flexible voltage solution in the flash

independently erased and programmed

100,000 times at commercial temperature or

10,000 times at extended temperature.

The boot block is located at either the top

(denoted by -T suffix) or the bottom (-B

suffix) of the address map in order to

accommodate different microprocessor

protocols for boot code location. The

hardware-lockable boot block provides

complete code security for the kernel code

required for system initialization. Locking

and unlocking of the boot block is

controlled by WP# and/or RP# (see Section

3.4 for details).

industry, providing two discrete voltage

supply pins: V_CCfor read operation, and V

PP

percentage of the time, 2.7V V operation

CC

can provide great power savings. If read

performance is an issue, however, 5V V

CC

provides faster read access times. For

program and erase operations, 5V V

PP

operation eliminates the need for in system

voltage converters, while 12V V operation

PP

provides faster program and erase for

situations where 12V is available, such as

manufacturing or designs where 12V is in-

system. For design simplicity, however, just

hook up V_CCand V_PPto the same 5V ± 10%

source.

The 28F800/28F008B boot block flash

memory family is a high-performance,

8-Mbit (8,388,608 bit) flash memory family

organized as either

512 Kwords of 16 bits each (28F800 only)

or

1024 Kbytes of 8 bits each (28F800 and

28F008B).

Separately erasable blocks, including a

hardware-lockable boot block (16,384

bytes), two parameter blocks (8,192 bytes

each) and main blocks (one block of 98,304

bytes and seven blocks of 131,072 bytes)

define the boot block flash family

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The Command User Interface (CUI) serves

as the interface between the microprocessor

or microcontroller and the internal

operation of the boot block flash memory

products. The internal Write State Machine

(WSM) automatically executes the

algorithms and timings necessary for

program and erase operations, including

verifications, thereby unburdening the

microprocessor or microcontroller of these

tasks. The Status Register (SR) indicates the

status of the WSM and whether it

when the flash memory powers-up, it

automatically defaults to the read array

mode, but during a warm system reset,

where power continues uninterrupted to the

system components, the flash memory

could remain in a non-read mode, such as

erase. Consequently, the system Reset

signal should be tied to RP# to reset the

memory to normal read mode upon

activation of the Reset signal (see Section

3.6).

The 28F800 provides both byte-wide or

word-wide input/output, which is

controlled by the BYTE# pin. Please see

Table 2 and Figure 13 for a detailed

description of BYTE# operations,

especially the usage of the DQ₁₅/A_–1pin.

successfully completed the desired program

or erase operation.

Program and erase automation allows

program and erase operations to be

executed using an industry-standard two-

write command sequence to the CUI. Data

writes are performed in word (28F800

family) or byte (28F800 or 28F008B

families) increments. Each byte or word in

the flash memory can be programmed

independently of other memory locations,

unlike erases, which erase all locations

within a block simultaneously.

The 8-Mbit SmartVoltage boot block flash

memory family is also designed with an

Automatic Power Savings (APS) feature

which minimizes system battery current

drain, allowing for very low power designs.

To provide even greater power savings, the

boot block family includes a deep power-

down mode which minimizes power

consumption by turning most of the flash

memory’s circuitry off. This mode is

controlled by the RP# pin and its usage is

discussed in Section 3.5, along with other

power consumption issues.

Additionally, the RP# pin provides

protection against unwanted command

writes due to invalid system bus conditions

that may occur during system reset and

power-up/down sequences. For example,

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PRODUCT PREVIEW

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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY

The 28F800 products are available in the

44-lead PSOP (Plastic Small Outline)

package (a ROM/EPROM-compatible

pinout) and the 48-lead TSOP (Thin Small

Outline, 1.2 mm thick) package as shown in

Figures 2, and 3, respectively. The 28F800

is not available in 56-lead TSOP. The

28F008B products are available in the 40-

lead TSOP package as shown in Figure1.

Refer to the DC Characteristics Table,

Section 5.2 (commercial temperature)

and Section 6.2 (extended temperature),

for complete current and voltage

The 8-Mbit boot block flash memory family

provides full-function, blocked flash

memories suitable for a wide range of

applications. These applications include

ROM-able applications storage, digital

cellular phone program and data storage,

telecommunication boot/firmware, printer

firmware/font storage and various other

embedded applications where program and

data storage are required.

The 8-Mbit flash memory products are also

excellent design solutions for digital

cellular phone and telecommunication

switching applications requiring very low

power consumption, high-performance,

high-density storage capability, modular

software designs, and a small form factor

package. The 8-Mbit’s blocking scheme

allows for easy segmentation of the

embedded code with

specifications. Refer to the AC

Characteristics Table, Section 5.3

(commercial temperature) and Section

6.3 (extended temperature), for read,

write and erase performance

specifications.

1.3

Applications

16 Kbytes of hardware-protected boot code,

eight main blocks of program code and two

parameter blocks of 8 Kbytes each for

frequently updated data storage and

diagnostic messages (e.g., phone numbers,

authorization codes).

Intel’s boot block architecture provides a

flexible solution for the different design

needs of various applications. The

asymmetrically-blocked memory map

allows the integration of several memory

components into a single flash device. The

boot block provides a secure boot PROM;

the parameter blocks can emulate EEPROM

functionality for parameter store with

proper software techniques; and the main

blocks provide code and data storage with

access times fast enough to execute code in

place, decreasing RAM requirements.

The 8-Mbit boot block flash memory family

combines high-density, low-power, high-

performance, cost-effective flash memories

with blocking and hardware protection

capabilities. Their flexibility and versatility

reduce costs throughout the product life

cycle. Flash memory is ideal for just-in-

time production flow, reducing system

inventory and costs, and eliminating

component handling during the production

phase.

When your product is in the end-user’s

hands, and updates or feature enhancements

become necessary, flash memory reduces

the update costs by allowing user-

performed code changes instead of costly

product returns or technician calls.

7

PRODUCT PREVIEW

8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY

1.4 Pinouts

E

The 28F008B 40-lead TSOP pinout for

Intel’s SmartVoltage Boot Block

space-constrained designs is shown in

Figure 1. For designs that require x16

operation but have space concerns, refer to

the 48-lead pinout in Figure3. The 28F800

44-lead PSOP pinout follows the industry-

standard ROM/EPROM pinout, as shown in

Figure 2.

architecture provides pinout upgrade paths

to the 8-Mbit density. 8-Mbit pinouts are

given on the chip illustration in the center,

with 2-Mbit and 4-Mbit pinouts going

outward from the center for reference.

28F004B 28F002B

28F002B 28F004B

A

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

A

17

GND

NC

16

15

14

16

15

14

40

39

38

37

36

16

15

14

13

12

11

17

GND

NC

A

GND

NC

A

DQ

13

12

11

13

12

11

NC

19

10

A

10

7

6

5

4

10

DQ

7

DQ

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

7

A

9

8

9

8

9

8

DQ

6

DQ

6

5

4

28F008B

40-LEAD TSOP

Boot Block

10 mmx20 mm

TOP VIEW

DQ

5

WE#

RP#

WE#

RP#

WE#

RP#

DQ

4

V

CC

V

PP

V

PP

V

CC

V

CC

WP#

A

7

A

5

A

3

A

1

WP#

NC

A

7

A

5

A

3

A

WP#

NC

DQ

OE#

GND

CE#

NC

DQ

A

18

DQ

18

7

3

2

1

0

3

2

1

0

3

A

DQ

2

A

6

DQ

1

A

5

DQ

0

A

4

OE#

GND

CE#

OE#

GND

CE#

A

3

A

2

A

1

A

1

A

0

0539_01

NOTE:

1. Pin 12 is DU for -BX/BL 12V V_PPVersions.

2. The 28F008B pinout is for the 8-Mbit boot block and not for the 28F008SA FlashFile™ Memory.

Figure 1. The 40-Lead TSOP Offers the Smallest Form Factor for Space-Constrained

Applications

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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY

28F400

28F200

28F400

RP#

WE#

A ₈

RP#

WE#

A ₈

RP#

WE#

A ₈

V_PP

A ₁₈

A ₁₇

A ₇

1

2

3

4

44

43

42

41

WP#

A ₁₇

NC

A ₇

A ₉

A ₇

A ₆

A ₅

A ₄

A ₃

A ₂

A ₁

A ₁₀

A ₁₁

A ₁₂

A ₁₃

A ₁₄

A ₁₅

A ₁₆

A ₁₀

A ₁₁

A ₁₂

A ₁₃

A ₁₄

A ₁₅

A ₁₆

A ₁₀

A ₁₁

A ₁₂

A ₁₃

A ₁₄

A ₁₅

A ₁₆

A ₆

A ₅

A ₄

A ₃

A ₂

A ₆

A ₅

A ₄

A ₃

A ₂

5

6

7

40

39

38

37

36

35

34

33

32

31

30

29

PA28F800

Boot Block

44-LEAD PSOP

0.525" x 1.110"

8

9

A ₁

10

11

12

13

14

15

16

A ₀

TOP VIEW

BYTE#

GND

BYTE#

CE#

GND

OE#

CE#

GND

OE#

CE#

GND

OE#

GND

DQ₁₅/A_-1

DQ ₇

DQ ₁₄

DQ ₆

DQ ₁₃

DQ ₅

DQ ₁₂

DQ ₄

V_CC

GND

DQ₁₅/A_-1

DQ ₇

DQ ₁₄

DQ ₆

DQ ₁₃

DQ ₅

DQ ₁₂

DQ ₄

V_CC

DQ₁₅/A_-1

DQ ₇

DQ ₁₄

DQ ₀

DQ ₈

DQ ₁

DQ ₉

DQ ₂

DQ ₁₀

DQ ₃

DQ ₁₁

DQ ₀

DQ ₈

DQ ₁

DQ ₉

DQ ₂

DQ ₁₀

DQ ₃

DQ ₁₁

DQ ₀

DQ ₈

DQ ₁

DQ ₉

DQ ₂

DQ ₁₀

DQ ₃

DQ ₁₁

17

28

DQ ₆

18

19

20

21

22

27

26

25

24

23

DQ ₁₃

DQ ₅

DQ ₁₂

DQ ₄

V_CC

0539_02

NOTE:

Pin 2 is DU for BX/BL 12V V_PPVersions, but for the 8-Mbit device, pin 2 has been changed to A₁₈(WP# on 2/4 Mbit). Designs

planning on upgrading to the 8-Mbit density from the 2/4-Mbit density in this package should design pin 2 to control WP# functionality

at the 2/4-Mbit level and allow for pin 2 to control A after upgrading to the 8-Mbit density.

18

Figure 2. The 44-Lead PSOP Offers a Convenient Upgrade from JEDEC ROM

Standards

28F400

28F200

A

NC

WE#

RP#

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

16

15

14

13

12

15

14

13

12

11

16

15

A

BYTE#

GND

BYTE#

GND

BYTE#

GND

DQ /A

14

A

13

12

11

/A

-1

DQ

-1

15

7

14

6

15

DQ

-1

15

11

DQ

7

14

6

DQ

14

DQ

10

9

10

9

8

10

A

9

A

8

A

DQ

6

A

8

DQ

13

NC

DQ

5

12

4

5

12

4

28F800C

Boot Block

DQ

12

WE#

RP#

WE#

RP#

DQ

V

DQ

4

V

48-LEAD TSOP

12 mm x 20 mm

CC

V

WP#

NC

V

PP

DQ

11

PP

11

3

10

2

9

1

11

3

10

2

9

1

8

WP#

NC

WP#

NC

DQ

3

DQ

OE#

GND

CE#

DQ

OE#

GND

CE#

DQ

10

TOP VIEW

A

NC

A

DQ

2

18

17

DQ

9

17

A

7

A

6

A

DQ

1

7

A

6

A

6

DQ

8

0

A

5

A

5

A

5

DQ

0

A

4

A

OE#

GND

CE#

4

3

2

4

3

2

A

3

A

23

24

A

2

A

1

A

0

1

0

0539_03

Figure 3. The 48-Lead TSOP Offers the Smallest Form Factor for x16 Operation

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1.5

Pin Descriptions

Table 2. 28F800/008B Pin Descriptions

Name and Function

Symbol

Type

ADDRESS INPUTS for memory addresses. Addresses are

internally latched during a write cycle.The 28F800 only has

A₀–A₁₈pins, while

A₀–A₁₉

INPUT

the 28F008B has A₀–A₁₉.

A₉

INPUT

ADDRESS INPUT: When A₉is at V_HHthe signature mode is

accessed. During this mode, A decodes between the

0

manufacturer and device IDs. When BYTE# is at a logic low,

only the lower byte of the signatures are read. DQ /A_–1is a

15

don’t care in the signature mode when BYTE# is low.

DQ₀–

DQ₇

INPUT/OUT

PUT

DATA INPUTS/OUTPUTS: Inputs array data on the second

CE# and WE# cycle during a Program command. Inputs

commands to the Command User Interface when CE# and

WE# are active. Data is internally latched during the Write

cycle. Outputs array, Intelligent Identifier and Status Register

data. The data pins float to tri-state when the chip is de-

selected or the outputs are disabled.

DQ₈–

DQ₁₅

INPUT/OUT

PUT

DATA INPUTS/OUTPUTS: Inputs array data on the second

CE# and WE# cycle during a Program command. Data is

internally latched during the Write cycle. Outputs array data.

The data pins float to tri-state when the chip is de-selected or

the outputs are disabled as in the byte-wide mode (BYTE# =

“0”). In the byte-wide mode DQ /A_–1becomes the lowest

15

order address for data output on DQ–DQ₇. The 28F008B

0

does not include these DQ₈–DQ₁₅pins.

CE#

INPUT

CHIP ENABLE: Activates the device’s control logic, input

buffers, decoders and sense amplifiers. CE# is active low.

CE# high de-selects the memory device and reduces power

consumption to standby levels. If CE# and RP# are high, but

not at a CMOS high level, the standby current will increase

due to current flow through the CE# and RP# input stages.

OE#

INPUT

OUTPUT ENABLE: Enables the device’s outputs through

the data buffers during a read cycle. OE# is active low.

WE#

WRITE ENABLE: Controls writes to the Command Register

and array blocks. WE# is active low. Addresses and data are

latched on the rising edge of the WE# pulse.

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RP#

INPUT

RESET/DEEP POWER-DOWN: Uses three voltage levels

(V_IL, V_IH, and V_HH) to control two different functions:

reset/deep power-down mode and boot block unlocking. It is

backwards-compatible with the BX/BL/BV products.

When RP# is at logic low, the device is in reset/deep

power-down mode, which puts the outputs at High-Z, resets

the Write State Machine, and draws minimum current.

When RP# is at logic high, the device is in standard

operation. When RP# transitions from logic-low to logic-

high, the device defaults to the read array mode.

When RP# is at V_HH, the boot block is unlocked and can be

programmed or erased. This overrides any control from the

WP# input.

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Table 2. 28F800/008B Pin Descriptions (Continued)

Symbol

Type

Name and Function

WP#

INPUT

WRITE PROTECT: Provides a method for unlocking the

boot block in a system without a 12V supply.

When WP# is at logic low, the boot block is locked ,

preventing program and erase operations to the boot block. If

a program or erase operation is attempted on the boot block

when WP# is low, the corresponding status bit (bit 4 for

program, bit 5 for erase) will be set in the Status Register to

indicate the operation failed.

When WP# is at logic high, the boot block is unlocked and

can be programmed or erased.

NOTE: This feature is overridden and the boot block

unlocked when RP# is at V . This pin is not available on the

HH

44-lead PSOP package. See Section 3.4 for details on write

protection.

BYTE#

INPUT

BYTE# ENABLE: Not available on 28F008B. Controls

whether the device operates in the byte-wide mode (x8) or

the word-wide mode (x16). BYTE# pin must be controlled at

CMOS levels to meet the CMOS current specification in the

standby mode.

When BYTE# is at logic low, the byte-wide mode is

enabled, where data is read and programmed on DQ–DQ₇

0

and DQ₁₅/A_–1becomes the lowest order address that decodes

between the upper and lower byte. DQ–DQ₁₄are tri-stated

8

during the byte-wide mode.

When BYTE# is at logic high, the word-wide mode is

enabled, where data is read and programmed on DQ–DQ₁₅.

0

V_CC

V_PP

DEVICE POWER SUPPLY: 5.0V ± 10%, 3.3V ± 0.3V,

2.7V–3.6V

PROGRAM/ERASE POWER SUPPLY: For erasing

memory array blocks or programming data in each block, a

voltage either of 5V ± 10% or 12V ± 5% must be applied to

this pin. When V_PP< V_PPLKall blocks are locked and

protected against Program and Erase commands.

GND

GROUND: For all internal circuitry.

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NC

NO CONNECT: Pin may be driven or left floating.

2.0

PRODUCT DESCRIPTION

2.1.1.2

Parameter Blocks - 2 x 8 KB

The boot block architecture includes

parameter blocks to facilitate storage of

frequently updated small parameters that

would normally require an EEPROM. By

using software techniques, the byte-rewrite

functionality of EEPROMs can be

emulated. These techniques are detailed in

Intel’s AP-604,

2.1

Memory Organization

2.1.1

BLOCKING

This product family features an

asymmetrically- blocked architecture

providing system memory integration. Each

erase block can be erased independently of

the others up to 100,000 times for

commercial temperature or up to 10,000

times for extended temperature. The block

sizes have been chosen to optimize their

functionality for common applications of

nonvolatile storage. The combination of

block sizes in the boot block architecture

allow the integration of several memories

into a single chip. For the address locations

of the blocks, see the memory maps in

Figures 4 and 5.

2.1.1.1

Boot Block - 1 x 16 KB

The boot block is intended to replace a

dedicated boot PROM in a microprocessor

or microcontroller-based system. The 16-

Kbyte (16,384 bytes) boot block is located

at either the top (denoted by -T suffix) or

the bottom (-B suffix) of the address map to

accommodate different microprocessor

protocols for boot code location. This boot

block features hardware controllable write-

protection to protect the crucial

microprocessor boot code from accidental

modification. The protection of the boot

block is controlled using a combination of

the V_PP, RP#, and WP# pins, as is detailed

in Section 3.4.

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2.1.1.3

Main Blocks - 1 x 96 KB + 7 x

128 KB

“Using Intel’s Boot Block Flash Memory

Parameter Blocks to Replace EEPROM.”

Each boot block component contains two

parameter blocks of

After the allocation of address space to the

boot and parameter blocks, the remainder is

divided into main blocks for data or code

storage. Each 8-Mbit device contains one

96-Kbyte (98,304 byte) block and seven

128-Kbyte (131,072 byte) blocks. See the

memory maps for each device for more

information.

8 Kbytes (8,192 bytes) each. The parameter

blocks are not write-protectable.

28F800-B

28F800-T

7FFFFH

16-Kbyte BOOT BLOCK

128-Kbyte MAIN BLOCK

7E000H

7DFFFH

7D000H

7CFFFH

7C000H

7BFFFH

8-Kbyte PARAMETER BLOCK

70000H

6FFFFH

8-Kbyte PARAMETER BLOCK

128-Kbyte MAIN BLOCK

60000H

5FFFFH

96-Kbyte MAIN BLOCK

70000H

6FFFFH

128-Kbyte MAIN BLOCK

50000H

4FFFFH

128-Kbyte MAIN BLOCK

60000H

5FFFFH

128-Kbyte MAIN BLOCK

40000H

3FFFFH

128-Kbyte MAIN BLOCK

50000H

4FFFFH

128-Kbyte MAIN BLOCK

30000H

2FFFFH

128-Kbyte MAIN BLOCK

40000H

3FFFFH

128-Kbyte MAIN BLOCK

20000H

1FFFFH

128-Kbyte MAIN BLOCK

30000H

2FFFFH

128-Kbyte MAIN BLOCK

10000H

0FFFFH

128-Kbyte MAIN BLOCK

20000H

1FFFFH

96-Kbyte MAIN BLOCK

04000H

03FFFH

03000H

02FFFH

128-Kbyte MAIN BLOCK

8-Kbyte PARAMETER BLOCK

10000H

0FFFFH

8-Kbyte PARAMETER BLOCK

02000H

01FFFH

128-Kbyte MAIN BLOCK

16-Kbyte BOOT BLOCK

00000H

0539_04

NOTE:

In x8 operation, the least significant system address should be connected to A. Memory maps are shown for x16 operation.

–1

Figure 4. Word-Wide x16-Mode Memory Maps

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28F800-T

28F800-B

FFFFFH

16-Kbyte BOOT BLOCK

128-Kbyte MAIN BLOCK

FC000H

FBFFFH

FA000H

F9FFFH

E0000H

DFFFFH

8-Kbyte PARAMETER BLOCK

128-Kbyte MAIN BLOCK

F8000H

F7FFFH

C0000H

BFFFFH

96-Kbyte MAIN BLOCK

128-Kbyte MAIN BLOCK

E0000H

DFFFFH

A0000H

9FFFFH

C0000H

BFFFFH

80000H

7FFFFH

128-Kbyte MAIN BLOCK

A0000H

9FFFFH

60000H

5FFFFH

80000H

7FFFFH

40000H

3FFFFH

60000H

5FFFFH

128-Kbyte MAIN BLOCK

96-Kbyte MAIN BLOCK

20000H

1FFFFH

40000H

3FFFFH

08000H

07FFFH

06000H

05FFFH

04000H

03FFFH

8-Kbyte PARAMETER BLOCK

20000H

1FFFFH

16-Kbyte BOOT BLOCK

00000H

0539_05

NOTE:

These memory maps apply to the 28F008B or the 28F800 (in x8 mode).

Figure 5. Byte-Wide x8-Mode Memory Maps

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3.0

PRODUCT FAMILY

3.1

Bus Operations

PRINCIPLES OF OPERATION

Flash memory reads, erases and writes in-

system via the local CPU. All bus cycles to

or from the flash memory conform to

standard microprocessor bus cycles. These

bus operations are summarized in Tables 3

and 4.

Flash memory combines EPROM

functionality with in-circuit electrical write

and erase. The boot block flash family

utilizes a Command User Interface (CUI)

and automated algorithms to simplify write

and erase operations. The CUI allows for

100% TTL-level control inputs, fixed power

supplies during erasure and programming,

and maximum EPROM compatibility.

When V_PP< V_PPLK, the device will only

successfully execute the following

3.2

Read Operations

READ ARRAY

3.2.1

When RP# transitions from V (reset) to

IL

V_IH, the device will be in the read array

mode and will respond to the read control

inputs (CE#, address inputs, and OE#)

without any commands being written to the

CUI.

When the device is in the read array mode,

five control signals must be controlled to

obtain data at the outputs.

commands: Read Array, Read Status

Register, Clear Status Register and

intelligent identifier mode. The device

provides standard EPROM read, standby

and output disable operations. Manufacturer

identification and device identification data

can be accessed through the CUI or through

the standard EPROM A high voltage

9

access (V_ID) for PROM programming

equipment.

The same EPROM read, standby and output

disable functions are available when 5V or

·

WE# must be logic high (V )

IH

CE# must be logic low (V )

IL

OE must be logic low (V )

IL

12V is applied to the V pin. In addition,

PP

RP# must be logic high (V )

IH

5V or 12V on V_PPallows write and erase of

the device. All functions associated with

altering memory contents: Program and

Erase, Intelligent Identifier Read, and Read

Status are accessed via the CUI.

The internal Write State Machine (WSM)

completely automates program and erase,

beginning operation signaled by the CUI

and reporting status through the Status

Register. The CUI handles the WE#

interface to the data and address latches, as

well as system status requests during WSM

operation.

BYTE# must be logic high or logic low.

In addition, the address of the desired

location must be applied to the address

pins. Refer to Figures12 and 13 for the

exact sequence and timing of these signals.

If the device is not in read array mode, as

would be the case after a program or erase

operation, the Read Mode command (FFH)

must be written to the CUI before reads can

take place.

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Table 3. Bus Operations for Word-Wide Mode (BYTE# = V _IH

)

Mode

Note RP# CE# OE# WE# A₉

A₀

V_PP

DQ_0–15

s

Read

1,2,3 V_IH

V_IH

V_IL

V_IH

X

V_IL

V_IH

X

V_IH

X

D_OUT

Output Disable

High Z

Standby

V_IH

Deep Power-

Down

9

4

V_IL

V_IH

X

Intelligent

Identifier (Mfr.)

V_IL

V_IH

V_ID

V_IL

V_IH

X

0089 H

Intelligent

Identifier

(Device)

4,5

See

Table 5

Write

6,7,8 V_IH

V_IL

V_IH

V_IL

X

D_IN

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Table 4. Bus Operations for Byte-Wide Mode (BYTE# = V _IL)

E

Mode

Note RP# CE# OE WE

A₉

A₀

A_–1V_PPDQ_0–7DQ_8–

s

#

14

Read

1,2,3 V_IHV_ILV_ILV_IH

X

D_OUTHigh

Z

Output

Disable

V_IHV_ILV_IHV_IH

X

High High

Z

Standby

V_IHV_IH

V_IL

X

High High

Z

Deep

Power-

Down

9

4

X

High High

Z

Intelligent

Identifier

(Mfr.)

V_IHV_ILV_ILV_IHV_IDV_IL

X

89H

High

Z

Intelligent

Identifier

(Device)

4,5

V_IHV_ILV_ILV_IHV_IDV_IH

See

Table

6

High

Z

Write

6,7,8 V_IHV_ILV_IHV_IL

X

D_IN

High

Z

NOTES:

1. Refer to DC Characteristics.

2. X can be V_IL, V_IHfor control pins and addresses, V_PPLKor V_PPHfor V_PP

.

3. See DC Characteristics for V_PPLK, V_PPH1, V_PPH2, V_HH, V_IDvoltages

4. Manufacturer and device codes may also be accessed via a CUI write sequence, A–A₁₈= X, A₁–A₁₉= X.

1

5. See Table 5 for device IDs.

6. Refer to Table7 for valid D_INduring a write operation.

7. Command writes for Block Erase or Word/Byte Write are only executed when V = V_PPH1 or V_PPH2.

PP

8. To write or erase the boot block, hold RP# at V_HHor WP# at V_IH. See Section 3.4.

9. RP# must be at GND± 0.2V to meet the maximum deep power-down current specified.

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3.2.2

INTELLIGENT IDENTIFIERS

3.3

Write Operations

To read the manufacturer and device codes,

the device must be in intelligent identifier

read mode, which can be reached using two

methods: by writing the intelligent identifier

3.3.1

COMMAND USER

INTERFACE (CUI)

The Command User Interface (CUI) is the

interface between the microprocessor and

the internal chip controller. Commands are

written to the CUI using standard

command (90H) or by taking the A pin to

9

V_ID. Once in intelligent identifier read

mode, A₀= 0 outputs the manufacturer’s

microprocessor write timings. The available

commands are Read Array, Read Intelligent

Identifier, Read Status Register, Clear

Status Register, Erase and Program

(summarized in Tables 6 and 7). The three

read modes are read array, intelligent

identifier read, and Status Register read. For

Program or Erase commands, the CUI

informs the Write State Machine (WSM)

that a write or erase has been requested.

During the execution of a Program

identification code and A = 1 outputs the

0

device code. In byte-wide mode, only the

lower byte of the above signatures is read

(DQ₁₅/A_–1is a “don’t care” in this mode).

See Table 5 for product signatures. To

return to read array mode, write a Read

Array command (FFH).

Table 5. Intelligent Identifier Table

Produc Mfr.

ID

Device ID

t

command, the WSM will control the

programming sequences and the CUI will

only respond to status reads. During an

erase cycle, the CUI willrespond to status

reads and erase suspend. After the WSM

has completed its task, it will set the WSM

Status bit to a “1” (ready), which indicates

that the CUI can respond to its full

-T

-B

(Top

Boot)

(Bottom

Boot)

28F800 0089

H

889C H

889D H

28F008 89 H

B

9C H

9D H

command set. Note that after the WSM has

returned control to the CUI, the CUI will

stay in the current command state until it

receives another command.

3.3.1.1

Command Function

Description

Device operations are selected by writing

specific commands into the CUI. Tables6

and 7 define the available commands.

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Table 6. Command Codes and Descriptions

E

Code Device Mode

Description

00

Invalid/

Reserved

Unassigned commands that should not be used. Intel reserves the

right to redefine these codes for future functions.

FF Read Array/ Places the device in read array mode, so that array data will be

Program or output on the data pins. This command can also be used to cancel

Erase Abort erase and program sequences after their set-up commands have been

issued. To cancel after issuing an Erase Set-Up command, issue this

command, which will reset to read array mode. To cancel a program

operation after issuing a Program Set-Up command, issue two Read

Array commands in sequence to reset to read array mode. If a

program or erase operation has already been initiated to the WSM

this command can not cancel that operation in progress.

40

Program

Set-Up

Sets the CUI into a state such that the next write will load the

Address and Data registers. After this command is executed, the

outputs default to the Status Register. Atwo Read Array command

sequence (FFH) is required to reset to Read Array after the Program

Set-Up command.

The second write after the Program Set-Up command will latch

addresses and data, initiating the WSM to begin execution of the

program algorithm. The device outputs Status Register data when

OE# is enabled. A Read Array command is required after

programming, to read array data. See Section 3.3.3.

10

20

Alternate

Program Set-

Up

(See 40H/Program Set-Up)

Erase

Set-Up

Prepares the CUI for the Erase Confirm command. If the next

command is not an Erase Confirm command, then the CUI will set

both the Program Status and Erase Status bits of the Status Register

to a “1,” place the device into the read Status Register state, and

wait for another command. See Section 3.3.4.

D0

Erase

Resume/

Erase

If the previous command was an Erase Set-Up command, then the

CUI will close the address and data latches, and begin erasing the

block indicated on the address pins. During erase, the device will

respond only to the Read Status Register and Erase Suspend

commands and will output Status Register data when OE# is

toggled low. Status Register data can be updated by toggling either

Confirm

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Table 6. Command Codes and Descriptions

Description

Code Device Mode

OE# or CE# low.

B0

Erase

Valid only while an erase operation is in progress and will be

ignored in any other circumstance. Issuing this command will begin

to suspend erase operation. The Status Register will indicate when

the device reaches erase suspend mode. In this mode, the CUI will

respond only to the Read Array, Read Status Register, and Erase

Resume commands and the WSM will also set the WSM Status bit

to a “1” (ready). The WSM will continue to idle in the SUSPEND

state, regardless of the state of all input control pins except RP#,

which will immediately shut down the WSM and the remainder of

the chip, if it is made active. During a suspend operation, the data

and address latches will remain closed, but the address pads are able

to drive the address into the read path. See Section 3.3.4.1.

Suspend

70

Read Status Puts the device into the read Status Register mode, so that reading

Register

the device will output the contents of the Status Register, regardless

of the address presented to the device. The device automatically

enters this mode after program or erase has completed. This is one

of the two commands that is executable while the WSM is

operating. See Section 3.3.2.

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Table 6. Command Codes and Descriptions (Continued)

Code Device Mode

Description

50 Clear Status The WSM can only set the Program Status and Erase Status bits in

Register

the Status Register to “1,” it cannot clear them to “0.”

The Status Register operates in this fashion for two reasons. The

first is to give the host CPU the flexibility to read the status bits at

any time. Second, when programming a string of bytes, a single

Status Register query after programming the string may be more

efficient, since it will return the accumulated error status of the

entire string. See Section 3.3.2.1.

90

Intelligent Puts the device into the intelligent identifier read mode, so that

Identifier

reading the device will output the manufacturer and device codes.

(A₀= 0 for manufacturer,

A₀= 1 for device, all other address inputs are ignored). See Section

3.2.2.

Table 7. Command Bus Definitions

First Bus Cycle

Note Oper Addr Data

Second Bus Cycle

Command

Oper

Addr

Data

Read Array

8

1

Write

X

FFH

90H

70H

50H

40H

10H

Intelligent Identifier

Read Status Register

Clear Status Register

Word/Byte Write

Read

IA

X

IID

2,4

3

X

SRD

X

WA

Write

WA

WD

Alternate Word/Byte

Write

6,7

Block Erase/Confirm

6,7

5

Write

BA

X

20H

B0H

Write

BA

X

D0H

Erase Suspend/Resume

ADDRESS

DATA

BA= Block Address

IA= Identifier Address

WA= Write Address

X= Don’t Care

SRD= Status Register Data

IID= Identifier Data

WD= Write Data

NOTES:

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1. Bus operations are defined in Tables3 and 4.

2. IA = Identifier Address: A = 0 for manufacturer code, A = 1 for device code.

0

3. SRD - Data read from Status Register.

4. IID = Intelligent Identifier Data. Following the Intelligent Identifier command, two read operations access manufacturer and device

codes.

5. BA = Address within the block being erased.

6. WA = Address to be written. WD = Data to be written at location WD.

7. Either 40H or 10H commands is valid.

8. When writing commands to the device, the upper data bus [DQ–DQ₁₅] = X (28F800 only) which is either V_ILor V_IH, to minimize

8

current draw.

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Table 8. Status Register Bit Definition

E

WSMS

7

ESS

6

ES

5

DWS

4

VPPS

3

R

2

R

1

R

0

NOTES:

SR.7 WRITE STATE MACHINE

STATUS

Check Write State Machine bit first to

determine Word/Byte program or Block

Erase completion, before checking

Program or Erase Status bits.

1 = Ready

0 = Busy

(WSMS)

SR.6 = ERASE-SUSPEND STATUS

(ESS)

When Erase Suspend is issued, WSM

halts execution and sets both WSMS and

ESS bits to “1.” ESS bit remains set to “1”

until an Erase Resume command is issued.

1 = Erase Suspended

0 = Erase In Progress/Completed

SR.5 = ERASE STATUS (ES)

1 = Error In Block Erasure

0 = Successful Block Erase

When this bit is set to “1,” WSM has

applied the max number of erase pulses to

the block and is still unable to verify

successful block erasure.

SR.4 = PROGRAM STATUS (DWS)

1 = Error in Byte/Word Program

0 = Successful Byte/Word Program

When this bit is set to “1,” WSM has

attempted but failed to program a byte or

word.

SR.3 = V_PPSTATUS (VPPS)

1 = V_PPLow Detect, Operation

Abort

The V_PPStatus bit does not provide

continuous indication of V level. The

PP

WSM interrogates V_PPlevel only after the

Byte Write or Erase command sequences

have been entered, and informs the system

0 = V_PPOK

if V_PPhas not been switched on. The V

PP

Status bit is not guaranteed to report

accurate feedback between V_PPLKand

V_PPH

.

SR.2-SR.0 = RESERVED FOR FUTURE

ENHANCEMENTS (R)

These bits are reserved for future use and

should be masked out when polling the

Status Register.

Status (70H) command to the CUI. This

causes all subsequent read operations to

output data from the Status Register until

another command is written to the CUI. To

return to reading from the array, issue a

Read Array (FFH) command.

3.3.2

STATUS REGISTER

The device Status Register indicates when a

program or erase operation is complete, and

the success or failure of that operation. To

read the Status Register write the Read

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The Status Register bits are output on DQ–

0

DQ₇, in both byte-wide (x8) or word-wide

(x16) mode. In the word-wide mode the

upper byte, DQ₈–DQ₁₅, outputs 00H during

a Read Status command. In the byte-wide

mode, DQ₈–DQ₁₄are tri-stated and DQ /A_–

15

₁retains the low order address function.

Important: The contents of the Status

Register are latched on the falling edge of

OE# or CE#, whichever occurs last in the

read cycle. This prevents possible bus

errors which might occur if Status Register

contents change while being read. CE# or

OE# must be toggled with each subsequent

status read, or the Status Register will not

indicate completion of a program or erase

operation.

When the WSM is active, the SR.7 register

will indicate the status of the WSM, and

will also hold the bits indicating whether or

not the WSM was successful in performing

the desired operation.

3.3.2.1

Clearing the Status Register

The WSM sets status bits 3 through 7 to

“1,” and clears bits 6 and 7 to “0,” but

cannot clear status bits 3 through 5 to “0.”

Bits 3 through 5 can only be

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cleared by the controlling CPU through the

use of the Clear Status Register (50H)

command, because these bits indicate

various error conditions. By allowing the

system software to control the resetting of

these bits, several operations may be

performed (such as cumulatively

When programming is complete, the

Program Status bits should be checked. If

the programming operation was

unsuccessful, bit 4 of the Status Register is

set to a “1” to indicate a Program Failure. If

bit 3 is set to a “1,” then V was not within

PP

acceptable limits, and the WSM did not

execute the programming sequence.

programming several bytes or erasing

multiple blocks in sequence) before reading

the Status Register to determine if an error

occurred during that series. Clear the Status

Register before beginning another

command or sequence. Note, again, that a

Read Array command must be issued

before data can be read from the memory or

intelligent identifier.

3.3.3

PROGRAM MODE

Programming is executed using a two-write

sequence. The Program Setup command is

written to the CUI followed by a second

write which specifies the address and data

to be programmed. The WSM will execute

a sequence of internally timed events to:

1. Program the desired bits of the

addressed memory word or byte.

2. Verify that the desired bits are

sufficiently programmed.

Programming of the memory results in

specific bits within a byte or word being

changed to a “0.”

If the user attempts to program “1”s, there

will be no change of the memory cell

content and no error occurs.

The Status Register indicates programming

status: while the program sequence is

executing, bit 7 of the Status Register is a

“0.” The Status Register can be polled by

toggling either CE# or OE#. While

programming, the only valid command is

Read Status Register.

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The Status Register should be cleared

before attempting the next operation. Any

CUI instruction can follow after

Clear the Status Register before attempting

the next operation. Any CUI instruction can

follow after erasure is completed; however,

reads from the Memory Array, Status

Register, or Intelligent Identifier cannot be

accomplished until the CUI is given the

Read Array command.

programming is completed; however, reads

from the Memory Array or Intelligent

Identifier cannot be accomplished until the

CUI is given the appropriate command.

3.3.4

ERASE MODE

To erase a block, write the Erase Set-Up

and Erase Confirm commands to the CUI,

along with the addresses identifying the

block to be erased. These addresses are

latched internally when the Erase Confirm

command is issued. Block erasure results in

all bits within the block being set to “1.”

Only one block can be erased at a time.

The WSM will execute a sequence of

internally timed events to:

1. Program all bits within the block to “0.”

2. Verify that all bits within the block are

sufficiently programmed to “0.”

3. Erase all bits within the block to “1.”

4. Verify that all bits within the block are

sufficiently erased.

While the erase sequence is executing, bit 7

of the Status Register is a “0.”

When the Status Register indicates that

erasure is complete, check the Erase Status

bit to verify that the erase operation was

successful. If the Erase operation was

unsuccessful, bit 5 of the Status Register

will be set to a “1,” indicating an Erase

Failure. If V_PPwas not within acceptable

limits after the Erase Confirm command is

issued, the WSM will not execute an erase

sequence; instead, bit 5 of the Status

Register is set to a “1” to indicate an Erase

Failure, and bit 3 is set to a “1” to identify

that V_PPsupply voltage was not within

acceptable limits.

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PP

3.3.4.1

Suspending and Resuming

Erase

3.4.1

V_PP= V_ILFOR COMPLETE

PROTECTION

Since an erase operation requires on the

order of seconds to complete, an Erase

Suspend command is provided to allow

erase-sequence interruption in order to read

data from another block of the memory.

Once the erase sequence is started, writing

the Erase Suspend command to the CUI

requests that the WSM pause the erase

sequence at a predetermined point in the

erase algorithm. The Status Register will

indicate if/when the erase operation has

been suspended.

For complete write protection of all blocks

in the flash device, the V programming

voltage can be held low. When V is below

V_PPLK, any program or erase operation will

result in a error in the Status Register.

PP

At this point, a Read Array command can

be written to the CUI in order to read data

from blocks other than that which is being

suspended. The only other valid command

at this time is the Erase Resume command

or Read Status Register command.

During erase suspend mode, the chip can go

into a pseudo-standby mode by taking CE#

to V_IH, which reduces active current draw.

To resume the erase operation, enable the

chip by taking CE# to V , then issuing the

IL

Erase Resume command, which continues

the erase sequence to completion. As with

the end of a standard erase operation, the

Status Register must be read, cleared, and

the next instruction issued in order to

continue.

3.4

Boot Block Locking

The boot block family architecture features

a hardware-lockable boot block so that the

kernel code for the system can be kept

secure while the parameter and main blocks

are programmed and erased independently

as necessary. Only the boot block can be

locked independently from the other blocks.

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WP# pin is not available on the 44-lead

PSOP package, the boot block cannot be

unlocked with a logic-level signal on that

package. Instead, RP# must be taken to

V_HH.

3.4.2

WP# = V_ILFOR BOOT BLOCK

LOCKING

When WP# = V , the boot block is locked

IL

and any program or erase operation to the

boot block will result in an error in the

Status Register. All other blocks remain

unlocked in this condition and can be

programmed or erased normally. Note that

this feature is overridden and the boot block

unlocked when RP# = V_HH. Since the WP#

pin is not available on the 44-lead PSOP

package, the boot block’s default status is

The truth table, Table 9, clearly defines the

write protection methods.

Table 9. Write Protection Truth Table for

SmartVoltage Boot Block Family

V_PP

RP WP Write Protection

#

Provided

V_IL

X

All Blocks Locked

locked when RP# is at V or V_IL. For the

IH

44-lead PSOP, the boot block cannot be

unlocked with a logic-level signal; instead,

RP# must be taken to V_HHas discussed in

Section 3.4.3 below.

V_IL

All Blocks Locked

(Reset)

³

V_PPLK

V_HH

X

All Blocks

Unlocked

³

V_PPLK

3.4.3

RP# = V_HHOR WP# = V_IHFOR

BOOT BLOCK UNLOCKING

V_IHV_ILBoot Block

Locked

³

V_PPLK

Two methods can be used to unlock the

boot block:

V_IHV_IHAll Blocks

Unlocked

³

V_PPLK

1. WP# = V_IH

NOTE:

2. RP# = V_HH

WP# pin not available on 44-lead PSOP. In this package, treat as

if the WP# pin is internally tied low, effectively eliminating the

last row of the above table.

If both or either of these two conditions are

met, the boot block will be unlocked and

can be programmed or erased. Since the

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Start

Bus

Operation

Command

Comments

Write

Setup

Program

Data = 40H

Write 40H,

Word/Byte Address

Addr = Word/Byte to Program

Data = Data to Program

Addr = Location to Program

Program

Write Word/Byte

Data/Address

Read

Status Register Data

Toggle CE# or OE#

to Update SRD.

Read

Status Register

Standby

Check SR.7

1 = WSM Ready

0 = WSM Busy

NO

SR.7 = 1

?

Repeat for subsequent Word/Byte Writes.

SR Full Status Check can be done after each Word/Byte

Write, or after a sequence of Word/Byte Writes.

Write FFH after the last write operation to reset device to

YES

Full Status

Check if Desired

read array mode.

Word/Byte Program

Complete

FULL STATUS CHECK PROCEDURE

Bus

Operation

Read Status Register

Data (See Above)

Command

Comments

Standby

Check SR.3

1 = V Low Detect

PP

1

V

PP

Range Error

SR.3=

0

Standby

Check SR.4

1 = V Byte Program Error

PP

1

Word/Byte Program

Error

SR.4 =

0

SR.3 MUST be cleared, if set during a program attempt,

before further attempts are allowed by the Write State Machine.

SR.4 is only cleared by the Clear Status Register Command,

in cases where multiple bytes are programmed before full

status is checked.

Word/Byte Program

Successful

If error is detected, clear the Status Register before attempting

retry or other error recovery.

0539_06

Figure 6. Automated Word/Byte Programming Flowchart

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Start

Bus

Operation

Command

Comments

Write

Erase Setup

Data = 20H

Write 20H,

Block Address

Addr = Within Block to be Erased

Write

Read

Erase

Confirm

Data = D0H

Addr = Within Block to be Erased

Write D0H and

Block Address

Status Register Data

Toggle CE# or OE#

to Update Status Register

Read Status

Register

Suspend Erase

Loop

Standby

Check SR.7

1 = WSM Ready

NO

0 = WSM Busy

0

YES

Suspend

Erase

SR.7 =

1

Repeat for subsequent block erasures.

Full Status Check can be done after each block erase,

or after a sequence of block erasures.

Write FFH after the last operation to reset device to read

Full Status

Check if Desired

array mode.

Block Erase

Complete

FULL STATUS CHECK PROCEDURE

Bus

Operation

Read Status Register

Data (See Above)

Command

Comments

Standby

Check SR.3

1 = V Low Detect

PP

1

SR.3 =

0

V

PP

Range Error

Standby

Check SR.4,5

Both 1 = Command

Sequence Error

1

Command Sequence

Error

Check SR.5

1 = Block Erase Error

SR.4,5 =

0

SR.3 MUST be cleared, if set during an erase attempt, before further

attempts are allowed by the Write State Machine.

Block Erase

Error

SR.5 =

0

SR.5 is only cleared by the Clear Status Register Command, in

cases where multiple blocks are erase before full status is checked.

If error is detected, clear the Status Register before attempting

retry or other error recovery.

Block Erase

Successful

0539_07

Figure 7. Automated Block Erase Flowchart

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Start

Bus

Command

Operation

Comments

Write

Read

Erase

Suspend

Data = B0H

Addr = X

Write B0H

Status Register Data

Toggle CE# or OE#

to update SRD.

Addr = X

Read

Status Register

Standby

Check SR.7

1 = WSM Ready

0 = WSM Busy

0

SR.7 =

1

Check SR.6

1 = Erase Suspended

0 = Erase Completed

Write

Read

Read Array

Data = FFH

Addr = X

Erase Completed

CSR.6 =

Read array data from block other

than the one being erased.

1

Write

Erase Resume

Data = D0H

Addr = X

Write FFH

Read Array Data

NO

Done

Reading

YES

Write D0H

Write FFH

Erase Resumed

Read Array Data

0539_08

Figure 8. Erase Suspend/Resume Flowchart

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3.5

Power Consumption

(GND ± 0.2V). Note: BYTE# pin must be

at CMOS levels to meet the I

CCD

specification.

3.5.1

ACTIVE POWER

With CE# at a logic-low level and RP# at a

logic-high level, the device is placed in the

active mode. Refer to the DC

During read modes, the RP# pin going low

de-selects the memory and places the output

drivers in a high impedance state. Recovery

from the deep power-down state, requires a

minimum access time of t_PHQV(see AC

Characteristics table).

Characteristics table for I current values.

CC

3.5.2

AUTOMATIC POWER

SAVINGS (APS)

During erase or program modes, RP# low

will abort either erase or program

operations, but the memory

Automatic Power Savings (APS) provides

low-power operation during active mode.

Power Reduction Control (PRC) circuitry

allows the device to put itself into a low

current state when not being accessed. After

data is read from the memory array, PRC

logic controls the device’s power

consumption by entering the APS mode

where typical I_CCcurrent is less than 1 mA.

The device stays in this static state with

outputs valid until a new location is read.

3.5.3

STANDBY POWER

With CE# at a logic-high level (V ), and

IH

the CUI in read mode, the memory is placed

in standby mode, which disables much of

the device’s circuitry and substantially

reduces power consumption. Outputs (DQ–

0

DQ₁₅or DQ₀–DQ₇) are placed in a high-

impedance state independent of the status of

the OE# signal. When CE# is at logic-high

level during erase or program operations,

the device will continue to perform the

operation and consume corresponding

active power until the operation is

completed.

3.5.4

DEEP POWER-DOWN MODE

The SmartVoltage boot block family

supports a low typical I_CCin deep power-

down mode, which turns off all circuits to

save power. This mode is activated by the

RP# pin when it is at a logic-low

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contents are no longer valid as the data has

been corrupted by the RP# function. As in

the read mode above, all internal circuitry is

turned off to achieve the power savings.

initialization would not occur because the

flash memory may be providing status

information instead of array data. Intel’s

Flash memories allow proper CPU

RP# transitions to V , or turning power off

to the device will clear the Status Register.

initialization following a system reset by

connecting the RP# pin to the same

IL

RESET# signal that resets the system CPU.

3.6

Power-Up/Down Operation

3.6.2

V_CC, V_PPAND RP#

TRANSITIONS

The device is protected against accidental

block erasure or programming during power

transitions. Power supply sequencing is not

required, since the device is indifferent as

The CUI latches commands as issued by

system software and is not altered by V or

CE# transitions or WSM actions. Its default

state upon power-up, after exit from deep

power-down mode, or after V transitions

above V_LKO(Lockout voltage), is read array

mode.

After any word/byte write or block erase

PP

to which power supply, V or V_CC, powers-

PP

up first. The CUI is reset to the read mode

after power-up, but the system must drop

CE# low or present a new address to ensure

valid data at the outputs.

A system designer must guard against

spurious writes when V_CCvoltages are

above V_LKOand V_PPis active. Since both

WE# and CE# must be low for a command

CC

operation is complete and even after V

PP

transitions down to V_PPLK, the CUI must be

reset to read array mode via the Read Array

command if accesses to the flash memory

are desired.

write, driving either signal to V will

inhibit writes to the device. The CUI

IH

Please refer to AP-617, “Additional Flash

architecture provides additional protection

since alteration of memory contents can

only occur after successful completion of

the two-step command sequences. The

device is also disabled until RP# is brought

to V_IH, regardless of the state of its control

inputs. By holding the device in reset (RP#

connected to system PowerGood) during

power-up/down, invalid bus conditions

during power-up can be masked, providing

yet another level of memory protection.

Data Protection Using V , RP#, and WP#”

PP

for a circuit-level description of how to

implement the protection discussed in

Section 3.6.

3.7

Power Supply Decoupling

Flash memory’s power switching

characteristics require careful device

decoupling methods. System designers

should consider three supply current issues:

1. Standby current levels (I_CCS

2. Active current levels (I

)

CCR

3.6.1

RP# CONNECTED TO

SYSTEM RESET

3. Transient peaks produced by falling and

rising edges of CE#.

The use of RP# during system reset is

important with automated write/erase

devices because the system expects to read

from the flash memory when it comes out

of reset. If a CPU reset occurs without a

flash memory reset, proper CPU

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3.7.1

V_PPTRACE ON PRINTED

CIRCUIT BOARDS

Transient current magnitudes depend on the

device outputs’ capacitive and inductive

loading. Two-line control and proper

decoupling capacitor selection will suppress

these transient voltage peaks. Each flash

device should have a 0.1 µF ceramic

Designing for in-system writes to the flash

memory requires special consideration of

the V_PPpower supply trace by the printed

circuit board designer. The V pin supplies

PP

the flash memory cells current for

programming and erasing. One should use

similar trace widths and layout

capacitor connected between each V and

GND, and between its V and GND. These

high- frequency, inherently low-inductance

capacitors should be placed as close as

possible to the package leads.

CC

PP

considerations given to the V power

CC

supply trace. Adequate V supply traces,

PP

and decoupling capacitors placed adjacent

to the component, will decrease spikes and

overshoots.

NOTE:

Table headings in Sections 5 and 6 (i.e., BV-70, BV-120, TBV-90, TBE-120) refer to

the specific products listed below. See Section 7.1 for more information on product

naming and line items.

Abbreviatio

n

Applicable Product Names

BV-70

BV-120

TBV-90

TBE-120

E28F008BV-T70, E28F008BV-B70, E28F800CV-T70, E28F800CV-

B70, PA28F800BV-T70, PA28F800BV-B70

E28F008BV-T120, E28F008BV-B120, PA28F800BV-T120,

PA28F800BV-B120

TE28F008BV-T90, TE28F008BV-B90, TE28F800CV-T90,

TE28F800CV-B90, TB28F800BV-T90, TB28F800BV-B90

TE28F008BE-T120, TE28F008BE-B120, TE28F800CE-T120,

TE28F800CE-B120, TB28F800BE-T120, TB28F800BE-B120

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4.0

ABSOLUTE MAXIMUM

RATINGS*

NOTICE: This datasheet contains information on products in the

sampling and initial production phases of development. The

specifications are subject to change without notice. Verify with

your local Intel Sales office that you have the latest datasheet

before finalizing a design.

Commercial Operating Temperature

During Read.....................0°C to +70°C

* WARNING: Stressing the device beyond the "Absolute

Maximum Ratings" may cause permanent damage. These are

stress ratings only. Operation beyond the "Operating

Conditions" is not recommended and extended exposure

beyond the "Operating Conditions" may effect device

reliability.

During Block Erase

and Word/Byte Write.......0°C to +70°C

Temperature Bias.........–10°C to +80°C

Extended Operating Temperature

NOTES:

1. Operating temperature is for commercial product defined

by this specification.

During Read.................–40°C to +85°C

2. Minimum DC voltage is –0.5V on input/output pins.

During transitions, this level may undershoot to –2.0V for

periods < 20 ns. Maximum DC voltage on input/output pins

is V_CC+ 0.5V which, during transitions, may overshoot to

V_CC+ 2.0V for periods

During Block Erase

and Word/Byte Write...–40°C to +85°C

Temperature Under Bias–40°C to +85°C

Storage Temperature........–65°C to +125°C

Voltage on Any Pin

< 20 ns.

3. Maximum DC voltage on V_PPmay overshoot to +14.0V for

periods < 20 ns. Maximum DC voltage on RP# or A may

overshoot to 13.5V for periods < 20 ns.

9

4. Output shorted for no more than one second. No more than

one output shorted at a time.

(except V_CC, V_PP, A₉and RP#)

(2)

with Respect to GND.–2.0V to +7.0V

Voltage on Pin RP# or Pin A

9

with Respect to GND–2.0V to

(2,3)

+13.5V

V_PPProgram Voltage with Respect

to GND during Block Erase

and Word/Byte Write–2.0V to

(2,3)

+14.0V

V_CCSupply Voltage

(2)

with Respect to GND.–2.0V to +7.0V

(4)

Output Short Circuit Current......100 mA

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5.0

COMMERCIAL OPERATING CONDITIONS

Table 10. Commercial Temperature and V _CCOperating Conditions

Symbol

Parameter

Notes

Min

0

Max

+70

3.6

Units

°C

T_A

Operating Temperature

V_CC

3.3V V_CCSupply Voltage (±

0.3V)

3.0

Volts

5V V_CCSupply Voltage (10%)

5V V_CCSupply Voltage (5%)

1

2

4.50

4.75

5.50

5.25

Volts

NOTES:

1. 10% V_CCspecifications apply to the 80 ns and 120 ns product versions in their standard test configuration.

2. 5% V_CCspecifications apply to the 80 ns versions in their high-speed test configuration.

5.1

Applying V_CCVoltages

When applying V_CCvoltage to the device, a delay may be required before initiating device

operation, depending on the V ramp rate. If V_CCramps slower than 1V/100 µs (0.01 V/µs)

CC

then no delay is required. If V ramps faster than 1V/100 µs (0.01 V/µs), then a delay of 2

CC

µs is required before initiating device opeation. RP# = GND is recommended during power-

up to protect against spurious write signals when V is between V_LKOand V_CCMIN

.

CC

V_CCRamp

Rate

Required Timing

No delay required.

£ 1V/100 ms

> 1V/100 ms

A delay time of 2 ms is required before any device operation is initiated,

including read operations, command writes, program operations, and erase

operations. This delayis measured beginning from the time V reaches

CC

V_CCMIN(3.0V for 3.3 ± 0.3V operation; and 4.5V for 5V operation).

NOTES:

1. These requirements must be strictly followedto guarantee all other read and write specifications.

2. To switch between 3.3V and 5V operation, the system should first transition V_CCfrom the existing voltage range to GND, and then

to the new voltage. Any time the V_CCsupply drops below V_CCMIN, the chip may be reset, aborting any operations pending or in

progress.

3. These guidelines must be followed for any V_CCtransition from GND.

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5.2

DC Characteristics

Table 11. DC Characteristics (Commercial)

Prod BV-70

BV-120

Sym

Parameter

V_CC3.3 ± 0.3V 5V ± 10% Unit

s

Test Conditions

Note Typ Max Typ Max

s

V_CC= V_CCMax

V_IN= V_CCor GND

I_IL

Input Load Current

1

±

1.0

±

1.0

µA

V_CC= V_CCMax

V_IN= V_CCor GND

I_LO

Output Leakage

Current

1

± 10

± 10 µA

V_CC= V_CCMax

CE# = RP# = BYTE#

=

I_CCSV_CCStandby

Current

1,3

0.4

1.5

0.8

2.0 mA

WP# = V_IH

V_CC= V_CCMax

CE# = RP# = V_CC

0.2V

60

110

8

50

130 µA

±

V_CC= V_CCMax

I_CCDV_CCDeep

1

0.2

8

µA

V_IN= V_CCor GND

RP# = GND ± 0.2V

Power-Down

Current

V_CCRead Current

for Word or Byte

CMOS INPUTS

V_CC= V_CCMax

CE# = GND, OE# =

V_CC

I_CCR

1,5,6 15

30

50

60

mA

f = 10 MHz (5V),

5 MHz (3.3V)

I_OUT= 0 mA

Inputs = GND ±

0.2V or

V_CC± 0.2V

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Table 11. DC Characteristics (Commercial)

TTL INPUTS

V_CC= V_CCMax

CE# = V_IL, OE# =

V_IH

15

30

55

65

mA

f = 10 MHz (5V),

5 MHz (3.3V)

I_OUT= 0 mA

Inputs = V_ILor V_IH

V_CCWrite Current

for Word or Byte

V_PP= V_PPH1 (at 5V)

Word Write in

Progress

I_CCW

1,4

13

10

13

10

30

25

30

25

30

18

50

45

35

30

mA

_VPP= V_PPH2 (at 12V)

Word Write in

Progress

V_PP= V_PPH1 (at 5V)

Block Erase in

Progress

V_PP= V_PPH2 (at

12V)

I_CCEV_CCErase Current

Block Erase in

Progress

V_CCErase Suspend

Current

CE# = V_IH

Block Erase Suspend

I_CCES

1,2

3

8.0

5

10

mA

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Table 11. DC Characteristics (Commercial) (Continued)

Prod

BV-70

BV-120

Sym

Parameter

V_CC3.3 ± 0.3V 5V ± 10% Unit

s

Test Conditions

Note Typ Max Typ Max

s

I_PPSV_PPStandby

Current

1

±

0.5

± 15

±

0.5

± 10 µA V_PP< V_PPH

2

V_PPDeep Power-

Down

I_PPD

1

0.2

5

0.2

5.0 µA RP# = GND ± 0.2V

Current

I_PPRV_PPRead Current

1

50

13

200

30

13

200 µA

V_PP³ V_PPH

2

V_PP= V_PPH1 (at 5V)

Word Write in

Progress

V_PP= V_PPH2 (at 12V)

Word Write in

Progress

V_PP= V_PPH1 (at 5V)

Block Erase in

Progress

V_PP= V_PPH2 (at 12V)

Block Erase in

Progress

I_PPWV_PPWord/Byte

Current

1,4

25

20

15

mA

8

13

8

25

30

8

10

5

I_PPEV_PPErase Current

1,4

mA

25

V_PPErase

Suspend Current

V_PP= V_PPHBlock

Erase

I_PPES

1

50

200

30

200 µA

Suspend in Progress

I_RP#RP# Boot Block

Unlock Current

1,4

500

500 µA RP# = V_HH

A₉Intelligent

I_ID

500 µA A₉= V_ID

Identifier Current

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Table 11. DC Characteristics (Commercial) Continued

Prod

BV-70

BV-120

Sym

Parameter

V_CC3.3 ± 0.3V 5V ± 10% Unit

Notes Min Max Min Max

Test

Conditions

V_IDA₉Intelligent Identifier

Voltage

11.4 12.6 11.4 12.6

V

V_ILInput Low Voltage

V_IHInput High Voltage

–0.5 0.8 –0.5 0.8

V

V_CC

+

V_CC

+

2.0

2.4

2.0

2.4

0.5V

V_CC= V_CC

Min

I_OL= 5.8 mA

V_OLOutput Low Voltage

0.45

V

V_CC= V_CC

Min

I_OH= –2.5

mA

V_OH1 Output High Voltage

(TTL)

0.85

x

V_CC

0.85

x

V_CC

V_CC= V_CC

Min

I_OH= –2.5

mA

V_CC= V_CC

Min

I_OH= –100

mA

V_OH2 Output High Voltage

(CMOS)

V

V_{CC –}

0.4V

V_{CC –}

0.4V

V_PPLV_PPLock-Out Voltage

K

3

0.0

4.5

1.5

5.5

0.0

4.5

1.5

5.5

Complete

Write

Protection

V_PPHV_PP(Prog/Erase

V

V_PPat 5V

1

Operations)

V_PPHV_PP(Prog/Erase

11.4 12.6 11.4 12.6

2.0 2.0

V_PPat 12V

2

Operations)

V_LKOV_CCErase/Write Lock

Voltage

8

41

PRODUCT PREVIEW

8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY

E

Table 11. DC Characteristics (Commercial) Continued

V_HHRP# Unlock Voltage

11.4 12.6 11.4 12.6

V

Boot Block

Write/Erase

Table 12. Capacitance (T_A= 25 °C, f = 1 MHz)

Symbol

Parameter

Notes

Typ

Max

Units

Conditions

C_IN

Input

4

6

8

pF

V_IN= 0V

Capacitance

C_OUT

Output

4, 7

10

12

pF

V_OUT= 0V

Capacitance

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at V_CC= 5.0V, T = +25°C. These currents are valid for all product

versions (packages and speeds).

2. I_CCESis specified with the device deselected. If the device is read while in erase suspend mode, current draw is the sum o_Cf _CI_ESand

I_CCR

.

3. Block erases and word/byte writes are inhibietd when V_PP= V_PPLK, and not guaranteed in the range between V_PPH1 and V_PPLK

.

4. Sampled, not 100% tested.

5. Automatic Power Savings (APS) reduces I_CCRto less than 1 mA typical, in static operation.

6. CMOS Inputs are either V_CC± 0.2V or GND ± 0.2V. TTL Inputs are either V or V_IH

.

IL

7. For the 28F008B, address pin A₁₀follows the C_OUTcapacitance numbers.

8. For all BV/CV parts, V_LKO= 2.0V for both 3.3V and 5V operations.

3.0

OUTPUT

INPUT

1.5

TEST POINTS

1.5

0.0

0539_09

NOTE:

AC test inputs are driven at 3.0V for a logic “1” and 0.0V for a logic “0.” Input timing begins, and output timing ends, at 1.5V. Input rise

and fall times (10%–90%) <10 ns.

Figure 9. 3.3V Inputs and Measurement Points

42

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2.4

2.0

0.8

2.0

0.8

INPUT

OUTPUT

TEST POINTS

0.45

0539_10

NOTE:

AC test inputs are driven at V_OH(2.4 V_TTL) for a logic “1” and V_OL(0.45 V_TTL) for a logic “0.” Input timing begins at V_IH(2.0 V_TTL

)

and V_IL(0.8 V_TTL) . Output timing ends at V_IHand V_IL. Input rise and fall times (10%–90%) <10 ns.

Figure 10. 5V Inputs and Measurement Points

Test Configuration Component Values

V_CC

Test Configuration

C_L

R₁

R₂

(pF)

(W) (W)

990 770

580 390

R ₁

3.3V Standard Test

5V Standard Test

5V High-Speed Test

50

100

30

Device

under

Test

Out

C_L

R ₂

NOTE:

C_Lincludes jig capacitance.

0539-11

NOTE:

See table for component values.

Figure 11. Test Configuration

43

PRODUCT PREVIEW

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E

5.3

AC Characteristics

Table 13. AC Characteristics: Read Only Operations (Commercial)

Prod BV-70

V_CC3.3±0.3V 5V±5%

(

(6)

(

5V±10%

5)

7)

Symbo

Parameter

Loa

d

50 pF

30 pF

100 pF

Unit

s

l

Note

s

Min

Max

Min

Max

Min

Max

t_AVAV

t_AVQV

t_ELQV

t_PHQV

Read Cycle Time

120

70

80

ns

ms

Address to Output Delay

CE# to Output Delay

RP# to Output Delay

120

1.5

70

80

2

0.4

5

0.4

5

t_GLQV

t_ELQX

t_EHQZ

t_GLQX

t_GHQZ

t_OH

OE# to Output Delay

2

3

65

55

45

30

20

35

25

ns

CE# to Output in Low Z

CE# to Output in High Z

OE# to Output in Low Z

OE# to Output in High Z

0

Output Hold from Address,

CE#, or OE# Change,

Whichever Occurs First

t_ELFL

t_ELFH

CE# Low to BYTE# High

or Low

3

5

ns

t_AVFL

Address to BYTE# High or

Low

t_FLQV

t_FHQV

BYTE# to Output Delay

3,4

3

120

45

70

20

80

25

ns

t_FLQZ

BYTE# Low to Output in

High Z

44

PRODUCT PREVIEW

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Table 13. AC Characteristics: Read Only Operations (Commercial) (Continued)

Prod

V_CC

BV-120

(5)

(7)

Sym

Parameter

3.3±0.3V

50 pF

5V±10%

100 pF

Units

Load

Notes Min Max Min Max

t_AVAV

t_AVQV

t_ELQV

t_PHQV

t_GLQV

t_ELQX

t_EHQZ

t_GLQX

t_GHQZ

t_OH

Read Cycle Time

150

120

ns

µs

ns

Address to Output Delay

CE# to Output Delay

150

1.5

90

120

0.45

40

2

RP# to Output Delay

OE# to Output Delay

2

3

CE# to Output in Low Z

CE# to Output in High Z

OE# to Output in Low Z

OE# to Output in High Z

0

80

60

30

Output Hold from Address, CE#,

or OE# Change, Whichever

Occurs First

t_ELFL

t_ELFH

CE# Low to BYTE# High or Low

3

5

ns

t_AVFL

Address to BYTE# High or Low

BYTE# to Output Delay

3

5

ns

t_FLQV

t_FHQV

3,4

150

120

t_FLQZ

BYTE# Low to Output in High Z

3

60

30

ns

NOTES:

1. See AC Input/Output Reference Waveform for timing measurements.

2. OE# may be delayed up to t_CE–t_OEafter the falling edge of CE# without impact on _Ct_E.

3. Sampled, but not 100% tested.

4. t_FLQV, BYTE# switching low to valid output delay will be equal to_At_VQV, measured from the time DQ /A_–1becomes valid.

15

5. See Test Configurations (Figure11), 3.3V Standard Test component values.

6. See Test Configurations (Figure11), 5V High-Speed Test component values.

7. See Test Configurations (Figure11), 5V Standard Test component values.

45

PRODUCT PREVIEW

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E

Device and

Address Selection

Data

Valid

Standby

V

IH

ADDRESSES (A)

V_IL

Address Stable

t_AVAV

V

IH

CE# (E)

V_IL

t_EHQZ

V

IH

OE# (G)

V_IL

t_GHQZ

V

WE# (W) ^IH

t_GLQV

t_GLQX

t_OH

V_IL

t_ELQV

V

OH

t_ELQX

High Z

DATA (D/Q)

V_OL

Valid Output

t_AVQV

V

IH

RP#(P)

V_IL

t_PHQV

0539_14

Figure 12. AC Waveforms for Read Operations

Device

Address Selection

Data

Valid

Standby

V_IH

ADDRESSES (A)

V_IL

Address Stable

t_AVAV

V_IH

CE# (E)

V_IL

t_EHQZ

t_AVFL

V_IH

OE# (G)

t_ELFL

V_IL

t_GHQZ

V_IH

BYTE# (F)

V_IL

t_GLQV

t_ELQV

t_GLQX

t_OH

V_OH

t_ELQX

High Z

DATA (D/Q)

(DQ0-DQ7)

V_OL

Data Output

on DQ0-DQ7

Data Output

on DQ0-DQ7

t_AVQV

V_OH

DATA (D/Q)

(DQ8-DQ14)

V_OL

Data Output

on DQ8-DQ14

t _FLQZ

t_AVQV

V_OH

(DQ15/A-1)

V_OL

High Z

Data Output

on DQ15

Address Input

0539_15

Figure 13. BYTE# Timing Diagram for Read Operations

46

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(1)

Table 14. AC Characteristics: WE#–Controlled Write Operations

Prod BV-70

(Commercial)

47

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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY

Table 14. AC Characteristics: WE#–Controlled Write Operations

E

(1)

(Commercial)

(

(10

(

Symbo

l

Parameter

V_CC3.3±0.3V 5V±5%

5V±10% Unit

9)

)

11)

Loa

50 pF

30 pF

100 pF

d

Note Mi Ma Mi Ma Mi Ma

s

n

x

n

x

n

x

t_AVAV

t_PHWL

Write Cycle Time

120

1.5

70

80

ns

RP# Setup to WE# Going

Low

0.4

5

0.4

5

ms

t_ELWL

CE# Setup to WE# Going

Low

0

ns

t_PHHWH

Boot Block Lock Setup to

WE# Going High

6,8 200

5,8 200

100

V_PPSetup to WE# Going

High

t_VPWH

t_AVWH

100

50

100

50

ns

Address Setup to WE#

Going High

3

4

90

t_DVWH

Data Setup to WE# Going

High

50

ns

t_WLWH

t_WHDX

WE# Pulse Width

90

0

50

0

50

0

ns

Data Hold Time from WE#

High

4

3

t_WHAX

t_WHEH

Address Hold Time from

WE# High

0

ns

CE# Hold Time from WE#

High

t_WHWL

WE# Pulse Width High

20

6

10

6

20

6

ns

µs

t_WHQV1

Duration of Word/Byte

Programming Operation

2,5

t_WHQV2

t_WHQV3

Duration of Erase

Operation (Boot)

2,5,6 0.3

2,5 0.3

0.3

s

Duration of Erase

Operation (Parameter)

48

PRODUCT PREVIEW

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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY

(1)

Table 14. AC Characteristics: WE#–Controlled Write Operations

(Commercial)

t_WHQV4

Duration of Erase

Operation (Main)

2,5

0.6

s

t_QWL

V_PPHold from Valid SRD

5,8

6,8

0

ns

t_QVPH

RP# V_HHHold from Valid

SRD

t_PHBR

Boot-Block Lock Delay

7,8

200

100

ns

49

PRODUCT PREVIEW

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E

(1)

Table 14. AC Characteristics: WE#–Controlled Write Operations

(Commercial)

(Continued)

Prod

V_CC

BV-120

(9)

(11)

Sym

Parameter

3.3±0.3V

50 pF

5V±10%

100 pF

Unit

Load

Note Min Max Min Max

t_AVAV

t_PHWL

t_ELWL

Write Cycle Time

180

1.5

0

120

0.45

0

ns

µs

ns

RP# Setup to WE# Going Low

CE# Setup to WE# Going Low

t_PHHWHBoot Block Lock Setup to WE#

Going High

6,8

200

100

V_PPSetup to WE#

Going High

t_VPWH

5,8

3

200

150

100

50

ns

t_AVWHAddress Setup to WE# Going

High

t_DVWHData Setup to WE# Going High

t_WLWHWE# Pulse Width

4

150

0

50

0

ns

t_WHDXData Hold Time from WE# High

4

3

t_WHAXAddress Hold Time from WE#

High

0

t_WHEH

CE# Hold Time from WE# High

0

30

6

0

30

6

ns

µs

t_WHWLWE# Pulse Width High

t_WHQV1Duration of Word/Byte

Programming Operation

2,5

2,5,6

2,5

t_WHQV2Duration of Erase Operation

(Boot)

0.3

0.6

0

0.3

0.6

0

s

t_WHQV3Duration of Erase Operation

(Parameter)

t_WHQV4Duration of Erase Operation

(Main)

2,5

s

t_QWL

V_PPHold from Valid SRD

5,8

ns

50

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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY

t_QVPH

RP# V_HHHold from Valid SRD

Boot-Block Lock Delay

6,8

7,8

0

ns

t_PHBR

200

100

NOTES:

1. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC

characteristics during read mode.

2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled internally which

includes verify and margining operations.

3. Refer to command definition table for valid A . (Table 7)

IN

4. Refer to command definition table for valid D . (Table 7)

IN

5. Program/erase durations are measured to valid SRD data (successful operation, SR.7=1).

6. For boot block program/erase, RP# should be held at V_HHor WP# should be held at V_IHuntil operation completes successfully.

7. Time t_PHBRis required for successful locking of the boot block.

8. Sampled, but not 100% tested.

9. See Test Configurations (Figure11), 3.3V Standard Test component values.)

10. See Test Configurations (Figure11), 5V High-Speed Test component values.

11. See Test Configurations (Figure11), 5V Standard Test component values.

1

2

3

4

5

6

V

IH

ADDRESSES (A)

V_IL

A_IN

t_AVAV

t_AVWH

t_WHAX

V

IH

CE# (E)

V_IL

t_ELWL

t_WHEH

V

IH

OE# (G)

V_IL

t_WHWL

t_WHQV1,2,3,4

V

IH

WE# (W)

V_IL

t_WLWH

t_DVWH

t_WHDX

V

IH

High Z

Valid

SRD

DATA (D/Q)

D_IN

t_PHHWH

D_IN

V_IL

t_PHWL

t_QVPH

V_HH

6.5V

V

IH

RP# (P)

V_IL

V

IH

WP#

V_IL

t_QVVL

t_VPWH

V_PPH

2

V_PPH

V_PPLK

V_IL

1

V

(V)

PP

0539_16

Figure 14. AC Waveforms for Write and Erase Operations (WE#–Controlled Writes)

51

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E

(1,12)

Table 15. AC Characteristics: CE#–Controlled Write Operations

(Commercial)

Prod

BV-70

(

(10

(

V_CC3.3±0.3V 5V±5%

5V±10%

9)

)

11)

Symbo

l

Parameter

Loa

50 pF

30 pF

100 pF

Unit

d

Note Min

120

Max

Min

Max

Min

Max

t_AVAV

t_PHEL

Write Cycle Time

70

80

ns

µs

RP# High Recovery to CE#

Going Low

1.5

0.4

5

0.4

5

t_WLEL

WE# Setup to CE# Going

Low

0

6,8 200

5,8 200

0

ns

t_PHHEH

Boot Block Lock Setup to

CE# Going High

100

V_PPSetup to CE# Going

High

t_VPEH

t_AVEH

100

50

100

50

ns

Address Setup to CE#

Going High

3

4

90

t_DVEH

Data Setup to CE# Going

High

50

ns

t_ELEH

t_EHDX

CE# Pulse Width

90

0

50

0

50

0

ns

Data Hold Time from CE#

High

4

3

t_EHAX

t_EHWH

Address Hold Time from

CE# High

0

ns

WE # Hold Time from CE#

High

t_EHEL

CE# Pulse Width High

20

6

10

6

20

6

ns

µs

t_EHQV1

Duration of Word/Byte

Programming Operation

2,5

t_EHQV2

Duration of Erase

Operation (Boot)

2,5,6 0.3

0.3

s

52

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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY

(1,12)

Table 15. AC Characteristics: CE#–Controlled Write Operations

(Commercial)

t_EHQV3

Duration of Erase

Operation (Parameter)

2,5

0.3

0.6

s

t_EHQV4

Duration of Erase

Operation (Main)

2,5

0.6

t_QWL

V_PPHold from Valid SRD

5,8

6,8

0

ns

t_QVPH

RP# V_HHHold from Valid

SRD

t_PHBR

Boot-Block Lock Delay

7,8

200

100

ns

(1,12)

Table 15. AC Characteristics: CE#–Controlled Write Operations

(Continued)

(Commercial)

Prod

V_CC

BV-120

(9)

(11)

Sym

Parameter

3.3±0.3V

50 pF

5V±10%

100 pF

Unit

Load

Note Min Max Min Max

t_AVAV

t_PHEL

Write Cycle Time

180

1.5

120

ns

RP# High Recovery to CE# Going

Low

0.45

ms

t_WLEL

WE# Setup to CE# Going Low

0

ns

t_PHHEHBoot Block Lock Setup to CE#

Going High

6,8

200

100

t_VPEH

t_AVEH

t_DVEH

t_ELEH

t_EHDX

t_EHAX

V_PPSetup to CE# Going High

Address Setup to CE# Going High

Data Setup to CE# Going High

CE# Pulse Width

5,8

3

200

150

0

100

50

0

ns

4

Data Hold Time from CE# High

4

3

Address Hold Time from CE#

High

0

t_EHWH

t_EHEL

WE # Hold Time from CE# High

CE# Pulse Width High

0

ns

30

53

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E

t_EHQV1Duration of Word/Byte

Programming Operation

2,5

2,5,6

2,5

6

µs

t_EHQV2Duration of Erase Operation

(Boot)

0.3

0.6

0.3

0.6

s

t_EHQV3Duration of Erase Operation

(Parameter)

s

t_EHQV4Duration of Erase Operation

(Main)

2,5

s

t_QWL

V_PPHold from Valid SRD

RP# V_HHHold from Valid SRD

Boot-Block Lock Delay

5,8

6,8

7,8

0

ns

t_QVPH

t_PHBR

200

100

ms

NOTES:

See WE# Controlled Write Operations for notes 1 through 11.

12. Chip-Enable controlled writes: write operations are driven by the valid combination of CE# and WE# in systems where

CE# defines the write pulse-width (within a longer WE# timing waveform), all set-up, hold and inactive WE# times should

be measured relative to the CE# waveform.

54

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8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY

1

2

3

4

5

6

V_IH

ADDRESSES (A)

V_IL

A_IN

t_AVAV

t_AVEH

t_EHAX

V_IH

WE# (W)

V_IL

t _WLEL

t_EHWH

V_IH

OE# (G)

V_IL

V_IH

t _EHEL

t _EHQV1,2,3,4

CE# (E)

V_IL

t _ELEH

t _DVEH

t _EHDX

V_IH

DATA (D/Q)

V_IL

High Z

Valid

SRD

D

D_IN

D

IN

t_PHHEH

t _PHEL

t_QVPH

V_HH

6.5V

V_IH

RP# (P)

V_IL

V_IH

WP#

V_IL

t _VPEH

t_QVVL

V_PPH

2

V_PPH

V_PPLK

V_IL

1

V

(V)

PP

0539_17

NOTES:

1. V Power-Up and Standby.

CC

2. Write program or Erase Setup Command.

3. Write Valid Address and Data (Program) or Erase Confirm Command.

4. Automated Program or Erase Delay.

5. Read Status Register Data.

6. Write Read Array Command.

Figure 15. Alternate AC Waveforms for Write and Erase Operations (CE#–Controlled

Writes)

55

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E

it

Table 16. Erase and Program Timings (Commercial T _A= 0°C to +70°C)

5V ± 10%

12V ± 5%

V_PP

V_CC

Parameter

5V ± 10% 3.3 ± 0.3V 5V ± 10% Un

3.3 ± 0.3V

Typ Max Typ Max Typ Max Typ Max

Boot/Parameter Block Erase

Time

0.84

7

0.8

7

0.44

7

0.34

7

s

Main Block Erase Time

2.4

1.7

14

1.9

1.8

14

1.3

1.6

14

1.1

1.2

14

s

Main Block Write Time (Byte

Mode)

Main Block Write Time (Word 1.1

Mode)

0.9

0.8

0.6

s

Byte Write Time

Word Write Time

10

13

10

13

8

µs

NOTES:

1. All numbers are sampled, not 100% tested.

2. Max erase times are specified under worst case conditions. The max erase times are tested at the same value independent of _CV_Cand

V_PP. See Note 3 for typical conditions.

3. Typical conditions are 25°C with V_CCand V_PPat the center of the specifed voltage range. Production programming using

V_CC= 5.0V, V_PP= 12.0V typically results in a 60% reduction in programming time.

4. Contact your Intel representative for information regarding maximum byte/word write specifications.

56

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6.0

EXTENDED OPERATING CONDITIONS

Table 17. Extended Temperature and V_CCOperating Conditions

Symbol

Parameter

Notes

Min

–40

2.7

Max

+85

3.6

Units

°C

T_A

Operating Temperature

V_CC

2.7V–3.6V V_CCSupply

Voltage

1

2

Volts

3.3V V_CCSupply Voltage (±

0.3V)

3.0

3.6

Volts

5V V_CCSupply Voltage (10%)

4.50

5.50

NOTES:

1. AC specifications are valid at both voltage ranges. See DC Characteristics tables for voltage range-specific specifications.

2. 10% V_CCspecifications apply to 100 ns versions in their standard test configuration.

6.1

Applying V_CCVoltages

When applying V_CCvoltage to the device, a delay may be required before initiating device

operation, depending on the V ramp rate. If V_CCramps slower than 1V/100 µs (0.01 V/µs)

CC

then no delay is required. If V ramps faster than 1V/100 µs (0.01 V/µs), then a delay of 2

CC

µs is required before initiating device opeation. RP# = GND is recommended during power-

up to protect against spurious write signals when V is between V_LKOand V_CCMIN

.

CC

V_CCRamp

Rate

Required Timing

No delay required.

£ 1V/100 ms

> 1V/100 ms

A delay time of 2 ms is required before any device operation is initiated,

including read operations, command writes, program operations, and erase

operations. This delayis measured beginning from the time V reaches

CC

V_CCMIN(2.7V for 2.7V–3.6V operation, 3.0V for 3.3± 0.3V operation; and

4.5V for 5V operation).

NOTES:

1. These requirements must be strictly followed to guarantee all other read and write specifications.

2. To switch between 3.3V and 5V operation, thesystem should first transition V_CCfrom the existing voltage range to GND, and then

to the new voltage. Any time the V_CCsupply drops below V_CCMIN, the chip may be reset, aborting any operations pending or in

progress.

3. These guidelines must be followed for any V_CCtransition from GND.

57

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E

6.2

DC Characteristics

Table 18. DC Characteristics: Extended Temperature Operation

Prod TBE-120

TBV-90

TBE-120

Sym Paramet

er

V_CC2.7V–3.6V

3.3V ±

0.3V

5V ± 10% Unit Test Conditions

Note Typ Ma Typ Ma Typ Ma

s

x

V_CC= V_CCMax

V_IN= V_CCor GND

I_IL

Input

Load

1

±

1.0

±

1.0

±

1.0

µA

Current

V_CC= V_CCMax

V_IN= V_CCor GND

I_LO

Output

Leakage

Current

1

± 10

± 10 µA

V_CC

I_CCS

1,3

50 110 60 110 70 150 µA

CMOS Levels

Standby

Current

V_CC= V_CCMax

CE# = RP# = WP#

=

V_CC± 0.2V

0.4 1.5 0.4 1.5 0.8 2.5 mA

TTL Levels

V_CC= V_CCMax

CE# = RP# =

BYTE#

= V_IH

V_CCDeep

Power-

Down

V_CC= V_CCMax

V_IN= V_CCor GND

RP# = GND ±

0.2V

I_CCD

1

0.2

8

0.2

8

0.2

8

µA

Current

58

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Table 18. DC Characteristics: Extended Temperature Operation

V_CCRead

Current

for Word

or Byte

CMOS INPUTS

V_CC= V_CCMax

CE = V_IL

I_CCR

1,5,6 14

30

15

30

50

65 mA

f = 10 MHz (5V)

5 MHz (3.3V)

I_OUT= 0 mA

Inputs = GND ±

0.2V

or V_CC± 0.2V

TTL INPUTS

V_CC= V_CCMax

CE# = V_IL

14

30

15

30

55

70 mA

f = 10 MHz (5V),

5 MHz (3.3V)

I_OUT= 0 mA

Inputs = V_ILor V_IH

59

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E

Table 18. DC Characteristics: Extended Temperature Operation (Continued)

Prod TBE-120

V_CC2.7V–3.6V

TBV-90

TBE-120

Sym Paramet

er

3.3V ±

0.3V

5V ± 10% Unit Test Conditions

Note Typ Ma Typ Ma Typ Ma

s

x

V_CCWrite

I_CCW

V_PP= V_PPH1 (at

5V)

Word/Byte

Program

1,4

8

9

30

13

10

30

50 mA

Current

for Word

or Byte

in Progress

V_PP= V_PPH2 (at

12V)

25

45 mA

Word/Byte

Program

in Progress

V_CCErase

I_CCE

V_PP= V_PPH1 (at

5V)

Block Erase in

Progress

1,4

12

9

30

25

13

10

3

30

25

22

18

5

45 mA

40 mA

12.0 mA

Current

V_PP= V_PPH2 (at

12V)

Block Erase in

Progress

V_CCErase

I_CCES

V_PP= V_PPH1 (at

5V)

CE# = V_IH

Block Erase

Suspend

1,2

2.5 8.0

8.0

Suspend

Current

V_PP

Standby

Current

V_PPDeep

Power-

down

I_PPS

1

± 5 ± 15 ± 5 ± 15 ± 5 ± 15 µA V_PP< V_PPH2

I_PPD

0.2 10

0.2 10 µA RP# = GND ±

0.2V

Current

60

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Table 18. DC Characteristics: Extended Temperature Operation (Continued)

V_PPRead

Current

V_PPWrite

Current

for

I_PPR

1

50 200 50 200 50 200 µA

V_PP³ V_PPH

2

V_PP= V_PPH

30 mA

I_PPW

1,4

13

30

13

30

13

Word Write in

Progress

V_PP= V_PPH1 (at

5V)

Word/Byt

e

V_PP= V_PPH

8

25

8

25

8

25 mA

Word Write in

Progress

V_PP= V_PPH2 (at

12V)

61

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E

Table 18. DC Characteristics: Extended Temperature Operation (Continued)

Prod TBE-120

V_CC2.7V–3.6V

TBV-90

TBE-120

Sym Paramet

er

3.3V ±

0.3V

5V ± 10% Unit Test Conditions

Note Typ Ma Typ Ma Typ Ma

s

x

V_PPErase

I_PPE

V_PP= V_PPH

1,4

13

8

30

13

8

30

15

10

25 mA

Current

Block Erase in

Progress

V_PP= V_PPH1 (at

5V)

V_PP= V_PPH

25

20 mA

Block Erase in

Progress

V_PP= V_PPH2 (at

12V)

V_PPErase

Suspend

Current

V_PP= V_PPH

Block Erase

Suspend

I_PPES

1

50 200 50 200 50 200 µA

in Progress

RP# = V_HH

V_PP= 12V

I_RP#

RP# Boot 1,4

Block

Unlock

500

500 µA

Current

A₉

I_ID

1,4

500 µA A₉= V_ID

Intelligen

t

Identifier

Current

62

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Table 18. DC Characteristics: Extended Temperature Operation (Continued)

Prod TBE-120

TBV-90

TBE-120

Sym Paramet

V_CC

2.7V–

3.6V

3.3V ±

0.3V

5V ± 10% Unit Test Conditions

er

Note Min Ma Min Ma Mi Ma

s

x

n

x

A₉

V_ID

11.4 12. 11.4 12.6 11. 12.6

V

Intelligen

t

6

4

Identifier

Voltage

V_IL

V_IH

Input

Low

Voltage

–0.5 0.8 –0.5 0.8

–

0.5

0.8

V

V_CC

±

V_CC

±

V_CC

±

0.5

V

Input

High

Voltage

2.0

0.5

V

0.5

V

V_CC= V_CCMin

V_PP= 12V

V_OLOutput

Low

0.4

5

0.45

V

I_OL= 5.8 mA (5V)

Voltage

2 mA (3.3V)

V_CC= V_CCMin

I_OH= –2.5 mA

V_OH1 Output

High

2.4

V

Voltage

(TTL)

V_CC= V_CCMin

I_OH= –2.5 mA

V_OH2 Output

High

0.85

✕

V_CC

0.85

✕

V_CC

0.8

5 ✕

V_CC

Voltage

V_CC= V_CCMin

I_OH= –100 µA

(CMOS)

V_CC–

0.4V

V_CC

–

0.4

V

0.4

V

63

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E

Table 18. DC Characteristics: Extended Temperature Operation (Continued)

V_PP

Lock-Out

Voltage

V_PP

during

V_PPL

3

0.0 1.5 0.0 1.5 0.0 1.5

4.5 5.5 4.5 5.5 4.5 5.5

V

Complete Write

Protection

K

V_PPH

1

V_PPat 5V

Prog/Eras

e

Operation

s

V_PPH

2

11.4 12. 11.4 12.6 11. 12.6

V

V_PPat 12V

6

4

V_CC

V_LKO

8

2.0

Erase/Wri

te Lock

Voltage

V_HHRP#

Unlock

Voltage

11.4 12. 11.4 12.6 11. 12.6

V

Boot Block Write/

Erase

V_PP= 12V

6

4

Table 19. Capacitance (T_A= 25 °C, f = 1 MHz)

Symbol

Parameter

Notes

Typ

Max

Units

Conditions

C_IN

Input

4

6

8

pF

V_IN= 0V

Capacitance

C_OUT

Output

4

10

12

pF

V_OUT= 0V

Capacitance

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at V_CC= 5.0V, T = +25°C. These currents are valid for all product

versions (packages and speeds).

2. I_CCESis specified with device de-selected. If device is read while in erase suspend, current draw is sum of_CI_CESand I_CCR

.

3. Block erases and word/byte writes inhibited when V_PP= V_PPLK, and not guaranteed in the range between V_PPH1 and V_PPLK

.

4. Sampled, not 100% tested.

5. Automatic Power Savings (APS) reduces I_CCRto less than 1 mA typical, in static operation.

6. CMOS Inputs are either V_CC± 0.2V or GND ± 0.2V. TTL Inputs are either V or V_IH

.

IL

7. For the 28F008B address pin A₁₀follows the C_OUTcapacitance numbers.

8. For all BV/CV/BE/CE parts, V_LKO= 2.0V for 2.7V, 3.3V and 5.0V operations.

64

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2.7

OUTPUT

INPUT

1.35

TEST POINTS

1.35

0.0

0539_18

NOTE:

AC test inputs are driven at 2.7 for a logic “1” and 0.0V for a logic “0.” Input timing begins, and output timing ends, at 1.35V. Input rise

and fall times (10%–90%) <10 ns.

Figure 16. 2.7–3.6V Input Range and Measurement Points

3.0

OUTPUT

INPUT

1.5

TEST POINTS

1.5

0.0

0539_09

NOTE:

AC test inputs are driven at 3.0V for a logic “1” and 0.0V for a logic “0.” Input timing begins, and output timing ends, at 1.5V. Input rise

and fall times (10%–90%) <10 ns.

Figure 17. 3.3V Input Range and Measurement Points

2.4

2.0

0.8

2.0

0.8

INPUT

OUTPUT

TEST POINTS

0.45

0539_10

NOTE:

AC test inputs are driven at V_OH(2.4 V_TTL) for a logic “1” and V_OL(0.45 V_TTL) for a logic “0.” Input timing begins at V_IH(2.0 V_TTL

)

and V_IL(0.8 V_TTL) . Output timing ends at V_IHand V_IL. Input rise and fall times (10%–90%) < 10 ns.

Figure 18. 5V Input Range and Measurement Points

65

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E

Figure 19. Test Configuration

V_CC

Test Configuration Component Values

R

Test Configuration

C_L

R₁

R₂

1

(pF)

(W) (W)

Device

under

Test

2.7V and 3.3V

50

990 770

Out

Standard

Test

C_L

2

5V Standard Test

100

580 390

NOTE:

C_Lincludes jig capacitance.

0539_11

NOTE:

See table for component values.

66

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6.3

AC Characteristics

(1)

Table 20. AC Characteristics: Read Only Operations (Extended Temperature)

Prod TBE-120

TBV-90

TBE-120

(

Sym

Parameter

V_CC

2.7–

3.6V

3.3±0.3V 5V±10% Unit

5)

6)

(5)

s

Loa

d

50 pF

100 pF

Note Mi Ma Mi Ma Mi Ma

s

n

x

n

x

n

x

t_AVAV

t_AVQV

t_ELQV

t_PHQV

Read Cycle Time

120

90

ns

ms

Address to Output Delay

CE# to Output Delay

RP# to Output Delay

120

1.5

120

1.5

90

2

0.4

5

t_GLQV

t_ELQX

t_EHQZ

t_GLQX

t_GHQZ

t_OH

OE# to Output Delay

2

3

65

55

45

65

55

45

40

30

ns

CE# to Output in Low Z

CE# to Output in High Z

OE# to Output in Low Z

OE# to Output in High Z

0

Output Hold from Address,

CE#, or OE# Change,

Whichever Occurs First

t_ELFL

t_ELFH

CE# Low to BYTE# High

or Low

3

5

ns

t_AVFL

Address to BYTE# High or

Low

t_FLQV

t_FHQV

BYTE# to Output Delay

3,4

3

120

45

120

45

90

30

t_FLQZ

BYTE# Low to Output in

High Z

NOTES:

67

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E

1. See AC Input/Output Reference Waveform for timing measurements.

2. OE# may be delayed up to t_CE–t_OEafter the falling edge of CE# without impact on _Ct_E.

3. Sampled, but not 100% tested.

4. t_FLQV, BYTE# switching low to valid output delay will be equal to_At_VQV, measured from the time DQ /A_–1becomes valid.

5. See Test Configurations (Figure19), 2.7–3.6V and 3.3± 0.3V Standard Test component values.

15

6. See Test Configurations (Figure19), 5V Standard Test component values.

68

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(1)

Table 21. AC Characteristics: WE#-Controlled Write Operations (Extended

Temperature)

Prod TBE-120

TBV-90

TBE-120

(

Sym

Parameter

V_CC

2.7–

3.6V

3.3±0.3V 5V±10% Units

9)

10)

(9)

Loa

d

50 pF

100 pF

Note Mi Ma Mi Ma Mi Ma

s

n

x

n

x

n

x

t_AVAV

t_PHWL

Write Cycle Time

120

1.5

120

1.5

90

ns

RP# High Recovery to

WE# Going Low

0.4

5

ms

t_ELWL

CE# Setup to WE# Going

Low

0

ns

t_PHHWH

Boot Block Lock Setup to

WE# Going High

6,8 200

5,8 200

200

100

V_PPSetup to WE#

Going High

t_VPWH

t_AVWH

200

90

100

60

ns

Address Setup to WE#

Going High

3

4

90

70

t_DVWH

Data Setup to WE# Going

High

70

60

ns

t_WLWH

t_WHDX

WE# Pulse Width

90

0

90

0

60

0

ns

Data Hold Time from WE#

High

4

3

t_WHAX

t_WHEH

t_WHWL

Address Hold Time from

WE# High

0

ns

CE# Hold Time from WE#

High

WE# Pulse Width High

30

20

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E

(1)

Table 21. AC Characteristics: WE#-Controlled Write Operations (Extended

Temperature)

t_WHQV1

t_WHQV2

t_WHQV3

t_WHQV4

Duration of Word/Byte

Write Operation

2,5,8

6

µs

Duration of Erase

Operation (Boot)

2,5,6 0.3

, 8

0.3

0.6

0.3

0.6

s

Duration of Erase

Operation (Parameter)

2,5,8 0.3

s

Duration of Erase

Operation (Main)

2,5,8 0.6

s

70

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(1)

Table 21. AC Characteristics: WE#-Controlled Write Operations (Extended

Temperature) (Continued)

Prod TBE-120

TBV-90

TBE-120

(

Sym

Parameter

V_CC

2.7–

3.6V

3.3±0.3V 5V±10% Unit

9)

10)

(9)

Loa

d

50 pF

100 pF

Note Mi Ma Mi Ma Mi Ma

s

n

0

x

n

0

x

n

0

x

V_PPHold from Valid SRD

t_QWL

5,8

6,8

ns

RP# V_HHHold from Valid

SRD

t_QVPH

t_PHBR

Boot-Block Lock Delay

7,8

200

100

ns

NOTES:

1. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC

Characteristics during read mode.

2. The on-chip WSM completely automates program/erase operations; program/erase algotrhims are now controlled internally which

includes verify and margining operations.

3. Refer to command definition table for valid A . (Table 7)

IN

4. Refer to command definition table for valid D . (Table 7)

IN

5. Program/erase durations are measured to valid SRD data (successful operation, SR.7 = 1)

6. For boot block program/erase, RP# should be held at V_HHor WP# should be held at V_IHuntil operation completes successfully.

7. Time t_PHBRis required for successful locking of the boot block.

8. Sampled, but not 100% tested.

9. See Test Configurations (Figure19), 2.7–3.6V and 3.3± 0.3V Standard Test component values.

10. See Test Configurations (Figure19), 5V Standard Test component values.

71

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E

(1,11)

Table 22. AC Characteristics: CE#–Controlled Write Operations

Temperature)

(Extended

Prod TBE-120

TBV-90

TBE-120

(

Sym

Parameter

V_CC

2.7–

3.6V

3.3±0.3V 5V±10% Unit

9)

10)

(9)

Loa

d

50 pF

100 pF

Note Mi Ma Mi Ma Mi Ma

s

n

x

n

x

n

x

t_AVAV

Write Cycle Time

120

1.5

120

1.5

90

ns

t_PHEL

t_WLEL

t_PHHEH

t_VPEH

t_AVEH

t_DVEH

RP# High Recovery to CE#

Going Low

0.4

5

ms

WE# Setup to CE# Going

Low

0

ns

Boot Block Lock Setup to

CE# Going High

6,8 200

5,8 200

90

200

90

100

60

V_PPSetup to CE# Going

High

Address Setup to CE#

Going High

Data Setup to CE# Going

High

3

4

70

60

t_ELEH

t_EHDX

CE# Pulse Width

90

0

90

0

60

0

ns

Data Hold Time from CE#

High

t_EHAX

t_EHWH

Address Hold Time from

CE# High

4

3

0

ns

WE# Hold Time from CE#

High

t_EHEL

CE# Pulse Width High

20

6

20

6

20

6

ns

µs

t_EHQV1

Duration of Word/Byte

Write Operation

2,5

72

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(1,11)

Table 22. AC Characteristics: CE#–Controlled Write Operations

(Extended

Temperature)

t_EHQV2

t_EHQV3

t_EHQV4

Duration of Erase

Operation (Boot)

2,5,6 0.3

0.3

0.6

0.3

0.6

s

Duration of Erase

Operation (Parameter)

2,5

0.3

0.6

Duration of Erase

Operation (Main)

t_QWL

V_PPHold from Valid SRD

5,8

6,8

0

ns

t_QVPH

RP# V_HHHold from Valid

SRD

t_PHBR

Boot-Block Lock Delay

7,8

200

100

ns

NOTES:

See WE# Controlled Write Operations for notes 1 through 10.

11. Chip-Enable controlled writes: write operations are driven by the valid combination of CE# and WE# in systems where CE# defines

the write pulse-width (within a longer WE# timing waveform), all set-up, hold and inactive WE# times should be measured relative

to the CE# waveform.

73

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Table 23. Extended Temperature Operations - Erase and Program Timings

5V ± 10%

12V ± 5%

V_PP

V_CC

2.7–3.6V

3.3 ±

0.3V

5V ±

10%

2.7–3.6V

3.3 ±

0.3V

5V ±

10%

Parameter

Typ Ma Typ Ma Typ Ma Typ Ma Typ Ma Typ Ma Un

x

it

Boot/Parameter 0.88 TB 0.84

7

0.8

7

0.46 TB 0.44

D

7

0.34

7

s

Block Erase

Time

D

Main Block

Erase Time

2.5 TB 2.4 14 1.9 14 1.36 TB 1.3 14 1.1 14

s

D

Main Block

Write Time

(Byte Mode)

1.87

1.21

1.7

1.1

1.4

0.9

1.76

0.88

1.6

0.8

1.2

0.6

Main Block

Write Time

(Word Mode)

s

Byte Write

Time

11

10

13

10

13

8.8

8

µs

Word Write

Time

14.3

NOTES:

1. All numbers are sampled, not 100% tested.

2. Max erase times are specified under worst case conditions. The max erase times are tested at the same value independent of_CV_Cand

V_PP. See Note 3 for typical conditions.

3. Typical conditions are 25°C with V_CCand V_PPat the center of the specifed voltage range. Production programming using

V_CC= 5.0V, V_PP= 12.0V typically results in a 60% reduction in programming time.

4. Contact your Intel representative for information regarding maximum byte/word write specifications.

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ADDITIONAL INFORMATION

Ordering Information

7.0

7.1

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E

E2 8 F 8 0 0CV - T 7 0

Access Speed

Operating Temperature

T = Extended Temp

BE:

BV:

ns,

V_CC= 2.7V

V_CC= 5V

Blank

= Commercial Temp

T =

B =

Top Boot

Bottom Boot

Package

E = TSOP

PA = 44-Lead PSOP

Voltage Options

V

E

(V_PP/ V_CC

= (5 or 12 / 3.3 or 5)

= (5 or 12 / 2.7 or 5)

)

TB

= Ext. Temp 44-Lead PSOP

Product line designator

for all Intel Flash products

Architecture

B

C

= Boot Block

= Compact 48-Lead TSOP

Boot Block

Density / Organization

00X

X00

= x8-only (X = 1, 2, 4, 8)

= x8/x16 Selectable (X = 2, 4, 8)

0530-23

VALID COMBINATIONS:

Commercial

40-Lead TSOP

44-Lead PSOP

48-Lead TSOP

E28F008BVT70

E28F008BVB70

E28F008BVT120

E28F008BVB120

PA28F800BVT70

PA28F800BVB70

PA28F800BVT120

PA28F800BVB120

E28F800CVT70

E28F800CVB70

Extended

TE28F008BVT90

TE28F008BVB90

TB28F800BVT90

TB28F800BVB90

TE28F800CVT90

TE28F800CVB90

TE28F008BET120

TE28F008BEB120

TE28F800CET120

TE28F800CEB120

Table 24. Summary of Line Items

Name

V_CC

V_PP

Package

Temperature

2.7–3.6

3.3±0.3

5 ± 10% 5 ± 10% 12 ± 5%

40-Ld

TSOP

44-Ld

PSOP

48-Ld

TSOP

Comm

Ext

Ö

28F008

BV

Ö

28F800

BV

Ö

28F800

CV

Ö

28F008

BE

Ö

28F800

CE

Ö

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Document

7.2

References

Order

Number

290531

290530

290448

290449

2-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet

4-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet

28F002/200BX-T/B 2-Mbit Boot Block Flash Memory Datasheet

28F002/200BL-T/B 2-Mbit Low Power Boot Block Flash Memory

Datasheet

290450

28F004/400BL-T/B 4-Mbit Low Power Boot Block Flash Memory

Datasheet

290451

292148

28F004/400BX-T/B 4-Mbit Boot Block Flash Memory Datasheet

AP-604 “Using Intel’s Boot Block Flash Memory Parameter Blocks to

Replace

EEPROM”

292172

292130

292154

AP-617 “Additional Flash Data Protection Using V , RP#, and WP#”

PP

AB-57 “Boot Block Architecture for Safe Firmware Updates”

AB-60 “2/4/8-Mbit SmartVoltage Boot Block Flash Memory Family”

7.3

Revision History

-001

-002

Initial release of datasheet, no specifications included

Explanation of WP# on 44-lead PSOP added; AC/DC Specifications

added, including BE product text and 2.7V specifications.

-003

28F800BE row removed from Table 1

Applying V_CCvoltages (Sections 5.1 and 6.1) rewritten for clarity.

Minor cosmetic changes/edits.

77

PRODUCT PREVIEW


型号：	E28F008BVB120
厂家：	INTEL
描述：	8-MBIT (512K X 16, 1024K X 8) SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY 8兆位（ 512K ×16 ， 1024K ×8 ） SmartVoltage BOOT BLOCK闪存系列闪存
文件：	总77页 (文件大小：559K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

E28F008BVB120 [INTEL]

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