BX80547RE2667C/SL7VS

®

Δ

Intel Celeron D Processor 300

Sequence

Datasheet

– On 90 nm Process in the 775-Land Package

December 2005

Document Number: 304092-006

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY

ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN

INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS

ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES

RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER

INTELLECTUAL PROPERTY RIGHT. INTEL PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE SUSTAINING

APPLICATIONS.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

®

The Intel Celeron D processor 300 sequence on 90 nm process and in the 775-land package may contain design defects or errors known as errata

which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Δ

Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across

different processor families. Over time processor numbers will increment based on changes in clock, speed, cache, FSB, or other features, and

increments are not intended to represent proportional or quantitative increases in any particular feature. Current roadmap processor number

progression is not necessarily representative of future roadmaps. See www.intel.com/products/processor_number for details.

Φ

®

Intel Extended Memory 64 Technology (Intel EM64T) requires a computer system with a processor, chipset, BIOS, operating system, device

drivers and applications enabled for Intel EM64T. Processor will not operate (including 32-bit operation) without an Intel EM64T-enabled BIOS.

Performance will vary depending on your hardware and software configurations. See http://www.intel.com/info/em64t for more information including

details on which processors support EM64T or consult with your system vendor for more information.

Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system.

Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Intel, Celeron, Pentium, Itanium, Intel Xeon, Intel NetBurst and the Intel logo are trademarks or registered trademarks of Intel Corporation or its

subsidiaries in the United States and other countries.

*Other names and brands may be claimed as the property of others.

2

Datasheet

Contents

1

Introduction.......................................................................................................................11

1.1

Terminology.........................................................................................................12

1.1.1 Processor Packaging Terminology.........................................................12

References..........................................................................................................13

1.2

2

Electrical Specifications....................................................................................................15

2.1

2.2

2.3

FSB and GTLREF ...............................................................................................15

Power and Ground Lands ...................................................................................15

Decoupling Guidelines ........................................................................................15

2.3.1 VCC Decoupling.....................................................................................16

2.3.2 FSB GTL+ Decoupling ...........................................................................16

2.3.3 FSB Clock (BCLK[1:0]) and Processor Clocking....................................16

Voltage Identification...........................................................................................17

2.4.1 Phase Lock Loop (PLL) Power and Filter...............................................19

Reserved, Unused, and TESTHI Signals............................................................20

FSB Signal Groups..............................................................................................20

GTL+ Asynchronous Signals...............................................................................22

Test Access Port (TAP) Connection....................................................................23

FSB Frequency Select Signals (BSEL[2:0])........................................................23

Absolute Maximum and Minimum Ratings..........................................................23

Processor DC Specifications...............................................................................24

2.11.1 Processor DC Specifications..................................................................24

VCC Overshoot Specification..............................................................................30

2.12.1 Die Voltage Validation............................................................................30

GTL+ FSB Specifications....................................................................................31

2.4

2.5

2.6

2.7

2.8

2.9

2.10

2.11

2.12

2.13

3

Package Mechanical Specifications.................................................................................33

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

Package Mechanical Drawing.............................................................................33

Processor Component Keep-Out Zones .............................................................37

Package Loading Specifications .........................................................................37

Package Handling Guidelines .............................................................................37

Package Insertion Specifications ........................................................................38

Processor Mass Specification .............................................................................38

Processor Materials.............................................................................................38

Processor Markings.............................................................................................38

Processor Land Coordinates...............................................................................40

4

5

Land Listing and Signal Descriptions ...............................................................................41

4.1

4.2

Processor Land Assignments..............................................................................41

Alphabetical Signals Reference ..........................................................................62

Thermal Specifications and Design Considerations.........................................................71

5.1

5.2

Processor Thermal Specifications.......................................................................71

5.1.1 Thermal Specifications...........................................................................71

5.1.2 Thermal Metrology .................................................................................74

Processor Thermal Features...............................................................................74

5.2.1 Thermal Monitor .....................................................................................74

Datasheet

3

5.2.2 Thermal Monitor 2 ..................................................................................75

5.2.3 On-Demand Mode..................................................................................76

5.2.4 PROCHOT# Signal ................................................................................77

5.2.5 THERMTRIP# Signal .............................................................................77

5.2.6

T

and Fan Speed Reduction ....................................................77

CONTROL

5.2.7 Thermal Diode........................................................................................78

6

7

Features...........................................................................................................................79

6.1

6.2

Power-On Configuration Options ........................................................................79

Clock Control and Low Power States..................................................................79

6.2.1 Normal State ..........................................................................................80

6.2.2 HALT Powerdown State.........................................................................80

6.2.3 Stop-Grant States ..................................................................................81

6.2.4 HALT Snoop State, Grant Snoop State .................................................81

Boxed Processor Specifications.......................................................................................83

7.1

Mechanical Specifications...................................................................................84

7.1.1 Boxed Processor Cooling Solution Dimensions.....................................84

7.1.2 Boxed Processor Fan Heatsink Weight..................................................86

7.1.3 Boxed Processor Retention Mechanism and Heatsink Attach

Clip Assembly ........................................................................................86

Electrical Requirements ......................................................................................86

7.2.1 Fan Heatsink Power Supply...................................................................86

Thermal Specifications........................................................................................88

7.3.1 Boxed Processor Cooling Requirements ...............................................88

7.3.2 Variable Speed Fan ...............................................................................90

7.2

7.3

8

Debug Tools Specifications..............................................................................................93

8.1

Logic Analyzer Interface (LAI).............................................................................93

8.1.1 Mechanical Considerations ....................................................................93

8.1.2 Electrical Considerations........................................................................93

4

Datasheet

Figures

2-1

2-2

2-3

3-1

3-2

3-3

3-4

3-5

3-6

3-7

4-1

4-2

5-1

5-2

5-3

6-1

7-1

7-2

7-3

7-4

7-5

7-6

7-7

7-8

7-9

Phase Lock Loop (PLL) Filter Requirements ......................................................19

VCC Static and Transient Tolerance for 775_VR_CONFIG_04A .......................27

VCC Overshoot Example Waveform...................................................................30

Processor Package Assembly Sketch.................................................................33

Processor Package Drawing 1............................................................................34

Processor Package Drawing 2............................................................................35

Processor Package Drawing 3............................................................................36

Processor Top-Side Marking Example (with Processor Number).......................38

Processor Top-Side Marking Example................................................................39

Processor Land Coordinates (Top View) ............................................................40

Landout Diagram (Top View – Left Side) ............................................................42

Landout Diagram (Top View – Right Side)..........................................................43

Thermal Profile for Platform Compatibility Guide ‘04 A Processors....................73

Case Temperature (TC) Measurement Location.................................................74

Thermal Monitor 2 Frequency and Voltage Ordering..........................................76

Processor Low Power State Machine .................................................................80

Mechanical Representation of the Boxed Processor ..........................................83

Space Requirements for the Boxed Processor (Side View)................................84

Space Requirements for the Boxed Processor (Top View).................................85

Space Requirements for the Boxed Processor (Overall View)............................85

Boxed Processor Fan Heatsink Power Cable Connector Description.................87

Baseboard Power Header Placement Relative to Processor Socket..................88

Boxed Processor Fan Heatsink Airspace Keep-out Requirements (Top View) ..89

Boxed Processor Fan Heatsink Airspace Keep-out Requirements (Side View) .89

Boxed Processor Fan Heatsink Set Points .........................................................90

Datasheet

5

Tables

1-1

2-1

2-2

2-3

2-4

2-5

2-6

2-7

2-8

2-9

2-10

2-11

2-12

2-13

2-14

2-15

2-16

2-17

3-1

3-2

3-3

4-1

4-2

4-3

References..........................................................................................................13

Core Frequency to FSB Multiplier Configuration.................................................16

Voltage Identification Definition...........................................................................18

FSB Signal Groups .............................................................................................21

Signal Characteristics .........................................................................................22

Signal Reference Voltages..................................................................................22

BSEL[2:0] Frequency Table for BCLK[1:0] .........................................................23

Processor DC Absolute Maximum Ratings.........................................................24

Voltage and Current Specifications.....................................................................25

VCC Static and Transient Tolerance for 775_VR_CONFIG_04A Processors....26

GTL+ Asynchronous Signal Group DC Specifications.......................................28

GTL+ Signal Group DC Specifications................................................................28

PWRGOOD and TAP Signal Group DC Specifications ......................................29

VTTPWRGD DC Specifications ..........................................................................29

BSEL [2:0] and VID[5:0] DC Specifications.........................................................29

BOOTSELECT DC Specifications.......................................................................29

VCC Overshoot Specifications............................................................................30

GTL+ Bus Voltage Definitions.............................................................................31

Processor Loading Specifications.......................................................................37

Package Handling Guidelines.............................................................................37

Processor Materials ............................................................................................38

Alphabetical Land Assignments..........................................................................44

Numerical Land Assignments .............................................................................53

Signal Description ...............................................................................................62

Processor Thermal Specifications.......................................................................72

Thermal Profile for Processors............................................................................73

Thermal Diode Parameters .................................................................................78

Thermal Diode Interface......................................................................................78

Power-On Configuration Option Signals .............................................................79

Fan Heatsink Power and Signal Specifications...................................................87

Boxed Processor Fan Heatsink Set Points .........................................................91

5-1

5-2

5-3

5-4

6-1

7-1

7-2

6

Datasheet

Revision History

Revision

Number

Description

Date

-001

-002

-003

•

Initial release

September 2004

November 2004

December 2004

Added 3.06 GHz processor

Updated Clock Control and Low Power States section in chapter 6

Added support for processor numbers 346, 341, 336, 331, and 326

•

Added the letter “J” to processor numbers 345J, 340J, 335J, 330J and

325J

-004

June 2005

•

Added EM64T support

-005

-006

Added support for processor number 351

Added support for processor number 355

June 2005

December 2005

§

Datasheet

7

8

Datasheet

Intel^®Celeron^®D Processor 300 Sequence

Features

Available at 3.33 GHz, 3.20 GHz,

3.06 GHz, 2.93 GHz, 2.80 GHz, 2.66 GHz,

and 2.53 GHz

Binary compatible with applications

running on previous members of the Intel

microprocessor line

FSB frequencies at 533 MHz

Hyper-Pipelined Technology

—Advance Dynamic Execution

—Very deep out-of-order execution

Enhanced branch prediction

16-KB Level 1 data cache

256-KB Advanced Transfer Cache (on-die,

full-speed Level 2 (L2) cache) with 4-way

associativity and Error Correcting Code

(ECC)

144 Streaming SIMD Extensions 2 (SSE2)

instructions

Supports Execute Disable Bit capability

13 Streaming SIMD Extensions 3 (SSE3)

instructions

Power Management capabilities

—System Management mode

—Multiple low-power states

Optimized for 32-bit applications running

on advanced 32-bit operating systems

775-Land Package

®

The Intel Celeron D processor family expands Intel’s processor family into the value-priced PC

market segment. Celeron D processors provide the value that offers the customer the capability to

affordably get onto the Internet, and use educational programs, home-office software, and

productivity applications. All of the Celeron D processors include an integrated L2 cache, and are

built on Intel’s advanced CMOS process technology. The Celeron D processor is backed by over

30 years of Intel experience in manufacturing high-quality, reliable microprocessors.

®

Intel Extended Memory 64 Technology (Intel EM64T) enables Celeron D processors to execute

operating systems and applications written to take advantage of the Intel EM64T.

The Celeron D processor also includes the Execute Disable Bit capability. This feature, combined

with a supported operating system, allows memory to be marked as executable or non-executable.

§

Datasheet

9

10

Datasheet

Introduction

1 Introduction

®

The Intel Celeron D processor 300 sequence on 90 nm process and in the 775-land package is a

®

follow-on to the Intel Celeron D processor in the 478-pin package. This processor uses Flip-

Chip Land Grid Array (FC-LGA4) package technology, and plugs into a 775-land LGA socket,

referred to as the LGA775 socket. LGA775 is required to support higher frequency processors.

This next generation of socket provides longevity for processor support beyond 2004. LGA775

designs support the Celeron D processor providing great flexibility and breadth of processor

choices.

The Intel Celeron D processor 300 sequence on 90 nm process in the 775-land package supports

Φ

®

Intel Extended Memory 64 Technology (Intel EM64T) as an enhancement to Intel’s IA-32

architecture. This enhancement enables the processor to execute operating systems and

applications written to take advantage of Intel EMT64T. With appropriate 64 bit supporting

hardware and software, platforms based on an Intel processor supporting Intel EM64T can enable

use of extended virtual and physical memory. Further details on the 64-bit extension architecture

®

and programming model is provided in the Intel Extended Memory 64 Technology Software

Developer Guide at http://developer.intel.com/technology/64bitextensions/.

Note: In this document the Celeron D processor on 90 nm process and in the 775-land package is also

referred to as Celeron D processor in the 775-land package or as the “processor”.

®

Note: In this document, unless otherwise specified, the Intel Celeron D processor 300 sequence refers

to Intel Celeron D processors 355, 351, 345J/346, 340J/341, 335J/336, 330J/331, and 325J/326.

®

Note: Intel Celeron D processors 355, 351, 346, 341, 336, 331, and 326 support Intel Extended

Memory 64 Technology (Intel EM64T)

The Celeron D processor in the 775-land package, like its predecessor, the Celeron D processor in

the 478-pin package, is based on the same Intel 32-bit microarchitecture and maintains the tradition

of compatibility with IA-32 software. It maintains the same Front Side Bus (FSB) data transfer

speed at 533 MT/s and Level 2 cache size of 256 KB.

The Celeron D Processor in the 775-Land Package includes the Execute Disable Bit capability

®

previously available in Intel Itanium processors. This feature, combined with a supported

operating system, allows memory to be marked as executable or nonexecutable. If code attempts to

run in non-executable memory, the processor generates an error to the operating system. This

feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and

®

can, thus, help improve the overall security of the system. See the Intel Architecture Software

Developer's Manual for more detailed information.

Intel will enable support components for the processor including heatsink, heatsink retention

mechanism, and socket. Manufacturability is a high priority; hence, mechanical assembly may be

completed from the top of the baseboard and should not require any special tooling.

The processor includes an address bus powerdown capability that removes power from the address

and data pins when the FSB is not in use. This feature is always enabled on the processor.

Datasheet

11

Introduction

1.1

Terminology

A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the active

state when driven to a low level. For example, when RESET# is low, a reset has been requested.

Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where

the name does not imply an active state but describes part of a binary sequence (such as address or

data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a

hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).

“FSB” refers to the interface between the processor and system core logic (a.k.a. the chipset

components). The FSB is a multiprocessing interface to processors, memory, and I/O.

1.1.1

Processor Packaging Terminology

Commonly used terms are explained here for clarification:

®

• Intel Celeron D processor in the 775-land package — Processor in the FC-LGA4

package with a 256 KB L2 cache.

• Processor — For this document, the term “processor” is the generic form of the Celeron D

processor in the 775-land package.

• Keep-out zone — The area on or near the processor that system design can not use.

®

• Intel 915G\915GV\910GL and 915P/915PL Express chipset — Chipsets that support

DDR and DDR2 memory technology for the Celeron D processor in the 775-land package.

• Processor core — Processor core die with integrated L2 cache.

• FC-LGA4 package — The Celeron D processor in the 775-land package is available in a

Flip-Chip Land Grid Array 4 package, consisting of a processor core mounted on a substrate

with an integrated heat spreader (IHS).

• LGA775 socket — The Celeron D processor in the 775-land package mates with the system

board through a surface mount, 775-land, LGA socket.

• Integrated heat spreader (IHS) —A component of the processor package used to enhance

the thermal performance of the package. Component thermal solutions interface with the

processor at the IHS surface.

• Retention mechanism (RM)—Since the LGA775 socket does not include any mechanical

features for heatsink attach, a retention mechanism is required. Component thermal solutions

should attach to the processor via a retention mechanism that is independent of the socket.

• Storage conditions—Refers to a non-operational state. The processor may be installed in a

platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air.

Under these conditions, processor lands should not be connected to any supply voltages, have

any I/Os biased, or receive any clocks. Upon exposure to “free air” (i.e., unsealed packaging or

a device removed from packaging material) the processor must be handled in accordance with

moisture sensitivity labeling (MSL) as indicated on the packaging material.

• Functional operation—Refers to normal operating conditions in which all processor

specifications, including DC, AC, system bus, signal quality, mechanical and thermal, are

satisfied.

12

Datasheet

Introduction

1.2

References

Material and concepts available in the following documents may be beneficial when reading this

document.

Table 1-1. References

Document Numbers/

Location

Document

http://developer.intel.com/

design/Pentium4/guides/

302553.htm

Intel^®Pentium^®4 Processor on 90 nm Process in the 775-Land LGA Package

Thermal Design Guide

http://developer.intel.com/

Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket design/Pentium4/guides/

302356.htm

http://developer.intel.com/

LGA775 Socket Mechanical Design Guide

design/pentium4/guides/

302666.htm

Intel^®Architecture Software Developer's Manual

IA-32 Intel^®Architecture Software Developer's Manual Volume 1: Basic

Architecture

IA-32 Intel^®Architecture Software Developer's Manual Volume 2A: Instruction http://developer.intel.com/

Set Reference Manual A–M

design/pentium4/

manuals/index_new.htm

IA-32 Intel^®Architecture Software Developer's Manual Volume 2B: Instruction

Set Reference Manual, N–Z

IA-32 Intel^®Architecture Software Developer's Manual Volume 3: System

Programming Guide

http://developer.intel.com/

design/pentium4/

manuals/index_new.htm

IA-32 Intel^®Architecture and Intel^®Extended Memory 64 Software

Developer's Manual Documentation Changes

§

Datasheet

13

Introduction

14

Datasheet

Electrical Specifications

2 Electrical Specifications

This chapter describes the electrical characteristics of the processor interfaces and signals. DC

electrical characteristics are provided.

2.1

FSB and GTLREF

Most processor FSB signals use Gunning Transceiver Logic (GTL+) signaling technology.

Platforms implement a termination voltage level for GTL+ signals defined as V . V must be

TT TT

provided via a separate voltage source and not be connected to V . This configuration allows for

CC

improved noise tolerance as processor frequency increases. Because of the speed improvements to

the data and address bus, signal integrity and platform design methods have become more critical

than with previous processor families.

The GTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to

determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the system board

(see Table 2-17 for GTLREF specifications). Termination resistors are provided on the processor

silicon and are terminated to V . Intel chipsets will also provide on-die termination, thus

TT

eliminating the need to terminate the bus on the system board for most GTL+ signals.

Some GTL+ signals do not include on-die termination and must be terminated on the system board.

See Table 2-4 for details regarding these signals.

The GTL+ bus depends on incident wave switching. Therefore timing calculations for GTL+

signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the

FSB, including trace lengths, is highly recommended when designing a system.

2.2

2.3

Power and Ground Lands

For clean on-chip power distribution, the Celeron D processor in the 775-land package has

226 VCC (power), 24 VTT and 273 VSS (ground) lands. All power lands must be connected to

V

, all VTT lands must be connected to V , while all VSS lands must be connected to a system

CC

TT

ground plane. The processor VCC lands must be supplied by the voltage determined by the Voltage

IDentification (VID) signals.

Decoupling Guidelines

Due to its large number of transistors and high internal clock speeds, the processor is capable of

generating large current swings between low and full power states. This may cause voltages on

power planes to sag below their minimum values if bulk decoupling is not adequate. Care must be

taken in the board design to ensure that the voltage provided to the processor remains within the

specifications listed in Table 2-8. Failure to do so can result in timing violations or reduced lifetime

of the component. For further information, refer to the Voltage Regulator Down (VRD) 10.1 Design

Guide For Desktop LGA775 Socket.

Datasheet

15

Electrical Specifications

2.3.1

V_CCDecoupling

Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR)

and keep a low interconnect resistance from the regulator to the socket. Bulk decoupling for the

large current swings when the part is powering on, or entering/exiting low power states, must be

provided by the voltage regulator solution (VR). For more details, refer to the Voltage Regulator

Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket.

2.3.2

2.3.3

FSB GTL+ Decoupling

The Celeron D processor in the 775-land package integrates signal termination on the die as well as

incorporating high frequency decoupling capacitance on the processor package. Decoupling must

also be provided by the system baseboard for proper GTL+ bus operation.

FSB Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor.

As in previous generation processors, the Celeron D processor in the 775-land package core

frequency is a multiple of the BCLK[1:0] frequency. Refer to Table 2-1 for the Celeron D

processor in the 775-land package supported ratios.

The Celeron D processor in the 775-land package uses a differential clocking implementation. For

more information on the Celeron D processor in the 775-land package clocking, refer to the

CK410/CK410M Clock Synthesizer/Driver Specification.

Table 2-1. Core Frequency to FSB Multiplier Configuration

Multiplication of System Core Processor Core Frequency (133 MHz BCLK

Notes¹

Frequency to FSB Frequency

Number

/ 533 MHz FSB)

1/19

325J/326

330J/331

335J/336

340J/341

345J/346

351

2.53 GHz

2.66 GHz

2.80 GHz

2.93 GHz

3.06 GHz

3.20 GHz

3.33 GHz

—

1/20

1/21

1/22

1/23

1/24

1/25

355

NOTES:

1.

Individual processors operate only at or below the rated frequency.

16

Datasheet

Electrical Specifications

2.4

Voltage Identification

The VID specification for the Celeron D processor in the 775-land package is supported by the

Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket. The voltage set

by the VID signals is the maximum voltage allowed by the processor. A minimum voltage is

provided in Table 2-8 and changes with frequency. This allows processors running at a higher

frequency to have a relaxed minimum voltage specification. The specifications have been set such

that one voltage regulator can work with all supported frequencies.

Individual processor VID values may be calibrated during manufacturing such that two devices at

the same speed may have different VID settings.

The Celeron D processor in the 775-land package uses six voltage identification signals, VID[5:0],

to support automatic selection of power supply voltages. Table 2-2 specifies the voltage level

corresponding to the state of VID[5:0]. A ‘1’ in this table refers to a high voltage level and a ‘0’

refers to low voltage level. If the processor socket is empty (VID[5:0] = x11111), or the voltage

regulation circuit cannot supply the voltage that is requested, it must disable itself. See the Voltage

Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket for more details.

Power source characteristics must be guaranteed to be stable when the supply to the voltage

regulator is stable.

The LL_ID[1:0] lands are used by the platform to configure the proper loadline slope for the

processor. LL_ID[1:0] = 00 for the Celeron D processor in the 775-land package.

The VTT_SEL land is used by the platform to configure the proper V voltage level for the

TT

processor. VTT_SEL = 1 for the Celeron D processor in the 775-land package.

The GTLREF_SEL signal is used by the platform to select the appropriate chipset GTLREF level.

GTLREF_SEL = 0 for the Celeron D processor in the 775-land package.

The VID_SELECT signal is used by the platform to select the VID table that is to be used by the

voltage regulator.

LL_ID[1:0], VTT_SEL, GTLREF_SEL, and VID_SELECT are signals that are implemented on

the processor package. That is they are either connected directly to V or are open lands.

SS

Datasheet

17

Electrical Specifications

Table 2-2. Voltage Identification Definition

VID5

VID4

VID3

VID2

VID1

VID0

VID

VID5

VID4

VID3

VID2

VID1

VID0

VID

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0.8375

0.8500

0.8625

0.8750

0.8875

0.9000

0.9125

0.9250

0.9375

0.9500

0.9625

0.9750

0.9875

1.0000

1.0125

1.0250

1.0375

1.0500

1.0625

1.0750

1.0875

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1.2125

1.2250

1.2375

1.2500

1.2625

1.2750

1.2875

1.3000

1.3125

1.3250

1.3375

1.3500

1.3625

1.3750

1.3875

1.4000

1.4125

1.4250

1.4375

1.4500

1.4625

VR output

off

1

0

1

0

1

1.4750

1.4875

VR output

off

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1.1000

1.1125

1.1250

1.1375

1.1500

1.1625

1.1750

1.1875

1.2000

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1.5000

1.5125

1.5250

1.5375

1.5500

1.5625

1.5750

1.5875

1.6000

18

Datasheet

Electrical Specifications

2.4.1

Phase Lock Loop (PLL) Power and Filter

V

and V

are power sources required by the PLL clock generators for the Celeron D

CCIOPLL

CCA

processor in the 775-land package. Since these PLLs are analog, they require low noise power

supplies for minimum jitter. Jitter is detrimental to the system: it degrades external I/O timings as

well as internal core timings (i.e., maximum frequency). To prevent this degradation, these supplies

must be low pass filtered from V .

TT

The AC low-pass requirements, with input at V are as follows:

TT

• < 0.2 dB gain in pass band

• < 0.5 dB attenuation in pass band < 1 Hz

• > 34 dB attenuation from 1 MHz to 66 MHz

• > 28 dB attenuation from 66 MHz to core frequency

The filter requirements are illustrated in Figure 2-1.

.

Figure 2-1. Phase Lock Loop (PLL) Filter Requirements

0.2 dB

0 dB

–0.5 dB

Forbidden

Zone

Forbidden

Zone

–28 dB

–34 dB

DC

1 Hz

Passband

fpeak

1 MHz

66 MHz

fcore

High

Frequency

Band

Filter_Spec

NOTES:

1. Diagram not to scale.

2. No specification exists for frequencies beyond fcore (core frequency).

3. fpeak, if existent, should be less than 0.05 MHz.

Datasheet

19

Electrical Specifications

2.5

Reserved, Unused, and TESTHI Signals

All RESERVED signals must remain unconnected. Connection of these signals to V ,V , V

CC SS

TT,

or to any other signal (including each other) can result in component malfunction or

incompatibility with future processors. See Chapter 4 for a land listing of the processor and the

location of all RESERVED signals.

For reliable operation, always connect unused inputs or bidirectional signals to an appropriate

signal level. In a system level design, on-die termination has been included on the Celeron D

processor in the 775-land package to allow signals to be terminated within the processor silicon.

Most unused GTL+ inputs should be left as no connects, as GTL+ termination is provided on the

processor silicon. However, see Table 2-4 for details on GTL+ signals that do not include on-die

termination. Unused active high inputs should be connected through a resistor to ground (V ).

SS

Unused outputs can be left unconnected; however, this may interfere with some test access port

(TAP) functions, complicate debug probing, and prevent boundary scan testing. A resistor must be

used when tying bidirectional signals to power or ground. When tying any signal to power or

ground, a resistor will also allow for system testability. For unused GTL+ input or I/O signals, use

pull-up resistors of the same value as the on-die termination resistors (R_TT). Refer to Table 2-17 for

more details.

TAP, GTL+ Asynchronous inputs, and GTL+ Asynchronous outputs do not include on-die

termination. Inputs and used outputs must be terminated on the system board. Unused outputs may

be terminated on the system board or left unconnected. Note that leaving unused outputs

unterminated may interfere with some TAP functions, complicate debug probing, and prevent

boundary scan testing.

The TESTHI signals must be tied to the processor V using a matched resistor, where a matched

TT

resistor has a resistance value within ±20% of the impedance of the board transmission line traces.

For example, if the trace impedance is 60 Ω, then a value between 48 Ω and 72 Ω is required.

The TESTHI signals may use individual pull-up resistors or be grouped together as detailed below.

A matched resistor must be used for each group:

• TESTHI[1:0]

• TESTHI[7:2]

• TESTHI8 – cannot be grouped with other TESTHI signals

• TESTHI9 – cannot be grouped with other TESTHI signals

• TESTHI10 – cannot be grouped with other TESTHI signals

• TESTHI11 – cannot be grouped with other TESTHI signals

• TESTHI12 – cannot be grouped with other TESTHI signals

• TESTHI13 – cannot be grouped with other TESTHI signals

2.6

FSB Signal Groups

The FSB signals have been combined into groups by buffer type. GTL+ input signals have

differential input buffers, which use GTLREF as a reference level. In this document, the term

"GTL+ Input" refers to the GTL+ input group as well as the GTL+ I/O group when receiving.

Similarly, "GTL+ Output" refers to the GTL+ output group as well as the GTL+ I/O group when

driving.

20

Datasheet

Electrical Specifications

With the implementation of a source synchronous data bus comes the need to specify two sets of

timing parameters. One set is for common clock signals which are dependent upon the rising edge

of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals

which are relative to their respective strobe lines (data and address) as well as the rising edge of

BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at

any time during the clock cycle. Table 2-3 identifies which signals are common clock, source

synchronous, and asynchronous.

Table 2-3. FSB Signal Groups

Signal Group

Type

Signals¹

Synchronous to

BCLK[1:0]

GTL+ Common Clock Input

BPRI#, DEFER#, RS[2:0]#, RSP#, TRDY#, EDRDY#²

Synchronous to

BCLK[1:0]

AP[1:0]#, ADS#, BINIT#, BNR#, BPM[5:0]#, BR0#, DBSY#,

DP[3:0]#, DRDY#, HIT#, HITM#, LOCK#, MCERR#

GTL+ Common Clock I/O

Signals

Associated Strobe

REQ[4:0]#, A[16:3]#³

PC_REQ#^{2, 4}

ADSTB0#

A[35:17]#³

ADSTB1#

Synchronous to assoc.

strobe

GTL+ Source Synchronous I/O

D[15:0]#, DBI0#

D[31:16]#, DBI1#

D[47:32]#, DBI2#

D[63:48]#, DBI3#

DSTBP0#, DSTBN0#

DSTBP1#, DSTBN1#

DSTBP2#, DSTBN2#

DSTBP3#, DSTBN3#

Synchronous to

BCLK[1:0]

GTL+ Strobes

ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#

A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#,

STPCLK#, RESET#

GTL+ Asynchronous Input

GTL+ Asynchronous Output

GTL+ Asynchronous Input/Output

TAP Input

FERR#/PBE#, IERR#, THERMTRIP#

PROCHOT#

Synchronous to TCK

Clock

TCK, TDI, TMS, TRST#

TDO

TAP Output

FSB Clock

BCLK[1:0], ITP_CLK[1:0]⁵

VCC, VTT, VCCA, VCCIOPLL, VID[7:0], VSS, VSSA,

GTLREF[1:0], COMP[5:0], RESERVED, TESTHI[13:0],

THERMDA, THERMDC, VCC_SENSE, VSS_SENSE,

BSEL[2:0], SKTOCC#, DBR#⁵, VTTPWRGD, BOOTSELECT,

PWRGOOD, VTT_OUT_LEFT, VTT_OUT_RIGHT, VTT_SEL,

LL_ID[1:0], VID_SELECT, GTLREF_SEL

Power/Other

NOTES:

1. Refer to Section 4.2 for signal descriptions.

2. EDRDY# and PC_REQ# are not features of the Celeron D processor in the 775-land package. They are

included here for future processor compatibility.

3. The value of these signals during the active-to-inactive edge of RESET# defines the processor configuration

options. See Section 6.1 for details.

4. PC_REQ# is driven by the processor as Common Clock (1X); however, it must be received at the chipset as

Source Synchronous and associated with ADSTB0#.

5. In processor systems where there is no debug port implemented on the system board, these signals are used

to support a debug port interposer. In systems with the debug port implemented on the system board, these

signals are no connects.

Datasheet

21

Electrical Specifications

Table 2-4. Signal Characteristics

Signals with R_TT

Signals with no R_TT

A20M#, BCLK[1:0], BPM[5:0]#, BR0#, BSEL[2:0],

COMP[5:0], FERR#/PBE#, IERR#, IGNNE#,

INIT#, LINT0/INTR, LINT1/NMI, PWRGOOD,

RESET#, SKTOCC#, SMI#, STPCLK#, TDO,

TESTHI[13:0], THERMDA, THERMDC,

THERMTRIP#, VID[5:0], VTTPWRGD,

A[35:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#,

BNR#, BOOTSELECT¹, BPRI#, D[63:0]#, DBI[3:0]#,

DBSY#, DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#,

DSTBP[3:0]#, HIT#, HITM#, LOCK#, MCERR#,

PROCHOT#, REQ[4:0]#, RS[2:0]#, RSP#, TRDY#,

EDRDY#², PC_REQ#²

GTLREF[1:0], TCK, TDI, TRST#, TMS

Open Drain Signals³

BSEL[2:0], VID[7:0], THERMTRIP#, FERR#/PBE#,

IERR#, BPM[5:0]#, BR0#, TDO, VTT_SEL, LL_ID[1:0],

MS_ID[1:0], GTLREF_SEL, VID_SELECT

NOTES:

1.

2.

The BOOTSELECT signal has a 500–5000 Ω pull-up to V rather than on-die termination.

TT

EDRDY# and PC_REQ# are not features of the Celeron D processor in the 775-land package. They are included here for

future processor compatibility.

3.

Signals that do not have R , nor are actively driven to their high-voltage level.

TT

.

Table 2-5. Signal Reference Voltages

GTLREF

V_TT/2

BPM[5:0]#, LINT0/INTR, LINT1/NMI, RESET#, BINIT#,

BNR#, HIT#, HITM#, MCERR#, PROCHOT#, BR0#,

A[35:0]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BPRI#, D[63:0]#,

DBI[3:0]#, DBSY#, DEFER#, DP[3:0]#, DRDY#,

DSTBN[3:0]#, DSTBP[3:0]#, LOCK#, REQ[4:0]#, RS[2:0]#,

RSP#, TRDY#, EDRDY#¹, PC_REQ#¹

BOOTSELECT, VTTPWRGD, A20M#,

IGNNE#, INIT#, PWRGOOD², SMI#,

STPCLK#, TCK², TDI², TMS², TRST#²

NOTES:

1.

EDRDY# and PC_REQ# are not features of the Celeron D processor in the 775-land package. They are included here for

future processor compatibility.

2.

These signals also have hysteresis added to the reference voltage. See Table 2-12 for more information.

2.7

GTL+ Asynchronous Signals

Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS input

buffers. All of these signals follow the same DC requirements as GTL+ signals; however, the

outputs are not actively driven high (during a logical 0 to 1 transition) by the processor. These

signals do not have setup or hold time specifications in relation to BCLK[1:0].

All of the GTL+ Asynchronous signals are required to be asserted/de-asserted for at least six

BCLKs for the processor to recognize the proper signal state. See Section 2.11 for the DC

specifications for the GTL+ Asynchronous signal groups. See Section 6.2 for additional timing

requirements for entering and leaving the low power states.

22

Datasheet

Electrical Specifications

2.8

2.9

Test Access Port (TAP) Connection

Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is

recommended that the Celeron D processor in the 775-land package be first in the TAP chain and

followed by any other components within the system. A translation buffer should be used to

connect to the rest of the chain unless one of the other components is capable of accepting an input

of the appropriate voltage level. Similar considerations must be made for TCK, TMS, TRST#, TDI,

and TDO. Two copies of each signal may be required, with each driving a different voltage level.

FSB Frequency Select Signals (BSEL[2:0])

The BSEL[2:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]).

Table 2-6 defines the possible combinations of the signals and the frequency associated with each

combination. The required frequency is determined by the processor, chipset, and clock

synthesizer. All agents must operate at the same frequency.

The Celeron D processor in the 775-land package currently operates at a 533 MHz FSB frequency

(selected by a 133 MHz BCLK[1:0] frequency). Individual processors will only operate at their

specified FSB frequency.

For more information about these signals, refer to Section 4.2.

Table 2-6. BSEL[2:0] Frequency Table for BCLK[1:0]

BSEL2

BSEL1

BSEL0

FSB Frequency

L

H

L

Reserved

133 MHz

Reserved

L

H

L

H

L

H

L

H

2.10

Absolute Maximum and Minimum Ratings

Table 2-7 specifies absolute maximum and minimum ratings. Within functional operation limits,

functionality and long-term reliability can be expected.

At conditions outside functional operation condition limits, but within absolute maximum and

minimum ratings, neither functionality nor long-term reliability can be expected. If a device is

returned to conditions within functional operation limits after having been subjected to conditions

outside these limits, but within the absolute maximum and minimum ratings, the device may be

functional, but with its lifetime degraded depending on exposure to conditions exceeding the

functional operation condition limits.

Datasheet

23

Electrical Specifications

At conditions exceeding absolute maximum and minimum ratings, neither functionality nor long-

term reliability can be expected. Moreover, if a device is subjected to these conditions for any

length of time then, when returned to conditions within the functional operating condition limits, it

will either not function, or its reliability will be severely degraded.

Although the processor contains protective circuitry to resist damage from static electric discharge,

precautions should always be taken to avoid high static voltages or electric fields.

Table 2-7. Processor DC Absolute Maximum Ratings

Symbol

V_CC

Parameter

Min

Max

Unit

Notes^{1, 2}

Core voltage with respect to

V_SS

- 0.3

1.55

V

—

FSB termination voltage with

respect to V_SS

V_TT

- 0.3

1.55

V

—

T_C

Processor case temperature

Processor storage temperature

See Chapter 5

–40

See Chapter 5

+85

°C

—

3, 4

T_STORAGE

NOTES:

1.

2.

3.

For functional operation, all processor electrical, signal quality, mechanical and thermal specifications must be satisfied.

Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor.

Storage temperature is applicable to storage conditions only. In this scenario, the processor must not receive a clock, and

no lands can be connected to a voltage bias. Storage within these limits will not affect the long-term reliability of the device.

For functional operation, refer to the processor case temperature specifications.

4.

This rating applies to the processor and does not include any tray or packaging.

2.11

Processor DC Specifications

The processor DC specifications in this section are defined at the processor core silicon and

not at the package lands unless noted otherwise. See Chapter 4 for the signal definitions and

signal assignments. Most of the signals on the processor FSB are in the GTL+ signal group. The

DC specifications for these signals are listed in Table 2-11.

Previously, legacy signals and Test Access Port (TAP) signals to the processor used low-voltage

CMOS buffer types. However, these interfaces now follow DC specifications similar to GTL+. The

DC specifications for these signal groups are listed in Table 2-10 and Table 2-12.

Table 2-8 through Table 2-14 list the DC specifications for the Celeron D processor in the 775-land

package and are valid only while meeting specifications for case temperature, clock frequency, and

input voltages. Care should be taken to read all notes associated with each parameter.

2.11.1

Processor DC Specifications

The processor DC specifications in this section are defined at the processor core silicon and

not at the package lands unless noted otherwise. See Chapter 4 for the signal definitions and

signal assignments. Most of the signals on the processor FSB are in the GTL+ signal group. The

DC specifications for these signals are listed in Table 2-10.

Table 2-8 through Table 2-15 list the DC specifications for the Celeron D processor in the 775-land

package and are valid only while meeting specifications for case temperature, clock frequency, and

input voltages. Care should be taken to read all notes associated with each parameter.

24

Datasheet

Electrical Specifications

Table 2-8. Voltage and Current Specifications

Symbol

Parameter

Min

Typ

Max

Unit

Notes

1

VID range

VID

1.250

—

1.400

V

Processor Core Frequency

Number

V_CCfor 775_VR_CONFIG_04A

processors

325J/326

330J/331

335J/336

340J/341

345J/346

351

2.53 GHz

2.66 GHz

2.80 GHz

2.93 GHz

3.06 GHz

3.20 GHz

3.33 GHz

V_CC

Refer to Table 2-9 and

Figure 2-2

2, 3, 4, 5, 6

V

355

Processor Core Frequency

Number

I_CCfor processor with multiple

VID

325J/326

330J/331

335J/336

340J/341

345J/346

351

2.53 GHz

2.66 GHz

2.80 GHz

2.93 GHz

3.06 GHz

3.20 GHz

3.33 GHz

78

I_CC

7

—

A

355

Processor Core Frequency

Number

I_CCStop-Grant

325J/326

330J/331

335J/336

340J/341

345J/346

351

2.53 GHz

2.66 GHz

2.80 GHz

2.93 GHz

3.06 GHz

3.20 GHz

3.33 GHz

40

I_SGNT

8, 9, 13

—

A

355

10

I_TCC

V_TT

I_CCTCC active

—

I_CC

A

V

FSB termination voltage (DC+AC

specifications)

11, 12

1.14

1.20

1.26

VTT_OUT

I_CC

DC Current that may be drawn from

VTT_OUT per pin

—

580

mA

—

13, 14

13

I_TT

FSB termination current

I_CCfor PLL lands

—

3.5

120

100

200

A

I_{CC_VCCA}

mA

μA

13

I_{CC_VCCIOPLL}I_CCfor I/O PLL land

13

I_{CC_GTLREF}

I_CCfor GTLREF

NOTES:

1.

Individual processor VID values may be calibrated during manufacturing such that two devices at the same speed may have

different VID settings.

Datasheet

25

Electrical Specifications

2.

3.

These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is re-

quired. See Section 2.4 and Table 2-2 for more information.

The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the socket with a

100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length

of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the oscillo-

scope probe.

4.

5.

6.

775_VR_CONFIG_04A refers to voltage regulator configurations that are defined in the Voltage Regulator Down (VRD) 10.1

Design Guide For Desktop LGA775 Socket.

Refer to Table 2-9 and Figure 2-2 for the minimum, typical, and maximum V

allowed for a given current. The processor

CC

should not be subjected to any V and I combination wherein V exceeds V for a given current.

CC

CC_max

These frequencies will operate properly in a system designed for 775_VR_CONFIG_04B processors. The power and I will

CC

be incrementally higher in this configuration due to the improved loadline and resulting higher V

.

CC

7.

8.

9.

I

is specified at V

.

CC_max

The current specified is also for AutoHALT State.

Icc Stop-Grant and I Sleep are specified at V

.

CC_max

CC

10. The maximum instantaneous current the processor will draw while the thermal control circuit is active as indicated by the as-

sertion of PROCHOT# is the same as the maximum Icc for the processor.

11. VTT must be provided via a separate voltage source and not be connected to V . This specification is measured at the land.

CC

12. Baseboard bandwidth is limited to 20 MHz.

13. These parameters are based on design characterization and are not tested.

14. This is maximum total current drawn from V plane by only the processor. This specification does not include the current com-

TT

ing from R (through the signal line). Refer to the Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775

TT

Socket to determine the total I drawn by the system.

TT

Table 2-9. V Static and Transient Tolerance for 775_VR_CONFIG_04A Processors

CC

Voltage Deviation from VID Setting (V)^{1, 2, 3}

I_CC(A)

Maximum Voltage

Typical Voltage

Minimum Voltage

1.70 mΩ

1.75 mΩ

1.80 mΩ

0

5

0.000

-0.009

-0.017

-0.026

-0.034

-0.043

-0.051

-0.060

-0.068

-0.077

-0.085

-0.094

-0.102

-0.111

-0.119

-0.128

-0.133

-0.025

-0.034

-0.043

-0.051

-0.060

-0.069

-0.078

-0.086

-0.095

-0.104

-0.113

-0.121

-0.130

-0.139

-0.148

-0.156

-0.162

-0.050

-0.059

-0.068

-0.077

-0.086

-0.095

-0.104

-0.113

-0.122

-0.131

-0.140

-0.149

-0.158

-0.167

-0.176

-0.185

-0.190

10

15

20

25

30

35

40

45

50

55

60

65

70

75

78

NOTES:

1.

The loadline specification includes both static and transient limits except for overshoot allowed as shown in

Section 2.12.

2.

3.

This table is intended to aid in reading discrete points on Figure 2-2.

The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage

regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands. Refer

to the Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket for socket loadline

guidelines and VR implementation details.

26

Datasheet

Electrical Specifications

Figure 2-2. V Static and Transient Tolerance for 775_VR_CONFIG_04A

CC

Icc [A]

0

10

20

30

40

50

60

70

VID - 0.000

VID - 0.025

VID - 0.050

VID - 0.075

VID - 0.100

VID - 0.125

VID - 0.150

VID - 0.175

VID - 0.200

Vcc Maximum

Vcc Typical

Vcc Minimum

NOTES:

1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in

Section 2.12.

2. This loadline specification shows the deviation from the VID set point.

3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage

regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands. Refer to

the Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket for socket loadline

guidelines and VR implementation details.

Datasheet

27

Electrical Specifications

Table 2-10. GTL+ Asynchronous Signal Group DC Specifications

Symbol

Parameter

Min

Max

Unit Notes¹

2, 3

V_IL

V_IH

V_OH

I_OL

I_LI

Input Low Voltage

0.0

V_TT/2 – (0.10 * V_TT

)

—

3, 4, 5, 6

Input High Voltage

Output High Voltage

Output Low Current

Input Leakage Current

V_TT/2 + (0.10 * V_TT

)

V_TT

—

5, 6, 7

0.90*V_TT

—

V

8

V_TT/[(0.50*R_{TT_MIN}) + R_{ON_MIN}

± 200

]

A

9

N/A

µA

Output Leakage

Current

10

I_LO

N/A

8

± 200

12

µA

R_ON

Buffer On Resistance

Ω

NOTES:

1.

2.

3.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.

LINT0/INTR and LINT1/NMI use GTLREF as a reference voltage. For these two signals

V

IL

V

= GTLREF + (0.10 * VTT) and V = GTLREF – (0.10 * VTT).

IH

IL

4.

5.

6.

7.

8.

is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.

and V may experience excursions above V

.

TT

OH

The VTT referred to in these specifications refers to instantaneous V

All outputs are open drain.

The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test

load.

.

TT

9.

Leakage to V with land held at V .

SS TT

10. Leakage to V with land held at 300 mV.

TT

Table 2-11. GTL+ Signal Group DC Specifications

Symbol

Parameter

Min

Max

Unit Notes¹

2, 3

V_IL

V_IH

V_OH

I_OL

Input Low Voltage

Input High Voltage

Output High Voltage

Output Low Current

0.0

GTLREF + (0.10 * V_TT

0.90*V_TT

GTLREF – (0.10 * V_TT

)

V

3, 4, 5

)

V_TT

V

3, 5

V

N/A

V_TT/[(0.50*R_{TT_MIN}) + R_{ON_MIN}

± 200

]

A

-

Input Leakage

Current

6

I_LI

N/A

µA

Output Leakage

Current

6

I_LO

N/A

8

± 200

12

µA

R_ON

Buffer On Resistance

Ω

NOTES:

1.

2.

3.

4.

5.

6.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.

The V referred to in these specifications is the instantaneous V

V

IL

.

TT

V

is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.

and V may experience excursions above V

IH

.

IH

OH

TT

Leakage to V with land held at V

.

SS

TT

28

Datasheet

Electrical Specifications

.

Table 2-12. PWRGOOD and TAP Signal Group DC Specifications

Symbol

Parameter

Min

Max

Unit

Notes^{1, 2}

3

V_HYS

Input Hysteresis

200

350

mV

Input low to high

threshold voltage

4

V_T+

0.5 * (V_{TT +}V_{HYS_MIN}

)

0.5 * (V_{TT +}V_{HYS_MAX}

)

V

Input high to low

threshold voltage

V_T

0.5 * (V_TT– V_{HYS_MAX}

)

0.5 * (V_TT– V_{HYS_MIN})

-

4

5

6

V_OH

I_OL

Output High Voltage

Output Low Current

Input Leakage Current

Output Leakage Current

Buffer On Resistance

N/A

—

7

V_TT

45

V

mA

µA

Ω

I_LI

± 200

12

I_LO

R_ON

NOTES:

1.

2.

3.

4.

5.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

All outputs are open drain.

V

represents the amount of hysteresis, nominally centered about 0.5 * V , for all TAP inputs.

HYS

TT

The V referred to in these specifications refers to instantaneous V

.

TT

The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test

load.

6.

Leakage to V with land held at V .

SS TT

Table 2-13. VTTPWRGD DC Specifications

Symbol

Parameter

Input Low Voltage

Input High Voltage

Min

Typ

Max

Unit

Notes

V_IL

V_IH

—

0.3

—

V

0.9

Table 2-14. BSEL [2:0] and VID[5:0] DC Specifications

Symbol

Parameter

Max

Unit

Notes^{1, 2}

R_ON(BSEL) Buffer On Resistance

R_ON(VID) Buffer On Resistance

60

8

Ω

—

I_OL

I_LO

Max Land Current

mA

µA

V

—

3

Output Leakage Current

Voltage Tolerance

200

V_TOL

V_TT(max)

—

NOTES:

1.

2.

3.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

These parameters are not tested and are based on design simulations.

Leakage to V with land held at 2.5 V.

SS

Table 2-15. BOOTSELECT DC Specifications

Symbol

Parameter

Min

Typ

Max

Unit

Notes

1

V_IL

V_IH

Input Low Voltage

Input High Voltage

—

0.24

—

V

0.96

—

NOTES:

1.

These parameters are not tested and are based on design simulations.

Datasheet

29

Electrical Specifications

2.12

V Overshoot Specification

CC

The Celeron D processor in the 775-land package can tolerate short transient overshoot events

where V exceeds the VID voltage when transitioning from a high to low current load condition.

CC

This overshoot cannot exceed VID + V_{OS_MAX}(V_{OS_MAX}is the maximum allowable overshoot

voltage). The time duration of the overshoot event must not exceed T_{OS_MAX}(T_{OS_MAX}is the

maximum allowable time duration above VID). These specifications apply to the processor die

voltage as measured across the VCC_SENSE and VSS_SENSE lands.

Table 2-16. V Overshoot Specifications

CC

Symbol

Parameter

Min

Typ

Max

Unit

Figure

V_{OS_MAX}Magnitude of V_CCovershoot above VID

T_{OS_MAX}Time duration of V_CCovershoot above VID

—

0.050

25

V

2-3

μs

Figure 2-3. V Overshoot Example Waveform

CC

Example Overshoot Waveform

V_OS

VID + 0.050

VID

T_OS

Time

T_OS: Overshoot time above VID

V_OS: Overshoot above VID

NOTES:

1. V_OSis measured overshoot voltage.

2. T_OSis measured time duration above VID.

2.12.1

Die Voltage Validation

Overshoot events from application testing on real processors must meet the specifications in

Table 2-16 when measured across the VCC_SENSE and VSS_SENSE lands. Overshoot events that

are < 10 ns in duration may be ignored. These measurements of processor die level overshoot

should be taken with a 100 MHz bandwidth limited oscilloscope. Refer to the Voltage Regulator

Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket for additional voltage regulator

validation details.

30

Datasheet

Electrical Specifications

2.13

GTL+ FSB Specifications

Termination resistors are not required for most GTL+ signals, as these are integrated into the

processor silicon.

Valid high and low levels are determined by the input buffers which compare a signal’s voltage

with a reference voltage called GTLREF.

Table 2-17 lists the GTLREF specifications. The GTL+ reference voltage (GTLREF) should be

generated on the system board using high precision voltage divider circuits.

Table 2-17. GTL+ Bus Voltage Definitions

Symbol

Parameter

Min

Typ

Max

Units Notes¹

Bus Reference

Voltage

2, 3, 4

GTLREF

(0.98 * 0.67) * V_TT0.67 * V_TT(1.02 * 0.67) * V_TT

V

On die pullup for

BOOTSELECT

signal

5

R_PULLUP

500

54

—

5000

66

Ω

Termination

Resistance

6

R_TT

60

Ω

7

COMP[1:0]

COMP[3:2]

COMP[5:4]

NOTES:

COMP Resistance

59.8

99

60.4

100

61

101

61

Ω

7

Ω

7

59.8

60.4

Ω

1.

2.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

The tolerances for this specification have been stated generically to enable the system designer to calculate the minimum

and maximum values across the range of V

.

TT

3.

4.

5.

6.

7.

GTLREF should be generated from V by a voltage divider of 1% resistors or 1% matched resistors.

TT

The V referred to in these specifications is the instantaneous V

.

TT

These pull-ups are to V

.

TT

R

is the on-die termination resistance measured at V /2 of the GTL+ output driver.

TT

COMP resistance must be provided on the system board with 1% resistors. COMP[1:0] resistors are to V . COMP[3:2]

SS

resistors are to V . COMP[5:4] resistors are to V

.

TT

§

Datasheet

31

Electrical Specifications

32

Datasheet

Package Mechanical Specifications

3 Package Mechanical

Specifications

The Celeron D processor in the 775-land package is packaged in a Flip-Chip Land Grid Array

(FC-LGA4) package that interfaces with the motherboard via an LGA775 socket. The package

consists of a processor core mounted on a substrate land-carrier. An integrated heat spreader (IHS)

is attached to the package substrate and core and serves as the mating surface for processor

component thermal solutions, such as a heatsink. Figure 3-1 shows a sketch of the processor

package components and how they are assembled together. Refer to the LGA775 Socket

Mechanical Design Guide for complete details on the LGA775 socket.

The package components shown in Figure 3-1 include the following:

• Integrated Heat Spreader (IHS)

• Thermal Interface Material (TIM)

• Processor core (die)

• Package substrate

• Capacitors

Figure 3-1. Processor Package Assembly Sketch

Core (die)

TIM

IHS

Substrate

Capacitors

LGA775 Socket

System Board

NOTE:

1. Socket and motherboard are included for reference and are not part of processor package.

3.1

Package Mechanical Drawing

The package mechanical drawings are shown in Figure 3-2 through Figure 3-4. The drawings

include dimensions necessary to design a thermal solution for the processor. These dimensions

include:

• Package reference with tolerances (total height, length, width, etc.)

• IHS parallelism and tilt

• Land dimensions

• Top-side and back-side component keep-out dimensions

• Reference datums

All drawing dimensions are in mm [in].

Datasheet

33

Package Mechanical Specifications

Figure 3-2. Processor Package Drawing 1

34

Datasheet

Package Mechanical Specifications

Figure 3-3. Processor Package Drawing 2

Datasheet

35

Package Mechanical Specifications

Figure 3-4. Processor Package Drawing 3

36

Datasheet

Package Mechanical Specifications

3.2

Processor Component Keep-Out Zones

The processor may contain components on the substrate that define component keep-out zone

requirements. A thermal and mechanical solution design must not intrude into the required keep-

out zones. Decoupling capacitors are typically mounted to either the topside or land-side of the

package substrate. See Figure 3-2 and Figure 3-3 for keep-out zones.

The location and quantity of package capacitors may change due to manufacturing efficiencies but

will remain within the component keep-in.

3.3

Package Loading Specifications

Table 3-1 provides dynamic and static load specifications for the processor package. These

mechanical maximum load limits should not be exceeded during heatsink assembly, shipping

conditions, or standard use condition. Also, any mechanical system or component testing should

not exceed the maximum limits. The processor package substrate should not be used as a

mechanical reference or load-bearing surface for thermal and mechanical solution. The minimum

loading specification must be maintained by any thermal and mechanical solutions.

.

Table 3-1. Processor Loading Specifications

Parameter

Minimum

Maximum

Notes

1, 2, 3

Static

20 lbf

—

45 lbf

1, 3, 4

Dynamic

145 lbf

NOTES:

1.

2.

These specifications apply to uniform compressive loading in a direction normal to the processor IHS.

This is the maximum force that can be applied by a heatsink retention clip. The clip must also provide the minimum spec-

ified load on the processor package.

3.

4.

These specifications are based on limited testing for design characterization. Loading limits are for the package only and

do not include the limits of the processor socket.

Dynamic loading is defined as an 11 ms duration average load superimposed on the static load requirement.

3.4

Package Handling Guidelines

Table 3-2 includes a list of guidelines on package handling in terms of recommended maximum

loading on the processor IHS relative to a fixed substrate. These package handling loads may be

experienced during heatsink removal.

Table 3-2. Package Handling Guidelines

Parameter

Maximum Recommended

Notes

1, 4

Shear

Tensile

70 lbf

25 lbf

2, 4

3, 4

Torque

35 lbf-in

NOTES:

1.

2.

3.

4.

A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface.

A tensile load is defined as a pulling load applied to the IHS in a direction normal to the IHS surface.

A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the IHS top surface.

These guidelines are based on limited testing for design characterization.

Datasheet

37

Package Mechanical Specifications

3.5

Package Insertion Specifications

The Celeron D processor in the 775-land package can be inserted into and removed from a

LGA775 socket 15 times. The socket should meet the LGA775 requirements detailed in the

LGA775 Socket Mechanical Design Guide.

3.6

3.7

Processor Mass Specification

The typical mass of the Celeron D processor in the 775-land package is 21.5 g [0.76 oz]. This mass

[weight] includes all the components that are included in the package.

Processor Materials

Table 3-3 lists some of the package components and associated materials.

Table 3-3. Processor Materials

Component

Material

Integrated Heat Spreader (IHS)

Substrate

Nickel Plated Copper

Fiber Reinforced Resin

Gold Plated Copper

Substrate Lands

3.8

Processor Markings

Figure 3-6 and Figure 3-6 show the topside markings on the processor. This diagrams are to aid in

the identification of the Celeron D processor in the 775-land package.

Figure 3-5. Processor Top-Side Marking Example (with Processor Number)

m

I

‘04

©

Celeron® D

Processor

Number

346 SL7NX XXXXX

3.06GHz/256/533

FFFFFFFF-NNNN

2D Matrix

38

Datasheet

Package Mechanical Specifications

Figure 3-6. Processor Top-Side Marking Example

GROUP1 LINE1

GROUP1 LINE2

GROUP1 LINE3

GROUP1 LINE4

GROUP1 LINE5

Grp1line1: INTEL m © ‘03

Grp1line2: CELERON® D

Grp1line3: 2.53GHZ/256/533

Grp1line4: SLxxx PHILLIPINES

Grp1line5: 7407A234

ATPO #

SERIAL #

ATPO #

SER #

2D Matrix

Datasheet

39

Package Mechanical Specifications

3.9

Processor Land Coordinates

Figure 3-7 shows the top view of the processor land coordinates. The coordinates are referred to

throughout the document to identify processor lands.

.

Figure 3-7. Processor Land Coordinates (Top View)

V

/ V

S S

C C

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

AN

AM

AL

AK

A J

AH

AG

AF

AE

AD

AC

AB

AA

Y

AN

AM

AL

AK

A J

AH

AG

AF

AE

AD

AC

AB

AA

Y

W

V

W

V

Address /

C om m on C lock

/ Async

775-Land P ackage Quadrants

(Top V iew )

U

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

V

/ C locks

D ata

TT

§

40

Datasheet

Land Listing and Signal Descriptions

4 Land Listing and Signal

Descriptions

This chapter contains the processor land assignments and signal descriptions.

4.1

Processor Land Assignments

This section contains the land listings for the Celeron D processor in the 775-land package. The

landout footprint is shown in Figure 4-1 and Figure 4-2. These figures show the physical location

of each signal on the package landout footprint (top view). Table 4-1 is a listing of all processor

lands ordered alphabetically by land (signal) name. Table 4-2 is also a listing of all processor lands;

the ordering is by land number.

Datasheet

41

Land Listing and Signal Descriptions

Figure 4-1. Landout Diagram (Top View – Left Side)

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

AN

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

AM

AL

AK

AJ

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

AH

AG

AF

AE

AD

AC

AB

AA

Y

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

W

V

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

U

T

R

VSS

P

N

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

M

VCC

L

K

J

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

DP3#

VSS

DP0#

DP2#

VCC

H

GTLREF

_SEL

BSEL1

DP1#

G

F

BSEL2 BSEL0 BCLK1 TESTHI4 TESTHI5 TESTHI3 TESTHI6 RESET# D47#

D44# DSTBN2# DSTBP2# D35#

D36#

D37#

VSS

D32#

VSS

D31#

D30#

D33#

VSS

RSVD

VSS

BCLK0 VTT_SEL TESTHI0 TESTHI2 TESTHI7 RSVD

VSS

D45#

D46#

D43#

D42#

VSS

D41#

VSS

D40#

DBI2#

D38#

D39#

VSS

E

D

VSS

VTT

VSS

VTT

VSS

VTT

VSS

VTT

RSVD

VSS

RSVD

D34#

RSVD

VTT

D48#

D49#

VCCIO

PLL

C

VTT

VSS

D58#

DBI3#

VSS

D54# DSTBP3#

VSS

D51#

D53#

B

A

VTT

30

VTT

29

VTT

28

VTT

27

VTT

26

VTT

25

VSS

24

VSSA

VCCA

23

D63#

D62#

22

D59#

VSS

21

VSS

RSVD

20

D60#

D61#

19

D57#

VSS

18

VSS

D56#

17

D55#

DSTBN3# VSS

16 15

42

Datasheet

Land Listing and Signal Descriptions

Figure 4-2. Landout Diagram (Top View – Right Side)

14

13

12

11

10

9

8

7

6

5

4

3

2

1

VID_

VSS_MB_

VCC_MB_

VSS_

VCC_

SENSE

VCC

VSS

VCC

VSS

VCC

VSS

VID0

VSS

AN

SELECT REGULATION REGULATION SENSE

VCC

VSS

VCC

VSS

VCC

VID7

VSS

VTTPWRGD

VID3

VID6

VID1

VSS

VID5

VID4

VSS

VID2

VSS

AM

AL

AK

AJ

PROCHOT# THERMDA

VCC

RSVD

A35#

VSS

ITP_CLK0

ITP_CLK1

VSS

THERMDC

BPM1#

VSS

VCC

A34#

A33#

A31#

A27#

VSS

BPM0#

RSVD

BPM3#

BPM4#

VSS

VCC

VSS

A32#

A30#

A28#

RSVD

VSS

AH

AG

AF

AE

AD

AC

AB

VCC

A29#

BPM5#

VSS

TRST#

TDO

VCC

VSS

SKTOCC#

VCC

RSVD

A22#

RSVD

TCK

ADSTB1#

A25#

A24#

BINIT#

VSS

BPM2#

DBR#

IERR#

TDI

VCC

VSS

RSVD

A26#

TMS

VCC

A17#

MCERR#

VSS

VTT_OUT_

RIGHT

VCC

VSS

A23#

VSS

A21#

A20#

VSS

LL_ID1

VSS

AA

Y

BOOT

SELECT

A19#

RSVD

VCC

VSS

A18#

VSS

A10#

VSS

A16#

A14#

A12#

A9#

VSS

A15#

A13#

A11#

TESTHI1 TESTHI12

MS_ID0

MS_ID1

VSS

W

V

VSS

AP1#

VSS

LL_ID0

AP0#

U

T

COMP5

COMP1

FERR#/

PBE#

VCC

VSS

ADSTB0#

VSS

A8#

VSS

COMP3

R

VCC

VSS

A4#

RSVD

VSS

INIT#

VSS

SMI#

TESTHI11

P

N

VSS

RSVD

IGNNE# PWRGOOD

THER-

VSS

VCC

VSS

REQ2#

A5#

A7#

STPCLK#

M

MTRIP#

VCC

VSS

A3#

A6#

VSS

TESTHI13

VSS

LINT1

LINT0

L

REQ3#

VSS

REQ0#

A20M#

K

VTT_OUT_

LEFT

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

REQ4#

VSS

REQ1#

VSS

RSVD

VSS

COMP4

J

H

TESTHI10

RSP#

GTLREF1

GTLREF0

VSS

D29#

D28#

VSS

D27#

VSS

DSTBN1# DBI1# RSVD

D16#

D18#

D19#

VSS

BPRI#

D17#

VSS

DEFER#

VSS

RSVD

VSS

PC_REQ#

RS1#

TESTHI9 TESTHI8

COMP2

EDRDY#

VSS

G

F

D24#

DSTBP1#

VSS

D23#

VSS

D21#

D22#

VSS

HITM#

HIT#

BR0#

TRDY#

VSS

D26#

D25#

RSVD

D20#

RSVD

VSS

E

D

C

RSVD

D15#

D12#

ADS#

RSVD

DRDY#

VSS

D52#

VSS

D14#

D11#

VSS

RSVD

DSTBN0#

VSS

D3#

D1#

VSS

LOCK#

BNR#

VSS

D50#

14

RSVD

COMP0

13

D13#

VSS

12

VSS

D9#

11

D10# DSTBP0#

VSS

DBI0#

8

D6#

D7#

7

D5#

VSS

6

VSS

D4#

5

D0#

D2#

4

RS0#

RS2#

3

DBSY#

VSS

2

B

A

D8#

VSS

10

9

1

Datasheet

43

Land Listing and Signal Descriptions

Table 4-1. Alphabetical Land

Assignments

Table 4-1. Alphabetical Land

Assignments

Land

#

Signal Buffer

Type

Land

#

Signal Buffer

Type

Land Name

Direction

Land Name

Direction

A3#

A4#

L5

P6

Source Synch Input/Output

BPM0#

BPM1#

BPM2#

BPM3#

BPM4#

BPM5#

BPRI#

BR0#

BSEL0

BSEL1

BSEL2

COMP0

COMP1

COMP2

COMP3

COMP4

COMP5

D0#

AJ2

AJ1

AD2

AG2

AF2

AG3

G8

Common Clock Input/Output

A5#

M5

A6#

L4

A7#

M4

A8#

R4

A9#

T5

Common Clock

Input

A10#

U6

F3

Common Clock Input/Output

A11#

T4

G29

H30

G30

A13

T1

Power/Other

Output

Input

A12#

U5

A13#

U4

A14#

V5

A15#

V4

Input

A16#

W5

AB6

W6

Y6

G2

Input

A17#

R1

Input

A18#

J2

Input

A19#

T2

Input

A20#

Y4

B4

Source Synch Input/Output

A20M#

A21#

K3

Asynch GTL+

Input

D1#

C5

AA4

AD6

AA5

AB5

AC5

AB4

AF5

AF4

AG6

AG4

AG5

AH4

AH5

AJ5

AJ6

D2

Source Synch Input/Output

Common Clock Input/Output

Source Synch Input/Output

Common Clock Input/Output

D2#

A4

A22#

D3#

C6

A23#

D4#

A5

A24#

D5#

B6

A25#

D6#

B7

A26#

D7#

A7

A27#

D8#

A10

A11

B10

C11

D8

A28#

D9#

A29#

D10#

D11#

A30#

A31#

D12#

D13#

D14#

D15#

D16#

D17#

D18#

D19#

D20#

D21#

D22#

D23#

D24#

D25#

D26#

A32#

B12

C12

D11

G9

A33#

A34#

A35#

ADS#

ADSTB0#

ADSTB1#

AP0#

AP1#

BCLK0

BCLK1

BINIT#

BNR#

BOOTSELECT

F8

R6

F9

AD5

U2

E9

D7

U3

E10

D10

F11

F12

D13

E13

F28

G28

AD3

C2

Clock

Input

Common Clock Input/Output

Y1

Power/Other

Input

44

Datasheet

Land Listing and Signal Descriptions

Table 4-1. Alphabetical Land

Assignments

Table 4-1. Alphabetical Land

Assignments

Land

#

Signal Buffer

Type

Land

#

Signal Buffer

Type

Land Name

Direction

Land Name

Direction

D27#

D28#

D29#

D30#

D31#

D32#

D33#

D34#

D35#

D36#

D37#

D38#

D39#

D40#

D41#

D42#

D43#

D44#

D45#

D46#

D47#

D48#

D49#

D50#

D51#

D52#

D53#

D54#

D55#

D56#

D57#

D58#

D59#

D60#

D61#

D62#

D63#

DBI0#

DBI1#

DBI2#

DBI3#

DBR#

DBSY#

DEFER#

G13

F14

G14

F15

G15

G16

E15

E16

G18

G17

F17

F18

E18

E19

F20

E21

F21

G21

E22

D22

G22

D20

D17

A14

C15

C14

B15

C18

B16

A17

B18

C21

B21

B19

A19

A22

B22

A8

Source Synch Input/Output

DP0#

J16

H15

H16

J17

C1

Common Clock Input/Output

Source Synch Input/Output

DP1#

DP2#

DP3#

DRDY#

DSTBN0#

DSTBN1#

DSTBN2#

DSTBN3#

DSTBP0#

DSTBP1#

DSTBP2#

DSTBP3#

C8

G12

G20

A16

B9

E12

G19

C17

F2

1

EDRDY#

Common Clock

Asynch GTL+

Power/Other

—

Input

Output

—

FERR#/PBE#

GTLREF_SEL

GTLREF0

GTLREF1

HIT#

R3

H29

H1

Input

—

H2

D4

Common Clock Input/Output

HITM#

E4

IERR#

AB2

N2

Asynch GTL+

TAP

Output

Input

IGNNE#

INIT#

P3

Input

ITP_CLK0

ITP_CLK1

LINT0

AK3

AJ3

K1

Input

TAP

Input

Asynch GTL+

Power/Other

Input

LINT1

L1

Input

LL_ID0

V2

Output

LL_ID1

AA2

C3

LOCK#

Common Clock Input/Output

MCERR#

MS_ID0

MS_ID1

AB3

W1

V1

Power/Other

Common Clock

Asynch GTL+

Power/Other

Output

1

PC_REQ#

G5

Output

PROCHOT#

PWRGOOD

REQ0#

AL2

N1

Input/Output

Input

K4

Source Synch Input/Output

REQ1#

J5

G11

D19

C20

AC2

B2

REQ2#

M6

K6

REQ3#

REQ4#

J6

Power/Other

Common Clock Input/Output

Common Clock Input

Output

RESERVED

A20

AC4

AE3

—

G7

Datasheet

45

Land Listing and Signal Descriptions

Table 4-1. Alphabetical Land

Assignments

Table 4-1. Alphabetical Land

Assignments

Land

#

Signal Buffer

Type

Land

#

Signal Buffer

Type

Land Name

Direction

Land Name

Direction

RESERVED

RESET#

AE4

AE6

AH2

C9

—

TESTHI8

TESTHI9

TESTHI10

TESTHI11

TESTHI12

TESTHI13

THERMDA

THERMDC

THERMTRIP#

TMS

G3

Power/Other

Asynch GTL+

TAP

Input

—

G4

—

H5

—

P1

D1

—

W2

D14

D16

E23

E24

E5

—

L2

—

AL1

—

AK1

—

M2

Output

Input

—

AC1

E6

—

TRDY#

TRST#

VCC

E3

Common Clock

TAP

E7

—

AG1

AA8

F23

F29

F6

—

Power/Other

—

VCC

AB8

—

VCC

AC23

AC24

AC25

AC26

AC27

AC28

AC29

AC30

AC8

—

G10

B13

J3

—

VCC

—

VCC

—

VCC

—

N4

—

VCC

—

N5

—

VCC

—

P5

—

VCC

—

Y3

—

VCC

—

D23

AK6

G6

—

VCC

—

VCC

AD23

AD24

AD25

AD26

AD27

AD28

AD29

AD30

AD8

—

VCC

—

G23

B3

Common Clock

Power/Other

Asynch GTL+

TAP

Input

Output

Input

Output

Input

VCC

—

RS0#

VCC

—

RS1#

F5

VCC

—

RS2#

A3

VCC

—

RSP#

H4

VCC

—

SKTOCC#

SMI#

AE8

P2

VCC

—

VCC

—

STPCLK#

TCK

M3

VCC

AE11

AE12

AE14

AE15

AE18

AE19

AE21

AE22

AE23

AE9

—

AE1

AD1

AF1

F26

W3

F25

G25

G27

G26

G24

F24

VCC

—

TDI

TAP

VCC

—

TDO

TAP

VCC

—

TESTHI0

Power/Other

VCC

—

TESTHI1

VCC

—

TESTHI2

VCC

—

TESTHI3

VCC

—

TESTHI4

VCC

—

TESTHI5

VCC

—

TESTHI6

VCC

AF11

AF12

—

TESTHI7

VCC

—

46

Datasheet

Land Listing and Signal Descriptions

Table 4-1. Alphabetical Land

Assignments

Table 4-1. Alphabetical Land

Assignments

Land

#

Signal Buffer

Type

Land

#

Signal Buffer

Type

Land Name

Direction

Land Name

Direction

VCC

AF14

AF15

AF18

AF19

AF21

AF22

AF8

Power/Other

—

VCC

AJ18

AJ19

AJ21

AJ22

AJ25

AJ26

AJ8

Power/Other

—

AF9

AJ9

AG11

AG12

AG14

AG15

AG18

AG19

AG21

AG22

AG25

AG26

AG27

AG28

AG29

AG30

AG8

AK11

AK12

AK14

AK15

AK18

AK19

AK21

AK22

AK25

AK26

AK8

AK9

AL11

AL12

AL14

AL15

AL18

AL19

AL21

AL22

AL25

AL26

AL29

AL30

AL8

AG9

AH11

AH12

AH14

AH15

AH18

AH19

AH21

AH22

AH25

AH26

AH27

AH28

AH29

AH30

AH8

AL9

AM11

AM12

AM14

AM15

AM18

AM19

AM21

AM22

AM25

AM26

AH9

AJ11

AJ12

AJ14

AJ15

Datasheet

47

Land Listing and Signal Descriptions

Table 4-1. Alphabetical Land

Assignments

Table 4-1. Alphabetical Land

Assignments

Land

#

Signal Buffer

Type

Land

#

Signal Buffer

Type

Land Name

Direction

Land Name

Direction

VCC

AM29

AM30

AM8

AM9

AN11

AN12

AN14

AN15

AN18

AN19

AN21

AN22

AN25

AN26

AN29

AN30

AN8

AN9

J10

Power/Other

—

VCC

K28

K29

K30

K8

Power/Other

—

L8

M23

M24

M25

M26

M27

M28

M29

M30

M8

N23

N24

N25

N26

N27

N28

N29

N30

N8

J11

J12

J13

J14

J15

P8

J18

R8

J19

T23

T24

T25

T26

T27

T28

T29

T30

T8

J20

J21

J22

J23

J24

J25

J26

J27

J28

U23

U24

U25

U26

U27

U28

U29

U30

U8

J29

J30

J8

J9

K23

K24

K25

K26

K27

V8

48

Datasheet

Land Listing and Signal Descriptions

Table 4-1. Alphabetical Land

Assignments

Table 4-1. Alphabetical Land

Assignments

Land

#

Signal Buffer

Type

Land

#

Signal Buffer

Type

Land Name

Direction

Land Name

Direction

VCC

W23

W24

W25

W26

W27

W28

W29

W30

W8

Power/Other

—

VSS

AA27

AA28

AA29

AA3

Power/Other

—

AA30

AA6

AA7

AB1

AB23

AB24

AB25

AB26

AB27

AB28

AB29

AB30

AB7

Y23

Y24

Y25

Y26

Y27

Y28

Y29

Y30

Y8

AC3

VCC_MB_

REGULATION

AC6

AN5

Power/Other

Output

AC7

VCCA

VCCIOPLL

VCC_SENSE

VID_SELECT

VID0

A23

C23

AN3

AN7

AM2

AL5

AM3

AL6

AK4

AL4

AM5

AM7

A12

A15

A18

A2

Power/Other

—

AD4

AD7

Output

—

AE10

AE13

AE16

AE17

AE2

VID1

VID2

VID3

AE20

AE24

AE25

AE26

AE27

AE28

AE29

AE30

AE5

VID4

VID5

VID6

VID7

VSS

—

VSS

—

VSS

—

VSS

A21

A24

A6

—

AE7

VSS

—

AF10

AF13

AF16

AF17

AF20

AF23

AF24

VSS

—

VSS

A9

—

VSS

AA23

AA24

AA25

AA26

—

VSS

—

VSS

—

VSS

—

Datasheet

49

Land Listing and Signal Descriptions

Table 4-1. Alphabetical Land

Assignments

Table 4-1. Alphabetical Land

Assignments

Land

#

Signal Buffer

Type

Land

#

Signal Buffer

Type

Land Name

Direction

Land Name

Direction

VSS

AF25

AF26

AF27

AF28

AF29

AF3

Power/Other

—

VSS

AK17

AK2

Power/Other

—

AK20

AK23

AK24

AK27

AK28

AK29

AK30

AK5

AF30

AF6

AF7

AG10

AG13

AG16

AG17

AG20

AG23

AG24

AG7

AK7

AL10

AL13

AL16

AL17

AL20

AL23

AL24

AL27

AL28

AL3

AH1

AH10

AH13

AH16

AH17

AH20

AH23

AH24

AH3

AL7

AM1

AM10

AM13

AM16

AM17

AM20

AM23

AM24

AM27

AM28

AM4

AH6

AH7

AJ10

AJ13

AJ16

AJ17

AJ20

AJ23

AJ24

AJ27

AJ28

AJ29

AJ30

AJ4

AN1

AN10

AN13

AN16

AN17

AN2

AN20

AN23

AN24

AN27

AN28

AJ7

AK10

AK13

AK16

50

Datasheet

Land Listing and Signal Descriptions

Table 4-1. Alphabetical Land

Assignments

Table 4-1. Alphabetical Land

Assignments

Land

#

Signal Buffer

Type

Land

#

Signal Buffer

Type

Land Name

Direction

Land Name

Direction

VSS

B1

B11

B14

B17

B20

B24

B5

Power/Other

—

VSS

H10

H11

H12

H13

H14

H17

H18

H19

H20

H21

H22

H23

H24

H25

H26

H27

H28

H3

Power/Other

—

B8

C10

C13

C16

C19

C22

C24

C4

C7

D12

D15

D18

D21

D24

D3

H6

H7

H8

H9

D5

J4

D6

J7

D9

K2

E11

E14

E17

E2

K5

K7

L23

L24

L25

L26

L27

L28

L29

L3

E20

E25

E26

E27

E28

E29

E8

L30

L6

F10

F13

F16

F19

F22

F4

L7

M1

M7

N3

N6

F7

N7

G1

P23

Datasheet

51

Land Listing and Signal Descriptions

Table 4-1. Alphabetical Land

Assignments

Table 4-1. Alphabetical Land

Assignments

Land

#

Signal Buffer

Type

Land

#

Signal Buffer

Type

Land Name

Direction

Land Name

Direction

VSS

P24

P25

P26

P27

P28

P29

P30

P4

Power/Other

—

VSS_SENSE

VTT

AN4

A25

A26

A27

A28

A29

A30

B25

B26

B27

B28

B29

B30

C25

C26

C27

C28

C29

C30

D25

D26

D27

D28

D29

D30

J1

Power/Other

Output

—

VTT

—

VTT

—

VTT

—

VTT

—

VTT

—

VTT

—

P7

VTT

—

R2

VTT

—

R23

R24

R25

R26

R27

R28

R29

R30

R5

VTT

—

VTT

—

VTT

—

VTT

—

VTT

—

VTT

—

VTT

—

VTT

—

VTT

—

R7

VTT

—

T3

VTT

—

T6

VTT

—

T7

VTT

—

U1

VTT

—

U7

VTT

—

V23

V24

V25

V26

V27

V28

V29

V3

VTT_OUT_LEFT

Output

VTT_OUT_

RIGHT

AA1

Power/Other

Output

VTT_SEL

VTTPWRGD

NOTES:

F27

Power/Other

Output

Input

AM6

1. EDRDY# and PC_REQ# are not features of the

Celeron D processor in the 775-land package.

They are included here for future processor com-

patibility.

V30

V6

V7

W4

W7

Y2

Y5

Y7

VSS_MB_

AN6

B23

Power/Other

Output

—

REGULATION

VSSA

52

Datasheet

Land Listing and Signal Descriptions

Table 4-2. Numerical Land Assignments

Land

#

Signal Buffer

Type

Land

#

Signal Buffer

Type

Land Name

Direction

Land Name

Direction

A2

A3

VSS

RS2#

D2#

Power/Other

Common Clock

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

—

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

C1

D55#

VSS

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Input/Output

Input

—

A4

Input/Output

D57#

D60#

VSS

Input/Output

A5

D4#

Input/Output

A6

VSS

—

A7

D7#

Input/Output

D59#

D63#

VSSA

VSS

Input/Output

A8

DBI0#

VSS

Input/Output

A9

—

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

B1

D8#

Input/Output

D9#

Input/Output

VTT

VSS

—

VTT

COMP0

D50#

VSS

Input

VTT

Input/Output

VTT

—

VTT

DSTBN3#

D56#

VSS

Input/Output

VTT

Input/Output

DRDY#

BNR#

LOCK#

VSS

Common Clock Input/Output

—

C2

D61#

RESERVED

VSS

Input/Output

C3

—

C4

Power/Other

Source Synch

Power/Other

Source Synch

—

Power/Other

Source Synch

Power/Other

—

C5

D1#

Input/Output

D62#

VCCA

VSS

Input/Output

C6

D3#

Input/Output

—

C7

VSS

—

C8

DSTBN0#

RESERVED

VSS

Input/Output

VTT

C9

—

VTT

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

C25

C26

C27

C28

C29

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

—

VTT

D11#

D14#

VSS

Input/Output

VTT

Input/Output

VTT

—

VTT

D52#

D51#

VSS

Input/Output

VSS

Input/Output

B2

DBSY#

RS0#

D0#

Common Clock Input/Output

—

B3

Common Clock

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

—

Input

Input/Output

—

DSTBP3#

D54#

VSS

Input/Output

B4

Input/Output

B5

VSS

—

B6

D5#

Input/Output

—

DBI3#

D58#

VSS

Input/Output

B7

D6#

Input/Output

B8

VSS

—

B9

DSTBP0#

D10#

VSS

Input/Output

—

VCCIOPLL

VSS

B10

B11

B12

B13

B14

B15

VTT

D13#

RESERVED

VSS

Input/Output

—

VTT

Power/Other

Source Synch

—

VTT

D53#

Input/Output

VTT

Datasheet

53

Land Listing and Signal Descriptions

Table 4-2. Numerical Land Assignments

Land

#

Signal Buffer

Type

Land

#

Signal Buffer

Type

Land Name

Direction

Land Name

Direction

C30

D1

VTT

RESERVED

ADS#

VSS

Power/Other

—

E15

E16

E17

E18

E19

E20

E21

E22

E23

E24

E25

E26

E27

E28

E29

F2

D33#

D34#

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

—

Input/Output

D2

Common Clock Input/Output

Power/Other

Common Clock Input/Output

VSS

—

D3

—

D39#

Input/Output

D4

HIT#

D40#

Input/Output

D5

VSS

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

—

VSS

—

D6

VSS

—

D42#

Input/Output

D7

D20#

Input/Output

D45#

Input/Output

D8

D12#

Input/Output

RESERVED

VSS

—

D9

VSS

—

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

E2

D22#

Input/Output

Power/Other

Common Clock

—

D15#

Input/Output

VSS

—

VSS

—

VSS

—

D25#

Input/Output

VSS

—

RESERVED

VSS

—

VSS

—

1

Power/Other

—

EDRDY#

Input

RESERVED

D49#

—

F3

BR0#

VSS

Common Clock Input/Output

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

—

Input/Output

F4

Power/Other

Common Clock

—

Input

VSS

—

F5

RS1#

DBI2#

D48#

Input/Output

F6

RESERVED

VSS

—

Input/Output

F7

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

—

VSS

—

F8

D17#

Input/Output

—

D46#

Input/Output

F9

D18#

RESERVED

VSS

—

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

F20

F21

F22

F23

F24

F25

F26

F27

F28

F29

G1

VSS

Power/Other

Common Clock

D23#

Input/Output

—

VTT

—

D24#

VTT

—

VSS

VTT

—

D28#

Input/Output

—

VTT

—

D30#

VTT

—

VSS

VTT

—

D37#

Input/Output

—

VSS

—

D38#

E3

TRDY#

HITM#

RESERVED

VSS

Input

VSS

E4

Common Clock Input/Output

D41#

Input/Output

—

E5

—

D43#

E6

—

VSS

E7

—

RESERVED

TESTHI7

TESTHI2

TESTHI0

VTT_SEL

BCLK0

RESERVED

VSS

—

E8

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Clock

Input

E9

D19#

Input/Output

—

Input

E10

E11

E12

E13

E14

D21#

Input

VSS

Output

Input

DSTBP1#

D26#

Input/Output

—

VSS

Power/Other

—

54

Datasheet

Land Listing and Signal Descriptions

Table 4-2. Numerical Land Assignments

Land

#

Signal Buffer

Type

Land

#

Signal Buffer

Type

Land Name

Direction

Land Name

Direction

G2

G3

COMP2

TESTHI8

TESTHI9

Power/Other

Common Clock

—

Input

H16

H17

H18

H19

H20

H21

H22

H23

H24

H25

H26

H27

H28

H29

H30

J1

DP2#

VSS

Common Clock Input/Output

Power/Other

—

G4

Input

VSS

—

1

G5

PC_REQ#

Output

—

VSS

—

G6

RESERVED

DEFER#

BPRI#

D16#

VSS

—

G7

Common Clock

Source Synch

—

Input

VSS

—

G8

Input

VSS

—

G9

Input/Output

—

VSS

—

G10

G11

G12

G13

G14

G15

G16

G17

G18

G19

G20

G21

G22

G23

G24

G25

G26

G27

G28

G29

G30

H1

RESERVED

DBI1#

VSS

—

Source Synch

Common Clock

Power/Other

Clock

Input/Output

Input

VSS

—

DSTBN1#

D27#

VSS

—

VSS

—

D29#

VSS

—

D31#

GTLREF_SEL

BSEL1

VTT_OUT_LEFT

COMP4

RESERVED

VSS

—

D32#

Output

D36#

Output

D35#

J2

Input

DSTBP2#

DSTBN2#

D44#

J3

—

J4

Power/Other

Source Synch

Power/Other

—

J5

REQ1#

REQ4#

VSS

Input/Output

D47#

J6

Input/Output

RESET#

TESTHI6

TESTHI3

TESTHI5

TESTHI4

BCLK1

BSEL0

BSEL2

GTLREF0

GTLREF1

VSS

J7

—

Input

J8

VCC

Input

J9

VCC

Input

J10

J11

J12

J13

J14

J15

J16

J17

J18

J19

J20

J21

J22

J23

J24

J25

J26

J27

J28

J29

VCC

Input

VCC

Input

VCC

Power/Other

—

Output

Input

VCC

H2

—

DP0#

DP3#

VCC

Common Clock Input/Output

H3

Power/Other

Common Clock

Power/Other

—

H4

RSP#

Input

Power/Other

—

H5

TESTHI10

VSS

Input

VCC

H6

—

VCC

H7

VSS

—

VCC

H8

VSS

—

VCC

H9

VSS

—

VCC

H10

H11

H12

H13

H14

H15

VSS

—

VCC

VSS

—

VCC

VSS

—

VCC

VSS

—

VCC

VSS

—

VCC

DP1#

Common Clock Input/Output

VCC

Datasheet

55

Land Listing and Signal Descriptions

Table 4-2. Numerical Land Assignments

Land

#

Signal Buffer

Type

Land

#

Signal Buffer

Type

Land Name

Direction

Land Name

Direction

J30

K1

VCC

LINT0

VSS

Power/Other

Asynch GTL+

Power/Other

Asynch GTL+

Source Synch

Power/Other

Source Synch

Power/Other

Asynch GTL+

Power/Other

Source Synch

Power/Other

Asynch GTL+

Source Synch

Power/Other

—

M26

M27

M28

M29

M30

N1

VCC

Power/Other

Asynch GTL+

Power/Other

—

Input

—

K2

—

VCC

—

K3

A20M#

REQ0#

VSS

Input

VCC

—

K4

Input/Output

VCC

—

K5

—

PWRGOOD

IGNNE#

VSS

Input

K6

REQ3#

VSS

Input/Output

N2

Input

K7

—

N3

—

K8

VCC

—

N4

RESERVED

VSS

—

K23

K24

K25

K26

K27

K28

K29

K30

L1

VCC

—

N5

—

VCC

—

N6

Power/Other

Asynch GTL+

Power/Other

—

VCC

—

N7

VSS

—

VCC

—

N8

VCC

—

VCC

—

N23

N24

N25

N26

N27

N28

N29

N30

P1

VCC

—

VCC

—

VCC

—

VCC

—

VCC

—

VCC

—

VCC

—

LINT1

TESTHI13

VSS

Input

VCC

—

L2

Input

VCC

—

L3

—

VCC

—

L4

A6#

Input/Output

VCC

—

L5

A3#

Input/Output

TESTHI11

SMI#

Input

L6

VSS

—

P2

Input

L7

VSS

—

P3

INIT#

VSS

Input

L8

VCC

—

P4

—

L23

L24

L25

L26

L27

L28

L29

L30

M1

M2

M3

M4

M5

M6

M7

M8

M23

M24

M25

VSS

—

P5

RESERVED

A4#

—

VSS

—

P6

Source Synch

Power/Other

Asynch GTL+

Source Synch

Power/Other

Source Synch

Power/Other

Input/Output

VSS

—

P7

VSS

—

VSS

—

P8

VCC

—

VSS

—

P23

P24

P25

P26

P27

P28

P29

P30

R1

VSS

—

VSS

—

VSS

—

VSS

—

VSS

—

VSS

—

VSS

—

VSS

—

VSS

—

THERMTRIP#

STPCLK#

A7#

Output

VSS

—

Input

VSS

—

Input/Output

VSS

—

Input

A5#

Input/Output

COMP3

VSS

REQ2#

VSS

Input/Output

R2

—

R3

FERR#/PBE#

A8#

Output

Input/Output

—

VCC

R4

VCC

R5

VSS

VCC

R6

ADSTB0#

VSS

Input/Output

—

VCC

R7

56

Datasheet

Land Listing and Signal Descriptions

Table 4-2. Numerical Land Assignments

Land

#

Signal Buffer

Type

Land

#

Signal Buffer

Type

Land Name

Direction

Land Name

Direction

R8

R23

R24

R25

R26

R27

R28

R29

R30

T1

VCC

VSS

Power/Other

Source Synch

Power/Other

—

V4

V5

A15#

A14#

VSS

Source Synch

Power/Other

Source Synch

Power/Other

—

Input/Output

—

Input/Output

VSS

—

V6

—

VSS

—

V7

VSS

—

VSS

—

V8

VCC

—

VSS

—

V23

V24

V25

V26

V27

V28

V29

V30

W1

W2

W3

W4

W5

W6

W7

W8

W23

W24

W25

W26

W27

W28

W29

W30

Y1

VSS

—

VSS

—

VSS

—

VSS

—

VSS

—

VSS

—

VSS

—

COMP1

COMP5

VSS

Input

VSS

—

T2

Input

VSS

—

T3

—

VSS

—

T4

A11#

A9#

Input/Output

VSS

—

T5

Input/Output

MS_ID0

TESTHI12

TESTHI1

VSS

Output

T6

VSS

—

Input

T7

VSS

Input

T8

VCC

VSS

—

T23

T24

T25

T26

T27

T28

T29

T30

U1

A16#

A18#

VSS

Input/Output

—

VCC

—

VCC

—

VCC

—

VCC

—

VCC

—

VCC

—

U2

AP0#

AP1#

A13#

A12#

A10#

VSS

Common Clock Input/Output

VCC

—

U3

VCC

—

U4

Source Synch

Power/Other

Input/Output

VCC

—

U5

Input/Output

BOOTSELECT

VSS

Input

U6

Input/Output

Y2

—

U7

—

Y3

RESERVED

A20#

VSS

—

U8

VCC

MS_ID1

LL_ID0

VSS

Y4

Source Synch

Power/Other

Source Synch

Power/Other

Input/Output

U23

U24

U25

U26

U27

U28

U29

U30

V1

—

Y5

—

Y6

A19#

VSS

Input/Output

—

Y7

—

Y8

VCC

—

Y23

Y24

Y25

Y26

Y27

Y28

Y29

VCC

—

VCC

—

VCC

—

VCC

Output

—

VCC

V2

VCC

V3

VCC

Datasheet

57

Land Listing and Signal Descriptions

Table 4-2. Numerical Land Assignments

Land

#

Signal Buffer

Type

Land

#

Signal Buffer

Type

Land Name

Direction

Land Name

Direction

Y30

AA1

VCC

Power/Other

—

AC26

AC27

AC28

AC29

AC30

AD1

VCC

Power/Other

TAP

—

VTT_OUT_

RIGHT

Output

VCC

—

AA2

AA3

LL_ID1

VSS

Power/Other

Source Synch

Power/Other

Asynch GTL+

Output

VCC

—

VCC

—

AA4

A21#

A23#

VSS

Input/Output

TDI

Input

AA5

Input/Output

AD2

BPM2#

BINIT#

VSS

Common Clock Input/Output

AA6

—

AD3

AA7

VSS

AD4

Power/Other

Source Synch

Power/Other

TAP

—

AA8

VCC

VSS

—

AD5

ADSTB1#

A22#

VSS

Input/Output

AA23

AA24

AA25

AA26

AA27

AA28

AA29

AA30

AB1

—

AD6

Input/Output

VSS

—

AD7

—

VSS

—

AD8

VCC

VSS

—

AD23

AD24

AD25

AD26

AD27

AD28

AD29

AD30

AE1

VCC

—

VSS

—

VCC

—

VSS

—

VCC

—

VSS

—

VCC

—

VSS

—

VCC

—

VSS

—

VCC

—

AB2

IERR#

MCERR#

A26#

A24#

A17#

VSS

Output

VCC

—

AB3

Common Clock Input/Output

VCC

—

AB4

Source Synch

Power/Other

TAP

Input/Output

TCK

Input

—

AB5

Input/Output

AE2

VSS

Power/Other

—

AB6

Input/Output

AE3

RESERVED

VSS

—

AB7

—

AE4

—

AB8

VCC

VSS

—

AE5

Power/Other

—

AB23

AB24

AB25

AB26

AB27

AB28

AB29

AB30

AC1

—

AE6

RESERVED

VSS

—

VSS

—

AE7

Power/Other

—

VSS

—

AE8

SKTOCC#

VCC

Output

—

VSS

—

AE9

VSS

—

AE10

AE11

AE12

AE13

AE14

AE15

AE16

AE17

AE18

AE19

AE20

AE21

AE22

AE23

VSS

—

VSS

—

VCC

—

VSS

—

VCC

—

VSS

—

VSS

—

TMS

DBR#

VSS

Input

VCC

—

AC2

Power/Other

—

Output

VCC

—

AC3

—

VSS

—

AC4

RESERVED

A25#

VSS

—

VSS

—

AC5

Source Synch

Power/Other

Input/Output

VCC

—

AC6

—

VCC

—

AC7

VSS

—

AC8

VCC

—

AC23

AC24

AC25

VCC

—

VCC

—

58

Datasheet

Land Listing and Signal Descriptions

Table 4-2. Numerical Land Assignments

Land

#

Signal Buffer

Type

Land

#

Signal Buffer

Type

Land Name

Direction

Land Name

Direction

AE24

AE25

AE26

AE27

AE28

AE29

AE30

AF1

VSS

TDO

BPM4#

VSS

A28#

A27#

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

TRST#

BPM3#

BPM5#

A30#

A31#

A29#

VSS

Power/Other

TAP

—

AG8

AG9

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

RESERVED

VSS

A32#

A33#

VSS

VCC

VSS

Power/Other

—

AG10

AG11

AG12

AG13

AG14

AG15

AG16

AG17

AG18

AG19

AG20

AG21

AG22

AG23

AG24

AG25

AG26

AG27

AG28

AG29

AG30

AH1

—

Output

—

AF2

Common Clock Input/Output

—

AF3

Power/Other

Source Synch

Power/Other

TAP

—

AF4

Input/Output

—

AF5

Input/Output

—

AF6

—

Input

—

AF7

—

AF8

—

AF9

—

AF10

AF11

AF12

AF13

AF14

AF15

AF16

AF17

AF18

AF19

AF20

AF21

AF22

AF23

AF24

AF25

AF26

AF27

AF28

AF29

AF30

AG1

—

AH2

—

AH3

Power/Other

Source Synch

Power/Other

—

AH4

Input/Output

AH5

Input/Output

AH6

—

AH7

AH8

AH9

AH10

AH11

AH12

AH13

AH14

AH15

AH16

AH17

AH18

AH19

AH20

AH21

VCC

VSS

VCC

VSS

AG2

Common Clock Input/Output

AG3

VSS

AG4

Source Synch

Power/Other

Input/Output

—

VCC

VSS

AG5

AG6

AG7

VCC

Datasheet

59

Land Listing and Signal Descriptions

Table 4-2. Numerical Land Assignments

Land

#

Signal Buffer

Type

Land

#

Signal Buffer

Type

Land Name

Direction

Land Name

Direction

AH22

AH23

AH24

AH25

AH26

AH27

AH28

AH29

AH30

AJ1

VCC

VSS

Power/Other

—

AK6

AK7

RESERVED

VSS

—

Power/Other

Asynch GTL+

Power/Other

—

VSS

AK8

VCC

VSS

—

VCC

AK9

—

VCC

AK10

AK11

AK12

AK13

AK14

AK15

AK16

AK17

AK18

AK19

AK20

AK21

AK22

AK23

AK24

AK25

AK26

AK27

AK28

AK29

AK30

AL1

—

VCC

VSS

—

VCC

—

VCC

—

VCC

VSS

—

BPM1#

BPM0#

ITP_CLK1

VSS

Common Clock Input/Output

—

AJ2

—

AJ3

TAP

Input

VSS

—

AJ4

Power/Other

Source Synch

Power/Other

TAP

—

VCC

VSS

—

AJ5

A34#

A35#

VSS

Input/Output

—

AJ6

Input/Output

—

AJ7

—

VCC

VSS

—

AJ8

VCC

—

AJ9

VCC

—

AJ10

AJ11

AJ12

AJ13

AJ14

AJ15

AJ16

AJ17

AJ18

AJ19

AJ20

AJ21

AJ22

AJ23

AJ24

AJ25

AJ26

AJ27

AJ28

AJ29

AJ30

AK1

VSS

—

VSS

—

VCC

—

VCC

VSS

—

VCC

—

VSS

—

VCC

—

VSS

—

VCC

—

VSS

—

VSS

—

VSS

—

VSS

—

THERMDA

PROCHOT#

VSS

—

VCC

—

AL2

Input/Output

VCC

—

AL3

—

Output

—

VSS

—

AL4

VID5

VID1

VID3

VSS

VCC

—

AL5

VCC

—

AL6

VSS

—

AL7

VSS

—

AL8

VCC

VSS

—

VCC

—

AL9

—

VCC

—

AL10

AL11

AL12

AL13

AL14

AL15

AL16

AL17

AL18

AL19

—

VSS

—

VCC

VSS

—

VSS

—

VSS

—

VSS

—

VCC

VSS

—

THERMDC

VSS

—

AK2

—

AK3

ITP_CLK0

VID4

VSS

Input

Output

—

VSS

—

AK4

Power/Other

VCC

—

AK5

—

60

Datasheet

Land Listing and Signal Descriptions

Table 4-2. Numerical Land Assignments

Land

#

Signal Buffer

Type

Land

#

Signal Buffer

Type

Land Name

Direction

Land Name

Direction

AL20

AL21

AL22

AL23

AL24

AL25

AL26

AL27

AL28

AL29

AL30

AM1

VSS

VCC

VSS

Power/Other

—

AN4

AN5

VSS_SENSE

Power/Other

Output

VCC_MB_

REGULATION

—

VSS_MB_

REGULATION

AN6

Power/Other

Output

—

VSS

—

AN7

AN8

VID_SELECT

VCC

VSS

Power/Other

Output

—

VCC

VSS

—

AN9

—

AN10

AN11

AN12

AN13

AN14

AN15

AN16

AN17

AN18

AN19

AN20

AN21

AN22

AN23

AN24

AN25

AN26

AN27

AN28

AN29

AN30

NOTES:

VSS

—

VCC

VSS

VCC

VSS

—

VCC

VSS

AM2

VID0

VID2

VSS

Output

—

AM3

AM4

VSS

AM5

VID6

VTTPWRGD

VID7

VCC

VSS

Output

Input

Output

—

VCC

VSS

AM6

AM7

AM8

VCC

VSS

AM9

—

AM10

AM11

AM12

AM13

AM14

AM15

AM16

AM17

AM18

AM19

AM20

AM21

AM22

AM23

AM24

AM25

AM26

AM27

AM28

AM29

AM30

AN1

—

VCC

VSS

—

VSS

—

VCC

VSS

—

VCC

VSS

—

VSS

—

VCC

VSS

—

VCC

VSS

—

1. EDRDY# and PC_REQ# are not features of the

Celeron D processor in the 775-land package.

They are included here for future processor com-

patibility.

—

VCC

VSS

—

VSS

—

VCC

VSS

—

VSS

—

VCC

VSS

—

AN2

VSS

—

AN3

VCC_SENSE

Output

Datasheet

61

Land Listing and Signal Descriptions

4.2

Alphabetical Signals Reference

Table 4-3. Signal Description (Sheet 1 of 9)

Name

Type

Description

A[35:3]# (Address) define a 2³⁶-byte physical memory address space. In

sub-phase 1 of the address phase, these signals transmit the address of a

transaction. In sub-phase 2, these signals transmit transaction type

information. These signals must connect the appropriate pins/lands of all

agents on the processor FSB. A[35:3]# are protected by parity signals

AP[1:0]#. A[35:3]# are source synchronous signals and are latched into the

receiving buffers by ADSTB[1:0]#.

Input/

Output

A[35:3]#

On the active-to-inactive transition of RESET#, the processor samples a

subset of the A[35:3]# signals to determine power-on configuration. See

Section 6.1 for more details.

If A20M# (Address-20 Mask) is asserted, the processor masks physical

address bit 20 (A20#) before looking up a line in any internal cache and

before driving a read/write transaction on the bus. Asserting A20M#

emulates the 8086 processor's address wrap-around at the 1-MB

boundary. Assertion of A20M# is only supported in real mode.

A20M#

ADS#

Input

A20M# is an asynchronous signal. However, to ensure recognition of this

signal following an Input/Output write instruction, it must be valid along with

the TRDY# assertion of the corresponding Input/Output Write bus

transaction.

ADS# (Address Strobe) is asserted to indicate the validity of the transaction

address on the A[35:3]# and REQ[4:0]# signals. All bus agents observe the

ADS# activation to begin parity checking, protocol checking, address

decode, internal snoop, or deferred reply ID match operations associated

with the new transaction.

Input/

Output

Address strobes are used to latch A[35:3]# and REQ[4:0]# on their rising

and falling edges. Strobes are associated with signals as shown below.

Signals

Associated Strobe

Input/

Output

ADSTB[1:0]#

REQ[4:0]#, A[16:3]#

A[35:17]#

ADSTB0#

ADSTB1#

AP[1:0]# (Address Parity) are driven by the request initiator along with

ADS#, A[35:3]#, and the transaction type on the REQ[4:0]#. A correct

parity signal is high if an even number of covered signals are low and low if

an odd number of covered signals are low. This allows parity to be high

when all the covered signals are high. AP[1:0]# should connect the

appropriate pins/lands of all Celeron D processor in the 775-land package

FSB agents. The following table defines the coverage model of these

signals.

Input/

Output

AP[1:0]#

Request Signals

Subphase 1

Subphase 2

A[35:24]#

A[23:3]#

AP0#

AP1#

AP0#

REQ[4:0]#

62

Datasheet

Land Listing and Signal Descriptions

Table 4-3. Signal Description (Sheet 2 of 9)

Name

Type

Description

The differential pair BCLK (Bus Clock) determines the FSB frequency. All

processor FSB agents must receive these signals to drive their outputs and

latch their inputs.

BCLK[1:0]

Input

All external timing parameters are specified with respect to the rising edge

of BCLK0 crossing V_CROSS

.

BINIT# (Bus Initialization) may be observed and driven by all processor

FSB agents and if used, must connect the appropriate pins/lands of all

such agents. If the BINIT# driver is enabled during power-on configuration,

BINIT# is asserted to signal any bus condition that prevents reliable future

operation.

If BINIT# observation is enabled during power-on configuration, and

BINIT# is sampled asserted, symmetric agents reset their bus LOCK#

activity and bus request arbitration state machines. The bus agents do not

reset their IOQ and transaction tracking state machines upon observation

of BINIT# activation. Once the BINIT# assertion has been observed, the

bus agents will re-arbitrate for the FSB and attempt completion of their bus

queue and IOQ entries.

Input/

Output

BINIT#

If BINIT# observation is disabled during power-on configuration, a central

agent may handle an assertion of BINIT# as appropriate to the error

handling architecture of the system.

BNR# (Block Next Request) is used to assert a bus stall by any bus agent

who is unable to accept new bus transactions. During a bus stall, the

current bus owner cannot issue any new transactions.

Input/

Output

BNR#

This input is required to determine whether the processor is installed in a

platform that supports the Celeron D processor in the 775-land package.

The Celeron D processor in the 775-land package will not operate if this

BOOTSELECT

Input

signal is low. This input has a weak internal pull-up to V_TT

.

BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor

signals. They are outputs from the processor that indicate the status of

breakpoints and programmable counters used for monitoring processor

performance. BPM[5:0]# should connect the appropriate pins/lands of all

processor FSB agents.

BPM4# provides PRDY# (Probe Ready) functionality for the TAP port.

PRDY# is a processor output used by debug tools to determine processor

debug readiness.

Input/

Output

BPM[5:0]#

BPM5# provides PREQ# (Probe Request) functionality for the TAP port.

PREQ# is used by debug tools to request debug operation of the

processor.

These signals do not have on-die termination. Refer to Section 2.5 for

termination requirements.

BPRI# (Bus Priority Request) is used to arbitrate for ownership of the

processor FSB. It must connect the appropriate pins/lands of all processor

FSB agents. Observing BPRI# active (as asserted by the priority agent)

causes all other agents to stop issuing new requests, unless such requests

are part of an ongoing locked operation. The priority agent keeps BPRI#

asserted until all of its requests are completed, then releases the bus by

de-asserting BPRI#.

BPRI#

Input

BR0# drives the BREQ0# signal in the system and is used by the

processor to request the bus. During power-on configuration this signal is

sampled to determine the agent ID = 0.

Input/

Output

BR0#

This signal does not have on-die termination and must be terminated.

The BCLK[1:0] frequency select signals BSEL[2:0] are used to select the

processor input clock frequency. Table 2-6 defines the possible

combinations of the signals and the frequency associated with each

combination. The required frequency is determined by the processor,

chipset, and clock synthesizer. All agents must operate at the same

frequency. For more information about these signals, refer to Section 2.9.

BSEL[2:0]

Output

Datasheet

63

Land Listing and Signal Descriptions

Table 4-3. Signal Description (Sheet 3 of 9)

Name

COMP[1:0]

Type

Description

COMP[1:0] must be terminated to V_SSon the system board using precision

resistors.

Analog

For future processor compatibility COMP[3:2] must be terminated to V_TTon

the system board using precision resistors.

COMP[3:2]

COMP[5:4]

Analog

For future processor compatibility, COMP[5:4] must be terminated to V_TT

on the system board using precision resistors.

D[63:0]# (Data) are the data signals. These signals provide a 64-bit data

path between the processor FSB agents, and must connect the appropriate

pins/lands on all such agents. The data driver asserts DRDY# to indicate a

valid data transfer.

D[63:0]# are quad-pumped signals and will thus be driven four times in a

common clock period. D[63:0]# are latched off the falling edge of both

DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond

to a pair of one DSTBP# and one DSTBN#. The following table shows the

grouping of data signals to data strobes and DBI#.

Quad-Pumped Signal Groups

Input/

Output

DSTBN#/

DSTBP#

D[63:0]#

Data Group

DBI#

D[15:0]#

D[31:16]#

D[47:32]#

D[63:48]#

0

1

2

3

0

1

2

3

Furthermore, the DBI# signals determine the polarity of the data signals.

Each group of 16 data signals corresponds to one DBI# signal. When the

DBI# signal is active, the corresponding data group is inverted and

therefore sampled active high.

DBI[3:0]# (Data Bus Inversion) are source synchronous and indicate the

polarity of the D[63:0]# signals.The DBI[3:0]# signals are activated when

the data on the data bus is inverted. If more than half the data bits, within a

16-bit group, would have been asserted electrically low, the bus agent may

invert the data bus signals for that particular sub-phase for that 16-bit

group.

DBI[3:0] Assignment To Data Bus

Input/

DBI[3:0]#

Output

Bus Signal

Data Bus Signals

DBI3#

DBI2#

DBI1#

DBI0#

D[63:48]#

D[47:32]#

D[31:16]#

D[15:0]#

DBR# is used only in processor systems where no debug port is

implemented on the system board. DBR# is used by a debug port

DBR#

Output interposer so that an in-target probe can drive system reset. If a debug port

is implemented in the system, DBR# is a no connect in the system. DBR#

is not a processor signal.

DBSY# (Data Bus Busy) is asserted by the agent responsible for driving

Input/ data on the processor FSB to indicate that the data bus is in use. The data

Output bus is released after DBSY# is de-asserted. This signal must connect the

appropriate pins/lands on all processor FSB agents.

DBSY#

64

Datasheet

Land Listing and Signal Descriptions

Table 4-3. Signal Description (Sheet 4 of 9)

Name

Type

Description

DEFER# is asserted by an agent to indicate that a transaction cannot be

guaranteed in-order completion. Assertion of DEFER# is normally the

responsibility of the addressed memory or Input/Output agent. This signal

must connect the appropriate pins/lands of all processor FSB agents.

DEFER#

Input

DP[3:0]# (Data Parity) provide parity protection for the D[63:0]# signals.

They are driven by the agent responsible for driving D[63:0]#, and must

connect the appropriate pins/lands of all processor FSB agents.

Input/

Output

DP[3:0]#

DRDY#

DRDY# (Data Ready) is asserted by the data driver on each data transfer,

Input/ indicating valid data on the data bus. In a multi-common clock data

Output transfer, DRDY# may be de-asserted to insert idle clocks. This signal must

connect the appropriate pins/lands of all processor FSB agents.

Data strobe used to latch in D[63:0]#.

Signals

Associated Strobe

D[15:0]#, DBI0#

D[31:16]#, DBI1#

D[47:32]#, DBI2#

D[63:48]#, DBI3#

DSTBN0#

DSTBN1#

DSTBN2#

DSTBN3#

Input/

Output

DSTBN[3:0]#

Data strobe used to latch in D[63:0]#.

Signals

Associated Strobe

D[15:0]#, DBI0#

D[31:16]#, DBI1#

D[47:32]#, DBI2#

D[63:48]#, DBI3#

DSTBP0#

DSTBP1#

DSTBP2#

DSTBP3#

Input/

Output

DSTBP[3:0]#

This signal indicates to the processor that the memory controller is about to

drive data on the bus based on a read request. The signal is driven from

the memory controller one BCLK[1:0] prior to data being driven on the bus.

EDRDY# is not a feature of the Celeron D processor in the 775-land

package. It is included here for future processor compatibility.

EDRDY#

Input

FERR#/PBE# (Floating Point Error/Pending Break Event) is a multiplexed

signal and its meaning is qualified by STPCLK#. When STPCLK# is not

asserted, FERR#/PBE# indicates a floating-point error and will be asserted

when the processor detects an unmasked floating-point error. When

STPCLK# is not asserted, FERR#/PBE# is similar to the ERROR# signal

on the Intel 387 coprocessor, and is included for compatibility with systems

using MS-DOS*-type floating-point error reporting. When STPCLK# is

FERR#/PBE#

Output asserted, an assertion of FERR#/PBE# indicates that the processor has a

pending break event waiting for service. The assertion of FERR#/PBE#

indicates that the processor should be returned to the Normal state. For

additional information on the pending break event functionality, including

the identification of support of the feature and enable/disable information,

refer to volume 3 of the Intel Architecture Software Developer's Manual and

the Intel Processor Identification and the CPUID Instruction application

note.

GTLREF0 determines the signal reference level for GTL+ input signals.

GTLREF1 is not a feature of the Celeron D processor in the 775-Land

GTLREF[1:0]

Input

package. It is included here for future processor compatibility. GTLREF0 is

used by the GTL+ receivers to determine if a signal is a logical 0 or logical

1.

Datasheet

65

Land Listing and Signal Descriptions

Table 4-3. Signal Description (Sheet 5 of 9)

Name

Type

Description

GTLREF_SEL

Output GTLREF_SEL is used to select the appropriate chipset GTLREF voltage.

Input/ HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop

Output operation results. Any FSB agent may assert both HIT# and HITM#

together to indicate that it requires a snoop stall, which can be continued by

HIT#

reasserting HIT# and HITM# together.

HITM#

Input/

Output

IERR# (Internal Error) is asserted by a processor as the result of an

internal error. Assertion of IERR# is usually accompanied by a

SHUTDOWN transaction on the processor FSB. This transaction may

optionally be converted to an external error signal (e.g., NMI) by system

IERR#

Output

core logic. The processor will keep IERR# asserted until the assertion of

RESET#.

This signal does not have on-die termination. Refer to Section 2.5 for

termination requirements.

IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore

a numeric error and continue to execute noncontrol floating-point

instructions. If IGNNE# is de-asserted, the processor generates an

exception on a noncontrol floating-point instruction if a previous floating-

point instruction caused an error. IGNNE# has no effect when the NE bit in

IGNNE#

Input

control register 0 (CR0) is set.

IGNNE# is an asynchronous signal. However, to ensure recognition of this

signal following an input/output write instruction, it must be valid along with

the TRDY# assertion of the corresponding Input/Output Write bus

transaction.

INIT# (Initialization), when asserted, resets integer registers inside the

processor without affecting its internal caches or floating-point registers.

The processor then begins execution at the power-on Reset vector

configured during power-on configuration. The processor continues to

handle snoop requests during INIT# assertion. INIT# is an asynchronous

signal and must connect the appropriate pins/lands of all processor FSB

agents.

INIT#

Input

If INIT# is sampled active on the active to inactive transition of RESET#,

then the processor executes its Built-in Self-Test (BIST).

ITP_CLK[1:0] are copies of BCLK that are used only in processor systems

where no debug port is implemented on the system board. ITP_CLK[1:0]

are used as BCLK[1:0] references for a debug port implemented on an

interposer. If a debug port is implemented in the system, ITP_CLK[1:0] are

no connects in the system. These are not processor signals.

ITP_CLK[1:0]

LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins/lands of

all APIC Bus agents. When the APIC is disabled, the LINT0 signal

becomes INTR, a maskable interrupt request signal, and LINT1 becomes

NMI, a nonmaskable interrupt. INTR and NMI are backward compatible

with the signals of those names on the Pentium processor. Both signals are

asynchronous.

LINT[1:0]

Input

Both of these signals must be software configured via BIOS programming

of the APIC register space to be used either as NMI/INTR or LINT[1:0].

Because the APIC is enabled by default after Reset, operation of these

signals as LINT[1:0] is the default configuration.

The LL_ID[1:0] signals are used to select the correct loadline slope for the

processor.

LL_ID[1:0]

Output

66

Datasheet

Land Listing and Signal Descriptions

Table 4-3. Signal Description (Sheet 6 of 9)

Name

Type

Description

LOCK# indicates to the system that a transaction must occur atomically.

This signal must connect the appropriate pins/lands of all processor FSB

agents. For a locked sequence of transactions, LOCK# is asserted from

the beginning of the first transaction to the end of the last transaction.

Input/

Output

LOCK#

When the priority agent asserts BPRI# to arbitrate for ownership of the

processor FSB, it will wait until it observes LOCK# de-asserted. This

enables symmetric agents to retain ownership of the processor FSB

throughout the bus locked operation and ensure the atomicity of lock.

MCERR# (Machine Check Error) is asserted to indicate an unrecoverable

error without a bus protocol violation. It may be driven by all processor FSB

agents.

MCERR# assertion conditions are configurable at a system level. Assertion

options are defined by the following options:

•

Enabled or disabled.

Input/

Output

MCERR#

Asserted, if configured, for internal errors along with IERR#.

Asserted, if configured, by the request initiator of a bus transaction

after it observes an error.

•

Asserted by any bus agent when it observes an error in a bus

transaction.

For more details regarding machine check architecture, refer to the IA-32

Software Developer’s Manual, Volume 3: System Programming Guide.

These signals are provided to indicate the Market Segment for the

processor and may be used for future processor compatibility or for keying.

MS_ID[1:0]

PC_REQ#

Output

This signal provides an external bus indicator that the processor is done

with the DRAM page and that the DRAM page could/should be closed.

PC_REQ# is not a feature of the Celeron D processor in the 775-land

package. It is included here for future processor compatibility.

As an output, PROCHOT# (Processor Hot) will go active when the

processor temperature monitoring sensor detects that the processor has

reached its maximum safe operating temperature. This indicates that the

processor Thermal Control Circuit (TCC) has been activated, if enabled. As

an input, assertion of PROCHOT# by the system will activate the TCC, if

enabled. The TCC will remain active until the system de-asserts

PROCHOT#. See Section 5.2.4 for more details.

Input/

Output

PROCHOT#

PWRGOOD (Power Good) is a processor input. The processor requires

this signal to be a clean indication that the clocks and power supplies are

stable and within their specifications. ‘Clean’ implies that the signal will

remain low (capable of sinking leakage current), without glitches, from the

time that the power supplies are turned on until they come within

specification. The signal must then transition monotonically to a high state.

PWRGOOD can be driven inactive at any time, but clocks and power must

again be stable before a subsequent rising edge of PWRGOOD.

PWRGOOD

Input

The PWRGOOD signal must be supplied to the processor; it is used to

protect internal circuits against voltage sequencing issues. It should be

driven high throughout boundary scan operation.

REQ[4:0]# (Request Command) must connect the appropriate pins/lands

of all processor FSB agents. They are asserted by the current bus owner to

define the currently active transaction type. These signals are source

synchronous to ADSTB0#. Refer to the AP[1:0]# signal description for a

details on parity checking of these signals.

Input/

Output

REQ[4:0]#

Datasheet

67

Land Listing and Signal Descriptions

Table 4-3. Signal Description (Sheet 7 of 9)

Name

Type

Description

Asserting the RESET# signal resets the processor to a known state and

invalidates its internal caches without writing back any of their contents. For

a power-on Reset, RESET# must stay active for at least one millisecond

after V_CCand BCLK have reached their proper specifications. On

observing active RESET#, all FSB agents will de-assert their outputs within

two clocks. RESET# must not be kept asserted for more than 10 ms while

PWRGOOD is asserted.

RESET#

Input

A number of bus signals are sampled at the active-to-inactive transition of

RESET# for power-on configuration. These configuration options are

described in the Section 6.1.

This signal does not have on-die termination and must be terminated on

the system board.

RS[2:0]# (Response Status) are driven by the response agent (the agent

responsible for completion of the current transaction), and must connect

the appropriate pins/lands of all processor FSB agents.

RS[2:0]#

RSP#

Input

RSP# (Response Parity) is driven by the response agent (the agent

responsible for completion of the current transaction) during assertion of

RS[2:0]#, the signals for which RSP# provides parity protection. It must

connect to the appropriate pins/lands of all processor FSB agents.

A correct parity signal is high if an even number of covered signals are low

and low if an odd number of covered signals are low. While RS[2:0]# = 000,

RSP# is also high, since this indicates it is not being driven by any agent

guaranteeing correct parity.

SKTOCC# (Socket Occupied) will be pulled to ground by the processor.

SKTOCC#

SMI#

Output System board designers may use this signal to determine if the processor

is present.

SMI# (System Management Interrupt) is asserted asynchronously by

system logic. On accepting a System Management Interrupt, the processor

saves the current state and enter System Management Mode (SMM). An

SMI Acknowledge transaction is issued, and the processor begins program

execution from the SMM handler.

Input

If SMI# is asserted during the de-assertion of RESET# the processor will

tristate its outputs.

STPCLK# (Stop Clock), when asserted, causes the processor to enter a

low power Stop-Grant state. The processor issues a Stop-Grant

Acknowledge transaction, and stops providing internal clock signals to all

processor core units except the FSB and APIC units. The processor

continues to snoop bus transactions and service interrupts while in Stop-

Grant state. When STPCLK# is de-asserted, the processor restarts its

internal clock to all units and resumes execution. The assertion of

STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous

input.

STPCLK#

Input

TCK (Test Clock) provides the clock input for the processor Test Bus (also

known as the Test Access Port).

TCK

Input

TDI (Test Data In) transfers serial test data into the processor. TDI provides

the serial input needed for JTAG specification support.

TDI

TDO (Test Data Out) transfers serial test data out of the processor. TDO

provides the serial output needed for JTAG specification support.

TDO

Output

Input

TESTHI[13:0] must be connected to a V_TTpower source through a resistor

for proper processor operation. See Section 2.5 for more details.

TESTHI[13:0]

THERMDA

THERMDC

Other Thermal Diode Anode. See Section 5.2.7.

Other Thermal Diode Cathode. See Section 5.2.7.

68

Datasheet

Land Listing and Signal Descriptions

Table 4-3. Signal Description (Sheet 8 of 9)

Name

Type

Description

In the event of a catastrophic cooling failure, the processor will

automatically shut down when the silicon has reached a temperature

approximately 20 °C above the maximum T_C. Assertion of THERMTRIP#

(Thermal Trip) indicates the processor junction temperature has reached a

level beyond which permanent silicon damage may occur. Upon assertion

of THERMTRIP#, the processor will shut off its internal clocks (thus halting

program execution) in an attempt to reduce the processor junction

temperature. To protect the processor, its core voltage (V_CC) must be

removed following the assertion of THERMTRIP#. Driving of the

THERMTRIP# signal is enabled within 10 μs of the assertion of

PWRGOOD and is disabled on de-assertion of PWRGOOD. Once

activated, THERMTRIP# remains latched until PWRGOOD is de-asserted.

While the de-assertion of the PWRGOOD signal will de-assert

THERMTRIP#, if the processor’s junction temperature remains at or above

the trip level, THERMTRIP# will again be asserted within 10 μs of the

assertion of PWRGOOD.

THERMTRIP#

Output

TMS (Test Mode Select) is a JTAG specification support signal used by

debug tools.

TMS

Input

TRDY# (Target Ready) is asserted by the target to indicate that it is ready

to receive a write or implicit writeback data transfer. TRDY# must connect

the appropriate pins/lands of all FSB agents.

TRDY#

TRST#

TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must

be driven low during power on Reset.

VCC are the power pins for the processor. The voltage supplied to these

pins is determined by the VID[5:0] pins.

VCC

Input

VCCA

VCCA provides isolated power for the internal processor core PLLs.

VCCIOPLL provides isolated power for internal processor FSB PLLs.

Follow the guidelines for VCCA.

VCCIOPLL

VCC_SENSE is an isolated low impedance connection to processor core

VCC_SENSE

Output power (V_CC). It can be used to sense or measure voltage near the silicon

with little noise.

This land is provided as a voltage regulator feedback sense point for V_CC

.

It is connected internally in the processor package to the sense point land

U27 as described in the Voltage Regulator-Down (VRD) 10.1 Design Guide

for Desktop Socket 775.

VCC_MB_REGULATION

Output

VID[7:6] (Voltage ID) are not used by the Celeron D processor in the 775-

Land package. These signals are included here for future processor

compatibility.

VID[5:0] (Voltage ID) signals are used to support automatic selection of

power supply voltages (V_CC). These are open drain signals that are driven

by the Celeron D processor in the 775-land package and must be pulled up

on the motherboard. Refer to the Voltage Regulator-Down (VRD) 10.1

Design Guide for Desktop Socket 775 for more information. The voltage

supply for these signals must be valid before the VR can supply V_CCto the

processor. Conversely, the VR output must be disabled until the voltage

supply for the VID signals becomes valid. The VID signals are needed to

support the processor voltage specification variations. See Table 2-2 for

definitions of these signals. The VR must supply the voltage that is

requested by the signals, or disable itself.

VID[7:0]

Output

VID_SELECT is used to select the VID table that is to be used by the

voltage regulator.

VID_SELECT

VR Table Used

VID_SELECT

Output

L

VRD10.1

VRD11

H

Datasheet

69

Land Listing and Signal Descriptions

Table 4-3. Signal Description (Sheet 9 of 9)

Name

Type

Description

VSS are the ground pins for the processor and should be connected to the

system ground plane.

VSS

Input

VSSA

VSSA is the isolated ground for internal PLLs.

VSS_SENSE is an isolated low impedance connection to processor core

VSS_SENSE

Output

V_SS. It can be used to sense or measure ground near the silicon with little

noise.

This land is provided as a voltage regulator feedback sense point for V_SS. It

is connected internally in the processor package to the sense point land

V27 as described in the Voltage Regulator-Down (VRD) 10.1 Design Guide

for Desktop Socket 775.

VSS_MB_REGULATION

VTT

FSB termination voltage.

The VTT_OUT_LEFT and VTT_OUT_RIGHT signals are included to

provide a local V_TTfor some signals that require termination to V_TTon the

motherboard.

For future processor compatibility some signals are required to be pulled

up to VTT_OUT_LEFT or VTT_OUT_RIGHT. Refer to the following table

for the signals that should be pulled up to VTT_OUT_LEFT and

VTT_OUT_RIGHT.

VTT_OUT_LEFT

VTT_OUT_RIGHT

Output

Pull Up Signal

Signals to be Pulled Up

VTT_PWRGOOD, VID[5:0], GTLREF, TMS,

TDI, TDO, BPM[5:0], other VRD components

VTT_OUT_RIGHT

RESET#, BR0#, PWRGOOD, TESTHI1,

TESTHI8, TESTHI9, TESTHI10, TESTHI11,

TESTHI12, TESTHI13

VTT_OUT_LEFT

The VTT_SEL signal is used to select the correct V_TTvoltage level for the

processor.

VTT_SEL

Output

Input

The processor requires this input to determine that the V_TTvoltages are

stable and within specification.

VTTPWRGD

§

70

Datasheet

Thermal Specifications and Design Considerations

5 Thermal Specifications and

Design Considerations

5.1

Processor Thermal Specifications

The Celeron D processor in the 775-land package requires a thermal solution to maintain

temperatures within operating limits as set forth in Section 5.1.1. Any attempt to operate the

processor outside these operating limits may result in permanent damage to the processor and

potentially other components within the system. As processor technology changes, thermal

management becomes increasingly crucial when building computer systems. Maintaining the

proper thermal environment is key to reliable, long-term system operation.

A complete thermal solution includes both component and system level thermal management

features. Component level thermal solutions can include active or passive heatsinks attached to the

processor Integrated Heat Spreader (IHS). Typical system level thermal solutions may consist of

system fans combined with ducting and venting.

®

For more information on designing a component level thermal solution, refer to the Intel

®

Pentium 4 Processor on 90 nm Process in the 775-Land LGA Package Thermal Design Guide.

Note: The boxed processor will ship with a component thermal solution. Refer to Chapter 7 for details on

the boxed processor.

5.1.1

Thermal Specifications

To allow for the optimal operation and long-term reliability of Intel processor-based systems, the

system/processor thermal solution should be designed such that the processor remains within the

minimum and maximum case temperature (T ) specifications when operating at or below the

C

Thermal Design Power (TDP) value listed per frequency in Table 5-1. Thermal solutions not

designed to provide this level of thermal capability may affect the long-term reliability of the

processor and system. For more details on thermal solution design, refer to the appropriate

processor thermal design guidelines.

The Celeron D processor in the 775-land package introduces a new methodology for managing

processor temperatures that is intended to support acoustic noise reduction through fan speed

control. Selection of the appropriate fan speed will be based on the temperature reported by the

processor’s Thermal Diode. If the diode temperature is greater than or equal to T

then the

CONTROL

processor case temperature must remain at or below the temperature as specified by the thermal

profile. If the diode temperature is less than T , then the case temperature is permitted to

CONTROL

exceed the thermal profile; however, the diode temperature must remain at or below T

.

CONTROL

Systems that implement fan speed control must be designed to take these conditions into account.

Systems that do not alter the fan speed only need to guarantee the case temperature meets the

thermal profile specifications.

To determine a processor's case temperature specification based on the thermal profile, it is

necessary to accurately measure processor power dissipation. Intel has developed a methodology

for accurate power measurement that correlates to Intel test temperature and voltage conditions.

Datasheet

71

Thermal Specifications and Design Considerations

®

Refer to the Intel Pentium 4 Processor on 90 nm Process in the 775-Land LGA Package

Thermal Design Guide and the Processor Power Characterization Methodology for the details of

this methodology.

The case temperature is defined at the geometric top center of the processor IHS. Analysis

indicates that real applications are unlikely to cause the processor to consume maximum power

dissipation for sustained periods of time. Intel recommends that complete thermal solution designs

target the Thermal Design Power (TDP) indicated in Table 5-1 instead of the maximum processor

power consumption. The Thermal Monitor feature is intended to help protect the processor in the

unlikely event that an application exceeds the TDP recommendation for a sustained period of time.

For more details on the usage of this feature, refer to Section 5.2. To ensure maximum flexibility

for future requirements, systems should be designed to the Platform Compatibility Guide ‘04 A

guidelines, even if a processor with a lower thermal dissipation is currently planned. In all cases,

the Thermal Monitor feature must be enabled for the processor to remain within

specification.

Table 5-1. Processor Thermal Specifications

Processor

Number

Processor Core

Frequency (GHz)

ThermalDesign Minimum T_C

Maximum T_C(°C)

Notes

Power (W)

(°C)

See Table 5-2 and

Figure 5-1

1, 2

325J/326

330J/331

335J/336

340J/341

345J/346

351

2.53

2.66

2.80

2.93

3.06

3.20

3.33

84

5

See Table 5-2 and

Figure 5-1

1, 2

84

5

See Table 5-2 and

Figure 5-1

See Table 5-2 and

Figure 5-1

See Table 5-2 and

Figure 5-1

See Table 5-2 and

Figure 5-1

See Table 5-2 and

Figure 5-1

355

NOTES:

1.

Thermal Design Power (TDP) should be used for processor thermal solution design targets. The TDP is not the maxi-

mum power that the processor can dissipate.

2.

This table shows the maximum TDP for a given frequency range. Individual processors may have a lower TDP. There-

fore, the maximum T will vary depending on the TDP of the individual processor. Refer to thermal profile figure and

C

associated table for the allowed combinations of power and T .

C

72

Datasheet

Thermal Specifications and Design Considerations

Table 5-2. Thermal Profile for Processors

Power (W) Maximum T_C(°C)

Power (W)

Maximum T_C(°C)

Power (W)

Maximum T_C(°C)

0

44.2

44.8

45.3

45.9

46.4

47.0

47.6

48.1

48.7

49.2

49.8

50.4

50.9

51.5

52.0

30

32

34

36

38

40

42

44

46

48

50

52

54

56

58

52.6

53.2

53.7

54.3

54.8

55.4

56.0

56.5

57.1

57.6

58.2

58.8

59.3

59.9

60.4

60

62

64

66

68

70

72

74

76

78

80

82

84

61.0

61.6

62.1

62.7

63.2

63.8

64.4

64.9

65.5

66.0

66.6

67.2

67.7

2

4

6

8

10

12

14

16

18

20

22

24

26

28

Figure 5-1. Thermal Profile for Platform Compatibility Guide ‘04 A Processors

70.0

65.0

y = 0.28x + 44.2

60.0

55.0

50.0

45.0

40.0

0

10

20

30

40

50

60

70

80

Power (W)

Datasheet

73

Thermal Specifications and Design Considerations

5.1.2

Thermal Metrology

The maximum and minimum case temperatures (T ) are specified in Table 5-1. These temperature

C

specifications are meant to help ensure proper operation of the processor. Figure 5-2 illustrates

where Intel recommends T thermal measurements should be made. For detailed guidelines on

C

®

temperature measurement methodology, refer to the Intel Pentium 4 Processor on 90 nm

Process in the 775-Land LGA Package Thermal Design Guide.

Figure 5-2. Case Temperature (T ) Measurement Location

C

Measure from edge of top surface of processor IHS

14.35 mm

Measure T_Cat this point

(geometric center of the

top surface of the IHS)

14.35 mm

37.5 mm x 37.5 mm Substrate

5.2

Processor Thermal Features

5.2.1

Thermal Monitor

The Thermal Monitor feature helps control the processor temperature by activating the TCC when

the processor silicon reaches its maximum operating temperature. The TCC reduces processor

power consumption as needed by modulating (starting and stopping) the internal processor core

clocks. The Thermal Monitor feature must be enabled for the processor to be operating

within specifications. The temperature at which Thermal Monitor activates the thermal control

circuit is not user configurable and is not software visible. Bus traffic is snooped in the normal

manner, and interrupt requests are latched (and serviced during the time that the clocks are on)

while the TCC is active.

When the Thermal Monitor feature is enabled, and a high temperature situation exists (i.e., TCC is

active), the clocks will be modulated by alternately turning the clocks off and on at a duty cycle

specific to the processor (typically 30–50%). Clocks often will not be off for more than 3.0 µs

when the TCC is active. Cycle times are processor speed dependent and will decrease as processor

core frequencies increase. A small amount of hysteresis has been included to prevent rapid active/

inactive transitions of the TCC when the processor temperature is near its maximum operating

temperature. Once the temperature has dropped below the maximum operating temperature, and

the hysteresis timer has expired, the TCC goes inactive and clock modulation ceases.

With a properly designed and characterized thermal solution, it is anticipated that the TCC would

only be activated for very short periods of time when running the most power intensive

applications. The processor performance impact due to these brief periods of TCC activation is

74

Datasheet

Thermal Specifications and Design Considerations

expected to be so minor that it would be immeasurable. An under-designed thermal solution that is

not able to prevent excessive activation of the TCC in the anticipated ambient environment may

cause a noticeable performance loss, and in some cases may result in a T_Cthat exceeds the

specified maximum temperature and may affect the long-term reliability of the processor. In

addition, a thermal solution that is significantly under-designed may not be capable of cooling the

®

processor even when the TCC is active continuously. Refer to the Intel Pentium 4 Processor on

90 nm Process in the 775-Land LGA Package Thermal Design Guide for information on designing

a thermal solution.

The duty cycle for the TCC, when activated by the Thermal Monitor, is factory configured and

cannot be modified. The Thermal Monitor does not require any additional hardware, software

drivers, or interrupt handling routines.

5.2.2

Thermal Monitor 2

The Celeron D processor in the 775-land package also supports a power management capability

known as Thermal Monitor 2. This mechanism provides an efficient mechanism for limiting the

processor temperature by reducing power consumption within the processor.

When Thermal Monitor 2 is enabled, and a high temperature situation is detected, the enhanced

Thermal Control Circuit (TCC) will be activated. This enhanced TCC causes the processor to

adjust its operating frequency (bus multiplier) and input voltage (VID). This combination of

reduced frequency and VID results in a decrease in processor power consumption.

A processor enabled for Thermal Monitor 2 includes two operating points, each consisting of a

specific operating frequency and voltage. The first point represents the normal operating conditions

for the processor.

The second point consists of both a lower operating frequency and voltage. When the enhanced

TCC is activated, the processor automatically transitions to the new frequency. This transition

occurs very rapidly (on the order of 5 μs). During the frequency transition, the processor is unable

to service any bus requests, and consequently, all bus traffic is blocked. Edge-triggered interrupts

will be latched and kept pending until the processor resumes operation at the new frequency.

Once the new operating frequency is engaged, the processor will transition to the new core

operating voltage by issuing a new VID code to the voltage regulator. The voltage regulator must

support VID transitions to support Thermal Monitor 2. During the voltage change, it will be

necessary to transition through multiple VID codes to reach the target operating voltage. Each step

will be one VID table entry (i.e., 12.5 mV steps). The processor continues to execute instructions

during the voltage transition. Operation at this lower voltage reduces both the dynamic and leakage

power consumption of the processor, providing a reduction in power consumption at a minimum

performance impact.

Once the processor has sufficiently cooled and a minimum activation time has expired, the

operating frequency and voltage transition back to the normal system operating point. Transition of

the VID code will occur first, to insure proper operation once the processor reaches its normal

operating frequency. Refer to Figure 5-3 for an illustration of this ordering.

Datasheet

75

Thermal Specifications and Design Considerations

Figure 5-3. Thermal Monitor 2 Frequency and Voltage Ordering

T

TM2

Temperature

f

MAX

f_TM2

Frequency

VID

TM2

VID

PROCHOT#

Time

The PROCHOT# signal is asserted when a high temperature situation is detected, regardless of

whether or not Thermal Monitor or Thermal Monitor 2 is enabled.

It should be noted that the Thermal Monitor 2 TCC can not be activated via the on demand mode.

The Thermal Monitor TCC, however, can be activated through the use of the on-demand mode.

5.2.3

On-Demand Mode

The Celeron D processor in the 775-land package provides an auxiliary mechanism that allows

system software to force the processor to reduce its power consumption. This mechanism is

referred to as "On-Demand" mode and is distinct from the Thermal Monitor feature. On-Demand

mode is intended as a means to reduce system level power consumption. Systems using the Celeron

D processor in the 775-land package must not rely on software usage of this mechanism to limit the

processor temperature.

If bit 4 of the ACPI P_CNT Control Register (located in the processor IA32_THERM_CONTROL

MSR) is written to a '1', the processor will immediately reduce its power consumption via

modulation (starting and stopping) of the internal core clock, independent of the processor

temperature. When using On-Demand mode, the duty cycle of the clock modulation is

programmable via bits 3:1 of the same ACPI P_CNT Control Register. In On-Demand mode, the

duty cycle can be programmed from 12.5% on/ 87.5% off, to 87.5% on/12.5% off in 12.5%

increments. On-Demand mode may be used in conjunction with the Thermal Monitor. If the system

tries to enable On-Demand mode at the same time the TCC is engaged, the factory configured duty

cycle of the TCC will override the duty cycle selected by the On-Demand mode.

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Thermal Specifications and Design Considerations

5.2.4

PROCHOT# Signal

An external signal, PROCHOT# (processor hot), is asserted when the processor die temperature

has reached its maximum operating temperature. If the Thermal Monitor is enabled (note that the

Thermal Monitor must be enabled for the processor to be operating within specification), the TCC

will be active when PROCHOT# is asserted. The processor can be configured to generate an

interrupt upon the assertion or de-assertion of PROCHOT#. Refer to the Intel Architecture

Software Developer's Manuals for specific register and programming details.

The Celeron D processor in the 775-land package implements a bi-directional PROCHOT#

capability to allow system designs to protect various components from over-temperature situations.

The PROCHOT# signal is bi-directional in that it can either signal when the processor has reached

its maximum operating temperature or be driven from an external source to activate the TCC. The

ability to activate the TCC via PROCHOT# can provide a means for thermal protection of system

components.

One application is the thermal protection of voltage regulators (VR). System designers can create a

circuit to monitor the VR temperature and activate the TCC when the temperature limit of the VR

is reached. By asserting PROCHOT# (pulled-low) and activating the TCC, the VR can cool down

as a result of reduced processor power consumption. Bi-directional PROCHOT# can allow VR

thermal designs to target maximum sustained current instead of maximum current. Systems should

still provide proper cooling for the VR, and rely on bi-directional PROCHOT# only as a backup in

case of system cooling failure. The system thermal design should allow the power delivery

circuitry to operate within its temperature specification even while the processor is operating at its

Thermal Design Power. With a properly designed and characterized thermal solution, it is

anticipated that bi-directional PROCHOT# would only be asserted for very short periods of time

when running the most power intensive applications. An under-designed thermal solution that is

not able to prevent excessive assertion of PROCHOT# in the anticipated ambient environment may

cause a noticeable performance loss. Refer to the Voltage Regulator-Down (VRD) 10.1 Design

Guide for Desktop Socket 775 for details on implementing the bi-directional PROCHOT# feature.

5.2.5

5.2.6

THERMTRIP# Signal

Regardless of whether or not the Thermal Monitor feature is enabled, in the event of a catastrophic

cooling failure, the processor will automatically shut down when the silicon has reached an

elevated temperature (refer to the THERMTRIP# definition in Table 4-3). At this point, the FSB

signal THERMTRIP# will go active and stay active as described in Table 4-3. THERMTRIP#

activation is independent of processor activity and does not generate any bus cycles.

T_CONTROLand Fan Speed Reduction

T

is a temperature specification based on a temperature reading from the thermal diode.

CONTROL

The value for T

will be calibrated in manufacturing and configured for each processor.

CONTROL

When T

is above T

, then T must be at or below T

as defined by the thermal

DIODE

CONTROL

C

C-MAX

profile in Table 5-2 and Figure 5-1. Otherwise, the processor temperature can be maintained at

(or lower) as measured by the thermal diode.

T

CONTROL

The purpose of this feature is to support acoustic optimization through fan speed control. Contact

your Intel representative for further details and documentation.

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77

Thermal Specifications and Design Considerations

5.2.7

Thermal Diode

The processor incorporates an on-die thermal diode. A thermal sensor located on the system board

may monitor the die temperature of the processor for thermal management/long term die

temperature change purposes. Table 5-3 and Table 5-4 provide the diode parameter and interface

specifications. This thermal diode is separate from the Thermal Monitor’s thermal sensor and

cannot be used to predict the behavior of the Thermal Monitor.

Table 5-3. Thermal Diode Parameters

Symbol

I_FW

Parameter

Forward Bias Current

Min

Typ

Max

Unit

Notes

1

11

—

187

µA

—

Ω

2, 3, 4, 5

2, 3, 6

n

Diode Ideality Factor

Series Resistance

1.0083

3.242

1.011

3.33

1.023

3.594

R_T

NOTES:

1.

2.

3.

4.

Intel does not support or recommend operation of the thermal diode under reverse bias.

Characterized at 75 °C.

Not 100% tested. Specified by design characterization.

The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode equation:

qV /nkT

I

= I * (e

D

–1)

FW

S

where I = saturation current, q = electronic charge, V = voltage across the diode, k = Boltzmann Constant, and

S

D

T = absolute temperature (Kelvin).

5.

6.

Devices found to have an ideality factor in the range of +3 n to +5 n will create a temperature error approximately 2° C higher

than the actual temperature. To minimize any potential acoustic impact of this temperature error, T

by 2° C on these parts. Processors with an ideality between ±3 n will not be affected.

will be increased

CONTROL

The series resistance, R , is provided to allow for a more accurate measurement of the diode temperature. R , as defined,

T

includes the lands of the processor but does not include any socket resistance or board trace resistance between the socket

and the external remote diode thermal sensor. R can be used by remote diode thermal sensors with automatic series re-

T

sistance cancellation to calibrate out this error term. Another application is that a temperature offset can be manually calcu-

lated and programmed into an offset register in the remote diode thermal sensors as exemplified by the equation:

T

= [R * (N-1) * I

] / [nk/q * ln N]

error

T

FWmin

where T

= sensor temperature error, N = sensor current ratio, k = Boltzmann Constant, q = electronic charge.

error

Table 5-4. Thermal Diode Interface

Signal Name

Land Number

Signal Description

THERMDA

THERMDC

AL1

AK1

diode anode

diode cathode

§

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Datasheet

Features

6 Features

This chapter contains power-on configuration options and clock control/low power state

descriptions.

6.1

Power-On Configuration Options

Several configuration options can be configured by hardware. The Celeron D processor in the

775-land package samples the hardware configuration at reset, on the active-to-inactive transition

of RESET#. For specifications on these options, refer to Table 6-1.

The sampled information configures the processor for subsequent operation. These configuration

options cannot be changed except by another reset. All resets reconfigure the processor; for reset

purposes, the processor does not distinguish between a "warm" reset and a "power-on" reset.

Table 6-1. Power-On Configuration Option Signals

Configuration Option

Signal^{1, 2}

Output tristate

SMI#

Execute BIST

INIT#

In Order Queue pipelining (set IOQ depth to 1)

Disable MCERR# observation

Disable BINIT# observation

APIC Cluster ID (0-3)

Disable bus parking

A7#

A9#

A10#

A[12:11]#

A15#

BR0#

Symmetric agent arbitration ID

RESERVED

A[6:3]#, A8#, A[14:13]#, A[16:30]#, A[32:35]#

NOTES:

1.

2.

Asserting this signal during RESET# will select the corresponding option.

Address signals not identified in this table as configuration options should not be asserted during RESET#.

6.2

Clock Control and Low Power States

The processor allows the use of AutoHALT and Stop-Grant to reduce power consumption by

stopping the clock to internal sections of the processor, depending on each particular state. See

Figure 6-1 for a visual representation of the processor low power states.

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79

Features

Figure 6-1. Processor Low Power State Machine

HALT or MWAIT Instruction and

HALT Bus Cycle Generated

HALT State

BCLK running

Snoops and interrupts allow ed

Norm al State

Normal execution

INIT#, BINIT#, INTR, NMI, SMI#,

RESET#, FSB interrupts

Snoop

Event

Occurs

Snoop

Event

Serviced

STPCLK#

Asserted

STPCLK#

De-asserted

HALT Snoop State

BCLK running

Service snoops to caches

Snoop Event Occurs

Snoop Event Serviced

Stop-GrantState

Grant Snoop State

BCLK running

Snoops and interrupts allow ed

Service snoops to caches

6.2.1

6.2.2

Normal State

This is the normal operating state for the processor.

HALT Powerdown State

HALT is a low power state entered when all the logical processors have executed the HALT or

MWAIT instructions. When one of the logical processors executes the HALT instruction, that

logical processor is halted; however, the other processor continues normal operation. The processor

will transition to the Normal state upon the occurrence of SMI#, BINIT#, INIT#, or LINT[1:0]

(NMI, INTR). RESET# will cause the processor to immediately initialize itself.

The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or

the HALT Power Down state. See the Intel Architecture Software Developer's Manual, Volume III:

System Programmer's Guide for more information.

The system can generate a STPCLK# while the processor is in the HALT Power Down state. When

the system de-asserts the STPCLK# interrupt, the processor will return execution to the HALT

state.

While in HALT Power Down state, the processor will process bus snoops.

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Features

6.2.3

Stop-Grant States

When the STPCLK# signal is asserted, the Stop-Grant state of the processor is entered 20 bus

clocks after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle.

Since the GTL+ signals receive power from the FSB, these signals should not be driven (allowing

the level to return to V ) for minimum power drawn by the termination resistors in this state. In

TT

addition, all other input signals on the FSB should be driven to the inactive state.

BINIT# will not be serviced while the processor is in Stop-Grant state. The event will be latched

and can be serviced by software upon exit from the Stop Grant state.

RESET# will cause the processor to immediately initialize itself, but the processor will stay in

Stop-Grant state. A transition back to the Normal state will occur with the de-assertion of the

STPCLK# signal.

A transition to the HALT/Grant Snoop state will occur when the processor detects a snoop on the

FSB (see Section 6.2.4).

While in the Stop-Grant state, SMI#, INIT#, BINIT# and LINT[1:0] will be latched by the

processor, and only serviced when the processor returns to the Normal state. Only one occurrence

of each event will be recognized upon return to the Normal state.

While in Stop-Grant state, the processor will process a FSB snoop.

6.2.4

HALT Snoop State, Grant Snoop State

The processor will respond to snoop transactions on the FSB while in Stop-Grant state or in HALT

Power Down state. During a snoop transaction, the processor enters the HALT:Grant Snoop state.

The processor will stay in this state until the snoop on the FSB has been serviced (whether by the

processor or another agent on the FSB). After the snoop is serviced, the processor will return to the

Stop-Grant state or HALT Power Down state, as appropriate.

§

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81

Features

82

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Boxed Processor Specifications

7 Boxed Processor Specifications

The Celeron D processor in the 775-land package will also be offered as an boxed Intel processor.

Boxed Intel processors are intended for system integrators who build systems from baseboards and

standard components. The boxed Celeron D processor in the 775-land package will be supplied

with a cooling solution. This chapter documents baseboard and system requirements for the

cooling solution that will be supplied with the boxed Celeron D processor in the 775-land package.

This chapter is particularly important for OEMs that manufacture baseboards for system

integrators. Figure 7-1 shows a mechanical representation of a boxed Celeron D processor in the

775-land package.

Note: Unless otherwise noted, all figures in this chapter are dimensioned in millimeters and

inches [in brackets].

Note: Drawings in this section reflect only the specifications on the boxed Intel processor product. These

dimensions should not be used as a generic keep-out zone for all cooling solutions. It is the system

designer’s responsibility to consider their proprietary cooling solution when designing to the

®

required keep-out zone on their system platforms and chassis. Refer to the Intel Pentium 4

Processor on 90 nm Process in the 775-Land LGA Package Thermal Design Guide for further

guidance.

Figure 7-1. Mechanical Representation of the Boxed Processor

NOTE: The airflow of the fan heatsink is into the center and out of the sides of the fan heatsink.

Datasheet

83

Boxed Processor Specifications

7.1

Mechanical Specifications

7.1.1

Boxed Processor Cooling Solution Dimensions

This section documents the mechanical specifications of the boxed Celeron D processor in the

775- land package fan heatsink. The boxed processor will be shipped with an unattached fan

heatsink. Figure 7-1 shows a mechanical representation of the boxed Pentium 4 processor in the

775-land package.

Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling. The

physical space requirements and dimensions for the boxed processor with assembled fan heatsink

are shown in Figure 7-2 (Side View), and Figure 7-3 (Top View). The airspace requirements for the

boxed processor fan heatsink must also be incorporated into new baseboard and system designs.

Airspace requirements are shown in Figure 7-7 and Figure 7-8. Note that some figures have

centerlines shown (marked with alphabetic designations) to clarify relative dimensioning.

Figure 7-2. Space Requirements for the Boxed Processor (Side View)

95.0

[3.74]

81.3

[3.2]

10.0

[0.39]

25.0

[0.98]

84

Datasheet

Boxed Processor Specifications

Figure 7-3. Space Requirements for the Boxed Processor (Top View)

95.0

[3.74]

95.0

[3.74]

NOTES:

1. Diagram does not show the attached hardware for the clip design and is provided only as a mechanical

representation.

Figure 7-4. Space Requirements for the Boxed Processor (Overall View)

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85

Boxed Processor Specifications

7.1.2

7.1.3

Boxed Processor Fan Heatsink Weight

The boxed processor fan heatsink will not weigh more than 450 grams. Refer to Chapter 5 and the

®

Intel Pentium 4 Processor on 90 nm Process in the 775-Land LGA Package Thermal Design

Guide for details on the processor weight and heatsink requirements.

Boxed Processor Retention Mechanism and Heatsink

Attach Clip Assembly

The boxed processor thermal solution requires a heatsink attach clip assembly to secure the

processor and fan heatsink in the baseboard socket. The boxed processor will ship with the heatsink

attach clip assembly.

7.2

Electrical Requirements

7.2.1

Fan Heatsink Power Supply

The boxed processor's fan heatsink requires a +12 V power supply. A fan power cable will be

shipped with the boxed processor to draw power from a power header on the baseboard. The power

cable connector and pinout are shown in Figure 7-5. Baseboards must provide a matched power

header to support the boxed processor. Table 7-1 contains specifications for the input and output

signals at the fan heatsink connector.

The fan heatsink outputs a SENSE signal that is an open- collector output that pulses at a rate of

2 pulses per fan revolution. A baseboard pull-up resistor provides V to match the system board-

OH

mounted fan speed monitor requirements, if applicable. Use of the SENSE signal is optional. If the

SENSE signal is not used, pin 3 of the connector should be tied to GND.

th

The fan heatsink receives a PWM signal from the motherboard from the 4 pin of the connector

labeled as CONTROL.

Note: The boxed processor’s fan heatsink requires a constant +12 V supplied to pin 2 and does not

support variable voltage control or 3-pin PWM control.

The power header on the baseboard must be positioned to allow the fan heatsink power cable to

reach it. The power header identification and location should be documented in the platform user’s

manual, or on the system board itself. Figure 7-6 shows the location of the fan power connector

relative to the processor socket. The baseboard power header should be positioned within

4.33 inches from the center of the processor socket.

86

Datasheet

Boxed Processor Specifications

Figure 7-5. Boxed Processor Fan Heatsink Power Cable Connector Description

Signal

Straight square pin, 4-pin terminal housing with

polarizing ribs and friction locking ramp.

1

2

3

4

GND

+12 V

0.100" pitch, 0.025" square pin width.

SENSE

CONTROL

Match with straight pin, friction lock header on

mainboard.

3 4

1 2

Table 7-1. Fan Heatsink Power and Signal Specifications

Description

Min

Typ

Max

Unit

Notes

+12V: 12 volt fan power supply

10.2

12

13.8

V

IC:

Peak Fan current draw

Fan start-up current draw

Fan start-up current draw maximum duration

—

1.1

—

1.5

2.2

1.0

A

—

Second

pulses per

fan revolution

1

SENSE: SENSE frequency

—

2

—

2,3

CONTROL

2100

2500

2800

Hz

NOTES:

1.

2.

3.

Baseboard should pull this pin up to 5 V with a resistor.

Open Drain Type, Pulse Width Modulated.

Fan will have a pull-up resistor to 4.75 V (maximum 5.25 V).

Figure 7-6. Baseboard Power Header Placement Relative to Processor Socket

R110

[4.33]

B

C

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87

Boxed Processor Specifications

7.3

Thermal Specifications

This section describes the cooling requirements of the fan heatsink solution used by the boxed

processor.

7.3.1

Boxed Processor Cooling Requirements

The boxed processor may be directly cooled with a fan heatsink. However, meeting the processor's

temperature specification is also a function of the thermal design of the entire system, and

ultimately the responsibility of the system integrator. For the processor temperature specification,

refer to Chapter 5. The boxed processor fan heatsink is able to keep the processor temperature

within the specifications listed in Table 5-1 for chassis that provide good thermal management. For

the boxed processor fan heatsink to operate properly, it is critical that the airflow provided to the

fan heatsink is unimpeded. Airflow of the fan heatsink is into the center and out of the sides of the

fan heatsink. Airspace is required around the fan to ensure that the airflow through the fan heatsink

is not blocked. Blocking the airflow to the fan heatsink reduces the cooling efficiency and

decreases fan life. Figure 7-7 and Figure 7-8 illustrate an acceptable airspace clearance for the fan

heatsink. The air temperature entering the fan should be kept below 38 °C. Again, meeting the

processor's temperature specification is the responsibility of the system integrator.

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Boxed Processor Specifications

Figure 7-7. Boxed Processor Fan Heatsink Airspace Keep-out Requirements (Top View)

Figure 7-8. Boxed Processor Fan Heatsink Airspace Keep-out Requirements (Side View)

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89

Boxed Processor Specifications

7.3.2

Variable Speed Fan

If the boxed processor fan heatsink 4-pin connector is connected to a 3-pin motherboard header, it

will operate as follows:

The boxed processor fan will operate at different speeds over a short range of internal chassis

temperatures. This allows the processor fan to operate at a lower speed and noise level, while

internal chassis temperatures are low. If internal chassis temperature increases beyond a lower

set point, the fan speed will rise linearly with the internal temperature until the higher set point

is reached. At that point, the fan speed is at its maximum. As fan speed increases, so does fan

noise levels. Systems should be designed to provide adequate air around the boxed processor

fan heatsink that remains cooler than the lower set point. These set points, represented in

Figure 7-9 and Table 7-2, can vary by a few degrees from fan heatsink to fan heatsink. The

internal chassis temperature should be kept below 38 ºC. Meeting the processor’s temperature

specification (see Chapter 5) is the responsibility of the system integrator.

Note: The motherboard must supply a constant +12 V to the processor’s power header to ensure proper

operation of the variable speed fan for the boxed processor (refer to Table 7-1) for the specific

requirements.

Figure 7-9. Boxed Processor Fan Heatsink Set Points

Higher Set Point

Highest Noise Level

Increasing Fan

Speed & Noise

Lower Set Point

Lowest Noise Level

X

Y

Z

Internal Chassis Temperature (Degrees C)

90

Datasheet

Boxed Processor Specifications

Table 7-2. Boxed Processor Fan Heatsink Set Points

Boxed Processor

Fan Heatsink Set

Point (ºC)

Boxed Processor Fan Speed

Notes

When the internal chassis temperature is below or equal to this set

point, the fan operates at its lowest speed. Recommended maximum

internal chassis temperature for nominal operating environment.

1

X ≤ 30

When the internal chassis temperature is at this point, the fan operates

between its lowest and highest speeds. Recommended maximum

internal chassis temperature for worst-case operating environment.

Y = 34

When the internal chassis temperature is above or equal to this set

point, the fan operates at its highest speed.

1

Z ≥ 38

NOTES:

1.

Set point variance is approximately ±1°C from fan heatsink to fan heatsink.

If the boxed processor fan heatsink 4-pin connector is connected to a 4-pin motherboard header and

the motherboard is designed with a fan speed controller with PWM output (see CONTROL in

Table 7-1) and remote thermal diode measurement capability, the boxed processor will operate as

follows:

As processor power has increased the required thermal solutions have generated increasingly more

noise. Intel has added an option to the boxed processor that allows system integrators to have a

quieter system in the most common usage.

th

The 4 wire PWM solution provides better control over chassis acoustics. This is achieved by

more accurate measurement of processor die temperature through the processor’s temperature

diode (T

). Fan RPM is modulated through the use of an ASIC located on the motherboard

DIODE

th

that sends out a PWM control signal to the 4 pin of the connector labeled as CONTROL. The fan

speed is based on actual processor temperature instead of internal ambient chassis temperatures.

If the new 4-pin active fan heat sink solution is connected to an older 3-pin baseboard, processor

fan header, it will default back to a thermistor controlled mode, allowing compatibility with

existing 3-pin baseboard designs. Under thermistor controlled mode, the fan RPM is automatically

varied based on the inlet temperature measured by a thermistor located at the fan inlet.

Note: For more details on specific motherboard requirements for 4-wire based fan speed control, see the

®

Intel Pentium 4 Processor on 90 nm Process in the 775-Land LGA Package Thermal Design

Guide.

§

Datasheet

91

Boxed Processor Specifications

92

Datasheet

Debug Tools Specifications

8 Debug Tools Specifications

Refer to the ITP700 Debug Port Design Guide for information regarding debug tools

specifications. The ITP700 Debug Port Design Guide is located on http://developer.intel.com.

8.1

Logic Analyzer Interface (LAI)

Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use

in debugging Celeron D processor in the 775-land package systems. Tektronix* and Agilent*

should be contacted to get specific information about their logic analyzer interfaces. The following

information is general in nature. Specific information must be obtained from the logic analyzer

vendor.

Due to the complexity of Celeron D processor in the 775-land package systems, the LAI is critical

in providing the ability to probe and capture FSB signals. There are two sets of considerations to

keep in mind when designing a Celeron D processor in the 775-land package system that can make

use of an LAI: mechanical and electrical.

8.1.1

Mechanical Considerations

The LAI is installed between the processor socket and the Celeron D processor in the 775-land

package. The LAI lands plug into the socket, while the Celeron D processor in the 775-land

package lands plug into a socket on the LAI. Cabling that is part of the LAI egresses the system to

allow an electrical connection between the Celeron D processor in the 775-land package and a

logic analyzer. The maximum volume occupied by the LAI, known as the keep-out volume, as well

as the cable egress restrictions, should be obtained from the logic analyzer vendor. System

designers must make sure that the keep-out volume remains unobstructed inside the system. Note

that it is possible that the keep-out volume reserved for the LAI may differ from the space normally

occupied by the Celeron D processor in the 775-land package heatsink. If this is the case, the logic

analyzer vendor will provide a cooling solution as part of the LAI.

8.1.2

Electrical Considerations

The LAI will also affect the electrical performance of the FSB; therefore, it is critical to obtain

electrical load models from each of the logic analyzers to be able to run system level simulations to

prove that their tool will work in the system. Contact the logic analyzer vendor for electrical

specifications and load models for the LAI solution they provide.

§

Datasheet

93

Debug Tools Specifications

94

Datasheet


型号：	BX80547RE2667C/SL7VS
厂家：	INTEL
描述：	RISC Microprocessor, 32-Bit, 2660MHz, CMOS, PBGA775 外围集成电路
文件：	总94页 (文件大小：2796K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BX80547RE2667C/SL7VS [INTEL]

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