AV80577UG0091M/SLGSB

Intel® Celeron® Mobile Processor

Dual-Core on 45-nm Process

Datasheet

For Platforms Based on Mobile Intel® 4 Series Express Chipset Family

September 2009

Document Number: 321111-003

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2

Datasheet

Contents

1

Introduction..............................................................................................................7

1.1

1.2

Terminology .......................................................................................................8

References .........................................................................................................9

2

Low Power Features................................................................................................ 11

2.1

Clock Control and Low Power States .................................................................... 11

2.1.1 Core Low-Power States ........................................................................... 12

2.1.2 Package Low-Power States ...................................................................... 13

Low-Power FSB Features.................................................................................... 15

Processor Power Status Indicator (PSI#) Signal..................................................... 15

2.2

2.3

3

Electrical Specifications........................................................................................... 17

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

Power and Ground Pins ...................................................................................... 17

FSB Clock (BCLK[1:0]) and Processor Clocking...................................................... 17

Voltage Identification......................................................................................... 17

Catastrophic Thermal Protection.......................................................................... 20

Reserved and Unused Pins.................................................................................. 20

FSB Frequency Select Signals (BSEL[2:0])............................................................ 21

FSB Signal Groups............................................................................................. 21

CMOS Signals ................................................................................................... 23

Maximum Ratings.............................................................................................. 23

3.10 Processor DC Specifications ................................................................................ 24

4

5

Package Mechanical Specifications and Pin Information.......................................... 29

4.1

4.2

4.3

Package Mechanical Specifications....................................................................... 29

Processor Pinout and Pin List .............................................................................. 33

Alphabetical Signals Reference............................................................................ 53

Thermal Specifications and Design Considerations .................................................. 61

5.1

Monitoring Die Temperature ............................................................................... 61

5.1.1 Thermal Diode ....................................................................................... 62

5.1.2 Thermal Diode Offset.............................................................................. 64

5.1.3 Intel® Thermal Monitor........................................................................... 65

5.1.4 Digital Thermal Sensor............................................................................ 66

5.1.5 Out of Specification Detection .................................................................. 67

5.1.6 PROCHOT# Signal Pin............................................................................. 67

Datasheet

3

Figures

1

2

3

4

5

6

Package-Level Low-Power States................................................................................11

Core Low-Power States .............................................................................................12

4-MB and Fused 2-MB Micro-FCPGA Processor Package Drawing (Sheet 1 of 2).................30

4-MB and Fused 2-MB Micro-FCPGA Processor Package Drawing (Sheet 2 of 2).................31

2-MB Micro-FCPGA Processor Package Drawing (Sheet 1 of 2) ........................................32

2-MB Micro-FCPGA Processor Package Drawing (Sheet 2 of 2) ........................................33

Tables

1

2

3

4

5

6

7

8

9

Coordination of Core-Level Low-Power States at the Package Level .................................11

Voltage Identification Definition..................................................................................17

BSEL[2:0] Encoding for BCLK Frequency......................................................................21

FSB Pin Groups ........................................................................................................22

Processor Absolute Maximum Ratings..........................................................................23

DC Voltage and Current Specifications.........................................................................25

FSB Differential BCLK Specifications............................................................................26

AGTL+ Signal Group DC Specifications ........................................................................27

CMOS Signal Group DC Specifications..........................................................................28

10 Open Drain Signal Group DC Specifications ..................................................................28

11 The Coordinates of the Processor Pins as Viewed from the Top of the Package

(Sheet 1 of 2)..........................................................................................................34

12 The Coordinates of the Processor Pins as Viewed from the Top of the Package

(Sheet 2 of 2)..........................................................................................................35

13 Pin Listing by Pin Name.............................................................................................37

14 Pin Listing by Pin Number..........................................................................................44

15 Signal Description.....................................................................................................53

16 Power Specifications for the Intel Celeron Dual-Core Processor - Standard Voltage............61

17 Thermal Diode Interface............................................................................................62

18 Thermal Diode Parameters Using Diode Model..............................................................63

19 Thermal Diode Parameters Using Transistor Model ........................................................64

20 Thermal Diode ntrim and Diode Correction Toffset ........................................................65

4

Datasheet

Revision History

Document

Number

Revision

Number

Description

Date

321111

-001

-002

• Initial Release

November 2008

June 2009

• Added T3000, T3100, T3300, and T3500 processors

• Added specifications for SFF processor SU2300

• Added C4 state support information for SU2300 SFF

processor

• Added Speedstep technology suppport information for

SU2300 SFF processor

• details:

• Chapter 1: updated feature list for SFF processor

• Section 2.1: added C4/deeper sleep state information

• Figure 1: updated C4/deeper sleep state information

• Figure 2: updated C4/deeper sleep state information

• Table 1: Added C4/deeper sleep state information

321111

-003

September 2009

• Section Section 2.1.1.6, Section 2.1.2.6: Added C4/deeper

sleep state information

• Section 2.2: Added information on Intel speedstep

technology description

• Table 8: added table for SU2300 processor DC specifications

• Table 25: added table for SU2300 thermal specifications

• Figure 7, Table 19, Table 20, Table 17, Table 23 added

SU2300 pin and package information

§

Datasheet

5

6

Datasheet

Introduction

1 Introduction

This document provides electrical, mechanical, and thermal specifications for the

Intel® Celeron® Mobile Processor Dual-Core T1x00, Intel(R) Celeron Processors T3x00

and Intel(R) Celeron Dual-core SFF Processors. The processor supports the Mobile

Intel® 4 Series Express Chipset and Intel® 82801IBM (ICH9M) Controller-Hub Based

Systems.

Note:

In this document, the Celeron processor is referred to as the processor and Mobile

Intel® 4 Series Express Chipset family is referred to as the (G)MCH.

The following list provides some of the key features on this processor:

• Dual-Core processor for mobile with enhanced performance

• Intel architecture with Intel® Wide Dynamic Execution

• L1 Cache to Cache (C2C) transfer

• On-die, primary 32-KB instruction cache and 32-KB write-back data cache in each

core

• On-die, 1-MB second level shared cache with advanced transfer cache architecture

• Streaming SIMD Extensions 2 (SSE2), Streaming SIMD Extensions 3 (SSE3) and

Supplemental Streaming SIMD Extensions 3 (SSSE3)

• 667-MHz Source-Synchronous Front Side Bus (FSB) for the T1x00 Series, and 800-

MHz Source-Synchronous Front Side Bus (FSB) for the T3x00 Series processors

and SFF processors

• Digital Thermal Sensor (DTS)

• Intel® 64 Technology

• PSI2 functionality

• Execute Disable Bit support for enhanced security

• Half ratio support (N/2) for Core to Bus ratio

• Supports enhanced Intel® Virtualization Technology (SFF processor only)

• Intel® Deeper Sleep low-power state with P_LVL4 I/O Support (SFF processor

only)

• Advanced power management feature includes Enhanced Intel SpeedStep®

Technology (SFF processor only)

Datasheet

7

Introduction

1.1

Terminology

Term

Definition

A “#” symbol after a signal name refers to an active low signal, indicating a

signal is in the active state when driven to a low level. For example, when

RESET# is low, a reset has been requested. Conversely, when NMI is high,

a nonmaskable interrupt has occurred. In the case of signals where the

name does not imply an active state but describes part of a binary

sequence (such as address or data), the “#” symbol implies that the signal

is inverted. For example, D[3:0] = “HLHL” refers to a hex ‘A’, and D[3:0]#

= “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level).

XXXX means that the specification or value is yet to be determined.

#

Front Side Bus

(FSB)

Refers to the interface between the processor and system core logic (also

known as the chipset components).

Advanced Gunning Transceiver Logic. Used to refer to Assisted GTL+

signaling technology on some Intel processors.

AGTL+

Refers to a non-operational state. The processor may be installed in a

platform, in a tray, or loose. Processors may be sealed in packaging or

exposed to free air. Under these conditions, processor landings should not

be connected to any supply voltages, have any I/Os biased or receive any

clocks. Upon exposure to “free air” (i.e., unsealed packaging or a device

removed from packaging material) the processor must be handled in

accordance with moisture sensitivity labeling (MSL) as indicated on the

packaging material.

Storage

Conditions

Enhanced Intel

SpeedStep®

Technology

Technology that provides power management capabilities to laptops.

Processor core die with integrated L1 and L2 cache. All AC timing and

signal integrity specifications are at the pads of the processor core.

Processor Core

Intel® 64

Technology

64-bit memory extensions to the IA-32 architecture.

Intel®

Virtualization

Technology

Processor virtualization which when used in conjunction with Virtual

Machine Monitor software enables multiple, robust independent software

environments inside a single platform.

TDP

V_CC

V_SS

Thermal Design Power

The processor core power supply

The processor ground

8

Datasheet

Introduction

1.2

References

Material and concepts available in the following documents may be beneficial when

reading this document.

Document

Document Number

See http://

www.intel.com/design/

mobile/specupdt/

319734.htm

Intel® Celeron® Dual-Core T1x00 Processors Specification Update

for Platforms Based on Mobile Intel® 4 Series Express Chipset Family

Mobile Intel® 4 Series Express Chipset Family Datasheet

355969

320123

Mobile Intel® 4 Series Express Chipset Family Specification Update

See http://

www.intel.com/Assets/

PDF/datasheet/

316972.pdf

Intel® I/O Controller Hub 9(ICH9)/ I/O Controller Hub 9M (ICH9M)

Datasheet

See http://

www.intel.com/Assets/

PDF/specupdate/

316973.pdf

Intel® I/O Controller Hub 8 (ICH8)/ I/O Controller Hub 8M (ICH8M)

Specification Update

See http://

www.intel.com/design/

pentium4/manuals/

index_new.htm

Intel® 64 and IA-32 Architectures Software Developer’s Manual

See http://

Intel® 64 and IA-32 Architectures Software Developer's Manuals

Documentation Change

developer.intel.com/

design/processor/

specupdt/252046.htm

Volume 1: Basic Architecture

253665

253666

253667

253668

253669

Volume 2A: Instruction Set Reference, A-M

Volume 2B: Instruction Set Reference, N-Z

Volume 3A: System Programming Guide

Volume 3B: System Programming Guide

Datasheet

9

Introduction

10

Datasheet

Low Power Features

2 Low Power Features

2.1

Clock Control and Low Power States

The processor supports the C1/AutoHALT, C1/MWAIT, C2, C3 and some support the C4

core low-power states, along with their corresponding package-level states for power

management. See Chapter 3 to see if C4 is supported. These package states include

Normal, Stop Grant, Stop Grant Snoop, Sleep, and Deep Sleep. The processor’s central

power management logic enters a package low-power state by initiating a P_LVLx

(P_LVL2, P_LVL3, P_LVL4) I/O read to the (G)MCH. Figure 1 shows the package-level

low-power states and Figure 2 shows the core low-power states. Refer to Table 1 for a

mapping of core low-power states to package low-power states.

The processor implements two software interfaces for requesting low-power states:

MWAIT instruction extensions with sub-state hints and P_LVLx reads to the ACPI P_BLK

register block mapped in the processor’s I/O address space. The P_LVLx I/O reads are

converted to equivalent MWAIT C-state requests inside the processor and do not

directly result in I/O reads on the processor FSB. The monitor address does not need to

be setup before using the P_LVLx I/O read interface. The sub-state hints used for each

P_LVLx read can be configured through the IA32_MISC_ENABLES Model Specific

Register (MSR).

If the processor encounters a chipset break event while STPCLK# is asserted, it asserts

the PBE# output signal. Assertion of PBE# when STPCLK# is asserted indicates to

system logic that the processor should return to the Normal state.

Table 1.

Coordination of Core-Level Low-Power States at the Package Level

Core States

Package States

C0

C1⁽¹⁾

C2

Normal

Stop Grant

Deep Sleep

Deeper Sleep

C3

C4

NOTE: AutoHALT or MWAIT/C1

Figure 1.

Package-Level Low-Power States

SLP# asserted

DPSLP# asserted

DPRSTP# asserted

STPCLK# asserted

Stop

Grant

Deep

Sleep

Deeper

Sleep^†

Normal

Sleep

STPCLK# deasserted

SLP# deasserted

DPSLP# deasserted

DPRSTP# deasserted

Snoop Snoop

serviced occurs

Stop Grant

Snoop

† — Deeper Sleep includes the Deeper Sleep state and Deep C4 sub-state

Datasheet

11

Low Power Features

Figure 2.

Core Low-Power States

Stop

Grant

STPCLK#

asserted

STPCLK#

deasserted

STPCLK#

deasserted

STPCLK#

asserted

STPCLK#

deasserted

STPCLK#

asserted

C1/Auto

Halt

C1/MWAIT

Core state

break

HLT instruction

MWAIT(C1)

Halt break

C0

P_LVL2 or

MWAIT(C2)

Core State

break

Core state

break

P_LVL3 or

C2^†

P_LVL4

MWAIT(C4)

Core

state

MWAIT(C3)

C4^{† ‡}

break

C3^†

break = A20M# transition, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt

e state break = (halt break OR Monitor event) AND STPCLK# high (not asserted)

STPCLK# assertion and de-assertion have no effect if a core is in C2, C3, or C4.

Core C4 state supports the package level Deep C4 sub-state.

2.1.1

Core Low-Power States

2.1.1.1

C0 State

This is the normal operating state of the processor.

2.1.1.2

C1/AutoHALT Powerdown State

C1/AutoHALT is a low-power state entered when the processor core executes the HALT

instruction. The processor core transitions to the C0 state upon the occurrence of

SMI#, INIT#, LINT[1:0] (NMI, INTR), or FSB interrupt message. RESET# causes the

processor to immediately initialize itself.

A System Management Interrupt (SMI) A System Management Interrupt (SMI) handler

returns execution to either Normal state or the C1/AutoHALT Powerdown state. See the

Intel® 64 and IA-32 Intel® Architecture Software Developer's Manual, Volume 3A/3B:

System Programmer's Guide for more information.

The system can generate a STPCLK# while the processor is in the C1/AutoHALT

Powerdown state. When the system deasserts the STPCLK# interrupt, the processor

returns execution to the HALT state.

The processor in C1/AutoHALT powerdown state process only the bus snoops. The

processor enters a snoopable sub-state (not shown in Figure 2) to process the snoop

and then return to the C1/AutoHALT Powerdown state.

12

Datasheet

Low Power Features

2.1.1.3

2.1.1.4

C1/MWAIT Powerdown State

C1/MWAIT is a low-power state entered when the processor core executes the MWAIT

instruction. Processor behavior in the C1/MWAIT state is identical to the C1/AutoHALT

state except that there is an additional event that can cause the processor core to

return to the C0 state: the Monitor event. See the Intel® 64 and IA-32 Intel®

Architecture Software Developer's Manual, Volume 2A/2B: Instruction Set Reference

for more information.

Core C2 State

The core of the processor can enter the C2 state by initiating a P_LVL2 I/O read to the

P_BLK or an MWAIT(C2) instruction, but the processor does not issue a Stop Grant

Acknowledge special bus cycle unless the STPCLK# pin is also asserted.

The processor in C2 state processes only the bus snoops. The processor enters a

snoopable sub-state (not shown in Figure 2) to process the snoop and then return to

the C2 state.

2.1.1.5

Core C3 State

Core C3 state is a very low-power state the processor core can enter while maintaining

context. The core of the processor can enter the C3 state by initiating a P_LVL3 I/O

read to the P_BLK or an MWAIT(C3) instruction. Before entering the C3 state, the

processor core flushes the contents of its L1 cache into the processor’s L2 cache.

Except for the caches, the processor core maintains all its architectural state in the C3

state. The Monitor remains armed if it is configured. All of the clocks in the processor

core are stopped in the C3 state.

Because the core’s caches are flushed, the processor keeps the core in the C3 state

when the processor detects a snoop on the FSB. The processor core transitions to the

C0 state upon the occurrence of a Monitor event, SMI#, INIT#, LINT[1:0] (NMI, INTR),

or FSB interrupt message. RESET# causes the processor core to immediately initialize

itself.

2.1.1.6

Core C4 State

Individual cores of the dual-core processor that have C4 can enter the C4 state by

initiating a P_LVL4 I/O read to the P_BLK or an MWAIT(C4) instruction. The processor

core behavior in the C4 state is nearly identical to the behavior in the C3 state. The

only difference is that if both processor cores are in C4, the central power management

logic will request that the entire processor enter the Deeper Sleep package low-power

state (see Section 2.1.2.6)

2.1.2

Package Low-Power States

Package level low-power states are applicable to the processor.

2.1.2.1

Normal State

This is the normal operating state for the processor. The processor enters the Normal

state when the core is in the C0, C1/AutoHALT, or C1/MWAIT state.

2.1.2.2

Stop-Grant State

When the STPCLK# pin is asserted the core of the processor enters the Stop-Grant

state within 20 bus clocks after the response phase of the processor-issued Stop Grant

Acknowledge special bus cycle. When the STPCLK# pin is deasserted the core returns

to the previous core low-power state.

Datasheet

13

Low Power Features

Since the AGTL+ signal pins receive power from the FSB, these pins should not be

driven (allowing the level to return to V_CCP) for minimum power drawn by the

termination resistors in this state. In addition, all other input pins on the FSB should be

driven to the inactive state.

RESET# causes the processor to immediately initialize itself, but the processor stays in

Stop-Grant state. When RESET# is asserted by the system the STPCLK#, SLP#, and

DPSLP# pins must be deasserted more than 480 µs prior to RESET# deassertion (AC

Specification T45). When re-entering the Stop-Grant state from the Sleep state,

STPCLK# should be deasserted ten or more bus clocks after the deassertion of SLP#

(AC Specification T75).

While in the Stop-Grant state, the processor services snoops and latch interrupts

delivered on the FSB. The processor latches SMI#, INIT# and LINT[1:0] interrupts and

services only upon return to the Normal state.

The PBE# signal may be driven when the processor is in Stop-Grant state. PBE# is

asserted if there is any pending interrupt or monitor event latched within the processor.

Pending interrupts that are blocked by the EFLAGS.IF bit being clear still cause

assertion of PBE#. Assertion of PBE# indicates to system logic that the processor

should return to the Normal state.

A transition to the Stop Grant Snoop state occurs when the processor detects a snoop

on the FSB (see Section 2.1.2.3). A transition to the Sleep state (see Section 2.1.2.4)

occurs with the assertion of the SLP# signal.

2.1.2.3

2.1.2.4

Stop Grant Snoop State

The processor responds to snoop or interrupt transactions on the FSB while in Stop-

Grant state by entering the Stop-Grant Snoop state. The processor stays in this state

until the snoop on the FSB has been serviced (whether by the processor or another

agent on the FSB) or the interrupt has been latched. The processor returns to the Stop-

Grant state once the snoop has been serviced or the interrupt has been latched.

Sleep State

The Sleep state is a low-power state in which the processor maintains its context,

maintains the phase-locked loop (PLL), and stops all internal clocks. The Sleep state is

entered through assertion of the SLP# signal while in the Stop-Grant state. The SLP#

pin should only be asserted when the processor is in the Stop-Grant state. SLP#

assertions while the processor is not in the Stop-Grant state is out of specification and

may result in unapproved operation.

In the Sleep state, the processor is incapable of responding to snoop transactions or

latching interrupt signals. No transitions or assertions of signals (with the exception of

SLP#, DPSLP# or RESET#) are allowed on the FSB while the processor is in Sleep

state. Snoop events that occur while in Sleep state or during a transition into or out of

Sleep state causes unpredictable behavior. Any transition on an input signal before the

processor has returned to the Stop-Grant state results in unpredictable behavior.

If RESET# is driven active while the processor is in the Sleep state, and held active as

specified in the RESET# pin specification, then the processor resets itself, ignoring the

transition through Stop-Grant state. If RESET# is driven active while the processor is in

the Sleep state, the SLP# and STPCLK# signals should be deasserted immediately after

RESET# is asserted to ensure the processor correctly executes the Reset sequence.

While in the Sleep state, the processor is capable of entering an even lower power

state, the Deep Sleep state, by asserting the DPSLP# pin. (See Section 2.1.2.5.) While

the processor is in the Sleep state, the SLP# pin must be deasserted if another

asynchronous FSB event needs to occur.

14

Datasheet

Low Power Features

2.1.2.5

Deep Sleep State

Deep Sleep state is a very low-power state the processor can enter while maintaining

context. Deep Sleep state is entered by asserting the DPSLP# pin while in the Sleep

state. BCLK may be stopped during the Deep Sleep state for additional platform level

power savings. BCLK stop/restart timings on appropriate chipset based platforms with

the CK505 clock chip are as follows:

• Deep Sleep entry: the system clock chip may stop/tristate BCLK within 2 BCLKs of

DPSLP# assertion. It is permissible to leave BCLK running during Deep Sleep.

• Deep Sleep exit: the system clock chip must drive BCLK to differential DC levels

within 2-3 ns of DPSLP# deassertion and start toggling BCLK within 10 BCLK

periods.

To re-enter the Sleep state, the DPSLP# pin must be deasserted. BCLK can be re-

started after DPSLP# deassertion as described above. A period of 15 microseconds (to

allow for PLL stabilization) must occur before the processor can be considered to be in

the Sleep state. Once in the Sleep state, the SLP# pin must be deasserted to re-enter

the Stop-Grant state.

While in Deep Sleep state, the processor is incapable of responding to snoop

transactions or latching interrupt signals. No transitions of signals are allowed on the

FSB while the processor is in Deep Sleep state. Any transition on an input signal before

the processor has returned to Stop-Grant state results in unpredictable behavior.

2.1.2.6

Deeper Sleep State

The Deeper Sleep state is similar to the Deep Sleep state but further reduces core

voltage levels. One of the potential lower core voltage levels is achieved by entering the

base Deeper Sleep state. The Deeper Sleep state is entered through assertion of the

DPRSTP# pin while in the Deep Sleep state. The following lower core voltage level is

achieved by entering the Intel Enhanced Deeper Sleep state which is a sub-state of

Deeper Sleep state. Intel Enhanced Deeper Sleep state is entered through assertion of

the DPRSTP# pin while in the Deep Sleep only when the L2 cache has been completely

shut down.

Exit from Deeper Sleep is initiated by DPRSTP# deassertion when either core requests

a core state other than C4 or either core requests a processor performance state other

than the lowest operating point.

2.2

Enhanced Intel SpeedStep® Technology

Some processors feature Enhanced Intel SpeedStep Technology. See each processor’s

DCL to see if it supports Enhanced Intel SpeedStep Technology. Following are the key

features of Enhanced Intel SpeedStep Technology:

• Multiple voltage and frequency operating points provide optimal performance at the

lowest power.

• Voltage and frequency selection is software-controlled by writing to processor

MSRs:

— If the target frequency is higher than the current frequency, V_CCis ramped up

in steps by placing new values on the VID pins, and the PLL then locks to the

new frequency.

— If the target frequency is lower than the current frequency, the PLL locks to the

new frequency and the V_CCis changed through the VID pin mechanism.

— Software transitions are accepted at any time. If a previous transition is in

progress, the new transition is deferred until the previous transition completes.

Datasheet

15

Low Power Features

• The processor controls voltage ramp rates internally to ensure glitch-free

transitions.

• Low transition latency and large number of transitions possible per second:

— Processor core (including L2 cache) is unavailable for up to 10 μs during the

frequency transition.

— The bus protocol (BNR# mechanism) is used to block snooping.

• Improved Intel® Thermal Monitor mode:

— When the on-die thermal sensor indicates that the die temperature is too high

the processor can automatically perform a transition to a lower frequency and

voltage specified in a software-programmable MSR.

— The processor waits for a fixed time period. If the die temperature is down to

acceptable levels, an up-transition to the previous frequency and voltage point

occurs.

— An interrupt is generated for the up and down Intel Thermal Monitor transitions

enabling better system-level thermal management.

• Enhanced thermal management features:

— Digital Thermal Sensor and Out of Specification detection.

— Intel Thermal Monitor 1 (TM1) in addition to Intel Thermal Monitor 2 (TM2) in

case of unsuccessful TM2 transition.

— Dual core thermal management synchronization.

Each core in the dual-core processor implements an independent MSR for controlling

Enhanced Intel SpeedStep Technology, but both cores must operate at the same

frequency and voltage. The processor has performance state coordination logic to

resolve frequency and voltage requests from the two cores into a single frequency and

voltage request for the package as a whole. If both cores request the same frequency

and voltage, then the processor will transition to the requested common frequency and

voltage. If the two cores have different frequency and voltage requests, then the

processor will take the highest of the two frequencies and voltages as the resolved

request and transition to that frequency and voltage.

Caution:

Enhanced Intel SpeedStep Technology transitions are multistep processes

that require clocked control. These transitions cannot occur when the processor is in

the Sleep or Deep Sleep package low-power states since processor clocks are not

active in these states.

2.3

Low-Power FSB Features

The processor incorporates FSB low-power enhancements:

• Dynamic On Die Termination disabling

• Low V_CCP(I/O termination voltage)

The On Die Termination on the processor FSB buffers is disabled when the signals are

driven low, resulting in power savings. The low I/O termination voltage is on a

dedicated voltage plane independent of the core voltage, enabling low I/O switching

power at all times.

16

Datasheet

Low Power Features

2.4

Processor Power Status Indicator (PSI#) Signal

The PSI# signal is asserted when the processor is in a reduced power consumption

state. PSI# can be used to improve light load efficiency of the voltage regulator,

resulting in platform power savings and extended battery life. The algorithm that the

processor uses for determining when to assert PSI# is different from the algorithm

used in previous processors.

Datasheet

17

Low Power Features

18

Datasheet

Electrical Specifications

3 Electrical Specifications

3.1

Power and Ground Pins

For clean, on-chip power distribution, the processor has a large number of V_CC(power)

and V_SS(ground) inputs. All power pins must be connected to V_CCpower planes while

all V_SSpins must be connected to system ground planes. Use of multiple power and

ground planes is recommended to reduce I*R drop. The processor V_CCpins must be

supplied the voltage determined by the VID (Voltage ID) pins.

3.2

FSB Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the

processor. As in previous generation processors, the processor core frequency is a

multiple of the BCLK[1:0] frequency. The processor uses a differential clocking

implementation.

3.3

Voltage Identification

The processor uses seven voltage identification pins,VID[6:0], to support automatic

selection of power supply voltages. The VID pins for processor are CMOS outputs

driven by the processor VID circuitry. Table 2 specifies the voltage level corresponding

to the state of VID[6:0]. A 1 refers to a high-voltage level and a 0 refers to low-voltage

level.

Table 2.

Voltage Identification Definition (Sheet 1 of 4)

VID6

VID5

VID4

VID3

VID2

VID1

VID0

V_CC(V)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.5000

1.4875

1.4750

1.4625

1.4500

1.4375

1.4250

1.4125

1.4000

1.3875

1.3750

1.3625

1.3500

1.3375

1.3250

1.3125

1.3000

1.2875

1.2750

1.2625

1.2500

1.2375

Datasheet

19

Electrical Specifications

Table 2.

Voltage Identification Definition (Sheet 2 of 4)

VID6

VID5

VID4

VID3

VID2

VID1

VID0

V_CC(V)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1.2250

1.2125

1.2000

1.1875

1.1750

1.1625

1.1500

1.1375

1.1250

1.1125

1.1000

1.0875

1.0750

1.0625

1.0500

1.0375

1.0250

1.0125

1.0000

0.9875

0.9750

0.9625

0.9500

0.9375

0.9250

0.9125

0.9000

0.8875

0.8750

0.8625

0.8500

0.8375

0.8250

0.8125

0.8000

0.7875

0.7750

0.7625

0.7500

0.7375

0.7250

0.7125

0.7000

0.6875

0.6750

0.6625

0.6500

20

Datasheet

Electrical Specifications

Table 2.

Voltage Identification Definition (Sheet 3 of 4)

VID6

VID5

VID4

VID3

VID2

VID1

VID0

V_CC(V)

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.6375

0.6250

0.6125

0.6000

0.5875

0.5750

0.5625

0.5500

0.5375

0.5250

0.5125

0.5000

0.4875

0.4750

0.4625

0.4500

0.4375

0.4250

0.4125

0.4000

0.3875

0.3750

0.3625

0.3500

0.3375

0.3250

0.3125

0.3000

0.2875

0.2750

0.2625

0.2500

0.2375

0.2250

0.2125

0.2000

0.1875

0.1750

0.1625

0.1500

0.1375

0.1250

0.1125

0.1000

0.0875

0.0750

0.0625

Datasheet

21

Electrical Specifications

Table 2.

Voltage Identification Definition (Sheet 4 of 4)

VID6

VID5

VID4

VID3

VID2

VID1

VID0

V_CC(V)

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.0500

0.0375

0.0250

0.0125

0.0000

3.4

3.5

Catastrophic Thermal Protection

The processor supports the THERMTRIP# signal for catastrophic thermal protection. An

external thermal sensor should also be used to protect the processor and the system

against excessive temperatures. Even with the activation of THERMTRIP#, which halts

all processor internal clocks and activity, leakage current can be high enough that the

processor cannot be protected in all conditions without power removal to the processor.

If the external thermal sensor detects a catastrophic processor temperature of 125 °C

(maximum), or if the THERMTRIP# signal is asserted, the V_CCsupply to the processor

must be turned off within 500 ms to prevent permanent silicon damage due to thermal

runaway of the processor. THERMTRIP# functionality is not guaranteed if the

PWRGOOD signal is not asserted.

Reserved and Unused Pins

All RESERVED (RSVD) pins must remain unconnected. Connection of these pins to V_CC

,

V_SS, or to any other signal (including each other) may result in component malfunction

or incompatibility with future processors. See Section 4.2 for a pin listing of the

processor and the location of all RSVD pins.

For reliable operation, always connect unused inputs or bidirectional signals to an

appropriate signal level. Unused active low AGTL+ inputs may be left as no connects if

AGTL+ termination is provided on the processor silicon. Unused active high inputs

should be connected through a resistor to ground (V_SS). Unused outputs can be left

unconnected.

The TEST1 and TEST2 pins must have a stuffing option of separate pull-down resistors

to V_SS.

For the purpose of testability, route the TEST3 and TEST5 signals through a ground-

referenced Zo = 55-Ω trace that ends in a via that is near a GND via and is accessible

through an oscilloscope connection.

22

Datasheet

Electrical Specifications

3.6

FSB Frequency Select Signals (BSEL[2:0])

The BSEL[2:0] signals are used to select the frequency of the processor input clock

(BCLK[1:0]). These signals should be connected to the clock chip and the appropriate

chipset on the platform. The BSEL encoding for BCLK[1:0] is shown in Table 3.

Table 3.

BSEL[2:0] Encoding for BCLK Frequency

BSEL[2]

BSEL[1] BSEL[0]

BCLK Frequency

L

H

L

RESERVED

133 MHz

L

H

L

RESERVED

200 MHz

L

H

L

RESERVED

H

L

3.7

FSB Signal Groups

The FSB signals have been combined into groups by buffer type in the following

sections. AGTL+ input signals have differential input buffers, which use GTLREF as a

reference level. In this document, the term “AGTL+ Input” refers to the AGTL+ input

group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers

to the AGTL+ output group as well as the AGTL+ I/O group when driving.

With the implementation of a source synchronous data bus, two sets of timing

parameters need to be specified. One set is for common clock signals, which are

dependent upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second

set is for the source synchronous signals, which are relative to their respective strobe

lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are

still present (A20M#, IGNNE#, etc.) and can become active at any time during the

clock cycle. Table 4 identifies which signals are common clock, source synchronous,

and asynchronous.

Datasheet

23

Electrical Specifications

Table 4.

FSB Pin Groups

Signal Group

Type

Signals¹

Synchronous

to BCLK[1:0]

AGTL+ Common Clock Input

AGTL+ Common Clock I/O

BPRI#, DEFER#, PREQ#⁵, RESET#, RS[2:0]#, TRDY#

Synchronous

to BCLK[1:0]

ADS#, BNR#, BPM[3:0]#³, BR0#, DBSY#, DRDY#, HIT#,

HITM#, LOCK#, PRDY#³, DPWR#

Signals

Associated Strobe

REQ[4:0]#,

A[16:3]#

ADSTB[0]#

ADSTB[1]#

A[35:17]#

Synchronous

to assoc.

strobe

D[15:0]#,

DINV0#

DSTBP0#,

DSTBN0#

AGTL+ Source Synchronous

I/O

D[31:16]#,

DINV1#

DSTBP1#,

DSTBN1#

D[47:32]#,

DINV2#

DSTBP2#,

DSTBN2#

D[63:48]#,

DINV3#

DSTBP3#,

DSTBN3#

Synchronous

to BCLK[1:0]

AGTL+ Strobes

CMOS Input

ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#

A20M#, DPRSTP#, DPSLP#, IGNNE#, INIT#, LINT0/INTR,

LINT1/NMI, PWRGOOD, SMI#, SLP#, STPCLK#

Asynchronous

Open Drain Output

Open Drain I/O

CMOS Output

Asynchronous FERR#, IERR#, THERMTRIP#

Asynchronous PROCHOT#⁴

Asynchronous PSI#, VID[6:0], BSEL[2:0]

Synchronous

TCK, TDI, TMS, TRST#

to TCK

CMOS Input

Synchronous

TDO

Open Drain Output

FSB Clock

to TCK

Clock

BCLK[1:0]

COMP[3:0], DBR#², GTLREF, RSVD, TEST2, TEST1, THERMDA,

THERMDC, V_CC, V_CCA, V_CCP,V_{CC_SENSE}, V_SS,V_{SS_SENSE}

Power/Other

NOTES:

1.

2.

Refer to Chapter 4 for signal descriptions and termination requirements.

In processor systems where there is no debug port implemented on the system board, these signals are

used to support a debug port interposer. In systems with the debug port implemented on the system

board, these signals are no connects.

3.

4.

5.

BPM[2:1]# and PRDY# are AGTL+ output only signals.

PROCHOT# signal type is open drain output and CMOS input.

On die termination differs from other AGTL+ signals.

24

Datasheet

Electrical Specifications

3.8

CMOS Signals

CMOS input signals are shown in Table 4. Legacy output FERR#, IERR# and other non-

AGTL+ signals (THERMTRIP# and PROCHOT#) utilize Open Drain output buffers. These

signals do not have setup or hold time specifications in relation to BCLK[1:0]. However,

all of the CMOS signals are required to be asserted for more than four BCLKs in order

for the processor to recognize them. See Section 3.10 for the DC specifications for the

CMOS signal groups.

3.9

Maximum Ratings

Table 5 specifies absolute maximum and minimum ratings. If the processor stays within

functional operation limits, functionality and long-term reliability can be expected.

Caution:

At conditions outside functional operation condition limits, but within absolute

maximum and minimum ratings, neither functionality nor long term reliability can be

expected. At conditions exceeding absolute maximum and minimum ratings, neither

functionality nor long term reliability can be expected.

Caution:

Precautions should always be taken to avoid high-static voltages or electric fields.

Table 5.

Processor Absolute Maximum Ratings

Symbol

Parameter

Min

Max

Unit

Notes¹

Processor storage

temperature

TSTORAGE

-40

85

°C

2, 3, 4

Any processor supply voltage

with respect to V_SS

V_CC

-0.3

-0.1

1.55

V

AGTL+ buffer DC input

voltage with respect to V_SS

V_inAGTL+

V_{inAsynch_CMOS}

NOTES:

CMOS buffer DC input

voltage with respect to V_SS

1.

For functional operation, all processor electrical, signal quality, mechanical and thermal

specifications must be satisfied.

2.

Storage temperature is applicable to storage conditions only. In this scenario, the

processor must not receive a clock, and no lands can be connected to a voltage bias.

Storage within these limits does not affect the long term reliability of the device. For

functional operation, please refer to the processor case temperature specifications.

This rating applies to the processor and does not include any tray or packaging.

Failure to adhere to this specification can affect the long-term reliability of the processor.

3.

4.

Datasheet

25

Electrical Specifications

3.10

Processor DC Specifications

The processor DC specifications in this section are defined at the processor

core (pads) unless noted otherwise. See Table 4 for the pin signal definitions and

signal pin assignments.

Table 7 through Table 10 list the DC specifications for the processor and are valid only

while meeting specifications for junction temperature, clock frequency, and input

voltages. The Highest Frequency Mode (HFM) and Super Low Frequency Mode

(SuperLFM) refer to the highest and lowest core operating frequencies supported on

the processor. Active mode load line specifications apply in all states except in the Deep

Sleep and Deeper Sleep states. V_CC,BOOTis the default voltage driven by the voltage

regulator at power up in order to set the VID values. Unless specified otherwise, all

specifications for the processor are at Tjunction = 100 °C. Care should be taken to read

all notes associated with each parameter.

26

Datasheet

Electrical Specifications

Table 6.

Symbol

DC Voltage and Current Specifications for the T3x00 Celeron Processors

Parameter

Min

Typ

Max

Unit

Notes

V_CC

V_CCof the Processor Core

Default V_CCVoltage for Initial Power Up

AGTL+ Termination Voltage

PLL Supply Voltage

0.8

1.25

V

1, 2

2, 8

V_CC,BOOT

V_CCP

1.20

1.05

1.5

1.00

1.10

V_CCA

1.425

1.575

I_CCfor processors

I_CCDES

47

A

5

Recommended Design Targets:

I_CCfor processors

Processor

I_CC

Frequency

Die Variant

Number

T3000

T3100

1.8 GHz

1.9 GHz

1 MB

47

A

3, 4

I_AH

I_SGNT

I_SLP

,

I_CCAuto-Halt & Stop-Grant

25.4

A

3, 4

I_CCSleep

24.7

22.9

A

3, 4

I_DSLP

I_CCDeep Sleep

V_CCPower Supply Current Slew Rate at

CPU Package Pin

dI_CC/DT

I_CCA

600

130

A/µs

mA

6, 7

I_CCfor V_CCASupply

I_CCfor V_CCPSupply before V_CCStable

I_CCfor V_CCPSupply after V_CCStable

4.5

2.5

A

9

I_CCP

10

NOTES:

1.

Each processor is programmed with a maximum valid voltage identification value (VID), which is set at

manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing

in such a way that two processors at the same frequency may have different settings within the VID range.

Note that this differs from the VID employed by the processor during a power management event (Intel

Thermal Monitor 2, or Extended Halt State).

2.

The voltage specifications are assumed to be measured across V_{CC_SENSE}and V_{SS_SENSE}pins at socket with

a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-mΩ minimum impedance.

The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from

the system is not coupled in the scope probe.

3.

4.

5.

6.

Specified at 105 °C Tj.

Specified at the nominal V_CC

800-MHz FSB supported

Instantaneous current I_{CC_CORE_INST}of 55 A has to be sustained for short time (t_INST) of 10 µs. Average

current is less than maximum specified I_CCDES. VR OCP threshold should be high enough to support current

levels described herein.

.

7.

8.

Measured at the bulk capacitors on the motherboard.

Based on simulations and averaged over the duration of any change in current. Specified by design/

characterization at nominal V_CC. Not 100% tested.

9.

10.

This is a power-up peak current specification, which is applicable when V_CCPis high and V_{CC_CORE}is low.

This is a steady-state I_CCcurrent specification, which is applicable when both V_CCPand V_{CC_CORE}are high.

1-MB L2 cache.

Datasheet

27

Electrical Specifications

Table 7.

Symbol

DC Voltage and Current Specifications for the T1x00 Celeron Mobile

Processors

Parameter

Min

Typ

Max

Unit

Notes

V_CC

V_CCof the Processor Core

Default V_CCVoltage for Initial Power Up

AGTL+ Termination Voltage

PLL Supply Voltage

0.95

1.15

1.20

1.05

1.5

1.30

V

1, 2

2, 8

V_CC,BOOT

V_CCP

1.00

1.10

V_CCA

1.425

1.575

I_CCfor processors

I_CCDES

36

A

5

Recommended Design Targets:

I_CCfor processors

Processor

I_CC

Frequency

Die Variant

Number

T1600

T1700

1.66 GHz

1.83 GHz

1 MB

41

A

3, 4

I_AH

I_SGNT

I_SLP

,

I_CCAuto-Halt & Stop-Grant

I_CCSleep

21

A

3, 4

20.5

18.6

A

3, 4

I_DSLP

I_CCDeep Sleep

V_CCPower Supply Current Slew Rate at

CPU Package Pin

dI_CC/DT

I_CCA

600

130

A/µs

mA

6, 7

I_CCfor V_CCASupply

I_CCfor V_CCPSupply before V_CCStable

I_CCfor V_CCPSupply after V_CCStable

4.5

2.5

A

9

I_CCP

10

NOTES:

1.

Each processor is programmed with a maximum valid voltage identification value (VID), which is set at

manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing

in such a way that two processors at the same frequency may have different settings within the VID range.

Note that this differs from the VID employed by the processor during a power management event (Intel

Thermal Monitor 2, or Extended Halt State).

2.

The voltage specifications are assumed to be measured across V_{CC_SENSE}and V_{SS_SENSE}pins at socket with

a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-mΩ minimum impedance.

The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from

the system is not coupled in the scope probe.

3.

4.

5.

6.

Specified at 100 °C Tj.

Specified at the nominal V_CC

667-MHz FSB supported

Instantaneous current I_{CC_CORE_INST}of 55 A has to be sustained for short time (t_INST) of 10 µs. Average

current is less than maximum specified I_CCDES. VR OCP threshold should be high enough to support current

levels described herein.

.

7.

8.

Measured at the bulk capacitors on the motherboard.

Based on simulations and averaged over the duration of any change in current. Specified by design/

characterization at nominal V_CC. Not 100% tested.

9.

10.

11.

This is a power-up peak current specification, which is applicable when V_CCPis high and V_{CC_CORE}is low.

This is a steady-state I_CCcurrent specification, which is applicable when both V_CCPand V_{CC_CORE}are high.

512-KB L2 cache.

28

Datasheet

Electrical Specifications

Table 8 lists the DC specifications for the processor and are valid only while meeting

specifications for junction temperature, clock frequency, and input voltages. The

Highest Frequency Mode (HFM) and Lowest Frequency Mode (LFM) refer to the highest

and lowest core operating frequencies supported on the Genuine Intel Processor. Unless

specified otherwise, all specifications for the processor are at Tjunction =100 ºC. Care

should be taken to read all notes associated with each parameter.

Table 8.

Voltage and Current Specifications for the Ultra Low Voltage Dual-Core 1M

Cache Intel Celeron SFF Genuine Intel Processor

Symbol

Parameter

V_CCof the Processor Core

Min

Typ

Max

Unit

Notes

V_CC

0.8

1.1

V

1, 2

2, 8

V_CC,BOOT

V_CCP

Default V_CCVoltage for Initial Power Up

—

1.00

1.425

—

1.20

1.05

1.5

—

1.10

1.575

18

V

A

AGTL+ Termination Voltage

V_CCA

PLL Supply Voltage

I_CCDES

I_CCfor Processors Recommended Design Target

5

I_CCfor processors

Processor

I_CC

Frequency

1.2GHz

Die Variant

1MB

Number

SU2300

17.6

A

3, 4

I_AH,

I_CCAuto-Halt & Stop-Grant

I_CCSleep

—

6.3

5.9

I_SGNT

I_SLP

A

3, 4

I_DSLP

I_CCDeep Sleep

5.0

I_DPRSLP

dI_CC/DT

I_CCA

I_CCDeeper Sleep

—

3.2

600

130

A

3, 4

7

V_CCPower Supply Current Slew Rate at

Processor Package Pin

A/µs

mA

I_CCfor V_CCASupply

I_CCfor V_CCPSupply before V_CCStable

I_CCfor V_CCPSupply after V_CCStable

8

9

4.5

2.5

A

I_CCP

NOTES:

1.

Each processor is programmed with a maximum valid voltage identification value (VID), which is set at

manufacturing and can not be altered. Individual maximum VID values are calibrated during

manufacturing such that two processors at the same frequency may have different settings within the VID

range. Note that this differs from the VID employed by the processor during a power management event

(ex: Extended Halt State).

2.

The voltage specifications are assumed to be measured across V_CCSENSEand V_SSSENSEpins at socket with a

100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-mΩ minimum impedance.

The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from

the system is not coupled in the scope probe.

3.

4.

Specified at 100°C Tj.

Specified at nominal V_CC

.

Datasheet

29

Electrical Specifications

5.

6.

7.

800-MHz FSB supported

Measured at the bulk capacitors on the motherboard.

Based on simulations and averaged over the duration of any change in current. Specified by design/

characterization at nominal V_CC. Not 100% tested.

8.

9.

10.

This is a power-up peak current specification, which is applicable when V_CCPis high and V_CCcore is low.

This is a steady-state Icc current specification, which is applicable when both V_CCPand V_CCcore are high.

SU2300 processor operates at same core frequency in HFM and LFM.

Table 9.

FSB Differential BCLK Specifications

Symbol

Parameter

Crossing Voltage

Min

Typ

Max

Unit

Notes¹

V_CROSS

ΔV_CROSS

V_SWING

I_LI

0.3

0.55

140

V

2, 7, 8

Range of Crossing Points

Differential Output Swing

Input Leakage Current

Pad Capacitance

mV

µA

pF

2, 7, 5

300

-5

6

3

4

+5

Cpad

0.95

1.2

1.45

1.

2.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

Crossing Voltage is defined as absolute voltage where rising edge of BCLK0 is equal to the

falling edge of BCLK1.

3.

4.

5.

6.

7.

8.

For Vin between 0 V and V_IH.

Cpad includes die capacitance only. No package parasitics are included.

ΔV_CROSSis defined as the total variation of all crossing voltages as defined in Note 2.

Measurement taken from differential waveform.

Measurement taken from single-ended waveform.

Only applies to the differential rising edge (Clock rising and Clock# falling).

30

Datasheet

Electrical Specifications

Table 10.

AGTL+ Signal Group DC Specifications

Symbol

Parameter

I/O Voltage

Min

Typ

Max

Unit Notes¹

V_CCP

1.00

1.05

2/3 V_CCP

27.5

55

1.10

V

GTLREF Reference Voltage

V

6

10

11

3,6

2,4

6

R_COMP

R_ODT

V_IH

Compensation Resistor

Termination Resistor

Input High Voltage

Input Low Voltage

27.23

27.78

Ω

V

GTLREF+0.10

-0.10

V_CCP

0

V_CCP+0.10

GTLREF-0.10

V_CCP

V_IL

V_OH

R_TT

Output High Voltage

Termination Resistance

V_CCP-0.10

50

V_CCP

55

61

7

Ω

R_ON

I_LI

Buffer On Resistance

Input Leakage Current

Pad Capacitance

22

25

28

5

8

9

Ω

±100

2.55

µA

pF

Cpad

1.6

2.1

NOTES:

1.

2.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

_ILis defined as the maximum voltage level at a receiving agent that is interpreted as a

logical low value.

_IHis defined as the minimum voltage level at a receiving agent that is interpreted as a

logical high value.

_IHand V_OHmay experience excursions above V_CCP. However, input signal drivers must

V

3.

4.

5.

V

comply with the signal quality specifications.

This is the pull-down driver resistance. Measured at 0.31*V_CCP. R_ON(min) = 0.4*R_TT, R_ON

(typ) = 0.455*R_TT, R_ON(max) = 0.51*R_TT. R_TTtypical value of 55 Ω is used for R_ONtyp/

min/max calculations.

6.

7.

GTLREF should be generated from V_CCPwith a 1%-tolerance resistor divider. The V_CCP

referred to in these specifications is the instantaneous V_CCP

_TTis the on-die termination resistance measured at V_OLof the AGTL+ output driver.

Measured at 0.31*V_CCP. R_TTis connected to V_CCPon die.

Specified with on die R_TTand R_ONturned off. Vin between 0 and V_CCP

.

R

8.

.

9.

10.

11.

Cpad includes die capacitance only. No package parasitics are included.

This is the external resistor on the comp pins.

On die termination resistance measured at 0.33*V_CCP

.

Datasheet

31

Electrical Specifications

Table 11.

CMOS Signal Group DC Specifications

Symbol

Parameter

I/O Voltage

Min

Typ

Max

Unit Notes¹

V_CCP

V_IH

1.00

1.05

V_CCP

1.10

V

Input High Voltage

0.7*V_CCP

V_CCP+0.1

V

2

Input Low Voltage

CMOS

V_IL

-0.10

0.00

0.3*V_CCP

V_OH

V_OL

Output High Voltage

Output Low Voltage

Output High Current

Output Low Current

Input Leakage Current

Pad Capacitance

0.9*V_CCP

-0.10

1.5

V_CCP

0

V_CCP+0.1

0.1*V_CCP

4.1

V

2

5

4

6

7

V

I_OH

mA

µA

pF

I_OL

1.5

4.1

I_LI

±100

2.55

Cpad1

1.6

2.1

1.2

Pad Capacitance for

CMOS Input

Cpad2

0.95

1.45

3

NOTES:

1.

2.

3.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

The V_CCPreferred to in these specifications refers to instantaneous V_CCP

Cpad2 includes die capacitance for all other CMOS input signals. No package parasitics are

included.

.

4.

5.

6.

7.

Measured at 0.1*V_CCP

.

Measured at 0.9*V_CCP

.

For Vin between 0 V and V_CCP. Measured when the driver is tristated.

Cpad1 includes die capacitance only for DPRSTP#, DPSLP#, PWRGOOD. No package

parasitics are included.

Table 12.

Open Drain Signal Group DC Specifications

Symbol

Parameter

Min

Typ

Max

Unit Notes¹

V_OH

V_OL

I_OL

Output High Voltage

Output Low Voltage

Output Low Current

Output Leakage Current

Pad Capacitance

V_CCP-5%

V_CCP

V_CCP+5%

0.20

V

3

0

16

50

mA

µA

pF

2

4

5

I_LO

±200

2.45

Cpad

1.9

2.2

NOTES:

1.

2.

3.

4.

5.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

Measured at 0.2 V.

V

_OHis determined by value of the external pull-up resistor to V_CCP

.

For Vin between 0 V and V_OH

.

Cpad includes die capacitance only. No package parasitics are included.

§

32

Datasheet

Package Mechanical Specifications and Pin Information

4 Package Mechanical

Specifications and Pin

Information

4.1

Package Mechanical Specifications

The processor is available in a 1-MB, 478-pin Micro-FCPGA package. The package

mechanical dimensions, keep-out zones, processor mass specifications, and package

loading specifications are shown in Figure 3 through Figure 6.

The SFF processor (ULV DC) is available 956-ball Micro-FCBGA packages. The package

mechanical dimensions are shown in Figure 7.

The maximum outgoing co-planarity is 0.2 mm (8 mils) for SFF Package

The mechanical package pressure specifications are in a direction normal to the surface

of the processor. This requirement is to protect the processor die from fracture risk due

to uneven die pressure distribution under tilt, stack-up tolerances and other similar

conditions. These specifications assume that a mechanical attach is designed

specifically to load one type of processor.

Moreover, the processor package substrate should not be used as a mechanical

reference or load-bearing surface for the thermal or mechanical solution. Please refer

to the Santa Rosa Platform Mechanical Design Guide for more details.

Note:

For M-step based processors refer to the 2-MB package drawings.

Datasheet

33

Package Mechanical Specifications and Pin Information

Figure 3.

4-MB and Fused 2-MB Micro-FCPGA Processor Package Drawing (Sheet 1 of 2)

h

34

Datasheet

Package Mechanical Specifications and Pin Information

Figure 4.

4-MB and Fused 2-MB Micro-FCPGA Processor Package Drawing (Sheet 2 of 2)

Datasheet

35

Package Mechanical Specifications and Pin Information

Figure 5.

2-MB Micro-FCPGA Processor Package Drawing (Sheet 1 of 2)

36

Datasheet

Package Mechanical Specifications and Pin Information

Figure 6.

2-MB Micro-FCPGA Processor Package Drawing (Sheet 2 of 2)

Datasheet

37

Package Mechanical Specifications and Pin Information

Figure 7.

SFF (ULV DC) Die Micro-FCBGA Processor Package Drawing

38

Datasheet

Package Mechanical Specifications and Pin Information

4.2

Processor Pinout and Pin List

Table 13 shows the top view pinout of the Intel Celeron Dual-Core processor. The pin

list, arranged in two different formats, is shown in the following pages.

Table 13.

The Coordinates of the Processor Pins as Viewed from the Top of the Package

(Sheet 1 of 2)

1

2

3

4

5

6

7

8

9

10

11

12

13

A

B

VSS

RSVD

SMI#

INIT#

VSS

FERR#

DPSLP#

A20M#

VSS

VCC

VSS

VCC

VSS

VCC

VSS

A

B

LINT1

IGNNE

#

THERM

TRIP#

C

D

E

RESET#

VSS

RSVD

VSS

LINT0

VSS

VCC

VSS

VCC

VSS

C

D

E

STPCLK

#

PWRGO

OD

RSVD

BNR#

VSS

SLP#

DPRSTP

#

DBSY#

HITM#

VSS

VCC

VSS

VCC

VSS

VCC

VSS

F

BR0#

VSS

RS[0]#

RS[2]#

RS[1]#

VSS

RSVD

HIT#

F

G

TRDY#

BPRI#

G

REQ[1]

#

H

J

ADS#

A[9]#

VSS

LOCK#

A[3]#

DEFER#

VSS

H

J

REQ[3]

#

VSS

VCCP

REQ[2]

#

REQ[0]

#

K

L

VSS

A[6]#

A[4]#

VSS

VCCP

VSS

K

L

REQ[4]#

A[13]#

VSS

A[5]#

RSVD

ADSTB[0

]#

M

A[7]#

VCCP

M

N

P

R

T

VSS

A[8]#

A[12]#

VSS

A[10]#

VSS

RSVD

A[11]#

VSS

VCCP

VSS

N

P

R

T

A[15]#

A[16]#

VSS

A[14]#

A[24]#

VSS

A[19]#

A[26]#

VSS

VCCP

VSS

RSVD

A[25]#

A[18]#

U

A[23]#

A[30]#

A[21]#

U

ADSTB[1

]#

V

VSS

RSVD

A[31]#

VSS

VCCP

V

W

Y

VSS

COMP[3]

COMP[2]

VSS

A[27]#

A[17]#

VSS

A[32]#

VSS

A[29]#

A[33]#

VSS

A[28]#

A[22]#

VSS

A[20]#

VSS

W

Y

AA

AB

A[35]#

TDO

TDI

VCC

VSS

VCC

VSS

VCC

VSS

AA

AB

A[34]#

TMS

TRST#

BPM[3]

#

AC

AD

AE

AF

PREQ#

BPM[2]#

VSS

PRDY#

VSS

TCK

VSS

VID[0]

PSI#

VCC

VSS

VCC

VSS

VCC

VSS

VCC

AC

AD

AE

AF

BPM[1]

#

BPM[0]

#

VSS

SENSE

VID[6]

VID[4]

VSS

VID[2]

VCC

SENSE

TEST5

VSS

VID[5]

VID[3]

VID[1]

VSS

VCC

VSS

VCC

VSS

1

2

3

4

5

6

7

8

9

10

11

12

13

Datasheet

39

Package Mechanical Specifications and Pin Information

Table 14.

The Coordinates of the Processor Pins as Viewed from the Top of the Package

(Sheet 2 of 2)

14

15

16

17

18

19

20

21

22

23

24

THRMDA

VSS

25

26

A

B

C

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

BCLK[1]

VSS

BCLK[0]

BSEL[0]

VSS

TEST6

VCCA

A

B

C

VCC

BSEL[1]

TEST1

THRMDC

VSS

DBR#

BSEL[2]

TEST3

PROCHO

T#

D

VCC

VSS

VCC

VSS

IERR#

RSVD

VSS

DPWR#

TEST2

VSS

D

E

F

VSS

VCC

VSS

VCC

VSS

VCC

VSS

DRDY#

VCCP

D[0]#

VSS

D[7]#

D[4]#

VSS

D[6]#

VSS

D[2]#

D[13]#

VSS

E

F

D[1]#

D[9]#

G

D[3]#

D[5]#

G

DSTBP[

0]#

H

VSS

D[12]#

D[15]#

VSS

DINV[0]#

H

DSTBN[

0]#

J

K

L

VCCP

VSS

D[11]#

VSS

D[10]#

D[8]#

VSS

J

K

L

D[14]#

D[22]#

D[17]#

D[29]#

VSS

DSTBN[

1]#

D[20]#

DSTBP[

1]#

M

VCCP

VSS

D[23]#

D[21]#

VSS

M

N

P

VCCP

VSS

D[16]#

D[26]#

VSS

DINV[1]#

VSS

D[31]#

D[24]#

VSS

N

P

D[25]#

D[18]#

COMP[0

]

R

T

VCCP

VSS

D[19]#

VSS

D[28]#

D[27]#

VSS

R

T

D[37]#

DINV[2]#

D[30]#

D[38]#

VSS

COMP[1

]

U

D[39]#

U

V

VCCP

VSS

D[36]#

VSS

D[34]#

D[43]#

VSS

D[35]#

VSS

V

W

D[41]#

D[44]#

W

DSTBN[

2]#

Y

VSS

D[32]#

VSS

D[42]#

D[45]#

VSS

D[40]#

VSS

Y

DSTBP[

2]#

A

AA

VSS

VCC

VSS

VCC

VSS

VCC

D[50]#

D[46]#

A

B

AB

AC

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

D[52]#

VSS

D[51]#

D[60]#

VSS

D[63]#

D[61]#

VSS

D[33]#

VSS

D[47]#

D[57]#

VSS

DINV[3

]#

D[53]# AC

A

D

A

GTLREF

D

D[54]#

VCC

D[59]#

D[58]#

D[49]#

D[48]#

DSTBN[3]

#

AE

AF

D[55]#

VSS

AE

AF

DSTBP[3]

#

VCC

VSS

VCC

VSS

VCC

VSS

D[62]#

D[56]#

VSS

TEST4

14

15

16

17

18

19

20

21

22

23

24

25

26

40

Datasheet

Package Mechanical Specifications and Pin Information

Table 15.

SFF Processor Top View Upper Left Side

BD BC BB BA AY AW AV AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC

COMP[

2]

VSS

TMS

TDI

TDO

A[35]#

A[17]#

A[31]#

A[30]#

A[19]#

A[16]#

1

BPM[3]

#

COMP[

3]

VSS

VID[5]

VSS

PREQ#

TCK

A[22]#

A[20]#

VSS

A[34]#

A[28]#

VSS

A[32]#

A[27]#

VSS

A[21]#

A[18]#

VSS

A[23]#

A[26]#

VSS

A[11]#

A[12]#

VSS

2

VSS

VID[4]

VID[1]

VSS

3

VSS

VID[6]

VSS

A[24]#

VSS

4

BPM[2]

#

ADSTB

[1]#

RSVD0

4

RSVD0

3

A[33]#

VSS

A[29]#

VCCP

VSS

A[25]#

VCCP

VSS

A[14]#

VCCP

VSS

A[10]#

VCCP

VSS

5

VSS

6

BPM[1]

#

VCCP

VSS

VCCP

VSS

VCCP

VSS

7

BPM[0]

#

VID[0]

PSI#

VID[3]

VID[2]

VSS

TRST#

PRDY#

VSS

8

VSS

9

TEST5

VSS

VCCP

VCC

VSS

VCCP

VCC

VSS

VCCP

VCC

VSS

10

11

12

13

14

15

16

17

18

19

20

21

22

VSS

VCCP

VSS

VCCS

ENSE

VSS

VSSSE

NSE

VCC

VCCP

VCC

VCCP

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

Datasheet

41

Package Mechanical Specifications and Pin Information

Table 16.

SFF Processor Top View Upper Right Side

AB AA

Y

W

V

U

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

REQ[2]

#

REQ[0]

#

A[7]#

A[5]#

LOCK#

TRDY#

DBSY#

VSS

1

RSVD0

2

RSVD0

1

A[15]#

VSS

A[9]#

A[3]#

BR0#

RS[0]#

HIT#

HITM#

VSS

2

VSS

BPRI#

VCCP

VSS

BNR#

DBR#

VSS

LINT1

A20M#

LINT0

VSS

3

ADSTB

[0]#

REQ[3]

#

RSVD0

6

A[8]#

A[13]#

VSS

A[4]#

VSS

A[6]#

VSS

VCCP

VCC

ADS#

VSS

VCCP

VCC

RS[2]#

VSS

RS[1]#

VSS

FERR#

VSS

4

REQ[4]

#

REQ[1]

#

DEFER

#

RESET

#

SMI#

VSS

VCCP

VSS

5

VSS

VCCP

VCC

VSS

6

DPRST

P#

PWRG

OOD

VCCP

VSS

VCCP

VSS

VCCP

VSS

VCCP

VSS

VCCP

VSS

7

RSVD0

7

STPCL

K#

DPSLP

#

VSS

INIT#

SLP#

VCCP

VCC

8

RSVD0

5

VCCP

VSS

VCCP

VSS

VCCP

VSS

9

THER

MTRIP

#

IGNNE

#

VCCP

VCC

VCCP

VCC

VCCP

VCC

VSS

VCCP

VCC

10

11

12

13

14

15

16

17

18

19

20

21

22

VCCP

VSS

VCCP

VCC

VCCP

VCC

VCCP

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

42

Datasheet

Package Mechanical Specifications and Pin Information

Table 17.

SFF Processor Top View Lower Left Side

BD BC BB BA AY AW AV AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC

VSS

D[52]#

VSS

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

D[26]#

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VCCP

VSS

VCC

VCCP

VSS

VCC

THRM

DC

THRM

DA

VSS

D[58]#

D[62]#

D[54]#

VSS

VCCP

VSS

VCCP

VSS

VCCP

VSS

VCCP

VSS

D[55]#

D[61]#

VSS

D[56]#

VSS

VCCP

D[45]#

VSS

VCCP

D[43]#

VSS

VCCP

D[35]#

VSS

DINV[3

]#

VSS

DSTBP

[3]#

D[48]#

D[50]#

VSS

D[59]#

VSS

DSTBN

[3]#

D[57]#

VSS

D[42]#

VSS

D[34]#

VSS

DINV[2

]#

D[60]#

VSS

D[51]#

D[63]#

D[53]#

D[33]#

D[46]#

D[41]#

D[47]#

D[37]#

D[44]#

TEST4

D[27]#

TEST6

VSS

GTLRE

F

DSTBP

[2]#

COMP[

0]

D[36]#

DSTBN

[2]#

COMP[

1]

VSS

D[49]#

D[32]#

D[40]#

D[39]#

D[38]#

Datasheet

43

Package Mechanical Specifications and Pin Information

Table 18.

SFF Processor Top View Lower Right Side

AB AA

Y

W

V

U

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

VSS

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VCCP

VCCA

VSS

VCCP

VCCA

VSS

VCC

VCCP

VSS

VCC

VCCP

VSS

VCCP

TEST1

VSS

VCCP

VSS

VCCP

DRDY#

D[0]#

VSS

BCLK[

1]

BCLK[

0]

VCCP

VSS

VCCP

VSS

VCCP

VSS

VCCP

VSS

VCCP

VSS

VCCP

VSS

VCCP

D[17]#

VSS

VCCP

VSS

VCCP

VSS

BSEL[1

]

BSEL[0

]

PROC

HOT#

BSEL[2

]

VSS

D[6]#

D[13]#

D[1]#

VSS

DINV[0

]#

DSTBN

[0]#

D[25]#

D[24]#

VSS

D[29]#

VSS

D[11]#

VSS

D[12]#

VSS

D[4]#

VSS

TEST2

VSS

IERR#

VSS

DSTBP

[0]#

DPWR

#

D[21]#

D[23]#

D[20]#

D[10]#

D[22]#

D[8]#

D[15]#

D[7]#

D[2]#

VSS

DSTBP

[1]#

DSTBN

[1]#

DINV[1

]#

D[28]#

D[19]#

D[3]#

TEST3

D[30]#

D[18]#

D[31]#

D[16]#

D[14]#

D[9]#

D[5]#

VSS

44

Datasheet

Package Mechanical Specifications and Pin Information

Table 19.

Pin Name

Pin Listing by Pin Name

(Sheet 2 of 16)

Table 19.

Pin Name

Pin Listing by Pin Name

(Sheet 1 of 16)

Number

Signal Buffer

Type

Direction

Number

Signal Buffer

Type

Direction

Input/

Output

A[24]#

A[25]#

A[26]#

A[27]#

A[28]#

A[29]#

A[30]#

A[31]#

A[32]#

A[33]#

A[34]#

R4

Source Synch

Input/

Output

A[3]#

J4

Source Synch

Input/

Output

T5

Input/

Output

A[4]#

L5

L4

K5

M3

N2

J1

Input/

Output

T3

Input/

Output

A[5]#

Input/

Output

W2

W5

Y4

Input/

Output

A[6]#

Input/

Output

Input/

Output

A[7]#

Input/

Output

Input/

Output

A[8]#

Input/

Output

U2

Input/

Output

A[9]#

Input/

Output

V4

Input/

Output

A[10]#

A[11]#

A[12]#

A[13]#

A[14]#

A[15]#

A[16]#

A[17]#

A[18]#

A[19]#

A[20]#

A[21]#

A[22]#

A[23]#

N3

P5

P2

L2

P4

P1

R1

Y2

U5

R3

W6

U4

Y5

U1

Input/

Output

W3

AA4

AB2

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

A[35]#

A20M#

ADS#

AA3

A6

Source Synch

CMOS

Input/

Output

Input

Input/

Output

Input/

Output

H1

Common Clock

Input/

Output

Input/

Output

ADSTB[0]# M1

ADSTB[1]# V1

Source Synch

Input/

Output

Input/

Output

BCLK[0]

BCLK[1]

A22

A21

Bus Clock

Input

Input/

Output

Input/

Output

Input/

Output

BNR#

E2

Common Clock

Input/

Output

Input/

Output

BPM[0]#

AD4

Input/

Output

BPM[1]#

BPM[2]#

AD3

AD1

Common Clock Output

Input/

Output

Input/

Common Clock

Output

BPM[3]#

BPRI#

AC4

G5

Input/

Output

Common Clock Input

Datasheet

45

Package Mechanical Specifications and Pin Information

Table 19.

Pin Listing by Pin Name

(Sheet 3 of 16)

Table 19.

Pin Name

Pin Listing by Pin Name

(Sheet 4 of 16)

Signal Buffer

Type

Signal Buffer

Type

Pin Name

Direction

Number

Input/

Output

Input/

Output

BR0#

F1

Common Clock

D[15]#

D[16]#

D[17]#

D[18]#

D[19]#

D[20]#

D[21]#

D[22]#

D[23]#

D[24]#

D[25]#

D[26]#

D[27]#

D[28]#

D[29]#

D[30]#

D[31]#

D[32]#

D[33]#

D[34]#

D[35]#

D[36]#

H23

N22

K25

P26

R23

L23

M24

L22

M23

P25

P23

P22

T24

R24

L25

T25

N25

Y22

AB24

V24

V26

V23

Source Synch

BSEL[0]

BSEL[1]

BSEL[2]

B22

B23

C21

CMOS

Output

Input/

Output

Input/

Output

Input/

Output

COMP[0]

COMP[1]

COMP[2]

COMP[3]

D[0]#

R26

U26

AA1

Y1

Power/Other

Source Synch

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

E22

F24

E26

G22

F23

G25

E25

E23

K24

G24

J24

J23

H22

F26

K22

Input/

Output

Input/

Output

D[1]#

Input/

Output

Input/

Output

D[2]#

Input/

Output

Input/

Output

D[3]#

Input/

Output

Input/

Output

D[4]#

Input/

Output

Input/

Output

D[5]#

Input/

Output

Input/

Output

D[6]#

Input/

Output

Input/

Output

D[7]#

Input/

Output

Input/

Output

D[8]#

Input/

Output

Input/

Output

D[9]#

Input/

Output

Input/

Output

D[10]#

D[11]#

D[12]#

D[13]#

D[14]#

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

46

Datasheet

Package Mechanical Specifications and Pin Information

Table 19.

Pin Name

Pin Listing by Pin Name

(Sheet 5 of 16)

Table 19.

Pin Name

Pin Listing by Pin Name

(Sheet 6 of 16)

Signal Buffer

Type

Signal Buffer

Type

Direction

Number

Input/

Output

Input/

Output

D[37]#

D[38]#

D[39]#

D[40]#

D[41]#

D[42]#

D[43]#

D[44]#

D[45]#

D[46]#

D[47]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

T22

Source Synch

D[59]#

D[60]#

D[61]#

D[62]#

AD21

AC22

AD23

AF22

Source Synch

Input/

Output

Input/

Output

U25

Input/

Output

Input/

Output

U23

Input/

Output

Input/

Output

Y25

Input/

Output

Input/

Output

W22

Y23

D[63]#

DBR#

AC23

C20

E1

Source Synch

CMOS

Input/

Output

Input/

Output

DBSY#

DEFER#

DINV[0]#

Common Clock

Input/

Output

W24

W25

AA23

AA24

AB25

AE24

AD24

AA21

AB22

AB21

AC26

AD20

AE22

AF23

AC25

AE21

H5

Common Clock Input

Input/

Output

Input/

Source Synch

Output

H25

Input/

Output

Input/

Source Synch

Output

DINV[1]#

DINV[2]#

DINV[3]#

N24

U22

Input/

Output

Input/

Source Synch

Output

Input/

Output

Input/

Source Synch

Output

AC20

Input/

Output

DPRSTP#

DPSLP#

E5

B5

CMOS

Input

Input/

Output

Input/

Output

DPWR#

DRDY#

D24

F21

Common Clock

Source Synch

Input/

Output

Input/

Output

Input/

Output

Input/

Output

DSTBN[0]# J26

DSTBN[1]# L26

DSTBN[2]# Y26

DSTBN[3]# AE25

DSTBP[0]# H26

DSTBP[1]# M26

DSTBP[2]# AA26

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Datasheet

47

Package Mechanical Specifications and Pin Information

Table 19.

Pin Name

Pin Listing by Pin Name

(Sheet 7 of 16)

Table 19.

Pin Name

Pin Listing by Pin Name

(Sheet 8 of 16)

Signal Buffer

Type

Signal Buffer

Type

Direction

Number

Input/

Output

RSVD

SLP#

SMI#

STPCLK#

TCK

F6

Reserved

CMOS

Open Drain

Test

DSTBP[3]# AF24

Source Synch

M4

FERR#

A5

Open Drain

Output

Input

N5

GTLREF

AD26

Power/Other

T2

Input/

Output

HIT#

G6

E4

Common Clock

V3

D7

Input

Output

Input/

Output

HITM#

A3

IERR#

IGNNE#

INIT#

LINT0

LINT1

D20

C4

Open Drain

CMOS

Output

Input

D5

AC5

AA6

AB3

C23

D25

C24

AF26

AF1

A26

B3

CMOS

TDI

C6

CMOS

TDO

B4

CMOS

TEST1

TEST2

TEST3

TEST4

TEST5

TEST6

Input/

Output

Test

LOCK#

H4

Common Clock

Test

PRDY#

PREQ#

AC2

AC1

Common Clock Output

Common Clock Input

Test

Input/

Open Drain

PROCHOT# D21

Test

Output

THERMTRIP

#

PSI#

AE6

D6

CMOS

Output

Input

C7

Open Drain

Output

Input

PWRGOOD

THRMDA

THRMDC

TMS

A24

B25

AB5

G2

Power/Other

CMOS

Input/

Output

REQ[0]#

REQ[1]#

REQ[2]#

REQ[3]#

REQ[4]#

K3

H2

K2

J3

Source Synch

Input/

Output

TRDY#

TRST#

VCC

Common Clock Input

Input/

Output

AB6

A7

CMOS

Input

Power/Other

Input/

Output

VCC

A9

VCC

A10

A12

A13

A15

A17

A18

A20

AA7

AA9

AA10

AA12

Input/

Output

L1

VCC

RESET#

RS[0]#

RS[1]#

RS[2]#

RSVD

C1

F3

Common Clock Input

Reserved

VCC

F4

VCC

G3

B2

C3

D2

D3

D22

VCC

RSVD

Reserved

VCC

RSVD

Reserved

VCC

RSVD

Reserved

VCC

RSVD

Reserved

VCC

48

Datasheet

Package Mechanical Specifications and Pin Information

Table 19.

Pin Name

Pin Listing by Pin Name

(Sheet 9 of 16)

Table 19.

Pin Name

Pin Listing by Pin Name

(Sheet 10 of 16)

Signal Buffer

Type

Signal Buffer

Type

Direction

Number

VCC

AA13

AA15

AA17

AA18

AA20

AB7

Power/Other

VCC

AE18

AE20

AF9

AF10

AF12

AF14

AF15

AF17

AF18

AF20

B7

Power/Other

AB9

AB10

AB12

AB14

AB15

AB17

AB18

AB20

AC7

B9

B10

B12

B14

B15

B17

B18

B20

C9

AC9

AC10

AC12

AC13

AC15

AC17

AC18

AD7

C10

C12

C13

C15

C17

C18

D9

AD9

AD10

AD12

AD14

AD15

AD17

AD18

AE9

D10

D12

D14

D15

D17

D18

E7

AE10

AE12

AE13

AE15

AE17

E9

E10

Datasheet

49

Package Mechanical Specifications and Pin Information

Table 19.

Pin Name

Pin Listing by Pin Name

(Sheet 11 of 16)

Table 19.

Pin Name

Pin Listing by Pin Name

(Sheet 12 of 16)

Signal Buffer

Type

Signal Buffer

Type

Direction

Number

VCC

E12

E13

E15

E17

E18

E20

F7

Power/Other

CMOS

VID[2]

VID[3]

VID[4]

VID[5]

VID[6]

VSS

AE5

CMOS

Output

VCC

AF4

CMOS

VCC

AE3

CMOS

VCC

AF3

CMOS

VCC

AE2

CMOS

VCC

A2

Power/Other

Power/other

Power/Other

VCC

A4

VCC

F9

A8

VCC

F10

F12

F14

F15

F17

F18

F20

B26

C26

G21

J6

A11

VCC

A14

VCC

A16

VCC

A19

VCC

A23

VCC

A25

VCC

AA2

AA5

AA8

AA11

AA14

AA16

AA19

AA22

AA25

AB1

AB4

AB8

AB11

AB13

AB16

AB19

AB23

AB26

AC3

AC6

AC8

AC11

VCCA

VCCP

VCCSENSE

VID[0]

VID[1]

J21

K6

K21

M6

M21

N6

N21

R6

R21

T6

T21

V6

V21

W21

AF7

AD6

AF5

Output

CMOS

50

Datasheet

Package Mechanical Specifications and Pin Information

Table 19.

Pin Name

Pin Listing by Pin Name

(Sheet 13 of 16)

Table 19.

Pin Name

Pin Listing by Pin Name

(Sheet 14 of 16)

Signal Buffer

Type

Signal Buffer

Type

Direction

Number

VSS

AC14

AC16

AC19

AC21

AC24

AD2

Power/Other

VSS

B16

B19

B21

B24

C2

Power/Other

C5

AD5

C8

AD8

C11

C14

C16

C19

C22

C25

D1

AD11

AD13

AD16

AD19

AD22

AD25

AE1

D4

AE4

D8

AE8

D11

D13

D16

D19

D23

D26

E3

AE11

AE14

AE16

AE19

AE23

AE26

AF2

E6

AF6

E8

AF8

E11

E14

E16

E19

E21

E24

F2

AF11

AF13

AF16

AF19

AF21

AF25

B6

F5

B8

F8

B11

F11

F13

B13

Datasheet

51

Package Mechanical Specifications and Pin Information

Table 19.

Pin Name

Pin Listing by Pin Name

(Sheet 15 of 16)

Table 19.

Pin Name

Pin Listing by Pin Name

(Sheet 16 of 16)

Signal Buffer

Type

Signal Buffer

Type

Direction

Number

VSS

F16

F19

F22

F25

G1

Power/Other

VSS

VSSSENSE

R2

Power/Other

R5

R22

R25

T1

G4

T4

G23

G26

H3

T23

T26

U3

H6

U6

H21

H24

J2

U21

U24

V2

J5

V5

J22

J25

K1

V22

V25

W1

W4

W23

W26

Y3

K4

K23

K26

L3

L6

Y6

L21

L24

M2

Y21

Y24

AE7

Output

M5

M22

M25

N1

Table 20.

Pin Name

Pin Listing by Pin Number

(Sheet 1 of 17)

Signal

Direction

N4

Number Buffer Type

N23

N26

P3

VSS

A2

A3

A4

A5

A6

A7

Power/Other

CMOS

SMI#

VSS

Input

Power/Other

Open Drain

CMOS

P6

FERR#

A20M#

VCC

Output

Input

P21

P24

Power/Other

52

Datasheet

Package Mechanical Specifications and Pin Information

Table 20.

Pin Name

Pin Listing by Pin Number

(Sheet 2 of 17)

Table 20.

Pin Name

Pin Listing by Pin Number

(Sheet 3 of 17)

Signal

Direction

Number Buffer Type

VSS

A8

Power/Other

Bus Clock

VSS

VCC

VSS

VCC

AA16

AA17

AA18

AA19

AA20

Power/Other

VCC

A9

VCC

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

VSS

VCC

Input/

Output

D[50]#

VSS

AA21

AA22

AA23

Source Synch

Power/Other

Source Synch

VSS

VCC

Input/

Output

VSS

D[45]#

VCC

Input/

Output

D[46]#

VSS

AA24

AA25

AA26

AB1

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

VCC

VSS

VCC

Input/

Output

DSTBP[2]#

VSS

BCLK[1]

BCLK[0]

VSS

Input

Bus Clock

Input/

Output

Power/Other

Test

A[34]#

AB2

THRMDA

VSS

TDO

VSS

TMS

TRST#

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

AB3

Open Drain

Power/Other

CMOS

Output

AB4

TEST6

AB5

Input

Input/

Output

COMP[2]

VSS

AA1

AA2

AA3

Power/Other

Source Synch

AB6

CMOS

AB7

Power/Other

AB8

Input/

Output

A[35]#

AB9

Input/

Output

AB10

AB11

AB12

AB13

AB14

AB15

AB16

AB17

AB18

AB19

AB20

A[33]#

AA4

Source Synch

VSS

TDI

AA5

Power/Other

CMOS

AA6

Input

VCC

VSS

VCC

VSS

VCC

VSS

VCC

AA7

Power/Other

Power/other

Power/Other

AA8

AA9

AA10

AA11

AA12

AA13

AA14

AA15

Input/

Output

D[52]#

AB21

Source Synch

Datasheet

53

Package Mechanical Specifications and Pin Information

Table 20.

Pin Name

Pin Listing by Pin Number

(Sheet 4 of 17)

Table 20.

Pin Listing by Pin Number

(Sheet 5 of 17)

Signal

Direction

Pin Name

Direction

Number Buffer Type

Input/

Output

Input/

Output

D[51]#

VSS

AB22

AB23

AB24

Source Synch

Power/Other

Source Synch

D[53]#

AC26

Source Synch

Common

Clock

BPM[2]#

VSS

AD1

AD2

AD3

Output

Input/

Output

D[33]#

Power/Other

Input/

Output

Common

Clock

D[47]#

VSS

AB25

AB26

AC1

Source Synch

Power/Other

BPM[1]#

Output

Common

Clock

Input/

Output

BPM[0]#

AD4

Common

Clock

PREQ#

Input

VSS

VID[0]

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

AD5

Power/Other

CMOS

Common

Clock

AD6

Output

PRDY#

VSS

AC2

AC3

AC4

Output

AD7

Power/Other

AD8

Common

Clock

Input/

Output

BPM[3]#

AD9

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

TCK

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

AC5

CMOS

Input

AC6

Power/Other

AC7

AC8

AC9

AC10

AC11

AC12

AC13

AC14

AC15

AC16

AC17

AC18

AC19

Input/

Output

D[54]#

AD20

Source Synch

Input/

Output

D[59]#

VSS

AD21

AD22

AD23

Source Synch

Power/Other

Source Synch

Input/

Output

D[61]#

Input/

Output

DINV[3]#

VSS

AC20

AC21

AC22

Source Synch

Power/Other

Source Synch

Input/

Output

D[49]#

AD24

Source Synch

VSS

AD25

AD26

AE1

Power/Other

CMOS

Input/

Output

D[60]#

GTLREF

VSS

Input

Input/

Output

D[63]#

VSS

AC23

AC24

AC25

Source Synch

Power/Other

Source Synch

VID[6]

VID[4]

VSS

AE2

Output

AE3

CMOS

Input/

Output

D[57]#

AE4

Power/Other

54

Datasheet

Package Mechanical Specifications and Pin Information

Table 20.

Pin Name

Pin Listing by Pin Number

(Sheet 6 of 17)

Table 20.

Pin Name

Pin Listing by Pin Number

(Sheet 7 of 17)

Signal

Direction

Number Buffer Type

VID[2]

PSI#

VSSSENSE

VSS

AE5

CMOS

Output

VSS

VCC

VSS

VCC

VSS

VCC

VSS

AF13

AF14

AF15

AF16

AF17

AF18

AF19

AF20

AF21

Power/Other

AE6

CMOS

AE7

Power/Other

AE8

VCC

AE9

VCC

AE10

AE11

AE12

AE13

AE14

AE15

AE16

AE17

AE18

AE19

AE20

VSS

VCC

VSS

Input/

Output

D[62]#

AF22

AF23

AF24

Source Synch

VCC

Input/

Output

VSS

D[56]#

VCC

Input/

Output

DSTBP[3]#

VCC

VSS

AF25

AF26

B2

Power/Other

Test

VCC

TEST4

RSVD

INIT#

LINT1

DPSLP#

VSS

Input/

Output

Reserved

D[58]#

AE21

Source Synch

B3

CMOS

Input

Input/

Output

D[55]#

VSS

AE22

AE23

AE24

Source Synch

Power/Other

Source Synch

B4

CMOS

B5

CMOS

B6

Power/Other

Input/

Output

D[48]#

VCC

B7

Input/

Output

VSS

B8

DSTBN[3]# AE25

Source Synch

VCC

B9

VSS

AE26

AF1

Power/Other

Test

VCC

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

TEST5

VSS

AF2

Power/Other

CMOS

VCC

VID[5]

VID[3]

VID[1]

VSS

AF3

Output

VSS

AF4

CMOS

VCC

AF5

CMOS

VCC

AF6

Power/Other

VSS

VCCSENSE

VSS

AF7

VCC

AF8

VCC

AF9

VSS

VCC

AF10

AF11

AF12

VCC

VSS

VCC

Datasheet

55

Package Mechanical Specifications and Pin Information

Table 20.

Pin Name

Pin Listing by Pin Number

(Sheet 8 of 17)

Table 20.

Pin Name

Pin Listing by Pin Number

(Sheet 9 of 17)

Signal

Direction

Number Buffer Type

BSEL[0]

BSEL[1]

VSS

B22

B23

B24

B25

B26

CMOS

Output

STPCLK#

PWRGOOD

SLP#

VSS

D5

CMOS

Input

CMOS

D6

CMOS

Power/Other

D7

CMOS

THRMDC

VCCA

D8

Power/Other

Open Drain

VCC

D9

Common

Clock

VCC

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

RESET#

C1

Input

VSS

C2

C3

C4

C5

C6

Power/Other

Reserved

CMOS

VCC

RSVD

IGNNE#

VSS

VCC

Power/Other

CMOS

VCC

LINT0

Input

VSS

THERMTRIP

#

C7

Open Drain

Output

VCC

VSS

C8

Power/Other

CMOS

VSS

VCC

C9

IERR#

Output

VCC

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

C25

C26

D1

Input/

Output

VSS

PROCHOT#

D21

Open Drain

VCC

RSVD

VSS

D22

D23

Reserved

VCC

Power/Other

VSS

Common

Clock

Input/

Output

DPWR#

D24

VCC

VSS

TEST2

VSS

D25

D26

Test

VCC

Power/Other

VCC

Common

Clock

Input/

Output

DBSY#

E1

VSS

Common

Clock

Input/

Output

DBR#

BSEL[2]

VSS

Output

BNR#

VSS

E2

E3

E4

CMOS

Power/Other

Test

Common

Clock

Input/

Output

HITM#

TEST1

TEST3

VSS

Test

DPRSTP#

VSS

E5

CMOS

Input

Power/Other

Reserved

E6

Power/Other

VCCA

VSS

VCC

E7

VSS

E8

RSVD

VSS

D2

VCC

E9

D3

Reserved

VCC

E10

E11

D4

Power/Other

VSS

56

Datasheet

Package Mechanical Specifications and Pin Information

Table 20.

Pin Name

Pin Listing by Pin Number

(Sheet 10 of 17)

Table 20.

Pin Name

Pin Listing by Pin Number

(Sheet 11 of 17)

Signal

Direction

Number Buffer Type

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

E12

E13

E14

E15

E16

E17

E18

E19

E20

E21

Power/Other

VCC

VSS

VCC

F18

F19

F20

Power/Other

Common

Clock

Input/

Output

DRDY#

VSS

F21

F22

F23

Power/Other

Source Synch

Input/

Output

D[4]#

Input/

Output

D[1]#

VSS

F24

F25

F26

G1

Source Synch

Power/Other

Source Synch

Power/Other

Input/

Output

Input/

Output

D[0]#

E22

Source Synch

D[13]#

VSS

Input/

Output

D[7]#

VSS

E23

E24

E25

Source Synch

Power/Other

Source Synch

Common

Clock

TRDY#

G2

Input

Input/

Output

Common

Clock

D[6]#

RS[2]#

VSS

G3

G4

G5

Input/

Output

Power/Other

D[2]#

E26

Source Synch

Common

Clock

BPRI#

Input

Common

Clock

Input/

Output

BR0#

VSS

F1

F2

F3

Common

Clock

Input/

Output

HIT#

VCCP

D[3]#

VSS

G6

Power/Other

Common

Clock

G21

G22

G23

G24

Power/Other

Source Synch

Power/Other

Source Synch

RS[0]#

Input

Input/

Output

Common

Clock

RS[1]#

F4

VSS

RSVD

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

F5

Power/Other

Reserved

Input/

Output

D[9]#

F6

F7

Power/Other

Input/

Output

D[5]#

VSS

G25

G26

H1

Source Synch

Power/Other

F8

F9

Common

Clock

Input/

Output

F10

F11

F12

F13

F14

F15

F16

F17

ADS#

Input/

Output

REQ[1]#

VSS

H2

H3

H4

Source Synch

Power/Other

Common

Clock

Input/

Output

LOCK#

Common

Clock

DEFER#

H5

Input

Datasheet

57

Package Mechanical Specifications and Pin Information

Table 20.

Pin Name

Pin Listing by Pin Number

(Sheet 12 of 17)

Table 20.

Pin Name

Pin Listing by Pin Number

(Sheet 13 of 17)

Signal

Direction

Number Buffer Type

VSS

H6

Power/Other

VSS

K23

K24

Power/Other

Source Synch

H21

Input/

Output

D[8]#

Input/

Output

D[12]#

H22

Source Synch

Input/

Output

D[17]#

VSS

K25

K26

L1

Source Synch

Power/Other

Source Synch

Input/

Output

D[15]#

VSS

H23

H24

H25

Source Synch

Power/Other

Source Synch

Input/

Output

REQ[4]#

Input/

Output

DINV[0]#

Input/

Output

A[13]#

VSS

L2

L3

L4

Source Synch

Power/Other

Source Synch

Input/

Output

DSTBP[0]#

H26

Source Synch

Input/

Output

Input/

Output

A[9]#

VSS

J1

J2

J3

Source Synch

Power/Other

Source Synch

A[5]#

Input/

Output

A[4]#

L5

Source Synch

Input/

Output

REQ[3]#

VSS

L6

Power/Other

Input/

Output

L21

A[3]#

J4

Source Synch

Input/

Output

D[22]#

L22

Source Synch

VSS

J5

Power/Other

VCCP

VSS

J6

Input/

Output

D[20]#

VSS

L23

L24

L25

Source Synch

Power/Other

Source Synch

J21

J22

Input/

Output

Input/

Output

D[29]#

D[11]#

J23

Source Synch

Input/

Output

Input/

Output

DSTBN[1]# L26

Source Synch

D[10]#

VSS

J24

J25

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Input/

Output

ADSTB[0]#

VSS

M1

M2

M3

Source Synch

Power/Other

Source Synch

Input/

Output

DSTBN[0]# J26

Input/

Output

VSS

K1

K2

A[7]#

Input/

Output

REQ[2]#

RSVD

VSS

M4

Reserved

M5

Power/Other

Input/

Output

REQ[0]#

VSS

K3

K4

K5

Source Synch

Power/Other

Source Synch

VCCP

VSS

M6

M21

M22

Input/

Output

A[6]#

Input/

Output

D[23]#

M23

Source Synch

VCCP

K6

Power/Other

K21

Input/

Output

D[21]#

VSS

M24

M25

Source Synch

Power/Other

Input/

Output

D[14]#

K22

Source Synch

58

Datasheet

Package Mechanical Specifications and Pin Information

Table 20.

Pin Name

Pin Listing by Pin Number

(Sheet 14 of 17)

Table 20.

Pin Name

Pin Listing by Pin Number

(Sheet 15 of 17)

Signal

Direction

Number Buffer Type

Input/

Output

VSS

R2

R3

Power/Other

Source Synch

DSTBP[1]#

VSS

M26

N1

Source Synch

Power/Other

Source Synch

Input/

Output

A[19]#

Input/

Output

Input/

Output

A[8]#

N2

A[24]#

R4

Source Synch

Input/

Output

VSS

R5

Power/Other

A[10]#

N3

Source Synch

VCCP

VSS

R6

VSS

N4

Power/Other

Reserved

R21

R22

RSVD

VCCP

N5

N6

Power/Other

Input/

Output

D[19]#

R23

Source Synch

N21

Input/

Output

Input/

Output

D[16]#

VSS

N22

N23

N24

Source Synch

Power/Other

Source Synch

D[28]#

VSS

R24

R25

R26

Source Synch

Power/Other

Input/

Output

Input/

Output

DINV[1]#

COMP[0]

Input/

Output

VSS

T1

T2

Power/Other

Reserved

D[31]#

VSS

N25

N26

P1

Source Synch

Power/Other

Source Synch

RSVD

Input/

Output

A[26]#

VSS

T3

T4

T5

Source Synch

Power/Other

Source Synch

Input/

Output

A[15]#

Input/

Output

A[12]#

VSS

P2

P3

P4

Source Synch

Power/Other

Source Synch

Input/

Output

A[25]#

VCCP

T6

Power/Other

Input/

Output

A[14]#

T21

Input/

Output

Input/

Output

D[37]#

VSS

T22

T23

T24

Source Synch

Power/Other

Source Synch

A[11]#

P5

Source Synch

VSS

P6

Power/Other

Input/

Output

P21

D[27]#

Input/

Output

D[26]#

P22

Source Synch

Input/

Output

D[30]#

VSS

T25

T26

U1

Source Synch

Power/Other

Source Synch

Input/

Output

D[25]#

VSS

P23

P24

P25

Source Synch

Power/Other

Source Synch

Input/

Output

A[23]#

Input/

Output

D[24]#

Input/

Output

A[30]#

VSS

U2

U3

U4

Source Synch

Power/Other

Source Synch

Input/

Output

D[18]#

A[16]#

P26

R1

Source Synch

Input/

Output

Input/

Output

A[21]#

Datasheet

59

Package Mechanical Specifications and Pin Information

Table 20.

Pin Listing by Pin Number

(Sheet 16 of 17)

Table 20.

Pin Name

Pin Listing by Pin Number

(Sheet 17 of 17)

Signal

Pin Name

Direction

Number Buffer Type

Input/

Output

Input/

Output

A[18]#

U5

Source Synch

D[41]#

VSS

W22

W23

W24

Source Synch

Power/Other

Source Synch

VSS

U6

Power/Other

U21

Input/

Output

D[43]#

Input/

Output

DINV[2]#

U22

Source Synch

Input/

Output

D[44]#

VSS

W25

W26

Y1

Source Synch

Power/Other

Input/

Output

D[39]#

VSS

U23

U24

U25

Source Synch

Power/Other

Source Synch

Input/

Output

COMP[3]

Input/

Output

D[38]#

Input/

Output

A[17]#

VSS

Y2

Y3

Y4

Source Synch

Power/Other

Source Synch

Input/

Output

COMP[1]

U26

V1

Power/Other

Source Synch

Input/

Output

Input/

Output

ADSTB[1]#

A[29]#

VSS

V2

V3

Power/Other

Reserved

Input/

Output

A[22]#

Y5

Source Synch

RSVD

VSS

Y6

Power/Other

Input/

Output

A[31]#

V4

Source Synch

Y21

VSS

V5

Power/Other

Input/

Output

D[32]#

Y22

Source Synch

VCCP

VSS

V6

Input/

Output

V21

V22

D[42]#

VSS

Y23

Y24

Y25

Source Synch

Power/Other

Source Synch

Input/

Output

D[36]#

V23

Source Synch

Input/

Output

D[40]#

Input/

Output

D[34]#

VSS

V24

V25

V26

W1

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Input/

Output

DSTBN[2]# Y26

Source Synch

Input/

Output

D[35]#

VSS

Input/

Output

A[27]#

W2

Input/

Output

A[32]#

VSS

W3

W4

W5

Source Synch

Power/Other

Source Synch

Input/

Output

A[28]#

Input/

Output

A[20]#

VCCP

W6

Source Synch

Power/Other

W21

60

Datasheet

Package Mechanical Specifications and Pin Information

Table 21.

SFF Listing by Ball Name

Ball

Number

Signal Name

Ball

Number

Signal Name

ADSTB[1]#

BCLK[0]

BCLK[1]

BNR#

AN5

A35

C35

J5

A[3]#

A[4]#

P2

V4

A[5]#

W1

A[6]#

T4

BPM[0]#

BPM[1]#

BPM[2]#

BPM[3]#

BPRI#

AY8

BA7

BA5

AY2

L5

A[7]#

AA1

AB4

T2

A[8]#

A[9]#

A[10]#

A[11]#

A[12]#

A[13]#

A[14]#

A[15]#

A[16]#

A[17]#

A[18]#

A[19]#

A[20]#

A[21]#

A[22]#

A[23]#

A[24]#

A[25]#

A[26]#

A[27]#

A[28]#

A[29]#

A[30]#

A[31]#

A[32]#

A[33]#

A[34]#

A[35]#

A20M#

ADS#

AC5

AD2

AD4

AA5

AE5

AB2

AC1

AN1

AK4

AG1

AT4

AK2

AT2

AH2

AF4

AJ5

AH4

AM4

AP4

AR5

AJ1

AL1

AM2

AU5

AP2

AR1

C7

BR0#

M2

BSEL[0]

BSEL[1]

BSEL[2]

COMP[0]

COMP[1]

COMP[2]

COMP[3]

D[0]#

A37

C37

B38

AE43

AD44

AE1

AF2

F40

G43

E43

J43

D[1]#

D[2]#

D[3]#

D[4]#

H40

H44

G39

E41

L41

K44

N41

T40

M40

G41

M44

L43

P44

V40

V44

AB44

D[5]#

D[6]#

D[7]#

D[8]#

D[9]#

D[10]#

D[11]#

D[12]#

D[13]#

D[14]#

D[15]#

D[16]#

D[17]#

D[18]#

D[19]#

M4

ADSTB[0]#

Y4

Datasheet

61

Package Mechanical Specifications and Pin Information

Ball

Number

Ball

Signal Name

Number

D[20]#

D[21]#

D[22]#

D[23]#

D[24]#

D[25]#

D[26]#

D[27]#

D[28]#

D[29]#

D[30]#

D[31]#

D[32]#

D[33]#

D[34]#

D[35]#

D[36]#

D[37]#

D[38]#

D[39]#

D[40]#

D[41]#

D[42]#

D[43]#

D[44]#

D[45]#

D[46]#

D[47]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

R41

W41

D[58]#

D[59]#

BC35

BC39

BA41

BB40

BA35

AU43

J7

N43

D[60]#

U41

D[61]#

AA41

AB40

AD40

AC41

AA43

Y40

D[62]#

D[63]#

DBR#

DBSY#

J1

DEFER#

DINV[0]#

DINV[1]#

DINV[2]#

DINV[3]#

DPRSTP#

DPSLP#

DPWR#

N5

P40

R43

AJ41

BC37

G7

Y44

T44

AP44

AR43

AH40

AF40

AJ43

AG41

AF44

AH44

AM44

AN43

AM40

AK40

AG43

AP40

AN41

AL41

AV38

AT44

AV40

AU41

AW41

AR41

BA37

BB38

AY36

AT40

B8

C41

F38

K40

U43

AK44

AY40

J41

DRDY#

DSTBN[0]#

DSTBN[1]#

DSTBN[2]#

DSTBN[3]#

DSTBP[0]#

DSTBP[1]#

DSTBP[2]#

DSTBP[3]#

FERR#

W43

AL43

AY38

D4

GTLREF

AW43

H2

HIT#

HITM#

F2

IERR#

B40

F10

D8

IGNNE#

INIT#

LINT0

C9

LINT1

C5

LOCK#

N1

PRDY#

AV10

AV2

D38

PREQ#

PROCHOT#

62

Datasheet

Package Mechanical Specifications and Pin Information

Ball

Number

Ball

Number

Signal Name

PSI#

PWRGOOD

REQ[0]#

REQ[1]#

REQ[2]#

REQ[3]#

REQ[4]#

RESET#

RS[0]#

RS[1]#

RS[2]#

RSVD01

RSVD02

RSVD03

RSVD04

RSVD05

RSVD06

RSVD07

SLP#

BD10

E7

VCC

AB18

AB20

AB22

AB24

AB26

AB28

AB30

AB32

AC33

AD16

AD18

AD20

AD22

AD24

AD26

AD28

AD30

AD32

AE33

AF16

AF18

AF20

AF22

AF24

AF26

AF28

AF30

AF32

AG33

AH16

AH18

AH20

AH22

AH24

AH26

AH28

AH30

AH32

R1

R5

U1

P4

W5

G5

K2

H4

K4

V2

Y2

AG5

AL5

J9

F4

H8

D10

E5

SMI#

STPCLK#

TCK

F8

AV4

AW7

AU1

E37

D40

C43

AE41

AY10

AC43

B10

BB34

BD34

AW5

L1

TDI

TDO

TEST1

TEST2

TEST3

TEST4

TEST5

TEST6

THERMTRIP#

THRMDA

THRMDC

TMS

TRDY#

TRST#

VCC

AV8

AA33

AB16

VCC

Datasheet

63

Package Mechanical Specifications and Pin Information

Ball

Number

Ball

Signal Name

Number

VCC

AJ33

AK16

AK18

AK20

AK22

AK24

AK26

AK28

AK30

AK32

AL33

AM14

AM16

AM18

AM20

AM22

AM24

AM26

AM28

AM30

AM32

AN33

AP14

AP16

AP18

AP20

AP22

AP24

AP26

AP28

AP30

AP32

AR33

AT14

AT16

AT18

AT20

AT22

VCC

AT24

AT26

AT28

AT30

AT32

AT34

AU33

AV14

AV16

AV18

AV20

AV22

AV24

AV26

AV28

AV30

AV32

AY14

AY16

AY18

AY20

AY22

AY24

AY26

AY28

AY30

AY32

B16

B18

B20

B22

B24

B26

B28

B30

BB14

BB16

BB18

64

Datasheet

Package Mechanical Specifications and Pin Information

Ball

Number

Ball

Number

Signal Name

VCC

BB20

BB22

BB24

BB26

BB28

BB30

BB32

BD14

BD16

BD18

BD20

BD22

BD24

BD26

BD28

BD30

BD32

D16

VCC

H22

H24

H26

H28

H30

H32

J33

K16

K18

K20

K22

K24

K26

K28

K30

K32

L33

M16

M18

M20

M22

M24

M26

M28

M30

M32

N33

P16

P18

P20

P22

P24

P26

P28

P30

P32

R33

T16

D18

D20

D22

D24

D26

D28

D30

F16

F18

F20

F22

F24

F26

F28

F30

F32

G33

H16

H18

H20

Datasheet

65

Package Mechanical Specifications and Pin Information

Ball

Number

Ball

Signal Name

Number

VCC

VCCA

VCCP

T18

T20

T22

T24

T26

T28

T30

T32

U33

V16

V18

V20

V22

V24

V26

V28

V30

V32

W33

Y16

Y18

Y20

Y22

Y24

Y26

Y28

Y30

Y32

B34

D34

A13

A33

AA7

AA9

AA11

AA13

AA35

AA37

VCCP

AB10

AB12

AB14

AB36

AB38

AC7

AC9

AC11

AC13

AC35

AC37

AD14

AE7

AE9

AE11

AE13

AE35

AE37

AF10

AF12

AF14

AF36

AF38

AG7

AG9

AG11

AG13

AG35

AG37

AH14

AJ7

AJ9

AJ11

AJ13

AJ35

AJ37

AK10

AK12

66

Datasheet

Package Mechanical Specifications and Pin Information

Ball

Number

Ball

Number

Signal Name

VCCP

AK14

AK36

AK38

AL7

VCCP

F14

F34

F36

G11

G13

G35

H12

H14

H36

J11

J13

J35

J37

K10

K12

K14

K36

K38

L7

AL9

AL11

AL13

AL35

AL37

AN7

AN9

AN11

AN13

AN35

AN37

AP10

AP12

AP36

AP38

AR7

L9

AR9

L11

L13

L35

L37

M14

N7

AR11

AR13

AU11

AU13

B12

B14

N9

B32

N11

N13

N35

N37

P10

P12

P14

P36

P38

R7

C13

C33

D12

D14

D32

E11

E13

E33

E35

F12

R9

Datasheet

67

Package Mechanical Specifications and Pin Information

Ball

Number

Ball

Signal Name

Number

VCCP

VCCSENSE

VID[0]

VID[1]

VID[2]

VID[3]

VID[4]

VID[5]

VID[6]

VSS

R11

R13

R35

R37

T14

U7

VSS

A21

A23

A25

A27

A29

A31

U9

A39

U11

U13

U35

U37

V10

V12

V14

V36

V38

W7

A41

AA3

AA15

AA17

AA19

AA21

AA23

AA25

AA27

AA29

AA31

AA39

AB6

W9

W11

W13

W35

W37

Y14

BD12

BD8

BC7

BB10

BB8

BC5

BB4

AY4

A5

AB8

AB34

AB42

AC3

AC15

AC17

AC19

AC21

AC23

AC25

AC27

AC29

AC31

AC39

AD6

VSS

A7

VSS

A9

VSS

A11

A15

A17

A19

VSS

AD8

VSS

AD10

AD12

VSS

68

Datasheet

Package Mechanical Specifications and Pin Information

Ball

Number

Ball

Number

Signal Name

VSS

AD34

AD36

AD38

AD42

AE3

VSS

AJ3

AJ15

AJ17

AJ19

AJ21

AJ23

AJ25

AJ27

AJ29

AJ31

AJ39

AK6

AE15

AE17

AE19

AE21

AE23

AE25

AE27

AE29

AE31

AE39

AF6

AK8

AK34

AK42

AL3

AF8

AL15

AL17

AL19

AL21

AL23

AL25

AL27

AL29

AL31

AL39

AM6

AF34

AF42

AG3

AG15

AG17

AG19

AG21

AG23

AG25

AG27

AG29

AG31

AG39

AH6

AM8

AM10

AM12

AM34

AM36

AM38

AM42

AN3

AH8

AH10

AH12

AH34

AH36

AH38

AH42

AN15

AN17

AN19

Datasheet

69

Package Mechanical Specifications and Pin Information

Ball

Number

Ball

Signal Name

Number

VSS

AN21

AN23

AN25

AN27

AN29

AN31

AN39

AP6

VSS

AU23

AU25

AU27

AU29

AU31

AU35

AU37

AU39

AV6

AP8

AP34

AP42

AR3

AV12

AV34

AV36

AV42

AV44

AW1

AR15

AR17

AR19

AR21

AR23

AR25

AR27

AR29

AR31

AR35

AR37

AR39

AT6

AW3

AW9

AW11

AW13

AW15

AW17

AW19

AW21

AW23

AW25

AW27

AW29

AW31

AW33

AW35

AW37

AW39

AY6

AT8

AT10

AT12

AT36

AT38

AT42

AU3

AU7

AU9

AY12

AY34

AY42

AY44

B4

AU15

AU17

AU19

AU21

70

Datasheet

Package Mechanical Specifications and Pin Information

Ball

Number

Ball

Number

Signal Name

VSS

B6

VSS

BC41

BD4

BD6

BD36

BD38

BD40

C3

B36

B42

BA1

BA3

BA9

BA11

BA13

BA15

BA17

BA19

BA21

BA23

BA25

BA27

BA29

BA31

BA33

BA39

BA43

BB2

C11

C15

C17

C19

C21

C23

C25

C27

C29

C31

C39

D2

D6

D36

D42

D44

E1

BB6

BB12

BB36

BB42

BC3

E3

E9

BC9

E15

E17

E19

E21

E23

E25

E27

E29

E31

E39

F6

BC11

BC15

BC17

BC19

BC21

BC23

BC25

BC27

BC29

BC31

BC33

F42

Datasheet

71

Package Mechanical Specifications and Pin Information

Ball

Number

Ball

Signal Name

Number

VSS

F44

G1

VSS

L21

L23

L25

L27

L29

L31

L39

M6

G3

G9

G15

G17

G19

G21

G23

G25

G27

G29

G31

G37

H6

M8

M10

M12

M34

M36

M38

M42

N3

H10

H34

H38

H42

J3

N15

N17

N19

N21

N23

N25

N27

N29

N31

N39

P6

J15

J17

J19

J21

J23

J25

J27

J29

J31

J39

K6

P8

P34

P42

R3

K8

R15

R17

R19

R21

R23

R25

R27

K34

K42

L3

L15

L17

L19

72

Datasheet

Package Mechanical Specifications and Pin Information

Ball

Number

Ball

Number

Signal Name

VSS

R29

R31

R39

T6

VSS

Y6

Y8

VSS

Y10

Y12

Y34

Y36

Y38

Y42

BC13

VSS

T8

VSS

T10

T12

T34

T36

T38

T42

U3

VSS

VSSSENSE

U5

U15

U17

U19

U21

U23

U25

U27

U29

U31

U39

V6

V8

V34

V42

W3

W15

W17

W19

W21

W23

W25

W27

W29

W31

W39

Datasheet

73

Package Mechanical Specifications and Pin Information

74

Datasheet

Package Mechanical Specifications and Pin Information

4.3

Alphabetical Signals Reference

Table 22.

Name

Signal Description (Sheet 1 of 7)

Type

Description

A[35:3]# (Address) define a 2³⁶-byte physical memory address space. In sub-

phase 1 of the address phase, these pins transmit the address of a transaction. In

sub-phase 2, these pins transmit transaction type information. These signals must

connect the appropriate pins of both agents on the processor FSB. A[35:3]# are

source synchronous signals and are latched into the receiving buffers by

ADSTB[1:0]#. Address signals are used as straps which are sampled before

RESET# is deasserted.

Input/

Output

A[35:3]#

If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit

20 (A20#) before looking up a line in any internal cache and before driving a read/

write transaction on the bus. Asserting A20M# emulates the 8086 processor's

address wrap-around at the 1-Mbyte boundary. Assertion of A20M# is only

supported in real mode.

A20M#

Input

A20M# is an asynchronous signal. However, to ensure recognition of this signal

following an Input/Output write instruction, it must be valid along with the TRDY#

assertion of the corresponding Input/Output Write bus transaction.

ADS# (Address Strobe) is asserted to indicate the validity of the transaction

address on the A[35:3]# and REQ[4:0]# pins. All bus agents observe the ADS#

activation to begin parity checking, protocol checking, address decode, internal

snoop, or deferred reply ID match operations associated with the new transaction.

Input/

Output

ADS#

Address strobes are used to latch A[35:3]# and REQ[4:0]# on their rising and

falling edges. Strobes are associated with signals as shown below.

Input/

Output

Signals

REQ[4:0]#, A[16:3]# ADSTB[0]#

A[35:17]# ADSTB[1]#

Associated Strobe

ADSTB[1:0]#

The differential pair BCLK (Bus Clock) determines the FSB frequency. All FSB

agents must receive these signals to drive their outputs and latch their inputs.

BCLK[1:0]

BNR#

Input

All external timing parameters are specified with respect to the rising edge of

BCLK0 crossing V_CROSS

.

BNR# (Block Next Request) is used to assert a bus stall by any bus agent who is

unable to accept new bus transactions. During a bus stall, the current bus owner

cannot issue any new transactions.

Input/

Output

BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals.

They are outputs from the processor which indicate the status of breakpoints and

programmable counters used for monitoring processor performance. BPM[3:0]#

should connect the appropriate pins of all processor FSB agents.This includes

debug or performance monitoring tools.

Output

BPM[2:1]#

BPM[3,0]#

Input/

Output

BPRI# (Bus Priority Request) is used to arbitrate for ownership of the FSB. It must

connect the appropriate pins of both FSB agents. Observing BPRI# active (as

asserted by the priority agent) causes the other agent to stop issuing new

requests, unless such requests are part of an ongoing locked operation. The

priority agent keeps BPRI# asserted until all of its requests are completed, then

releases the bus by deasserting BPRI#.

BPRI#

BR0#

Input

Input/

Output

BR0# is used by the processor to request the bus. The arbitration is done between

processor (Symmetric Agent) and (G)MCH (High Priority Agent).

Datasheet

75

Package Mechanical Specifications and Pin Information

Table 22.

Name

Signal Description (Sheet 2 of 7)

Type

Description

BSEL[2:0] (Bus Select) are used to select the processor input clock frequency.

Table 3 defines the possible combinations of the signals and the frequency

associated with each combination. The required frequency is determined by the

processor, chipset and clock synthesizer. All agents must operate at the same

frequency.

BSEL[2:0]

COMP[3:0]

Output

COMP[3:0] must be terminated on the system board using precision (1%

tolerance) resistors.

Analog

D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path

between the FSB agents, and must connect the appropriate pins on both agents.

The data driver asserts DRDY# to indicate a valid data transfer.

D[63:0]# are quad-pumped signals and are driven four times in a common clock

period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and

DSTBN[3:0]#. Each group of 16 data signals corresponds to a pair of one DSTBP#

and one DSTBN#. The following table shows the grouping of data signals to data

strobes and DINV#.

Quad-Pumped Signal Groups

Data

Group

DSTBN#/

DSTBP#

Input/

Output

DINV#

D[63:0]#

D[15:0]#

D[31:16]#

D[47:32]#

D[63:48]#

0

1

2

3

0

1

2

3

Furthermore, the DINV# pins determine the polarity of the data signals. Each

group of 16 data signals corresponds to one DINV# signal. When the DINV# signal

is active, the corresponding data group is inverted and therefore sampled active

high.

DBR# (Data Bus Reset) is used only in processor systems where no debug port is

implemented on the system board. DBR# is used by a debug port interposer so

that an in-target probe can drive system reset. If a debug port is implemented in

the system, DBR# is a no-connect in the system. DBR# is not a processor signal.

DBR#

Output

DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on

the FSB to indicate that the data bus is in use. The data bus is released after

DBSY# is deasserted. This signal must connect the appropriate pins on both FSB

agents.

Input/

Output

DBSY#

DEFER#

DEFER# is asserted by an agent to indicate that a transaction cannot be

guaranteed in-order completion. Assertion of DEFER# is normally the responsibility

of the addressed memory or Input/Output agent. This signal must connect the

appropriate pins of both FSB agents.

Input

76

Datasheet

Package Mechanical Specifications and Pin Information

Table 22.

Name

Signal Description (Sheet 3 of 7)

Type

Description

DINV[3:0]# (Data Bus Inversion) are source synchronous and indicate the polarity

of the D[63:0]# signals. The DINV[3:0]# signals are activated when the data on

the data bus is inverted. The bus agent inverts the data bus signals if more than

half the bits, within the covered group, would change level in the next cycle.

DINV[3:0]# Assignment To Data Bus

Data Bus

Bus Signal

Input/

Output

DINV[3:0]#

Signals

DINV[3]#

DINV[2]#

DINV[1]#

DINV[0]#

D[63:48]#

D[47:32]#

D[31:16]#

D[15:0]#

DPRSTP# when asserted on the platform causes the processor to transition from

the Deep Sleep State to the Deeper Sleep state. In order to return to the Deep

Sleep State, DPRSTP# must be deasserted. DPRSTP# is driven by the Intel

82801HBM ICH8M I/O Controller Hub-based chipset.

DPRSTP#

Input

DPSLP# when asserted on the platform causes the processor to transition from the

Sleep State to the Deep Sleep state. In order to return to the Sleep State, DPSLP#

must be deasserted. DPSLP# is driven by the Intel 82801HBM ICH8M chipset.

DPSLP#

DPWR#

DPWR# is a control signal used by the chipset to reduce power on the processor

data bus input buffers. The processor drives this pin during dynamic FSB frequency

switching.

Input/

Output

DRDY# (Data Ready) is asserted by the data driver on each data transfer,

indicating valid data on the data bus. In a multi-common clock data transfer,

DRDY# may be deasserted to insert idle clocks. This signal must connect the

appropriate pins of both FSB agents.

Input/

Output

DRDY#

Data strobe used to latch in D[63:0]#.

Signals

Associated

Strobe

Input/

Output

D[15:0]#, DINV[0]#

DSTBN[0]#

DSTBN[3:0]#

D[31:16]#, DINV[1]# DSTBN[1]#

D[47:32]#, DINV[2]# DSTBN[2]#

D[63:48]#, DINV[3]# DSTBN[3]#

Data strobe used to latch in D[63:0]#.

Signals

Associated Strobe

D[15:0]#, DINV[0]#

D[31:16]#, DINV[1]#

D[47:32]#, DINV[2]#

D[63:48]#, DINV[3]#

DSTBP[0]#

DSTBP[1]#

DSTBP[2]#

DSTBP[3]#

Input/

Output

DSTBP[3:0]#

Datasheet

77

Package Mechanical Specifications and Pin Information

Table 22.

Name

Signal Description (Sheet 4 of 7)

Type

Description

FERR# (Floating-point Error)/PBE#(Pending Break Event) is a multiplexed signal

and its meaning is qualified with STPCLK#. When STPCLK# is not asserted, FERR#/

PBE# indicates a floating point when the processor detects an unmasked floating-

point error. FERR# is similar to the ERROR# signal on the Intel 387 coprocessor,

and is included for compatibility with systems using MS-DOS*-type floating-point

error reporting. When STPCLK# is asserted, an assertion of FERR#/PBE# indicates

that the processor has a pending break event waiting for service. The assertion of

FERR#/PBE# indicates that the processor should be returned to the Normal state.

When FERR#/PBE# is asserted, indicating a break event, it remains asserted until

STPCLK# is deasserted. Assertion of PREQ# when STPCLK# is active also causes

an FERR# break event.

FERR#/PBE#

Output

For additional information on the pending break event functionality, including

identification of support of the feature and enable/disable information, refer to

Volumes 3A and 3B of the Intel® 64 and IA-32 Architectures Software Developer’s

Manual and the Intel® Processor Identification and CPUID Instruction application

note.

GTLREF determines the signal reference level for AGTL+ input pins. GTLREF should

be set at 2/3 V_CCP. GTLREF is used by the AGTL+ receivers to determine if a signal

is a logical 0 or logical 1.

GTLREF

Input

Input/

Output

HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation

results. Either FSB agent may assert both HIT# and HITM# together to indicate

that it requires a snoop stall, which can be continued by reasserting HIT# and

HITM# together.

HIT#

Input/

Output

HITM#

IERR# (Internal Error) is asserted by a processor as the result of an internal error.

Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the

FSB. This transaction may optionally be converted to an external error signal (e.g.,

NMI) by system core logic. The processor keeps IERR# asserted until the assertion

of RESET#, BINIT#, or INIT#.

IERR#

Output

Input

IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a

numeric error and continue to execute noncontrol floating-point instructions. If

IGNNE# is deasserted, the processor generates an exception on a noncontrol

floating-point instruction if a previous floating-point instruction caused an error.

IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.

IGNNE#

IGNNE# is an asynchronous signal. However, to ensure recognition of this signal

following an Input/Output write instruction, it must be valid along with the TRDY#

assertion of the corresponding Input/Output Write bus transaction.

INIT# (Initialization), when asserted, resets integer registers inside the processor

without affecting its internal caches or floating-point registers. The processor then

begins execution at the power-on Reset vector configured during power-on

configuration. The processor continues to handle snoop requests during INIT#

assertion. INIT# is an asynchronous signal. However, to ensure recognition of this

signal following an Input/Output Write instruction, it must be valid along with the

TRDY# assertion of the corresponding Input/Output Write bus transaction. INIT#

must connect the appropriate pins of both FSB agents.

INIT#

Input

If INIT# is sampled active on the active to inactive transition of RESET#, then the

processor executes its Built-in Self-Test (BIST)

78

Datasheet

Package Mechanical Specifications and Pin Information

Table 22.

Name

Signal Description (Sheet 5 of 7)

Type

Description

LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all APIC Bus

agents. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable

interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR

and NMI are backward compatible with the signals of those names on the Intel®

Pentium® processor. Both signals are asynchronous.

LINT[1:0]

Input

Both of these signals must be software configured via BIOS programming of the

APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC

is enabled by default after Reset, operation of these pins as LINT[1:0] is the default

configuration.

LOCK# indicates to the system that a transaction must occur atomically. This signal

must connect the appropriate pins of both FSB agents. For a locked sequence of

transactions, LOCK# is asserted from the beginning of the first transaction to the

end of the last transaction.

Input/

Output

LOCK#

When the priority agent asserts BPRI# to arbitrate for ownership of the FSB, it

waits until it observes LOCK# deasserted. This enables symmetric agents to retain

ownership of the FSB throughout the bus locked operation and ensure the

atomicity of lock.

PRDY#

PREQ#

Output

Input

Probe Ready signal used by debug tools to determine processor debug readiness.

Probe Request signal used by debug tools to request debug operation of the

processor.

As an output, PROCHOT# (Processor Hot) goes active when the processor

temperature monitoring sensor detects that the processor has reached its

maximum safe operating temperature. This indicates that the processor Thermal

Control Circuit (TCC) has been activated, if enabled. As an input, assertion of

PROCHOT# by the system activates the TCC, if enabled. The TCC remains active

until the system deasserts PROCHOT#.

Input/

Output

PROCHOT#

By default PROCHOT# is configured as an output. The processor must be enabled

via the BIOS for PROCHOT# to be configured as bidirectional.

This signal may require voltage translation on the motherboard.

Processor Power Status Indicator signal. This signal is asserted when the processor

is in both in the Normal state (HFM to LFM) and in lower power states (Deep Sleep

and Deeper Sleep).

PSI#

Output

Input

PWRGOOD (Power Good) is a processor input. The processor requires this signal to

be a clean indication that the clocks and power supplies are stable and within their

specifications. ‘Clean’ implies that the signal remains low (capable of sinking

leakage current), without glitches, from the time that the power supplies are

turned on until they come within specification. The signal must then transition

monotonically to a high state. PWRGOOD can be driven inactive at any time, but

clocks and power must again be stable before a subsequent rising edge of

PWRGOOD.

PWRGOOD

REQ[4:0]#

The PWRGOOD signal must be supplied to the processor; it is used to protect

internal circuits against voltage sequencing issues. It should be driven high

throughout boundary scan operation.

REQ[4:0]# (Request Command) must connect the appropriate pins of both FSB

agents. They are asserted by the current bus owner to define the currently active

transaction type. These signals are source synchronous to ADSTB[0]#.

Input/

Output

Datasheet

79

Package Mechanical Specifications and Pin Information

Table 22.

Name

Signal Description (Sheet 6 of 7)

Type

Description

Asserting the RESET# signal resets the processor to a known state and invalidates

its internal caches without writing back any of their contents. For a power-on

Reset, RESET# must stay active for at least two milliseconds after V_CCand BCLK

have reached their proper specifications. On observing active RESET#, both FSB

agents deasserts their outputs within two clocks. All processor straps must be valid

within the specified setup time before RESET# is deasserted. There is a 55-Ω

(nominal) on die pull-up resistor on this signal.

RESET#

Input

RS[2:0]# (Response Status) are driven by the response agent (the agent

responsible for completion of the current transaction), and must connect the

appropriate pins of both FSB agents.

RS[2:0]#

RSVD

Input

Reserved These pins are RESERVED and must be left unconnected on the board. However, it

/No is recommended that routing channels to these pins on the board be kept open for

Connect possible future use.

SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter

the Sleep state. During Sleep state, the processor stops providing internal clock

signals to all units, leaving only the Phase-Locked Loop (PLL) still operating.

Processors in this state does not recognize snoops or interrupts. The processor

recognizes only assertion of the RESET# signal, deassertion of SLP#, and removal

of the BCLK input while in Sleep state. If SLP# is deasserted, the processor exits

Sleep state and returns to Stop-Grant state, restarting its internal clock signals to

the bus and processor core units. If DPSLP# is asserted while in the Sleep state,

the processor exits the Sleep state and transition to the Deep Sleep state.

SLP#

Input

SMI# (System Management Interrupt) is asserted asynchronously by system logic.

On accepting a System Management Interrupt, the processor saves the current

state and enters System Management Mode (SMM). An SMI Acknowledge

transaction is issued and the processor begins program execution from the SMM

handler.

SMI#

Input

If an SMI# is asserted during the deassertion of RESET#, then the processor

tristates its outputs.

STPCLK# (Stop Clock), when asserted, causes the processor to enter a low power

Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and

stops providing internal clock signals to all processor core units except the FSB and

APIC units. The processor continues to snoop bus transactions and service

interrupts while in Stop-Grant state. When STPCLK# is deasserted, the processor

restarts its internal clock to all units and resumes execution. The assertion of

STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input.

STPCLK#

TCK (Test Clock) provides the clock input for the processor Test Bus (also known as

the Test Access Port).

TCK

TDI

Input

TDI (Test Data In) transfers serial test data into the processor. TDI provides the

serial input needed for JTAG specification support.

TDO (Test Data Out) transfers serial test data out of the processor. TDO provides

the serial output needed for JTAG specification support.

TDO

Output

TEST1, TEST2,

TEST3,

TEST1 and TEST2 must have a stuffing option of separate pulldown resistors to

V

_SS. For the purpose of testability, route the TEST3 and TEST5 signals through a

TEST4,

Input

ground-referenced Zo=55 Ω trace that ends in a via that is near a GND via and is

accessible through an oscilloscope connection.

TEST5,

TEST6

THRMDA

THRMDC

Other

Thermal Diode Anode.

Thermal Diode Cathode.

80

Datasheet

Package Mechanical Specifications and Pin Information

Table 22.

Name

Signal Description (Sheet 7 of 7)

Type

Description

The processor protects itself from catastrophic overheating by use of an internal

thermal sensor. This sensor is set well above the normal operating temperature to

ensure that there are no false trips. The processor stops all execution when the

junction temperature exceeds approximately 125 °C. This is signalled to the

system by the THERMTRIP# (Thermal Trip) pin.

THERMTRIP#

Output

TMS

Input

TMS (Test Mode Select) is a JTAG specification support signal used by debug tools.

TRDY# (Target Ready) is asserted by the target to indicate that it is ready to

receive a write or implicit writeback data transfer. TRDY# must connect the

appropriate pins of both FSB agents.

TRDY#

TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven

low during power on Reset.

TRST#

Input

V_CC

Input

Processor core power supply.

V_SS

Processor core ground node.

V_CCA

V_CCP

V_CCAprovides isolated power for the internal processor core PLL’s.

Processor I/O Power Supply.

V_{CC_SENSE}together with V_{SS_SENSE}are voltage feedback signals to Intel® MVP-6

that control the 2.1-mΩ loadline at the processor die. It should be used to sense

voltage near the silicon with little noise.

V_{CC_SENSE}

VID[6:0]

V_{SS_SENSE}

Output

VID[6:0] (Voltage ID) pins are used to support automatic selection of power supply

voltages (V_CC). Unlike some previous generations of processors, these are CMOS

signals that are driven by the processor. The voltage supply for these pins must be

valid before the VR can supply Vcc to the processor. Conversely, the VR output

must be disabled until the voltage supply for the VID pins becomes valid. The VID

pins are needed to support the processor voltage specification variations. See

Table 2 for definitions of these pins. The VR must supply the voltage that is

requested by the pins, or disable itself.

V_{SS_SENSE}together with V_{CC_SENSE}are voltage feedback signals to Intel MVP-6

that control the 2.1-mΩ loadline at the processor die. It should be used to sense

ground near the silicon with little noise.

§

Datasheet

81

Package Mechanical Specifications and Pin Information

82

Datasheet

Thermal Specifications and Design Considerations

5 Thermal Specifications and

Design Considerations

Maintaining the proper thermal environment is key to reliable, long-term system

operation. A complete thermal solution includes both component and system level

thermal management features. The system/processor thermal solution should be

designed so that the processor remains within the minimum and maximum junction

temperature (Tj) specifications at the corresponding thermal design power (TDP) value

listed in Table 24 through Table 26.

Caution:

Operating the processor outside these limits may result in permanent damage to the

processor and potentially other components in the system.

Table 23.

Symbol

Power Specifications for the 3x00 Celeron Processors

Processor

Number

Thermal Design

Power

Core Frequency & Voltage

Unit

Notes

TDP

T1600

T1700

1.66 GHz

35

W

1, 4, 5, 6, 9

1.83 GHz

Symbol

Parameter

Min Typ Max

Unit

P_AH,

Auto Halt, Stop Grant Power at HFM V_CC

13.9

W

2, 5, 7

P_SGNT

P_SLP

P_DSLP

T_J

Sleep Power at V_CC

13.1

5.5

W

°C

2, 5, 7

2, 5, 8

3, 4

Deep Sleep Power at V_CC

Junction Temperature

0

105

Table 24.

Symbol

Power Specifications for the Intel Celeron Dual-Core Processor - Standard

Voltage

Processor

Number

Thermal Design

Power

Core Frequency & Voltage

Unit

Notes

TDP

T1600

T1700

1.66 GHz

35

W

1, 4, 5, 6, 9

1.83 GHz

Symbol

Parameter

Min Typ Max

Unit

P_AH,

Auto Halt, Stop Grant Power at HFM V_CC

13.5

W

2, 5, 7

P_SGNT

P_SLP

P_DSLP

T_J

Sleep Power at V_CC

12.9

7.7

W

°C

2, 5, 7

2, 5, 8

3, 4

Deep Sleep Power at V_CC

Junction Temperature

0

100

NOTES:

1.

The TDP specification should be used to design the processor thermal solution. The TDP is not the

maximum theoretical power the processor can generate.

2.

Not 100% tested. These power specifications are determined by characterization of the processor currents

at higher temperatures and extrapolating the values for the temperature indicated.

Datasheet

83

Thermal Specifications and Design Considerations

3.

4.

As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic

mode is used to indicate that the maximum T_Jhas been reached. Refer to Section 5.1 for details.

The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within

specifications.

At Tj of 100 ^oC

At Tj of 50 ^oC

At Tj of 35 ^oC

512-KB L2 cache

5.

6.

7.

8.

Table 25.

Power Specifications for the Ultra Low Voltage Dual-Core 1M Cache Intel

Celeron (SFF) Genuine Intel Processor

Processor

Number

Thermal Design

Power

Symbol

Core Frequency

Unit

Notes

TDP

SU2300

1.2 GHz

Parameter

10

Min Typ Max

2.9

W

Unit

W

1, 4, 5

Notes

2, 6

Symbol

P_AH,

Auto Halt, Stop Grant Power

P_SGNT

P_SLP

Sleep Power

2.9

1.3

0.6

W

°C

2, 6

2,7

P_DSLP

P_DPRSLP

T_J

Deep Sleep Power

Deeper Sleep Power

Junction Temperature

2, 7

3,4

0

100

NOTES:

1.

2.

3.

4.

The TDP specification should be used to design the processor thermal solution. The TDP is not the

maximum theoretical power the processor can generate.

Not 100% tested. These power specifications are determined by characterization of the processor currents

at higher temperatures and extrapolating the values for the temperature indicated.

As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic

mode is used to indicate that the maximum T_Jhas been reached. Refer to Section 5.1 for more details.

The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within

specifications.

5.

6.

At Tj of 100 ^oC

At Tj of 50 °C

7.

At Tj of 35 ^oC

5.1

Monitoring Die Temperature

The processor incorporates three methods of monitoring die temperature:

• Thermal Diode

• Intel Thermal Monitor

• Digital Thermal Sensor

84

Datasheet

Thermal Specifications and Design Considerations

5.1.1

Thermal Diode

The processor incorporates an on-die PNP transistor whose base emitter junction is

used as a thermal diode, with its collector shorted to ground. The thermal diode can be

read by an off-die analog/digital converter (a thermal sensor) located on the

motherboard or a stand-alone measurement kit. The thermal diode may be used to

monitor the die temperature of the processor for thermal management or

instrumentation purposes but is not a reliable indication that the maximum operating

temperature of the processor has been reached. When using the thermal diode, a

temperature offset value must be read from a processor MSR and applied. See

Section 5.1.2 for more details. Please see Section 5.1.3 for thermal diode usage

recommendation when the PROCHOT# signal is not asserted.

The reading of the external thermal sensor (on the motherboard) connected

to the processor thermal diode signals does not reflect the temperature of the

hottest location on the die. This is due to inaccuracies in the external thermal

sensor, on-die temperature gradients between the location of the thermal diode and the

hottest location on the die, and time based variations in the die temperature

measurement. Time-based variations can occur when the sampling rate of the thermal

diode (by the thermal sensor) is slower than the rate at which the T_Jtemperature can

change.

Offset between the thermal diode-based temperature reading and the Intel Thermal

Monitor reading may be characterized using the Intel Thermal Monitor’s Automatic

mode activation of the thermal control circuit. This temperature offset must be taken

into account when using the processor thermal diode to implement power management

events. This offset is different than the diode Toffset value programmed into the

processor Model Specific Register (MSR).

Table 26 to Table 29 provide the diode interface and specifications. The diode model

parameters apply to the traditional thermal sensors that use the diode equation to

determine the processor temperature. Transistor model parameters have been added

to support thermal sensors that use the transistor equation method. The Transistor

model may provide more accurate temperature measurements when the diode ideality

factor is closer to the maximum or minimum limits. Contact your external sensor

supplier for recommendations. The thermal diode is separate from the Intel Thermal

Monitor’s thermal sensor and cannot be used to predict the behavior of the Intel

Thermal Monitor.

Table 26.

Thermal Diode Interface

Signal Name

Pin/Ball Number

Signal Description

THERMDA

THERMDC

A24

A25

Thermal diode anode

Thermal diode cathode

Datasheet

85

Thermal Specifications and Design Considerations

Table 27.

Thermal Diode Parameters Using Diode Model

Symbol

Parameter

Min

Typ

Max

Unit

Notes

I_FW

n

Forward Bias Current

Diode Ideality Factor

Series Resistance

5

200

1.050

6.24

µA

1

1.000

2.79

1.009

4.52

2, 3, 4

2, 3, 5

R_T

Ω

NOTES:

1.

Intel does not support or recommend operation of the thermal diode under reverse bias.

Intel does not support or recommend operation of the thermal diode when the processor

power supplies are not within their specified tolerance range.

Characterized across a temperature range of 50-100°C.

Not 100% tested. Specified by design characterization.

The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by

the diode equation:

2.

3.

4.

qV /nkT

I_FW= I_S* (e

D

–1)

where I_S= saturation current, q = electronic charge, V_D= voltage across the diode, k =

Boltzmann Constant, and T = absolute temperature (Kelvin).

5.

The series resistance, R_T, is provided to allow for a more accurate measurement of the

junction temperature. R_T, as defined, includes the lands of the processor but does not

include any socket resistance or board trace resistance between the socket and the

external remote diode thermal sensor. R_Tcan be used by remote diode thermal sensors

with automatic series resistance cancellation to calibrate out this error term. Another

application is that a temperature offset can be manually calculated and programmed into

an offset register in the remote diode thermal sensors as exemplified by the equation:

T_error= [R_T* (N-1) * I_FWmin] / [nk/q * ln N]

where T_error= sensor temperature error, N = sensor current ratio, k = Boltzmann

Constant, q = electronic charge.

86

Datasheet

Thermal Specifications and Design Considerations

Table 28.

Thermal Diode Parameters Using Transistor Model

Symbol

Parameter

Min

Typ

Max

Unit

Notes

I_FW

I_E

Forward Bias Current

Emitter Current

5

200

μA

1,2

1

n_Q

Transistor Ideality

0.997

0.3

1.001

4.52

1.005

0.760

6.24

3,4,5

3,4

3,6

Beta

R_T

Series Resistance

2.79

Ω

NOTES:

1.

2.

3.

4.

5.

Intel does not support or recommend operation of the thermal diode under reverse bias.

Same as I_FWin Table 27.

Characterized across a temperature range of 50-100°C.

Not 100% tested. Specified by design characterization.

The ideality factor, nQ, represents the deviation from ideal transistor model behavior as

exemplified by the equation for the collector current:

qV /n kT

I_C= I_S* (e

BE

Q

–1)

where I_S= saturation current, q = electronic charge, V_BE= voltage across the transistor

base emitter junction (same nodes as VD), k = Boltzmann Constant, and T = absolute

temperature (Kelvin).

6.

The series resistance, R_T, provided in the Diode Model Table (Table 27) can be used for


型号：	AV80577UG0091M/SLGSB
厂家：	INTEL
描述：	RISC Microprocessor, 64-Bit, 1200MHz, CMOS, PBGA956
文件：	总98页 (文件大小：1636K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AV80577UG0091M/SLGSB [INTEL]

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