AU80610006240AA_技术文档

Intel® Atom™ Processor 230^∆

Series

Datasheet

April 2010

Document Number: 319977-003

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∆ Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor

family, not across different processor families. Click here for details

Intel® 64 requires a computer system with a processor, chipset, BIOS, operating system, device drivers, and applications

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2

Datasheet

Contents

1

Introduction.....................................................................................................6

1.1

1.2

1.3

Intel® Atom™ Processor 230 Series Features.............................................6

Terminology ..........................................................................................7

Reference Documents .............................................................................8

2

Low Power Features ..........................................................................................9

2.1 Clock Control and Low-power States .........................................................9

2.1.1

2.1.2

2.1.3

Thread Low-power State Descriptions.........................................10

Package Low-power State Descriptions.......................................11

Front Side Bus........................................................................11

3

Electrical Specifications....................................................................................12

3.1

3.2

3.3

FSB and GTLREF ..................................................................................12

Power and Ground Pins .........................................................................12

Decoupling Guidelines...........................................................................12

3.3.1

3.3.2

VCCP Decoupling.....................................................................13

FSB AGTL+ Decoupling ............................................................13

3.4

3.5

3.6

3.7

3.8

3.9

3.10

3.11

3.12

Voltage Identification and Power Sequencing............................................13

Catastrophic Thermal Protection.............................................................15

Reserved and Unused Pins.....................................................................15

FSB Frequency Select Signals (BSEL[2:0])...............................................16

FSB Signal Groups................................................................................16

CMOS Asynchronous Signals..................................................................17

3.10 Maximum Ratings .........................................................................17

Processor DC Specifications ...................................................................18

AGTL+ FSB Specifications......................................................................22

4

5

Package Mechanical Specifications and Ball Information........................................23

4.1

Package Mechanical Specifications ..........................................................23

4.1.1

4.1.2

4.1.3

4.1.4

Package Mechanical Drawings ...................................................23

Package Loading Specifications .................................................24

Processor Mass Specifications ...................................................24

Processor Pinout Assignment ....................................................24

4.2

Signal Description ................................................................................30

Thermal Specifications and Design Considerations ...............................................38

5.1 Thermal Specifications ..........................................................................38

5.1.1

5.1.2

5.1.3

5.1.4

5.1.5

Thermal Diode........................................................................39

Intel® Thermal Monitor............................................................41

Digital Thermal Sensor.............................................................42

Out of Specification Detection ...................................................43

PROCHOT# Signal Pin..............................................................43

6

Debug Tools Specifications...............................................................................45

Datasheet

3

Figures

Tables

Figure 1. Thread Low-power States .....................................................................9

Figure 2. Package Mechanical Drawing................................................................23

Figure 3. Pinout Diagram (Top View, Left Side) ...................................................25

Figure 4. Pinout Diagram (Top View, Right Side) .................................................26

Table 1. Coordination of Thread Low-power States at the Package Level .................10

Table 2. Voltage Identification Definition ............................................................13

Table 3. Processor VID Pin to VRD11 VID Pin Mapping..........................................15

Table 4. BSEL[2:0] Encoding for BCLK Frequency ................................................16

Table 5. FSB Pin Groups...................................................................................16

Table 6. Processor Absolute Maximum Ratings ....................................................18

Table 7. Voltage and Current Specifications for the Intel® Atom™ Processor ...........19

Table 8. FSB Differential BCLK Specifications ......................................................20

Table 9. AGTL+/CMOS Signal Group DC Specifications .........................................20

Table 10. Legacy CMOS Signal Group DC Specifications........................................21

Table 11. Open Drain Signal Group DC Specifications...........................................22

Table 13. Pinout Arranged By Signal Name .........................................................27

Table 14. Signal Description..............................................................................30

Table 15. Power Specifications for the Processor..................................................39

Table 16. Thermal Diode Interface.....................................................................40

Table 17. Thermal Diode Parameters using Transistor Model .................................40

4

Datasheet

Revision History

Revision

Number

Description

Revision

Date

001

002

003

• Initial Release

• Update pin-map

• Add SSSE3

June 2008

February 2009

April 2010

• Changed A[35:2] to A[32:2]

• Changed Vboot

• Changed Ron and Rodt

• Removed L2 Dynamic Cache Sizing

• Updated Table 7: Removed dI/dt details from the table

§

Datasheet

5

Introduction

1 Introduction

The Intel® Atom™ Single Core processor 230 sequence is built on Hi-k 45-nanometer

process technology. In Nettop’08 platform, Intel Atom Single Core processor 230

sequence supports SiS as well as Intel chipsets. This document contains electrical,

mechanical and thermal specifications for the processor.

Note: In this document, the Intel Atom Single Core processor 230 series will be referred to as

the “processor”. Intel chipsets are referred to as GMCH and ICH respectively.

Note: In is document, the Intel Atom processor 200 series is replaced by Intel Atom

Processor 230 Series.

1.1

Intel® Atom™ Processor 230 Series Features

•

Available at 1.6 GHz,

On die, primary 32-kB instructions cache and 24-KB write-back data cache

533-MHz Source-Synchronous front side bus (FSB)

Threading enabled

On-die 512-KB, 8-way L2 cache

•

Support for IA 32-bit and Intel^®64 architecture

Streaming SIMD Extensions 2 and 3 (SSE2 and SSE3) support

Micro-FCBGA packaging technologies

Thermal management support via TM1

FSB Lane Reversal for flexible routing

Supports C0 and C1 states only

L2 Dynamic Cache Sizing

Execute Disable Bit support for enhanced security

This processor series represents a new family of processors designed from the

ground- up on a ground-breaking new low-power microarchitecture. It is

manufactured on industry-leading 45 nm process with Hi-K Metal Gate technology.

This processor series enables a new class of simple and affordable internet-centric

computers called “Entry Level Desktop Platforms” that is best suited for applications

focused on internet usage models—communicate, listen, watch, play, share, and learn.

6

Datasheet

Introduction

1.2

Terminology

Term

Definition

#

A “#” symbol after a signal name refers to an active low signal,

indicating a signal is in the active state when driven to a low level. For

example, when RESET# is low, a reset has been requested.

Conversely, when NMI is high, a nonmaskable interrupt has occurred.

In the case of signals where the name does not imply an active state

but describes part of a binary sequence (such as address or data), the

“#” symbol implies that the signal is inverted. For example, D[3:0] =

“HLHL” refers to a hex ‘A’, and D[3:0]#

= “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic

level).

Front Side Bus

(FSB)

Refers to the interface between the processor and system core logic

(also known as the GMCH chipset components).

AGTL+

Advanced Gunning Transceiver Logic. Used to refer to Assisted GTL+

signaling technology on some Intel processors.

CMOS

Complementary metal-Oxide semiconductor.

Storage

Refers to a non-operational state. The processor may be installed in a

platform, in a tray, or loose. Processors may be sealed in packaging or

exposed to free air. Under these conditions, processor landings should

not be connected to any supply voltages, have any I/Os biased or

receive any clocks. Upon exposure to “free air” (i.e., unsealed

packaging or a device removed from packaging material) the

processor must be handled in accordance with moisture sensitivity

labeling (MSL) as indicated on the packaging material.

Conditions

Enhanced Intel

SpeedStep®

Technology

Technology that provides power management capabilities to low

power devices.

Processor Core

Processor core die with integrated L1 and L2 cache. All AC timing and

signal integrity specifications are at the pads of the processor core.

Intel® 64

64-bit memory extensions to the IA-32 architecture.

Technology

Intel® Virtualization

Technology

Processor virtualization which when used in conjunction with Virtual

Machine Monitor software enables multiple, robust independent

software environments inside a single platform.

TDP

VCC

VTT

VR

Thermal Design Power

The processor core power supply

FSB AGTL+ termination voltage with respect to VSS

Voltage Regulator

VSS

The processor ground

Datasheet

7

Introduction

1.3

Reference Documents

Document

Document Number

www.intel.com/design/pr

ocessor/specupdt/31997

8.pdf

Intel® Atom™ Processors 200 Series Specification Update

www.intel.com/design/pr

ocessor/designex/31997

9.pdf

Intel® Atom™ Processors 200 Series Thermal and Mechanical

Design Guidelines

http://www.intel.com/de

sign/processor/applnots/

241618.htm

AP-485, Intel® Processor Identification and CPUID Instruction

Application Note

http://www.intel.com/de

sign/processor/applnots/

313214.htm

Voltage Regulator-Down (VRD) 11.0 - Processor Power Delivery

Design Guidelines

Intel® 64 and IA-32 Architectures Software Developer's Manuals

Volume 1: Basic Architecture

http://www.intel.com/pr

oducts/processor/manual

s/index.htm

Volume 2A: Instruction Set Reference, A-M

Volume 2B: Instruction Set Reference, N-Z

Volume 3A: System Programming Guide

Volume 3B: System Programming Guide

§

8

Datasheet

Low Power Features

2 Low Power Features

2.1

Clock Control and Low-power States

The processor supports low power states at the thread level and the package level. A

thread may independently enter the C1/AutoHALT and C1/MWAIT low power states.

When both threads are in a common low-power state the central power management

logic ensures the entire processor enters the respective package low power state by

initiating a P_LVLx I/O read to the chipset.

The processor implements two software interfaces for requesting low power states,

MWAIT instruction extensions with sub-state hints and P_LVLx reads to the ACPI

P_BLK register block mapped in the processor’s I/O address space. The P_LVLx I/O

reads are converted to equivalent MWAIT C-state requests inside the processor and do

not directly result in I/O reads on the processor FSB. The monitor address does not

need to be setup before using the P_LVLx I/O read interface. The sub-state hints used

for each P_LVLx read can be configured in a software programmable MSR.

Figure 2-1 shows the thread low-power states. Table 2-1 provides a mapping of

thread low-power states to package low power states.

Figure 1. Thread Low-power States

Datasheet

9

Low Power Features

Table 1. Coordination of Thread Low-power States at the Package Level

Thread State

Package State2

C0

C11

C0

Normal

C11

Normal

AutoHalt

NOTES:

1.

2.

AutoHALT or MWAIT/C1.

To enter a package state, both threads must be in a common low power state. If the

threads are not in a common low power state, the package state will resolve to the

highest power C state.

2.1.1

Thread Low-power State Descriptions

2.1.1.1

Thread C0 State

This is the normal operating state for threads in the processor.

2.1.1.2

2.1.1.2 Thread C1/AutoHALT Powerdown State

C1/AutoHALT is a low-power state entered when a thread executes the HALT

instruction. The processor thread will transition to the C0 state upon occurrence of

SMI#, INIT#, LINT[1:0] (NMI, INTR), or FSB interrupt messages. RESET# will cause

the processor to immediately initialize itself.

A System Management Interrupt (SMI) handler will return execution to either Normal

state or the AutoHALT Powerdown state. See the Intel® 64 and IA-32 Architectures

Software Developer's Manuals, Volume 3A/3B: System Programmer's Guide for more

information.

While in AutoHALT Powerdown state, the processor threads will process bus snoops

and snoops from the other thread. The processor will enter a snoopable sub-state (not

shown in Figure 2-1) to process the snoop and then return to the AutoHALT

Powerdown state.

2.1.1.3

Thread C1/MWAIT Powerdown State

C1/MWAIT is a low-power state entered when the processor thread executes the

MWAIT(C1) instruction. Processor behavior in the MWAIT state is identical to the

AutoHALT state except that Monitor events can cause the processor to return to the

C0 state. See the Intel® 64 and IA-32 Architectures Software Developer's Manuals,

Volume 2A: Instruction Set Reference, A-M and Volume 2B: Instruction Set Reference,

N-Z, for more information.

10

Datasheet

Low Power Features

2.1.2

Package Low-power State Descriptions

Note: The following state descriptions assume that both threads are in the a common low

power state. For cases when only one thread is in a low power state, please see

Section 2.1.1.

2.1.2.1

Normal State

This is the normal operating state for the processor. The processor remains in the

Normal state when the threads are in the C0, C1/AutoHALT, or C1/MWAIT state.

2.1.3

Front Side Bus

The Intel® Atom™ processor has only one signaling mode, where the data and

address busses and the strobe signals are operating in GTL mode. The reason to use

GTL is to improve signal integrity.

§

Datasheet

11

Electrical Specifications

3 Electrical Specifications

This chapter contains signal group descriptions, absolute maximum ratings, voltage

identification, and power sequencing. The chapter also includes DC specifications.

3.1

FSB and GTLREF

Intel® Atom™ processor supports two kinds of signaling protocol: Complementary

Metal Oxide Semiconductor (CMOS), and Advanced Gunning Transceiver Logic

(AGTL+). For FSB data and address bus, only AGTL+ is used.

The termination voltage level for the Intel® Atom™ processor CMOS and AGTL+

signals is V_TT= 1.10 V (nominal). Due to speed improvements to data and address

bus, signal integrity and platform design methods have become more critical than with

previous processor families.

The CMOS sideband signals are listed in Table 3-5.

The AGTL+ inputs, including the sideband signals listed in Table 3-5, require a

reference voltage (GTLREF) that is used by the receivers to determine if a signal is a

logical 0 or a logical 1. GTLREF must be generated on the system board. Termination

resistors are provided on the processor silicon and are terminated to its I/O voltage

(VTT). The appropriate chipset will also provide on-die termination, thus eliminating

the need to terminate the bus on the system board for most AGTL+ signals.

The AGTL+ bus depends on incident wave switching. Timing calculations for AGTL+

signals are based on flight time as opposed to capacitive deratings. Analog signal

simulation of the FSB, including trace lengths, is highly recommended when designing

a system.

3.2

Power and Ground Pins

For clean, on-chip power distribution, the processor will have a large number of VTT

(FSB AGTL+ reference voltage), VCCP (power) and VSS (ground) inputs. All power

pins must be connected to VCCP power planes while all VSS pins must be connected

to system ground planes. Use of multiple power and ground planes is recommended

to reduce I*R drop. The processor VCCP pins must be supplied the voltage stated in

Table 3-7

3.3

Decoupling Guidelines

Due to its large number of transistors and high internal clock speeds, the processor is

capable of generating large average current swings between low and full power states.

This may cause voltages on power planes to sag below their minimum values if bulk

decoupling is not adequate. Larger bulk storage, supply current during longer lasting

changes in current demand by the component, such as coming out of an idle condition.

12

Datasheet

Electrical Specifications

Similarly, they act as a storage well for current when entering an idle condition from a

running condition. Care must be taken in the board design to ensure that the voltage

provided to the processor remains within the specifications listed in Table 3-7. Failure

to do so can result in timing violations or reduced lifetime of the component. For further

information and design guidelines, refer to the Voltage Regulator-Down (VRD) 11.0

Processor Power Delivery Design Guidelines.

3.3.1

VCCP Decoupling

V_CCPregulator solutions need to provide bulk capacitance with a low Effective Series

Resistance (ESR) and keep a low interconnect resistance from the regulator to the

socket. Bulk decoupling for the large current swings when the part is powering on, or

entering/exiting low-power states, must be provided by the voltage regulator solution

For more details on decoupling recommendations, Refer to the Voltage Regulator-Down

(VRD) 11.0 Processor Power Delivery Design Guidelines.

3.3.2

FSB AGTL+ Decoupling

The processor integrates signal termination on the die. Decoupling must also be

provided by the system motherboard for proper AGTL+ bus operation.

3.4

Voltage Identification and Power Sequencing

Table 2. Voltage Identification Definition

VID6

VID5 VID4 VID3 VID2 VID1

VID0

VCC (V)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1.2000

1.1875

1.1750

1.1625

1.1500

1.1375

1.1250

1.1125

1.1000

1.0875

1.0750

1.0625

1.0500

1.0375

1.0250

1.0125

0.9375

0.9250

0.9125

Datasheet

13

Electrical Specifications

VID6

VID5 VID4 VID3 VID2 VID1

VID0

VCC (V)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.9000

0.8875

0.8750

0.8625

0.8500

0.8375

0.8250

0.8125

0.8000

0.7875

0.7750

0.7625

0.7500

1.0000

0.9875

0.9750

0.9625

0.9500

0.7375

0.7250

0.7125

0.7000

The VID specification for the processor is defined by the RS - Voltage Regulator-Down

(VRD) 11.0 Processor Power Delivery Design Guidelines.

The processor uses seven voltage identification pins, VID[6:0], to support automatic

selection of power supply voltages. The VID pins for processor are CMOS outputs

driven by the processor VID circuitry. Table 3-2 specifies the voltage level

corresponding to the state of VID[6:0]. A “1” in this refers to a high-voltage level and

a “0” refers to low-voltage level. For more details about VR design to support the

processor power supply requirements, Refer to the Voltage Regulator-Down (VRD)

11.0 Processor Power Delivery Design Guidelines.

VRD11 has 8 VID pins (VID[7:0]) compared to 7 VID pins for the processor. VRD11

VID[n] should be connected to processor VID[n-1]. VRD11 VID[0] should be tied to

Vss.

14

Datasheet

Electrical Specifications

Table 3. Processor VID Pin to VRD11 VID Pin Mapping

Processor VID Pin

Map to VRD11 VID Pin

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0 (tie to ground)

Power source characteristics must be stable whenever the supply to the voltage

regulator is stable.

3.5

Catastrophic Thermal Protection

The processor supports the THERMTRIP# signal for catastrophic thermal protection.

An external thermal sensor should also be used to protect the processor and the

system against excessive temperature. Even with the activation of THERMTRIP#,

which halts all processor internal clocks and activities, leakage current can be high

enough such that the processor cannot be protected in all conditions without the

removal of power to the processor. If the external thermal sensor detects a

catastrophic processor temperature of 125 °C (maximum), or if the THERMTRIP#

signal is asserted, the VCC supply to the processor must be turned off within 500 ms

to prevent permanent silicon damage due to thermal runaway of the processor.

THERMTRIP functionality is not ensured if the PWRGOOD signal is not asserted.

3.6

Reserved and Unused Pins

All RESERVED (RSVD) pins must remain unconnected. Connection of these pins to

VCCP, VSS, or to any other signal (including each other) can result in component

malfunction or incompatibility with future processors. See section Chapter 4.2 for a

pin listing of the processor and the location of all RSVD pins.

For reliable operation, always connect unused inputs or bidirectional signals to an

appropriate signal level. Unused active low AGTL+ inputs may be left as no connects if

AGTL+ termination is provided on the processor silicon. Unused active high inputs

should be connected through a resistor to ground (VSS). Unused outputs can be left

unconnected.

Datasheet

15

Electrical Specifications

3.7

FSB Frequency Select Signals (BSEL[2:0])

Only 133 MHz is supported by the processor. The BSEL[2:0] signals need to be set

accordingly to select the frequency of the processor input clock (BCLK[1:0]). These

signals should be connected to the clock chip and the appropriate chipset on the

platform. The BSEL encoding for BCLK[1:0] is shown in Table 3-4.

Table 4. BSEL[2:0] Encoding for BCLK Frequency

BSEL[2]

BSEL[1]

BSEL[0]

BCLK Frequency

L

H

133 MHz

NOTE: All other bus selections reserved.

3.8

FSB Signal Groups

To simplify the following discussion, the FSB signals have been combined into groups

by buffer type. AGTL+ input signals have differential input buffers, which use GTLREF

as a reference level. In this document, the term “AGTL+ Input” refers to the AGTL+

input group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+

Output” refers to the AGTL+ output group as well as the AGTL+ I/O group when

driving.

With the implementation of a source synchronous data bus comes the need to specify

two sets of timing parameters. One set is for common clock signals which are

dependent upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second

set is for the source synchronous signals which are relative to their respective strobe

lines (data and address) as well as the rising edge of BCLK0. Asynchronous signals are

still present (A20M#, IGNNE#, etc.) and can become active at any time during the

clock cycle. Table 3-5 identifies which signals are common clock, source synchronous,

and asynchronous.

Table 5. FSB Pin Groups

Signal Group

Type

Signals1

AGTL+ Common Clock Synchronous to BPRI#, DEFER#, PREQ#, RESET#, RS[2:0]#, TRDY#,

Input BCLK[1:0] DPWR#

AGTL+ Common Clock Synchronous to ADS#, BNR#, BPM[3:0]#, BR0#, DBSY#, DRDY#, HIT#,

I/O

BCLK[1:0]

HITM#, LOCK#, PRDY#

Signals Associated Strobe REQ[4:0]#, A[16:3]#

ADSTB0# A[32:17]#, ADSTB1#

AGTL+ Source

Synchronous I/O

Synchronous to

assoc. strobe

D[15:0]#, DBI0#, DINV[0]# DSTBP0#, DSTBN0#

D[31:16]#, DBI1#, DINV[0]# DSTBP1#, DSTBN1#

D[47:32]#, DBI2#, DINV[0]# DSTBP2#, DSTBN2#

D[63:48]#, DBI3#, DINV[0]# DSTBP3#, DSTBN3#

16

Datasheet

Electrical Specifications

Signal Group

Type

Signals1

Synchronous to

BCLK[1:0]

AGTL+ Strobes

CMOS Input

ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#

IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PWRGOOD,

SMI#

Asynchronous

Open Drain Output

Open Drain I/O

CMOS Output

Asynchronous FERR#, IERR#, THERMTRIP#

Asynchronous PROCHOT#3

Asynchronous VID[6:0], BSEL[2:0]

Synchronous to

TCK

CMOS Input

TCK, TDI, TMS, TRST#

Synchronous to

Open Drain Output

FSB Clock

TDO

TCK

Clock

BCLK[1:0]

COMP[3:0], HFPLL (old name is DBR#2), GTLREF,

TEST2/Dclk, TEST1/Aclk, THERMDA, THERMDC, VCCA,

VCCP, VTT, VCC_SENSE, VSS, VSS_SENSE, VCCQ[1:0]

Power/Other

NOTES:

1.

1. In processor systems where there is no debug port implemented on the system

board, these signals are used to support a debug port interposer. In systems with the

debug port implemented on the system board, these signals are no connects.

2. PROCHOT# signal type is open drain output and CMOS input.

3. On die termination differs from other AGTL+ signals, refer to your Platform Design

Guidelines for up to day recommendations.

2.

3.

3.9

CMOS Asynchronous Signals

CMOS input signals are shown in Table 3-5. Legacy output FERR#, IERR# and other

non- AGTL+ signals (THERMTRIP# and PROCHOT#) use Open Drain output buffers.

These signals do not have setup or hold time specifications in relation to BCLK[1:0].

However, all of the CMOS signals are required to be asserted for more than 4 BCLKs

for the processor to recognize them. See Section 3.11 and Section for the DC and AC

specifications for the CMOS signal groups.

3.10

3.10Maximum Ratings

Table 3-6 specifies absolute maximum and minimum ratings. Within functional

operation limits, functionality and long-term reliability can be expected.

At conditions outside functional operation condition limits, but within absolute

maximum and minimum ratings, neither functionality nor long term reliability can be

expected. If a device is returned to conditions within functional operation limits after

having been subjected to conditions outside these limits, but within the absolute

maximum and minimum ratings, the device may be functional, but with its lifetime

degraded depending on exposure to conditions exceeding the functional operation

condition limits.

Datasheet

17

Electrical Specifications

At conditions exceeding absolute maximum and minimum ratings, neither

functionality nor long term reliability can be expected. Moreover, if a device is

subjected to these conditions for any length of time then, when returned to conditions

within the functional operating condition limits, it will either not function or its

reliability will be severely degraded.

Although the processor contains protective circuitry to resist damage from static

electric discharge, precautions should always be taken to avoid high static voltages or

electric fields.

Table 6. Processor Absolute Maximum Ratings

Symbol

TSTORAGE

Parameter

Min

Max

Unit

Notes1,5

Processor Storage Temperature

-40

85

°C

2,3,4

Any Processor Supply Voltage with

Respect to VSS

VCC

-0.3

-0.1

1.55

V

6

AGTL+ Buffer DC Input Voltage with

Respect to VSS

VinAGTL+

CMOS Buffer DC Input Voltage with

Respect to VSS

VinAsynch_CMOS

NOTES:

1.

1. For functional operation, all processor electrical, signal quality, mechanical and

thermal specifications must be satisfied.

2.

Storage temperature is applicable to storage conditions only. In this scenario, the

processor must not receive a clock, and no lands can be connected to a voltage bias.

Storage within these limits will not affect the long term reliability of the device. For

functional operation, refer to the processor case temperature specifications.

This rating applies to the processor and does not include any tray or packaging.

Failure to adhere to this specification can affect the long term reliability of the processor.

Overshoot and undershoot guidelines for input, output, and I/O signals are in Chapter 4.

The V_CCmax supported by the process is 1.2 V but the parameter can change (burnin

3.

4.

5.

6.

voltage is higher).

3.11

Processor DC Specifications

The processor DC specifications in this section are defined at the processor core

(pads) unless noted otherwise. See Chapter 4 for the pin signal definitions and signal

pin assignments. Most of the signals on the FSB are in the AGTL+ signal group. The

DC specifications for these signals are listed in Table 3-9. DC specifications for the

CMOS group are listed in Table 3-10.

Table 3-9 through Table 3-11 list the DC specifications for the Intel® Atom™

processor and are valid only while meeting specifications for junction temperature,

clock frequency, and input voltages. Unless specified otherwise, all specifications for

the Intel® Atom™ processor are at TJ = 90°C. Care should be taken to read all notes

associated with each parameter.

18

Datasheet

Electrical Specifications

Table 7. Voltage and Current Specifications for the Intel® Atom™ Processor

Symbol

FSB

Parameter

Min

Typ

Max

Unit

Notes6

BCLK Frequency

132.6

133.33

133.5

MHz

Frequency

FSB AGTL+ termination voltage with respect to

VSS

VTT

1.05

1.10

1.5

1.15

V

VCCP

Vcc Core voltage with respect to VSS

PLL Supply voltage

0.7

1.425

1.10

1.2

1.575

1.2

V

7,8

VCCA

VCC BOOT

Default VCCP voltage for initial power up

10

3

ICC for VTT supply after VCCP stable

ICC for VTT supply at startup

1.5

2.5

ITT

A

ICC for Intel® Atom™ Processors

ICCDES

4

3

Recommended Design Target (Estimated)

ICC for Intel® Atom™ Processors

Processor

Core Frequency

ICC

IAH

Number

1.6 GHz @ VCCP (AVID

230

4

A

1, 2

controlled)

ICC Auto-Halt

2.0

A

ICCA

ICC for VCCA Supply

130

mA

NOTES:

1.

2.

3.

Specified at 90°C T .

Specified at the nominal

J

V

.

CCP

Refer to the RS - Voltage Regulator-Down (VRD) 11.0 - Processor Power Delivery Design Guidelines for

design target capability.

4.

5.

Measured at the bulk capacitors on the motherboard.

Based on simulations and averaged over the duration of any change in current. Specified by design/

characterization at nominal V_CCP. Not 100% tested.

6.

7.

Unless otherwise noted, all specifications in this table are based on estimates and simulations or

empirical data. These specifications will be updated with characterized data from silicon measurements

at a later date.

V_CCPis determined by processor VID[6:0] pins. Each processor is programmed with a maximum valid

voltage identification value (VID), which is set at manufacturing and cannot be altered. Individual

maximum VID values are calibrated during manufacturing such that two processors at the same

frequency may have different settings within VID range. Refer to VID Table 3-2 for the specific voltages

corresponding to VID[6:0] codes.

This is the Vccp range, not the absolute voltage set for the core. The Vccp tolerance should be

+/- 50 mV, inclusive of ripple, VR tolerance and transient (droop and overshoot).

Since CPU is soldered down with no loadline and no dynamic VID, there is no “socket load line

slope(SKT_LL)”; “socket load line tolerance band” but only “Tolerance Band (TOB)” of 50mV; no

“maximum overshoot above VID (OS_AMP)”; no “maximum overshoot time duration above VID

(OS_TIME)”; no “peak to peak ripple amplitude (RIPPLE)”; no “thermal compensation voltage drift

(THERMAL_DRIF)”; no “maximum DC test (Current I_DC_MAX)”; no “minimum DC test (Current

8.

9.

Datasheet

19

Electrical Specifications

I_DC_MIN)”; “Voltage Regulator Thermal Design Current (VR_TDC_)” of 3.64A; “current step rise time

(I_RISE) of 2.5 A/us”.

±50 mV tolerance

10.

Table 8. FSB Differential BCLK Specifications

Symbol

Parameter

Min

Typ

Max

Unit

Figure

Notes1

VIH

VIL

Input High Voltage

Input Low Voltage

Crossing Voltage

1.15

-0.3

0.55

140

V

7, 8

2, 7, 9

2, 7, 5

6

VCROSS

0.3

V

ΔVCROSS Range of Crossing Points

mV

µA

pF

VSWING

ILI

Differential Output Swing

Input Leakage Current

Pad Capacitance

300

-5

+5

3

Cpad

1.2

1.45

2.0

4

NOTES:

1.

1. Unless otherwise noted, all specifications in this table apply to all processor

frequencies.

2.

Crossing Voltage is defined as absolute voltage where rising edge of BCLK0 is equal to

the falling edge of BCLK1.

3.

4.

5.

6.

7.

8.

9.

For Vin between 0 V and VIH.

Cpad includes die capacitance only. No package parasitics are included.

ΔVCROSS is defined as the total variation of all crossing voltages as defined in note 2.

Measurement taken from differential waveform.

Measurement taken from single-ended waveform.

“Steady state” voltage, not including Overshoots or Undershoots.

Only applies to the differential rising edge (clock rising and clock# falling).

Table 9. AGTL+/CMOS Signal Group DC Specifications

Symbol

VTT

Parameter

I/O Voltage

Min

Typ

Max

Unit

Notes1

1.05

1.10

1.15

V

11

GTLREF

RCOMP

GTL Reference Voltage

2/3 VTT

V

5, 12,13

9, 11

0.62 VTT

Compensation Resistor

COMP[0] & COMP[2]

24.75

49.5

25

25.25

50.5

Ω

COMP[1] & COMP[3]

Termination Resistor

50

55

RODT

VIH

Ω

V

Ω

10

3,5

2,4

5

Input High Voltage

GTLREF+0.10

-0.10

VTT

0

VTT+0.10

GTLREF-0.10

VTT

VIL

Input Low Voltage

VOH

RTT

Output High Voltage

Termination Resistance

GTL Buffer on Resistance

VTT-0.10

45

VTT

50

55

6

RON (GTL

mode)

8.5

ILI

Input Leakage Current

±100

µA

7

20

Datasheet

Electrical Specifications

Symbol

Cpad

Parameter

Min

Typ

Max

Unit

Notes1

Pad Capacitance

1.8

2.1

2.75

pF

8

NOTES:

1.

2.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

_ILis defined as the maximum voltage level at a receiving agent that will be interpreted

V

as a logical low value.

V_IHis defined as the minimum voltage level at a receiving agent that will be interpreted

3.

as a logical high value.

VIH and VOH may experience excursions above VTT. However, input signal drivers

must comply with the signal quality specifications.

GTLREF should be generated from VTT with a 1% tolerance resistor divider. The VTT

referred to in these specifications is the instantaneous VTT. Please refer to latest

Nettop’08 Platform Design Guide for GTLREF settings.

4.

5.

6.

RTT is the on-die termination resistance measured at VOL of the AGTL+ output driver.

Measured at 0.31*VTT. RTT is connected to VTT on die. Refer to processor I/O buffer

models for I/V characteristics.

7.

8.

9.

Specified with on die RTT and RON are turned off. Vin between 0 and VTT.

Cpad includes die capacitance only. No package parasitics are included.

This is the external resistor on the comp pins.

10. On die termination resistance, measured at 0.33*VTT.

11. RCOMP resistance must be provided on the system board with 1% resistors.

12. Refer to platform design guide for platform specific GTLREF value.

13. 2/3 VTT for paring with SiS 671 chipset and 0.62 VTT for pairing with Intel 945GC

chipset.

Table 10. Legacy CMOS Signal Group DC Specifications

Symbol

Parameter

I/O Voltage

Min

Typ

Max

Unit

Notes1

VTT

VIH

1.05

0.7*VTT

-0.10

0.9*VTT

-0.10

1.5

1.10

VTT

0.00

VTT

0

1.15

VTT+0.1

0.3*VTT

VTT+0.1

0.1*VTT

4.1

V

Input High Voltage

Input Low Voltage CMOS

Output High Voltage

Output Low Voltage

Output High Current

Output Low Current

Input Leakage Current

Pad Capacitance

2

2, 3

2

VIL

V

VOH

VOL

IOH

V

2

mA

µA

pF

5

IOL

1.5

4.1

4

ILI

± 100

2.55

6

Cpad1

Cpad2

1.6

2.1

1.2

7

Pad Capacitance for CMOS

Input

0.95

1.45

8

NOTES:

1.

2.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

The V_TTreferred to in these specifications refers to instantaneous

V .

TT

3.

4.

5.

6.

7.

Refer to the processor I/O Buffer Models for I/V characteristics.

Measured at 0.1*V

Measured at 0.9*V

.

TT

For Vin between 0V and V_TT. Measured when the driver is tri-stated.

Cpad1 includes die capacitance only for DPRSTP#, DPSLP#, PWRGOOD. No package

parasitics are included.

Cpad2 includes die capacitance for all other CMOS input signals. No package parasitics

are included.

8.

Datasheet

21

Electrical Specifications

Table 11. Open Drain Signal Group DC Specifications

Symbol

Parameter

Min

Typ

Max

Unit

Notes¹

VOH

Output High Voltage

VTT-5%

VTT

VTT+5%

V

3

VOL

IOL

Output Low Voltage

Output Low Current

Output Leakage Current

Pad Capacitance

0

0.20

50

V

16

mA

µA

pF

2

4

5

ILO

±200

2.45

Cpad

1.9

2.2

NOTES:

1.

2.

3.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

Measured at 0.2 V.

V_OHis determined by value of the external pull-up resistor to V_TT. Refer to platform

design guide for details.

For Vin between 0 V and

Cpad includes die capacitance only. No package parasitics are included.

4.

5.

V

OH

.

3.12

AGTL+ FSB Specifications

Routing topology recommendations may be found in the appropriate platform design

guides. Termination resistors are not required for most AGTL+ signals, as these are

integrated into the processor silicon.

Valid high and low levels are determined by the input buffers which compare a signal’s

voltage with a reference voltage called GTLREF (known as VREF in previous

documentation).

Table 3-9 lists the GTLREF specifications. The AGTL+ reference voltage (GTLREF)

should be generated on the system board using high precision voltage divider circuits.

It is important that the system board impedance is held to the specified tolerance, and

that the intrinsic trace capacitance for the AGTL+ signal group traces is known and

well- controlled. For more details on platform design, see the appropriate platform

design guides.

§

22

Datasheet

Package Mechanical Specifications and Ball Information

4 Package Mechanical

Specifications and Ball

Information

This chapter provides the package specifications, pinout assignments, and signal

description.

4.1

Package Mechanical Specifications

The processor will be available in 512 kB, 437 pins in FCBGA8 package.

4.1.1

Package Mechanical Drawings

Figure 2. Package Mechanical Drawing

Datasheet

23

Package Mechanical Specifications and Ball Information

4.1.2

4.1.3

4.1.4

Package Loading Specifications

Package loading is 5lb max static compressive.

Processor Mass Specifications

Processor mass is 1.4g.

Processor Pinout Assignment

Figure 4-3 and Figure 4-4 are graphic representations of the processor pinout

assignments. Table 4-12 lists the pinout by signal name.

24

Datasheet

Package Mechanical Specifications and Ball Information

Figure 3. Pinout Diagram (Top View, Left Side)

1

2

3

4

VSS

5

D[54]#

VSS

6

D[56]#

D[59]#

D[58]#

NC

7

GTLREF

CMREF

D[62]#

VCCA

VSS

8

9

VCCQ0

VTT

10

11

VCCP

VSS

A

B

C

D

E

VSS

RSVD

VSS

VTT

VSS

VCCP

VSS

A

B

C

D

E

VSS

RSVD

VSS

D[60]#

D[55]#

D[51]#

VSS

D[52]#

D[61]#

RSVD

THRMDA

VSS

D[48]#

D[63]#

DSTBN[3]

D[57]#

D[49]#

D[41]#

D[45]#

DINV[3]

VSS

VTT

D[53]#

D[50]#

VSS

THRMDC

VSS

VTT

F

DSTBP[3]

D[40]#

VSS

VTT

F

G

H

J

VSS

BSEL[2]

BSEL[1]

VSS

NC

VSS

VTT

G

H

J

D[46]#

D[47]#

VSS

NC

VSS

D[38]#

IGNNE#

NC

BSEL[0]

VSS

K

L

DSTBN[2] DSTBP[2]

NC

VSS

K

L

DINV[2]

VSS

D[43]#

D[36]#

D[42]#

D[37]#

D[33]#

COMP[1]

D[27]#

D[30]#

D[25]#

VSS

M

N

P

D[44]#

D[39]#

VSS

RSVD

VSS

EXTBGREF

RSVD

VSS

M

N

P

D[35]#

D[34]#

VSS

R

T

D[32]#

D[28]#

VSS

RSVD

VSS

RSVD

VSS

R

T

COMP[0]

D[19]#

VSS

U

V

W

Y

DPWR#

VSS

RSVD

VSS

VTT

U

V

W

Y

D[26]#

D[18]#

D24[]#

VSS

RSVD

VTT

BCLK[0]

VSS

D[31]#

D[21]#

D[20]#

D[15]# D[1]#

VSS

DSTBN[1] DSTBP[1] DINV[1]

D[22]# D[17]# D[8]#

D[7]#

VSS

D[0]#

D[4]#

AA

VSS

4

D[16]#

5

D[23]#

6

VSS

7

D[29]# D[14]#

A

1

2

3

8

9

10

11

Datasheet

25

Package Mechanical Specifications and Ball Information

Figure 4. Pinout Diagram (Top View, Right Side)

12

13

14

15

16

17

18

19

20

21

A

B

VCCP

RSVD

VSS

A[35]#

A[33]#

VSS

A[20]#

A[29]#

A[32]#

A[30]#

VSS

A

B

A[34]#

A[27]# ADSTB[1

]#

VSS

C

D

E

VCCP

VSS

VCCSENSE A[22]#

A[28]#

RESET#

VSS

A[31]#

VID[1]

VSS

RSVD

VID[5]

VSS

A[23]#

VSS

A[17]#

A[21]#

VSS

A[24]#

A[26]#

A[25]#

COMP[2]

A[9]#

RSVD

VSS

C

D

E

F

VSSSENSE

VTT

VSS

VTT

VSS

VID[2]

VSS

A[19]#

COMP[3]

VSS

F

VTT

VID[0]

VID[3]

BPM[2]#

BPM[3]#

VSS

IERR#

VID[4]

VSS

A[18]#

G

H

J

VSS

PROCHOT# VID[6] REQ[2]#

G

H

J

VSS

RSVD

VSS

BPM[1]#

PRDY#

VSS

A[4]#

A[11]#

REQ[1]#

VSS

PREQ#

TRST#

NC

A[7]#

A[15]#

K

L

VSS

BPM[0]#

TMS

A[14]# ADSTB[0]#

K

L

VSS

A[10]#

A[8]#

VSS

A[12]#

A[13]#

A[5]#

REQ[3]#

A[6]#

BR0#

A[16]#

VSS

M

N

P

VSS

NC

TDO

TCK

RSVD

SLP#

M

VSS

FORCEPR#

VSS

TDI

VSS

REQ[0]# N

VSS

RSVD

DPSLP#

RSVD

SMI#

VSS

A[3]#

VSS

P

R

T

R

T

VSS

LINT1

LINT0

VSS

STPCLK#

FERR#

VSS

DPRSTP# REQ[4]#

VSS

A20M

VSS

DRDY#

VSS

DEFER#

BPRI#

VSS

U

V

W

Y

VTT

RS[2]#

HITM#

LOCK#

VSS

U

V

W

Y

BCLK[1]

D[5]#

D[2]#

VSS

BR1#

INIT#

DINV[0]

D[12]#

D[6]#

PWRGOOD

VSS

ADS

D[13]#

D[9]#

D[11]#

D[10]#

RS[0]#

DBSY#

VSS

TRDY#

BNR#

VSS

DSTBN[0] DSTBP[0]

RS[1]#

HIT#

VSS

AA

D[3]#

14

VSS

15

VSS

A

12

13

16

17

18

19

20

21

26

Datasheet

Package Mechanical Specifications and Ball Information

Table 12. Pinout Arranged By Signal Name

Signal Name

Ball #

Signal

Name

Ball #

Signal Name

Ball #

Signal Name

Ball #

A[10]#

A[11]#

A[12]#

A[13]#

A[14]#

A[15]#

A[16]#

A[17]#

A[18]#

A[19]#

A[20]#

A[21]#

A[22]#

A[23]#

A[24]#

A[25]#

A[26]#

A[27]#

A[28]#

A[29]#

A[3]#

M19

H21

L20

M20

K19

J20

BCLK[0]

BCLK[1]

BNR#

V11

V12

Y19

K17

J18

H15

J15

U21

T20

V15

J6

D[28]#

D[29]#

D[3]#

T3

AA8

AA14

V2

D[62]#

D[63]#

D[7]#

C7

D2

Y10

Y9

BPM[0]#

BPM[1]#

BPM[2]#

BPM[3]#

BPRI#

D[30]#

D[31]#

D[32]#

D[33]#

D[34]#

D[35]#

D[36]#

D[37]#

D[38]#

D[39]#

D[4]#

D[8]#

W4

R3

D[9]#

Y13

Y18

V5

DBSY#

L21

C19

F19

E21

A16

D19

C14

C18

C20

E20

D20

B18

C15

B16

P21

B17

C16

A17

B14

B15

A14

H20

N20

R20

J19

R2

RSVD

P1

DEFER#

DINV[0]#

DINV[1]#

DINV[2]#

DINV[3]#

DPRSTP#

DPWR#

DRDY#

T21

W16

Y6

BR0#

N1

M2

P2

BR1#

BSEL[0]

BSEL[1]

BSEL[2]

COMP[0]

COMP[1]

COMP[2]

COMP[3]

D[0]#

L1

H5

J3

C5

G5

N3

AA11

G3

H2

N2

L2

R18

U4

T1

T2

D[40]#

D[41]#

D[42]#

D[43]#

D[44]#

D[45]#

D[46]#

D[47]#

D[48]#

D[49]#

D[5]#

T19

Y14

Y4

F20

F21

Y11

W10

W15

AA13

Y16

W13

AA9

W9

AA5

Y8

DSTBN[0]#

DSTBN[1]#

DSTBN[2]#

DSTBN[3]#

DSTBP[0]#

DSTBP[1]#

DSTBP[2]#

DSTBP[3]#

FERR#

K2

D[1]#

M3

J2

E2

D[10]#

D[11]#

D[12]#

D[13]#

D[14]#

D[15]#

D[16]#

D[17]#

D[18]#

D[19]#

D[2]#

Y15

Y5

H1

J1

A[30]#

A[31]#

A[32]#

A[33]#

A[34]#

A[35]#

A[4]#

K3

C2

F3

G2

W12

F1

T16

N15

A7

FORCEPR#

GTLREF

HIT#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[6]#

D3

B4

AA17

V20

F16

J4

W3

U1

HITM#

A[5]#

E1

IERR#

A[6]#

Y12

W7

W6

Y7

A5

IGNNE#

INIT#

A[7]#

D[20]#

D[21]#

D[22]#

D[23]#

D[24]#

D[25]#

D[27]#

C3

V16

T15

R15

W20

P17

D6

A[8]#

N19

G20

U18

U5

A6

LINT0

A[9]#

F2

LINT1

A20M#

RSVD

AA6

Y3

C6

LOCK#

B6

RSVD

ADS#

V19

B19

W2

U2

AA16

C4

NC

D[61]#

NC

H6

ADSTB[1]#

Datasheet

27

Package Mechanical Specifications and Ball Information

Signal Name

Ball #

Signal

Name

Ball #

Signal Name

Ball #

L10

Signal Name

Ball #

B13

TD

EXTBGREF

THERMTRIP#

THRMDA

THRMDC

TMS

M16

M6

VCC

VSS

VTT

NC

K4

K5

L11

L12

M10

M11

M12

N10

N11

N12

P10

P11

P12

R10

R11

R12

D7

B20

B21

C8

NC

M15

L16

K18

J16

G17

V17

N21

J21

G19

P20

R19

D15

W18

Y17

U20

D17

R17

M18

T17

B7

H17

E4

VCC

NC

VCC

PRDY#

PREQ#

PROCHOT#

PWRGOOD

REQ[0]#

REQ[1]#

REQ[2]#

REQ[3]#

REQ[4]#

RESET#

RS[0]#

RS[1]#

RS[2]#

RSVD

E5

VCC

C17

D1

L17

W19

K16

A10

A11

A12

B10

B11

B12

C10

C11

C12

D10

D11

D12

E10

E11

E12

F10

F11

F12

G10

G11

G12

H10

H11

H12

J10

J11

J12

P4

VCC

TRDY#

TRST#

VCC

D5

VCC

D8

VCC

D14

D18

D21

E3

VCC

E6

VCC

E7

VCC

E8

VCC

VCCA

VTT

E15

E16

E19

F4

VCC

V10

A9

VCC

VCCQ0

VCCSENSE

VID[0]

VID[1]

VID[2]

VID[3]

VID[4]

VID[5]

VID[6]

VSS

DPSLP#

RSVD

VCC

B9

VCC

C13

F15

D16

E18

G15

G16

E17

G18

A2

F5

RSVD

VCC

F6

CMREF

RSVD

VCC

F7

A13

R6

VCC

F17

F18

G1

RSVD

VCC

RSVD

N6

VCC

RSVD

T6

VCC

G4

RSVD

A3

VCC

G7

RSVD

C1

VCC

G9

RSVD

C21

E13

E14

F13

F14

N18

U17

R16

M17

N16

J5

VCC

VSS

A4

G13

G21

H3

VTT

VCC

VSS

A8

VTT

VCC

VSS

A15

A18

A19

A20

B1

VTT

VCC

VSS

H4

VTT

VCC

RSVD

VSS

H7

SLP#

VCC

H9

SMI#

VCC

VSS

H13

H14

J8

STPCLK#

TCK

VSS

V8

VSS

P5

VSS

V13

V14

V18

TDI

VSS

P6

VSS

J14

K8

VSS

VCC

K11

VSS

28

Datasheet

Package Mechanical Specifications and Ball Information

Signal Name

Ball #

Signal

Name

Ball #

Signal Name

Ball #

Signal Name

Ball #

VSS

RSVD

VSS

J7

J9

VCC

VSS

K12

P7

VSS

VSSSENSE

VTT

V21

W1

VTT

K14

L8

J13

J17

K1

P9

W5

VSS

VTT

H19

N8

P13

P15

P16

P18

P19

R1

W8

W11

W14

W17

W21

Y1

VTT

N14

P8

K6

VTT

K7

VTT

P14

R8

K9

VTT

K13

K15

K21

L3

VTT

R14

T8

R5

Y2

VTT

R7

Y20

Y21

AA2

AA3

AA4

AA7

AA10

AA12

AA15

AA18

AA19

AA20

D13

C9

VTT

T14

U8

R9

VTT

L4

R13

R21

T4

VTT

U9

L5

VTT

U10

U11

U12

U13

U14

V9

L6

VTT

L7

T5

VTT

L9

T7

VTT

L13

L15

L18

L19

M1

M5

M7

M9

M13

M21

N4

T9

VTT

T10

T11

T12

T13

T18

U3

RSVD

R4

M4

D4

U6

VTT

D9

U7

VTT

E9

U15

U16

U19

V1

VTT

F8

VTT

F9

N5

VTT

G8

N7

VTT

G14

L14

M8

N9

V4

VTT

N13

N17

V6

VTT

B5

VTT

M14

VSS

P3

VSS

B8

VSS

H18

Datasheet

29

Package Mechanical Specifications and Ball Information

4.2

Signal Description

Table 13. Signal Description

Signal Name

Type

Description

A[32:3]# (Address) defines a 232-byte physical memory address

space. In subphase 1 of the address phase, these pins transmit the

address of a transaction.

In sub-phase 2, these pins transmit transaction type information.

These signals must connect the appropriate pins of both agents on

the Intel® Atom™ processor FSB. A[32:3]# are source synchronous

signals and are latched into the receiving buffers by ADSTB[1:0]#.

Address signals are used as straps which are sampled before

RESET# is deasserted.

A[32:3]#

I/O

If A20M# (Address-20 Mask) is asserted, the processor masks

physical address bit 20 (A20#) before looking up a line in any

internal cache and before driving a read/write transaction on the

bus. Asserting A20M# emulates the 8086 processor's address wrap-

around at the 1-MB boundary. Assertion of A20M# is only supported

in real mode.

A20M#

I

A20M# is an asynchronous signal. However, to ensure recognition of

this signal following an input/output write instruction, it must be

valid along with the TRDY# assertion of the corresponding input/

output Write bus transaction.

ADS# (Address Strobe) is asserted to indicate the validity of the

transaction address on the A[32:3]# and REQ[4:0]# pins. All bus

agents observe the ADS# activation to begin parity checking,

protocol checking, address decode, internal loop, or deferred reply

ID match operations associated with the new transaction.

ADS#

I/O

Address strobes are used to latch A[32:3]# and REQ[4:0]# on their

rising and falling edges. Strobes are associated with signals as

shown below.

ADSTB[1:0]#

BCLK[1:0]

I/O

SignalsAssociated Strobe REQ[4:0]#, A[16:3]#ADSTB[0]#

A[32:17]#ADSTB[1]#

The differential pair BCLK (Bus Clock) determines the FSB

frequency. All FSB agents must receive these signals to drive their

outputs and latch their inputs. All external timing parameters are

specified with respect to the rising edge of BCLK0 crossing VCROSS.

I

BNR# (Block Next Request) is used to assert a bus stall by any bus

agent who is unable to accept new bus transactions. During a bus

stall, the current bus owner cannot issue any new transactions.

These are Wired-OR signals. Wired-OR is AGTL common clock I/O.

They are signals where both CPU & MCH may possibly driver

together, hence no receiver. We would potentially see overshoot and

undershoot issue. Therefore, there is a dedicated over/ undershoot

specification for Wired-OR signals.

BNR#

I/O

30

Datasheet

Package Mechanical Specifications and Ball Information

Signal Name

Type

Description

BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance

monitor signals. They are outputs from the processor which indicate

the status of breakpoints and programmable counters used for

monitoring processor performance. BPM[3:0]# should connect the

appropriate pins of all FSB agents. This includes debug or

performance monitoring tools. Refer to the platform design guide for

more detailed information.

BPM[0]#

O

BPM[1]#

I/O

BPM[2]#

BPM[3]#

O

I/O

BPRI# (Bus Priority Request) is used to arbitrate for ownership of

the FSB. It must connect the appropriate pins of both FSB agents.

Observing BPRI# active (as asserted by the priority agent) causes

the other agent to stop issuing new requests, unless such requests

are part of an ongoing locked operation. The priority agent keeps

BPRI# asserted until all of its requests are completed, then releases

the bus by deasserting BPRI#.

BPRI#

I

BR[1:0]#

BSEL[2:0]

I/O

O

BR0# is used by the processor to request the bus.

BSEL[2:0] (Bus Select) are used to select the processor input clock

frequency. For Intel® Atom™ processor, the BSEL is fixed to

operate at 133-MHz BCLK frequency.

COMP[3:0] must be terminated on the system board using precision

(1% tolerance) resistors. Refer to the platform design guide for

more details on implementation.

COMP[3:0]

PWR

D[63:0]# (Data) are the data signals. These signals provide a 64-

bit data path between the FSB agents, and must connect the

appropriate pins on both agents. The data driver asserts DRDY# to

indicate a valid data transfer.

D[63:0]# are quad-pumped signals and will thus be driven four

times in a common clock period. D[63:0]# are latched off the falling

edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of

16 data signals correspond to a pair of one DSTBP# and one

DSTBN#. The following table shows the grouping of data signals to

data strobes and DINV#.

Quad-Pumped Signal Groups,

Data GroupDSTBN#/DSTBP#DINV#

D[15:0]#/00

D[63:0]#

I/O

D[31:16]#/11

D[47:32]#/22

D[63:48]#/33

Furthermore, the DINV# pins determine the polarity of the data

signals. Each group of 16 data signals corresponds to one DINV#

signal. When the DINV# signal is active, the corresponding data

group is inverted and therefore sampled active high.

Datasheet

31

Package Mechanical Specifications and Ball Information

Signal Name

Type

Description

DBSY# (Data Bus Busy) is asserted by the agent responsible for

driving data on the FSB to indicate that the data bus is in use. The

data bus is released after DBSY# is deasserted. This signal must

connect the appropriate pins on both FSB agents.

DBSY#

I/O

DEFER# is asserted by an agent to indicate that a transaction

cannot be guaranteed in-order completion. Assertion of DEFER# is

normally the responsibility of the addressed memory or Input/

Output agent. This signal must connect the appropriate pins of both

FSB agents.

DEFER#

DINV[3:0]#

DPSLP#

I

DINV[3:0]# (Data Bus Inversion) are source synchronous and

indicate the polarity of the D[63:0]# signals. The DINV[3:0]#

signals are activated when the data on the data bus is inverted. The

bus agent will invert the data bus signals if more than half the bits,

within the covered group, would change level in the next cycle.

DINV[3 0]# Assignment To Data B

s SignalData B

s Signals

DPSLP# when asserted on the platform causes the processor to

transition from the Sleep State to the Deep Sleep state. In order to

return to the Sleep State, DPSLP# must be deasserted. DPSLP# is

driven by the SCH chipset. This signal is not used for Nettop’08

platform and tied to VTT.

DPRSTP# when asserted on the platform causes the processor to

transition from the Deep Sleep State to the Deeper Sleep state. In

order to return to the Deep Sleep State, DPRSTP# must be

deasserted. DPRSTP# is driven by the SCH chipset. This signal is not

used for Nettop’08 platform and tied to VTT.

DPRSTP#

DPWR# is a control signal from the chipset used to reduce power on

the processor data bus input buffers. This signal is not used for

Nettop’08 platform and tied to VTT.

DPWR#

DRDY#

I

DRDY# (Data Ready) is asserted by the data driver on each data

transfer, indicating valid data on the data bus. In a multi-common

clock data transfer, DRDY# may be deasserted to insert idle clocks.

This signal must connect the appropriate pins of both FSB agents.

I/O

Data strobe used to latch in D[63:0]#.

Signals Associated Strobe

D[15:0]#DINV[0]#, DSTBN[0]#

D[31:16]#DINV[1]#, DSTBN[1]#

D[47:32]#DINV[2]#, DSTBN[2]#

D[63:48]#DINV[3]#, DSTBN[3]#

DSTBN[3:0]#

I/O

Data strobe used to latch in D[63:0]#.

Signals Associated Strobe

D[15:0]#DINV[0]#, DSTBP[0]#

D[31:16]#DINV[1]#, DSTBP[1]#

D[47:32]#DINV[2]#, DSTBP[2]#

D[63:48]#DINV[3]#, DSTBP[3]#

DSTBP[3:0]#

I/O

32

Datasheet

Package Mechanical Specifications and Ball Information

Signal Name

Type

Description

FERR# (Floating-point Error)/PBE# (Pending Break Event) is a

multiplexed signal and its meaning is qualified with STPCLK#. When

STPCLK# is not asserted, FERR#/PBE# indicates a floating point

when the processor detects an unmasked floating-point error.

FERR# is similar to the ERROR# signal on the Intel 387 coprocessor,

and is included for compatibility with systems using MSDOS*- type

floating-point error reporting. When STPCLK# is asserted, an

assertion of FERR#/PBE# indicates that the processor has a pending

break event waiting for service. The assertion of FERR#/PBE#

FERR#/PBE#

O

indicates that the processor should be returned to the Normal state

GTLREF determines the signal reference level for AGTL+ input pins.

GTLREF is used by the AGTL+ receivers to determine if a signal is a

logical 0 or logical 1. Refer to the platform design guide for details

on GTLREF implementation.

GTLREF

PWR

CMOS signal reference voltage for data and address pin. Since

CMOS signaling is not used, this is a no connect. Tie this to GTLREF

as defensive design.

CMREF

PWR

EXTBGREF should be set at 2/3 VTT with resistor divider network

with a 1k // 2k Ohm resistors.

EXTBGREF

HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction

snoop operation results. Either FSB agent may assert both HIT# and

HITM# together to indicate that it requires a snoop stall, which can

be continued by reasserting HIT# and HITM# together.

HIT# HITM#

I/O

These are Wired-OR signals. Wired-OR is AGTL common clock I/O.

They are signals where both CPU & MCH may possibly driver

together, hence no receiver. We would potentially see overshoot and

undershoot issue. Therefore, there is a dedicated over/ undershoot

specification for Wired-OR signals.

IERR# (Internal Error) is asserted by a processor as the result of an

internal error. Assertion of IERR# is usually accompanied by a

SHUTDOWN transaction on the FSB. This transaction may optionally

be converted to an external error signal (e.g., NMI) by system core

logic. The processor will keep IERR# asserted until the assertion of

RESET#, or INIT#.

IERR#

O

For termination requirements, refer to the platform design guide.

IGNNE# (Ignore Numeric Error) is asserted to force the processor to

ignore a numeric error and continue to execute non-control floating-

point instructions. If IGNNE# is deasserted, the processor generates

an exception on a non-control floating-point instruction if a previous

floating-point instruction caused an error. IGNNE# has no effect

when the NE bit in control register 0 (CR0) is set.

IGNNE#

I

IGNNE# is an asynchronous signal. However, to ensure recognition

of this signal following an Input/Output write instruction, it must be

valid along with the TRDY# assertion of the corresponding Input/

Output Write bus transaction.

Datasheet

33

Package Mechanical Specifications and Ball Information

Signal Name

Type

Description

INIT# (Initialization), when asserted, resets integer registers inside

the processor without affecting its internal caches or floating-point

registers. The processor then begins execution at the power-on

Reset vector configured during power-on configuration. The

processor continues to handle snoop requests during INIT#

assertion. INIT# is an asynchronous signal. However, to ensure

recognition of this signal following an Input/Output Write instruction,

it must be valid along with the TRDY# assertion of the

corresponding Input/Output Write bus transaction. INIT# must

connect the appropriate pins of both FSB agents.

INIT#

I

If INIT# is sampled active on the active to inactive transition of

RESET#, Intel® Atom™ reverses its FSB data and address signals

internally to ease mother board layout for systems where the

chipset is on the other side of the mother board.

D[63:0] => D[0:63] A[32:3] => A[3:32] DINV[3:0]# is also

reversed.

LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins

of all APIC Bus agents. When the APIC is disabled, the LINT0 signal

becomes INTR, a maskable interrupt request signal, and LINT1

becomes NMI, a non-maskable interrupt. INTR and NMI are

backward compatible with the signals of those names on the

Pentium processor. Both signals are asynchronous.

LINT[1:0]

I

Both of these signals must be software configured via BIOS

programming of the APIC register space to be used either as NMI/

INTR or LINT[1:0]. Because the APIC is enabled by default after

Reset, operation of these pins as LINT[1:0] is the default

configuration.

Probe Ready signal used by debug tools to determine processor

debug readiness.

LOCK#

PRDY#

I/O

O

Probe Request signal used by debug tools to request debug

operation of the processor. Refer to the platform design guide for

more implementation details.

Probe Request signal used by debug tools to request debug

operation of the processor. Refer to the platform design guide for

more implementation details.

PREQ#

I

As an output, PROCHOT# (Processor Hot) will go active when the

processor temperature monitoring sensor detects that the processor

has reached its maximum safe operating temperature. This indicates

that the processor Thermal Control Circuit (TCC) has been activated,

if enabled. As an input, assertion of PROCHOT# by the system will

activate the TCC, if enabled. The TCC will remain active until the

PROCHOT#

I/O, O (DP)

system deasserts PROCHOT#.

For termination requirements, refer to the platform design guide.

This signal may require voltage translation on the motherboard.

Refer to the platform design guide for more details.

34

Datasheet

Package Mechanical Specifications and Ball Information

Signal Name

Type

Description

PWRGOOD (Power Good) is a processor input. The processor

requires this signal to be a clean indication that the clocks and

power supplies are stable and within their specifications. ‘Clean’

implies that the signal will remain low (capable of sinking leakage

current), without glitches, from the time that the power supplies are

turned on until they come within specification. The signal must then

transition monotonically to a high state. PWRGOOD can be driven

inactive at any time, but clocks and power must again be stable

before a subsequent rising edge of PWRGOOD.

PWRGOOD

I

The PWRGOOD signal must be supplied to the processor; it is used

to protect internal circuits against voltage sequencing issues. It

should be driven high throughout boundary scan operation.

REQ[4:0]# (Request Command) must connect the appropriate pins

of both FSB agents. They are asserted by the current bus owner to

define the currently active transaction type. These signals are

source synchronous to ADSTB[0]#.

REQ[4:0]#

I/O

Asserting the RESET# signal resets the processor to a known state

and invalidates its internal caches without writing back any of their

contents. For a power-on Reset, RESET# must stay active for at

least two milliseconds after VCC and BCLK have reached their

RESET#

I

proper specifications. On observing active RESET#, both FSB

agents will deassert their outputs within two clocks. All processor

straps must be valid within the specified setup time before RESET#

is deasserted.

RS[2:0]# (Response Status) are driven by the response agent (the

agent responsible for completion of the current transaction), and

must connect the appropriate pins of both FSB agents.

RS[2:0]#

RSVD

These pins are RESERVED and must be left unconnected on the

board. However, it is recommended that routing channels to these

pins on the board be kept open for possible future use.

Reserved/

No Connect

SLP# (Sleep), when asserted in Stop-Grant state, causes the

processor to enter the Sleep state. During Sleep state, the processor

stops providing internal clock signals to all units, leaving only the

Phase-Locked Loop (PLL) still operating. Processors in this state will

not recognize snoops or interrupts. The processor will recognize only

assertion of the RESET# signal, deassertion of SLP#, and removal of

the BCLK input while in Sleep state. If SLP# is deasserted, the

processor exits Sleep state and returns to Stop- Grant state,

restarting its internal clock signals to the bus and processor core

units. If DPSLP# is asserted while in the Sleep state, the processor

will exit the Sleep state and transition to the Deep Sleep state. This

signal is not used for Nettop’08 platform and tied to VTT.

SLP#

I

Datasheet

35

Package Mechanical Specifications and Ball Information

Signal Name

Type

Description

SMI# (System Management Interrupt) is asserted asynchronously

by system logic. On accepting a System Management Interrupt, the

processor saves the current state and enter System Management

Mode (SMM). An SMI Acknowledge transaction is issued, and the

processor begins program execution from the SMM handler. If SMI#

is asserted during the deassertion of RESET# the processor will

tristate its outputs.

SMI#

I

STOP-GRANT state is not supported, therefore this pin is not used.

Please refer to Nettop’08 Platform Design Guide for termination

requirement.

STPCLK#

TCK

I

TCK (Test Clock) provides the clock input for the processor Test Bus

(also known as the Test Access Port). Refer to the platform design

guide for termination requirements and implementation details.

TDI (Test Data In) transfers serial test data into the processor. TDI

provides the serial input needed for JTAG specification support.

TDI

I

TDO (Test Data Out) transfers serial test data out of the processor.

TDO provides the serial output needed for JTAG specification

support.

TDO

O

The processor protects itself from catastrophic overheating by use of

an internal thermal sensor. This sensor is set well above the normal

operating temperature to ensure that there are no false trips. The

processor will stop all execution when junction temperature exceeds

approximately 125 degree Celsius. This is signaled to the system by

the THERMTRIP# (Thermal Trip) pin. For termination requirements,

refer to the platform design guide.

THERMTRIP

O

Thermal Diode - Anode

THRMDA

THRMDC

TMS

PWR

Thermal Diode - Cathode

PWR

TMS (Test Mode Select) is a JTAG specification support signal used

by debug tools. Refer to the platform design guide for termination

requirements and implementation details.

I

TRDY# (Target Ready) is asserted by the target to indicate that it is

ready to receive a write or implicit writeback data transfer. TRDY#

must connect the appropriate pins of both FSB agents.

TRDY#

TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST#

must be driven low during power on Reset. Refer to the platform

design guide for termination requirements and implementation

details.

TRST#

I

36

Datasheet

Package Mechanical Specifications and Ball Information

Signal Name

Type

Description

VCCA provides isolated power for the internal processor core PLLs.

Refer to the platform design guide for complete implementation

details.

VCCA

PWR

Processor core power supply

VCCP

VSS

VTT

PWR

GND

PWR

Processor core ground node.

FSB AGTL+ termination voltage with respect to VSS

VID[6:0] (Voltage ID) pins are used to support automatic selection

of power supply voltages (VCC) but these pins are not used in the

Nettop’08 platform as the VID is fixed at 1.1V.

VID[6:0]

O

VCC_SENSE is an isolated low impedance connection to processor

core power (VCC). It can be used to sense or measure voltage near

the silicon with little noise.

VCC_SENSE

VSS_SENSE is an isolated low impedance connection to processor

core VSS. It can be used to sense or measure ground near the

silicon with little noise. Refer to the platform design guide for

termination recommendations and more details.

VSS_SENSE

O

§

Datasheet

37

Thermal Specifications and Design Considerations

5 Thermal Specifications and

Design Considerations

The processor requires a thermal solution to maintain temperatures within operating

limits as set forth in Section Thermal Specifications. Any attempt to operate the

processor outside these operating limits may result in permanent damage to the

processor and potentially other components in the system. As processor technology

changes, thermal management becomes increasingly crucial when building computer

systems. Maintaining the proper thermal environment is key to reliable, long-term

system operation.

A complete thermal solution includes both component and system level thermal

management features. Component level thermal solutions include active or passive

heatsink attached to the exposed processor die. The solution should make firm contact

to the die while maintaining processor mechanical specifications such as pressure. A

typical system level thermal solution may consist of a system fan used to evacuate or

pull air through the system. For more information on designing a component level

thermal solution, please refer to the appropriate Thermal and Mechanical Design

Guidelines (see Section 1.3). Alternatively, the processor may be in a fan-less system,

but would likely still use a multi-component heat spreader. Note that trading of thermal

solutions also involves trading performance.

5.1

Thermal Specifications

To allow for the optimal operation and long-term reliability of Intel processor-based

systems, the system/processor thermal solution should be designed such that the

processor remains within the minimum and maximum case temperature (Tc)

specifications at the corresponding thermal design power (TDP) value listed in Table

5-14. Thermal solutions not designed to provide this level of thermal capability may

affect the long-term reliability of the processor and system. For more details on

thermal solution design, refer to the appropriate Thermal and Mechanical Design

Guidelines (see Section 1.3).

The case temperature is defined at the geometric top center of the processor. Analysis

indicates that real applications are unlikely to cause the processor to consume the

theoretical maximum power dissipation for sustained time periods. Intel recommends

that complete thermal solution designs target the TDP indicated in Table 5-14 instead

of the maximum processor power consumption. The Intel Thermal Monitor feature is

designed to help protect the processor in the unlikely event that an application exceeds

the TDP recommendation for a sustained period of time. For more details on the usage

of this feature, refer to Section 5.1.2. In all cases the Intel Thermal Monitor feature

must be enabled for the processor to remain within specification.

38

Datasheet

Thermal Specifications and Design Considerations

Table 14. Power Specifications for the Processor

Symbol Processor

Number

Core

Frequency

and Voltage

Thermal Design

Power

Unit

Tc

min

(°C

Tc

max

(°C)

Notes

TDP

230

1.6 GHz & VCC

4.0

W

0

85.2

1, 3, 4

Symbol

Parameter

Auto Halt

Min Typ Max

Unit

PAH

1.0

W

2

NOTES:

1.

The TDP specification should be used to design the processor thermal solution. The TDP

is not the maximum theoretical power the processor can generate.

Not 100% tested. These power specifications are determined by characterization of the

processor currents at higher temperatures and extrapolating the values for the

temperature indicated.

2.

3.

4.

The Intel Thermal Monitor automatic mode must be enabled for the processor to

operate within specifications.

V_CCis determined by processor VID[6:0].

The processor incorporates three methods of monitoring die temperature: the Digital

Thermal Sensor, Intel Thermal Monitor, and the Thermal Diode. The Intel Thermal

Monitor (detailed in Section5.1.2) must be used to determine when the maximum

specified processor junction temperature has been reached.

5.1.1

Thermal Diode

The processor incorporates an on-die PNP transistor whose base emitter junction is

used as a thermal “diode”, with its collector shorted to ground. The thermal diode can

be read by an off-die analog/digital converter (a thermal sensor) located on the

motherboard or a stand-alone measurement kit. The thermal diode may be used to

monitor the die temperature of the processor for thermal management or

instrumentation purposes but is not a reliable indication that the maximum operating

temperature of the processor has been reached. When using the thermal diode, a

temperature offset value must be read from a processor MSR and applied. See

See Section 5.1.2 for thermal diode usage recommendation when the PROCHOT#

signal is not asserted.

The reading of the external thermal sensor (on the motherboard) connected to the

processor thermal diode signals will not necessarily reflect the temperature of the

hottest location on the die. This is due to inaccuracies in the external thermal sensor,

on-die temperature gradients between the location of the thermal diode and the hottest

location on the die, and time based variations in the die temperature measurement.

Time based variations can occur when the sampling rate of the thermal diode (by the

thermal sensor) is slower than the rate at which the T_Jtemperature can change.

Offset between the thermal diode based temperature reading and the Intel Thermal

Monitor reading may be characterized using the Intel Thermal Monitor’s Automatic

mode activation of the thermal control circuit. This temperature offset must be taken

into account when using the processor thermal diode to implement power management

events. This offset is different than the diode T_offsetvalue programmed into the

processor Model Specific Register (MSR).

Datasheet

39

Thermal Specifications and Design Considerations

Table 5-15 and Table 5-16 provide the diode interface and specifications. Transistor

model parameters shown in Table 5-16 providing more accurate temperature

measurements when the diode ideality factor is closer to the maximum or minimum

limits. Contact your external sensor supplier for their recommendation. The thermal

diode is separate from the Thermal Monitor’s thermal sensor and cannot be used to

predict the behavior of the Thermal Monitor.

Table 15. Thermal Diode Interface

Signal Name

Pin/Ball Number

Signal Description

THERMDA

THERMDC

E4

E5

Thermal diode anode

Thermal diode cathode

Table 16. Thermal Diode Parameters using Transistor Model

Symbol

Parameter

Min

Typ

Max

Unit Notes

IFW

IE

Forward Bias Current

Emitter Current

5

200

μA

1

5

nQ

Transistor Ideality

0.997

0.25

2.79

1.001

4.52

1.015

0.65

6.24

2,3,4

2,3

2,5

Beta

RT

Series Resistance

Ω

NOTES:

1.

2.

3.

4.

Intel does not support or recommend operation of the thermal diode under reverse bias.

Characterized across a temperature range of 50–100°C.

Not 100% tested. Specified by design characterization.

The ideality factor, nQ, represents the deviation from ideal transistor model behavior as

exemplified by the equation for the collector current:

qV_BE/n_QkT

I_C= I_S* (e

–1)

where I_S= saturation current, q = electronic charge, V_BE= voltage across the transistor

base emitter junction (same nodes as VD), k = Boltzmann Constant, and T = absolute

temperature (Kelvin).

The series resistance, R_T, provided in the Diode Model Table (Table 5-16) can be used for

5.

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system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.

64-bit computing on Intel® architecture requires a computer system with a processor, chipset, BIOS, operating system, device drivers and

applications enabled for Intel® 64 architecture. Processors will not operate (including 32-bit operation) without an Intel 64 architecture-

enabled BIOS. Performance will vary depending on your hardware and software configurations. Consult with your system vendor for more

information.

Hyper-Threading Technology (HT Technology) requires a computer system with an Intel® processor supporting HT Technology and an HT

Technology enabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use.

See www.intel.com/products/ht/hyperthreading_more.htm for more information including details on which processors support HT Technology.

Intel® Virtualization Technology requires a computer system with a processor, chipset, BIOS, virtual machine monitor (VMM) and for some

uses, certain platform software, enabled for it. Functionality, performance or other benefit will vary depending on hardware and software

configurations. Intel Virtualization Technology-enabled VMM applications are currently in development.

Note: Prices subject to change without notice. Prices are for direct Intel customers in 1000-unit bulk quantities and, unless specified,

represent the latest technology versions of the products. Taxes and shipping, etc. not included. Prices may vary for other package types and

shipment quantities, and special promotional arrangements may apply.

Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not

across different processor families. See http://www.intel.com/products/processor_number for details.

System and Maximum TDP is based on worst case scenarios. Actual TDP may be lower if not all I/Os for chipsets are used.

All information provided is subject to change at any time, without notice. Intel may make changes to manufacturing life cycle, specifications,

and product descriptions at any time, without notice. The information herein is provided "as-is" and Intel does not make any representations

or warranties whatsoever regarding accuracy of the information, nor on the product features, availability, functionality, or compatibility of the

products listed. Please contact system vendor for more information on specific products or systems.

Low Halogen implies the following:

Bromine and/or chlorine in materials that may be used during processing, but do not remain within the final product are not included in this

definition. The halogens fluorine (F), iodine (I), and astatine (At) are not restricted by this standard.

“BFR/CFR and PVC-Free” Definition: :

All PCB laminates must meet Br and Cl requirements for low halogen as defined in IPC-4101B

For components other than PCB laminates, all homogeneous materials must contain < 900 ppm (0.09%) of Bromine [if the Bromine (Br)

source is from BFRs] and < 900 ppm (0.09%) of Chlorine [if the Chlorine (Cl) source is from CFRs or PVC. Higher concentrations of Br and Cl

are allowed in homogenous materials of components other than PCB laminates as long as their sources are not BFRs, CFRs, PVC.

Although the elemental analysis for Br and Cl in homogeneous materials can be performed by any analytical method with sufficient sensitivity

and selectivity, the presence or absence of BFRs, CFRs or PVC must be verified by any acceptable analytical techniques that allow for the

unequivocal identification of the specific Br or Cl compounds, or by appropriate material declarations agreed to between customer and

supplier.

Max Turbo Frequency refers to the maximum single-core frequency that can be achieved with Intel® Turbo Boost Technology, which requires

a PC with a processor with Intel Turbo Boost Technology capability. Intel Turbo Boost Technology performance varies depending on hardware,

software, and overall system configuration. Check with your PC manufacturer on whether your system delivers Intel Turbo Boost Technology.

See www.intel.com/technology/turboboost/ for more information.

Some products can support AES New Instructions with a Processor Configuration update, in particular, i7-2630QM/i7-2635QM,

i7-2670QM/i7-2675QM, i5-2430M/i5-2435M, i5-2410M/i5-2415M. Please contact OEM for the BIOS that includes the latest Processor

configuration update.

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Ordering and Spec Information

Intel® Atom™ Processor N450 (512K Cache, 1.66 GHz) FC-BGA8, Tray

Socket

Step

Step TDP

Ordering Code

Spec Code

SLBMG

Low Halogen

VT-x

No

FCBGA559

5.5 W

AU80610004653AA

Yes

Compatible Products

Intel® NM10 Express Chipset

Intel® NM10 Platform Controller Hub

# of CPUs: 1

Chipsets

Embedded: Yes

System Price: $84

System TDP: 7.6W

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