AT80602002265AB_技术文档

Intel® Xeon® Processor 5500 Series

Datasheet, Volume 1

June 2011

Document Number: 321321-002

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Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel

reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future

changes to them.

The Intel® Xeon® Processor 5500 Series may contain design defects or errors known as errata which may cause the product to

deviate from published specifications.Current characterized errata are available on request.

Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family,

not across different processor families. See http://www.intel.com/products/processor_number for details. Over time processor

numbers will increment based on changes in clock, speed, cache, FSB, or other features, and increments are not intended to

represent proportional or quantitative increases in any particular feature. Current roadmap processor number progression is not

necessarily representative of future roadmaps. See www.intel.com/products/processor_number for details.

Hyper-Threading Technology requires a computer system with a processor supporting HT Technology and an HT Technology-

enabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. For

more information including details on which processors support HT Technology, see

http://www.intel.com/products/ht/hyperthreading_more.htm

Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting

operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.

64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device

drivers and applications enabled for Intel® 64 architecture. Performance will vary depending on your hardware and software

configurations. Consult with your system vendor for more information.

Intel® Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor

(VMM) and, for some uses, certain computer system software enabled for it. Functionality, performance or other benefits will vary

depending on hardware and software configurations and may require a BIOS update. Software applications may not be compatible

with all operating systems. Please check with your application vendor.

Intel® Turbo Boost Technology requires a PC with a processor with Intel Turbo Boost Technology capability. Intel Turbo Boost

Technology performance varies depending on hardware, software and overall system configuration. Check with your PC

manufacturer on whether your system delivers Intel Turbo Boost Technology. For more information, see www.intel.com.

Enhanced Intel SpeedStep® Technology. See the http://processorfinder.intel.com or contact your Intel representative for more

information.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Intel, Xeon, Enhanced Intel SpeedStep Technology, and the Intel logo are trademarks of Intel Corporation in the United States and

other countries.

*Other brands and names are the property of their respective owners.

®

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Intel Xeon Processor 5500 Series Datasheet, Volume 1

Contents

1

Introduction..............................................................................................................9

1.1

1.2

1.3

Terminology ..................................................................................................... 10

References ....................................................................................................... 12

Statement of Volatility ....................................................................................... 12

2

Intel® Xeon® Processors 5500 Series Electrical Specifications ............................... 13

2.1

Processor Signaling ........................................................................................... 13

2.1.1 Intel^®QuickPath Interconnect ................................................................. 13

2.1.2 DDR3 Signal Groups ............................................................................... 13

2.1.3 Platform Environmental Control Interface (PECI) ........................................ 14

2.1.4 Processor Sideband Signals ..................................................................... 14

2.1.5 System Reference Clock.......................................................................... 14

2.1.6 Test Access Port (TAP) Signals ................................................................. 15

2.1.7 Power / Other Signals............................................................................. 15

2.1.8 Reserved or Unused Signals..................................................................... 23

Signal Group Summary...................................................................................... 23

Mixing Processors.............................................................................................. 25

Flexible Motherboard Guidelines (FMB)................................................................. 26

Absolute Maximum and Minimum Ratings ............................................................. 26

Processor DC Specifications ................................................................................ 27

2.6.1 VCC Overshoot Specifications................................................................... 31

2.6.2 Die Voltage Validation............................................................................. 32

2.2

2.3

2.4

2.5

2.6

3

Package Mechanical Specifications .......................................................................... 43

3.1

Package Mechanical Specifications....................................................................... 43

3.1.1 Package Mechanical Drawing.................................................................... 44

3.1.2 Processor Component Keep-Out Zones...................................................... 47

3.1.3 Package Loading Specifications ................................................................ 47

3.1.4 Package Handling Guidelines.................................................................... 47

3.1.5 Package Insertion Specifications............................................................... 47

3.1.6 Processor Mass Specification.................................................................... 48

3.1.7 Processor Materials................................................................................. 48

3.1.8 Processor Markings................................................................................. 48

3.1.9 Processor Land Coordinates..................................................................... 48

4

Land Listing............................................................................................................. 49

4.1

Intel® Xeon® Processors 5500 Series Pin Assignments.......................................... 49

4.1.1 Land Listing by Land Name...................................................................... 49

4.1.2 Land Listing by Land Number................................................................... 67

5

6

Signal Definitions .................................................................................................... 85

5.1 Signal Definitions .............................................................................................. 85

Thermal Specifications ............................................................................................ 89

6.1

Package Thermal Specifications........................................................................... 89

6.1.1 Thermal Specifications ............................................................................ 89

6.1.2 Thermal Metrology ............................................................................... 102

Processor Thermal Features.............................................................................. 103

6.2.1 Processor Temperature ......................................................................... 103

6.2.2 Adaptive Thermal Monitor...................................................................... 103

6.2.3 On-Demand Mode ................................................................................ 105

6.2.4 PROCHOT# Signal................................................................................ 105

6.2.5 THERMTRIP# Signal ............................................................................. 106

Platform Environment Control Interface (PECI).................................................... 106

6.3.1 PECI Client Capabilities ......................................................................... 107

6.2

6.3

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Intel Xeon Processor 5500 Series Datasheet, Volume 1

3

6.3.2 Client Command Suite...........................................................................108

6.3.3 Multi-Domain Commands.......................................................................124

6.3.4 Client Responses ..................................................................................124

6.3.5 Originator Responses ............................................................................125

6.3.6 Temperature Data ................................................................................126

6.3.7 Client Management...............................................................................127

7

Features ................................................................................................................131

7.1

7.2

Power-On Configuration (POC)...........................................................................131

Clock Control and Low Power States...................................................................132

7.2.1 Thread and Core Power State Descriptions ...............................................133

7.2.2 Package Power State Descriptions...........................................................134

7.2.3 Intel Xeon Processor 5500 Series C-State Power Specifications ...................135

Sleep States ...................................................................................................136

Intel^®Turbo Boost Technology..........................................................................136

Enhanced Intel SpeedStep^®Technology .............................................................136

7.3

7.4

7.5

8

Boxed Processor Specifications..............................................................................137

8.1

Introduction....................................................................................................137

8.1.1 Available Boxed Thermal Solution Configurations ......................................137

8.1.2 An Intel “Combo” Boxed Passive / Active Combination Heat Sink Solution.....137

8.1.3 Intel Boxed “Active” Heat Sink Solution ...................................................138

8.1.4 Intel Boxed 25.5mm Tall Passive Heat Sink Solution..................................139

Mechanical Specifications..................................................................................140

8.2.1 Boxed Processor Heat Sink Dimensions and Baseboard Keepout Zones ........140

8.2.2 Boxed Processor Retention Mechanism and Heat Sink

8.2

Support (URS)......................................................................................149

Fan Power Supply (“Combo” and “Active” Solution) ..............................................150

8.3.1 Boxed Processor Cooling Requirements....................................................151

Boxed Processor Contents.................................................................................153

8.3

8.4

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Intel Xeon Processor 5500 Series Datasheet, Volume 1

Figures

2-1

Active ODT for a Differential Link Example............................................................ 13

Input Device Hysteresis ..................................................................................... 14

VCC Static and Transient Tolerance Loadlines1,2,3,4.............................................. 31

VCC Overshoot Example Waveform...................................................................... 32

Load Current Versus Time (130W TDP Processor),2................................................ 33

Load Current Versus Time (95W TDP Processor),2 ................................................. 34

Load Current Versus Time (80W TDP Processor),2 ................................................. 35

Load Current Versus Time (60W TDP Processor),2 ................................................. 36

Load Current Versus Time (38W TDP Processor),2 ................................................. 37

2-2

2-3

2-4

2-5

2-6

2-7

2-8

2-9

2-10 VTT Static and Transient Tolerance Loadlines ........................................................ 39

3-1

3-2

3-3

3-4

6-1

6-2

6-3

6-4

6-5

6-6

6-7

6-8

6-9

Processor Package Assembly Sketch .................................................................... 43

Processor Package Drawing (Sheet 1 of 2)............................................................ 45

Processor Package Drawing (Sheet 2 of 2)............................................................ 46

Processor Top-Side Markings .............................................................................. 48

Intel® Xeon® Processor W5580 Thermal Profile.................................................... 91

Intel® Xeon® Processor 5500 Series Advanced SKU Thermal Profile........................ 93

Intel Xeon Processor 5500 Series Standard/Basic SKUs Thermal Profile .................... 95

Intel Xeon Processor 5500 Series Low Power SKU Thermal Profile............................ 97

Intel Xeon Processor L5518 Thermal Profile .......................................................... 99

Intel Xeon Processor L5508 Thermal Profile ........................................................ 101

Case Temperature (TCASE) Measurement Location .............................................. 102

Frequency and Voltage Ordering........................................................................ 104

Ping()............................................................................................................ 108

6-10 Ping() Example ............................................................................................... 108

6-11 GetDIB()........................................................................................................ 109

6-12 Device Info Field Definition............................................................................... 109

6-13 Revision Number Definition............................................................................... 109

6-14 GetTemp() ..................................................................................................... 110

6-15 GetTemp() Example......................................................................................... 110

6-16 PCI Configuration Address ................................................................................ 111

6-17 PCIConfigRd()................................................................................................. 112

6-18 PCIConfigWr() ................................................................................................ 114

6-19 Thermal Status Word....................................................................................... 116

6-20 Thermal Data Configuration Register.................................................................. 117

6-21 Machine Check Read MbxSend() Data Format...................................................... 117

6-22 ACPI T-state Throttling Control Read / Write Definition......................................... 119

6-23 MbxSend() Command Data Format.................................................................... 120

6-24 MbxSend() ..................................................................................................... 120

6-25 MbxGet() ....................................................................................................... 122

6-26 Temperature Sensor Data Format...................................................................... 126

6-27 PECI Power-up Timeline ................................................................................... 128

7-1

7-2

8-1

8-2

8-3

8-4

8-5

8-6

8-7

PROCHOT# POC Timing Requirements ............................................................... 132

Power States .................................................................................................. 133

Boxed Active Heat Sink.................................................................................... 138

Boxed Passive / Active Combination Heat Sink (With Removable Fan) .................... 138

Boxed Passive/Active Combination Heat Sink (with Fan Removed) ......................... 139

Intel Boxed 25.5 mm Tall Passive Heat Sink Solution ........................................... 139

Top Side Baseboard Keep-Out Zones ................................................................. 141

Top Side Baseboard Mounting-Hole Keep-Out Zones ............................................ 142

Bottom Side Baseboard Keep-Out Zones ............................................................ 143

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Intel Xeon Processor 5500 Series Datasheet, Volume 1

5

8-8

8-9

Primary and Secondary Side 3D Height Restriction Zones......................................144

Volumetric Height Keep-Ins...............................................................................145

8-10 Volumetric Height Keep-Ins...............................................................................146

8-11 4-Pin Fan Cable Connector (For Active Heat Sink) ................................................147

8-12 4-Pin Base Baseboard Fan Header (For Active Heat Sink) ......................................148

8-13 Thermal Solution Installation.............................................................................150

8-14 Fan Cable Connector Pin Out For 4-Pin Active Thermal Solution..............................151

Tables

1-1

Intel® Xeon® Processor 5500 Series Feature Set Overview ....................................10

References........................................................................................................12

Processor Power Supply Voltages1 .......................................................................15

Voltage Identification Definition ...........................................................................17

Power-On Configuration (POC[7:0]) Decode ..........................................................22

VTT Voltage Identification Definition.....................................................................23

Signal Groups ...................................................................................................23

Signals With On-Die Termination (ODT)................................................................25

Processor Absolute Minimum and Maximum Ratings ...............................................27

Voltage and Current Specifications.......................................................................27

VCC Static and Transient Tolerance.....................................................................30

1-2

2-1

2-2

2-3

2-4

2-5

2-6

2-7

2-8

2-9

2-10 VCC Overshoot Specifications..............................................................................31

2-11 VTT Static and Transient Tolerance .....................................................................37

2-12 DDR3 Signal Group DC Specifications ...................................................................39

2-13 PECI DC Electrical Limits.....................................................................................40

2-14 RESET# Signal DC Specifications .........................................................................41

2-15 TAP Signal Group DC Specifications......................................................................41

2-16 PWRGOOD Signal Group DC Specifications ............................................................41

2-17 Control Sideband Signal Group DC Specifications ...................................................42

3-1

3-2

3-3

4-1

4-2

5-1

6-1

6-2

6-3

6-4

6-5

6-6

6-7

6-8

6-9

Processor Loading Specifications..........................................................................47

Package Handling Guidelines...............................................................................47

Processor Materials ............................................................................................48

Land Listing by Land Name .................................................................................49

Land Listing by Land Number ..............................................................................67

Signal Definitions...............................................................................................85

Intel® Xeon® Processor W5580 Thermal Specifications..........................................91

Intel Xeon Processor W5580 Thermal Profile..........................................................92

Intel Xeon Processor 5500 Series Advanced SKU Thermal Specifications....................92

Intel Xeon Processor 5500 Series Advanced SKU Thermal Profile A...........................94

Intel Xeon Processor 5500 Series Advanced SKU Thermal Profile B...........................94

Intel Xeon Processor 5500 Series Standard/Basic SKUs Thermal Specifications...........95

Intel Xeon Processor 5500 Series Standard/Basic SKUs Thermal Profile.....................96

Intel Xeon Processor 5500 Series Low Power SKU Thermal Specifications ..................96

Intel Xeon Processor 5500 Series Low Power SKU Thermal Profile ............................98

6-10 Intel Xeon Processor L5518 Thermal Specifications.................................................98

6-11 Intel Xeon Processor L5518 Thermal Profile.........................................................100

6-12 Intel Xeon Processor L5508 Thermal Specifications...............................................100

6-13 Intel Xeon Processor L5508 Thermal Profile.........................................................101

6-14 Summary of Processor-specific PECI Commands ..................................................107

6-15 GetTemp() Response Definition .........................................................................111

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Intel Xeon Processor 5500 Series Datasheet, Volume 1

6-16 PCIConfigRd() Response Definition .................................................................... 112

6-17 PCIConfigWr() Device/Function Support ............................................................. 113

6-18 PCIConfigWr() Response Definition .................................................................... 114

6-19 Mailbox Command Summary ............................................................................ 115

6-20 Counter Definition ........................................................................................... 116

6-21 Machine Check Bank Definitions ........................................................................ 118

6-22 ACPI T-state Duty Cycle Definition..................................................................... 119

6-23 MbxSend() Response Definition......................................................................... 121

6-24 MbxGet() Response Definition........................................................................... 122

6-25 Domain ID Definition ....................................................................................... 124

6-26 Multi-Domain Command Code Reference ............................................................ 124

6-27 Completion Code Pass/Fail Mask........................................................................ 124

6-28 Device Specific Completion Code (CC) Definition.................................................. 125

6-29 Originator Response Guidelines......................................................................... 125

6-30 Error Codes and Descriptions ............................................................................ 127

6-31 PECI Client Response During Power-Up (During ‘Data Not Ready’) ......................... 127

6-32 Power Impact of PECI Commands versus C-states ............................................... 129

6-33 PECI Client Response During S1........................................................................ 129

7-1

7-2

7-3

7-4

8-1

8-2

8-3

Power On Configuration Signal Options............................................................... 131

Coordination of Thread Power States at the Core Level......................................... 133

Processor C-State Power Specifications .............................................................. 135

Processor S-States .......................................................................................... 136

PWM Fan Frequency Specifications For 4-Pin Active Thermal Solution ..................... 151

Fan Specifications For 4-Pin Active Thermal Solution ............................................ 151

Fan Cable Connector Pin Out for 4-Pin Active Thermal Solution.............................. 151

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Intel Xeon Processor 5500 Series Datasheet, Volume 1

7

Revision History

Document

Number

Revision

Number

Description

Date

321321

001

002

•

Initial release

March 2009

June 2011

Added Section 1.3: Statement of Volatility

§

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8

Intel Xeon Processor 5500 Series Datasheet, Volume 1

Introduction

1 Introduction

The Intel^®Xeon^®processor 5500 series is the first-generation server/workstation

multi-core processor to implement key new technologies:

• Integrated Memory Controller

• Point-to-point link interface based on Intel^®QuickPath Technology

The processor is optimized for performance with the power efficiencies of a low-power

microarchitecture to enable smaller, quieter systems.

This document provides DC electrical specifications, differential signaling specifications,

pinout and signal definitions, package mechanical specifications and thermal

requirements, and additional features pertinent to implementation and operation of the

processor. For information on register descriptions, refer to the Intel^®Xeon^®Processor

5500 Series Datasheet, Volume 2.

Intel Xeon processor 5500 series are multi-core processors, based on 45 nm process

technology. The processor family features a range of thermal design power (TDP)

envelopes from 38W TDP up to 130W TDP. These processors feature two Intel

QuickPath Interconnect point-to-point links capable of up to 6.4 GT/s, up to 8 MB of

shared cache, and an Integrated Memory Controller. The processors support all the

existing Streaming SIMD Extensions 2 (SSE2), Streaming SIMD Extensions 3 (SSE3)

and Streaming SIMD Extensions 4 (SSE4). The processors support several Advanced

Technologies: Execute Disable Bit, Intel^®64 Technology, Enhanced Intel SpeedStep^®

Technology, Intel^®Virtualization Technology (Intel^®VT), Intel^®Hyper-Threading

Technology (Intel^®HT Technology), and Intel^®Turbo Boost Technology (Intel^®TBT).

The Intel Xeon processor 5500 series family supports multiple platform segments.

• 2-Socket Workstation Platforms support Intel^®Xeon^®Processor W5580, a 130W

Thermal Design Power (TDP) SKU. These platforms provide optimal overall

performance and reliability, in addition to high-end graphics support. Note, specific

platform usage conditions apply when implementing these processors.

• 2-Socket High Performance Server and High Performance Computing (HPC)

Platforms support Intel Xeon processor 5500 series Advanced SKU (95W TDP).

These platforms provide optimal overall performance.

• 2-Socket Volume Server Platforms support Intel Xeon processor 5500 series

Standard/Basic SKUs (80W TDP). These platforms provide optimal performance per

watt for rack-optimized platforms.

• Ultra Dense Platforms implement Intel Xeon processor 5500 series Low Power SKU

(60W TDP). These processors are intended for dual-processor server blades and

embedded servers.

• Intel^®Xeon^®Processor L5518 with 60W TDP and elevated case temperatures. The

elevated case temperatures are intended to meet the short-term thermal profile

requirements of NEBS Level 3. These 2-Socket processors are ideal for thermally-

constrained form factors in embedded servers, comms and storage markets.

• Intel^®Xeon^®Processor L5508 with 38W TDP and elevated case temperatures. The

elevated case temperatures are intended to meet the short-term thermal profile

requirements of NEBS Level 3. These 2-Socket processors are ideal for thermally-

constrained form factors in embedded servers, comms and storage markets.

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Intel Xeon Processor 5500 Series Datasheet, Volume 1

9

Introduction

• 1-Socket Workstation Platforms support Intel Xeon processor 5500 series SKUs.

These platforms enable a wide range of options for either the performance, power,

or cost sensitive customer.

Note:

All references to “chipset” in this document pertain to the Intel^®5520 chipset and

Intel^®5500 chipset, unless specifically stated otherwise.

Table 1-1.

Intel® Xeon® Processor 5500 Series Feature Set Overview

Feature

Intel Xeon Processor 5500 Series

Cache Sizes

- Instruction Cache = 32 KB, per core

- Data Cache = 32 KB, per core

- 256 KB Mid-Level Cache per core

- 8 MB shared among cores (up to 4)

Data Transfer Rate

Two (2) full-width Intel QuickPath Interconnect links, up to 6.4 GT/s in

each direction

Multi-Core Support

Dual Processor Support

Package

Up to 4 Cores per processor

Up to 2 processors per platform

1366-land FCLGA

1.1

Terminology

A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in

the active state when driven to a low level. For example, when RESET# is low, a reset

has been requested.

A ‘_N’ and ‘_P’ after a signal name refers to a differential pair.

Commonly used terms are explained here for clarification:

• 1366-land FC-LGA package — The Intel Xeon processor 5500 series is available

in a Flip-Chip Land Grid Array (FC-LGA) package, consisting of processor mounted

on a land grid array substrate with an integrated heat spreader (IHS).

• DDR3 — Double Data Rate 3 synchronous dynamic random access memory

(SDRAM) is the name of the new DDR memory standard that is being developed as

the successor to DDR2 SDRAM.

• Enhanced Intel SpeedStep Technology — Enhanced Intel SpeedStep

Technology allows the operating system to reduce power consumption when

performance is not needed.

• Intel Turbo Boost Technology — Intel Turbo Boost Technology is a way to

automatically run the processor core faster than the marked frequency if the part is

operating under power, temperature, and current specifications limits of the

Thermal Design Power (TDP). This results in increased performance of both single

and multi-threaded applications.

• Execute Disable Bit — Execute Disable allows memory to be marked as

executable or non-executable, when combined with a supporting operating system.

If code attempts to run in non-executable memory the processor raises an error to

the operating system. This feature can prevent some classes of viruses or worms

that exploit buffer over run vulnerabilities and can thus help improve the overall

security of the system. See the Intel^®64 and IA-32 Architecture Software

Developer's Manuals for more detailed information.

• Functional Operation — Refers to the normal operating conditions in which all

processor specifications, including DC, AC, signal quality, mechanical, and thermal,

are satisfied.

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10

Intel Xeon Processor 5500 Series Datasheet, Volume 1

Introduction

• Intel Xeon Processor 5500 Series — Includes processor substrate and

integrated heat spreader (IHS).

• Integrated Memory Controller (IMC) — As the term implies, the Memory

Controller is integrated on the processor die.

• Intel QuickPath Interconnect (Intel^®QPI) — A cache-coherent, link-based

Interconnect specification for Intel processors, chipsets, and I/O bridge

components.

• Intel^®64 Architecture — An enhancement to Intel's IA-32 architecture, allowing

the processor to execute operating systems and applications written to take

advantage of Intel^®64.

• Intel Virtualization Technology (Intel^®VT) — A set of hardware

enhancements to Intel server and client platforms that can improve virtualization

solutions. VT provides a foundation for widely-deployed virtualization solutions and

enables more robust hardware assisted virtualization solution.

• Integrated Heat Spreader (IHS) — A component of the processor package used

to enhance the thermal performance of the package. Component thermal solutions

interface with the processor at the IHS surface.

• Jitter — Any timing variation of a transition edge or edges from the defined Unit

Interval (UI).

• LGA1366 Socket — The 1366-land FC-LGA package mates with the system board

through this surface mount, 1366-contact socket.

• Server SKU — A processor Stock Keeping Unit (SKU) to be installed in either

server or workstation platforms. Electrical, power and thermal specifications for

these SKU’s are based on specific use condition assumptions. Server processors

may be further categorized as Advanced, Standard/Basic, and Low Power SKUs. For

further details on use condition assumptions, please refer to the latest Product

Release Qualification (PRQ) Report available via your Customer Quality Engineer

(CQE) contact.

• Storage Conditions — Refers to a non-operational state. The processor may be

installed in a platform, in a tray, or loose. Processors may be sealed in packaging or

exposed to free air. Under these conditions, processor lands should not be

connected to any supply voltages, have any I/Os biased, or receive any clocks.

• Unit Interval (UI) — Signaling convention that is binary and unidirectional. In

this binary signaling, one bit is sent for every edge of the forwarded clock, whether

it be a rising edge or a falling edge. If a number of edges are collected at instances

t₁, t₂, t_n,...., t_kthen the UI at instance “n” is defined as:

UI _n= t _n- t

n - 1

• Workstation SKU — A processor SKU to be installed in workstation platforms

only. Electrical, power and thermal specifications for these processors have been

developed based on Intel’s reliability goals at a reference use condition. In addition,

the processor validation and production test conditions have been optimized based

on these conditions. Operating “Workstation” processors in a server environment or

other application, could impact reliability performance, which means Intel’s

reliability goals may not be met. For further details on use condition assumptions or

reliability performance, please refer to the latest Product Release Qualification

(PRQ) Report available via your Customer Quality Engineer (CQE) contact.

• NEBS — Network Equipment Building System. NEBS is the most common set of

environmental design guidelines applied to telecommunications equipment in the

United States.

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Intel Xeon Processor 5500 Series Datasheet, Volume 1

11

Introduction

1.2

References

Platform designers are strongly encouraged to maintain familiarity with the most up-to-

date revisions of processor and platform collateral.

Table 1-2.

References

Document

Location

Notes

®

AP-485, Intel Processor Identification and the CPUID Instruction

241618

1

®

Intel 64 and IA-32 Architecture Software Developer's Manual

253665

253666

253667

253668

253669

•

Volume 1: Basic Architecture

Volume 2A: Instruction Set Reference, A-M

Volume 2B: Instruction Set Reference, N-Z

Volume 3A: System Programming Guide, Part 1

Volume 3B: Systems Programming Guide, Part 2

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Intel 64 and IA-32 Architectures Optimization Reference Manual

248966

1

®

Intel Virtualization Technology Specification for Directed I/O

D51397-001

Architecture Specification

®

Intel Xeon Processor 5500 Series Datasheet, Volume 2

321322

321323

1

Intel® Xeon® Processor 5500/5600 Series Thermal/Mechanical

Design Guide

®

Intel Xeon Processor 5500 Series Specification Update

321324

1

Entry-Level Electronics-Bay Specifications: A Server System

Infrastructure (SSI) Specification for Entry Pedestal Servers and

Workstations

www.ssiforum.org

ACPI Specifications

www.acpi.info

Notes:

1.

Document is available publicly at http://www.intel.com.

1.3

Statement of Volatility

No Intel Xeon processor 5500 series product family processors retain any end user data

when powered down and/or when the parts are physically removed from the socket.

§

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12

Intel Xeon Processor 5500 Series Datasheet, Volume 1

Intel® Xeon® Processors 5500 Series Electrical Specifications

2 Intel^®Xeon^®Processors 5500

Series Electrical Specifications

2.1

Processor Signaling

Intel Xeon processor 5500 series include 1366 lands, which utilize various signaling

technologies. Signals are grouped by electrical characteristics and buffer type into

various signal groups. These include Intel QuickPath Interconnect, DDR3 (Reference

Clock, Command, Control and Data), Platform Environmental Control Interface (PECI),

Processor Sideband, System Reference Clock, Test Access Port (TAP), and Power/Other

signals. Refer to Table 2-5 for details.

Detailed layout, routing, and termination guidelines corresponding to these signal

groups can be found in the applicable platform design guide (Refer to Section 1.2).

Intel strongly recommends performing analog simulations of all interfaces. Please refer

to Section 1.2 for signal integrity model availability.

®

2.1.1

Intel QuickPath Interconnect

Intel Xeon processor 5500 series provide two Intel QuickPath Interconnect ports for

high speed serial transfer between other enabled components. Each port consists of

two uni-directional links (for transmit and receive). A differential signaling scheme is

utilized, which consists of opposite-polarity (D_P, D_N) signal pairs.

On-die termination (ODT) is included on the processor silicon and terminated to V_SS.

Intel chipsets also provide ODT, thus eliminating the need to terminate on the system

board. Figure 2-1 illustrates the active ODT.

Figure 2-1. Active ODT for a Differential Link Example

T_X

R_X

Signal

R_TT

2.1.2

DDR3 Signal Groups

The memory interface utilizes DDR3 technology, which consists of numerous signal

groups. These include: Reference Clocks, Command Signals, Control Signals, and Data

Signals. Each group consists of numerous signals, which may utilize various signaling

technologies. Please refer to Table 2-5 for further details.

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Intel® Xeon® Processors 5500 Series Electrical Specifications

2.1.3

Platform Environmental Control Interface (PECI)

PECI is an Intel proprietary interface that provides a communication channel between

Intel processors and chipset components to external thermal monitoring devices. The

Intel Xeon Processor 5500 Series contains a Digital Thermal Sensor (DTS) that reports

a relative die temperature as an offset from Thermal Control Circuit (TCC) activation

temperature. Temperature sensors located throughout the die are implemented as

analog-to-digital converters calibrated at the factory. PECI provides an interface for

external devices to read processor temperature, perform processor manageability

functions, and manage processor interface tuning and diagnostics. Please refer to

Section 6 for processor specific implementation details for PECI.

The PECI interface operates at a nominal voltage set by V_TTD. The set of DC electrical

specifications shown in Table 2-13 is used with devices normally operating from a V_TTD

interface supply.

2.1.3.1

Input Device Hysteresis

The PECI client and host input buffers must use a Schmitt-triggered input design for

improved noise immunity. Please refer to Figure 2-2 and Table 2-13.

Figure 2-2. Input Device Hysteresis

V_TTD

Maximum V_P

PECI High Range

Minimum V_P

Maximum V_N

Minimum

Hysteresis Signal Range

Valid Input

Minimum V_N

PECI Ground

PECI Low Range

2.1.4

2.1.5

Processor Sideband Signals

Intel Xeon processor 5500 series include sideband signals that provide a variety of

functions. Details can be found in Table 2-5 and the applicable platform design guide.

All Asynchronous Processor Sideband signals are required to be asserted/deasserted

for at least eight BCLKs in order for the processor to recognize the proper signal state.

See Table 2-17 for DC specifications.

System Reference Clock

The processor core, processor uncore, Intel QuickPath Interconnect link, and DDR3

memory interface frequencies are generated from BCLK_DP and BCLK_DN signals.

There is no direct link between core frequency and Intel QuickPath Interconnect link

frequency (for example, no core frequency to Intel QuickPath Interconnect multiplier).

The processor maximum core frequency, Intel QuickPath Interconnect link frequency

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Intel® Xeon® Processors 5500 Series Electrical Specifications

and DDR3 memory frequency are set during manufacturing. It is possible to override

the processor core frequency setting using software. This permits operation at lower

core frequencies than the factory set maximum core frequency.

The processor core frequency is configured during reset by using values stored within

the device during manufacturing. The stored value sets the lowest core multiplier at

which the particular processor can operate. If higher speeds are desired, the

appropriate ratio can be configured via the IA32_PERF_CTL MSR.

Clock multiplying within the processor is provided by the internal phase locked loop

(PLL), which requires a constant frequency BCLK_DP, BCLK_DN input, with exceptions

for spread spectrum clocking.

2.1.6

Test Access Port (TAP) Signals

Due to the voltage levels supported by other components in the Test Access Port (TAP)

logic, it is recommended that the processor(s) be first in the TAP chain and followed by

any other components within the system. A translation buffer should be used to

connect to the rest of the chain unless one of the other components is capable of

accepting an input of the appropriate voltage. Similar considerations must be made for

TCK, TDO, TMS, and TRST#. Two copies of each signal may be required with each

driving a different voltage level.

Processor TAP signal DC specifications can be found in Table 2-17.

Note:

While TDI, TMS and TRST# do not include On-Die Termination (ODT), these signals are

weakly pulled-up via a 1-5 kΩ resistor to V_TT.

While TCK does not include ODT, this signal is weakly pulled-down via a 1-5 kΩ resistor

to V_SS.

2.1.7

Power / Other Signals

Processors also include various other signals including power/ground, sense points, and

analog inputs. Details can be found in Table 2-5 and the applicable platform design

guide.

Table 2-1 outlines the required voltage supplies necessary to support Intel Xeon

processor 5500 series.

Table 2-1. Processor Power Supply Voltages¹

Power Rail

Nominal Voltage

Notes

See Table 2-9;

Figure 2-3

Each processor includes a dedicated VR11.1 regulator.

V_CC

1.80 V

1.50 V

Each processor includes dedicated V

and PLL circuits.

V_CCPLL

V_DDQ

CCPLL

Each processor and DDR3 stack shares a dedicated voltage regulator.

Each processor includes a dedicated VR11.0 regulator.

V

= V

+ V

; P1V1_Vtt is VID[4:2] controlled,

TT

TTA

TTD

See Table 2-11;

Figure 2-10

VID range is 1.0255-1.2000 V; 20 mV offset (see Table 2-4); V

V_TTA, V_TTD

TT

represents a typical voltage. V

31.5 mV offset from V (typ).

and V

loadlines represent a

TT_MIN

TT_MAX

TT

Note:

1. Refer to Table 2-8 for voltage and current specifications.

Further platform and processor power delivery details can be found in the Intel^®Xeon^®

Processor 5500 Platform Design Guide (PDG).

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Intel® Xeon® Processors 5500 Series Electrical Specifications

2.1.7.1

Power and Ground Lands

For clean on-chip power distribution, processors include lands for all required voltage

supplies. These include:

• 210 each V_CC(271 ea. V_SS) lands must be supplied with the voltage determined by

the VID[7:0] signals. Table 2-2 defines the voltage level associated with each core

VID pattern. Table 2-9 and Figure 2-3 represent V_CCstatic and transient limits.

• 3 each V_CCPLLlands, connected to a 1.8 V supply, power the Phase Lock Loop (PLL)

clock generation circuitry. An on-die PLL filter solution is implemented within the

Intel Xeon processor 5500 series.

• 45 each V_DDQ(17 ea. V_SS) lands, connected to a 1.50 V supply, provide power to

the processor DDR3 interface. This supply also powers the DDR3 memory

subsystem.

• 7 each V_TTA(5 ea. V_SS) and 26 ea. V_TTD(17 ea. V_SS) lands must be supplied with

the voltage determined by the VTT_VID[4:2] signals. Coupled with a 20 mV offset,

this corresponds to a VTT_VID pattern of ‘010xxx10’. Table 2-4 specifies the

voltage levels associated with each VTT_{_}VID pattern. Table 2-11 and Figure 2-10

represent V_TTstatic and transient limits.

All V_CC, V_CCPLL,V_DDQ,V_TTA, and V_TTDlands must be connected to their respective

processor power planes, while all V_SSlands must be connected to the system ground

plane. Refer to the Intel^®Xeon^®Processor 5500 Platform Design Guide (PDG) for

decoupling, voltage plane and routing guidelines for each power supply voltage.

2.1.7.2

Decoupling Guidelines

Due to its large number of transistors and high internal clock speeds, the Intel Xeon

processor 5500 series is capable of generating large current swings between low and

full power states. This may cause voltages on power planes to sag below their

minimum values if bulk decoupling is not adequate. Larger bulk storage (C_BULK), such

as electrolytic capacitors, supply current during longer lasting changes in current

demand, for example coming out of an idle condition. Similarly, they act as a storage

well for current when entering an idle condition from a running condition. Care must be

taken in the baseboard design to ensure that the voltages provided to the processor

remains within the specifications listed in Table 2-8. Failure to do so can result in timing

violations or reduced lifetime of the processor.

2.1.7.3

Processor V

Voltage Identification (VID) Signals

CC

The voltage set by the VID signals is the maximum reference voltage regulator (VR)

output to be delivered to the processor V_CClands. VID signals are CMOS push/pull

outputs. Please refer to Table 2-17 for the DC specifications for these and other

processor sideband signals.

Individual processor VID values may be calibrated during manufacturing such that two

processor units with the same core frequency may have different default VID settings.

The Intel Xeon processor 5500 series uses eight voltage identification signals,

VID[7:0], to support automatic selection of core power supply voltages. Table 2-2

specifies the voltage level corresponding to the state of VID[7:0]. A ‘1’ in this table

refers to a high voltage level and a ‘0’ refers to a low voltage level. If the processor

socket is empty (SKTOCC# high), or the voltage regulation circuit cannot supply the

voltage that is requested, the voltage regulator must disable itself.

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The Intel Xeon processor 5500 series provides the ability to operate while transitioning

to an adjacent VID and its associated processor core voltage (V_CC). This is represented

by a DC shift in the loadline. It should be noted that a low-to-high or high-to-low

voltage state change may result in as many VID transitions as necessary to reach the

target core voltage. Transitions above the maximum specified VID are not permitted.

Table 2-8 includes VID step sizes and DC shift ranges. Minimum and maximum voltages

must be maintained as shown in Table 2-9.

The VRM or EVRD utilized must be capable of regulating its output to the value defined

by the new VID. DC specifications for dynamic VID transitions are included in Table 2-8

and Table 2-9.

Power source characteristics must be guaranteed to be stable whenever the supply to

the voltage regulator is stable.

Table 2-2.

Voltage Identification Definition (Sheet 1 of 5)

VID7

VID6

VID5

VID4

VID3

VID2

VID1

VID0

V

CC_MAX

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

OFF

1.60000

1.59375

1.58750

1.58125

1.57500

1.56875

1.56250

1.55625

1.55000

1.54375

1.53750

1.53125

1.52500

1.51875

1.51250

1.50625

1.50000

1.49375

1.48750

1.48125

1.47500

1.46875

1.46250

1.45625

1.45000

1.44375

1.43750

1.43125

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Table 2-2.

Voltage Identification Definition (Sheet 2 of 5)

VID7

VID6

VID5

VID4

VID3

VID2

VID1

VID0

V

CC_MAX

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.42500

1.41875

1.41250

1.40625

1.40000

1.39375

1.38750

1.38125

1.37500

1.36875

1.36250

1.35625

1.35000

1.34375

1.33750

1.33125

1.32500

1.31875

1.31250

1.30625

1.30000

1.29375

1.28750

1.28125

1.27500

1.26875

1.26250

1.25625

1.25000

1.24375

1.23750

1.23125

1.22500

1.21875

1.21250

1.20625

1.20000

1.19375

1.18750

1.18125

1.17500

1.16875

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Table 2-2.

Voltage Identification Definition (Sheet 3 of 5)

VID7

VID6

VID5

VID4

VID3

VID2

VID1

VID0

V

CC_MAX

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.16250

1.15625

1.15000

1.14375

1.13750

1.13125

1.12500

1.11875

1.11250

1.10625

1.10000

1.09375

1.08750

1.08125

1.07500

1.06875

1.06250

1.05625

1.05000

1.04375

1.03750

1.03125

1.02500

1.01875

1.01250

1.00625

1.00000

0.99375

0.98750

0.98125

0.97500

0.96875

0.96250

0.95625

0.95000

0.94375

0.93750

0.93125

0.92500

0.91875

0.91250

0.90625

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Table 2-2.

Voltage Identification Definition (Sheet 4 of 5)

VID7

VID6

VID5

VID4

VID3

VID2

VID1

VID0

V

CC_MAX

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.90000

0.89375

0.88750

0.88125

0.87500

0.86875

0.86250

0.85625

0.85000

0.84375

0.83750

0.83125

0.82500

0.81875

0.81250

0.80625

0.80000

0.79375

0.78750

0.78125

0.77500

0.76875

0.76250

0.75625

0.75000

0.74375

0.73750

0.73125

0.72500

0.71875

0.71250

0.70625

0.70000

0.69375

0.68750

0.68125

0.67500

0.66875

0.66250

0.65625

0.65000

0.64375

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Table 2-2.

Voltage Identification Definition (Sheet 5 of 5)

VID7

VID6

VID5

VID4

VID3

VID2

VID1

VID0

V

CC_MAX

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.63750

0.63125

0.62500

0.61875

0.61250

0.60625

0.60000

0.59375

0.58750

0.58125

0.57500

0.56875

0.56250

0.55625

0.55000

0.54375

0.53750

0.53125

0.52500

0.51875

0.51250

0.50625

0.50000

OFF

Notes:

1.

When the “11111111” VID pattern is observed, or when the SKTOCC# pin is high, the voltage regulator

output should be disabled.

2.

3.

Shading denotes the expected VID range of the Intel Xeon processor 5500 series.

The VID range includes VID transitions that may be initiated by thermal events, Extended HALT state

transitions (see Section 7.2), higher C-States (see Section 7.2) or Enhanced Intel SpeedStep Technology

®

transitions (see Section 7.5). The Extended HALT state must be enabled for the processor to

remain within its specifications.

Once the VRM/EVRD is operating after power-up, if either the Output Enable signal is de-asserted or a

specific VID off code is received, the VRM/EVRD must turn off its output (the output should go to high

impedance) within 500 ms and latch off until power is cycled.

4.

2.1.7.3.1

Power-On Configuration (POC) Logic

VID[7:0] signals also serve a second function. During power-up, Power-On

Configuration POC[7:0] functionality is multiplexed onto these signals via 1-5 kΩ pull-

up or pull down resistors located on the baseboard. These values provide voltage

regulator keying (VID[7]), inform the processor of the platforms power delivery

capabilities (MSID[2:0]), and program the gain applied to the ISENSE input

(CSC[2:0]). Table 2-3 maps VID signals to the corresponding POC functionality.

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Table 2-3.

Power-On Configuration (POC[7:0]) Decode

Function

Bits

POC Settings

Description

VR_Key

VID[7]

0b for VR11.1

Electronic safety key

distinguishing VR11.1

Spare

VID[6]

0b (default)

Reserved for future use

CSC[2:0]

VID[5:3]

-000

-001

-010

-011

-100

-101

-111

Feature Disabled

ICC_MAX = 40A

Current Sensor Configuration

(CSC) programs the gain

applied to the ISENSE A/D

output. ISENSE data is then

used to dynamically calculate

current and power.

1

ICC_MAX = 50A

ICC_MAX = 80A

ICC_MAX = 100A

ICC_MAX = 120A

2

ICC_MAX = 150A

MSID[2:0]

VID[2:0]

-001

-011

-100

-101

-110

38W TDP / 40A ICC_MAX

60W TDP / 80A ICC_MAX

80W TDP / 100A ICC_MAX

95W TDP / 120A ICC_MAX

MSID[2:0] signals are provided

to indicate the Market Segment

for the processor and may be

used for future processor

compatibility or keying. See

130W TDP / 150A ICC_MAX Figure 7-1 for platform timing

requirements of the MSID[2:0]

signals.

Notes:

1. This setting is defined for future use; no specific Intel Xeon processor 5500 series SKU is defined with ICC_MAX

= 50A

2. General rule: Set PWM IMON slope to: 900 mV=IMAX, where IMAX =IccMAX with one exception: for Intel Xeon

Processor W5580 set IMON slope to 900 mV=180A, but for all other SKUs they have to match, as shown

above. Consult your PWM data sheet for the IMON slope setting.

Some POC signals include specific timing requirements. Please refer to Section 7.1 for

further details.

2.1.7.4

Processor V Voltage Identification (VTT_VID) Signals

TT

The voltage set by the VTT_VID signals is the typical reference voltage regulator (VR)

output to be delivered to the processor V_TTAand V_TTDlands. It is expected that one

regulator will supply all V_TTAand V_TTDlands. VTT_VID signals are CMOS push/pull

outputs. Please refer to Table 2-17 for the DC specifications for these signals.

Individual processor VTT_VID values may be calibrated during manufacturing such that

two processor units with the same core frequency may have different default VTT_VID

settings.

The Intel Xeon processor 5500 series utilizes three voltage identification signals to

support automatic selection of power supply voltages. These correspond to

VTT_VID[4:2]. The V_TTvoltage level delivered to the processor lands must also

encompass a 20 mV offset (See Table 2-4; V_{TT_TYP}) above the voltage level

corresponding to the state of the VTT_VID[7:0] signals (See Table 2-4; VR 11.0

Voltage). Table 2-11 and Figure 2-10 provide the resulting static and transient

tolerances. Please note that the maximum and minimum electrical loadlines are defined

by a 31.5 mV tolerance band above and below V_{TT_TYP}values.

Power source characteristics must be guaranteed to be stable whenever the supply to

the voltage regulator is stable.

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Table 2-4.

V_TTVoltage Identification Definition

VR 11.0

Voltage

V

TT_TYP

(Voltage + Offset)

VID7 VID6

VID5

VID4

VID3 VID2 VID1 VID0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1.200 V

1.175 V

1.150 V

1.125 V

1.100 V

1.075 V

1.050 V

1.025 V

1.220 V

1.195 V

1.170 V

1.145 V

1.120 V

1.095 V

1.070 V

1.045 V

2.1.8

Reserved or Unused Signals

All Reserved (RSVD) signals must remain unconnected. Connection of these signals to

V_CC, V_TTA, V_TTD, V_DDQ, V_SS, or any other signal (including each other) can result in

component malfunction or incompatibility with future processors. See Section 4 for the

land listing and the location of all Reserved signals.

For reliable operation, connect unused inputs or bidirectional signals to an appropriate

signal level. Unused Intel QuickPath Interconnect input and output pins can be left

floating. Unused active high inputs should be connected through a resistor to ground

(V_SS). Unused outputs can be left unconnected; however, this may interfere with some

TAP functions, complicate debug probing, and prevent boundary scan testing. A resistor

must be used when tying bidirectional signals to power or ground. When tying any

signal to power or ground, including a resistor will also allow for system testability.

Resistor values should be within ± 20% of the impedance of the baseboard trace,

unless otherwise noted in the appropriate platform design guidelines.

TAP signals do not include on-die termination, however they may include resistors on

package (refer to Section 2.1.6 for details). Inputs and utilized outputs must be

terminated on the baseboard. Unused outputs may be terminated on the baseboard or

left unconnected. Note that leaving unused outputs unterminated may interfere with

some TAP functions, complicate debug probing, and prevent boundary scan testing.

2.2

Signal Group Summary

Signals are combined in Table 2-5 by buffer type and characteristics. “Buffer Type”

denotes the applicable signaling technology and specifications.

Table 2-5.

Signal Groups (Sheet 1 of 2)

1

Signal Group

Buffer Type

Signals

Intel QuickPath Interconnect Signals

Differential

Single ended

Intel QuickPath Interconnect Input

QPI[0/1]_DRX_D[N/P][19:0],

QPI[0/1]_CLKRX_DP, QPI[0/1]_CLKRX_DN

Intel QuickPath Interconnect Output

QPI[0/1]_DTX_D[N/P][19:0],

QPI[0/1]_CLKTX_DP, QPI[0/1]_CLKTX_DN

Analog Input

2

QPI[0/1]_COMP

DDR3 Reference Clocks

Differential

Output

DDR{0/1/2}_CLK_[P/N][3:0]

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Table 2-5.

Signal Groups (Sheet 2 of 2)

1

Signal Group

Buffer Type

Signals

2

DDR3 Command Signals

Single ended

CMOS Output

DDR{0/1/2}_RAS#, DDR{0/1/2}_CAS#,

DDR{0/1/2}_WE#, DDR{0/1/2}_MA[15:0],

DDR{0/1/2}_BA[2:0], DDR{0/1/2}_MA_PAR

Single ended

Asynchronous Output

DDR{0/1/2}_RESET#

2

DDR3 Control Signals

Single ended

CMOS Output

DDR{0/1/2}_CS#[7:0], DDR{0/1/2}_ODT[5:0],

DDR{0/1/2}_CKE[3:0]

Analog Input

DDR_VREF, DDR_COMP[2:0]

2

DDR3 Data Signals

Single ended

Differential

CMOS Input/Output

DDR{0/1/2}_DQ[63:0], DDR{0/1/2}_ECC[7:0]

DDR{0/1/2}_DQS_[N/P][17:0]

CMOS Input/Output

Asynchronous Input

Single ended

DDR{0/1/2}_PAR_ERR#[2:0],

DDR_THERM#

Platform Environmental Control Interface (PECI)

Single ended Asynchronous Input/Output

PECI

Processor Sideband Signals

Single ended

GTL Input/Output

BPM#[7:0], CAT_ERR#

PECI_ID#

Asynchronous Input

Asynchronous GTL Output

Asynchronous GTL Input

Asynchronous GTL Input/Output

Asynchronous CMOS Output

CMOS Output

PRDY#, THERMTRIP#

PREQ#

PROCHOT#

PSI#

VID[7:6],

VID[5:3]/CSC[2:0],

VID[2:0]/MSID[2:0],

VTT_VID[4:2]

System Reference Clock

Differential Input

Test Access Port (TAP) Signals

BCLK_DP, BCLK_DN

Differential

Single ended

CMOS Output

Input

BCLK_ITP_DP, BCLK_ITP_DN

TCK, TDI, TMS, TRST#

TDO

GTL Output

PWRGOOD Signals

Single ended

Asynchronous Input

CCPWRGOOD, VDDPWRGOOD, VTTPWRGOOD

RESET#

RESET Signal

Single ended

Asynchronous Input

Power/Other Signals

Power / Ground

V

, V

, V , V

, V

TTD SS

CC

CCPLL

DDQ

TTA

Analog Input

Sense Points

COMP0, ISENSE

VCCSENSE, VSSSENSE, VSS_SENSE_VTTD,

VTTD_SENSE

Other

SKTOCC#, DBR#

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Intel Xeon Processor 5500 Series Datasheet, Volume 1

Intel® Xeon® Processors 5500 Series Electrical Specifications

Notes:

1. Refer to Section 4 for land assignments and Section 5 for signal definitions.

2. DDR{0/1/2} refers to DDR3 Channel 0, DDR3 Channel1 and DDR3 Channel 2.

Signals that include on-die termination (ODT) are listed in Table 2-6.

Table 2-6. Signals With On-Die Termination (ODT)

1

Intel QuickPath Interface Signal Group

QPI[1:0]_DRX_DP[19:0], QPI[1:0]_DRX_DN[19:0], QPI[1:0]_TRX_DP[19:0], QPI[1:0]_TRX_DN[19:0],

QPI[0/1]_CLKRX_D[N/P], QPI[0/1]_CLKTX_D[N/P]

2

DDR3 Signal Group

DDR{0/1/2}_DQ[63:0], DDR{0/1/2}_DQS_[N/P][17:0], DDR{0/1/2}_ECC[7:0],

3

DDR{0/1/2}_PAR_ERR#[2:0]

Processor Sideband Signal Group

6

7

6

BPM#[7:0] , PECI_ID# , PREQ#

Test Access Port (TAP) Signal Group

4

5

TCK , TDI , TMS , TRST#

Power/Other Signal Group

8

VCCPWRGOOD, VDDPWRGOOD, VTTPWRGOOD

Notes:

1.

2.

3.

4.

5.

6.

7.

8.

Unless otherwise specified, signals have ODT in the package with a 50 Ω pull-down to V

.

SS

Unless otherwise specified, all DDR3 signals are terminated to V

DDR{0/1/2}_PAR_ERR#[2:0] are terminated to V

/2.

DDQ

DDQ.

TCK does not include ODT, this signal is weakly pulled-down via a 1-5 kΩ resistor to V

.

SS

TDI, TMS, TRST# do not include ODT, these signals are weakly pulled-up via 1-5kΩ resistor to V .

TT

BPM[7:0]# and PREQ# signals have ODT in package with 35 Ω pull-ups to V

TT.

PECI_ID# has ODT in package with a 1-5 kΩ pull-up to V .

TT

VCCPWRGOOD, VDDPWRGOOD, and VTTPWRGOOD have ODT in package with a 5-20 kΩ pull-down to V

.

SS

2.3

Mixing Processors

Intel supports dual processor (DP) configurations consisting of processors:

1. from the same power optimization segment

2. that support the same maximum Intel QuickPath Interconnect and DDR3 memory

speeds

3. that share symmetry across physical packages with respect to the number of

logical processor per package, number of cores per package, number of Intel

QuickPath interfaces, and cache topology

4. that have identical Extended Family, Extended Model, Processor Type, Family Code

and Model Number as indicated by the function 1 of the CPUID instruction

Note:

Processors must operate with the same Intel QuickPath Interconnect, DDR3 memory,

and core frequency.

While Intel does nothing to prevent processors from operating together, some

combinations may not be supported due to limited validation, which may result in

uncharacterized errata. Coupling this fact with the large number of Intel Xeon

processor 5500 series attributes, the following population rules and stepping matrix

have been developed to clearly define supported configurations.

1. Processors must be of the same power-optimization segment. This insures

processors include the same maximum Intel QuickPath Interconnect and DDR3

operating speeds and cache sizes.

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Intel® Xeon® Processors 5500 Series Electrical Specifications

2. Processors must operate at the same core frequency. Note, processors within the

same power-optimization segment supporting different maximum core frequencies

(for example, a 2.93 GHz / 95 W and 2.66 GHz / 95 W) can be operated within a

system. However, both must operate at the highest frequency rating commonly

supported. Mixing components operating at different internal clock frequencies is

not supported and will not be validated by Intel.

3. Processors must share symmetry across physical packages with respect to the

number of logical processors per package, number of cores per package (but not

necessarily the same subset of cores within the packages), number of Intel

QuickPath Interconnect interfaces, and cache topology.

4. Mixing dissimilar steppings is only supported with processors that have identical

Extended Family, Extended Model, Processor Type, Family Code and Model Number

as indicated by the function 1 of the CPUID instruction. Mixing processors of

different steppings but the same model (as per CPUID instruction) is supported.

Details regarding the CPUID instruction are provided in the AP-485,

Intel^®Processor Identification and the CPUID Instruction application note and the

Intel^®64 and IA-32 Architectures Software Developer’s Manual, Volume 2A.

5. After AND’ing the feature flag and extended feature flags from the installed

processors, any processor whose set of feature flags exactly matches the AND’ed

feature flags can be selected by the BIOS as the BSP. If no processor exactly

matches the AND’ed feature flag values, then the processor with the numerically

lower CPUID should be selected as the BSP.

6. Intel requires that the proper microcode update be loaded on each processor

operating within the system. Any processor that does not have the proper

microcode update loaded is considered by Intel to be operating out of specification.

7. Customers are fully responsible for the validation of their system configuration.

2.4

2.5

Flexible Motherboard Guidelines (FMB)

The Flexible Motherboard (FMB) guidelines are estimates of the maximum values the

Intel Xeon processor 5500 series will have over certain time periods. The values are

only estimates and actual specifications for future processors may differ. Processors

may or may not have specifications equal to the FMB value in the foreseeable future.

System designers should meet the FMB values to ensure their systems will be

compatible with future Intel Xeon processor 5500 series.

Absolute Maximum and Minimum Ratings

Table 2-7 specifies absolute maximum and minimum ratings which lie outside the

functional limits of the processor. Only within specified operation limits, can

functionality and long-term reliability be expected.

At conditions outside functional operation condition limits, but within absolute

maximum and minimum ratings, neither functionality nor long-term reliability can be

expected. If a device is returned to conditions within functional operation limits after

having been subjected to conditions outside these limits, but within the absolute

maximum and minimum ratings, the device may be functional, but with its lifetime

degraded depending on exposure to conditions exceeding the functional operation

condition limits.

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Intel Xeon Processor 5500 Series Datasheet, Volume 1

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At conditions exceeding absolute maximum and minimum ratings, neither functionality

nor long-term reliability can be expected. Moreover, if a device is subjected to these

conditions for any length of time then, when returned to conditions within the

functional operating condition limits, it will either not function or its reliability will be

severely degraded.

Although the processor contains protective circuitry to resist damage from static

electric discharge, precautions should always be taken to avoid high static voltages or

electric fields.

Table 2-7.

Processor Absolute Minimum and Maximum Ratings

1,2

Symbol

Parameter

Min

Nominal

Max

Unit

Notes

Processor core voltage with respect to V

Processor PLL voltage with respect to V

-0.300

1.350

V

V_CC

V_CCPLL

V_DDQ

SS

1.800

1.500

4

SS

Processor I/O supply voltage for DDR3

with respect to V

SS

Processor uncore analog voltage with

respect to V

0.825

1.350

V

3

V_TTA

V_TTD

SS

Processor uncore digital voltage with

respect to V

SS

Processor case temperature

See

Section 6

See

Section 6

°C

T_CASE

Storage temperature

-40

85

°C

5,6,7

T_STORAGE

Analog input voltage with respect to Vss

for sensing Core current consumption

-0.30

1.150

V

V_ISENSE

Notes:

1.

For functional operation, all processor electrical, signal quality, mechanical and thermal specifications must

be satisfied.

Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor.

2.

3.

4.

5.

V

and V

should be derived from the same voltage regulator (VR).

TTA

TTD

5% tolerance.

Storage temperature is applicable to storage conditions only. In this scenario, the processor must not

receive a clock, and no lands can be connected to a voltage bias. Storage within these limits will not affect

the long-term reliability of the device. For functional operation, please refer to the processor case

temperature specifications.

6.

7.

This rating applies to the processor and does not include any tray or packaging.

Failure to adhere to this specification can affect the long-term reliability of the processor.

2.6

Processor DC Specifications

DC specifications are defined at the processor pads, unless otherwise noted.

DC specifications are only valid while meeting specifications for case temperature

(T_CASEspecified in Section 6), clock frequency, and input voltages. Care should be

taken to read all notes associated with each specification.

Table 2-8.

Voltage and Current Specifications (Sheet 1 of 3)

Voltage

Plane

1

Symbol

Parameter

Min

Typ

Max

Unit

Notes

VID

V

VID Range

-

0.750

1.350

V

2,3

CC

V

Core Voltage

(Launch - FMB)

V

3,4,6,7,11

CC

See Table 2-9 and Figure 2-3

6.250

V

VID step size during a

transition

-

mV

V

9

VID_STEP

V

PLL Voltage

(DC + AC specification)

V

0.95*V

1.800

1.05*V

CCPLL

10

CCPLL

(Typ)

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Table 2-8.

Voltage and Current Specifications (Sheet 2 of 3)

Voltage

Plane

1

Symbol

Parameter

Min

Typ

Max

1.05*V

Unit

Notes

V

I/O Voltage for DDR3

(DC + AC specification)

V

0.95*V

1.500

V

10

DDQ

(Typ)

VTT_VID

V

VID Range

-

1.045

1.220

V

2,3

TT

V

Uncore Voltage

(Launch - FMB)

V

See Table 2-11 and Figure 2-10

3,5,8,11

TT

I

Max. Processor Current:

Intel Xeon Processor

W5580

(TDP = 130W)

(Launch - FMB)

V

150

1.1

9

6

22

A

11

CC_MAX

CC

®

I

CCPLL_MAX

V

CCPLL

I

DDQ_MAX

I

V

DDQ

TT_MAX

V

TTA

V

TTD

Max. Processor Current:

Intel Xeon Processor

5500 Series Advanced

SKU

V

120

1.1

9

6

22

A

11

CC

V

CCPLL

V

DDQ

V

TTA

(TDP = 95W)

V

TTD

(Launch - FMB)

Max. Processor Current:

Intel Xeon Processor

5500 Series

Standard/Basic SKU

(TDP = 80W)

V

100

1.1

9

6

22

A

CC

V

CCPLL

V

DDQ

V

TTA

TTD

(Launch - FMB)

Max. Processor Current:

Intel Xeon Processor

5500 Series Low Power

SKU

(TDP = 60W)

(Launch - FMB)

V

80

1.1

9

6

20

A

CC

V

CCPLL

V

DDQ

V

TTA

TTD

Max. Processor Current:

Intel Xeon Processor

L5518

(TDP = 60W)

(Launch - FMB)

V

80

1.1

9

6

20

A

11

CC

®

V

CCPLL

V

DDQ

V

TTA

V

TTD

Max. Processor Current:

V

40

1.1

9

6

20

A

CC

®

Intel Xeon Processor

L5508

V

CCPLL

V

DDQ

(TDP = 38W)

V

TTA

(Launch - FMB)

V

TTD

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Table 2-8.

Voltage and Current Specifications (Sheet 3 of 3)

Voltage

Plane

1

Symbol

Parameter

Min

Typ

Max

Unit

Notes

I

Thermal Design

Current:

Intel Xeon Processor

W5580

(TDP = 130W)

V

110

1.1

9

6

22

A

11,12

CC_TDC

CC

I

CCPLL_TDC

V

CCPLL

I

DDQ_TDC

I

V

DDQ

TT_TDC

V

TTA

V

TTD

(Launch - FMB)

Thermal Design

Current:

Intel Xeon Processor

5500 Series Advanced

SKU

V

85

1.1

9

6

22

A

11,12

CC

V

CCPLL

V

DDQ

V

TTA

(TDP = 95W)

V

TTD

(Launch - FMB)

Thermal Design

Current:

Intel Xeon Processor

5500 Series

Standard/Basic SKU

(TDP = 80W)

(Launch - FMB)

V

70

1.1

9

6

22

A

11,12

CC

V

CCPLL

V

DDQ

V

TTA

V

TTD

Thermal Design

Current:

V

60

1.1

9

6

20

A

CC

V

CCPLL

Intel Xeon Processor

5500 Series Low Power

SKU

V

DDQ

V

TTA

(TDP = 60W)

V

TTD

(Launch - FMB)

Thermal Design

Current:

Intel Xeon Processor

L5518

(TDP = 60W)

(Launch - FMB)

V

60

1.1

9

6

20

A

11,12

13,14

CC

V

CCPLL

V

DDQ

V

TTA

TTD

Thermal Design

Current:

Intel Xeon Processor

L5508

(TDP = 38W)

V

28

1.1

9

6

20

A

CC

V

CCPLL

V

DDQ

V

TTA

V

TTD

(Launch - FMB)

I

DDR3 System Memory

Interface Supply

Current in Standby

State

V

1.0

A

DDQ_S3

DDQ

Notes:

1. Unless otherwise noted, all specifications in this table apply to all processors. These specifications are based

on pre-silicon characterization and will be updated as further data becomes available.

2. Individual processor VID and/or VTT_VID values may be calibrated during manufacturing such that two

devices at the same speed may have different settings.

3. These voltages are targets only. A variable voltage source should exist on systems in the event that a

different voltage is required.

4. The V voltage specification requirements are measured across vias on the platform for the VCCSENSE and

CC

VSSSENSE pins close to the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe

capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the probe should be

less than 5 mm. Ensure external noise from the system is not coupled in the scope probe.

5. The V voltage specification requirements are measured across vias on the platform for the VTTD_SENSE

TT

and VSS_SENSE_VTTD lands close to the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum

probe capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the probe should

be less than 5 mm. Ensure external noise from the system is not coupled in the scope probe.

6. Refer to Table 2-9 and corresponding Figure 2-3. The processor should not be subjected to any static V

CC

level that exceeds the V

associated with any particular current. Failure to adhere to this specification

CC_MAX

can shorten processor lifetime.

7. Minimum V and maximum I are specified at the maximum processor case temperature (T ) shown in

CC

CC_MAX

CC

CASE

Table 6-1. I

is specified at the relative V

point on the V load line. The processor is capable of

CC_MAX CC

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drawing I

for up to 10 ms. Refer to Figure 2-5 through Figure 2-8 for further details on the average

CC_MAX

processor current draw over various time durations.

8. Refer to Table 2-11 and corresponding Figure 2-10. The processor should not be subjected to any static V

TT

level that exceeds the V

associated with any particular current. Failure to adhere to this specification

TT_MAX

can shorten processor lifetime.

9. This specification represents the V reduction due to each VID transition. See Section 2.1.7.3.

CC

10.Baseboard bandwidth is limited to 20 MHz.

11.FMB is the flexible motherboard guidelines. See Section 2.4 for FMB details.

12.ICC_TDC (Thermal Design Current) is the sustained (DC equivalent) current that the processor is capable of

drawing indefinitely and should be used for the voltage regulator temperature assessment. The voltage

regulator is responsible for monitoring its temperature and asserting the necessary signal to inform the

processor of a thermal excursion.

13.Specification is at T

= 50°C.

CASE

14.Characterized by design (not tested).

Table 2-9.

V_CCStatic and Transient Tolerance

1,2,3,4

I

(A)

V

(V)

V

(V)

V (V)

CC_MIN

Notes

CC

CC_MAX

CC_TYP

0

VID - 0.000

VID - 0.004

VID - 0.008

VID - 0.012

VID - 0.016

VID - 0.020

VID - 0.024

VID - 0.028

VID - 0.032

VID - 0.036

VID - 0.040

VID - 0.044

VID - 0.048

VID - 0.052

VID - 0.056

VID - 0.060

VID - 0.064

VID - 0.068

VID - 0.072

VID - 0.076

VID - 0.080

VID - 0.084

VID - 0.088

VID - 0.092

VID - 0.096

VID - 0.100

VID - 0.104

VID - 0.108

VID - 0.112

VID - 0.116

VID - 0.120

VID - 0.015

VID - 0.019

VID - 0.023

VID - 0.027

VID - 0.031

VID - 0.035

VID - 0.039

VID - 0.043

VID - 0.047

VID - 0.051

VID - 0.055

VID - 0.059

VID - 0.063

VID - 0.067

VID - 0.071

VID - 0.075

VID - 0.079

VID - 0.083

VID - 0.087

VID - 0.091

VID - 0.095

VID - 0.099

VID - 0.103

VID - 0.107

VID - 0.111

VID - 0.115

VID - 0.119

VID - 0.123

VID - 0.127

VID - 0.131

VID - 0.135

VID - 0.030

VID - 0.034

VID - 0.038

VID - 0.042

VID - 0.046

VID - 0.050

VID - 0.054

VID - 0.058

VID - 0.062

VID - 0.066

VID - 0.070

VID - 0.074

VID - 0.078

VID - 0.082

VID - 0.086

VID - 0.090

VID - 0.094

VID - 0.098

VID - 0.102

VID - 0.106

VID - 0.110

VID - 0.114

VID - 0.118

VID - 0.122

VID - 0.126

VID - 0.130

VID - 0.134

VID - 0.138

VID - 0.142

VID - 0.146

VID - 0.150

5

10

15

20

25

30

35

40

45

50

55

60

65

70

75

80

85

90

95

100

105

110

115

120

125

130

135

140

145

150

Notes:

1. The V

and V

loadlines represent static and transient limits. Please see Section 2.6.1 for V

CC

CC_MIN

CC_MAX

overshoot specifications.

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2.

3.

This table is intended to aid in reading discrete points on Figure 2-3.

The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage

regulation feedback for voltage regulator circuits must also be taken from processor VCC_SENSE and

VSS_SENSE lands. Please refer to the appropriate platform design guide for further details on regulator and

decoupling implementations.

4.

Processor core current (I ) ranges are valid up to I

of the processor SKU as defined in Table 2-8,

CC

CC_MAX

“Voltage and Current Specifications”.

Figure 2-3. V_CCStatic and Transient Tolerance Loadlines^1,2,3,4

Icc [A]

0

10

20

30

40

50

60

70

80

90

100

110

120

130

140

150

VID - 0.000

VID - 0.020

VID - 0.040

VID - 0.060

VID - 0.080

VID - 0.100

VID - 0.120

VID - 0.140

VID - 0.160

VID - 0.180

Notes:

1.

The V

and V

loadlines represent static and transient limits. Please see Section 2.6.1 for V

CC_MAX CC

CC_MIN

overshoot specifications.

2.

3.

Refer to Table 2-9 for V Static and Transient Tolerance.

CC

The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage

regulation feedback for voltage regulator circuits must also be taken from processor VCC_SENSE and

VSS_SENSE lands. Please refer to the appropriate platform design guide for further details on regulator and

decoupling implementations.

4.

Processor core current (I ) ranges are valid up to I

of the processor SKU as defined in Table 2-8.

CC

CC_MAX

2.6.1

V

Overshoot Specifications

CC

The Intel Xeon Processor 5500 Series can tolerate short transient overshoot events

where V_CCexceeds the VID voltage when transitioning from a high-to-low current load

condition. This overshoot cannot exceed VID + V_{OS_MAX}(V_{OS_MAX}is the maximum

allowable overshoot above VID). These specifications apply to the processor die voltage

as measured across the VCC_SENSE and VSS_SENSE lands.

Table 2-10. V_CCOvershoot Specifications

Symbol

Parameter

Magnitude of V overshoot above VID

Min

Max

Units

Figure

Notes

V

-

50

25

mV

µs

2-4

OS_MAX

CC

T

Time duration of V overshoot above VID

CC

OS_MAX

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Figure 2-4. V_CCOvershoot Example Waveform

Example Overshoot Waveform

V_OS

VID + 0.050

VID - 0.000

T_OS

0

5

10

15

20

25

Time [us]

T_OS: Overshoot time above VID

V_OS: Overshoot above VID

Notes:

1.

2.

V

is the measured overshoot voltage.

is the measured time duration above VID.

OS

T

2.6.2

Die Voltage Validation

Core voltage (V_CC) overshoot events at the processor must meet the specifications in

Table 2-10 when measured across the VCC_SENSE and VSS_SENSE lands. Overshoot

events that are < 10 ns in duration may be ignored. These measurements of processor

die level overshoot should be taken with a 100 MHz bandwidth limited oscilloscope.

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Figure 2-5. Load Current Versus Time (130W TDP Processor)^1,2

155

150

145

140

135

130

125

120

115

110

105

0.01

0.1

1

10

100

1000

Time Duration, (s)

Notes:

1.

Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than

I

.

CC_TDC

2.

Not 100% tested. Specified by design characterization.

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Intel® Xeon® Processors 5500 Series Electrical Specifications

Figure 2-6. Load Current Versus Time (95W TDP Processor)^1,2

125.0

120.0

115.0

110.0

105.0

100.0

95.0

90.0

85.0

80.0

0.01

0.1

1

10

100

1000

Time Duration, (s)

Notes:

1.

Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than

I

.

CC_TDC

2.

Not 100% tested. Specified by design characterization.

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Figure 2-7. Load Current Versus Time (80W TDP Processor)^1,2

105

100

95

90

85

80

75

70

65

0.01

0.1

1

10

100

1000

Time Duration, (s)

Notes:

1.

Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than

I

.

CC_TDC

2.

Not 100% tested. Specified by design characterization.

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Intel® Xeon® Processors 5500 Series Electrical Specifications

Figure 2-8. Load Current Versus Time (60W TDP Processor)^1,2

85

80

75

70

65

60

55

0.01

0.1

1

10

100

1000

Time Duration, (s)

Notes:

1.

Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than

I

.

CC_TDC

2.

Not 100% tested. Specified by design characterization.

®

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Intel Xeon Processor 5500 Series Datasheet, Volume 1

Intel® Xeon® Processors 5500 Series Electrical Specifications

Figure 2-9. Load Current Versus Time (38W TDP Processor)^1,2

45

40

35

30

25

20

0.01

0.1

1

10

100

1000

Time Duration, (s)

Notes:

1.

Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than

I

.

CC_TDC

2.

Not 100% tested. Specified by design characterization.

Table 2-11. V_TTStatic and Transient Tolerance (Sheet 1 of 2)

1,2,3,4

I

(A)

V

(V)

V

(V)

V (V)

TT_Min

Notes

TT

TT_Max

TT_Typ

0

VTT_VID + 0.0315

VTT_VID + 0.0255

VTT_VID + 0.0195

VTT_VID + 0.0135

VTT_VID + 0.0075

VTT_VID + 0.0015

VTT_VID - 0.0045

VTT_VID - 0.0105

VTT_VID - 0.0165

VTT_VID - 0.0225

VTT_VID - 0.0285

VTT_VID - 0.0345

VTT_VID - 0.0405

VTT_VID - 0.0000

VTT_VID - 0.0060

VTT_VID - 0.0120

VTT_VID - 0.0180

VTT_VID - 0.0240

VTT_VID - 0.0300

VTT_VID - 0.0360

VTT_VID - 0.0420

VTT_VID - 0.0480

VTT_VID - 0.0540

VTT_VID - 0.0600

VTT_VID - 0.0660

VTT_VID - 0.0720

VTT_VID - 0.0315

VTT_VID - 0.0375

VTT_VID - 0.0435

VTT_VID - 0.0495

VTT_VID - 0.0555

VTT_VID - 0.0615

VTT_VID - 0.0675

VTT_VID - 0.0735

VTT_VID - 0.0795

VTT_VID - 0.0855

VTT_VID - 0.0915

VTT_VID - 0.0975

VTT_VID - 0.1035

1

2

3

4

5

6

7

8

9

10

11

12

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Intel Xeon Processor 5500 Series Datasheet, Volume 1

37

Intel® Xeon® Processors 5500 Series Electrical Specifications

Table 2-11. V_TTStatic and Transient Tolerance (Sheet 2 of 2)

1,2,3,4

I

(A)

V

(V)

V

(V)

V (V)

TT_Min

Notes

TT

TT_Max

TT_Typ

13

VTT_VID - 0.0465

VTT_VID - 0.0525

VTT_VID - 0.0585

VTT_VID - 0.0645

VTT_VID - 0.0705

VTT_VID - 0.0765

VTT_VID - 0.0825

VTT_VID - 0.0885

VTT_VID - 0.0945

VTT_VID - 0.1005

VTT_VID - 0.1065

VTT_VID - 0.1125

VTT_VID - 0.1185

VTT_VID - 0.1245

VTT_VID - 0.1305

VTT_VID - 0.1365

VTT_VID - 0.0780

VTT_VID - 0.0840

VTT_VID - 0.0900

VTT_VID - 0.0960

VTT_VID - 0.1020

VTT_VID - 0.1080

VTT_VID - 0.1140

VTT_VID - 0.1200

VTT_VID - 0.1260

VTT_VID - 0.1320

VTT_VID - 0.1380

VTT_VID - 0.1440

VTT_VID - 0.1500

VTT_VID - 0.1560

VTT_VID - 0.1620

VTT_VID - 0.1680

VTT_VID - 0.1095

VTT_VID - 0.1155

VTT_VID - 0.1215

VTT_VID - 0.1275

VTT_VID - 0.1335

VTT_VID - 0.1395

VTT_VID - 0.1455

VTT_VID - 0.1515

VTT_VID - 0.1575

VTT_VID - 0.1635

VTT_VID - 0.1695

VTT_VID - 0.1755

VTT_VID - 0.1815

VTT_VID - 0.1875

VTT_VID - 0.1935

VTT_VID - 0.1995

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

Note:

1.

2.

3.

I

listed in this table is the sum of I

and I

.

TTD

TT

TTA

This table is intended to aid in reading discrete points on Figure 2-10.

The V and V loadlines represent static and transient limits. Each is characterized by a 31.5 mV

TT_MIN

TT_MAX

.

offset from V

TT_TYP

4.

The loadlines specify voltage limits at the die measured at the VTTD_SENSE and VSS_SENSE_VTTD lands.

Voltage regulation feedback for regulator circuits must also be taken from VTTD_SENSE and

VSS_SENSE_VTTD lands.

®

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Intel Xeon Processor 5500 Series Datasheet, Volume 1

Intel® Xeon® Processors 5500 Series Electrical Specifications

Figure 2-10. V_TTStatic and Transient Tolerance Loadlines

I_TT[A]

0

5

10

15

20

25

0.0500

0.0375

0.0250

0.0125

0.0000

-0.0125

-0.0250

-0.0375

-0.0500

-0.0625

-0.0750

-0.0875

-0.1000

-0.1125

-0.1250

-0.1375

-0.1500

-0.1625

-0.1750

-0.1875

-0.2000

-0.2125

Notes:

1.

The V

offset from V

and V

TT_TYP

loadlines represent static and transient limits. Each is characterized by a 31.5 mV

TT_MIN

TT_MAX

.

2.

3.

Refer to Table 2-4 for processor VTT_VID information.

Refer to Table 2-11 for V Static and Transient Tolerance.

TT

Table 2-12. DDR3 Signal Group DC Specifications (Sheet 1 of 2)

1

Symbol

Parameter

Min

Typ

Max

Units

Notes

V

Input Low Voltage

Input High Voltage

Output Low Voltage

0.43*V

V

2,

3, 4

6

IL

DDQ

V

0.57*V

IH

DDQ

(V

/(R +R

/ 2)* (R

VTT_TERM

DDQ

ON

V

OL

OH

ON

))

Output High

Voltage

V

- ((V

/ 2)*

DDQ

V

Ω

4,6

5

DDQ

V

R

(R /(R +R

))

ON

VTT_TERM

DDR3 Clock Buffer

On Resistance

21

16

31

24

DDR3 Command

Buffer On

Resistance

5

R

ON

DDR3 Reset Buffer

On Resistance

25

21

75

31

Ω

5

DDR3 Control

Buffer On

Resistance

DDR3 Data Buffer

On Resistance

21

31

Ω

5

7

On-Die Termination

for Data Signals

45

90

55

110

Data ODT

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Intel Xeon Processor 5500 Series Datasheet, Volume 1

39

Intel® Xeon® Processors 5500 Series Electrical Specifications

Table 2-12. DDR3 Signal Group DC Specifications (Sheet 2 of 2)

1

Symbol

Parameter

Min

Typ

Max

Units

Notes

On-Die Termination

for Parity Error bits

60

80

Ω

ParErr ODT

Input Leakage

Current

N/A

mA

I

± 500

LI

DDR_COMP0 COMP Resistance

DDR_COMP1 COMP Resistance

DDR_COMP2 COMP Resistance

99

100

24.9

130

101

Ω

8

24.65

128.7

25.15

131.3

Notes:

1.

2.

3.

4.

5.

6.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

V

is the maximum voltage level at a receiving agent that will be interpreted as a logical low value.

IL

IH

is the minimum voltage level at a receiving agent that will be interpreted as a logical high value.

and V

may experience excursions above V

.

OH

DDQ

This is the pull down driver resistance. Refer to processor signal integrity models for I/V characteristics.

VTT_TERM

R

is the termination on the DIMM and not controlled by the Intel Xeon Processor 5500 Series.

Please refer to the applicable DIMM datasheet.

7.

8.

The minimum and maximum values for these signals are programmable by BIOS to one of the pairs.

COMP resistance must be provided on the system board with 1% resistors. DDR_COMP[2:0] resistors are

to Vss.

Table 2-13. PECI DC Electrical Limits

1

Symbol

Definition and Conditions

Min

Max

Units

Notes

V

R

Input Voltage Range

Hysteresis

-0.150

0.100 * V

0.275 * V

0.550 * V

V

+ 0.150

V

In

TTD

Hysteresis

TTD

Negative-edge threshold voltage

Positive-edge threshold voltage

Pullup Resistance

0.500 * V

0.725 * V

2,6

N

TTD

P

Pullup

N/A

50

Ω

(V

= 0.75 * V

)

TTD

OH

I

High impedance state leakage to

(V = V

Leak+

Leak-

µA

3

V

)

OL

TTD

leak

High impedance leakage to GND

(V = V

N/A

25

10

µA

pF

3

)

OH

leak

C

V

Bus capacitance per node

4,5

Bus

Signal noise immunity above

300 MHz

Noise

0.100 * V

N/A

V

p-p

TTD

Note:

1.

2.

V

supplies the PECI interface. PECI behavior does not affect V

min/max specifications.

TTD

It is expected that the PECI driver will take into account, the variance in the receiver input thresholds and

consequently, be able to drive its output within safe limits (-0.150 V to 0.275*V for the low level and

0.725*V

TTD

to V

+0.150 for the high level).

TTD

3.

4.

The leakage specification applies to powered devices on the PECI bus.

One node is counted for each client and one node for the system host. Extended trace lengths might appear

as additional nodes.

5.

6.

Excessive capacitive loading on the PECI line may slow down the signal rise/fall times and consequently

limit the maximum bit rate at which the interface can operate.

Please refer to Figure 2-2 for further information.

®

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Intel Xeon Processor 5500 Series Datasheet, Volume 1

Intel® Xeon® Processors 5500 Series Electrical Specifications

Table 2-14. RESET# Signal DC Specifications

1

Symbol

Parameter

Min

Typ

Max

0.60 V

TTA

Units

Notes

V

Input Low Voltage

Input High Voltage

V

Ω

2,3

IL

*

V

R

0.70

V

TTA

2,3,5

IH

*

Processor Sideband Buffer

On Resistance

10

18

± 200

ON

I

Input Leakage Current

μA

4

LI

Notes:

1.

2.

3.

4.

5.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

The V

referred to in these specifications refers to instantaneous V

.

TTA

Based on a test load of 50 Ω to V

.

TTA

For V between 0 V and V . Measured when the driver is tristated.

IN

TTA

V

and V may experience excursions above V .

IH

OH TT

Table 2-15. TAP Signal Group DC Specifications

1

Symbol

Parameter

Min

Typ

Max

Units

Notes

V

Input Low Voltage

Input High Voltage

Output Low Voltage

0.40

V

TTA

V

2,3

2,3,5

2,6

IL

IH

OL

*

V

0.60

V

TTA

*

V

* R

+ R

/

TTA

ON

)

SYS_TERM

(R

ON

V

R

Output High Voltage

V

2,5

OH

TTA

Processor Sideband Buffer

On Resistance

10

18

± 200

Ω

ON

I

Input Leakage Current

μA

4

LI

Notes:

1.

2.

3.

4.

5.

6.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

The V referred to in these specifications refers to instantaneous V

.

TTA

Based on a test load of 50 Ω to V

.

TTA

For V between 0 V and V . Measured when the driver is tristated.

IN

TTA

V

R

and V may experience excursions above V .

IH

OH TT

is the termination on the system and is not controlled by the Intel Xeon processor 5500 series

SYS_TERM

Table 2-16. PWRGOOD Signal Group DC Specifications

1

Symbol

Parameter

Min

Typ

Max

0.25 V

TTA

Units

Notes

V

Input Low Voltage for

VTTPWRGOOD and

VCCPWRGOOD signals

V

2,3

IL

*

Input Low Voltage for

VDDPWRGOOD signal

0.29

V

3

IL

V

Input High Voltage for

VTTPWRGOOD and

VCCPWRGOOD signals

0.75

V

TTA

2,3

IH

*

Input High Voltage for

VDDPWRGOOD signal

0.87

V

3

4

IH

ODT

On-Die Termination

45

10

55

18

R

Processor Sideband Buffer

On Resistance

Ω

ON

I

Input Leakage Current

± 200

μA

LI

Notes:

1.

2.

3.

4.

5.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

The V referred to in these specifications refers to instantaneous V

.

TTA

Based on a test load of 50 Ω to V

.

TTA

For V between 0 V and V . Measured when the driver is tristated.

IN

TTA

V

and V may experience excursions above V .

IH

OH TT

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Intel Xeon Processor 5500 Series Datasheet, Volume 1

41

Intel® Xeon® Processors 5500 Series Electrical Specifications

Table 2-17. Control Sideband Signal Group DC Specifications

1

Symbol

Parameter

Min

Typ

Max

Units

Notes

V

Input Low Voltage

0.64

0.15

V

2,3

IL

*

TTA

Input Low Voltage for

PECI_ID signal

IL

V

Input High Voltage

0.76

V

2,3

IH

*

TTA

Input High Voltage for

PECI_ID signal

0.85

V

Output Low Voltage

V

ON

* R

/

V

2,4

OL

TTA

ON

)

SYS_TERM

(R

+ R

V

Output High Voltage

On-Die Termination

V

2

5

OH

TTA

ODT

45

10

55

R

Processor Sideband Buffer

On Resistance

18

Ω

ON

R

Buffer On Resistance for

VID[7:0]

100

ON

I

Input Leakage Current

± 200

± 50

μA

6

LI

I

Input Leakage Current for

DDR_THERM# signal

LI

COMP0

COMP Resistance

49.4

49.9

50.4

Ω

7

Notes:

1.

2.

3.

4.

5.

6.

7.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

The V referred to in these specifications refers to instantaneous V

.

TTA

Based on a test load of 50 Ω to V

TTA.

R

is the termination on the system and is not controlled by the Intel Xeon processor 5500 series.

SYS_TERM

Applies to all Processor Sideband signals, unless otherwise mentioned in Table 2-5.

For V between 0 V and V . Measured when the driver is tristated.

IN

TTA

COMP resistance must be provided on the system board with 1% resistors. See the applicable platform

design guide for implementation details. COMP0 resistors are to VSS.

§

®

42

Intel Xeon Processor 5500 Series Datasheet, Volume 1

Package Mechanical Specifications

3 Package Mechanical

Specifications

3.1

Package Mechanical Specifications

The processor is packaged in a Flip-Chip Land Grid Array (FC-LGA6) package that

interfaces with the motherboard via an LGA1366 socket. The package consists of a

processor mounted on a substrate land-carrier. An integrated heat spreader (IHS) is

attached to the package substrate and core and serves as the mating surface for

processor component thermal solutions, such as a heatsink. Figure 3-1 shows a sketch

of the processor package components and how they are assembled together. Refer to

the Processors and Socket in the Intel® Xeon® Processor 5500/5600 Series

Thermal/Mechanical Design Guide for complete details on the LGA1366 socket.

The package components shown in Figure 3-1 include the following:

1. Integrated Heat Spreader (IHS)

2. Thermal Interface Material (TIM)

3. Processor core (die)

4. Package substrate

5. Capacitors

Figure 3-1. Processor Package Assembly Sketch

TIM

Die

IHS

Substrate

Capacitors

LGA1366 Socket

System Board

Note:

1.

Socket and motherboard are included for reference and are not part of processor package.

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Intel Xeon Processor 5500 Series Datasheet, Volume 1

43

Package Mechanical Specifications

3.1.1

Package Mechanical Drawing

The package mechanical drawings are shown in Figure 3-2 and Figure 3-3. The

drawings include dimensions necessary to design a thermal solution for the processor.

These dimensions include:

1. Package reference with tolerances (total height, length, width, and so forth)

2. IHS parallelism and tilt

3. Land dimensions

4. Top-side and back-side component keep-out dimensions

5. Reference datums

6. All drawing dimensions are in mm.

7. Guidelines on potential IHS flatness variation with socket load plate actuation and

installation of the cooling solution is available in the TMDG.

®

44

Intel Xeon Processor 5500 Series Datasheet, Volume 1

Package Mechanical Specifications

Figure 3-2. Processor Package Drawing (Sheet 1 of 2)

®

Intel Xeon Processor 5500 Series Datasheet, Volume 1

45

Package Mechanical Specifications

Figure 3-3. Processor Package Drawing (Sheet 2 of 2)

®

46

Intel Xeon Processor 5500 Series Datasheet, Volume 1

Package Mechanical Specifications

3.1.2

Processor Component Keep-Out Zones

The processor may contain components on the substrate that define component

keep-out zone requirements. A thermal and mechanical solution design must not

intrude into the required keep-out zones. Do not contact the Test Pad Area with

conductive material. Decoupling capacitors are typically mounted to either the topside

or land-side of the package substrate. See Figure 3-2 and Figure 3-3 for keep-out

zones. The location and quantity of package capacitors may change due to

manufacturing efficiencies but will remain within the component keep-in.

3.1.3

Package Loading Specifications

Table 3-1 provides load specifications for the processor package. These maximum

limits should not be exceeded during heatsink assembly, shipping conditions, or

standard use condition. Exceeding these limits during test may result in component

failure. The processor substrate should not be used as a mechanical reference or load-

bearing surface for thermal solutions.

.

Table 3-1.

Processor Loading Specifications

Parameter

Maximum

890 N [200 lbf]

Notes

Static Compressive Load

1, 2, 3, 5

1, 3, 4, 5

Dynamic Compressive Load

1779 N [400 lbf] [max static

compressive + dynamic load]

Notes:

1.

2.

These specifications apply to uniform compressive loading in a direction normal to the processor IHS.

This is the maximum static force that can be applied by the heatsink and Independent Loading Mechanism

(ILM).

3.

4.

5.

These specifications are based on limited testing for design characterization. Loading limits are for the

package constrained by the limits of the processor socket.

Dynamic loading is defined as an 11 ms duration average load superimposed on the static load

requirement.

See Intel® Xeon® Processor 5500/5600 Series Thermal/Mechanical Design Guide for minimum socket load

to engage processor within socket.

3.1.4

Package Handling Guidelines

Table 3-2 includes a list of guidelines on package handling in terms of recommended

maximum loading on the processor IHS relative to a fixed substrate. These package

handling loads may be experienced during heatsink removal.

Table 3-2.

Package Handling Guidelines

Parameter

Maximum Recommended

Notes

Shear

Tensile

Torque

70 lbs

25 lbs

-

35 in.lbs

3.1.5

Package Insertion Specifications

The processor can be inserted into and removed from a LGA1366 socket 15 times. The

socket should meet the LGA1366 requirements detailed in the TMDG.

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Intel Xeon Processor 5500 Series Datasheet, Volume 1

47

Package Mechanical Specifications

3.1.6

Processor Mass Specification

The typical mass of the processor is 35 grams. This mass [weight] includes all the

components that are included in the package.

3.1.7

Processor Materials

Table 3-3 lists some of the package components and associated materials.

Table 3-3.

Processor Materials

Component

Material

Nickel Plated Copper

Integrated Heat Spreader (IHS)

Substrate

Fiber Reinforced Resin

Gold Plated Copper

Substrate Lands

3.1.8

Processor Markings

Figure 3-4 shows the topside markings on the processor. This diagram is to aid in the

identification of the processor.

Figure 3-4. Processor Top-Side Markings

GRP1LINE1

GRP1LINE2

Legend:

Mark Text (Engineering Mark):

GRP1LINE1: INTEL{M}{C}’YY

GRP1LINE2: INTEL CONFIDENTIAL

GRP1LINE3: QDF ES XXXXX

GRP1LINE4: FORECAST-NAME

GRP1LINE5: {FPO} {e4}

Legend:

Mark Text (Production Mark):

INTEL{M}{C}’YY PROC#

SUB-BRAND

SSPEC XXXXX

SPEED/CACHE/INTC

{FPO} {e4}

GRP1LINE1:

GRP1LINE2:

GRP1LINE3:

GRP1LINE4:

GRP1LINE5:

G2L1

G2L2

G3L1

G3L2

3.1.9

Processor Land Coordinates

Please refer to Figure 3-3 which shows the bottom view of the processor land

coordinates. The coordinates are referred to throughout the document to identify

processor lands.

§

®

48

Intel Xeon Processor 5500 Series Datasheet, Volume 1

Land Listing

4 Land Listing

4.1

Intel^®Xeon^®Processors 5500 Series Pin

Assignments

This section provides sorted land list in Table 4-1 and Table 4-2. Table 4-1 is a listing of

all processor lands ordered alphabetically by land name. Table 4-2 is a listing of all

processor lands ordered by land number.

Note: A land name prefixed with a FC denotes a Future Connect land.

4.1.1

Land Listing by Land Name

Table 4-1.

Land Listing by Land Name

(Sheet 2 of 36)

Table 4-1.

Land Listing by Land Name

(Sheet 1 of 36)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

QPI0_DRX_DN[16]

QPI0_DRX_DN[17]

QPI0_DRX_DN[18]

QPI0_DRX_DN[19]

QPI0_DRX_DN[2]

QPI0_DRX_DN[3]

QPI0_DRX_DN[4]

QPI0_DRX_DN[5]

QPI0_DRX_DN[6]

QPI0_DRX_DN[7]

QPI0_DRX_DN[8]

QPI0_DRX_DN[9]

QPI0_DRX_DP[0]

QPI0_DRX_DP[1]

QPI0_DRX_DP[10]

QPI0_DRX_DP[11]

QPI0_DRX_DP[12]

QPI0_DRX_DP[13]

QPI0_DRX_DP[14]

QPI0_DRX_DP[15]

QPI0_DRX_DP[16]

QPI0_DRX_DP[17]

QPI0_DRX_DP[18]

QPI0_DRX_DP[19]

QPI0_DRX_DP[2]

QPI0_DRX_DP[3]

QPI0_DRX_DP[4]

AM41

AP40

AP39

AR38

AV37

AY36

BA37

AW38

AY38

AT39

AV40

AU41

AT37

AU38

AU42

AT43

AT40

AP42

AN43

AN40

AM42

AP41

AN39

AP38

AV36

AW36

BA36

QPI

I

BCLK_DN

AH35

AJ35

AA4

CMOS

GTL

I

BCLK_DP

I

BCLK_ITP_DN

BCLK_ITP_DP

BPM#[0]

O

AA5

O

B3

I/O

BPM#[1]

A5

GTL

BPM#[2]

C2

GTL

BPM#[3]

B4

GTL

BPM#[4]

D1

GTL

BPM#[5]

C3

GTL

BPM#[6]

D2

GTL

BPM#[7]

E2

GTL

CAT_ERR#

AC37

AB41

AR42

AR41

AF42

AG42

AL43

AU37

AV38

AT42

AR43

AR40

AN42

AM43

AM40

GTL

COMP0

Analog

QPI

QPI0_CLKRX_DN

QPI0_CLKRX_DP

QPI0_CLKTX_DN

QPI0_CLKTX_DP

QPI0_COMP

I

QPI

O

QPI

Analog

QPI

QPI0_DRX_DN[0]

QPI0_DRX_DN[1]

QPI0_DRX_DN[10]

QPI0_DRX_DN[11]

QPI0_DRX_DN[12]

QPI0_DRX_DN[13]

QPI0_DRX_DN[14]

QPI0_DRX_DN[15]

I

QPI

®

Intel Xeon Processor 5500 Series Datasheet, Volume 1

49

Land Listing

Table 4-1.

Land Listing by Land Name

(Sheet 3 of 36)

Table 4-1.

Land Listing by Land Name

(Sheet 4 of 36)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

QPI0_DRX_DP[5]

QPI0_DRX_DP[6]

QPI0_DRX_DP[7]

QPI0_DRX_DP[8]

QPI0_DRX_DP[9]

QPI0_DTX_DN[0]

QPI0_DTX_DN[1]

QPI0_DTX_DN[10]

QPI0_DTX_DN[11]

QPI0_DTX_DN[12]

QPI0_DTX_DN[13]

QPI0_DTX_DN[14]

QPI0_DTX_DN[15]

QPI0_DTX_DN[16]

QPI0_DTX_DN[17]

QPI0_DTX_DN[18]

QPI0_DTX_DN[19]

QPI0_DTX_DN[2]

QPI0_DTX_DN[3]

QPI0_DTX_DN[4]

QPI0_DTX_DN[5]

QPI0_DTX_DN[6]

QPI0_DTX_DN[7]

QPI0_DTX_DN[8]

QPI0_DTX_DN[9]

QPI0_DTX_DP[0]

QPI0_DTX_DP[1]

QPI0_DTX_DP[10]

QPI0_DTX_DP[11]

QPI0_DTX_DP[12]

QPI0_DTX_DP[13]

QPI0_DTX_DP[14]

QPI0_DTX_DP[15]

QPI0_DTX_DP[16]

QPI0_DTX_DP[17]

QPI0_DTX_DP[18]

QPI0_DTX_DP[19]

QPI0_DTX_DP[2]

QPI0_DTX_DP[3]

QPI0_DTX_DP[4]

AW37

BA38

AU39

AW40

AU40

AH38

AG39

AE43

AE41

AC42

AB43

AD39

AC40

AC38

AB38

AE38

AF40

AK38

AJ39

AJ40

AK41

AH42

AJ42

AH43

AG41

AG38

AF39

AF43

AE42

AD42

AC43

AD40

AC41

AC39

AB39

AD38

AE40

AK37

AJ38

AH40

QPI

I

QPI0_DTX_DP[5]

QPI0_DTX_DP[6]

QPI0_DTX_DP[7]

QPI0_DTX_DP[8]

QPI0_DTX_DP[9]

QPI1_CLKRX_DN

QPI1_CLKRX_DP

QPI1_CLKTX_DN

QPI1_CLKTX_DP

QPI1_COMP

AK40

AH41

AK42

AJ43

AG40

AR6

AT6

QPI

Analog

QPI

O

I

O

I

AE6

AF6

O

AL6

QPI1_DRX_DN[0]

QPI1_DRX_DN[1]

QPI1_DRX_DN[10]

QPI1_DRX_DN[11]

QPI1_DRX_DN[12]

QPI1_DRX_DN[13]

QPI1_DRX_DN[14]

QPI1_DRX_DN[15]

QPI1_DRX_DN[16]

QPI1_DRX_DN[17]

QPI1_DRX_DN[18]

QPI1_DRX_DN[19]

QPI1_DRX_DN[2]

QPI1_DRX_DN[3]

QPI1_DRX_DN[4]

QPI1_DRX_DN[5]

QPI1_DRX_DN[6]

QPI1_DRX_DN[7]

QPI1_DRX_DN[8]

QPI1_DRX_DN[9]

QPI1_DRX_DP[0]

QPI1_DRX_DP[1]

QPI1_DRX_DP[10]

QPI1_DRX_DP[11]

QPI1_DRX_DP[12]

QPI1_DRX_DP[13]

QPI1_DRX_DP[14]

QPI1_DRX_DP[15]

QPI1_DRX_DP[16]

QPI1_DRX_DP[17]

AV8

AW7

AR1

AR5

AN2

AM1

AM3

AP4

AN4

AN6

AM7

AL8

I

BA8

AW5

BA6

AY5

AU6

AW3

AU3

AT2

AU8

AV7

AT1

AR4

AP2

AN1

AM2

AP3

AM4

AN5

®

50

Intel Xeon Processor 5500 Series Datasheet, Volume 1

Land Listing

Table 4-1.

Land Listing by Land Name

(Sheet 5 of 36)

Table 4-1.

Land Listing by Land Name

(Sheet 6 of 36)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

QPI1_DRX_DP[18]

QPI1_DRX_DP[19]

QPI1_DRX_DP[2]

QPI1_DRX_DP[3]

QPI1_DRX_DP[4]

QPI1_DRX_DP[5]

QPI1_DRX_DP[6]

QPI1_DRX_DP[7]

QPI1_DRX_DP[8]

QPI1_DRX_DP[9]

QPI1_DTX_DN[0]

QPI1_DTX_DN[1]

QPI1_DTX_DN[10]

QPI1_DTX_DN[11]

QPI1_DTX_DN[12]

QPI1_DTX_DN[13]

QPI1_DTX_DN[14]

QPI1_DTX_DN[15]

QPI1_DTX_DN[16]

QPI1_DTX_DN[17]

QPI1_DTX_DN[18]

QPI1_DTX_DN[19]

QPI1_DTX_DN[2]

QPI1_DTX_DN[3]

QPI1_DTX_DN[4]

QPI1_DTX_DN[5]

QPI1_DTX_DN[6]

QPI1_DTX_DN[7]

QPI1_DTX_DN[8]

QPI1_DTX_DN[9]

QPI1_DTX_DP[0]

QPI1_DTX_DP[1]

QPI1_DTX_DP[10]

QPI1_DTX_DP[11]

QPI1_DTX_DP[12]

QPI1_DTX_DP[13]

QPI1_DTX_DP[14]

QPI1_DTX_DP[15]

QPI1_DTX_DP[16]

QPI1_DTX_DP[17]

AM6

AM8

AY8

AV5

BA7

AY6

AU7

AW4

AU4

AT3

AH8

AJ7

QPI

I

QPI1_DTX_DP[18]

QPI1_DTX_DP[19]

QPI1_DTX_DP[2]

QPI1_DTX_DP[3]

QPI1_DTX_DP[4]

QPI1_DTX_DP[5]

QPI1_DTX_DP[6]

QPI1_DTX_DP[7]

QPI1_DTX_DP[8]

QPI1_DTX_DP[9]

DBR#

AD5

AC8

AH6

AK6

AJ4

AG7

AJ3

AK1

AH3

AH2

AF10

AA8

Y7

QPI

O

I

QPI

I

QPI

I

QPI

I

QPI

I

QPI

I

QPI

I

QPI

I

QPI

O

Asynch

Analog

CMOS

Analog

CMOS

CLOCK

CMOS

DDR_COMP[0]

DDR_COMP[1]

DDR_COMP[2]

DDR_THERM#

DDR_VREF

AF3

AD1

AD3

AB3

AE4

AD4

AC6

AD7

AE5

AD8

AJ6

AC1

AB5

L23

B16

A16

C28

C12

C29

A30

B30

B31

K19

C19

E18

E19

J19

I

DDR0_BA[0]

O

DDR0_BA[1]

DDR0_BA[2]

DDR0_CAS#

DDR0_CKE[0]

DDR0_CKE[1]

DDR0_CKE[2]

DDR0_CKE[3]

DDR0_CLK_N[0]

DDR0_CLK_N[1]

DDR0_CLK_N[2]

DDR0_CLK_N[3]

DDR0_CLK_P[0]

DDR0_CLK_P[1]

DDR0_CLK_P[2]

DDR0_CLK_P[3]

DDR0_CS#[0]

DDR0_CS#[1]

DDR0_CS#[2]

DDR0_CS#[3]

DDR0_CS#[4]

DDR0_CS#[5]

AK5

AK4

AG6

AJ2

AJ1

AH4

AG2

AG8

AJ8

D19

F18

E20

G15

B10

C13

B9

AF2

AE1

AD2

AC3

AE3

AC4

AB6

AD6

B15

A7

DDR0_CS#[6]/

DDR0_ODT[4]

C11

®

Intel Xeon Processor 5500 Series Datasheet, Volume 1

51

Land Listing

Table 4-1.

Land Listing by Land Name

(Sheet 7 of 36)

Table 4-1.

Land Listing by Land Name

(Sheet 8 of 36)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

DDR0_CS#[7]/

DDR0_ODT[5]

B8

CMOS

O

DDR0_DQ[44]

DDR0_DQ[45]

DDR0_DQ[46]

DDR0_DQ[47]

DDR0_DQ[48]

DDR0_DQ[49]

DDR0_DQ[5]

G1

H3

CMOS

I/O

DDR0_DQ[0]

DDR0_DQ[1]

DDR0_DQ[10]

DDR0_DQ[11]

DDR0_DQ[12]

DDR0_DQ[13]

DDR0_DQ[14]

DDR0_DQ[15]

DDR0_DQ[16]

DDR0_DQ[17]

DDR0_DQ[18]

DDR0_DQ[19]

DDR0_DQ[2]

DDR0_DQ[20]

DDR0_DQ[21]

DDR0_DQ[22]

DDR0_DQ[23]

DDR0_DQ[24]

DDR0_DQ[25]

DDR0_DQ[26]

DDR0_DQ[27]

DDR0_DQ[28]

DDR0_DQ[29]

DDR0_DQ[3]

DDR0_DQ[30]

DDR0_DQ[31]

DDR0_DQ[32]

DDR0_DQ[33]

DDR0_DQ[34]

DDR0_DQ[35]

DDR0_DQ[36]

DDR0_DQ[37]

DDR0_DQ[38]

DDR0_DQ[39]

DDR0_DQ[4]

DDR0_DQ[40]

DDR0_DQ[41]

DDR0_DQ[42]

DDR0_DQ[43]

W41

V41

K42

K43

P42

P41

L43

L42

H41

H43

E42

E43

R43

J42

J41

F43

F42

D40

C41

A38

D37

D41

D42

R42

C38

B38

B5

CMOS

I/O

L3

L2

N1

N2

W42

T1

DDR0_DQ[50]

DDR0_DQ[51]

DDR0_DQ[52]

DDR0_DQ[53]

DDR0_DQ[54]

DDR0_DQ[55]

DDR0_DQ[56]

DDR0_DQ[57]

DDR0_DQ[58]

DDR0_DQ[59]

DDR0_DQ[6]

T2

M3

N3

R4

T3

U4

V1

Y2

Y3

U41

U1

DDR0_DQ[60]

DDR0_DQ[61]

DDR0_DQ[62]

DDR0_DQ[63]

DDR0_DQ[7]

U3

V4

W4

T42

N41

N43

U43

M41

M43

G43

C39

D4

DDR0_DQ[8]

DDR0_DQ[9]

DDR0_DQS_N[0]

DDR0_DQS_N[1]

DDR0_DQS_N[10]

DDR0_DQS_N[11]

DDR0_DQS_N[12]

DDR0_DQS_N[13]

DDR0_DQS_N[14]

DDR0_DQS_N[15]

DDR0_DQS_N[16]

DDR0_DQS_N[17]

DDR0_DQS_N[2]

DDR0_DQS_N[3]

DDR0_DQS_N[4]

DDR0_DQS_N[5]

DDR0_DQS_N[6]

C4

F1

G3

J1

B6

P1

C6

V3

F3

B35

G41

B40

E4

F2

W40

H2

H1

K3

L1

R3

M1

®

52

Intel Xeon Processor 5500 Series Datasheet, Volume 1

Land Listing

Table 4-1.

Land Listing by Land Name

(Sheet 9 of 36)

Table 4-1.

Land Listing by Land Name

(Sheet 10 of 36)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

DDR0_DQS_N[7]

DDR0_DQS_N[8]

DDR0_DQS_N[9]

DDR0_DQS_P[0]

DDR0_DQS_P[1]

DDR0_DQS_P[10]

DDR0_DQS_P[11]

DDR0_DQS_P[12]

DDR0_DQS_P[13]

DDR0_DQS_P[14]

DDR0_DQS_P[15]

DDR0_DQS_P[16]

DDR0_DQS_P[17]

DDR0_DQS_P[2]

DDR0_DQS_P[3]

DDR0_DQS_P[4]

DDR0_DQS_P[5]

DDR0_DQS_P[6]

DDR0_DQS_P[7]

DDR0_DQS_P[8]

DDR0_DQS_P[9]

DDR0_ECC[0]

W1

D35

V42

T43

L41

N42

H42

D39

D5

CMOS

I/O

O

DDR0_MA[5]

B24

C24

A25

B25

C26

B20

F12

C9

CMOS

Asynch

CMOS

CLOCK

CMOS

O

I

DDR0_MA[6]

DDR0_MA[7]

DDR0_MA[8]

DDR0_MA[9]

DDR0_MA_PAR

DDR0_ODT[0]

DDR0_ODT[1]

DDR0_ODT[2]

DDR0_ODT[3]

DDR0_PAR_ERR#[0]

DDR0_PAR_ERR#[1]

DDR0_PAR_ERR#[2]

DDR0_RAS#

B11

C7

J2

P2

D25

B28

A27

A15

D32

B13

C18

K13

H27

E14

H28

E27

D27

C27

D21

G20

L18

H19

C21

G19

K18

H18

D12

A8

V2

I

B36

F41

B39

E3

I

O

DDR0_RESET#

DDR0_WE#

K2

DDR1_BA[0]

R2

DDR1_BA[1]

W2

DDR1_BA[2]

D34

V43

C36

A36

F32

C33

C37

A37

B34

C34

A20

B21

B19

A26

B26

A10

A28

B29

C23

D24

B23

DDR1_CAS#

DDR1_CKE[0]

DDR1_CKE[1]

DDR1_CKE[2]

DDR1_CKE[3]

DDR1_CLK_N[0]

DDR1_CLK_N[1]

DDR1_CLK_N[2]

DDR1_CLK_N[3]

DDR1_CLK_P[0]

DDR1_CLK_P[1]

DDR1_CLK_P[2]

DDR1_CLK_P[3]

DDR1_CS#[0]

DDR1_CS#[1]

DDR1_CS#[2]

DDR1_CS#[3]

DDR1_CS#[4]

DDR1_CS#[5]

DDR0_ECC[1]

DDR0_ECC[2]

DDR0_ECC[3]

DDR0_ECC[4]

DDR0_ECC[5]

DDR0_ECC[6]

DDR0_ECC[7]

DDR0_MA[0]

DDR0_MA[1]

O

DDR0_MA[10]

O

DDR0_MA[11]

O

DDR0_MA[12]

O

DDR0_MA[13]

O

E15

E13

C17

E10

C14

DDR0_MA[14]

O

DDR0_MA[15]

O

DDR0_MA[2]

O

DDR0_MA[3]

O

DDR1_CS#[6]/

DDR1_ODT[4]

DDR0_MA[4]

O

®

Intel Xeon Processor 5500 Series Datasheet, Volume 1

53

Land Listing

Table 4-1.

Land Listing by Land Name

(Sheet 11 of 36)

Table 4-1.

Land Listing by Land Name

(Sheet 12 of 36)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

DDR1_CS#[7]/

DDR1_ODT[5]

E12

CMOS

O

DDR1_DQ[44]

DDR1_DQ[45]

DDR1_DQ[46]

DDR1_DQ[47]

DDR1_DQ[48]

DDR1_DQ[49]

DDR1_DQ[5]

G9

H9

CMOS

I/O

DDR1_DQ[0]

DDR1_DQ[1]

DDR1_DQ[10]

DDR1_DQ[11]

DDR1_DQ[12]

DDR1_DQ[13]

DDR1_DQ[14]

DDR1_DQ[15]

DDR1_DQ[16]

DDR1_DQ[17]

DDR1_DQ[18]

DDR1_DQ[19]

DDR1_DQ[2]

DDR1_DQ[20]

DDR1_DQ[21]

DDR1_DQ[22]

DDR1_DQ[23]

DDR1_DQ[24]

DDR1_DQ[25]

DDR1_DQ[26]

DDR1_DQ[27]

DDR1_DQ[28]

DDR1_DQ[29]

DDR1_DQ[3]

DDR1_DQ[30]

DDR1_DQ[31]

DDR1_DQ[32]

DDR1_DQ[33]

DDR1_DQ[34]

DDR1_DQ[35]

DDR1_DQ[36]

DDR1_DQ[37]

DDR1_DQ[38]

DDR1_DQ[39]

DDR1_DQ[4]

DDR1_DQ[40]

DDR1_DQ[41]

DDR1_DQ[42]

DDR1_DQ[43]

AA37

AA36

P39

N39

R34

R35

N37

N38

M35

M34

K35

J35

Y35

N34

M36

J36

H36

H33

L33

K32

J32

J34

H34

Y34

L32

K30

E9

CMOS

I/O

G5

J5

K4

K5

AB36

R5

DDR1_DQ[50]

DDR1_DQ[51]

DDR1_DQ[52]

DDR1_DQ[53]

DDR1_DQ[54]

DDR1_DQ[55]

DDR1_DQ[56]

DDR1_DQ[57]

DDR1_DQ[58]

DDR1_DQ[59]

DDR1_DQ[6]

T5

J4

M6

R8

R7

W6

W7

Y10

W10

Y40

V9

DDR1_DQ[60]

DDR1_DQ[61]

DDR1_DQ[62]

DDR1_DQ[63]

DDR1_DQ[7]

W5

AA7

W9

Y39

P34

P35

Y37

R37

P37

K37

K33

F7

DDR1_DQ[8]

DDR1_DQ[9]

DDR1_DQS_N[0]

DDR1_DQS_N[1]

DDR1_DQS_N[10]

DDR1_DQS_N[11]

DDR1_DQS_N[12]

DDR1_DQS_N[13]

DDR1_DQS_N[14]

DDR1_DQS_N[15]

DDR1_DQS_N[16]

DDR1_DQS_N[17]

DDR1_DQS_N[2]

DDR1_DQS_N[3]

DDR1_DQS_N[4]

DDR1_DQS_N[5]

DDR1_DQS_N[6]

E8

E5

F5

J7

F10

G8

M4

Y5

D6

E35

L36

L31

D7

F6

AA35

H8

J6

G6

G4

L5

H4

®

54

Intel Xeon Processor 5500 Series Datasheet, Volume 1

Land Listing

Table 4-1.

Land Listing by Land Name

(Sheet 13 of 36)

Table 4-1.

Land Listing by Land Name

(Sheet 14 of 36)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

DDR1_DQS_N[7]

DDR1_DQS_N[8]

DDR1_DQS_N[9]

DDR1_DQS_P[0]

DDR1_DQS_P[1]

DDR1_DQS_P[10]

DDR1_DQS_P[11]

DDR1_DQS_P[12]

DDR1_DQS_P[13]

DDR1_DQS_P[14]

DDR1_DQS_P[15]

DDR1_DQS_P[16]

DDR1_DQS_P[17]

DDR1_DQS_P[2]

DDR1_DQS_P[3]

DDR1_DQS_P[4]

DDR1_DQS_P[5]

DDR1_DQS_P[6]

DDR1_DQS_P[7]

DDR1_DQS_P[8]

DDR1_DQS_P[9]

DDR1_ECC[0]

Y9

G34

AA41

Y38

R38

P36

L37

K34

F8

CMOS

I/O

O

DDR1_MA[5]

F22

J27

CMOS

Asynch

CMOS

CLOCK

CMOS

O

I

DDR1_MA[6]

DDR1_MA[7]

D22

E22

G24

D20

D11

C8

DDR1_MA[8]

DDR1_MA[9]

DDR1_MA_PAR

DDR1_ODT[0]

DDR1_ODT[1]

DDR1_ODT[2]

DDR1_ODT[3]

DDR1_PAR_ERR#[0]

DDR1_PAR_ERR#[1]

DDR1_PAR_ERR#[2]

DDR1_RAS#

D14

F11

C22

E25

F25

G14

D29

G13

A17

F17

L26

F16

J26

H7

M5

Y4

I

F35

L35

L30

E7

I

O

DDR1_RESET#

DDR1_WE#

H6

DDR2_BA[0]

L6

DDR2_BA[1]

Y8

DDR2_BA[2]

G33

AA40

D36

F36

E33

G36

E37

F37

E34

G35

J14

J16

H14

E23

E24

B14

H26

F26

J17

L28

K28

DDR2_CAS#

DDR2_CKE[0]

DDR2_CKE[1]

DDR2_CKE[2]

DDR2_CKE[3]

DDR2_CLK_N[0]

DDR2_CLK_N[1]

DDR2_CLK_N[2]

DDR2_CLK_N[3]

DDR2_CLK_P[0]

DDR2_CLK_P[1]

DDR2_CLK_P[2]

DDR2_CLK_P[3]

DDR2_CS#[0]

DDR2_CS#[1]

DDR2_CS#[2]

DDR2_CS#[3]

DDR2_CS#[4]

DDR2_CS#[5]

G26

D26

L27

J21

DDR1_ECC[1]

DDR1_ECC[2]

DDR1_ECC[3]

DDR1_ECC[4]

K20

G21

L21

J22

DDR1_ECC[5]

DDR1_ECC[6]

DDR1_ECC[7]

DDR1_MA[0]

L20

H21

L22

G16

K14

D16

H16

E17

D9

DDR1_MA[1]

O

DDR1_MA[10]

O

DDR1_MA[11]

O

DDR1_MA[12]

O

DDR1_MA[13]

O

DDR1_MA[14]

O

DDR1_MA[15]

O

DDR1_MA[2]

O

DDR1_MA[3]

O

DDR2_CS#[6]/

DDR2_ODT[4]

L17

DDR1_MA[4]

O

®

Intel Xeon Processor 5500 Series Datasheet, Volume 1

55

Land Listing

Table 4-1.

Land Listing by Land Name

(Sheet 15 of 36)

Table 4-1.

Land Listing by Land Name

(Sheet 16 of 36)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

DDR2_CS#[7]/

DDR2_ODT[5]

J15

CMOS

O

DDR2_DQ[44]

DDR2_DQ[45]

DDR2_DQ[46]

DDR2_DQ[47]

DDR2_DQ[48]

DDR2_DQ[49]

DDR2_DQ[5]

L11

M10

L8

CMOS

I/O

DDR2_DQ[0]

DDR2_DQ[1]

DDR2_DQ[10]

DDR2_DQ[11]

DDR2_DQ[12]

DDR2_DQ[13]

DDR2_DQ[14]

DDR2_DQ[15]

DDR2_DQ[16]

DDR2_DQ[17]

DDR2_DQ[18]

DDR2_DQ[19]

DDR2_DQ[2]

DDR2_DQ[20]

DDR2_DQ[21]

DDR2_DQ[22]

DDR2_DQ[23]

DDR2_DQ[24]

DDR2_DQ[25]

DDR2_DQ[26]

DDR2_DQ[27]

DDR2_DQ[28]

DDR2_DQ[29]

DDR2_DQ[3]

DDR2_DQ[30]

DDR2_DQ[31]

DDR2_DQ[32]

DDR2_DQ[33]

DDR2_DQ[34]

DDR2_DQ[35]

DDR2_DQ[36]

DDR2_DQ[37]

DDR2_DQ[38]

DDR2_DQ[39]

DDR2_DQ[4]

DDR2_DQ[40]

DDR2_DQ[41]

DDR2_DQ[42]

DDR2_DQ[43]

W34

W35

R39

T36

W39

V39

T41

R40

M39

M40

J40

CMOS

I/O

M8

P7

N6

V34

P9

DDR2_DQ[50]

DDR2_DQ[51]

DDR2_DQ[52]

DDR2_DQ[53]

DDR2_DQ[54]

DDR2_DQ[55]

DDR2_DQ[56]

DDR2_DQ[57]

DDR2_DQ[58]

DDR2_DQ[59]

DDR2_DQ[6]

P10

N8

N7

R10

R9

J39

U5

V36

P40

N36

L40

K38

G40

F40

J37

U6

T10

U10

V37

T6

DDR2_DQ[60]

DDR2_DQ[61]

DDR2_DQ[62]

DDR2_DQ[63]

DDR2_DQ[7]

T7

V8

U9

H37

H39

G39

U36

F38

E38

K12

J12

V38

U38

U39

W36

T38

T40

L38

G38

J11

K8

DDR2_DQ[8]

DDR2_DQ[9]

DDR2_DQS_N[0]

DDR2_DQS_N[1]

DDR2_DQS_N[10]

DDR2_DQS_N[11]

DDR2_DQS_N[12]

DDR2_DQS_N[13]

DDR2_DQS_N[14]

DDR2_DQS_N[15]

DDR2_DQS_N[16]

DDR2_DQS_N[17]

DDR2_DQS_N[2]

DDR2_DQS_N[3]

DDR2_DQS_N[4]

DDR2_DQS_N[5]

DDR2_DQS_N[6]

H13

L13

G11

G10

H12

L12

U34

L10

K10

M9

P4

V7

G31

K39

E40

J9

K7

P5

N9

®

56

Intel Xeon Processor 5500 Series Datasheet, Volume 1

Land Listing

Table 4-1.

Land Listing by Land Name

(Sheet 17 of 36)

Table 4-1.

Land Listing by Land Name

(Sheet 18 of 36)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

DDR2_DQS_N[7]

DDR2_DQS_N[8]

DDR2_DQS_N[9]

DDR2_DQS_P[0]

DDR2_DQS_P[1]

DDR2_DQS_P[10]

DDR2_DQS_P[11]

DDR2_DQS_P[12]

DDR2_DQS_P[13]

DDR2_DQS_P[14]

DDR2_DQS_P[15]

DDR2_DQS_P[16]

DDR2_DQS_P[17]

DDR2_DQS_P[2]

DDR2_DQS_P[3]

DDR2_DQS_P[4]

DDR2_DQS_P[5]

DDR2_DQS_P[6]

DDR2_DQS_P[7]

DDR2_DQS_P[8]

DDR2_DQS_P[9]

DDR2_ECC[0]

T8

G30

T35

W37

T37

U40

M38

H38

H11

K9

CMOS

I/O

O

DDR2_MA[5]

DDR2_MA[6]

DDR2_MA[7]

DDR2_MA[8]

DDR2_MA[9]

DDR2_MA_PAR

DDR2_ODT[0]

DDR2_ODT[1]

DDR2_ODT[2]

DDR2_ODT[3]

DDR2_PAR_ERR#[0]

DDR2_PAR_ERR#[1]

DDR2_PAR_ERR#[2]

DDR2_RAS#

DDR2_RESET#

DDR2_WE#

FC_AH5

K23

K22

J24

CMOS

Asynch

CMOS

O

I

L25

H22

B18

L16

F13

D15

D10

F21

N4

V6

J25

I

H31

K40

E39

J10

L7

F23

I

D17

E32

C16

AH5

AJ37

AK8

AH36

AK35

B41

C42

AG35

AP7

AL39

A31

A40

AF1

O

P6

GTLREF

Analog

Asynch

GTL

I

U8

ISENSE

G29

U35

H32

F33

E29

E30

J31

J30

F31

F30

A18

K17

H17

H23

G23

F15

H24

G25

G18

J20

F20

PECI

I/O

I

PECI_ID#

PRDY#

O

I

DDR2_ECC[1]

PREQ#

GTL

DDR2_ECC[2]

PROCHOT#

PSI#

GTL

I/O

O

I

DDR2_ECC[3]

CMOS

Asynch

DDR2_ECC[4]

RESET#

DDR2_ECC[5]

RSVD

DDR2_ECC[6]

RSVD

DDR2_ECC[7]

RSVD

DDR2_MA[0]

RSVD

AF4

DDR2_MA[1]

O

RSVD

AG1

AG4

AG5

AK2

AK7

AK36

AL3

DDR2_MA[10]

O

RSVD

DDR2_MA[11]

O

RSVD

DDR2_MA[12]

O

RSVD

DDR2_MA[13]

O

RSVD

DDR2_MA[14]

O

RSVD

DDR2_MA[15]

O

RSVD

DDR2_MA[2]

O

RSVD

AL38

AL4

DDR2_MA[3]

O

RSVD

DDR2_MA[4]

O

RSVD

AL40

®

Intel Xeon Processor 5500 Series Datasheet, Volume 1

57

Land Listing

Table 4-1.

Land Listing by Land Name

(Sheet 19 of 36)

Table 4-1.

Land Listing by Land Name

(Sheet 20 of 36)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

RSVD

AL41

AL5

RSVD

SKTOCC#

TCK

K15

K24

AM36

AM38

AN36

AN38

AR36

AR37

AT36

AT4

K25

K27

K29

L15

U11

V11

AG36

AH10

AJ9

GTL

TAP

O

I

AT5

TDI

TAP

I

AU2

TDO

AJ10

AG37

AG10

AH9

TAP

O

I

AV1

THERMTRIP#

TMS

GTL

AV2

TAP

AV35

AV42

AV43

AW2

AW39

AW41

AW42

AY3

TRST#

VCC

TAP

I

AH11

AH33

AJ11

AJ33

AK11

AK12

AK13

AK15

AK16

AK18

AK19

AK21

AK24

AK25

AK27

AK28

AK30

AK31

AK33

AL12

AL13

AL15

AL16

AL18

AL19

PWR

VCC

AY35

AY39

AY4

VCC

AY40

AY41

B33

VCC

BA4

VCC

BA40

C31

VCC

C32

VCC

D30

VCC

D31

VCC

E28

VCC

F27

VCC

F28

VCC

G28

VCC

H29

VCC

J29

VCC

®

58

Intel Xeon Processor 5500 Series Datasheet, Volume 1

Land Listing

Table 4-1.

Land Listing by Land Name

(Sheet 21 of 36)

Table 4-1.

Land Listing by Land Name

(Sheet 22 of 36)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

VCC

AL21

AL24

AL25

AL27

AL28

AL30

AL31

AL33

AL34

AM12

AM13

AM15

AM16

AM18

AM19

AM21

AM24

AM25

AM27

AM28

AM30

AM31

AM33

AM34

AN12

AN13

AN15

AN16

AN18

AN19

AN21

AN24

AN25

AN27

AN28

AN30

AN31

AN33

AN34

AP12

PWR

VCC

AP13

AP15

AP16

AP18

AP19

AP21

AP24

AP25

AP27

AP28

AP30

AP31

AP33

AP34

AR10

AR12

AR13

AR15

AR16

AR18

AR19

AR21

AR24

AR25

AR27

AR28

AR30

AR31

AR33

AR34

AT10

AT12

AT13

AT15

AT16

AT18

AT19

AT21

AT24

AT25

PWR

®

Intel Xeon Processor 5500 Series Datasheet, Volume 1

59

Land Listing

Table 4-1.

Land Listing by Land Name

(Sheet 23 of 36)

Table 4-1.

Land Listing by Land Name

(Sheet 24 of 36)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

VCC

AT27

AT28

AT30

AT31

AT33

AT34

AT9

PWR

VCC

AV9

AW10

AW12

AW13

AW15

AW16

AW18

AW19

AW21

AW24

AW25

AW27

AW28

AW30

AW31

AW33

AW34

AW9

PWR

AU10

AU12

AU13

AU15

AU16

AU18

AU19

AU21

AU24

AU25

AU27

AU28

AU30

AU31

AU33

AU34

AU9

AY10

AY12

AY13

AY15

AY16

AY18

AY19

AY21

AY24

AY25

AY27

AY28

AY30

AY31

AY33

AY34

AY9

AV10

AV12

AV13

AV15

AV16

AV18

AV19

AV21

AV24

AV25

AV27

AV28

AV30

AV31

AV33

AV34

BA10

BA12

BA13

BA15

BA16

®

60

Intel Xeon Processor 5500 Series Datasheet, Volume 1

Land Listing

Table 4-1.

Land Listing by Land Name

(Sheet 25 of 36)

Table 4-1.

Land Listing by Land Name

(Sheet 26 of 36)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

VCC

BA18

BA19

BA24

BA25

BA27

BA28

BA30

BA9

M11

M13

M15

M19

M21

M23

M25

M29

M31

M33

N11

N33

R11

R33

T11

PWR

Analog

PWR

Asynch

PWR

VDDQ

B32

B7

PWR

CMOS

VCC

VDDQ

VCC

VDDQ

C10

C15

C20

C25

C30

D13

D18

D23

D28

E11

E16

E21

E26

E31

F14

F19

F24

G17

G22

G27

H15

H20

H25

J18

VCC

VDDQ

VCC

VDDQ

VCC

VDDQ

VCC

VDDQ

VCC

VDDQ

VCC

VDDQ

VCC

VDDQ

VCC

VDDQ

VCC

VDDQ

VCC

VDDQ

VCC

VDDQ

VCC

VDDQ

VCC

VDDQ

VCC

VDDQ

VCC

VDDQ

VCC

VDDQ

VCC

VDDQ

VCC

VDDQ

VCC

VDDQ

VCC

VDDQ

VCC

T33

VDDQ

VCC

W11

AR9

U33

V33

W33

AR7

AA6

A14

A19

A24

A29

A9

VDDQ

VCC_SENSE

VCCPLL

VCCPWRGOOD

VDDPWRGOOD

VDDQ

J23

VDDQ

J28

VDDQ

K16

K21

K26

L14

L19

L24

M17

M27

AL10

AL9

AN9

AM10

I

VDDQ

B12

B17

B22

B27

VID[0]/MSID[0]

VID[1]/MSID[1]

VID[2]/MSID[2]

VID[3]/CSC[0]

O

®

Intel Xeon Processor 5500 Series Datasheet, Volume 1

61

Land Listing

Table 4-1.

Land Listing by Land Name

(Sheet 27 of 36)

Table 4-1.

Land Listing by Land Name

(Sheet 28 of 36)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

VID[4]/CSC[1]

VID[5]/CSC[2]

VID[6]

VID[7]

VSS

AN10

AP9

CMOS

CSMO

CMOS

GND

O

VSS

AG9

AH1

GND

AP8

AH34

AH37

AH39

AH7

AN8

A35

VSS

A39

VSS

A4

AJ34

AJ36

AJ41

AJ5

VSS

A41

VSS

A6

VSS

AA3

VSS

AA34

AA38

AA39

AA9

AK10

AK14

AK17

AK20

AK22

AK23

AK26

AK29

AK3

VSS

AB37

AB4

VSS

AB40

AB42

AB7

VSS

AC2

AK32

AK34

AK39

AK43

AK9

VSS

AC36

AC5

VSS

AC7

VSS

AC9

VSS

AD11

AD33

AD37

AD41

AD43

AE2

AL1

VSS

AL11

AL14

AL17

AL2

VSS

AL20

AL22

AL23

AL26

AL29

AL32

AL35

AL36

AL37

AL42

AL7

VSS

AE39

AE7

VSS

AF35

AF38

AF41

AF5

VSS

AG11

AG3

AG33

AG43

VSS

®

62

Intel Xeon Processor 5500 Series Datasheet, Volume 1

Land Listing

Table 4-1.

Land Listing by Land Name

(Sheet 29 of 36)

Table 4-1.

Land Listing by Land Name

(Sheet 30 of 36)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

VSS

AM11

AM14

AM17

AM20

AM22

AM23

AM26

AM29

AM32

AM35

AM37

AM39

AM5

GND

VSS

AP36

AP37

AP43

AP5

GND

AP6

AR11

AR14

AR17

AR2

AR20

AR22

AR23

AR26

AR29

AR3

AM9

AN11

AN14

AN17

AN20

AN22

AN23

AN26

AN29

AN3

AR32

AR35

AR39

AT11

AT14

AT17

AT20

AT22

AT23

AT26

AT29

AT32

AT35

AT38

AT41

AT7

AN32

AN35

AN37

AN41

AN7

AP1

AP10

AP11

AP14

AP17

AP20

AP22

AP23

AP26

AP29

AP32

AP35

AT8

AU1

AU11

AU14

AU17

AU20

AU22

AU23

AU26

®

Intel Xeon Processor 5500 Series Datasheet, Volume 1

63

Land Listing

Table 4-1.

Land Listing by Land Name

(Sheet 31 of 36)

Table 4-1.

Land Listing by Land Name

(Sheet 32 of 36)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

VSS

AU29

AU32

AU35

AU36

AU43

AU5

GND

VSS

AY32

AY37

AY42

AY7

B2

GND

B37

B42

BA11

BA14

BA17

BA20

BA26

BA29

BA3

BA35

BA39

BA5

C35

C40

C43

C5

AV11

AV14

AV17

AV20

AV22

AV23

AV26

AV29

AV32

AV39

AV4

AV41

AW1

AW11

AW14

AW17

AW20

AW22

AW23

AW26

AW29

AW32

AW35

AW6

D3

D33

D38

D43

D8

E1

E36

E41

E6

AW8

F29

F34

F39

F4

AY11

AY14

AY17

AY2

F9

AY20

AY22

AY23

AY26

AY29

G12

G2

G32

G37

G42

®

64

Intel Xeon Processor 5500 Series Datasheet, Volume 1

Land Listing

Table 4-1.

Land Listing by Land Name

(Sheet 33 of 36)

Table 4-1.

Land Listing by Land Name

(Sheet 34 of 36)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

VSS

G7

H10

H30

H35

H40

H5

GND

VSS

N40

N5

GND

Analog

CMOS

PWR

VSS

P11

P3

VSS

P33

P38

P43

P8

VSS

J13

J3

VSS

J33

J38

J43

J8

VSS

R1

VSS

R36

R41

R6

VSS

K1

VSS

T34

T39

T4

K11

K31

K36

K41

K6

VSS

T9

VSS

U2

VSS

U37

U42

U7

L29

L34

L39

L4

VSS

V10

V35

V40

V5

VSS

L9

VSS

M12

M14

M16

M18

M2

VSS

W3

VSS

W38

W43

W8

VSS

M20

M22

M24

M26

M28

M30

M32

M37

M42

M7

VSS

Y1

VSS

Y11

Y33

Y36

Y41

Y6

VSS

VSS_SENSE

VSS_SENSE_VTTD

VTT_VID2

VTT_VID3

VTT_VID4

VTTA

AR8

AE37

AV3

AF7

AV6

AD10

O

N10

N35

®

Intel Xeon Processor 5500 Series Datasheet, Volume 1

65

Land Listing

Table 4-1.

Land Listing by Land Name

(Sheet 35 of 36)

Table 4-1.

Land Listing by Land Name

(Sheet 36 of 36)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

VTTA

VTTD

AE10

AE11

AE33

AF11

AF33

AF34

AG34

AA10

AA11

AA33

AB10

AB11

AB33

AB34

AB8

PWR

VTTD

AC11

AC33

AC34

AC35

AD34

AD35

AD36

AD9

PWR

Analog

Asynch

VTTD

AE34

AE35

AE8

VTTD

AE9

VTTD

AF36

AF37

AF8

VTTD

AB9

VTTD

AF9

AC10

VTTD_SENSE

VTTPWRGOOD

AE36

AB35

I

®

66

Intel Xeon Processor 5500 Series Datasheet, Volume 1

Land Listing

4.1.2

Land Listing by Land Number

Table 4-2.

Land Listing by Land Number

(Sheet 2 of 35)

Table 4-2.

Land Listing by Land Number

(Sheet 1 of 35)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

AA34

AA35

AA36

AA37

AA38

AA39

AA40

AA41

AB3

VSS

GND

CMOS

GND

CMOS

QPI

A4

A5

VSS

GND

GTL

DDR1_DQ[4]

DDR1_DQ[1]

DDR1_DQ[0]

VSS

I/O

BPM#[1]

I/O

A6

VSS

GND

A7

DDR0_CS#[5]

DDR1_CS#[1]

VDDQ

CMOS

PWR

O

A8

VSS

A9

DDR1_DQS_P[9]

DDR1_DQS_N[9]

QPI1_DTX_DN[13]

VSS

I/O

O

A10

A14

A15

A16

A17

A18

A19

A20

A24

A25

A26

A27

A28

A29

A30

A31

A35

A36

A37

A38

A39

A40

A41

AA3

AA4

AA5

AA6

AA7

AA8

AA9

AA10

AA11

AA33

DDR0_MA[13]

VDDQ

CMOS

PWR

O

DDR0_RAS#

DDR0_BA[1]

DDR2_BA[0]

DDR2_MA[0]

VDDQ

CMOS

PWR

O

AB4

GND

CMOS

QPI

AB5

DDR_THERM#

QPI1_DTX_DP[16]

VSS

I

AB6

O

AB7

GND

PWR

Asynch

CMOS

GND

QPI

AB8

VTTD

DDR0_MA[0]

VDDQ

CMOS

PWR

O

AB9

VTTD

AB10

AB11

AB33

AB34

AB35

AB36

AB37

AB38

AB39

AB40

AB41

AB42

AB43

AC1

VTTD

DDR0_MA[7]

DDR0_MA[11]

DDR0_PAR_ERR#[2]

DDR0_MA[14]

VDDQ

CMOS

Asynch

CMOS

PWR

O

I

VTTD

O

VTTPWRGOOD

DDR1_DQ[5]

VSS

I

I/O

DDR0_CKE[1]

RSVD

CMOS

O

QPI0_DTX_DN[17]

QPI0_DTX_DP[17]

VSS

O

VSS

GND

CMOS

GND

QPI

DDR0_ECC[1]

DDR0_ECC[5]

DDR0_DQ[26]

VSS

I/O

GND

Analog

GND

QPI

COMP0

VSS

QPI0_DTX_DN[13]

DDR_COMP[2]

VSS

O

RSVD

Analog

GND

QPI

VSS

GND

AC2

VSS

AC3

QPI1_DTX_DP[13]

QPI1_DTX_DP[15]

VSS

O

BCLK_ITP_DN

BCLK_ITP_DP

VDDPWRGOOD

DDR1_DQ[62]

DDR_COMP[0]

VSS

CMOS

Asynch

CMOS

Analog

GND

O

AC4

QPI

AC5

GND

QPI

I

AC6

QPI1_DTX_DN[16]

VSS

O

I/O

AC7

GND

QPI

AC8

QPI1_DTX_DP[19]

VSS

AC9

GND

PWR

VTTD

PWR

AC10

AC11

VTTD

PWR

VTTD

PWR

®

Intel Xeon Processor 5500 Series Datasheet, Volume 1

67

Land Listing

Table 4-2.

Land Listing by Land Number

(Sheet 3 of 35)

Table 4-2.

Land Listing by Land Number

(Sheet 4 of 35)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

AC33

AC34

AC35

AC36

AC37

AC38

AC39

AC40

AC41

AC42

AC43

AD1

VTTD

VSS

PWR

GND

GTL

QPI

AE8

AE9

VTTD

VTTA

VTTD

PWR

Analog

QPI

AE10

AE11

AE33

AE34

AE35

AE36

AE37

AE38

AE39

AE40

AE41

AE42

AE43

AF1

CAT_ERR#

I/O

O

QPI0_DTX_DN[16]

QPI0_DTX_DP[16]

QPI0_DTX_DN[15]

QPI0_DTX_DP[15]

QPI0_DTX_DN[12]

QPI0_DTX_DP[13]

QPI1_DTX_DN[11]

QPI1_DTX_DP[12]

QPI1_DTX_DN[12]

QPI1_DTX_DN[15]

QPI1_DTX_DP[18]

QPI1_DTX_DP[17]

QPI1_DTX_DN[17]

QPI1_DTX_DN[19]

VTTD

QPI

VTTD_SENSE

VSS_SENSE_VTTD

QPI0_DTX_DN[18]

VSS

QPI

O

QPI

GND

QPI

QPI0_DTX_DP[19]

QPI0_DTX_DN[11]

QPI0_DTX_DP[11]

QPI0_DTX_DN[10]

RSVD

O

AD2

QPI

AD3

QPI

AD4

QPI

AD5

QPI

AD6

QPI

AF2

QPI1_DTX_DP[10]

QPI1_DTX_DN[10]

RSVD

QPI

O

AD7

QPI

AF3

AD8

QPI

AF4

AD9

PWR

GND

PWR

GND

QPI

AF5

VSS

GND

QPI

AD10

AD11

AD33

AD34

AD35

AD36

AD37

AD38

AD39

AD40

AD41

AD42

AD43

AE1

VTTA

AF6

QPI1_CLKTX_DP

VTT_VID3

VTTD

O

VSS

AF7

CMOS

PWR

Asynch

PWR

GND

PWR

VSS

AF8

VTTD

AF9

VTTD

AF10

AF11

AF33

AF34

AF35

AF36

AF37

AF38

AF39

AF40

AF41

AF42

AF43

AG1

DBR#

I

VTTD

VTTA

VSS

VTTA

QPI0_DTX_DP[18]

QPI0_DTX_DN[14]

QPI0_DTX_DP[14]

VSS

O

VTTA

QPI

VSS

QPI

VTTD

GND

QPI

VTTD

QPI0_DTX_DP[12]

VSS

O

VSS

GND

QPI

GND

QPI

GND

QPI

QPI0_DTX_DP[1]

QPI0_DTX_DN[19]

VSS

O

QPI1_DTX_DP[11]

VSS

AE2

GND

QPI

AE3

QPI1_DTX_DP[14]

QPI1_DTX_DN[14]

QPI1_DTX_DN[18]

QPI1_CLKTX_DN

VSS

O

QPI0_CLKTX_DN

QPI0_DTX_DP[10]

RSVD

O

AE4

QPI

AE5

QPI

AE6

QPI

AG2

QPI1_DTX_DN[9]

VSS

QPI

O

AE7

GND

AG3

GND

®

68

Intel Xeon Processor 5500 Series Datasheet, Volume 1

Land Listing

Table 4-2.

Land Listing by Land Number

(Sheet 5 of 35)

Table 4-2.

Land Listing by Land Number

(Sheet 6 of 35)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

AG4

AG5

RSVD

AH43

AJ1

QPI0_DTX_DN[8]

QPI1_DTX_DN[7]

QPI1_DTX_DN[6]

QPI1_DTX_DP[6]

QPI1_DTX_DP[4]

VSS

QPI

O

AG6

QPI1_DTX_DN[5]

QPI1_DTX_DP[5]

QPI1_DTX_DP[0]

VSS

QPI

GND

TAP

GND

PWR

GTL

QPI

GND

QPI

O

AJ2

QPI

AG7

AJ3

QPI

AG8

AJ4

QPI

AG9

AJ5

GND

QPI

AG10

AG11

AG33

AG34

AG35

AG36

AG37

AG38

AG39

AG40

AG41

AG42

AG43

AH1

TMS

I

AJ6

QPI1_DTX_DN[2]

QPI1_DTX_DN[1]

QPI1_DTX_DP[1]

TDI

O

I

VSS

AJ7

QPI

VSS

AJ8

QPI

VTTA

AJ9

TAP

PROCHOT#

SKTOCC#

I/O

O

AJ10

AJ11

AJ33

AJ34

AJ35

AJ36

AJ37

AJ38

AJ39

AJ40

AJ41

AJ42

AJ43

AK1

TDO

TAP

O

VCC

PWR

GND

CMOS

GND

Analog

QPI

THERMTRIP#

QPI0_DTX_DP[0]

QPI0_DTX_DN[1]

QPI0_DTX_DP[9]

QPI0_DTX_DN[9]

QPI0_CLKTX_DP

VSS

O

VCC

O

VSS

O

BCLK_DP

VSS

I

O

GTLREF

I

O

QPI0_DTX_DP[3]

QPI0_DTX_DN[3]

QPI0_DTX_DN[4]

VSS

O

QPI

VSS

QPI

AH2

QPI1_DTX_DP[9]

QPI1_DTX_DP[8]

QPI1_DTX_DN[8]

FC_AH5

O

GND

QPI

AH3

QPI0_DTX_DN[7]

QPI0_DTX_DP[8]

QPI1_DTX_DP[7]

RSVD

O

AH4

QPI

AH5

QPI

AH6

QPI1_DTX_DP[2]

VSS

QPI

GND

QPI

O

AK2

AH7

AK3

VSS

GND

QPI

AH8

QPI1_DTX_DN[0]

TRST#

O

I

AK4

QPI1_DTX_DN[4]

QPI1_DTX_DN[3]

QPI1_DTX_DP[3]

RSVD

O

AH9

TAP

AK5

AH10

AH11

AH33

AH34

AH35

AH36

AH37

AH38

AH39

AH40

AH41

AH42

TCK

TAP

I

AK6

VCC

PWR

GND

CMOS

Asynch

GND

QPI

AK7

VCC

AK8

ISENSE

Analog

GND

PWR

GND

PWR

GND

I

VSS

AK9

VSS

BCLK_DN

I

AK10

AK11

AK12

AK13

AK14

AK15

AK16

AK17

VSS

PECI

I/O

VCC

VSS

VCC

QPI0_DTX_DN[0]

VSS

O

VCC

GND

QPI

VSS

QPI0_DTX_DP[4]

QPI0_DTX_DP[6]

QPI0_DTX_DN[6]

O

VCC

QPI

VCC

QPI

VSS

®

Intel Xeon Processor 5500 Series Datasheet, Volume 1

69

Land Listing

Table 4-2.

Land Listing by Land Number

(Sheet 7 of 35)

Table 4-2.

Land Listing by Land Number

(Sheet 8 of 35)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

AK18

AK19

AK20

AK21

AK22

AK23

AK24

AK25

AK26

AK27

AK28

AK29

AK30

AK31

AK32

AK33

AK34

AK35

AK36

AK37

AK38

AK39

AK40

AK41

AK42

AK43

AL1

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

Asynch

AL15

AL16

AL17

AL18

AL19

AL20

AL21

AL22

AL23

AL24

AL25

AL26

AL27

AL28

AL29

AL30

AL31

AL32

AL33

AL34

AL35

AL36

AL37

AL38

AL39

AL40

AL41

AL42

AL43

AM1

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

RSVD

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PECI_ID#

RSVD

I

QPI0_DTX_DP[2]

QPI0_DTX_DN[2]

VSS

QPI

O

GND

QPI

QPI0_DTX_DP[5]

QPI0_DTX_DN[5]

QPI0_DTX_DP[7]

VSS

O

QPI

RESET#

Asynch

I

GND

RSVD

VSS

RSVD

AL2

VSS

GND

Analog

QPI

AL3

RSVD

QPI0_COMP

QPI1_DRX_DN[13]

QPI1_DRX_DP[14]

QPI1_DRX_DN[14]

QPI1_DRX_DP[16]

VSS

AL4

RSVD

I

AL5

RSVD

AM2

QPI

AL6

QPI1_COMP

VSS

Analog

GND

QPI

AM3

QPI

AL7

AM4

QPI

AL8

QPI1_DRX_DN[19]

VID[1]/MSID[1]

VID[0]/MSID[0]

VSS

I

AM5

GND

QPI

AL9

CMOS

GND

O

AM6

QPI1_DRX_DP[18]

QPI1_DRX_DN[18]

QPI1_DRX_DP[19]

VSS

I

AL10

AL11

AL12

AL13

AL14

AM7

QPI

AM8

QPI

VCC

PWR

AM9

GND

CMOS

GND

VCC

PWR

AM10

AM11

VID[3]/CSC[0]

VSS

O

VSS

GND

®

70

Intel Xeon Processor 5500 Series Datasheet, Volume 1

Land Listing

Table 4-2.

Land Listing by Land Number

(Sheet 9 of 35)

Table 4-2.

Land Listing by Land Number

(Sheet 10 of 35)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

AM12

AM13

AM14

AM15

AM16

AM17

AM18

AM19

AM20

AM21

AM22

AM23

AM24

AM25

AM26

AM27

AM28

AM29

AM30

AM31

AM32

AM33

AM34

AM35

AM36

AM37

AM38

AM39

AM40

AM41

AM42

AM43

AN1

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

RSVD

VSS

RSVD

VSS

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

AN9

AN10

AN11

AN12

AN13

AN14

AN15

AN16

AN17

AN18

AN19

AN20

AN21

AN22

AN23

AN24

AN25

AN26

AN27

AN28

AN29

AN30

AN31

AN32

AN33

AN34

AN35

AN36

AN37

AN38

AN39

AN40

AN41

AN42

AN43

AP1

VID[2]/MSID[2]

CMOS

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

O

VID[4]/CSC[1]

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

GND

VCC

VSS

GND

QPI

RSVD

QPI0_DRX_DN[15]

QPI0_DRX_DN[16]

QPI0_DRX_DP[16]

QPI0_DRX_DN[14]

QPI1_DRX_DP[13]

QPI1_DRX_DN[12]

VSS

I

VSS

GND

QPI

RSVD

QPI

QPI0_DRX_DP[18]

QPI0_DRX_DP[15]

VSS

QPI

GND

QPI

GND

QPI

GND

I

QPI

AN2

QPI

QPI0_DRX_DN[13]

QPI0_DRX_DP[14]

VSS

I

AN3

GND

QPI

AN4

QPI1_DRX_DN[16]

QPI1_DRX_DP[17]

QPI1_DRX_DN[17]

VSS

I

AN5

QPI

AP2

QPI1_DRX_DP[12]

QPI1_DRX_DP[15]

QPI1_DRX_DN[15]

VSS

I

AN6

QPI

AP3

AN7

GND

CMOS

AP4

AN8

VID[7]

O

AP5

®

Intel Xeon Processor 5500 Series Datasheet, Volume 1

71

Land Listing

Table 4-2.

Land Listing by Land Number

(Sheet 11 of 35)

Table 4-2.

Land Listing by Land Number

(Sheet 12 of 35)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

AP6

VSS

GND

CMOS

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

QPI

AR3

AR4

VSS

GND

QPI

AP7

PSI#

VID[6]

O

QPI1_DRX_DP[11]

I

AP8

AR5

QPI1_DRX_DN[11]

QPI

AP9

VID[5]/CSC[2]

AR6

QPI1_CLKRX_DN

QPI

AP10

AP11

AP12

AP13

AP14

AP15

AP16

AP17

AP18

AP19

AP20

AP21

AP22

AP23

AP24

AP25

AP26

AP27

AP28

AP29

AP30

AP31

AP32

AP33

AP34

AP35

AP36

AP37

AP38

AP39

AP40

AP41

AP42

AP43

AR1

VSS

AR7

VCCPWRGOOD

Asynch

Analog

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

VSS

AR8

VSS_SENSE

VCC

AR9

VCC_SENSE

VCC

AR10

AR11

AR12

AR13

AR14

AR15

AR16

AR17

AR18

AR19

AR20

AR21

AR22

AR23

AR24

AR25

AR26

AR27

AR28

AR29

AR30

AR31

AR32

AR33

AR34

AR35

AR36

AR37

AR38

AR39

AR40

AR41

AR42

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

QPI0_DRX_DP[19]

QPI0_DRX_DN[18]

QPI0_DRX_DN[17]

QPI0_DRX_DP[17]

QPI0_DRX_DP[13]

VSS

I

VSS

QPI

RSVD

QPI

RSVD

QPI

QPI0_DRX_DN[19]

VSS

QPI

GND

QPI

I

QPI

GND

QPI

QPI0_DRX_DN[12]

QPI0_CLKRX_DP

QPI0_CLKRX_DN

I

QPI1_DRX_DN[10]

VSS

I

AR2

GND

®

72

Intel Xeon Processor 5500 Series Datasheet, Volume 1

Land Listing

Table 4-2.

Land Listing by Land Number

(Sheet 13 of 35)

Table 4-2.

Land Listing by Land Number

(Sheet 14 of 35)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

AR43

AT1

QPI0_DRX_DN[11]

QPI

I

AT40

AT41

AT42

AT43

AU1

QPI0_DRX_DP[12]

QPI

GND

QPI

I

QPI1_DRX_DP[10]

VSS

AT2

QPI1_DRX_DN[9]

QPI0_DRX_DN[10]

I

AT3

QPI1_DRX_DP[9]

QPI0_DRX_DP[11]

QPI

AT4

RSVD

VSS

GND

AT5

RSVD

AU2

RSVD

AT6

QPI1_CLKRX_DP

QPI

I

AU3

QPI1_DRX_DN[8]

QPI

I

AT7

VSS

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

AU4

QPI1_DRX_DP[8]

AT8

VSS

AU5

VSS

GND

QPI

AT9

VCC

AU6

QPI1_DRX_DN[6]

I

AT10

AT11

AT12

AT13

AT14

AT15

AT16

AT17

AT18

AT19

AT20

AT21

AT22

AT23

AT24

AT25

AT26

AT27

AT28

AT29

AT30

AT31

AT32

AT33

AT34

AT35

AT36

AT37

AT38

AT39

VCC

AU7

QPI1_DRX_DP[6]

QPI

VSS

AU8

QPI1_DRX_DP[0]

VCC

QPI

VCC

AU9

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

VCC

AU10

AU11

AU12

AU13

AU14

AU15

AU16

AU17

AU18

AU19

AU20

AU21

AU22

AU23

AU24

AU25

AU26

AU27

AU28

AU29

AU30

AU31

AU32

AU33

AU34

AU35

AU36

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

RSVD

QPI0_DRX_DP[0]

VSS

VCC

QPI

GND

QPI

I

VCC

VSS

QPI0_DRX_DN[7]

VSS

®

Intel Xeon Processor 5500 Series Datasheet, Volume 1

73

Land Listing

Table 4-2.

Land Listing by Land Number

(Sheet 15 of 35)

Table 4-2.

Land Listing by Land Number

(Sheet 16 of 35)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

AU37

AU38

AU39

AU40

AU41

AU42

AU43

AV1

QPI0_DRX_DN[0]

QPI

GND

I

AV34

AV35

AV36

AV37

AV38

AV39

AV40

AV41

AV42

AV43

AW1

AW2

AW3

AW4

AW5

AW6

AW7

AW8

AW9

VCC

PWR

QPI0_DRX_DP[1]

RSVD

QPI0_DRX_DP[7]

QPI0_DRX_DP[2]

QPI0_DRX_DN[2]

QPI0_DRX_DN[1]

VSS

QPI

I

QPI0_DRX_DP[9]

QPI0_DRX_DN[9]

QPI

QPI0_DRX_DP[10]

GND

QPI

VSS

QPI0_DRX_DN[8]

VSS

I

RSVD

GND

AV2

RSVD

AV3

VTT_VID2

CMOS

GND

QPI

O

RSVD

AV4

VSS

GND

AV5

QPI1_DRX_DP[3]

I

O

I

RSVD

AV6

VTT_VID4

CMOS

QPI

QPI1_DRX_DN[7]

QPI1_DRX_DP[7]

QPI1_DRX_DN[3]

VSS

QPI

I

AV7

QPI1_DRX_DP[1]

AV8

QPI1_DRX_DN[0]

VCC

QPI

I

QPI

AV9

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

QPI

AV10

AV11

AV12

AV13

AV14

AV15

AV16

AV17

AV18

AV19

AV20

AV21

AV22

AV23

AV24

AV25

AV26

AV27

AV28

AV29

AV30

AV31

AV32

AV33

VCC

QPI1_DRX_DN[1]

VSS

I

VSS

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

VCC

AW10 VCC

AW11 VSS

AW12 VCC

AW13 VCC

AW14 VSS

AW15 VCC

AW16 VCC

AW17 VSS

AW18 VCC

AW19 VCC

AW20 VSS

AW21 VCC

AW22 VSS

AW23 VSS

AW24 VCC

AW25 VCC

AW26 VSS

AW27 VCC

AW28 VCC

AW29 VSS

AW30 VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

®

74

Intel Xeon Processor 5500 Series Datasheet, Volume 1

Land Listing

Table 4-2.

Land Listing by Land Number

(Sheet 17 of 35)

Table 4-2.

Land Listing by Land Number

(Sheet 18 of 35)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

AW31 VCC

AW32 VSS

AW33 VCC

AW34 VCC

AW35 VSS

PWR

GND

PWR

GND

QPI

AY30

AY31

AY32

AY33

AY34

AY35

AY36

AY37

AY38

AY39

AY40

AY41

AY42

B2

VCC

VSS

VCC

RSVD

PWR

GND

PWR

AW36 QPI0_DRX_DP[3]

AW37 QPI0_DRX_DP[5]

AW38 QPI0_DRX_DN[5]

AW39 RSVD

I

QPI

QPI0_DRX_DN[3]

VSS

QPI

GND

QPI

I

QPI

QPI0_DRX_DN[6]

RSVD

AW40 QPI0_DRX_DP[8]

AW41 RSVD

QPI

I

RSVD

AW42 RSVD

RSVD

AY2

AY3

VSS

GND

VSS

GND

RSVD

VSS

AY4

RSVD

B3

BPM#[0]

BPM#[3]

DDR0_DQ[32]

DDR0_DQ[36]

VDDQ

GTL

I/O

AY5

QPI1_DRX_DN[5]

QPI

I

B4

GTL

AY6

QPI1_DRX_DP[5]

B5

CMOS

PWR

AY7

VSS

GND

QPI

B6

AY8

QPI1_DRX_DP[2]

VCC

I

B7

AY9

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

B8

DDR0_CS#[7]/

DDR0_ODT[5]

CMOS

O

AY10

AY11

AY12

AY13

AY14

AY15

AY16

AY17

AY18

AY19

AY20

AY21

AY22

AY23

AY24

AY25

AY26

AY27

AY28

AY29

VCC

B9

DDR0_CS#[3]

DDR0_CS#[1]

DDR0_ODT[2]

VDDQ

CMOS

PWR

O

VSS

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

B27

B28

VCC

VSS

DDR0_WE#

DDR1_MA[13]

DDR0_CS#[4]

DDR0_BA[0]

VDDQ

CMOS

PWR

O

VCC

VSS

VCC

DDR2_MA_PAR

DDR0_MA[10]

DDR0_MA_PAR

DDR0_MA[1]

VDDQ

CMOS

PWR

O

VSS

VCC

VSS

VCC

DDR0_MA[4]

DDR0_MA[5]

DDR0_MA[8]

DDR0_MA[12]

VDDQ

CMOS

PWR

O

VCC

VSS

VCC

VSS

DDR0_PAR_ERR#[1]

Asynch

I

®

Intel Xeon Processor 5500 Series Datasheet, Volume 1

75

Land Listing

Table 4-2.

Land Listing by Land Number

(Sheet 19 of 35)

Table 4-2.

Land Listing by Land Number

(Sheet 20 of 35)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

B29

B30

DDR0_MA[15]

DDR0_CKE[2]

CMOS

PWR

O

BA36

BA37

BA38

BA39

BA40

C2

QPI0_DRX_DP[4]

QPI0_DRX_DN[4]

QPI0_DRX_DP[6]

VSS

QPI

GND

I

B31

DDR0_CKE[3]

B32

VDDQ

B33

RSVD

B34

DDR0_ECC[6]

CMOS

GND

I/O

BPM#[2]

GTL

I/O

B35

DDR0_DQS_N[17]

C3

BPM#[5]

B36

DDR0_DQS_P[17]

C4

DDR0_DQ[33]

VSS

CMOS

GND

B37

VSS

C5

B38

DDR0_DQ[31]

CMOS

GTL

I/O

O

C6

DDR0_DQ[37]

DDR0_ODT[3]

DDR1_ODT[1]

DDR0_ODT[1]

VDDQ

CMOS

PWR

I/O

O

B39

DDR0_DQS_P[3]

C7

B40

DDR0_DQS_N[3]

C8

O

B41

PRDY#

C9

O

B42

VSS

GND

C10

C11

BA3

VSS

GND

DDR0_CS#[6]/

DDR0_ODT[4]

CMOS

O

BA4

RSVD

C12

C13

C14

DDR0_CAS#

CMOS

O

BA5

VSS

GND

QPI

DDR0_CS#[2]

BA6

QPI1_DRX_DN[4]

I

DDR1_CS#[6]/

DDR1_ODT[4]

BA7

QPI1_DRX_DP[4]

QPI

BA8

QPI1_DRX_DN[2]

VCC

QPI

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

C25

C26

C27

C28

C29

C30

C31

C32

C33

C34

C35

VDDQ

PWR

CMOS

CLOCK

PWR

BA9

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

DDR2_WE#

DDR1_CS#[4]

DDR1_BA[0]

DDR0_CLK_N[1]

VDDQ

O

BA10

BA11

BA12

BA13

BA14

BA15

BA16

BA17

BA18

BA19

BA20

BA24

BA25

BA26

BA27

BA28

BA29

BA30

BA35

VCC

VSS

VCC

VSS

DDR1_CLK_P[0]

DDR1_PAR_ERR#[0]

DDR0_MA[2]

DDR0_MA[6]

VDDQ

CLOCK

Asynch

CMOS

PWR

O

I

VCC

O

VSS

VCC

DDR0_MA[9]

DDR1_CKE[3]

DDR0_BA[2]

DDR0_CKE[0]

VDDQ

CMOS

PWR

O

VSS

VCC

VSS

VCC

RSVD

VCC

RSVD

VSS

DDR0_ECC[3]

DDR0_ECC[7]

VSS

CMOS

GND

I/O

VCC

VSS

®

76

Intel Xeon Processor 5500 Series Datasheet, Volume 1

Land Listing

Table 4-2.

Land Listing by Land Number

(Sheet 21 of 35)

Table 4-2.

Land Listing by Land Number

(Sheet 22 of 35)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

C36

C37

C38

C39

C40

C41

C42

C43

D1

DDR0_ECC[0]

DDR0_ECC[4]

CMOS

GND

I/O

D33

D34

D35

D36

D37

D38

D39

D40

D41

D42

D43

E1

VSS

GND

CMOS

GND

DDR0_DQS_P[8]

DDR0_DQS_N[8]

DDR1_ECC[0]

DDR0_DQ[27]

VSS

I/O

DDR0_DQ[30]

DDR0_DQS_N[12]

VSS

DDR0_DQ[25]

PREQ#

CMOS

GTL

I/O

I

DDR0_DQS_P[12]

DDR0_DQ[24]

DDR0_DQ[28]

DDR0_DQ[29]

VSS

CMOS

GND

I/O

VSS

GND

BPM#[4]

GTL

I/O

D2

BPM#[6]

GTL

D3

VSS

GND

D4

DDR0_DQS_N[13]

DDR0_DQS_P[13]

DDR1_DQ[38]

DDR1_DQS_N[4]

VSS

CMOS

GND

I/O

VSS

GND

D5

E2

BPM#[7]

GTL

I/O

D6

E3

DDR0_DQS_P[4]

DDR0_DQS_N[4]

DDR1_DQ[34]

VSS

CMOS

GND

D7

E4

D8

E5

D9

DDR2_CS#[5]

DDR2_ODT[3]

DDR1_ODT[0]

DDR1_CS#[0]

VDDQ

CMOS

PWR

O

E6

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

D31

D32

E7

DDR1_DQS_P[4]

DDR1_DQ[33]

DDR1_DQ[32]

DDR1_CS#[5]

VDDQ

CMOS

PWR

I/O

O

E8

E9

E10

E11

E12

DDR1_ODT[2]

DDR2_ODT[2]

DDR2_CS#[2]

DDR2_RAS#

VDDQ

CMOS

PWR

O

DDR1_CS#[7]/

DDR1_ODT[5]

CMOS

O

E13

E14

E15

E16

E17

E18

E19

E20

E21

E22

E23

E24

E25

E26

E27

E28

E29

DDR1_CS#[3]

DDR1_CAS#

DDR1_CS#[2]

VDDQ

CMOS

PWR

O

DDR0_CLK_P[1]

DDR1_MA_PAR

DDR1_CLK_N[0]

DDR1_MA[7]

VDDQ

CLOCK

CMOS

CLOCK

CMOS

PWR

O

DDR2_CS#[4]

DDR0_CLK_N[2]

DDR0_CLK_N[3]

DDR0_CLK_P[3]

VDDQ

CMOS

CLOCK

PWR

O

DDR0_MA[3]

DDR0_PAR_ERR#[0]

DDR2_CKE[2]

DDR1_CKE[2]

VDDQ

CMOS

Asynch

CMOS

PWR

O

I

DDR1_MA[8]

DDR1_MA[11]

DDR1_MA[12]

DDR1_PAR_ERR#[1]

VDDQ

CMOS

Asynch

PWR

O

I

O

DDR1_RESET#

RSVD

CMOS

O

DDR1_CKE[1]

RSVD

CMOS

O

RSVD

DDR0_RESET#

CMOS

DDR2_ECC[2]

CMOS

I/O

®

Intel Xeon Processor 5500 Series Datasheet, Volume 1

77

Land Listing

Table 4-2.

Land Listing by Land Number

(Sheet 23 of 35)

Table 4-2.

Land Listing by Land Number

(Sheet 24 of 35)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

E30

E31

E32

E33

E34

E35

E36

E37

E38

E39

E40

E41

E42

E43

F1

DDR2_ECC[3]

VDDQ

CMOS

PWR

I/O

F27

F28

F29

F30

F31

F32

F33

F34

F35

F36

F37

F38

F39

F40

F41

F42

F43

G1

RSVD

VSS

DDR2_RESET#

DDR1_ECC[2]

DDR1_ECC[6]

DDR1_DQS_N[17]

VSS

CMOS

GND

O

GND

CMOS

GND

I/O

DDR2_ECC[7]

DDR2_ECC[6]

DDR0_ECC[2]

DDR2_ECC[1]

VSS

I/O

DDR1_ECC[4]

DDR2_DQ[31]

DDR2_DQS_P[3]

DDR2_DQS_N[3]

VSS

CMOS

GND

I/O

DDR1_DQS_P[17]

DDR1_ECC[1]

DDR1_ECC[5]

DDR2_DQ[30]

VSS

CMOS

GND

I/O

DDR0_DQ[18]

DDR0_DQ[19]

DDR0_DQ[34]

DDR0_DQ[39]

DDR0_DQ[38]

VSS

CMOS

GND

I/O

DDR2_DQ[25]

DDR0_DQS_P[2]

DDR0_DQ[23]

DDR0_DQ[22]

DDR0_DQ[44]

VSS

CMOS

GND

I/O

F2

F3

F4

F5

DDR1_DQ[35]

DDR1_DQ[39]

DDR1_DQS_N[13]

DDR1_DQS_P[13]

VSS

CMOS

GND

I/O

G2

F6

G3

DDR0_DQ[35]

DDR1_DQ[42]

DDR1_DQ[46]

DDR1_DQS_N[5]

VSS

CMOS

GND

I/O

F7

G4

F8

G5

F9

G6

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

F20

F21

F22

F23

F24

F25

F26

DDR1_DQ[36]

DDR1_ODT[3]

DDR0_ODT[0]

DDR2_ODT[1]

VDDQ

CMOS

PWR

I/O

O

G7

G8

DDR1_DQ[37]

DDR1_DQ[44]

DDR2_DQ[37]

DDR2_DQ[36]

VSS

CMOS

GND

I/O

O

G9

O

G10

G11

G12

G13

G14

G15

G16

G17

G18

G19

G20

G21

G22

G23

DDR2_MA[13]

DDR2_CAS#

DDR2_BA[1]

DDR0_CLK_P[2]

VDDQ

CMOS

CLOCK

PWR

O

DDR1_WE#

DDR1_RAS#

DDR0_CS#[0]

DDR2_CS#[0]

VDDQ

CMOS

PWR

O

DDR2_MA[4]

DDR2_PAR_ERR#[0]

DDR1_MA[5]

DDR2_PAR_ERR#[2]

VDDQ

CMOS

Asynch

CMOS

Asynch

PWR

O

I

DDR2_MA[2]

DDR1_CLK_P[1]

DDR1_CLK_N[1]

DDR2_CLK_N[2]

VDDQ

CMOS

CLOCK

PWR

O

I

DDR1_PAR_ERR#[2]

DDR1_MA[15]

Asynch

CMOS

I

O

DDR2_MA[12]

CMOS

O

®

78

Intel Xeon Processor 5500 Series Datasheet, Volume 1

Land Listing

Table 4-2.

Land Listing by Land Number

(Sheet 25 of 35)

Table 4-2.

Land Listing by Land Number

(Sheet 26 of 35)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

G24

G25

G26

G27

G28

G29

G30

G31

G32

G33

G34

G35

G36

G37

G38

G39

G40

G41

G42

G43

H1

DDR1_MA[9]

DDR2_MA[15]

CMOS

PWR

O

H21

H22

H23

H24

H25

H26

H27

H28

H29

H30

H31

H32

H33

H34

H35

H36

H37

H38

H39

H40

H41

H42

H43

J1

DDR2_CLK_P[2]

DDR2_MA[9]

DDR2_MA[11]

DDR2_MA[14]

VDDQ

CLOCK

CMOS

PWR

O

DDR2_CKE[1]

VDDQ

RSVD

DDR2_DQS_P[8]

DDR2_DQS_N[8]

DDR2_DQS_N[17]

VSS

CMOS

GND

I/O

DDR1_MA[14]

DDR1_BA[2]

DDR1_CKE[0]

RSVD

CMOS

O

DDR1_DQS_P[8]

DDR1_DQS_N[8]

DDR1_ECC[7]

DDR1_ECC[3]

VSS

CMOS

GND

I/O

VSS

GND

CMOS

GND

DDR2_DQS_P[17]

DDR2_ECC[0]

DDR1_DQ[24]

DDR1_DQ[29]

VSS

I/O

DDR2_DQS_N[12]

DDR2_DQ[29]

DDR2_DQ[24]

DDR0_DQS_N[2]

VSS

CMOS

GND

I/O

DDR1_DQ[23]

DDR2_DQ[27]

DDR2_DQS_P[12]

DDR2_DQ[28]

VSS

CMOS

GND

I/O

DDR0_DQS_N[11]

DDR0_DQ[41]

DDR0_DQ[40]

DDR0_DQ[45]

DDR1_DQ[43]

VSS

CMOS

GND

I/O

DDR0_DQ[16]

DDR0_DQS_P[11]

DDR0_DQ[17]

DDR0_DQS_N[14]

DDR0_DQS_P[14]

VSS

CMOS

GND

I/O

H2

H3

H4

H5

J2

H6

DDR1_DQS_P[5]

DDR1_DQS_P[14]

DDR1_DQ[40]

DDR1_DQ[45]

VSS

CMOS

GND

I/O

J3

H7

J4

DDR1_DQ[52]

DDR1_DQ[47]

DDR1_DQ[41]

DDR1_DQS_N[14]

VSS

CMOS

GND

I/O

H8

J5

H9

J6

H10

H11

H12

H13

H14

H15

H16

H17

H18

H19

H20

J7

DDR2_DQS_P[13]

DDR2_DQ[38]

DDR2_DQ[34]

DDR1_MA[10]

VDDQ

CMOS

PWR

I/O

O

J8

J9

DDR2_DQS_N[4]

DDR2_DQS_P[4]

DDR2_DQS_N[13]

DDR2_DQ[33]

VSS

CMOS

GND

I/O

J10

J11

J12

J13

J14

J15

DDR2_CS#[3]

DDR2_MA[10]

DDR1_CLK_P[3]

DDR1_CLK_N[3]

VDDQ

CMOS

CLOCK

PWR

O

DDR1_MA[0]

CMOS

O

DDR2_CS#[7]/

DDR2_ODT[5]

J16

J17

DDR1_MA[1]

DDR1_MA[2]

CMOS

O

®

Intel Xeon Processor 5500 Series Datasheet, Volume 1

79

Land Listing

Table 4-2.

Land Listing by Land Number

(Sheet 27 of 35)

Table 4-2.

Land Listing by Land Number

(Sheet 28 of 35)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

J18

J19

J20

J21

J22

J23

J24

J25

J26

J27

J28

J29

J30

J31

J32

J33

J34

J35

J36

J37

J38

J39

J40

J41

J42

J43

K1

VDDQ

PWR

CLOCK

CMOS

CLOCK

PWR

K15

K16

K17

K18

K19

K20

K21

K22

K23

K24

K25

K26

K27

K28

K29

K30

K31

K32

K33

K34

K35

K36

K37

K38

K39

K40

K41

K42

K43

L1

RSVD

VDDQ

DDR0_CLK_P[0]

DDR2_MA[3]

DDR2_CLK_N[0]

DDR2_CLK_P[0]

VDDQ

O

PWR

CMOS

CLOCK

PWR

DDR2_MA[1]

DDR1_CLK_P[2]

DDR0_CLK_N[0]

DDR2_CLK_N[1]

VDDQ

O

DDR2_MA[7]

DDR2_PAR_ERR#[1]

DDR2_CKE[0]

DDR1_MA[6]

VDDQ

CMOS

Asynch

CMOS

PWR

O

I

DDR2_MA[6]

DDR2_MA[5]

RSVD

CMOS

O

RSVD

VDDQ

PWR

DDR2_ECC[5]

DDR2_ECC[4]

DDR1_DQ[27]

VSS

CMOS

GND

I/O

RSVD

DDR1_MA[4]

RSVD

CMOS

O

DDR1_DQ[31]

VSS

CMOS

GND

I/O

DDR1_DQ[28]

DDR1_DQ[19]

DDR1_DQ[22]

DDR2_DQ[26]

VSS

CMOS

GND

I/O

DDR1_DQ[26]

DDR1_DQS_N[12]

DDR1_DQS_P[12]

DDR1_DQ[18]

VSS

CMOS

GND

I/O

DDR2_DQ[19]

DDR2_DQ[18]

DDR0_DQ[21]

DDR0_DQ[20]

VSS

CMOS

GND

I/O

DDR1_DQS_N[11]

DDR2_DQ[23]

DDR2_DQS_N[2]

DDR2_DQS_P[2]

VSS

CMOS

GND

I/O

VSS

GND

K2

DDR0_DQS_P[5]

DDR0_DQS_N[5]

DDR1_DQ[48]

DDR1_DQ[49]

VSS

CMOS

GND

I/O

DDR0_DQ[10]

DDR0_DQ[11]

DDR0_DQ[42]

DDR0_DQ[47]

DDR0_DQ[46]

VSS

CMOS

GND

I/O

K3

K4

K5

L2

K6

L3

K7

DDR2_DQS_N[5]

DDR2_DQS_N[14]

DDR2_DQS_P[14]

DDR2_DQ[41]

VSS

CMOS

GND

I/O

L4

K8

L5

DDR1_DQS_N[6]

DDR1_DQS_P[6]

DDR2_DQS_P[5]

DDR2_DQ[46]

VSS

CMOS

GND

I/O

K9

L6

K10

K11

K12

K13

K14

L7

L8

DDR2_DQ[32]

DDR1_BA[1]

DDR2_CS#[1]

CMOS

I/O

O

L9

L10

L11

DDR2_DQ[40]

DDR2_DQ[44]

CMOS

I/O

O

®

80

Intel Xeon Processor 5500 Series Datasheet, Volume 1

Land Listing

Table 4-2.

Land Listing by Land Number

(Sheet 29 of 35)

Table 4-2.

Land Listing by Land Number

(Sheet 30 of 35)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

L12

L13

L14

L15

L16

L17

DDR2_DQ[39]

DDR2_DQ[35]

CMOS

PWR

I/O

M9

DDR2_DQ[42]

DDR2_DQ[45]

CMOS

PWR

I/O

M10

M11

M12

M13

M14

M15

M16

M17

M18

M19

M20

M21

M22

M23

M24

M25

M26

M27

M28

M29

M30

M31

M32

M33

M34

M35

M36

M37

M38

M39

M40

M41

M42

M43

N1

VDDQ

VCC

RSVD

VSS

GND

DDR2_ODT[0]

CMOS

O

VCC

PWR

DDR2_CS#[6]/

DDR2_ODT[4]

VSS

GND

VCC

PWR

L18

L19

L20

L21

L22

L23

L24

L25

L26

L27

L28

L29

L30

L31

L32

L33

L34

L35

L36

L37

L38

L39

L40

L41

L42

L43

M1

DDR1_CLK_N[2]

VDDQ

CLOCK

PWR

O

VSS

GND

VDDQ

PWR

DDR2_CLK_P[1]

DDR2_CLK_N[3]

DDR2_CLK_P[3]

DDR_VREF

CLOCK

Analog

PWR

O

I

VSS

GND

VCC

PWR

VSS

GND

VCC

PWR

VDDQ

VSS

GND

DDR2_MA[8]

DDR2_BA[2]

DDR2_CKE[3]

DDR1_MA[3]

VSS

CMOS

GND

O

VCC

PWR

VSS

GND

VCC

PWR

VSS

GND

VDDQ

PWR

DDR1_DQS_P[3]

DDR1_DQS_N[3]

DDR1_DQ[30]

DDR1_DQ[25]

VSS

CMOS

GND

I/O

VSS

GND

VCC

PWR

VSS

GND

VCC

PWR

VSS

GND

DDR1_DQS_P[2]

DDR1_DQS_N[2]

DDR1_DQS_P[11]

DDR2_DQS_N[11]

VSS

CMOS

GND

I/O

VCC

PWR

DDR1_DQ[17]

DDR1_DQ[16]

DDR1_DQ[21]

VSS

CMOS

GND

I/O

DDR2_DQ[22]

DDR0_DQS_P[1]

DDR0_DQ[15]

DDR0_DQ[14]

DDR0_DQ[43]

VSS

CMOS

GND

I/O

DDR2_DQS_P[11]

DDR2_DQ[16]

DDR2_DQ[17]

DDR0_DQS_N[1]

VSS

CMOS

GND

I/O

M2

DDR0_DQS_N[10]

DDR0_DQ[48]

DDR0_DQ[49]

DDR0_DQ[53]

DDR2_DQS_P[15]

VSS

CMOS

GND

I/O

M3

DDR0_DQ[52]

DDR1_DQS_N[15]

DDR1_DQS_P[15]

DDR1_DQ[53]

VSS

CMOS

GND

I/O

M4

N2

M5

N3

M6

N4

M7

N5

M8

DDR2_DQ[47]

CMOS

I/O

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Intel Xeon Processor 5500 Series Datasheet, Volume 1

81

Land Listing

Table 4-2.

Land Listing by Land Number

(Sheet 31 of 35)

Table 4-2.

Land Listing by Land Number

(Sheet 32 of 35)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

N6

N7

DDR2_DQ[49]

DDR2_DQ[53]

CMOS

GND

I/O

R2

R3

DDR0_DQS_P[6]

DDR0_DQS_N[6]

DDR0_DQ[54]

DDR1_DQ[50]

VSS

CMOS

GND

I/O

N8

DDR2_DQ[52]

DDR2_DQ[43]

VSS

R4

N9

R5

N10

N11

N33

N34

N35

N36

N37

N38

N39

N40

N41

N42

N43

P1

R6

VCC

PWR

R7

DDR1_DQ[55]

DDR1_DQ[54]

DDR2_DQ[55]

DDR2_DQ[54]

VCC

CMOS

PWR

I/O

VCC

PWR

R8

DDR1_DQ[20]

VSS

CMOS

GND

I/O

R9

R10

R11

R33

R34

R35

R36

R37

R38

R39

R40

R41

R42

R43

T1

DDR2_DQ[21]

DDR1_DQ[14]

DDR1_DQ[15]

DDR1_DQ[11]

VSS

CMOS

GND

I/O

VCC

PWR

DDR1_DQ[12]

DDR1_DQ[13]

VSS

CMOS

GND

I/O

DDR0_DQ[8]

DDR0_DQS_P[10]

DDR0_DQ[9]

DDR0_DQS_N[15]

DDR0_DQS_P[15]

VSS

CMOS

GND

I/O

DDR1_DQS_N[1]

DDR1_DQS_P[1]

DDR2_DQ[10]

DDR2_DQ[15]

VSS

CMOS

GND

I/O

P2

P3

DDR0_DQ[3]

DDR0_DQ[2]

DDR0_DQ[50]

DDR0_DQ[51]

DDR0_DQ[55]

VSS

CMOS

GND

I/O

P4

DDR2_DQS_N[15]

DDR2_DQS_N[6]

DDR2_DQS_P[6]

DDR2_DQ[48]

VSS

CMOS

GND

I/O

P5

P6

T2

P7

T3

P8

T4

P9

DDR2_DQ[50]

DDR2_DQ[51]

VSS

CMOS

GND

I/O

T5

DDR1_DQ[51]

DDR2_DQ[60]

DDR2_DQ[61]

DDR2_DQS_N[7]

VSS

CMOS

GND

I/O

P10

P11

P33

P34

P35

P36

P37

P38

P39

P40

P41

P42

P43

R1

T6

T7

VSS

GND

T8

DDR1_DQ[8]

DDR1_DQ[9]

DDR1_DQS_P[10]

DDR1_DQS_N[10]

VSS

CMOS

GND

I/O

T9

T10

T11

T33

T34

T35

T36

T37

T38

T39

T40

DDR2_DQ[58]

VCC

CMOS

PWR

I/O

VCC

PWR

VSS

GND

DDR1_DQ[10]

DDR2_DQ[20]

DDR0_DQ[13]

DDR0_DQ[12]

VSS

CMOS

GND

I/O

DDR2_DQS_N[9]

DDR2_DQ[11]

DDR2_DQS_P[1]

DDR2_DQS_N[1]

VSS

CMOS

GND

I/O

VSS

GND

DDR2_DQS_N[10]

CMOS

I/O

®

82

Intel Xeon Processor 5500 Series Datasheet, Volume 1

Land Listing

Table 4-2.

Land Listing by Land Number

(Sheet 33 of 35)

Table 4-2.

Land Listing by Land Number

(Sheet 34 of 35)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

T41

T42

T43

U1

DDR2_DQ[14]

DDR0_DQ[7]

CMOS

GND

I/O

V37

V38

V39

V40

V41

V42

V43

W1

DDR2_DQ[6]

DDR2_DQ[7]

CMOS

GND

I/O

DDR0_DQS_P[0]

DDR0_DQ[60]

VSS

DDR2_DQ[13]

VSS

U2

DDR0_DQ[1]

DDR0_DQS_N[9]

DDR0_DQS_P[9]

DDR0_DQS_N[7]

DDR0_DQS_P[7]

VSS

CMOS

GND

I/O

U3

DDR0_DQ[61]

DDR0_DQ[56]

DDR2_DQ[56]

DDR2_DQ[57]

VSS

CMOS

GND

I/O

U4

U5

U6

W2

U7

W3

U8

DDR2_DQS_P[7]

DDR2_DQ[63]

DDR2_DQ[59]

RSVD

CMOS

I/O

W4

DDR0_DQ[63]

DDR1_DQ[61]

DDR1_DQ[56]

DDR1_DQ[57]

VSS

CMOS

GND

I/O

U9

W5

U10

U11

U33

U34

U35

U36

U37

U38

U39

U40

U41

U42

U43

V1

W6

W7

VCCPLL

PWR

CMOS

GND

W8

DDR2_DQ[4]

DDR2_DQS_P[9]

DDR2_DQ[3]

VSS

I/O

W9

DDR1_DQ[63]

DDR1_DQ[59]

VCC

CMOS

PWR

I/O

W10

W11

W33

W34

W35

W36

W37

W38

W39

W40

W41

W42

W43

Y1

VCCPLL

PWR

DDR2_DQ[8]

DDR2_DQ[9]

DDR2_DQS_P[10]

DDR0_DQ[6]

VSS

CMOS

GND

I/O

DDR2_DQ[0]

DDR2_DQ[1]

DDR2_DQS_N[0]

DDR2_DQS_P[0]

VSS

CMOS

GND

I/O

DDR0_DQS_N[0]

DDR0_DQ[57]

DDR0_DQS_P[16]

DDR0_DQS_N[16]

DDR0_DQ[62]

VSS

CMOS

GND

I/O

DDR2_DQ[12]

DDR0_DQ[4]

DDR0_DQ[0]

DDR0_DQ[5]

VSS

CMOS

GND

I/O

V2

V3

V4

V5

VSS

GND

V6

DDR2_DQS_P[16]

DDR2_DQS_N[16]

DDR2_DQ[62]

DDR1_DQ[60]

VSS

CMOS

GND

I/O

Y2

DDR0_DQ[58]

DDR0_DQ[59]

DDR1_DQS_P[16]

DDR1_DQS_N[16]

VSS

CMOS

GND

I/O

V7

Y3

V8

Y4

V9

Y5

V10

V11

V33

V34

V35

V36

Y6

RSVD

Y7

DDR_COMP[1]

DDR1_DQS_P[7]

DDR1_DQS_N[7]

DDR1_DQ[58]

VSS

Analog

CMOS

GND

VCCPLL

PWR

CMOS

GND

Y8

I/O

DDR2_DQ[5]

VSS

I/O

Y9

Y10

Y11

DDR2_DQ[2]

CMOS

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Intel Xeon Processor 5500 Series Datasheet, Volume 1

83

Land Listing

Table 4-2.

Land Listing by Land Number

(Sheet 35 of 35)

Land

No.

Buffer

Type

Land Name

Direction

Y33

Y34

Y35

Y36

Y37

Y38

Y39

Y40

Y41

VSS

GND

CMOS

GND

DDR1_DQ[3]

DDR1_DQ[2]

VSS

I/O

DDR1_DQS_N[0]

DDR1_DQS_P[0]

DDR1_DQ[7]

DDR1_DQ[6]

VSS

CMOS

GND

I/O

§

®

84

Intel Xeon Processor 5500 Series Datasheet, Volume 1

Signal Definitions

5 Signal Definitions

5.1

Signal Definitions

Table 5-1.

Signal Definitions (Sheet 1 of 4)

Name

Type

Description

Differential bus clock input to the processor.

Notes

BCLK_DN

BCLK_DP

I

BCLK_ITP_DN

BCLK_ITP_DP

O

Buffered differential bus clock pair to ITP.

BPM#[7:0]

CAT_ERR#

I/O

BPM#[7:0] are breakpoint and performance monitor signals. They are outputs from

the processor which indicate the status of breakpoints and programmable counters

used for monitoring processor performance. BPM#[7:0] should be connected in a

wired OR topology between all packages on a platform.

I/O

Indicates that the system has experienced a catastrophic error and cannot continue

to operate. The processor will set this for non-recoverable machine check errors

other internal unrecoverable error. It is expected that every processor in the

system will have this hooked up in a wired-OR configuration. Since this is an I/O

pin, external agents are allowed to assert this pin which will cause the processor to

take a machine check exception.

On Intel Xeon processor 5500 series, CAT_ERR# is used for signalling the following

types of errors:

•

Legacy MCERR’s, CAT_ERR# is pulsed for 16 BCLKs.

Legacy IERR’s, CAT_ERR remains asserted until warm or cold reset.

COMP0

I

Impedance Compensation must be terminated on the system board using precision

resistor.

QPI0_CLKRX_DN

QPI0_CLKRX_DP

Intel QuickPath Interconnect received clock is the input clock that corresponds to

Intel QuickPath Interconnect port0 received data.

I

QPI0_CLKTX_DN

QPI0_CLKTX_DP

O

Intel QuickPath Interconnect forwarded clock sent with Intel QuickPath

Interconnect port 0 outbound data.

QPI0_COMP

I

Must be terminated on the system board using precision resistor.

QPI0_DRX_DN[19:0]

QPI0_DRX_DP[19:0]

I

QPI0_DRX_DN[19:0] and QPI0_DRX_DP[19:0] comprise the differential receive

data for Intel QuickPath Interconnect port0. The inbound 20 lanes are connected to

another component’s outbound lanes.

QPI0_DTX_DN[19:0]

QPI0_DTX_DP[19:0]

O

QPI0_DTX_DN[19:0] and QPI0_DTX_DP[19:0] comprise the differential transmit

data for Intel QuickPath Interconnect port0. The outbound 20 lanes are connected

to another component’s inbound lanes.

QPI1_CLKRX_DN

QPI1_CLKRX_DP

I

Intel QuickPath Interconnect received clock is the input clock that corresponds to

Intel QuickPath Interconnect 1 port received data.

QPI1_CLKTX_DN

QPI1_CLKTX_DP

O

Intel QuickPath Interconnect forwarded clock sent with Intel QuickPath

Interconnect port1 outbound data.

QPI1_COMP

I

Must be terminated on the system board using precision resistor.

QPI1_DRX_DN[19:0]

QPI1_DRX_DP[19:0]

QPI1_DRX_DN[19:0] and QPI1_DRX_DP[19:0] comprise the differential receive

data for Intel QuickPath Interconnect port1. The inbound 20 lanes are connected to

another component’s outbound lanes.

I

QPI1_DTX_DN[19:0]

QPI1_DTX_DP[19:0]

O

QPI1_DTX_DN[19:0] and QPI1_DTX_DP[19:0] comprise the differential transmit

data for Intel QuickPath Interconnect port1. The outbound 20 lanes are connected

to another component’s inbound lanes.

O

I

DBR#

DBR# is used only in systems where no debug port is implemented on the system

board. DBR# is used by a debug port interposer so that an in-target probe can

drive system reset.

DDR_COMP[2:0]

I

Must be terminated on the system board using precision resistors.

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Intel Xeon Processor 5500 Series Datasheet, Volume 1

85

Signal Definitions

Table 5-1.

Signal Definitions (Sheet 2 of 4)

Name

Type

Description

Notes

DDR_THERM#

I

DDR_THERM# is used for imposing duty cycle throttling on all memory channels.

The platform should ensure that DDR_THERM# is exerted when any DIMM is over

T64 (85 °C)

1

DDR{0/1/2}_BA[2:0]

O

Defines the bank which is the destination for the current Activate, Read, Write, or

Precharge command.

DDR{0/1/2}_CAS#

O

Column Address Strobe.

Clock Enable.

DDR{0/1/2}_CKE[3:0]

DDR{0/1/

2}_CLK_N[3:0]

Differential clocks to the DIMM. All command and control signals are valid on the

rising edge of clock.

DDR{0/1/

2}_CLK_P[3:0]

DDR{0/1/2}_CS[7:0]#

DDR{0/1/2}_DQ[63:0]

O

Each signal selects one rank as the target of the command and address.

DDR3 Data bits.

I/O

DDR{0/1/

2}_DQS_N[17:0]

DDR{0/1/

2}_DQS_P[17:0]

Differential pair, Data/ECC Strobe. Differential strobes latch data/ECC for each

DRAM. Different numbers of strobes are used depending on whether the connected

DRAMs are x4,x8. Driven with edges in center of data, receive edges are aligned

with data edges.

DDR{0/1/2}_ECC[7:0]

I/O

O

Check Bits - An Error Correction Code is driven along with data on these lines for

DIMMs that support that capability.

DDR{0/1/2}_MA[15:0]

Selects the Row address for Reads and writes, and the column address for

activates. Also used to set values for DRAM configuration registers.

DDR{0/1/2}_MA_PAR

DDR{0/1/2}_ODT[3:0]

O

Odd parity across Address and Command.

Enables various combinations of termination resistance in the target and non-target

DIMMs when data is read or written

DDR{0/1/

2}_PAR_ERR#[2:0]

I

Parity Error detected by Registered DIMM (one for each DIMM).

DDR{0/1/2}_RAS#

O

Row Address Strobe.

DDR{0/1/2}_RESET#

Resets DRAMs. Held low on power up, held high during self refresh, otherwise

controlled by configuration register.

DDR_VREF

DDR{0/1/2}_WE#

GTLREF

I

O

Voltage reference for DDR3.

Write Enable.

I

Voltage reference for GTL signals.

Current sense for VRD11.1.

ISENSE

I

PECI

I/O

PECI (Platform Environment Control Interface) is the serial sideband interface to

the processor and is used primarily for thermal, power and error management.

PECI_ID#

PRDY#

I

PECI_ID# is the PECI client address identifier. Assertion of this pin results in a PECI

client address of 0x31 (versus the default 0x30 client address). This pin is primarily

useful for PECI client address differentiation in DP platforms. One of the two

processors must be pulled down to VSS to strap to the address of 0x31.

O

PRDY# is a processor output used by debug tools to determine processor debug

readiness.

PREQ#

I/O

PREQ# is used by debug tools to request debug operation of the processor.

PROCHOT#

PROCHOT# will go active when the processor temperature monitoring sensor

detects that the processor has reached its maximum safe operating temperature.

This indicates that the processor Thermal Control Circuit has been activated, if

enabled. This signal can also be driven to the processor to activate the Thermal

Control Circuit.

If PROCHOT# is asserted at the deassertion of RESET#, the processor will tri-state

its outputs. This signal does not have on-die termination and must be terminated

on the system board.

®

86

Intel Xeon Processor 5500 Series Datasheet, Volume 1

Signal Definitions

Table 5-1.

Signal Definitions (Sheet 3 of 4)

Name

Type

Description

Notes

PSI#

O

Processor Power Status Indicator signal. This signal is asserted when maximum

possible processor core current consumption is less than 20A, Assertion of this

signal is an indication that the VR controller does not currently need to be able to

provide ICC above 20A, and the VR controller can use this information to move to

more efficient operation point. This signal will de-assert at least 3.3 µs before the

current consumption will exceed 20A. The minimum PSI# assertion time is 1 BCLK.

The minimum PSI# de-assertion time is 3.3 us.

This pin does not require a pull-down. For platforms which could experience false

PSI# assertions during power-up if this pin is left floating, a pull-up may be used

(1K-5K). Otherwise, it can be left floating. For boards currently pulling this signal to

Vss, this is not a critical change to make immediately, but it is recommended for

production builds.

RESET#

I

Asserting the RESET# signal resets the processor to a known state and invalidates

its internal caches without writing back any of their contents. Note some PLL, Intel

QuickPath Interconnect and error states are not effected by reset and only

VCCPWRGOOD forces them to a known state. For a power-on Reset, RESET# must

stay active for at least one millisecond after VCC and BCLK have reached their

proper specifications. RESET# must not be kept asserted for more than 10 ms

while VCCPWRGOOD is asserted. RESET# must be held deasserted for at least one

millisecond before it is asserted again. RESET# must be held asserted before

VCCPWRGOOD is asserted. This signal does not have on-die termination and must

be terminated on the system board. RESET# is a common clock signal.

SKTOCC#

TCK

O

I

Socket occupied, platform must sense a VSS at this pin to enable POWER_ON.

TCK (Test Clock) provides the clock input for the processor Test Bus (also known as

the Test Access Port).

TDI

I

TDI (Test Data In) transfers serial test data into the processor. TDI provides the

serial input needed for JTAG specification support.

TDO

O

TDO (Test Data Out) transfers serial test data out of the processor. TDO provides

the serial output needed for JTAG specification support.

THERMTRIP#

Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction

temperature has reached a level beyond which permanent silicon damage may

occur. Measurement of the temperature is accomplished through an internal

thermal sensor. Once activated, the processor will stop all execution and shut down

all PLLs. To further protect the processor, its core voltage (V ), V

V

and V

CC

TTA TTD DDQ

must be removed following the assertion of THERMTRIP#. Once activated,

THERMTRIP# remains latched until RESET# is asserted. While the assertion of the

RESET# signal may de-assert THERMTRIP#, if the processor's junction temperature

remains at or above the trip level, THERMTRIP# will again be asserted after

RESET# is de-asserted.

TMS

I

TMS (Test Mode Select) is a JTAG specification support signal used by debug tools.

TRST#

TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven

low during power on Reset.

V

O

V

and V

provide an isolated, low impedance connection to the

SS_SENSE

CC_SENSE

SS_SENSE

CC_SENSE

processor core voltage and ground. They can used to sense or measure power near

the silicon with little noise.

V

I

Power for processor core.

CC

VCCPWRGOOD

VCCPWRGOOD (Power Good) is a processor input. The processor requires this

signal to be a clean indication that BCLK, V , V

, V

and V

supplies are

CC

CCPLL

TTA

TTD

stable and within their specifications. 'Clean' implies that the signal will remain low

(capable of sinking leakage current), without glitches, from the time that the power

supplies are turned on until they come within specification. The signal must then

transition monotonically to a high state. VCCPWRGOOD can be driven inactive at

any time, but BCLK and power must again be stable before a subsequent rising

edge of VCCPWRGOOD. In addition at the time VCCPWRGOOD is asserted RESET#

must be active. The PWRGOOD signal must be supplied to the processor; it is used

to protect internal circuits against voltage sequencing issues. It should be driven

high throughout boundary scan operation.

V

I

Analog Power for Clocks.

CCPLL

DDQ

Power supply for the DDR3 interface.

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Signal Definitions

Table 5-1.

Signal Definitions (Sheet 4 of 4)

Name

VTT_VID[4:2]

Type

Description

Notes

O

VTT_VID[4:2] is used to support automatic selection of power supply voltages

(V ). The voltage supply for this signal must be valid before the VR can supply V

TT

to the processor. Conversely, the VR output must be disabled until the voltage

supply for the VID signal become valid. The VID signal is needed to support the

processor voltage specification variations. The VR must supply the voltage that is

requested by the signal.

V

I

Power for the analog portion of the Intel QuickPath Interconnect and Shared Cache.

Power for the digital portion of the Intel QuickPath Interconnect and Shared Cache.

TTA

TTD

VDDPWRGOOD

VDDPWRGOOD is an input that indicates the Vddq power supply is good. The

processor requires this signal to be a clean indication that the Vddq power supply is

stable and within their specifications. "Clean" implies that the signal will remain low

(capable of sinking leakage current), without glitches, from the time that the Vddq

supply is turned on until it come within specification. The signals must then

transition monotonically to a high state.

The PwrGood signal must be supplied to the processor, This signal is used to protect

internal circuits against voltage sequencing issues.

2

VID[7:6]

VID[5:3]/CSC[2:0]

VID[2:0]/MSID[2:0]

I/O

VID[7:0] (Voltage ID) are output signals that are used to support automatic

selection of power supply voltages (V ). The voltage supply for these signals must

CC

be valid before the VR can supply V to the processor. Conversely, the VR output

CC

must be disabled until the voltage supply for the VID signals become valid. The VID

signals are needed to support the processor voltage specification variations. The VR

must supply the voltage that is requested by the signals, or disable itself.

VID7 and VID6 should be tied separately to V via 1kOhm resistors during reset

SS

(this value is latched on the rising edge of VTTPWRGOOD).

MSID[2:0] - Market Segment ID, or MSID are provided to indicate the Market

Segment for the processor and may be used for future processor compatibility or

for keying. In addition, MSID protects the platform by preventing a higher power

processor from booting in a platform designed for lower power processors. This

value is latched from the platform in to the CPU, on the rising edge of

VTTPWRGOOD, during the cold boot power up sequence.

CSC[2:0] - Current Sense Configuration bits are output signals for ISENSE gain

setting. This value is latched on the rising edge of VTTPWRGOOD.

V

O

V

and V

provide an isolated, low impedance connection to the

SS_SENSE_VTT

TTD_SENSE

processor power and ground. They can used to sense or measure power near the

silicon.

SS_SENSE_VTT

VTTPWRGOOD

I

The processor requires this input signal to be a clean indication that the VTT power

supply is stable and within their specifications. 'Clean' implies that the signal will

remain low (capable of sinking leakage current), without glitches, from the time

that the power supplies are turned on until they come within specification. The

signal must then transition monotonically to a high state. to determine that the VTT

voltage is stable and within specification. Note it is not valid for VTTPWRGOOD to

be deasserted while VCCPWRGOOD is asserted.

V

The processor ground.

SS

Notes:

1. DDR{0/1/2} refers to DDR3 Channel 0, DDR3 Channel 1, and DDR3 Channel 2.

2. VID[7:0] is an Input only during Power On Configuration. It is an Output signal during normal operation.

§

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Thermal Specifications

6 Thermal Specifications

6.1

Package Thermal Specifications

The Intel^®Xeon^®processor 5500 series requires a thermal solution to maintain

temperatures within operating limits. Any attempt to operate the processor outside

these limits may result in permanent damage to the processor and potentially other

components within the system. Maintaining the proper thermal environment is key to

reliable, long-term system operation.

A complete solution includes both component and system level thermal management

features. Component level thermal solutions can include active or passive heatsinks

attached to the processor integrated heat spreader (IHS). Typical system level thermal

solutions may consist of system fans combined with ducting and venting.

This section provides data necessary for developing a complete thermal solution. For

more information on designing a component level thermal solution, refer to the Intel®

Xeon® Processor 5500/5600 Series Thermal/Mechanical Design Guide.

Note:

The boxed processor will ship with a component thermal solution. Refer to Section 8 for

details on the boxed processor.

6.1.1

Thermal Specifications

To allow optimal operation and long-term reliability of Intel processor-based systems,

the processor must remain within the minimum and maximum case temperature

(T_CASE) specifications as defined by the applicable thermal profile. See Table 6-2 and

Figure 6-1 for Intel^®Xeon^®Processor W5580 (130W TDP); Table 6-4 and Table 6-5,

and Figure 6-2 for Intel Xeon processor 5500 series Advanced SKU (95W TDP);

Table 6-7 and Figure 6-3 for Intel Xeon processor 5500 series Standard/Basic SKUs

(80W TDP); Table 6-9 and Figure 6-4 for Intel Xeon processor 5500 series Low Power

SKU (60W TDP); Table 6-11 and Figure 6-5 for Intel^®Xeon^®Processor L5518 (60W

TDP) supporting NEBS thermals; Table 6-13 and Figure 6-6 for Intel^®Xeon^®Processor

L5508 (38W TDP) supporting NEBS thermals. Thermal solutions not designed to

provide this level of thermal capability may affect the long-term reliability of the

processor and system. For more details on thermal solution design, please refer to this

processor’s TMDG.

The Intel Xeon processor 5500 series implement a methodology for managing

processor temperatures which is intended to support acoustic noise reduction through

fan speed control and to assure processor reliability. Selection of the appropriate fan

speed is based on the relative temperature data reported by the processor’s Platform

Environment Control Interface (PECI) as described in Section 6.3. If PECI is less than

TCONTROL, then the case temperature is permitted to exceed the Thermal Profile, but

PECI must remain at or below TCONTROL. If PECI >= TCONTROL, then the case

temperature must meet the Thermal Profile. The temperature reported over PECI is

always a negative value and represents a delta below the onset of thermal control

circuit (TCC) activation, as indicated by PROCHOT# (see Section 6.2, Processor

Thermal Features). Systems that implement fan speed control must be designed to use

this data. Systems that do not alter the fan speed only need to guarantee the case

temperature meets the thermal profile specifications.

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Intel Xeon Processor 5500 Series Datasheet, Volume 1

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Thermal Specifications

The Intel Xeon Processor W5580 (see Figure 6-1; Table 6-2) supports a single Thermal

Profile. For this processor, it is expected that the Thermal Control Circuit (TCC) would

only be activated for very brief periods of time when running the most power-intensive

applications. Refer to the Intel® Xeon® Processor 5500/5600 Series Thermal /

Mechanical Design Guide for details on system thermal solution design, thermal profiles

and environmental considerations.

The Intel Xeon processor 5500 series Advanced SKU supports two thermal profiles,

either of which can be implemented. Both ensure adherence to Intel reliability

requirements. Thermal Profile A (see Figure 6-2; Table 6-4) is representative of a

volumetrically unconstrained thermal solution (that is, industry enabled 2U heatsink).

In this scenario, it is expected that the Thermal Control Circuit (TCC) would only be

activated for very brief periods of time when running the most power intensive

applications. Thermal Profile B (see Figure 6-2; Table 6-5) is indicative of a constrained

thermal environment (that is, 1U form factor). Because of the reduced cooling

capability represented by this thermal solution, the probability of TCC activation and

performance loss is increased. Additionally, utilization of a thermal solution that does

not meet Thermal Profile B will violate the thermal specifications and may result in

permanent damage to the processor. Refer to this processor’s TMDG for details on

system thermal solution design, thermal profiles and environmental considerations.

The upper point of the thermal profile consists of the Thermal Design Power (TDP) and

the associated T_CASEvalue. It should be noted that the upper point associated with the

Intel Xeon processor 5500 series Advanced SKU Thermal Profile B (x = TDP and

y = T_{CASE_MAX_B}@ TDP) represents a thermal solution design point. In actuality the

processor case temperature will not reach this value due to TCC activation (see

Figure 6-2 for Intel Xeon processor 5500 series Advanced SKU).

The Intel Xeon processor 5500 series Standard/Basic SKUs (see Figure 6-3; Table 6-7)

support a single Thermal Profile. For this processor, it is expected that the Thermal

Control Circuit (TCC) would only be activated for very brief periods of time when

running the most power-intensive applications. Refer to this processor’s TMDG for

details on system thermal solution design, thermal profiles and environmental

considerations.

The Intel Xeon processor 5500 series Low Power SKU (see Figure 6-4; Table 6-9)

supports a single Thermal Profile. For this processor, it is expected that the Thermal

Control Circuit (TCC) would only be activated for very brief periods of time when

running the most power-intensive applications. Refer to this processor’s TMDG for

details on system thermal solution design, thermal profiles and environmental

considerations.

The Intel Xeon Processor L5518 and Intel Xeon Processor L5508 both support Thermal

Profiles with nominal and short-term conditions designed to meet NEBS level 3

compliance (see Figure 6-5 and Figure 6-6 respectively). For these SKU’s operation at

either the nominal or short-term thermal profiles should result in virtually no TCC

activation.

Analysis indicates that real applications are unlikely to cause the processor to consume

maximum power dissipation for sustained time periods. Intel recommends that

complete thermal solution designs target the Thermal Design Power (TDP), instead of

the maximum processor power consumption. The Adaptive Thermal Monitor feature is

intended to help protect the processor in the event that an application exceeds the TDP

recommendation for a sustained time period. For more details on this feature, refer to

Section 6.2. To ensure maximum flexibility for future requirements, systems should be

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Intel Xeon Processor 5500 Series Datasheet, Volume 1

Thermal Specifications

designed to the Flexible Motherboard (FMB) guidelines, even if a processor with lower

power dissipation is currently planned. The Adaptive Thermal Monitor feature

must be enabled for the processor to remain within its specifications.

Table 6-1.

Intel® Xeon® Processor W5580 Thermal Specifications

ThermalDesign

Power

Minimum

TCASE

(°C)

Maximum

TCASE

Core

Frequency

Notes

(W)

(°C)

Launch to FMB

130

5

See Figure 6-2; Table 6-4 1, 2, 3, 4, 5

Notes:

1.

These values are specified at V

for all processor frequencies. Systems must be designed to ensure

CC_MAX

the processor is not to be subjected to any static V and I combination wherein V exceeds V at

CC

CC_MAX

specified ICC. Please refer to the loadline specifications in Section 2.6.

Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the

maximum power that the processor can dissipate. TDP is measured at maximum T

These specifications are based on initial silicon characterization. These specifications may be further

updated as more characterization data becomes available.

Power specifications are defined at all VIDs found in Table 2-2. The Intel Xeon processor 5500 series may

be shipped under multiple VIDs for each frequency.

FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor

frequency requirements.

2.

3.

4.

5.

.

CASE

Figure 6-1. Intel® Xeon® Processor W5580 Thermal Profile

Notes:

1.

Intel Xeon Processor W5580 Thermal Profile is representative of a volumetrically unconstrained platform.

Please refer to Table 6-2 for discrete points that constitute the thermal profile.

Implementation of Intel Xeon Processor W5580 Thermal Profile should result in virtually no TCC activation.

Refer to the Intel® Xeon® Processor 5500/5600 Series Thermal / Mechanical Design Guide for system and

environmental implementation details.

2.

3.

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Thermal Specifications

Table 6-2.

Intel Xeon Processor W5580 Thermal Profile

Power (W)

T

(°C)

CASE_MAX

43.5

44.4

45.3

46.2

47.1

48.0

48.9

49.9

50.7

51.6

52.6

53.5

54.4

55.3

56.2

57.1

58.0

58.9

59.8

60.7

61.6

62.5

63.4

64.3

65.2

66.1

67.0

0

5

10

15

20

25

30

35.6

40

45

50

55

60

65

70

75

80

85

90

95

100

105

110

115

120

125

130

Table 6-3.

Intel Xeon Processor 5500 Series Advanced SKU Thermal Specifications

Thermal Design

Power

Minimum

TCASE

(°C)

Maximum

TCASE

Core

Frequency

Notes

(W)

(°C)

Launch to FMB

95

5

See Figure 6-2; Table 6-4

1, 2, 3, 4, 5

Notes:

1.

These values are specified at V

for all processor frequencies. Systems must be designed to ensure

CC_MAX

the processor is not to be subjected to any static V and I combination wherein V exceeds V at

CC

CC_MAX

specified ICC. Please refer to the loadline specifications in Section 2.6.

Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the

maximum power that the processor can dissipate. TDP is measured at maximum T

These specifications are based on initial silicon characterization. These specifications may be further

updated as more characterization data becomes available.

Power specifications are defined at all VIDs found in Table 2-2. The Intel Xeon processor 5500 series may

be shipped under multiple VIDs for each frequency.

FMB or Flexible Motherboard guidelines provide a design target for meeting all planned processor frequency

requirements.

2.

3.

4.

5.

.

CASE

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Intel Xeon Processor 5500 Series Datasheet, Volume 1

Thermal Specifications

Figure 6-2. Intel® Xeon® Processor 5500 Series Advanced SKU Thermal Profile

85

80

TCASE_M AX is a therm al solution design

point. In actuality, units will not significantly

exceed TCASE_M AX_A due to TCC activation.

75

70

65

60

55

50

45

40

Thermal Profile B

Y = 0.244*p + 57.8

0

5

10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95

Power [W]

Notes:

1.

Intel Xeon processor 5500 series Advanced SKU Thermal Profile A is representative of a volumetrically

unconstrained platform. Please refer to Table 6-4 for discrete points that constitute thermal profile A.

Implementation of Intel Xeon processor 5500 series Advanced SKU Thermal Profile A should result in

virtually no TCC activation. Furthermore, utilization of thermal solutions that do not meet Profile A will

result in increased probability of TCC activation and may incur measurable performance loss.

Intel Xeon processor 5500 series Advanced SKU Thermal Profile B is representative of a volumetrically

constrained platform. Please refer to Table 6-5 for discrete points that constitute thermal profile B.

Refer to the Intel® Xeon® Processor 5500/5600 Series Thermal / Mechanical Design Guide for system and

environmental implementation details.

2.

3.

4.

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Thermal Specifications

Table 6-4.

Intel Xeon Processor 5500 Series Advanced SKU Thermal Profile A

Power (W)

T

(°C)

CASE_MAX

57.8

58.7

59.6

60.5

61.4

62.3

63.2

64.2

65.0

65.9

66.9

67.8

68.7

69.6

70.5

71.4

72.3

73.2

74.1

75.0

0

5

10

15

20

25

30

35.6

40

45

50

55

60

65

70

75

80

85

90

95

Table 6-5.

Intel Xeon Processor 5500 Series Advanced SKU Thermal Profile B

Power (W)

T

(°C)

CASE_MAX

57.8

59.0

60.2

61.5

62.7

63.9

65.1

66.3

67.6

68.8

70.0

71.2

72.4

73.7

74.9

76.1

77.3

78.5

79.8

81.0

0

5

10

15

20

25

30

35

40

45

50

55

60

65

70

75

80

85

90

95

®

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Intel Xeon Processor 5500 Series Datasheet, Volume 1

Thermal Specifications

Table 6-6.

Intel Xeon Processor 5500 Series Standard/Basic SKUs Thermal Specifications

Thermal

Design Power

(W)

Minimum

TCASE

(°C)

Maximum

TCASE

Core

Frequency

Notes

(°C)

Launch to FMB

80

5

See Figure 6-3;

Table 6-7;

1, 2, 3, 4, 5

Notes:

1.

These values are specified at V

for all processor frequencies. Systems must be designed to ensure

CC_MAX

the processor is not to be subjected to any static V and I combination wherein V exceeds V at

specified I . Please refer to the loadline specifications in Section 2.6.

CC

CC_MAX

CC

2.

3.

4.

5.

Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the

maximum power that the processor can dissipate. TDP is measured at maximum T

These specifications are based on initial silicon characterization. These specifications may be further

updated as more characterization data becomes available.

Power specifications are defined at all VIDs found in Table 2-2. The Intel Xeon processor 5500 series may

be shipped under multiple VIDs for each frequency.

FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor

frequency requirements.

.

CASE

Figure 6-3. Intel Xeon Processor 5500 Series Standard/Basic SKUs Thermal Profile

Notes:

1.

Intel Xeon processor 5500 series Standard/Basic SKUs processor Thermal Profile is representative of a

volumetrically constrained platform. Please refer to Table 6-7 for discrete points that constitute the thermal

profile.

2.

3.

Implementation of Intel Xeon processor 5500 series Standard/Basic SKUs Thermal Profile should result in

virtually no TCC activation.

Refer to the Intel® Xeon® Processor 5500/5600 Series Thermal / Mechanical Design Guide for system and

environmental implementation details.

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Thermal Specifications

Table 6-7.

Intel Xeon Processor 5500 Series Standard/Basic SKUs Thermal Profile

Power (W)

T

(°C)

CASE_MAX

51.8

53.3

54.8

56.3

57.9

59.4

60.9

62.4

63.9

65.4

67.0

68.5

70.0

71.5

73.0

74.5

76.0

0

5

10

15

20

25

30

35

40

45

50

55

60

65

70

75

80

Table 6-8. Intel Xeon Processor 5500 Series Low Power SKU Thermal Specifications

Core

Frequency

Thermal Design Power

(W)

Minimum TCASE

(°C)

Maximum TCASE

(°C)

Notes

Launch to FMB

60

5

See Figure 6-4;

Table 6-9

1, 2, 3, 4, 5

Notes:

1.

These values are specified at V

for all processor frequencies. Systems must be designed to ensure

CC_MAX

the processor is not to be subjected to any static V and I combination wherein V exceeds V at

specified I . Please refer to the loadline specifications in Section 2.6.

CC

CC_MAX

CC

2.

3.

4.

5.

Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the

maximum power that the processor can dissipate. TDP is measured at maximum T

These specifications are based on initial silicon characterization. These specifications may be further

updated as more characterization data becomes available.

Power specifications are defined at all VIDs found in Table 2-2. The Intel Xeon processor 5500 series Low

Power SKU may be shipped under multiple VIDs for each frequency.

FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor

frequency requirements.

.

CASE

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Figure 6-4. Intel Xeon Processor 5500 Series Low Power SKU Thermal Profile

Notes:

1.

Intel Xeon processor 5500 series Low Power SKU Thermal Profile is representative of a volumetrically

constrained platform. Please refer to Table 6-9 for discrete points that constitute the thermal profile.

Implementation of Intel Xeon processor 5500 series Low Power SKU Thermal Profile should result in

virtually no TCC activation. Furthermore, utilization of thermal solutions that do not meet Intel Xeon

processor 5500 series Low Power SKU Thermal Profile will result in increased probability of TCC activation

and may incur measurable performance loss.

2.

3.

Refer to the Intel® Xeon® Processor 5500 Series Thermal / Mechanical Design Guide for system and

environmental implementation details.

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Thermal Specifications

Table 6-9.

Intel Xeon Processor 5500 Series Low Power SKU Thermal Profile

Power (W)

T

(°C)

CASE_MAX

51.9

53.4

54.9

56.4

57.9

59.5

61.0

62.5

64.0

65.5

67.0

68.5

70.0

0

5

10

15

20

25

30

35

40

45

50

55

60

Notes:

1.

These values are specified at V

for all processor frequencies. Systems must be designed to ensure

CC_MAX

the processor is not to be subjected to any static V and I combination wherein V exceeds V at

specified I . Please refer to the loadline specifications in Section 2.6.

CC

CC_MAX

CC

2.

3.

4.

5.

Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the

maximum power that the processor can dissipate. TDP is measured at maximum T

These specifications are based on initial silicon characterization. These specifications may be further

updated as more characterization data becomes available.

Power specifications are defined at all VIDs found in Table 2-2. The Intel Xeon processor 5500 series may

be shipped under multiple VIDs for each frequency.

FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor

frequency requirements.

.

CASE

Table 6-10. Intel Xeon Processor L5518 Thermal Specifications

Core

Frequency

Thermal Design Power

(W)

Minimum TCASE

(°C)

Maximum TCASE

(°C)

Notes

Launch to FMB

60

5

See Figure 6-5;

Table 6-11

1, 2, 3, 4, 5

Notes:

1.

These values are specified at V

for all processor frequencies. Systems must be designed to ensure

CC_MAX

the processor is not to be subjected to any static V and I combination wherein V exceeds V at

specified I . Please refer to the loadline specifications in Section 2.6.

CC

CC_MAX

CC

2.

3.

4.

5.

Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the

maximum power that the processor can dissipate. TDP is measured at maximum T

These specifications are based on initial silicon characterization. These specifications may be further

updated as more characterization data becomes available.

Power specifications are defined at all VIDs found in Table 2-2. The Intel Xeon Processor L5518 may be

shipped under multiple VIDs for each frequency.

FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor

frequency requirements

.

CASE

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Figure 6-5. Intel Xeon Processor L5518 Thermal Profile

Notes:

1.

Intel Xeon Processor L5518 Thermal Profile is representative of a volumetrically constrained platform.

Please refer to Table 6-11 for discrete points that constitute the thermal profile.

Implementation of Intel Xeon Processor L5518 nominal and short-term thermal profiles should result in

virtually no TCC activation. Furthermore, utilization of thermal solutions that do not meet this Thermal

Profile will result in increased probability of TCC activation and may incur measurable performance loss.

The Nominal Thermal Profile must be used for all normal operating conditions, or for products that do not

require NEBS Level 3 compliance.

The Short-Term Thermal Profile may only be used for short-term excursions to higher ambient operating

temperatures, not to exceed 96 hours per instance, 360 hours per year, and a maximum of 15 instances

per year, as compliant with NEBS Level 3. Operation at the Short-Term Thermal Profile for durations

exceeding 360 hours per year violate the processor thermal specifications and may result in permanent

damage to the processor.

2.

3.

4.

5.

Refer to the Intel® Xeon® Processor 5500/5600 Series Thermal / Mechanical Design Guide for system and

environmental implementation details.

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Thermal Specifications

Table 6-11. Intel Xeon Processor L5518 Thermal Profile

Power (W)

Nominal T

(°C)

Short-term T

(°C)

CASE_MAX

0

51.9

53.4

54.9

56.4

57.9

59.5

61.0

62.5

64.0

65.5

67.0

68.5

70.0

66.9

5

68.4

69.9

71.4

72.9

74.5

76.0

77.5

79.0

80.5

82.0

83.5

85.0

10

15

20

25

30

35

40

45

50

55

60

Notes:

1.

These values are specified at V

for all processor frequencies. Systems must be designed to ensure

CC_MAX

the processor is not to be subjected to any static V and I combination wherein V exceeds V at

specified I . Please refer to the loadline specifications in Section 2.6.

CC

CC_MAX

CC

2.

3.

4.

5.

Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the

maximum power that the processor can dissipate. TDP is measured at maximum T

These specifications are based on initial silicon characterization. These specifications may be further

updated as more characterization data becomes available.

Power specifications are defined at all VIDs found in Table 2-2. The Intel Xeon Processor L5518 may be

shipped under multiple VIDs for each frequency.

FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor

frequency requirements.

.

CASE

Table 6-12. Intel Xeon Processor L5508 Thermal Specifications

Core

Frequency

Thermal Design Power

(W)

Minimum TCASE

(°C)

Maximum TCASE

(°C)

Notes

Launch to FMB

38

5

See Figure 6-6;

Table 6-13

1, 2, 3, 4, 5, 6

Notes:

1.

These values are specified at V

for all processor frequencies. Systems must be designed to ensure

CC_MAX

the processor is not to be subjected to any static V and I combination wherein V exceeds V at

specified I . Please refer to the loadline specifications in Section 2.6.

CC

CC_MAX

CC

2.

3.

4.

5.

Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the

maximum power that the processor can dissipate. TDP is measured at maximum T

These specifications are based on initial silicon characterization. These specifications may be further

updated as more characterization data becomes available.

Power specifications are defined at all VIDs found in Table 2-2. The Intel Xeon Processor L5508 may be

shipped under multiple VIDs for each frequency.

FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor

frequency requirements.

.

CASE

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Figure 6-6. Intel Xeon Processor L5508 Thermal Profile

Notes:

1.

Intel Xeon Processor L5508 Thermal Profile is representative of a volumetrically constrained platform.

Please refer to Table 6-13 for discrete points that constitute the thermal profile.

Implementation of Intel Xeon Processor L5508 nominal and short-term thermal profiles should result in

virtually no TCC activation. Furthermore, utilization of thermal solutions that do not meet this Thermal

Profile will result in increased probability of TCC activation and may incur measurable performance loss.

The Nominal Thermal Profile must be used for all normal operating conditions, or for products that do not

require NEBS Level 3 compliance.

The Short-Term Thermal Profile may only be used for short-term excursions to higher ambient operating

temperatures, not to exceed 96 hours per instance, 360 hours per year, and a maximum of 15 instances

per year, as compliant with NEBS Level 3. Operation at the Short-Term Thermal Profile for durations

exceeding 360 hours per year violate the processor thermal specifications and may result in permanent

damage to the processor.

2.

3.

4.

5.

Refer to the Intel® Xeon® Processor 5500 Series Thermal / Mechanical Design Guide for system and

environmental implementation details.

Table 6-13. Intel Xeon Processor L5508 Thermal Profile

Power (W)

Nominal T

(°C)

Short-Term T

(°C)

CASE_MAX

0

50.0

52.7

55.3

58.0

60.6

63.3

66.0

68.6

70.2

65.0

5

67.7

70.3

73.0

75.6

78.3

81.0

83.6

85.2

10

15

20

25

30

35

38

Notes:

1. These values are specified at V

for all processor frequencies. Systems must be designed to ensure

CC_MAX

the processor is not to be subjected to any static V and I combination wherein V exceeds V at

CC

CC_MAX

specified I . Please refer to the loadline specifications in Section 2.6.

CC

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2.

3.

4.

5.

Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the

maximum power that the processor can dissipate. TDP is measured at maximum T

.

CASE

These specifications are based on initial silicon characterization. These specifications may be further

updated as more characterization data becomes available.

Power specifications are defined at all VIDs found in Table 2-2. The Intel Xeon Processor L5508 may be

shipped under multiple VIDs for each frequency.

FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor

frequency requirements.

6.1.2

Thermal Metrology

The minimum and maximum case temperatures (T_CASE) are specified in Table 6-6,

through Table 6-13 and are measured at the geometric top center of the processor

integrated heat spreader (IHS). Figure 6-7 illustrates the location where T_CASE

temperature measurements should be made. For detailed guidelines on temperature

measurement methodology, refer to the Intel® Xeon® Processor 5500/5600 Series

Thermal / Mechanical Design Guide.

Figure 6-7. Case Temperature (T_CASE) Measurement Location

Notes:

1.

2.

3.

4.

5.

6.

7.

Figure is not to scale and is for reference only.

B1: Max = 45.07 mm, Min = 44.93 mm.

B2: Max = 42.57 mm, Min = 42.43 mm.

C1: Max = 39.1 mm, Min = 38.9 mm.

C2: Max = 36.6 mm, Min = 36.4 mm.

C3: Max = 2.3 mm, Min = 2.2 mm

C4: Max = 2.3 mm, Min = 2.2 mm.

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6.2

Processor Thermal Features

6.2.1

Processor Temperature

A new feature in the Intel Xeon processor 5500 series is a software readable field in the

IA32_TEMPERATURE_TARGET register that contains the minimum temperature at

which the TCC will be activated and PROCHOT# will be asserted. The TCC activation

temperature is calibrated on a part-by-part basis and normal factory variation may

result in the actual TCC activation temperature being higher than the value listed in the

register. TCC activation temperatures may change based on processor stepping,

frequency or manufacturing efficiencies.

Note:

There is no specified correlation between DTS temperatures and processor case

temperatures; therefore it is not possible to use this feature to ensure the processor

case temperature meets the Thermal Profile specifications.

6.2.2

Adaptive Thermal Monitor

The Adaptive Thermal Monitor feature provides an enhanced method for controlling the

processor temperature when the processor silicon reaches its maximum operating

temperature. Adaptive Thermal Monitor uses Thermal Control Circuit (TCC) activation

to reduce processor power via a combination of methods. The first method

(Frequency/VID control) involves the processor adjusting its operating frequency (via

the core ratio multiplier) and input voltage (via the VID signals). This combination of

reduced frequency and VID results in a reduction to the processor power consumption.

The second method (clock modulation) reduces power consumption by modulating

(starting and stopping) the internal processor core clocks. The processor intelligently

selects the appropriate TCC method to use on a dynamic basis. BIOS is not required to

select a specific method (as with previous-generation processors supporting TM1 or

TM2).

The Adaptive Thermal Monitor feature must be enabled for the processor to be

operating within specifications. The temperature at which Adaptive Thermal

Monitor activates the Thermal Control Circuit is not user configurable and is not

software visible. Snooping and interrupt processing are performed in the normal

manner while the TCC is active.

With a properly designed and characterized thermal solution, it is anticipated that the

TCC would only be activated for very short periods of time when running the most

power intensive applications. The processor performance impact due to these brief

periods of TCC activation is expected to be so minor that it would be immeasurable. An

under-designed thermal solution that is not able to prevent excessive activation of the

TCC in the anticipated ambient environment may cause a noticeable performance loss,

and in some cases may result in a T_Cthat exceeds the specified maximum temperature

which may affect the long-term reliability of the processor. In addition, a thermal

solution that is significantly under-designed may not be capable of cooling the

processor even when the TCC is active continuously. Refer to the appropriate

Thermal/Mechanical Design Guide for information on designing a compliant thermal

solution.

The duty cycle for the TCC, when activated by the Thermal Monitor, is factory

configured and cannot be modified. The Thermal Monitor does not require any

additional hardware, software drivers, or interrupt handling routines.

The following sections provide more details on the different TCC mechanisms used by

Intel Xeon processor 5500 series.

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6.2.2.1

Frequency/VID Control

The processor uses Frequency/VID control whereby TCC activation causes the

processor to adjust its operating frequency (via the core ratio multiplier) and input

voltage (via the VID signals). This combination of reduced frequency and VID results in

a reduction to the processor power consumption.

This method includes multiple operating points, each consisting of a specific operating

frequency and voltage. The first operating point represents the normal operating

condition for the processor. The remaining points consist of both lower operating

frequencies and voltages. When the TCC is activated, the processor automatically

transitions to the new operating frequency. This transition occurs very rapidly (on the

order of 2 µs).

Once the new operating frequency is engaged, the processor will transition to the new

core operating voltage by issuing a new VID code to the voltage regulator. The voltage

regulator must support dynamic VID steps to support this method. During the voltage

change, it will be necessary to transition through multiple VID codes to reach the target

operating voltage. Each step will be one VID table entry (see Table 2-2). The processor

continues to execute instructions during the voltage transition. Operation at the lower

voltages reduces the power consumption of the processor.

A small amount of hysteresis has been included to prevent rapid active/inactive

transitions of the TCC when the processor temperature is near its maximum operating

temperature. Once the temperature has dropped below the maximum operating

temperature, and the hysteresis timer has expired, the operating frequency and

voltage transition back to the normal system operating point via the intermediate

VID/frequency points. Transition of the VID code will occur first, to insure proper

operation once the processor reaches its normal operating frequency. Refer to

Figure 6-8 for an illustration of this ordering.

Figure 6-8. Frequency and Voltage Ordering

Temperature

Frequency

f_MAX

f₁

f₂

VIDf_MAX

VIDf₁

VIDf₂

VID

PROCHOT#

Time

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6.2.2.2

Clock Modulation

Clock modulation is performed by alternately turning the clocks off and on at a duty

cycle specific to the processor (factory configured to 37.5% on and 62.5% off). The

period of the duty cycle is configured to 32 microseconds when the TCC is active. Cycle

times are independent of processor frequency. A small amount of hysteresis has been

included to prevent rapid active/inactive transitions of the TCC when the processor

temperature is near its maximum operating temperature. Once the temperature has

dropped below the maximum operating temperature, and the hysteresis timer has

expired, the TCC goes inactive and clock modulation ceases. Clock modulation is

automatically engaged as part of the TCC activation when the Frequency/VID targets

are at their minimum settings. It may also be initiated by software at a configurable

duty cycle.

6.2.3

On-Demand Mode

The processor provides an auxiliary mechanism that allows system software to force

the processor to reduce its power consumption. This mechanism is referred to as “On-

Demand” mode and is distinct from the Adaptive Thermal Monitor feature. On-Demand

mode is intended as a means to reduce system level power consumption. Systems

utilizing the Intel Xeon processor 5500 series must not rely on software usage of this

mechanism to limit the processor temperature. If bit 4 of the

IA32_CLOCK_MODULATION MSR is set to a ‘1’, the processor will immediately reduce

its power consumption via modulation (starting and stopping) of the internal core clock,

independent of the processor temperature. When using On-Demand mode, the duty

cycle of the clock modulation is programmable via bits 3:1 of the same

IA32_CLOCK_MODULATION MSR. In On-Demand mode, the duty cycle can be

programmed from 12.5% on/ 87.5% off to 87.5% on/12.5% off in 12.5% increments.

On-Demand mode may be used in conjunction with the Adaptive Thermal Monitor;

however, if the system tries to enable On-Demand mode at the same time the TCC is

engaged, the factory configured duty cycle of the TCC will override the duty cycle

selected by the On-Demand mode.

6.2.4

PROCHOT# Signal

An external signal, PROCHOT# (processor hot), is asserted when the processor core

temperature has reached its maximum operating temperature. If Adaptive Thermal

Monitor is enabled (note it must be enabled for the processor to be operating within

specification), the TCC will be active when PROCHOT# is asserted. The processor can

be configured to generate an interrupt upon the assertion or de-assertion of

PROCHOT#.

The PROCHOT# signal is bi-directional in that it can either signal when the processor

(any core) has reached its maximum operating temperature or be driven from an

external source to activate the TCC. The ability to activate the TCC via PROCHOT# can

provide a means for thermal protection of system components.

As an output, PROCHOT# will go active when the processor temperature monitoring

sensor detects that one or more cores has reached its maximum safe operating

temperature. This indicates that the processor Thermal Control Circuit (TCC) has been

activated, if enabled. As an input, assertion of PROCHOT# by the system will activate

the TCC, if enabled, for all cores. TCC activation due to PROCHOT# assertion by the

system will result in the processor immediately transitioning to the minimum frequency

and corresponding voltage (using Freq/VID control). Clock modulation is not activated

in this case. The TCC will remain active until the system de-asserts PROCHOT#.

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PROCHOT# can allow VR thermal designs to target maximum sustained current instead

of maximum current. Systems should still provide proper cooling for the VR, and rely

on PROCHOT# only as a backup in case of system cooling failure. The system thermal

design should allow the power delivery circuitry to operate within its temperature

specification even while the processor is operating at its Thermal Design Power.

With a properly designed and characterized thermal solution, it is anticipated that

PROCHOT# will only be asserted for very short periods of time when running the most

power intensive applications. An under-designed thermal solution that is not able to

prevent excessive assertion of PROCHOT# in the anticipated ambient environment may

cause a noticeable performance loss. Refer to the appropriate platform design guide

and for details on implementing the bi-directional PROCHOT# feature.

6.2.5

THERMTRIP# Signal

Regardless of whether Adaptive Thermal Monitor is enabled, in the event of a

catastrophic cooling failure, the processor will automatically shut down when the silicon

has reached an elevated temperature (refer to the THERMTRIP# definition in

Table 5-1). THERMTRIP# activation is independent of processor activity and does not

generate any Intel® QuickPath Interconnect transactions. The temperature at which

THERMTRIP# asserts is not user configurable and is not software visible.

6.3

Platform Environment Control Interface (PECI)

The Platform Environment Control Interface (PECI) uses a single wire for self-clocking

and data transfer. The bus requires no additional control lines. The physical layer is a

self-clocked one-wire bus that begins each bit with a driven, rising edge from an idle

level near zero volts. The duration of the signal driven high depends on whether the bit

value is a logic ‘0’ or logic ‘1’. PECI also includes variable data transfer rate established

with every message. In this way, it is highly flexible even though underlying logic is

simple.

The interface design was optimized for interfacing to Intel processor and chipset

components in both single processor and multiple processor environments. The single

wire interface provides low board routing overhead for the multiple load connections in

the congested routing area near the processor and chipset components. Bus speed,

error checking, and low protocol overhead provides adequate link bandwidth and

reliability to transfer critical device operating conditions and configuration information.

The PECI bus offers:

• A wide speed range from 2 Kbps to 2 Mbps

• CRC check byte used to efficiently and atomically confirm accurate data delivery

• Synchronization at the beginning of every message minimizes device timing

accuracy requirements

Note that the PECI commands described in this document apply to the Intel

Xeon processor 5500 series only. Refer to Table 6-14 for the list of PECI

commands supported by the Intel Xeon processor 5500 series PECI client.

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Table 6-14. Summary of Processor-specific PECI Commands

Supported on Intel Xeon Processor

Command

5500 Series CPU

Ping()

Yes

GetDIB()

GetTemp()

PCIConfigRd()

PCIConfigWr()

MbxSend() ¹

MbxGet() ¹

Note:

1.

Refer to Table 6-19 for a summary of mailbox commands supported by the Intel Xeon processor 5500

series CPU.

6.3.1

PECI Client Capabilities

The Intel Xeon processor 5500 series PECI client is designed to support the following

sideband functions:

• Processor and DRAM thermal management

• Platform manageability functions including thermal, power and electrical error

monitoring

• Processor interface tuning and diagnostics capabilities (Intel^®Interconnect BIST

[Intel^®IBIST]).

6.3.1.1

Thermal Management

Processor fan speed control is managed by comparing PECI thermal readings against

the processor-specific fan speed control reference point, or T_CONTROL. Both T_CONTROL

and PECI thermal readings are accessible via the processor PECI client. These variables

are referenced to a common temperature, the TCC activation point, and are both

defined as negative offsets from that reference. Algorithms for fan speed management

using PECI thermal readings and the T_CONTROLreference are documented in

Section 6.3.2.6.

PECI-based access to DRAM thermal readings and throttling control coefficients provide

a means for Board Management Controllers (BMCs) or other platform management

devices to feed hints into on-die memory controller throttling algorithms. These control

coefficients are accessible using PCI configuration space writes via PECI. The PECI-

based configuration write functionality is defined in Section 6.3.2.5, and the DRAM

throttling coefficient control functions are documented in the Intel® Xeon® Processor

5500 Series Datasheet, Volume 2.

6.3.1.2

Platform Manageability

PECI allows full read access to error and status monitoring registers within the

processor’s PCI configuration space. It also provides insight into thermal monitoring

functions such as TCC activation timers and thermal error logs.

The exact list of RAS-related registers in the PCI configuration space can be found in

the Intel® Xeon® Processor 5500 Series Datasheet, Volume 2.

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6.3.1.3

Processor Interface Tuning and Diagnostics

Intel Xeon processor 5500 series Intel IBIST allows for in-field diagnostic capabilities in

Intel QuickPath Interconnect and memory controller interfaces. PECI provides a port to

execute these diagnostics via its PCI Configuration read and write capabilities.

6.3.2

Client Command Suite

6.3.2.1

Ping()

Ping() is a required message for all PECI devices. This message is used to enumerate

devices or determine if a device has been removed, been powered-off, etc. A Ping()

sent to a device address always returns a non-zero Write FCS if the device at the

targeted address is able to respond.

6.3.2.1.1

Command Format

The Ping() format is as follows:

Write Length: 0

Read Length: 0

Figure 6-9. Ping()

Byte #

0

1

2

3

Write Length

0x00

Read Length

0x00

Client Address

FCS

Byte

Definition

An example Ping() command to PECI device address 0x30 is shown below.

Figure 6-10. Ping() Example

Byte #

0

1

2

3

Byte

0x30

0x00

0xe1

Definition

6.3.2.2

GetDIB()

The processor PECI client implementation of GetDIB() includes an 8-byte response and

provides information regarding client revision number and the number of supported

domains. All processor PECI clients support the GetDIB() command.

6.3.2.2.1

Command Format

The GetDIB() format is as follows:

Write Length: 1

Read Length: 8

Command: 0xf7

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Figure 6-11. GetDIB()

Byte #

0

1

2

3

4

Write Length

0x01

Read Length

0x08

Cmd Code

0xf7

Client Address

FCS

Byte

Definition

5

6

7

8

9

Revision

Number

Device Info

Reserved

10

11

12

13

Reserved

FCS

6.3.2.2.2

Device Info

The Device Info byte gives details regarding the PECI client configuration. At a

minimum, all clients supporting GetDIB will return the number of domains inside the

package via this field. With any client, at least one domain (Domain 0) must exist.

Therefore, the Number of Domains reported is defined as the number of domains in

addition to Domain 0. For example, if the number 0b1 is returned, that would indicate

that the PECI client supports two domains.

Figure 6-12. Device Info Field Definition

7

6 5 4 3 2 1 0

Reserved

# of Domains

Reserved

6.3.2.2.3

Revision Number

All clients that support the GetDIB command also support Revision Number reporting.

The revision number may be used by a host or originator to manage different command

suites or response codes from the client. Revision Number is always reported in the

second byte of the GetDIB() response. The Revision Number always maps to the

revision number of this document.

Figure 6-13. Revision Number Definition

7

4

0

3

Major Revision#

Minor Revision#

For a client that is designed to meet the specification, the Revision Number it returns

will be ‘0010 0000b’.

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6.3.2.3

GetTemp()

The GetTemp() command is used to retrieve the temperature from a target PECI

address. The temperature is used by the external thermal management system to

regulate the temperature on the die. The data is returned as a negative value

representing the number of degrees centigrade below the Thermal Control Circuit

Activation temperature of the PECI device. Note that a value of zero represents the

temperature at which the Thermal Control Circuit activates. The actual value that the

thermal management system uses as a control set point (Tcontrol) is also defined as a

negative number below the Thermal Control Circuit Activation temperature. TCONTROL

may be extracted from the processor by issuing a PECI Mailbox MbxGet() (see

Section 6.3.2.8), or using a RDMSR instruction.

Please refer to Section 6.3.6 for details regarding temperature data formatting.

6.3.2.3.1

Command Format

The GetTemp() format is as follows:

Write Length: 1

Read Length: 2

Command: 0x01

Multi-Domain Support: Yes (see Table 6-26)

Description: Returns the current temperature for addressed processor PECI client.

Figure 6-14. GetTemp()

Byte #

0

1

2

3

Write Length

0x01

Read Length

0x02

Cmd Code

0x01

Client Address

Byte

Definition

4

5

6

7

FCS

Temp[7:0]

Temp[15:8]

FCS

Example bus transaction for a thermal sensor device located at address 0x30 returning

a value of negative 10°C:

Figure 6-15. GetTemp() Example

Byte #

0

1

2

3

Byte

0x30

0x01

0x02

0x01

Definition

4

5

6

7

0xef

0x80

0xfd

0x4b

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6.3.2.3.2

Supported Responses

The typical client response is a passing FCS and good thermal data. Under some

conditions, the client’s response will indicate a failure.

Table 6-15. GetTemp() Response Definition

Response

Meaning

General Sensor Error (GSE)

0x0000

Thermal scan did not complete in time. Retry is appropriate.

Processor is running at its maximum temperature or is currently being reset.

All other data

Valid temperature reading, reported as a negative offset from the TCC

activation temperature.

6.3.2.4

PCIConfigRd()

The PCIConfigRd() command gives sideband read access to the entire PCI configuration

space maintained in the processor. This capability does not include support for route-

through to downstream devices or sibling processors. The exact listing of supported

devices, functions, and registers can be found in the Intel® Xeon® Processor 5500

Series Datasheet, Volume 2. PECI originators may conduct a device/function/register

enumeration sweep of this space by issuing reads in the same manner that BIOS

would. A response of all 1’s indicates that the device/function/register is

unimplemented.

PCI configuration addresses are constructed as shown in the following diagram. Under

normal in-band procedures, the Bus number (including any reserved bits) would be

used to direct a read or write to the proper device. Since there is a one-to-one mapping

between any given client address and the bus number, any request made with a bad

Bus number is ignored and the client will respond with a ‘pass’ completion code but all

0’s in the data. The only legal bus number is 0x00. The client will return all 1’s in the

data response and ‘pass’ for the completion code for all of the following conditions:

• Unimplemented Device

• Unimplemented Function

• Unimplemented Register

Figure 6-16. PCI Configuration Address

31

28 27

20 19

15 14

12 11

0

Reserved

Bus

Device

Function

Register

PCI configuration reads may be issued in byte, word, or dword granularities.

6.3.2.4.1

Command Format

The PCIConfigRd() format is as follows:

Write Length: 5

Read Length: 2 (byte data), 3 (word data), 5 (dword data)

Command: 0xc1

Multi-Domain Support: Yes (see Table 6-26)

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Description: Returns the data maintained in the PCI configuration space at the PCI

configuration address sent. The Read Length dictates the desired data return size. This

command supports byte, word, and dword responses as well as a completion code. All

command responses are prepended with a completion code that includes additional

pass/fail status information. Refer to Section 6.3.4.2 for details regarding completion

codes.

Figure 6-17. PCIConfigRd()

Byte #

0

1

2

3

Write Length

0x05

Read Length

{0x02,0x03,0x05}

Cmd Code

0xc1

Client Address

Byte

Definition

4

5

6

7

8

LSB

PCI Configuration Address

MSB

FCS

9

10

8+RL

9+RL

FCS

Completion

Code

Data 0

...

Data N

Note that the 4-byte PCI configuration address defined above is sent in standard PECI

ordering with LSB first and MSB last.

6.3.2.4.2

Supported Responses

The typical client response is a passing FCS, a passing Completion Code (CC) and valid

Data. Under some conditions, the client’s response will indicate a failure.

Table 6-16. PCIConfigRd() Response Definition

Response

Meaning

Abort FCS

CC: 0x40

CC: 0x80

Illegal command formatting (mismatched RL/WL/Command Code)

Command passed, data is valid

Error causing a response timeout. Either due to a rare, internal timing condition or a

processor RESET or processor S1 state. Retry is appropriate outside of the RESET or

S1 states.

6.3.2.5

PCIConfigWr()

The PCIConfigWr() command gives sideband write access to the PCI configuration

space maintained in the processor. The exact listing of supported devices, functions is

defined below in Table 6-17. PECI originators may conduct a device/function/register

enumeration sweep of this space by issuing reads in the same manner that BIOS

would.

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Table 6-17. PCIConfigWr() Device/Function Support

Writable

Description

Device

Function

2

1

5

4

3

Intel QuickPath Interconnect Link 0 Intel IBIST

Intel QuickPath Interconnect Link 1 Intel IBIST

2

1

3

Memory Controller Intel IBIST

4

Memory Controller Channel 0 Thermal Control / Status

Memory Controller Channel 1 Thermal Control / Status

Memory Controller Channel 2 Thermal Control / Status

5

6

Notes:

1. Currently not available for access through the PECI PCIConfigWr() command.

PCI configuration addresses are constructed as shown in Figure 6-16, and this

command is subject to the same address configuration rules as defined in

Section 6.3.2.4. PCI configuration reads may be issued in byte, word, or dword

granularities.

Because a PCIConfigWr() results in an update to potentially critical registers inside the

processor, it includes an Assured Write FCS (AW FCS) byte as part of the write data

payload. In the event that the AW FCS mismatches with the client-calculated FCS, the

client will abort the write and will always respond with a bad Write FCS.

6.3.2.5.1

Command Format

The PCIConfigWr() format is as follows:

Write Length: 7 (byte), 8 (word), 10 (dword)

Read Length: 1

Command: 0xc5

Multi-Domain Support: Yes (see Table 6-26)

Description: Writes the data sent to the requested register address. Write Length

dictates the desired write granularity. The command always returns a completion code

indicating the pass/fail status information. Write commands issued to illegal Bus

Numbers, or unimplemented Device / Function / Register addresses are ignored but

return a passing completion code. Refer to Section 6.3.4.2 for details regarding

completion codes.

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Figure 6-18. PCIConfigWr()

Byte #

0

1

2

3

Write Length

{0x07,0x08,0x10}

Read Length

0x01

Cmd Code

0xc5

Client Address

Byte

Definition

4

5

6

7

LSB

PCI Configuration Address

Data (1, 2 or 4 bytes)

MSB

8

WL-1

MSB

LSB

WL

WL+1

FCS

WL+2

WL+3

FCS

Completion

Code

AW FCS

Note that the 4-byte PCI configuration address and data defined above are sent in

standard PECI ordering with LSB first and MSB last.

6.3.2.5.2

Supported Responses

The typical client response is a passing FCS, a passing Completion Code and valid Data.

Under some conditions, the client’s response will indicate a failure.

Table 6-18. PCIConfigWr() Response Definition

Response

Meaning

Bad FCS

Electrical error or AW FCS failure

Abort FCS

CC: 0x40

CC: 0x80

Illegal command formatting (mismatched RL/WL/Command Code)

Command passed, data is valid

Error causing a response timeout. Either due to a rare, internal timing condition or a

processor RESET condition or processor S1 state. Retry is appropriate outside of the RESET

or S1 states.

6.3.2.6

Mailbox

The PECI mailbox (“Mbx”) is a generic interface to access a wide variety of internal

processor states. A Mailbox request consists of sending a 1-byte request type and

4-byte data to the processor, followed by a 4-byte read of the response data. The

following sections describe the Mailbox capabilities as well as the usage semantics for

the MbxSend and MbxGet commands which are used to send and receive data.

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6.3.2.6.1

Capabilities

Table 6-19. Mailbox Command Summary

Request

MbxSend

Data

(dword)

MbxGet

Data

(dword)

Command

Name

Type

Code

(byte)

Description

Ping

0x00

0x01

0x00

Verify the operability / existence of the Mailbox.

Thermal

Status

Read/Clear

Log bit clear Thermal

mask

Read the thermal status register and optionally clear any log bits.

The thermal status has status and log bits indicating the state of

processor TCC activation, external PROCHOT# assertion, and

Critical Temperature threshold crossings.

Status

Register

Counter

Snapshot

0x03

0x00

Snapshots all PECI-based counters

Counter Clear

Counter Read

0x04

0x05

0x00

Concurrently clear and restart all counters.

Counter

Number

Counter Data

Returns the counter number requested.

0: Total reference time

1: Total TCC Activation time counter

Icc-TDC Read

0x06

0x07

0x00

Icc-TDC

Returns the specified Icc-TDC of this part, in Amps.

Reads the thermal averaging constant.

Thermal Config

Data Read

Thermal

config data

Thermal Config

Data Write

0x08

0x09

0x0A

Thermal

0x00

Writes the thermal averaging constant.

Config Data

Tcontrol Read

0x00

Tcontrol

Reads the fan speed control reference temperature, Tcontrol, in

PECI temperature format.

Machine Check

Read

Bank

Number /

Index

Register Data

Read CPU Machine Check Banks.

T-state

Throttling

Control Read

0xB

0xC

0x00

ACPI T-state

Control Word

Reads the PECI ACPI T-state throttling control word.

Writes the PECI ACPI T-state throttling control word.

T-state

Throttling

Control Write

ACPI T-

state

Control

Word

0x00

Any MbxSend request with a request type not defined in Table 6-19 will result in a

failing completion code.

More detailed command definitions follow.

6.3.2.6.2

6.3.2.6.3

Ping

The Mailbox interface may be checked by issuing a Mailbox ‘Ping’ command. If the

command returns a passing completion code, it is functional. Under normal operating

conditions, the Mailbox Ping command should always pass.

Thermal Status Read / Clear

The Thermal Status Read provides information on package level thermal status. Data

includes:

• The status of TCC activation

• Bidirectional PROCHOT# assertion

• Critical Temperature

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These status bits are a subset of the bits defined in the IA32_THERM_STATUS MSR on

the processor, and more details on the meaning of these bits may be found in the

Intel 64 and IA-32 Architectures Software Developer’s Manual, Vol. 3B.

Both status and sticky log bits are managed in this status word. All sticky log bits are

set upon a rising edge of the associated status bit, and the log bits are cleared only by

Thermal Status reads or a processor reset. A read of the Thermal Status Word always

includes a log bit clear mask that allows the host to clear any or all log bits that it is

interested in tracking.

A bit set to 0b0 in the log bit clear mask will result in clearing the associated log bit. If

a mask bit is set to 0b0 and that bit is not a legal mask, a failing completion code will

be returned. A bit set to 0b1 is ignored and results in no change to any sticky log bits.

For example, to clear the TCC Activation Log bit and retain all other log bits, the

Thermal Status Read should send a mask of 0xFFFFFFFD.

Figure 6-19. Thermal Status Word

3

1

6 5 4 3 2 1 0

Reserved

Critical Temperature Log

Critical Temperature Status

Bidirectional PROCHOT# Log

Bidirectional PROCHOT#

Status

TCC Activation Log

TCC Activation Status

6.3.2.6.4

Counter Snapshot / Read / Clear

A reference time and ‘Thermally Constrained’ time are managed in the processor. These

two counters are managed via the Mailbox. These counters are valuable for detecting

thermal runaway conditions where the TCC activation duty cycle reaches excessive

levels.

The counters may be simultaneously snapshot, simultaneously cleared, or

independently read. The simultaneous snapshot capability is provided in order to

guarantee concurrent reads even with significant read latency over the PECI bus. Each

counter is 32-bits wide.

Table 6-20. Counter Definition

Counter

Number

Counter Name

Definition

Total Time

0x00

0x01

Counts the total time the processor has been executing with a

resolution of approximately 1ms. This counter wraps at 32 bits.

Thermally Constrained Time

Counts the total time the processor has been operating at a

lowered performance due to TCC activation. This timer includes

the time required to ramp back up to the original P-state target

after TCC activation expires. This timer does not include TCC

activation time as a result of an external assertion of

PROCHOT#.

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6.3.2.6.5

Icc-TDC Read

Icc-TDC is the Intel Xeon processor 5500 series TDC current draw specification. This

data may be used to confirm matching Icc profiles of processors in DP configurations. It

may also be used during the processor boot sequence to verify processor compatibility

with motherboard Icc delivery capabilities.

This command returns Icc-TDC in units of 1 Amp.

6.3.2.6.6

6.3.2.6.7

TCONTROL Read

TCONTROL is used for fan speed control management. The TCONTROL limit may be

read over PECI using this Mailbox function. Unlike the in-band MSR interface, this

TCONTROL value is already adjusted to be in the native PECI temperature format of a

2-byte, 2’s complement number.

Thermal Data Config Read / Write

The Thermal Data Configuration register allows the PECI host to control the window

over which thermal data is filtered. The default window is 256 ms. The host may

configure this window by writing a Thermal Filtering Constant as a power of two. For

example, sending a value of 9 results in a filtering window of 2⁹or 512 ms.

Figure 6-20. Thermal Data Configuration Register

3

1

4 3

0

Reserved

Thermal Filter Const

6.3.2.6.8

Machine Check Read

PECI offers read access to processor machine check banks 0, 1, 6 and 8.

Because machine check bank reads must be delivered through the Intel Xeon processor

5500 series Power Control Unit, it is possible that a fatal error in that unit will prevent

access to other machine check banks. Host controllers may read Power Control Unit

errors directly by issuing a PCIConfigRd() command of address 0x000000B0.

Figure 6-21. Machine Check Read MbxSend() Data Format

Byte #

Data

0

1

2

3

4

0x0A

Bank Index

Bank Number

Reserved

Request Type

Data[31:0]

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Table 6-21. Machine Check Bank Definitions

Bank Number

Bank Index

Meaning

0

1

6

8

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

MC0_CTL[31:0]

MC0_CTL[63:32]

MC0_STATUS[31:0]

MC0_STATUS[63:32]

MC0_ADDR[31:0]

MC0_ADDR[63:32]

MC0_MISC[31:0]

MC0_MISC[63:32]

MC1_CTL[31:0]

MC1_CTL[63:32]

MC1_STATUS[31:0]

MC1_STATUS[63:32]

MC1_ADDR[31:0]

MC1_ADDR[63:32]

MC1_MISC[31:0]

MC1_MISC[63:32]

MC6_CTL[31:0]

MC6_CTL[63:32]

MC6_STATUS[31:0]

MC6_STATUS[63:32]

MC6_ADDR[31:0]

MC6_ADDR[63:32]

MC6_MISC[31:0]

MC6_MISC[63:32]

MC8_CTL[31:0]

MC8_CTL[63:32]

MC8_STATUS[31:0]

MC8_STATUS[63:32]

MC8_ADDR[31:0]

MC8_ADDR[63:32]

MC8_MISC[31:0]

MC8_MISC[63:32]

6.3.2.6.9

T-state Throttling Control Read / Write

PECI offers the ability to enable and configure ACPI T-state (core clock modulation)

throttling. ACPI T-state throttling forces all CPU cores into duty cycle clock modulation

where the core toggles between C0 (clocks on) and C1 (clocks off) states at the

specified duty cycle. This throttling reduces CPU performance to the duty cycle

specified and, more importantly, results in processor power reduction.

The Intel Xeon processor 5500 series software initiated T-state throttling and automatic

T-state throttling as part of the internal Thermal Monitor response mechanism (upon

TCC activation). The PECI T-state throttling control register read/write capability is

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managed only in the PECI domain. In-band software may not manipulate or read the

PECI T-state control setting. In the event that multiple agents are requesting T-state

throttling simultaneously, the CPU always gives priority to the lowest power setting, or

the numerically lowest duty cycle.

On Intel Xeon processor 5500 series, the only supported duty cycle is 12.5% (12.5%

clocks on, 87.5% clocks off). It is expected that T-state throttling will be engaged only

under emergency thermal or power conditions. Future products may support more duty

cycles, as defined in the following table:

Table 6-22. ACPI T-state Duty Cycle Definition

Duty Cycle Code

0x0

Definition

Undefined

0x1

0x2

0x3

0x4

0x5

0x6

0x7

12.5% clocks on / 87.5% clocks off

25% clocks on / 75% clocks off

37.5% clocks on / 62.5% clocks off

50% clocks on / 50% clocks off

62.5% clocks on / 37.5% clocks off

75% clocks on / 25% clocks off

87.5% clocks on / 12.5% clocks off

The T-state control word is defined as follows:

Figure 6-22. ACPI T-state Throttling Control Read / Write Definition

\

Byte #

0

1

2

3

4

Request Type

Request Data

7

5 4 3

1 0

7

0

0xB / 0xC

Reserved

Data

Enable

Duty Cycle

6.3.2.7

MbxSend()

The MbxSend() command is utilized for sending requests to the generic Mailbox

interface. Those requests are in turn serviced by the processor with some nominal

latency and the result is deposited in the mailbox for reading. MbxGet() is used to

retrieve the response and details are documented in Section 6.3.2.8.

The details of processor mailbox capabilities are described in Section 6.3.2.6.1, and

many of the fundamental concepts of Mailbox ownership, release, and management are

discussed in Section 6.3.2.9.

6.3.2.7.1

Write Data

Regardless of the function of the mailbox command, a request type modifier and 4-byte

data payload must be sent. For Mailbox commands where the 4-byte data field is not

applicable (for example, the command is a read), the data written should be all zeroes.

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Figure 6-23. MbxSend() Command Data Format

0

1

2

3

4

Byte #

Byte

Definition

Request Type

Data[31:0]

Because a particular MbxSend() command may specify an update to potentially critical

registers inside the processor, it includes an Assured Write FCS (AW FCS) byte as part

of the write data payload. In the event that the AW FCS mismatches with the client-

calculated FCS, the client will abort the write and will always respond with a bad Write

FCS.

6.3.2.7.2

Command Format

The MbxSend() format is as follows:

Write Length: 7

Read Length: 1

Command: 0xd1

Multi-Domain Support: Yes (see Table 6-26)

Description: Deposits the Request Type and associated 4-byte data in the Mailbox

interface and returns a completion code byte with the details of the execution results.

Refer to Section 6.3.4.2 for completion code definitions.

Figure 6-24. MbxSend()

Byte #

0

1

2

3

Byte

Definition

Write Length

0x07

Read Length

0x01

Cmd Code

0xd1

Client Address

4

5

6

7

8

Request Type

LSB

Data[31:0]

MSB

9

10

11

12

Completion

Code

AW FCS

FCS

Note that the 4-byte data defined above is sent in standard PECI ordering with LSB first

and MSB last.

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Table 6-23. MbxSend() Response Definition

Response

Meaning

Bad FCS

CC: 0x4X

CC: 0x80

Electrical error

Semaphore is granted with a Transaction ID of ‘X’

Error causing a response timeout. Either due to a rare, internal timing condition or a

processor RESET condition or processor S1 state. Retry is appropriate outside of the

RESET or S1 states.

CC: 0x86

Mailbox interface is unavailable or busy

If the MbxSend() response returns a bad Read FCS, the completion code can't be

trusted and the semaphore may or may not be taken. In order to clean out the

interface, an MbxGet() must be issued and the response data should be discarded.

6.3.2.8

MbxGet()

The MbxGet() command is utilized for retrieving response data from the generic

Mailbox interface as well as for unlocking the acquired mailbox. Please refer to

Section 6.3.2.7 for details regarding the MbxSend() command. Many of the

fundamental concepts of Mailbox ownership, release, and management are discussed

in Section 6.3.2.9.

6.3.2.8.1

Write Data

The MbxGet() command is designed to retrieve response data from a previously

deposited request. In order to guarantee alignment between the temporally separated

request (MbxSend) and response (MbxGet) commands, the originally granted

Transaction ID (sent as part of the passing MbxSend() completion code) must be issued

as part of the MbxGet() request.

Any mailbox request made with an illegal or unlocked Transaction ID will get a failed

completion code response. If the Transaction ID matches an outstanding transaction ID

associated with a locked mailbox, the command will complete successfully and the

response data will be returned to the originator.

Unlike MbxSend(), no Assured Write protocol is necessary for this command because

this is a read-only function.

6.3.2.8.2

Command Format

The MbxGet() format is as follows:

Write Length: 2

Read Length: 5

Command: 0xd5

Multi-Domain Support: Yes (see Table 6-26)

Description: Retrieves response data from mailbox and unlocks / releases that

mailbox resource.

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Figure 6-25. MbxGet()

Byte #

0

1

2

3

Byte

Definition

Write Length

0x02

Read Length

0x05

Cmd Code

0xd5

Client Address

4

150

161

Completion

Code

Transaction ID

FCS

7

1850

1961

10

MSB

11

LSB

Response Data[31:0]

FCS

Note that the 4-byte data response defined above is sent in standard PECI ordering

with LSB first and MSB last.

Table 6-24. MbxGet() Response Definition

Response

Meaning

Aborted Write FCS Response data is not ready. Command retry is appropriate.

CC: 0x40

CC: 0x80

Command passed, data is valid

Error causing a response timeout. Either due to a rare, internal timing condition or a

processor RESET condition or processor S1 state. Retry is appropriate outside of the

RESET or S1 states.

CC: 0x81

CC: 0x82

CC: 0x83

CC: 0x84

CC: 0x85

CC: 0x86

CC: 0xFF

Thermal configuration data was malformed or exceeded limits.

Thermal status mask is illegal

Invalid counter select

Invalid Machine Check Bank or Index

Failure due to lack of Mailbox lock or invalid Transaction ID

Mailbox interface is unavailable or busy

Unknown/Invalid Mailbox Request

6.3.2.9

Mailbox Usage Definition

Acquiring the Mailbox

6.3.2.9.1

The MbxSend() command is used to acquire control of the PECI mailbox and issue

information regarding the specific request. The completion code response indicates

whether or not the originator has acquired a lock on the mailbox, and that completion

code always specifies the Transaction ID associated with that lock (see

Section 6.3.2.9.2).

Once a mailbox has been acquired by an originating agent, future requests to acquire

that mailbox will be denied with an ‘interface busy’ completion code response.

The lock on a mailbox is not achieved until the last bit of the MbxSend() Read FCS is

transferred (in other words, it is not committed until the command completes). If the

host aborts the command at any time prior to that bit transmission, the mailbox lock

will be lost and it will remain available for any other agent to take control.

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6.3.2.9.2

Transaction ID

For all MbxSend() commands that complete successfully, the passing completion code

(0x4X) includes a 4-bit Transaction ID (‘X’). That ID is the key to the mailbox and must

be sent when retrieving response data and releasing the lock by using the MbxGet()

command.

The Transaction ID is generated internally by the processor and has no relationship to

the originator of the request. On Intel Xeon processor 5500 series, only a single

outstanding Transaction ID is supported. Therefore, it is recommended that all devices

requesting actions or data from the Mailbox complete their requests and release their

semaphore in a timely manner.

In order to accommodate future designs, software or hardware utilizing the PECI

mailbox must be capable of supporting Transaction IDs between 0 and 15.

6.3.2.9.3

6.3.2.9.4

Releasing the Mailbox

The mailbox associated with a particular Transaction ID is only unlocked / released

upon successful transmission of the last bit of the Read FCS. If the originator aborts the

transaction prior to transmission of this bit (presumably due to an FCS failure), the

semaphore is maintained and the MbxGet() command may be retried.

Mailbox Timeouts

The mailbox is a shared resource that can result in artificial bandwidth conflicts among

multiple querying processes that are sharing the same originator interface. The

interface response time is quick, and with rare exception, back to back MbxSend() and

MbxGet() commands should result in successful execution of the request and release of

the mailbox. In order to guarantee timely retrieval of response data and mailbox

release, the mailbox semaphore has a timeout policy. If the PECI bus has a cumulative

‘0 time of 1ms since the semaphore was acquired, the semaphore is automatically

cleared. In the event that this timeout occurs, the originating agent will receive a failed

completion code upon issuing a MbxGet() command, or even worse, it may receive

corrupt data if this MbxGet() command so happens to be interleaved with an

MbxSend() from another process. Please refer to Table 6-24 for more information

regarding failed completion codes from MbxGet() commands.

Timeouts are undesirable, and the best way to avoid them and guarantee valid data is

for the originating agent to always issue MbxGet() commands immediately following

MbxSend() commands.

Alternately, mailbox timeout can be disabled. BIOS may write MSR

MISC_POWER_MGMT (0x1AA), bit 11 to 0b1 in order to force a disable of this

automatic timeout.

6.3.2.9.5

Response Latency

The PECI mailbox interface is designed to have response data available within plenty of

margin to allow for back-to-back MbxSend() and MbxGet() requests. However, under

rare circumstances that are out of the scope of this specification, it is possible that the

response data is not available when the MbxGet() command is issued. Under these

circumstances, the MbxGet() command will respond with an Abort FCS and the

originator should re-issue the MbxGet() request.

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6.3.3

Multi-Domain Commands

The Intel Xeon processor 5500 series does not support multiple domains, but it is

possible that future products will, and the following tables are included as a reference

for domain-specific definitions.

Table 6-25. Domain ID Definition

Domain ID

Domain Number

0b01

0

0b10

1

Table 6-26. Multi-Domain Command Code Reference

Domain 0

Domain 1

Code

Command Name

Code

GetTemp()

PCIConfigRd()

PCIConfigWr()

MbxSend()

0x01

0xC1

0xC5

0xD1

0xD5

0x02

0xC2

0xC6

0xD2

0xD6

MbxGet()

6.3.4

Client Responses

6.3.4.1

Abort FCS

The Client responds with an Abort FCS under the following conditions:

• The decoded command is not understood or not supported on this processor (this

includes good command codes with bad Read Length or Write Length bytes).

• Data is not ready.

• Assured Write FCS (AW FCS) failure. Note that under most circumstances, an

Assured Write failure will appear as a bad FCS. However, when an originator issues

a poorly formatted command with a miscalculated AW FCS, the client will

intentionally abort the FCS in order to guarantee originator notification.

6.3.4.2

Completion Codes

Some PECI commands respond with a completion code byte. These codes are designed

to communicate the pass/fail status of the command and also provide more detailed

information regarding the class of pass or fail. For all commands listed in Section 6.3.2

that support completion codes, each command’s completion codes is listed in its

respective section. What follows are some generalizations regarding completion codes.

An originator that is decoding these commands can apply a simple mask to determine

pass or fail. Bit 7 is always set on a failed command, and is cleared on a passing

command.

Table 6-27. Completion Code Pass/Fail Mask

0xxx xxxxb

1xxx xxxxb

Command passed

Command failed

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Table 6-28. Device Specific Completion Code (CC) Definition

Completion

Description

Code

0x00..0x3F

0x40

Device specific pass code

Command Passed

0x4X

Command passed with a transaction ID of ‘X’ (0x40 | Transaction_ID[3:0])

Device specific pass code

0x50..0x7F

CC: 0x80

Error causing a response timeout. Either due to a rare, internal timing condition or a

processor RESET condition or processor S1 state. Retry is appropriate outside of the RESET

or S1 states.

CC: 0x81

CC: 0x82

CC: 0x83

CC: 0x84

CC: 0x85

CC: 0x86

CC:0xFF

Thermal configuration data was malformed or exceeded limits.

Thermal status mask is illegal

Invalid counter select

Invalid Machine Check Bank or Index

Failure due to lack of Mailbox lock or invalid Transaction ID

Mailbox interface is unavailable or busy

Unknown/Invalid Mailbox Request

Note:

The codes explicitly defined in this table may be useful in PECI originator response

algorithms. All reserved or undefined codes may be generated by a PECI client device,

and the originating agent must be capable of tolerating any code. The Pass/Fail mask

defined in Table 6-27 applies to all codes and general response policies may be based

on that limited information.

6.3.5

Originator Responses

The simplest policy that an originator may employ in response to receipt of a failing

completion code is to retry the request. However, certain completion codes or FCS

responses are indicative of an error in command encoding and a retry will not result in

a different response from the client. Furthermore, the message originator must have a

response policy in the event of successive failure responses.

Please refer to the definition of each command in Section 6.3.2 for a specific definition

of possible command codes or FCS responses for a given command. The following

response policy definition is generic, and more advanced response policies may be

employed at the discretion of the originator developer.

Table 6-29. Originator Response Guidelines

Response

After 1 Attempt

After 3 attempts

Fail with PECI client device error

Bad FCS

Abort FCS

CC: Fail

Retry

Fail with PECI client device error. May be due to illegal command codes.

Either the PECI client doesn’t support the current command code, or it has

failed in its attempts to construct a response.

None (all 0’s) Force bus idle

(1ms low), retry

Fail with PECI client device error. Client may be dead or otherwise non-

responsive (in RESET or S1, for example).

CC: Pass

Pass

n/a

Good FCS

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6.3.6

Temperature Data

6.3.6.1

Format

The temperature is formatted in a 16-bit, 2’s complement value representing a number

of 1/64 degrees centigrade. This format allows temperatures in a range of ±512°C to

be reported to approximately a 0.016°C resolution.

Figure 6-26. Temperature Sensor Data Format

MSB

LSB

Upper nibble

Lower nibble

Upper nibble

Lower nibble

S

x

Sign

Integer Value (0-511)

Fractional Value (~0.016)

6.3.6.2

Interpretation

The resolution of the processor’s Digital Thermal Sensor (DTS) is approximately 1°C,

which can be confirmed by a RDMSR from IA32_THERM_STATUS MSR (0x19C) where it

is architecturally defined. PECI temperatures are sent through a configurable low-pass

filter prior to delivery in the GetTemp() response data. The output of this filter produces

temperatures at the full 1/64°C resolution even though the DTS itself is not this

accurate.

Temperature readings from the processor are always negative in a 2’s complement

format, and imply an offset from the reference TCC activation temperature. As an

example, assume that the TCC activation temperature reference is 100°C. A PECI

thermal reading of -10 indicates that the processor is running approximately 10°C

below the TCC activation temperature, or 90°C. PECI temperature readings are not

reliable at temperatures above TCC activation (since the processor is operating out of

specification at this temperature). Therefore, the readings are never positive.

6.3.6.3

Temperature Filtering

The processor digital thermal sensor (DTS) provides an improved capability to monitor

device hot spots, which inherently leads to more varying temperature readings over

short time intervals. Coupled with the fact that typical fan speed controllers may only

read temperatures at 4 Hz, it is necessary for the thermal readings to reflect thermal

trends and not instantaneous readings. Therefore, PECI supports a configurable low-

pass temperature filtering function. By default, this filter results in a thermal reading

that is a moving average of 256 samples taken at approximately 1msec intervals. This

filter’s depth, or smoothing factor, may be configured to between 1 sample and 1024

samples, in powers of 2. See the equation below for reference where the configurable

variable is ‘X’.

T_N= T_N-1+ 1/2^X* (T_SAMPLE- T_N-1

)

Please refer to Section 6.3.2.6.7 for the definition of the thermal configuration

command.

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6.3.6.4

Reserved Values

Several values well out of the operational range are reserved to signal temperature

sensor errors. These are summarized in the table below:

Table 6-30. Error Codes and Descriptions

Error Code

Description

0x8000

General Sensor Error (GSE)

6.3.7

Client Management

6.3.7.1

Power-up Sequencing

The PECI client is fully reset during processor RESET# assertion. This means that any

transactions on the bus will be completely ignored, and the host will read the response

from the client as all zeroes. After processor RESET# deassertion, the Intel Xeon

processor 5500 series PECI client is operational enough to participate in timing

negotiations and respond with reasonable data. However, the client data is not

guaranteed to be fully populated until approximately 500 µS after processor RESET# is

deasserted. Until that time, data may not be ready for all commands. The client

responses to each command are as follows:

Table 6-31. PECI Client Response During Power-Up (During ‘Data Not Ready’)

Command

Ping()

Response

Fully functional

GetDIB()

GetTemp()

PCIConfigRd()

PCIConfigWr()

MbxSend()

MbxGet()

Client responds with a ‘hot’ reading, or 0x0000

Fully functional

Client responds with Abort FCS (if MbxSend() has been previously issued)

In the event that the processor is tri-stated using power-on-configuration controls, the

PECI client will also be tri-stated. Processor tri-state controls are described in

Section 7.

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Figure 6-27. PECI Power-up Timeline

Vtt

VttPwrGd

SupplyVcc

Bclk

VccPwrGd

RESET#

Mclk

CSI pins

CSI training

idle

running

Reset uCode

Boot BIOS

uOp execution

In Reset

Data Not Rdy

Fully Operational

PECI Client Status

x

PECI Node ID

0b1 or 0b0

6.3.7.2

6.3.7.3

Device Discovery

The PECI client is available on all processors, and positive identification of the PECI

revision number can be achieved by issuing the GetDIB() command. Please refer to

Section 6.3.2.2 for details on GetDIB response formatting.

Client Addressing

The PECI client assumes a default address of 0x30. If nothing special is done to the

processor, all PECI clients will boot with this address. For DP enabled parts, a special

PECI_ID# pin is available to strap each PECI socket to a different node ID. The package

pin strap is evaluated at the assertion of VCCPWRGOOD (as depicted in Figure 6-27).

Since PECI_ID# is active low, tying the pin to ground results in a client address of

0x31, and tying it to V_TTresults in a client address of 0x30.

The client address may not be changed after VCCPWRGOOD assertion, until the next

power cycle on the processor. Removal of a processor from its socket or tri-stating a

processor in a DP configuration will have no impact to the remaining non-tri-stated

PECI client address.

6.3.7.4

C-States

The Intel Xeon processor 5500 series PECI client is fully functional under all core and

package C-states. Support for package C-states is a function of processor SKU and

platform capabilities. All package C-states (C1/C1E, C3, and C6) are annotated here for

completeness, but actual processor support for these C-states may vary.

Because the Intel Xeon processor 5500 series takes aggressive power savings actions

under the deepest C-states (C1/C1E, C3, and C6), PECI requests may have an impact

to platform power. The impact is documented below:

• Ping(), GetDIB(), GetTemp() and MbxGet() have no measurable impact on

processor power under C-states.

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• MbxSend(), PCIConfigRd() and PCIConfigWr() usage under package C-states may

result in increased power consumption because the processor must temporarily

return to a C0 state in order to execute the request. The exact power impact of a

pop-up to C0 varies by product SKU, the C-state from which the pop-up is initiated,

and the negotiated T_BIT

.

Table 6-32. Power Impact of PECI Commands versus C-states

Command

Ping()

Power Impact

Not measurable

GetDIB()

Not measurable

GetTemp()

PCIConfigRd()

PCIConfigWr()

MbxSend()

MbxGet()

Not measurable

Requires a package ‘pop-up’ to a C0 state

Not measurable

6.3.7.5

S-States

The PECI client is always guaranteed to be operational under S0 and S1 sleep states.

Under S3 and deeper sleep states, the PECI client response is undefined and therefore

unreliable.

Table 6-33. PECI Client Response During S1

Command

Response

Ping()

Fully functional

GetDIB()

GetTemp()

PCIConfigRd()

PCIConfigWr()

MbxSend()

MbxGet()

6.3.7.6

Processor Reset

The Intel Xeon processor 5500 series PECI client is fully reset on all RESET# assertions.

Upon deassertion of RESET#, where power is maintained to the processor (otherwise

known as a ‘warm reset’), the following are true:

• The PECI client assumes a bus Idle state.

• The Thermal Filtering Constant is retained.

• PECI Node ID is retained.

• GetTemp() reading resets to 0x0000.

• Any transaction in progress is aborted by the client (as measured by the client no

longer participating in the response).

• The processor client is otherwise reset to a default configuration.

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7 Features

7.1

Power-On Configuration (POC)

Several options can be configured by hardware. Power-On configuration (POC)

functionality is provided by strapping VID signals (see Table 2-3) or sampled on the

active-to-inactive transition of RESET#. For specifics on these options, please refer to

Table 7-1.

Please note that requests to execute Built-In Self Test (BIST) are not selected by

hardware, but rather passed across the Intel QuickPath Interconnect link during

initialization.

Processors sample VID[2:0]/MSID[2:0] and VID[5:3]/CSC[2:0] around the asserting

edge VTTPWRGOOD.

Table 7-1.

Power On Configuration Signal Options

Configuration Option

Output tristate

Signal

Reference

Section 6.2.4

1

PROCHOT#

2, 3

PECI ID

MSID

ODT/PECI_ID#

Section 6.3.7.3

Table 2-3

2, 3

VID[2:0]/MSID[2:0]

2, 3

CSC

VID[5:3]/CSC[2:0]

Table 2-3

Notes:

1. Asserting this signal during RESET# de-assertion will select the corresponding option. Once selected, this

option cannot be changed except via another reset. The processor does not distinguish between a "warm"

reset and a "power-on" reset. Output tri-state via the PROCHOT# power-on configuration option is referred

to as Fault Resilient Boot (FRB).

2. Latched when VTTPWRGOOD is asserted and all internal power good conditions are met.

3. See the signal definitions in Table 5-1 for the description of PECI_ID#, MSID, and CSC.

Assertion of the PROCHOT# signal through RESET# de-assertion (also referred to as

Fault Resilient Boot (FRB)) will tri-state processor outputs. Figure 7-1 outlines timing

requirements when utilizing PROCHOT# as a power-on configuration option. In the

event an FRB is desired, PROCHOT# and RESET# should be asserted simultaneously.

Furthermore, once asserted, PROCHOT# should remain low long enough to meet the

Power-On Configuration Hold Time (PROCHOT#). Failure to do so may result in false

tri-state.

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Figure 7-1. PROCHOT# POC Timing Requirements

Min Setup (2)

Min Hold (106)

BCLK

CPURESET#

Tri-State POC

(xxPROCHOT#)

Non-FRB assertion of

xxPROCHOT# during this window

can trigger false tri-state

xxPROCHOT# deassertion is not required for FRB

Power-On Configuration (POC) logic levels are MUX-ed onto the VID[7:0] signals with

1-5 KΩ pull-up and pull-down resistors located on the baseboard. These include:

• VID[2:0] / MSID[2:0] = Market Segment ID

• VID[5:3] / CSC[2:0] = Current Sense Configuration

• VID[6] = Reserved

• VID[7] = VR11.1 Select

Pull-up and pull-down resistors on the baseboard eliminate the need for timing

specifications After the voltage regulator’s OUTEN signal is asserted, the VID[7:0]

CMOS drivers (typically 50Ω up / down impedance) override the POC pull-up / down

resistors located on the baseboard and drive the necessary VID pattern. Please refer to

Table 2-3 for further details.

7.2

Clock Control and Low Power States

The processor supports low power states at the individual thread, core, and package

level for optimal power management. The processor implements software interfaces for

requesting low power states: MWAIT instruction extensions with sub-state hints, the

HLT instruction (for C1 and C1E) and P_LVLx reads to the ACPI P_BLK register block

mapped in the processor’s I/O address space. The P_LVLx I/O reads are converted to

equivalent MWAIT C-state requests inside the processor and do not directly result in

I/O reads to the system. The P_LVLx I/O Monitor address does not need to be set up

before using the P_LVLx I/O read interface.

Note:

Software may make C-state requests by using a legacy method involving I/O reads

from the ACPI-defined processor clock control registers, referred to as P_LVLx. This

feature is designed to provide legacy support for operating systems that initiate C-state

transitions via access to pre-defined ICH registers. The base P_LVLx register is P_LVL2,

corresponding to a C3 request. P_LVL3 is C6, and all P_LVL4+ are demoted to a C6.

P_LVLx is limited to a subset of C-states supported on the processor (for example,

P_LVL8 is not supported and will not cause an I/O redirection to a C8 request. Instead,

it will fall through like a normal I/O instruction). The range of I/O addresses that may

be converted into C-state requests is also defined in the PMG_IO_CAPTURE MSR, in the

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‘C-state Range’ field. This field maybe written by BIOS to restrict the range of I/O

addresses that are trapped and redirected to MWAIT instructions. Note that when I/O

instructions are used, no MWAIT substates can be defined, as therefore the request

defaults to have a sub-state or zero, but always assumes the ‘break on EFLAGS.IF==0’

control that can be selected using ECX with an MWAIT instruction.

Figure 7-2. Power States

C0

MWAIT C1,

HLT

MWAIT C6,

I/O C6

2

MWAIT C1,

HLT (C1E

enabled)

MWAIT C3,

I/O C3

C E¹

C1¹

1

C3

C6

1. No transition to C0 is needed to service a snoop when in C1 or C1E.

,

.

2. Transitions back to C0 occur on an interrupt or on access to monitored address (if state was entered via MWAIT).

.

7.2.1

Thread and Core Power State Descriptions

Individual threads may request low power states as described below. Core power states

are automatically resolved by the processor as shown in Table 7-2.

Table 7-2.

Coordination of Thread Power States at the Core Level

Core State

Thread 1 State

1

Thread 0 State

C0

C1

C3

C6

C0

C1¹

C3

C0

C1¹

C3

C0

C1¹

C3

C1¹

C0

C6

C3

C6

Notes:

1.

If enabled, state will be C1E.

7.2.1.1

C0 State

This is the normal operating state in the processor.

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7.2.1.2

C1/C1E State

C1/C1E is a low power state entered when all threads within a core execute a HLT or

MWAIT(C1E) instruction. The processor thread will transition to the C0 state upon

occurrence of an interrupt or an access to the monitored address if the state was

entered via the MWAIT instruction. RESET# will cause the processor to initialize itself

and return to C0.

A System Management Interrupt (SMI) handler will return execution to either Normal

state or the C1/C1E state. See the Intel® 64 and IA-32 Architectures Software

Developer's Manual, Volume III: System Programmer's Guide for more information.

While in C1/C1E state, the processor will process bus snoops and snoops from the

other threads.

To operate within specification, BIOS must enable the C1E feature for all installed

processors.

7.2.1.3

C3 State

Individual threads of the processor can enter the C3 state by initiating a P_LVL2 I/O

read to the P_BLK or an MWAIT(C3) instruction. Before entering core C3, the core

flushes the contents of its caches. Except for the caches, the processor core maintains

all its architectural state while in the C3 state. All of the clocks in the processor core are

stopped in the C3 state.

Because the core’s caches are flushed, the processor keeps the core in the C3 state

when the processor detects a snoop on the Intel QuickPath Interconnect Link or when

another logical processor in the same package accesses cacheable memory. The

processor core will transition to the C0 state upon occurrence of an interrupt. RESET#

will cause the processor core to initialize itself.

7.2.1.4

C6 State

Individual threads of the processor can enter the C6 state by initiating a P_LVL3 read to

the P_BLK or an MWAIT(C6) instruction. Before entering core C6, the processor saves it

state. The processor achieves additional power savings in the core C6 state.

7.2.2

Package Power State Descriptions

The package supports C0, C1/C1E, C3, and C6 power states. The package power state

is automatically resolved by the processor depending on the core power states and

permission from the rest of the system as described below.

7.2.2.1

Package C0 State

This is the normal operating state for the processor. The processor remains in the

Normal state when at least one of its cores is in the C0 or C1 state or when another

component in the system has not granted permission to the processor to go into a low

power state. Individual components of the processor may be in low power states while

the package in C0.

7.2.2.2

Package C1/C1E State

The package will enter the C1/C1E low power state when at least one core is in the

C1/C1E state and the rest of the cores are in the C1/C1E or lower power state. The

processor will also enter the C1/C1E state when all cores are in a power state lower

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than C1/C1E but the package low power state is limited to C1/C1E via the

PMG_CST_CONFIG_CONTROL MSR. In the C1E state, the processor will automatically

transition to the lowest power operating point (lowest supported voltage and associated

frequency). When entering the C1E state, the processor will first switch to the lowest

bus ratio and then transition to the lower VID. No notification to the system occurs

upon entry to C1/C1E.

To operate within specification, BIOS must enable the C1E feature for all installed

processors.

7.2.2.3

Package C3 State

The package will enter the C3 low power state when all cores are in the C3 or lower

power state and the processor has been granted permission by the other component(s)

in the system to enter the C3 state. The package will also enter the C3 state when all

cores are in an idle state lower than C3 but other component(s) in the system have

only granted permission to enter C3.

If Intel QuickPath Interconnect L1 has been granted, the processor will disable some

clocks and PLLs and for processors with an Integrated Memory Controller, the DRAM

will be put into self-refresh.

7.2.2.4

Package C6 State

The package will enter the C6 low power state when all cores are in the C6 or lower

power state and the processor has been granted permission by the other component(s)

in the system to enter the C6 state. The package will also enter the C6 state when all

cores are in an idle state lower than C6 but the other component(s) have only granted

permission to enter C6.

If Intel QuickPath Interconnect L1 has been granted, the processor will disable some

clocks and PLLs and the shared cache will enter a deep sleep state. Additionally, for

processors with an Integrated Memory Controller, the DRAM will be put into self-

refresh.

7.2.3

Intel Xeon Processor 5500 Series C-State Power

Specifications

Table 7-3 lists C-State power specifications for various Intel Xeon processor 5500 series

SKUs.

Table 7-3.

Processor C-State Power Specifications

Package

C-State

2

3

130W

95W

80W

60W

38W

1

C1E

C3

35 W

30 W

12 W

30 W

26 W

10 W

30/40 W

26/35 W

10/15 W

22 W

18 W

8 W

16 W

12 W

8 W

C6

Notes:

1. Specifications are at T

2. Standard/Basic SKUs.

= 50C with all cores in the specified C-State.

case

®

3. Applies to Low Power SKU and Intel Xeon Processor L5518.

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7.3

Sleep States

The processor supports the ACPI sleep states S0, S1, S3, and S4/S5 as shown in. For

information on ACPI S-states and related terminology, refer to ACPI Specification. The

S-state transitions are coordinated by the processor in response PM Request (PMReq)

messages from the chipset. The processor itself will never request a particular S-state.

Table 7-4.

Processor S-States

S-State

Power Reduction

Normal Code Execution

Allowed Transitions

S1 (via PMReq)

S0

S1

Cores in C1E like state, processor responds with

CmpD(S1) message.

S0 (via reset or PMReq)

S3, S4 (via PMReq)

S3

Memory put into self-refresh, processor responds with

CmpD(S3) message.

S0 (via reset)

S4/S5

Processor responds with CmpD(S4/S5) message.

S0 (via reset)

Notes:

1.

If the chipset requests an S-state transition which is not allowed, a machine check error

will be generated by the processor.

7.4

7.5

Intel^®Turbo Boost Technology

The processor supports ACPI Performance States (P-States). The P-state referred to as

P0 will be a request for Intel^®Turbo Boost Technology (Intel^®TBT). Intel TBT

opportunistically, and automatically, allows the processor to run faster than the marked

frequency if the part is operating below power, temperature and current limits. Max

Turbo Boost frequency is dependent on the number of active cores and varies by

processor line item configuration. Intel TBT doesn’t need special hardware support, and

can be enabled or disabled by BIOS.

Enhanced Intel SpeedStep^®Technology

The processor features Enhanced Intel SpeedStep^®Technology. Following are the key

features of Enhanced Intel SpeedStep Technology:

• Multiple voltage and frequency operating points provide optimal performance at the

lowest power.

• Voltage and frequency selection is software controlled by writing to processor

MSRs:

— If the target frequency is higher than the current frequency, V_CCis ramped up

in steps by placing new values on the VID pins and the PLL then locks to the

new frequency.

— If the target frequency is lower than the current frequency, the PLL locks to the

new frequency and the V_CCis changed through the VID pin mechanism.

— Software transitions are accepted at any time. If a previous transition is in

progress, the new transition is deferred until the previous transition completes.

• The processor controls voltage ramp rates internally to ensure smooth transitions.

• Low transition latency and large number of transitions possible per second:

— Processor core (including shared cache) is unavailable for less than 2µs during

the frequency transition.

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8 Boxed Processor Specifications

8.1

Introduction

Intel boxed processors are intended for system integrators who build systems from

components available through distribution channels. The Intel Xeon processor 5500

series will be offered as an Intel boxed processor, however the thermal solution will be

sold separately.

Unlike previous-generation boxed processors, Intel Xeon processor 5500 series boxed

processors will not include thermal solution in the box. Intel will offer boxed thermal

solutions separately through the same distribution channels. Please reference

Section 8.1.1 - Section 8.1.4 for more details on Boxed Processor Thermal Solutions.

8.1.1

Available Boxed Thermal Solution Configurations

Intel will offer three different Boxed Heat Sink solutions to support the boxed

Processors.

• Boxed Intel “Combo” Thermal Solution. The Passive / Active Combination Heat Sink

Solution is intended for processors with a TDP up to 130W in a pedestal or 2U+

chassis with appropriate ducting)

• Boxed Intel “Active” Thermal Solution. The Active Heat Sink Solution is intended for

processors with a TDP of 80W or lower in pedestal chassis

• Boxed Intel “Passive” Thermal Solution. The 25.5 mm tall Passive Heat Sink

Solution is intended for processors with a TDP of 95W or lower in Blades, 1U, or 2U

chassis with appropriate ducting.

8.1.2

An Intel “Combo” Boxed Passive / Active Combination

Heat Sink Solution

The Passive / Active combination solution, based on a 2U passive heat sink with a

removable fan, is intended for use with processors with TDP’s up to 130 W. This heat

pipe based solution is intended to be used as either a passive heat sink in a 2U or

larger chassis, or as an active heat sink for pedestal chassis. Figure 8-2 and Figure 8-3

are representations of the heat sink solution. Although the active combination solution

with the removable fan installed mechanically fits into a 2U keepout, its use has not

been validated in that configuration.

The Passive / Active combination solution in the active fan configuration is primarily

designed to be used in a pedestal chassis where sufficient air inlet space is present. The

Passive / Active combination solution with the fan removed, as with any passive

thermal solution, will require the use of chassis ducting and are targeted for use in rack

mount or ducted pedestal servers. The retention solution used for these products is

called Unified Retention System (URS).

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8.1.3

Intel Boxed “Active” Heat Sink Solution

The Boxed Active solution will be available for purchase for processors with TDP’s of

80W and lower and will be an aluminum extrusion. This heat sink solution is intended

to be used as an active heat sink only for pedestal chassis. Figure 8-1 is a

representation of the heat sink solution.

Both active solutions will utilize a fan capable of 4-pin pulse width modulated (PWM)

control. Use of a 4-pin PWM controlled active thermal solution helps customers meet

acoustic targets in pedestal platforms through the baseboard’s ability to directly control

the RPM of the processor heat sink fan. See Section 8.3 for more details on fan speed

control, also see Section 6.3 for more on the PWM and PECI interface along with Digital

Thermal Sensors (DTS).

Figure 8-1. Boxed Active Heat Sink

Figure 8-2. Boxed Passive / Active Combination Heat Sink (With Removable Fan)

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Figure 8-3. Boxed Passive/Active Combination Heat Sink (with Fan Removed)

Figure 8-4. Intel Boxed 25.5 mm Tall Passive Heat Sink Solution

8.1.4

Intel Boxed 25.5mm Tall Passive Heat Sink Solution

The boxed 25.5 mm Tall heatsink solution will be available for use with boxed

processors that have TDP’s of 95 W and lower. The 25.5 mm Tall passive solution is

designed to be used in Blades, 1U, and 2U chassis where ducting is present. The use of

a 25.5 mm Tall heatsink in a 2U chassis is recommended to achieve a lower heatsink

T_LAand a more optimized heatsink design. Figure 8-4 is a representation of the heat

sink solution. The retention solution used for these products is called Unified Retention

System (URS).

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8.2

Mechanical Specifications

This section documents the mechanical specifications of the boxed processor solution.

8.2.1

Boxed Processor Heat Sink Dimensions and Baseboard

Keepout Zones

The boxed processor and boxed thermal solution will be sold separately. Clearance is

required around the thermal solution to ensure unimpeded airflow for proper cooling.

Baseboard keepout zones are shown in Figure 8-5 through Figure 8-8. Physical space

requirements and dimensions for the boxed processor and assembled heat sink are

shown in Figure 8-9. Mechanical drawings for the 4-pin fan header and 4-pin connector

used for the active fan heat sink solution are represented in Figure 8-11 and

Figure 8-12.

None of the heat sink solutions exceed a mass of 550 grams. Note that this is per

processor, a dual processor system will have up to 1100 grams total mass in the heat

sinks.

See Section 3 for details on the processor mass.

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Figure 8-5. Top Side Baseboard Keep-Out Zones

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Figure 8-6. Top Side Baseboard Mounting-Hole Keep-Out Zones

3 . [ 3 4 6

8 5 . 0 0

]

3 . [ 1 5 0

]

2 X 8 0 . 0 0

2 . [ 8 5 4

]

2 X 7 2 . 5 0

2 . [ 6 6 5

6 7 . 7 0

]

2 . [ 2 8 3 5

5 8 . 0 0 0

]

1 . [ 8 5 6

4 7 . 1 5

]

1 . [ 2 9 3

3 2 . 8 5

]

0 . [ 8 6 6 1

2 2 . 0 0 0

]

4

B A L L 1

0 . [ 7 5 5

1 9 . 1 7

0 . [ 4 8 4

1 2 . 3 0

]

0 . [ 3 7 8

9 . 6 0

0 . [ 2 9 5

]

2 X 7 . 5 0

0 [ . 0 0 0 ]

2 X 0 . 0 0

0 . [ 1 9 7

5 . 0 0

]

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Figure 8-7. Bottom Side Baseboard Keep-Out Zones

0 . [ 1 9 7

5 . 0 0

]

0 [ . 0 0 0 ]

0 . 0 0

0 . [ 3 7 4

9 . 5 0

]

1 . [ 2 9 3

3 2 . 8 5

]

1 . [ 8 5 6

4 7 . 1 5

]

2 . [ 7 7 6

7 0 . 5 0

]

3 . [ 3 4 6

8 5 . 0 0

]

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Figure 8-8. Primary and Secondary Side 3D Height Restriction Zones

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Figure 8-9. Volumetric Height Keep-Ins

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Figure 8-10. Volumetric Height Keep-Ins

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Figure 8-11. 4-Pin Fan Cable Connector (For Active Heat Sink)

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Figure 8-12. 4-Pin Base Baseboard Fan Header (For Active Heat Sink)

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8.2.2

Boxed Processor Retention Mechanism and Heat Sink

Support (URS)

Baseboards designed for use by a system integrator should include holes that are in

proper alignment with each other to support the boxed processor. Refer to Figure 8-5

for mounting hole dimensions.

Figure 8-13 illustrates the Unified Retention System (URS) and the Unified Backplate

Assembly. The URS is designed to extend air-cooling capability through the use of

larger heat sinks with minimal airflow blockage and bypass. URS retention transfers

load to the baseboard via the Unified Backplate Assembly. The URS spring, captive in

the heatsink, provides the necessary compressive load for the thermal interface

material. For specific design details on the URS and the Unified Backplate please refer

to the Intel® Xeon® Processor 5500 Series Thermal / Mechanical Design Guide.

All components of the URS heat sink solution will be captive to the heat sink and will

only require a Phillips screwdriver to attach to the Unified Backplate Assembly. When

installing the URS the screws should be tightened until they will no longer turn easily.

This should represent approximately 8 inch-pounds of torque. More than that may

damage the retention mechanism components.

®

Intel Xeon Processor 5500 Series Datasheet, Volume 1

149

Boxed Processor Specifications

Figure 8-13. Thermal Solution Installation

8.3

Fan Power Supply (“Combo” and “Active”

Solution)

The 4-pin PWM controlled thermal solution is being offered to help provide better

control over pedestal chassis acoustics. This is achieved though more accurate

measurement of processor die temperature through the processor’s Digital Thermal

Sensors. Fan RPM is modulated through the use of an ASIC located on the baseboard

that sends out a PWM control signal to the 4th pin of the connector labeled as Control.

This thermal solution requires a constant +12 V supplied to pin 2 of the active thermal

solution and does not support variable voltage control or 3-pin PWM control. See

Table 8-1 through Table 8-3 for details on the 4-pin active heat sink solution

connectors.

®

150

Intel Xeon Processor 5500 Series Datasheet, Volume 1

Boxed Processor Specifications

The fan power header on the baseboard must be positioned to allow the fan heat sink

power cable to reach it. The fan power header identification and location must be

documented in the suppliers platform documentation, or on the baseboard itself. The

baseboard fan power header should be positioned within 177.8 mm [7 in.] from the

center of the processor socket.

Table 8-1.

Table 8-2.

PWM Fan Frequency Specifications For 4-Pin Active Thermal Solution

Description

Min Frequency

Nominal Frequency

Max Frequency

Unit

PWM Control

Frequency Range

21,000

25,000

28,000

Hz

Fan Specifications For 4-Pin Active Thermal Solution

Typ

Steady

Max

Steady

Max

Startup

Description

Min

Unit

+12 V: 12 volt fan power supply

IC: Fan Current Draw

10.8

N/A

12

13.2

2.2

V

A

1.25

1.5

Pulses per fan

revolution

SENSE: SENSE frequency

2

Figure 8-14. Fan Cable Connector Pin Out For 4-Pin Active Thermal Solution

Table 8-3.

Fan Cable Connector Pin Out for 4-Pin Active Thermal Solution

Pin Number

Signal

Color

1

2

3

4

Ground

Black

Yellow

Green

Blue

Power: (+12 V)

Sense: 2 pulses per revolution

Control: 21 KHz-28 KHz

8.3.1

Boxed Processor Cooling Requirements

As previously stated the boxed processor will have three cooling solutions available.

Each configuration will require unique design considerations. Meeting the processor’s

temperature specifications is also the function of the thermal design of the entire

system, and ultimately the responsibility of the system integrator. The processor

temperature specifications are found in Section 6 of this document.

®

Intel Xeon Processor 5500 Series Datasheet, Volume 1

151

Boxed Processor Specifications

8.3.1.1

2U Passive / Active Combination Heat Sink Solution

Active Configuration:

The active configuration of the combination solution is designed to help pedestal

chassis users to meet the thermal processor requirements without the use of chassis

ducting. It may be still be necessary to implement some form of chassis air guide or air

duct to meet the T_LAtemperature of 40°C depending on the pedestal chassis layout.

Use of the active configuration in a 2U rackmount chassis is not recommended.

It is recommended that the ambient air temperature outside of the chassis be kept at

or below 35°C. The air passing directly over the processor thermal solution should not

be preheated by other system components. Meeting the processor’s temperature

specification is the responsibility of the system integrator.

This thermal solution is for use with 95 W and 130 W TDP processor SKUs.

Passive Configuration:

In the passive configuration it is assumed that a chassis duct will be implemented.

Processors with a TDP of 130 W or 95 W must provide a minimum airflow of 30 CFM at

0.205 in. H₂O (51 m³/hr at 51.1 Pa) of flow impedance. For processors with a TDP of

130 W it is assumed that a 40°C T_LAis met. This requires a superior chassis design to

limit the T_RISEat or below 5°C with an external ambient temperature of 35°C. For

processors with a TDP of 95W it is assumed that a 55°C T_LAis met.

8.3.1.2

Active Heat Sink Solution (Pedestal only)

This active solution is designed to help pedestal chassis users to meet the thermal

processor requirements without the use of chassis ducting. It may be still be necessary

to implement some form of chassis air guide or air duct to meet the T_LAtemperature of

49°C depending on the pedestal chassis layout. Use of this active solution in a 2U

rackmount chassis has not been validated.

It is recommended that the ambient air temperature outside of the chassis be kept at

or below 35°C. The air passing directly over the processor thermal solution should not

be preheated by other system components. Meeting the processor’s temperature

specification is the responsibility of the system integrator.

This thermal solution is for use with processor SKUs no higher than 80W.

8.3.1.3

25.5 mm Tall Passive Heat Sink Solution (Blade + 1U + 2U Rack)

Note:

95 W SKU’s using the 25.5 mm Tall passive HS are only intended for use in 1U rack

configurations (Thermal Profile B). For use in 2U configurations see Section 8.3.1.2 for

details.

In the Blade, 1U and 2U configurations it is assumed that a chassis duct will be

implemented. Due to the complexity of the number of chassis and baseboard

configurations, several airflow and flow impedance values exist. Please refer to the

Intel® Xeon® Processor 5500/5600 Series Thermal / Mechanical Design Guide for

detailed mechanical drawings and specific airflow and impedance values applicable to

your use conditions. It is recommended that the ambient air temperature outside of the

chassis be kept at or below 35°C.

®

152

Intel Xeon Processor 5500 Series Datasheet, Volume 1

Boxed Processor Specifications

8.4

Boxed Processor Contents

The Boxed Processor and Boxed Thermal Solution contents are outlined below.

• Boxed Processor Contents

— Intel Xeon processor 5500 series

— Installation and warranty manual

— Intel Inside Logo

• Boxed Thermal Solution

— Heat sink assembly solution

— Thermal interface material (pre-applied on heat sink, if included)

— Installation and warranty manual

§

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Intel Xeon Processor 5500 Series Datasheet, Volume 1

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Boxed Processor Specifications

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“Announced” SKUs are not yet available. Please refer to the Launch Date for market availability.

Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating

system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.

64-bit computing on Intel® architecture requires a computer system with a processor, chipset, BIOS, operating system, device drivers and

applications enabled for Intel® 64 architecture. Processors will not operate (including 32-bit operation) without an Intel 64 architecture-

enabled BIOS. Performance will vary depending on your hardware and software configurations. Consult with your system vendor for more

information.

Hyper-Threading Technology (HT Technology) requires a computer system with an Intel® processor supporting HT Technology and an HT

Technology enabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use.

See www.intel.com/products/ht/hyperthreading_more.htm for more information including details on which processors support HT Technology.

Intel® Virtualization Technology requires a computer system with a processor, chipset, BIOS, virtual machine monitor (VMM) and for some

uses, certain platform software, enabled for it. Functionality, performance or other benefit will vary depending on hardware and software

configurations. Intel Virtualization Technology-enabled VMM applications are currently in development.

Note: Prices subject to change without notice. Prices are for direct Intel customers in 1000-unit bulk quantities and, unless specified,

represent the latest technology versions of the products. Taxes and shipping, etc. not included. Prices may vary for other package types and

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All information provided is subject to change at any time, without notice. Intel may make changes to manufacturing life cycle, specifications,

and product descriptions at any time, without notice. The information herein is provided "as-is" and Intel does not make any representations

or warranties whatsoever regarding accuracy of the information, nor on the product features, availability, functionality, or compatibility of the

products listed. Please contact system vendor for more information on specific products or systems.

Low Halogen implies the following:

Bromine and/or chlorine in materials that may be used during processing, but do not remain within the final product are not included in this

definition. The halogens fluorine (F), iodine (I), and astatine (At) are not restricted by this standard.

“BFR/CFR and PVC-Free” Definition: :

All PCB laminates must meet Br and Cl requirements for low halogen as defined in IPC-4101B

For components other than PCB laminates, all homogeneous materials must contain < 900 ppm (0.09%) of Bromine [if the Bromine (Br)

source is from BFRs] and < 900 ppm (0.09%) of Chlorine [if the Chlorine (Cl) source is from CFRs or PVC. Higher concentrations of Br and Cl

are allowed in homogenous materials of components other than PCB laminates as long as their sources are not BFRs, CFRs, PVC.

Although the elemental analysis for Br and Cl in homogeneous materials can be performed by any analytical method with sufficient sensitivity

and selectivity, the presence or absence of BFRs, CFRs or PVC must be verified by any acceptable analytical techniques that allow for the

unequivocal identification of the specific Br or Cl compounds, or by appropriate material declarations agreed to between customer and

supplier.

Max Turbo Frequency refers to the maximum single-core frequency that can be achieved with Intel® Turbo Boost Technology, which requires

a PC with a processor with Intel Turbo Boost Technology capability. Intel Turbo Boost Technology performance varies depending on hardware,

software, and overall system configuration. Check with your PC manufacturer on whether your system delivers Intel Turbo Boost Technology.

See www.intel.com/technology/turboboost/ for more information.

Some products can support AES New Instructions with a Processor Configuration update, in particular, i7-2630QM/i7-2635QM,

i7-2670QM/i7-2675QM, i5-2430M/i5-2435M, i5-2410M/i5-2415M. Please contact OEM for the BIOS that includes the latest Processor

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VT-x

Yes

FCLGA1366

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AT80602002712AA

SLBFH

Yes

Boxed Intel® Xeon® Processor L5506 (4M Cache, 2.13 GHz, 4.80 GT/s Intel® QPI) FC-LGA8

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Step

Step TDP

Ordering Code

Spec Code

VT-x

Yes

FCLGA1366

60 W

BX80602L5506

SLBFH

Yes

Compatible Products

Intel® Server Board S5520UR

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Intel® Compute Module MFS5520VIR