AT80601000897AA_技术文档

®

Intel Core™ i7-900 Desktop

Processor Extreme Edition Series

®

and Intel Core™ i7-900 Desktop

Processor Series

Datasheet, Volume 1

February 2010

Document # 320834-004

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED,

BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS

PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER,

AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING

LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY

PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. INTEL PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL,

LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel

reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future

changes to them.

The Intel Core™ i7-900 desktop processor Extreme Edition series and Intel Core™ i7-900 desktop processor series may contain

design defects or errors known as errata which may cause the product to deviate from published specifications.



Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor

family, not across different processor families. See http://www.intel.com/products/processor_number for details. Over time

processor numbers will increment based on changes in clock, speed, cache, FSB, or other features, and increments are not

intended to represent proportional or quantitative increases in any particular feature. Current roadmap processor number

progression is not necessarily representative of future roadmaps. See www.intel.com/products/processor_number for details.

Hyper-Threading Technology requires a computer system with a processor supporting HT Technology and an HT Technology-

enabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. For

more information including details on which processors support HT Technology, see

http://www.intel.com/products/ht/hyperthreading_more.htm

®

Intel 64 requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications enabled

®

for Intel 64. Processor will not operate (including 32-bit operation) without an Intel 64-enabled BIOS. Performance will vary

depending on your hardware and software configurations. See www.intel.com/info/em64t for more information including details on

®

which processors support Intel 64 or consult with your system vendor for more information.

®

± Intel Virtualization Technology requires a computer system with a processor, chipset, BIOS, virtual machine monitor (VMM) and

for some uses, certain platform software, enabled for it. Functionality, performance or other benefit will vary depending on

hardware and software configurations. Intel Virtualization Technology-enabled VMM applications are currently in development.

Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting

operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.

Enhanced Intel® SpeedStep Technology. See the Processor Spec Finder or contact your Intel representative for more information.

Intel® Turbo Boost Technology requires a PC with a processor with Intel Turbo Boost Technology capability. Intel Turbo Boost

Technology performance varies depending on hardware, software and overall system configuration. Check with your PC

manufacturer on whether your system delivers Intel Turbo Boost Technology. For more information, see www.intel.com.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Intel, Intel SpeedStep, Intel Core, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its

subsidiaries in the United States and other countries.

*Other names and brands may be claimed as the property of others.

2

Datasheet

Contents

1

Introduction..............................................................................................................9

1.1

1.2

Terminology ..................................................................................................... 10

References ....................................................................................................... 11

2

Electrical Specifications........................................................................................... 13

2.1

2.2

2.3

Intel^®QPI Differential Signaling.......................................................................... 13

Power and Ground Lands.................................................................................... 13

Decoupling Guidelines........................................................................................ 13

2.3.1 VCC, VTTA, VTTD, VDDQ Decoupling......................................................... 14

Processor Clocking (BCLK_DP, BCLK_DN) ............................................................. 14

2.4.1 PLL Power Supply................................................................................... 14

Voltage Identification (VID) ................................................................................ 14

Reserved or Unused Signals................................................................................ 17

Signal Groups................................................................................................... 18

Test Access Port (TAP) Connection....................................................................... 19

Platform Environmental Control Interface (PECI) DC Specifications........................... 20

2.9.1 DC Characteristics.................................................................................. 20

2.9.2 Input Device Hysteresis .......................................................................... 21

2.4

2.5

2.6

2.7

2.8

2.9

2.10 Absolute Maximum and Minimum Ratings ............................................................. 21

2.11 Processor DC Specifications ................................................................................ 22

2.11.1 DC Voltage and Current Specification........................................................ 23

2.11.2 VCC Overshoot Specification.................................................................... 29

2.11.3 Die Voltage Validation............................................................................. 30

3

Package Mechanical Specifications .......................................................................... 31

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

Package Mechanical Drawing............................................................................... 31

Processor Component Keep-Out Zones................................................................. 34

Package Loading Specifications ........................................................................... 34

Package Handling Guidelines............................................................................... 34

Package Insertion Specifications.......................................................................... 34

Processor Mass Specification............................................................................... 35

Processor Materials............................................................................................ 35

Processor Markings............................................................................................ 35

Processor Land Coordinates................................................................................ 36

4

5

6

Land Listing............................................................................................................. 37

Signal Descriptions.................................................................................................. 67

Thermal Specifications ............................................................................................ 71

6.1

Package Thermal Specifications........................................................................... 71

6.1.1 Thermal Specifications ............................................................................ 71

6.1.2 Thermal Metrology ................................................................................. 75

Processor Thermal Features................................................................................ 76

6.2.1 Processor Temperature ........................................................................... 76

6.2.2 Adaptive Thermal Monitor........................................................................ 76

6.2.3 THERMTRIP# Signal ............................................................................... 79

Platform Environment Control Interface (PECI)...................................................... 79

6.3.1 Introduction .......................................................................................... 79

6.3.2 PECI Specifications................................................................................. 81

Storage Conditions Specifications ........................................................................ 82

6.2

6.3

6.4

Datasheet

3

7

8

Features ..................................................................................................................83

7.1

7.2

Power-On Configuration (POC).............................................................................83

Clock Control and Low Power States.....................................................................83

7.2.1 Thread and Core Power State Descriptions .................................................84

7.2.2 Package Power State Descriptions.............................................................85

Sleep States .....................................................................................................86

ACPI P-States (Intel^®Turbo Boost Technology) .....................................................86

Enhanced Intel^®SpeedStep^®Technology .............................................................87

7.3

7.4

7.5

Boxed Processor Specifications................................................................................89

8.1

8.2

Introduction......................................................................................................89

Mechanical Specifications....................................................................................90

8.2.1 Boxed Processor Cooling Solution Dimensions.............................................90

8.2.2 Boxed Processor Fan Heatsink Weight .......................................................92

8.2.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly .....92

Electrical Requirements ......................................................................................92

8.3.1 Fan Heatsink Power Supply ......................................................................92

Thermal Specifications........................................................................................93

8.4.1 Boxed Processor Cooling Requirements......................................................93

8.4.2 Variable Speed Fan.................................................................................95

8.3

8.4

Figures

1-1

2-1

2-2

2-3

2-4

2-5

3-1

3-2

3-3

3-4

3-5

6-1

6-2

6-3

7-1

8-1

8-2

8-3

8-4

8-5

8-6

8-7

8-8

8-9

High-Level View of Processor Interfaces................................................................. 9

Active ODT for a Differential Link Example ............................................................13

Input Device Hysteresis......................................................................................21

VCC Static and Transient Tolerance Load Lines ......................................................25

VTT Static and Transient Tolerance Load Line ........................................................27

VCC Overshoot Example Waveform......................................................................30

Processor Package Assembly Sketch.....................................................................31

Processor Package Drawing (Sheet 1 of 2) ............................................................32

Processor Package Drawing (Sheet 2 of 2) ............................................................33

Processor Top-side Markings ...............................................................................35

Processor Land Coordinates and Quadrants (Bottom View) ......................................36

Processor Thermal Profile....................................................................................73

Thermal Test Vehicle (TTV) Case Temperature (TCASE) Measurement Location..........75

Frequency and Voltage Ordering..........................................................................77

Power States.....................................................................................................84

Mechanical Representation of the Boxed Processor .................................................89

Space Requirements for the Boxed Processor (side view) ........................................90

Space Requirements for the Boxed Processor (top view) .........................................91

Space Requirements for the Boxed Processor (overall view) ....................................91

Boxed Processor Fan Heatsink Power Cable Connector Description............................92

Baseboard Power Header Placement Relative to Processor Socket.............................93

Boxed Processor Fan Heatsink Airspace Keepout Requirements (top view).................94

Boxed Processor Fan Heatsink Airspace Keepout Requirements (side view)................94

Boxed Processor Fan Heatsink Set Points ..............................................................95

4

Datasheet

Tables

1-1

2-1

2-2

2-3

2-4

2-5

2-6

2-7

2-8

2-9

References ....................................................................................................... 11

Voltage Identification Definition........................................................................... 15

Market Segment Selection Truth Table for MS_ID[2:0]........................................... 17

Signal Groups................................................................................................... 18

Signals with ODT............................................................................................... 19

PECI DC Electrical Limits .................................................................................... 20

Processor Absolute Minimum and Maximum Ratings............................................... 22

Voltage and Current Specifications....................................................................... 23

VCC Static and Transient Tolerance ..................................................................... 24

VTT Voltage Identification (VID) Definition............................................................ 25

2-10 VTT Static and Transient Tolerance...................................................................... 26

2-11 DDR3 Signal Group DC Specifications................................................................... 27

2-12 RESET# Signal DC Specifications......................................................................... 28

2-13 TAP Signal Group DC Specifications ..................................................................... 28

2-14 PWRGOOD Signal Group DC Specifications............................................................ 28

2-15 Control Sideband Signal Group DC Specifications................................................... 29

2-16 VCC Overshoot Specifications.............................................................................. 29

3-1

3-2

3-3

4-1

4-2

5-1

6-1

6-2

6-3

6-4

6-5

6-6

7-1

7-2

7-3

8-1

8-2

Processor Loading Specifications ......................................................................... 34

Package Handling Guidelines............................................................................... 34

Processor Materials............................................................................................ 35

Land Listing by Land Name................................................................................. 37

Land Listing by Land Number.............................................................................. 52

Signal Definitions .............................................................................................. 67

Processor Thermal Specifications......................................................................... 72

Processor Thermal Profile ................................................................................... 73

Thermal Solution Performance above TCONTROL................................................... 74

Supported PECI Command Functions and Codes.................................................... 81

GetTemp0() Error Codes .................................................................................... 81

Storage Conditions ............................................................................................ 82

Power On Configuration Signal Options................................................................. 83

Coordination of Thread Power States at the Core Level........................................... 84

Processor S-States ............................................................................................ 86

Fan Heatsink Power and Signal Specifications........................................................ 93

Fan Heatsink Power and Signal Specifications........................................................ 95

Datasheet

5

6

Datasheet

Intel^®Core™ i7-900 Desktop Processor Extreme Edition

Series and Intel^®Core™ i7-900 Desktop Processor Series

Features

• Available at 3.20 GHz, 3.06 GHz, 2.93 GHz,

2.80 GHz, and 2.66 GHz (Intel Core™ i7-900

desktop desktop processor series)

• System Management mode

• Multiple low-power states

• 8-way cache associativity provides improved

cache hit rate on load/store operations

• Available at 3.33 GHz and 3.20 GHz (Intel

Core™ i7-900 desktop processor Extreme

Edition series)

• System Memory Interface

• Enhanced Intel Speedstep^®Technology

• Supports Intel^®64^Architecture

• Supports Intel^®Virtualization Technology

• Intel^®Turbo Boost Technology

— Memory controller integrated in

processor package

— 3 channels

— 2 DIMMs/channel supported (6 total)

— 24 GB maximum memory supported

— Support unbuffered DIMMs only

— Single Rank and Dual Rank DIMMs

supported

• Supports Execute Disable Bit capability

• Binary compatible with applications running

on previous members of the Intel

microprocessor line

• Intel^®Wide Dynamic Execution

• Very deep out-of-order execution

• Enhanced branch prediction

• Optimized for 32-bit applications running on

advanced 32-bit operating systems

• Intel^®Smart Cache

— DDR3 speeds of 800/1066 MHz

supported

— 512Mb, 1Gb, 2Gb,

Technologies/Densities supported

• Intel^®QuickPath Interconnect (QPI)

— Fast/narrow unidirectional links

— Concurrent bi-directional traffic

— Error detection using CRC

— Error correction using Link level retry

— Packet based protocol

• 8 MB Level 3 cache

• Intel^®Advanced Digital Media Boost

• Enhanced floating point and multimedia unit

for enhanced video, audio, encryption, and

3D performance

• New accelerators for improved string and

text processing operations

— Point to point cache coherent

interconnect

— Intel^®Interconnect Built In Self Test

(Intel^®IBIST) toolbox built-in

• 1366-land Package

• Power Management capabilities

Datasheet

7

Revision History

Revision

Number

Description

Date

November 2008

June 2009

-001

-002

•

Initial release

•

Added Intel Core™ i7 processor i7-950

Added Intel Core™ i7 processor Extreme Edition i7-975

-003

-004

•

Added Intel Core™ i7-900 desktop processor i7-960

Added Intel Core™ i7-900 desktop processor i7-930

October 2009

February 2010

§

8

Datasheet

Introduction

1 Introduction

The Intel^®Core™ i7-900 desktop processor Extreme Edition series and Intel^®Core™

i7-900 desktop processor series are intended for high performance high-end desktop,

Uni-processor (UP) server, and workstation systems. Several architectural and

microarchitectural enhancements have been added to this processor including four

processor cores in the processor package and increased shared cache.

The Intel^®Core™ i7-900 desktop processor Extreme Edition series and Intel^®Core™

i7-900 desktop processor series are the first desktop multi-core processor to

implement key new technologies:

• Integrated memory controller

• Point-to-point link interface based on Intel QPI

Figure 1-1 shows the interfaces used with these new technologies.

Figure 1-1. High-Level View of Processor Interfaces

CH 0

System

CH 1

Processor

Memory

(DDR3)

CH 2

Intel^®QuickPath

Interconnect (Intel^®QPI)

Note:

In this document the Intel^®Core™ i7-900 desktop processor Extreme Edition series

and Intel^®Core™ i7-900 desktop processor series will be referred to as “the processor.”

The Intel Core™ i7-900 desktop processor series refers to the Intel Core™ i7-900

desktop processors i7-960, i7-950, i7-940, i7-930, and i7-920.

The Intel Core™ i7-900 desktop processor Extreme Edition series refers to the Intel

Core™ i7-900 desktop processor Extreme Edition i7-975 and i7-965.

The processor is optimized for performance with the power efficiencies of a low-power

microarchitecture.

This document provides DC electrical specifications, differential signaling specifications,

pinout and signal definitions, package mechanical specifications and thermal

requirements, and additional features pertinent to the implementation and operation of

the processor. For information on register descriptions, refer to the Intel^®Core™ i7-

900 Desktop Processor Extreme Edition Series and Intel^®Core™ i7-900 Desktop

Processor Series Datasheet, Volume 2.

Datasheet

9

Introduction

The processor is a multi-core processor built on the 45 nm process technology, that

uses up to 130 W thermal design power (TDP). The processor features an Intel QPI

point-to-point link capable of up to 6.4 GT/s, 8 MB Level 3 cache, and an integrated

memory controller.

The processor supports all the existing Streaming SIMD Extensions 2 (SSE2),

Streaming SIMD Extensions 3 (SSE3) and Streaming SIMD Extensions 4 (SSE4). The

processor supports several Advanced Technologies: Intel^®64 Technology (Intel^®64),

Enhanced Intel SpeedStep^®Technology, Intel^®Virtualization Technology (Intel^®VT),

Intel^®Turbo Boost Technology, and Intel^®Hyper-Threading Technology.

1.1

Terminology

A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in

the active state when driven to a low level. For example, when RESET# is low, a reset

has been requested. Conversely, when VTTPWRGOOD is high, the V_TTpower rail is

stable.

‘_N’ and ‘_P’ after a signal name refers to a differential pair.

Commonly used terms are explained here for clarification:

• Intel^®Core™ i7-900 Desktop Processor Extreme Edition Series and Intel^®

Core™ i7-900 Desktop Processor Series — The entire product, including

processor substrate and integrated heat spreader (IHS).

• 1366-land LGA package — The Intel Core™ i7-900 desktop processor Extreme

Edition series and Intel Core™ i7-900 desktop processor series are available in a

Flip-Chip Land Grid Array (FC-LGA) package, consisting of the processor mounted

on a land grid array substrate with an integrated heat spreader (IHS).

• LGA1366 Socket — The processor (in the LGA 1366 package) mates with the

system board through this surface mount, 1366-contact socket.

• DDR3 — Double Data Rate 3 Synchronous Dynamic Random Access Memory

(SDRAM) is the name of the new DDR memory standard that is being developed as

the successor to DDR2 SRDRAM.

• Intel^®QuickPath Interconnect (Intel QPI)— Intel QPI is a cache-coherent,

point-to-point link based electrical interconnect specification for Intel processors

and chipsets.

• Integrated Memory Controller — A memory controller that is integrated into the

processor die.

• Integrated Heat Spreader (IHS) — A component of the processor package used

to enhance the thermal performance of the package. Component thermal solutions

interface with the processor at the IHS surface.

• Functional Operation — Refers to the normal operating conditions in which all

processor specifications, including DC, AC, signal quality, mechanical, and thermal,

are satisfied.

• Enhanced Intel SpeedStep^®Technology — Enhanced Intel SpeedStep

Technology allows the operating system to reduce power consumption when

performance is not needed.

• Execute Disable Bit — Execute Disable allows memory to be marked as

executable or non-executable, when combined with a supporting operating system.

If code attempts to run in non-executable memory the processor raises an error to

the operating system. This feature can prevent some classes of viruses or worms

that exploit buffer overrun vulnerabilities and can thus help improve the overall

10

Datasheet

Introduction

security of the system. See the Intel^®Architecture Software Developer's Manual

for more detailed information. Refer to http://developer.intel.com/ for future

reference on up to date nomenclatures.

• Intel^®64 Architecture — An enhancement to Intel's IA-32 architecture, allowing

the processor to execute operating systems and applications written to take

advantage of Intel^®64. Further details on Intel^®64 architecture and programming

model can be found at http://developer.intel.com/technology/intel64/.

• Intel^®Virtualization Technology (Intel^®VT) — A set of hardware

enhancements to Intel server and client platforms that can improve virtualization

solutions. Intel^®VT provides a foundation for widely-deployed virtualization

solutions and enables a more robust hardware assisted virtualization solution. More

information can be found at: http://www.intel.com/technology/virtualization/

• Unit Interval (UI) — Signaling convention that is binary and unidirectional. In

this binary signaling, one bit is sent for every edge of the forwarded clock, whether

it is a rising edge or a falling edge. If a number of edges are collected at instances

t₁, t₂, t_n,...., t_kthen the UI at instance “n” is defined as:

UI _n= t _n– t

n – 1

• Jitter — Any timing variation of a transition edge or edges from the defined Unit

Interval.

• Storage Conditions — Refers to a non-operational state. The processor may be

installed in a platform, in a tray, or loose. Processors may be sealed in packaging or

exposed to free air. Under these conditions, processor lands should not be

connected to any supply voltages, have any I/Os biased, or receive any clocks.

• OEM — Original Equipment Manufacturer.

1.2

References

Material and concepts available in the following documents may be beneficial when

reading this document.

Table 1-1.

References

Document

Location

®

Intel Core™ i7-900 Desktop Processor Extreme Edition Series and Intel

Core™ i7-900 Desktop Processor Series Specification Update

http://download.intel.com/design/

processor/specupdt/320836.pdf

®

Intel Core™ i7-900 Desktop Processor Extreme Edition and Intel

http://download.intel.com/design/

processor/datashts/320835.pdf

Core™ i7-900 Desktop Processor Series Datasheet Volume 2

®

Intel Core™ i7-900 Desktop Processor Extreme Edition Series and Intel

http://download.intel.com/design/

processor/designex/320837.pdf

Core™ i7-900 Desktop Processor Series and LGA1366 Socket Thermal and

Mechanical Design Guide

Intel X58 Express Chipset Datasheet

http://www.intel.com/Assets/PDF/

datasheet/320838.pdf

®

AP-485, Intel Processor Identification and the CPUID Instruction

http://www.intel.com/design/proc

essor/applnots/241618.htm

®

IA-32 Intel Architecture Software Developer's Manual

•

Volume 1: Basic Architecture

Volume 2A: Instruction Set Reference, A-M

Volume 2B: Instruction Set Reference, N-Z

Volume 3A: System Programming Guide, Part 1

Volume 3B: Systems Programming Guide, Part 2

http://www.intel.com/products/pr

ocessor/manuals/

Datasheet

11

Introduction

§

12

Datasheet

Electrical Specifications

2 Electrical Specifications

2.1

Intel^®QPI Differential Signaling

The processor provides an Intel QPI port for high speed serial transfer between other

Intel QPI-enabled components. The Intel QPI port consists of two unidirectional links

(for transmit and receive). Intel QPI uses a differential signalling scheme where pairs of

opposite-polarity (D_P, D_N) signals are used.

On-die termination (ODT) is provided on the processor silicon and termination is to V_SS.

Intel chipsets also provide ODT; thus, eliminating the need to terminate the Intel QPI

links on the system board.

Intel strongly recommends performing analog simulations of the Intel^®QPI interface.

Figure 2-1 illustrates the active ODT. Signal listings are included in Table 2-3 and

Table 2-4. See Chapter 5 for the pin signal definitions. All Intel QPI signals are in the

differential signal group.

Figure 2-1. Active ODT for a Differential Link Example

T_X

R_X

Signal

R_TT

2.2

2.3

Power and Ground Lands

For clean on-chip processor core power distribution, the processor has 210 VCC pads

and 119 VSS pads associated with V_CC; 8 VTTA pads and 5 VSS pads associated with

V_TTA; 28 VTTD pads and 17 VSS pads associated with V_TTD, 28 VDDQ pads and 17 VSS

pads associated with V_DDQ; and 3 VCCPLL pads. All VCCP, VTTA, VTTD, VDDQ and

VCCPLL lands must be connected to their respective processor power planes, while all

VSS lands must be connected to the system ground plane. The processor VCC lands

must be supplied with the voltage determined by the processor Voltage IDentification

(VID) signals. Table 2-1 specifies the voltage level for the various VIDs.

Decoupling Guidelines

Due to its large number of transistors and high internal clock speeds, the processor is

capable of generating large current swings between low and full power states. This may

cause voltages on power planes to sag below their minimum values if bulk decoupling is

not adequate. Larger bulk storage (C_BULK), such as electrolytic capacitors, supply

current during longer lasting changes in current demand; such as, coming out of an idle

condition. Similarly, capacitors act as a storage well for current when entering an idle

condition from a running condition. Care must be taken in the baseboard design to

Datasheet

13

Electrical Specifications

ensure that the voltage provided to the processor remains within the specifications

listed in Table 2-7. Failure to do so can result in timing violations or reduced lifetime of

the processor.

2.3.1

V , V

, V

Decoupling

DDQ

CC

TTA

TTD

Voltage regulator solutions need to provide bulk capacitance and the baseboard

designer must assure a low interconnect resistance from the regulator to the LGA1366

socket. Bulk decoupling must be provided on the baseboard to handle large current

swings. The power delivery solution must insure the voltage and current specifications

are met (as defined in Table 2-7).

2.4

Processor Clocking (BCLK_DP, BCLK_DN)

The processor core, Intel QPI, and integrated memory controller frequencies are

generated from BCLK_DP and BCLK_DN. Unlike previous processors based on front side

bus architecture, there is no direct link between core frequency and Intel QPI link

frequency (such as, no core frequency to Intel QPI multiplier). The processor maximum

core frequency, Intel QPI link frequency and integrated memory controller frequency,

are set during manufacturing. It is possible to override the processor core frequency

setting using software. This permits operation at lower core frequencies than the

factory set maximum core frequency.

The processor’s maximum non-turbo core frequency is configured during power-on

reset by using values stored internally during manufacturing. The stored value sets the

highest core multiplier at which the particular processor can operate. If lower max non-

turbo speeds are desired, the appropriate ratio can be configured using the

CLOCK_FLEX_MAX MSR.

The processor uses differential clocks (BCLK_DP, BCLK_DN). Clock multiplying within

the processor is provided by the internal phase locked loop (PLL), which requires a

constant frequency BCLK_DP, BCLK_DN input, with exceptions for spread spectrum

clocking. The processor core frequency is determined by multiplying the ratio by

133 MHz.

2.4.1

PLL Power Supply

An on-die PLL filter solution is implemented on the processor. Refer to Table 2-7 for DC

specifications.

2.5

Voltage Identification (VID)

The voltage set by the VID signals is the reference voltage regulator output voltage to

be delivered to the processor VCC pins. VID signals are CMOS push/pull drivers. Refer

to Table 2-15 for the DC specifications for these signals. The VID codes will change due

to temperature and/or current load changes in order to minimize the power of the part.

A voltage range is provided in Table 2-7. The specifications have been set such that one

voltage regulator can operate with all supported frequencies.

Individual processor VID values may be set during manufacturing such that two devices

at the same core frequency may have different default VID settings. This is reflected by

the VID range values provided in Table 2-1.

14

Datasheet

Electrical Specifications

The processor uses eight voltage identification signals, VID[7:0], to support automatic

selection of voltages. Table 2-1 specifies the voltage level corresponding to the state of

VID[7:0]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers to a low

voltage level. If the processor socket is empty (VID[7:0] = 11111111), or the voltage

regulation circuit cannot supply the voltage that is requested, the voltage regulator

must disable itself.

The processor provides the ability to operate while transitioning to an adjacent VID and

its associated processor core voltage (V_CC). This will represent a DC shift in the

loadline. It should be noted that a low-to-high or high-to-low voltage state change will

result in as many VID transitions as necessary to reach the target core voltage.

Transitions above the maximum specified VID are not permitted. Table 2-8 includes VID

step sizes and DC shift ranges. Minimum and maximum voltages must be maintained

as shown in Table 2-8.

The VR used must be capable of regulating its output to the value defined by the new

VID. DC specifications for dynamic VID transitions are included in Table 2-7 and

Table 2-8

Table 2-1.

Voltage Identification Definition (Sheet 1 of 3)

VID VID VID VID VID VID VID VID

V_{CC_MAX}

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

OFF

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.04375

1.03750

1.03125

1.02500

1.01875

1.01250

1.00625

1.00000

0.99375

0.98750

0.98125

0.97500

0.96875

0.96250

0.95626

0.95000

0.94375

0.93750

0.93125

0.92500

0.91875

0.91250

0.90625

0.90000

0.89375

0.88750

0.88125

0.87500

0.86875

0.86250

0.85625

OFF

1.60000

1.59375

1.58750

1.58125

1.57500

1.56875

1.56250

1.55625

1.55000

1.54375

1.53750

1.53125

1.52500

1.51875

1.51250

1.50625

1.50000

1.49375

1.48750

1.48125

1.47500

1.46875

1.46250

1.45625

1.45000

1.44375

1.43750

1.43125

1.42500

Datasheet

15

Electrical Specifications

Table 2-1.

Voltage Identification Definition (Sheet 2 of 3)

VID VID VID VID VID VID VID VID

V_{CC_MAX}

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1.41875

1.41250

1.40625

1.40000

1.39375

1.38750

1.38125

1.37500

1.36875

1.36250

1.35625

1.35000

1.34375

1.33750

1.33125

1.32500

1.31875

1.31250

1.30625

1.30000

1.29375

1.28750

1.28125

1.27500

1.26875

1.26250

1.25625

1.25000

1.24375

1.23750

1.23125

1.22500

1.21875

1.21250

1.20625

1.20000

1.19375

1.18750

1.18125

1.17500

1.16875

1.16250

1.15625

1.15000

1.14375

1.13750

1.13125

1.12500

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.85000

0.84374

0.83750

0.83125

0.82500

0.81875

0.81250

0.80625

0.80000

0.79375

0.78750

0.78125

0.77500

0.76875

0.76250

0.75625

0.75000

0.74375

0.73750

0.73125

0.72500

0.71875

0.71250

0.70625

0.70000

0.69375

0.68750

0.68125

0.67500

0.66875

0.66250

0.65625

0.65000

0.64375

0.63750

0.63125

0.62500

0.61875

0.61250

0.60625

0.60000

0.59375

0.58750

0.58125

0.57500

0.56875

0.56250

0.55625

16

Datasheet

Electrical Specifications

Table 2-1.

Voltage Identification Definition (Sheet 3 of 3)

VID VID VID VID VID VID VID VID

V_{CC_MAX}

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1.11875

1.11250

1.10625

1.10000

1.09375

1.08750

1.08125

1.07500

1.06875

1.06250

1.05625

1.05000

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.55000

0.54375

0.53750

0.53125

0.52500

0.51875

0.51250

0.50625

0.50000

OFF

Table 2-2.

Market Segment Selection Truth Table for MS_ID[2:0]

1

MSID2

MSID1

MSID0

Description

0

1

0

1

0

1

0

1

0

1

0

1

0

Reserved

Intel Core™ i7-900 desktop processor Extreme Edition series and

Intel Core™ i7-900 desktop processor series

1

Reserved

Notes:

1. The MSID[2:0] signals are provided to indicate the Market Segment for the processor and may be used for

future processor compatibility or for keying.

2.6

Reserved or Unused Signals

All Reserved (RSVD) signals must remain unconnected. Connection of these signals to

V_CC, V_TTA, V_TTD, V_DDQ, V_CCPLL, V_SS, or to any other signal (including each other) can

result in component malfunction or incompatibility with future processors. See

Chapter 4 for a land listing of the processor and the location of all Reserved signals.

For reliable operation, always connect unused inputs or bi-directional signals to an

appropriate signal level, except for unused integrated memory controller inputs,

outputs, and bi-directional pins which may be left floating. Unused active high inputs

should be connected through a resistor to ground (V_SS). Unused outputs maybe left

unconnected; however, this may interfere with some Test Access Port (TAP) functions,

complicate debug probing, and prevent boundary scan testing. A resistor must be used

when tying bi-directional signals to power or ground. When tying any signal to power or

ground, a resistor will also allow for system testability.

Datasheet

17

Electrical Specifications

2.7

Signal Groups

Signals are grouped by buffer type and similar characteristics as listed in Table 2-3. The

buffer type indicates which signaling technology and specifications apply to the signals.

All the differential signals, and selected DDR3 and Control Sideband signals have On-

Die Termination (ODT) resistors. There are some signals that do not have ODT and

need to be terminated on the board. The signals that have ODT are listed in Table 2-4.

Table 2-3.

Signal Groups (Sheet 1 of 2)

1,2

Signal Group

Type

Signals

System Reference Clock

Differential

Clock Input

BCLK_DP, BCLK_DN

®

Intel QPI Signal Groups

Differential

Intel QPI Input

Intel QPI Output

QPI_DRX_D[N/P][19:0], QPI_CLKRX_DP,

QPI_CLKRX_DN

QPI_DTX_D[N/P][19:0], QPI_CLKTX_DP,

QPI_CLKTX_DN

DDR3 Reference Clocks

DDR3 Output

DDR{0/1/2}_CLK[D/P][3:0]

Differential

DDR3 Command Signals

Single ended

CMOS Output

DDR{0/1/2}_RAS#, DDR{0/1/2}_CAS#,

DDR{0/1/2}_WE#, DDR{0/1/2}_MA[15:0],

DDR{0/1/2}_BA[2:0]

Single ended

Asynchronous Output

CMOS Output

DDR{0/1/2}_RESET#

DDR3 Control Signals

Single ended

DDR{0/1/2}_CS#[5:4], DDR{0/1/2}_CS#[1:0],

DDR{0/1/2}_ODT[3:0], DDR{0/1/2}_CKE[3:0]

DDR3 Data Signals

Single ended

Differential

CMOS Bi-directional

DDR{0/1/2}_DQ[63:0]

DDR{0/1/2}_DQS_[N/P][7:0]

TAP

Single ended

TAP Input

TCK, TDI, TMS, TRST#

TDO

GTL Output

Control Sideband

Single ended

Single Ended

Single ended

Asynchronous GTL Output

Asynchronous GTL Input

GTL Bi-directional

PRDY#

PREQ#

CAT_ERR#, BPM#[7:0]

Asynchronous Bi-directional

Analog Input

PECI

COMP0, QPI_CMP[0], DDR_COMP[2:0]

PROCHOT#

Asynchronous GTL Bi-

directional

Single ended

Asynchronous GTL Output

CMOS Input/Output

THERMTRIP#

VID[7:6]

VID[5:3]/CSC[2:0]

VID[2:0]/MSID[2:0]

VTT_VID[4:2]

18

Datasheet

Electrical Specifications

Table 2-3.

Signal Groups (Sheet 2 of 2)

1,2

Signal Group

Single ended

Type

CMOS Output

Signals

VTT_VID[4:2]

ISENSE

Single ended

Analog Input

Reset Signal

Single ended

Reset Input

RESET#

PWRGOOD Signals

Single ended

Asynchronous Input

VCCPWRGOOD, VTTPWRGOOD, VDDPWRGOOD

Power/Other

Power

VCC, VTTA, VTTD, VCCPLL, VDDQ

PSI#

Asynchronous CMOS Output

Sense Points

VCC_SENSE, VSS_SENSE

SKTOCC#, DBR#

Other

Notes:

1.

2.

Refer to Chapter 5 for signal descriptions.

DDR{0/1/2} refers to DDR3 Channel 0, DDR3 Channel 1, and DDR3 Channel 2.

Table 2-4.

Signals with ODT

•

QPI_DRX_DP[19:0], QPI_DRX_DN[19:0], QPI_DTX_DP[19:0], QPI_DTX_DN[19:0], QPI_CLKRX_D[N/P],

QPI_CLKTX_D[N/P]

•

DDR{0/1/2}_DQ[63:0], DDR{0/1/2}_DQS_[N/P][7:0], DDR{0/1/2}_PAR_ERR#[0:2], VDDPWRGOOD

BCLK_ITP_D[N/P]

PECI

BPM#[7:0], PREQ#, TRST#, VCCPWRGOOD, VTTPWRGOOD

Notes:

1.

2.

3.

Unless otherwise specified, signals have ODT in the package with 50  pulldown to V

.

SS

PREQ#, BPM[7:0], TDI, TMS and BCLK_ITP_D[N/P] have ODT in package with 35  pullup to V

VCCPWRGOOD, VDDPWRGOOD, and VTTPWRGOOD have ODT in package with a 10 k to 20 k pulldown

to V

.

TT

.

SS

4.

5.

6.

7.

TRST# has ODT in package with a 1 k to 5 k pullup to V .

TT

All DDR signals are terminated to VDDQ/2

DDR{0/1/2} refers to DDR3 Channel 0, DDR3 Channel 1, and DDR3 Channel 2.

While TMS and TDI do not have On-Die Termination, these signals are weakly pulled up using a 1–5 k

resistor to V

TT

8.

While TCK does not have On-Die Termination, this signal is weakly pulled down using a 1–5 kresistor to

V

.

SS

All Control Sideband Asynchronous signals are required to be asserted/de-asserted for

at least eight BCLKs for the processor to recognize the proper signal state. See

Section 2.11 for the DC specifications. See Chapter 6 for additional timing

requirements for entering and leaving the low power states.

2.8

Test Access Port (TAP) Connection

Due to the voltage levels supported by other components in the Test Access Port (TAP)

logic, it is recommended that the processor be first in the TAP chain and followed by

any other components within the system. A translation buffer should be used to

connect to the rest of the chain unless one of the other components is capable of

accepting an input of the appropriate voltage. Two copies of each signal may be

required with each driving a different voltage level.

Datasheet

19

Electrical Specifications

2.9

Platform Environmental Control Interface (PECI)

DC Specifications

PECI is an Intel proprietary interface that provides a communication channel between

Intel processors and chipset components to external thermal monitoring devices. The

processor contains a Digital Thermal Sensor (DTS) that reports a relative die

temperature as an offset from Thermal Control Circuit (TCC) activation temperature.

Temperature sensors located throughout the die are implemented as analog-to-digital

converters calibrated at the factory. PECI provides an interface for external devices to

read the DTS temperature for thermal management and fan speed control. More

detailed information may be found in the Platform Environment Control Interface

(PECI) Specification.

2.9.1

DC Characteristics

The PECI interface operates at a nominal voltage set by V_TTD. The set of DC electrical

specifications shown in Table 2-5 is used with devices normally operating from a V_TTD

interface supply. V_TTDnominal levels will vary between processor families. All PECI

devices will operate at the V_TTDlevel determined by the processor installed in the

system. For specific nominal V_TTDlevels, refer to Table 2-7.

Table 2-5.

PECI DC Electrical Limits

1

Symbol

Definition and Conditions

Input Voltage Range

Min

Max

Units

Notes

V

-0.150

V

in

TTD

V

Hysteresis

0.1 * V

N/A

hysteresis

TTD

V

Negative-edge threshold voltage

Positive-edge threshold voltage

High level output source

0.275 * V

0.550 * V

0.500 * V

n

TTD

0.725 * V

p

I

-6.0

0.5

N/A

1.0

mA

µA

source

(V

= 0.75 * V

)

TTD

OH

Low level output sink

(V = 0.25 * V

I

sink

)

TTD

OL

High impedance state leakage to V

TTD

I

N/A

100

2

leak+

(V

= V

)

OL

leak

High impedance leakage to GND

(V = V

I

N/A

µA

pF

leak-

)

OH

leak

C

Bus capacitance per node

Signal noise immunity above 300 MHz

10

bus

V

0.1 * V

N/A

V

p-p

noise

TTD

Notes:

1.

2.

V

supplies the PECI interface. PECI behavior does not affect V

min/max specifications.

TTD

The leakage specification applies to powered devices on the PECI bus.

20

Datasheet

Electrical Specifications

2.9.2

Input Device Hysteresis

The input buffers in both client and host models must use a Schmitt-triggered input

design for improved noise immunity. Use Figure 2-2 as a guide for input buffer design.

Figure 2-2. Input Device Hysteresis

V_TTD

Maximum V_P

PECI High Range

Minimum V_P

Maximum V_N

Minimum

Hysteresis Signal Range

Valid Input

Minimum V_N

PECI Ground

PECI Low Range

2.10

Absolute Maximum and Minimum Ratings

Table 2-6 specifies absolute maximum and minimum ratings, which lie outside the

functional limits of the processor. Only within specified operation limits can functionality

and long-term reliability be expected.

At conditions outside functional operation condition limits, but within absolute

maximum and minimum ratings, neither functionality nor long-term reliability can be

expected. If a device is returned to conditions within functional operation limits after

having been subjected to conditions outside these limits, but within the absolute

maximum and minimum ratings, the device may be functional, but with its lifetime

degraded depending on exposure to conditions exceeding the functional operation

condition limits.

At conditions exceeding absolute maximum and minimum ratings, neither functionality

nor long-term reliability can be expected. Moreover, if a device is subjected to these

conditions for any length of time then, when returned to conditions within the

functional operating condition limits, it will either not function or its reliability will be

severely degraded.

Although the processor contains protective circuitry to resist damage from Electro-

Static Discharge (ESD), precautions should always be taken to avoid high static

voltages or electric fields.

Datasheet

21

Electrical Specifications

.

Table 2-6.

Processor Absolute Minimum and Maximum Ratings

1, 2

Symbol

Parameter

Min

Max

Unit Notes

V

Processor Core voltage with respect to V

-0.3

—

1.55

1.35

V

CC

SS

Voltage for the analog portion of the integrated

memory controller, QPI link and Shared Cache

V

3

V

TTA

with respect to V

SS

Voltage for the digital portion of the integrated

memory controller, QPI link and Shared Cache

—

1.35

V

TTD

with respect to V

SS

Processor I/O supply voltage for DDR3 with

respect to V

—

1.875

1.89

V

DDQ

SS

V

Processor PLL voltage with respect to V

Processor case temperature

1.65

V

CCPLL

SS

See

Chapter 6

See

Chapter 6

C

T

CASE

Storage temperature

See

Chapter 6

See

Chapter 6

C

T

STORAGE

Notes:

1.

For functional operation, all processor electrical, signal quality, mechanical and thermal specifications must

be satisfied.

2.

3.

Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor.

V

and V

should be derived from the same VR.

TTA

TTD

2.11

Processor DC Specifications

The processor DC specifications in this section are defined at the processor

pads, unless noted otherwise. See Chapter 4 for the processor land listings and

Chapter 5 for signal definitions. Voltage and current specifications are detailed in

Table 2-7. For platform planning, refer to Table 2-8, which provides V_CCstatic and

transient tolerances. This same information is presented graphically in Figure 2-3.

The DC specifications for the DDR3 signals are listed in Table 2-11. Control Sideband

and Test Access Port (TAP) are listed in Table 2-12 through Table 2-15.

Table 2-7 through Table 2-15 list the DC specifications for the processor and are valid

only while meeting specifications for case temperature (T_CASEas specified in Chapter 6,

“Thermal Specifications”), clock frequency, and input voltages. Care should be taken to

read all notes associated with each parameter.

22

Datasheet

Electrical Specifications

2.11.1

DC Voltage and Current Specification

Table 2-7.

Voltage and Current Specifications

1

Symbol

Parameter

Min

Typ

Max

Unit

Notes

2

VID

VID range

0.8

—

1.375

V

Processor

Number

V

for processor core

CC

i7-975

i7-965

i7-960

i7-950

i7-940

i7-930

i7-920

3.33 GHz

3.20 GHz

3.06 GHz

2.93 GHz

2.80 GHz

2.66 GHz

3,4

V

See Table 2-8 and Figure 2-3

V

CC

Voltage for the analog portion of the

integrated memory controller, QPI link

and Shared Cache

5

V

See Table 2-10 and Figure 2-4

See Table 2-9 and Figure 2-4

V

TTA

Voltage for the digital portion of the

integrated memory controller, QPI link

and Shared Cache

V

5

TTD

V

Processor I/O supply voltage for DDR3

1.425

1.71

1.5

1.8

1.575

1.89

V

DDQ

PLL supply voltage (DC + AC

specification)

V

CCPLL

Processor

Number

I

for processor

CC

i7-975

i7-965

i7-960

i7-950

i7-940

i7-930

i7-920

3.33 GHz

145

3.20 GHz

3.06 GHz

2.93 GHz

2.80 GHz

2.66 GHz

6

I

—

A

CC

Current for the analog portion of the

integrated memory controller, QPI link

and Shared Cache

I

—

5

A

TTA

Current for the digital portion of the

integrated memory controller, QPI link

and Shared Cache

I

23

TTD

I

Processor I/O supply current for DDR3

—

6

1

A

DDQ

Processor I/O supply current for DDR3

while in S3

7

I

S3

DDQ

I

PLL supply current (DC + AC specification)

1.1

CC_VCCPLL

Notes:

1.

Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical

data. These specifications will be updated with characterized data from silicon measurements at a later date

Each processor is programmed with a maximum valid voltage identification value (VID), which is set at

manufacturing and can not be altered. Individual maximum VID values are calibrated during manufacturing

such that two processors at the same frequency may have different settings within the VID range. Please

note this differs from the VID employed by the processor during a power management event (Adaptive

2.

®

Thermal Monitor, Enhanced Intel SpeedStep Technology, or Low Power States).

3.

The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the

socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 M minimum

impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external

noise from the system is not coupled into the oscilloscope probe.

4.

5.

Refer to Table 2-8 and Figure 2-3 for the minimum, typical, and maximum VCC allowed for a given current.

The processor should not be subjected to any V_CCand I_CCcombination wherein V_CCexceeds V_{CC_MAX}for

a given current.

See Table 2-9 for details on V Voltage Identification and Table 2-9 and Figure 2-4 for details on the V

TT

Loadline.

6. I_{CC_MAX}specification is based on the V_{CC_MAX}loadline. Refer to Figure 2-3 for details.

7.

This specification is based on a processor temperature, as reported by the DTS, of less than or equal to

–25.

T

CONTROL

Datasheet

23

Electrical Specifications

Table 2-8.

V_CCStatic and Transient Tolerance

I

(A)

V

(V)

V

(V)

V (V)

CC_Min

Notes

CC

CC_Max

CC_Typ

0

VID - 0.000

VID - 0.004

VID - 0.008

VID - 0.012

VID - 0.016

VID - 0.020

VID - 0.024

VID - 0.028

VID - 0.032

VID - 0.036

VID - 0.040

VID - 0.044

VID - 0.048

VID - 0.052

VID - 0.056

VID - 0.060

VID - 0.062

VID - 0.068

VID - 0.072

VID - 0.076

VID - 0.080

VID - 0.084

VID - 0.088

VID - 0.092

VID - 0.096

VID - 0.100

VID - 0.104

VID - 0.108

VID - 0.112

VID - 0.019

VID - 0.023

VID - 0.027

VID - 0.031

VID - 0.035

VID - 0.039

VID - 0.043

VID - 0.047

VID - 0.051

VID - 0.055

VID - 0.059

VID - 0.063

VID - 0.067

VID - 0.071

VID - 0.075

VID - 0.079

VID - 0.081

VID - 0.087

VID - 0.091

VID - 0.095

VID - 0.099

VID - 0.103

VID - 0.107

VID - 0.111

VID - 0.115

VID - 0.119

VID - 0.123

VID - 0.127

VID - 0.131

VID - 0.038

VID - 0.042

VID - 0.046

VID - 0.050

VID - 0.054

VID - 0.058

VID - 0.062

VID - 0.066

VID - 0.070

VID - 0.074

VID - 0.078

VID - 0.082

VID - 0.086

VID - 0.090

VID - 0.094

VID - 0.098

VID - 0.100

VID - 0.106

VID - 0.110

VID - 0.114

VID - 0.118

VID - 0.122

VID - 0.126

VID - 0.130

VID - 0.134

VID - 0.138

VID - 0.142

VID - 0.146

VID - 0.150

1, 2, 3

5

10

15

20

25

30

35

40

45

50

55

60

65

70

75

78

85

90

95

100

105

110

115

120

125

130

135

140

Notes:

1.

The V

and V

loadlines represent static and transient limits. See Section 2.11.2 for V

CC_MIN

CC_MAX CC

overshoot specifications.

This table is intended to aid in reading discrete points on Figure 2-3.

The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage

regulation feedback for voltage regulator circuits must also be taken from processor VCC_SENSE and

VSS_SENSE lands.

2.

3.

24

Datasheet

Electrical Specifications

Figure 2-3. V_CCStatic and Transient Tolerance Load Lines

Icc [A]

0

10

20

30

40

50

60

70

80

90

100

110

120

130

140

VID - 0.000

VID - 0.013

VID - 0.025

VID - 0.038

VID - 0.050

VID - 0.063

VID - 0.075

VID - 0.088

VID - 0.100

VID - 0.113

VID - 0.125

VID - 0.138

VID - 0.150

VID - 0.163

VID - 0.175

Vcc Maximum

Vcc Typical

V

c

V

Vcc Minimum

Table 2-9.

V_TTVoltage Identification (VID) Definition

VTT VR - VID Input

V

TT_Typ

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1.220 V

1.195 V

1.170 V

1.145 V

1.120 V

1.095 V

1.070 V

1.045 V

Note:

1.

This is a typical voltage, see Table 2-10 for VTT_Max and VTT_Min voltage.

Datasheet

25

Electrical Specifications

Table 2-10. V_TTStatic and Transient Tolerance

1

I

(A)

V

(V)

V

(V)

V (V)

TT_Min

Notes

TT

TT_Max

TT_Typ

0

VID + 0.0315

VID + 0.0255

VID + 0.0195

VID + 0.0135

VID + 0.0075

VID + 0.0015

VID – 0.0045

VID – 0.0105

VID – 0.0165

VID – 0.0225

VID – 0.0285

VID – 0.0345

VID – 0.0405

VID – 0.0465

VID – 0.0525

VID – 0.0585

VID – 0.0645

VID – 0.0705

VID – 0.0765

VID – 0.0825

VID – 0.0885

VID – 0.0945

VID – 0.1005

VID – 0.1065

VID – 0.1125

VID – 0.1185

VID – 0.1245

VID – 0.1305

VID – 0.1365

VID – 0.0000

VID – 0.0060

VID – 0.0120

VID – 0.0180

VID – 0.0240

VID – 0.0300

VID – 0.0360

VID – 0.0420

VID – 0.0480

VID – 0.0540

VID – 0.0600

VID – 0.0660

VID – 0.0720

VID – 0.0780

VID – 0.0840

VID – 0.0900

VID – 0.0960

VID – 0.1020

VID – 0.1080

VID – 0.1140

VID – 0.1200

VID – 0.1260

VID – 0.1320

VID – 0.1380

VID – 0.1440

VID – 0.1500

VID – 0.1560

VID – 0.1620

VID – 0.1680

VID – 0.0315

VID – 0.0375

VID – 0.0435

VID – 0.0495

VID – 0.0555

VID – 0.0615

VID – 0.0675

VID – 0.0735

VID – 0.0795

VID – 0.0855

VID – 0.0915

VID – 0.0975

VID – 0.1035

VID – 0.1095

VID – 0.1155

VID – 0.1215

VID – 0.1275

VID – 0.1335

VID – 0.1395

VID – 0.1455

VID – 0.1515

VID – 0.1575

VID – 0.1635

VID – 0.1695

VID – 0.1755

VID – 0.1815

VID – 0.1875

VID – 0.1935

VID – 0.1995

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

Notes:

1. The I listed in this table is a sum of I

and I .

TTD

TT

TTA

2. The loadlines specify voltage limits at the die measured at the VTT_SENSE and VSS_SENSE_VTT lands. Voltage

regulation feedback for voltage regulator circuits must also be taken from processor VTT_SENSE and

VSS_SENSE_VTT lands.

26

Datasheet

Electrical Specifications

Figure 2-4. V_TTStatic and Transient Tolerance Load Line

Itt [A] (sum of Itta and Ittd)

0

5

10

15

20

25

0.0500

0.0375

0.0250

0.0125

0.0000

-0.0125

-0.0250

-0.0375

-0.0500

-0.0625

-0.0750

-0.0875

-0.1000

-0.1125

-0.1250

-0.1375

-0.1500

-0.1625

-0.1750

-0.1875

-0.2000

-0.2125

V

t

Vtt Maximum

V

Vtt Typical

Vtt Minimum

Table 2-11. DDR3 Signal Group DC Specifications

1

Symbol

Parameter

Min

Typ

Max

Units

Notes

V

Input Low Voltage

Input High Voltage

Output Low Voltage

—

0.43*V

—

V

2,4

3

IL

DDQ

V

0.57*V

—

IH

DDQ

(V

/ 2)* (R

))

VTT_TERM

/

ON

DDQ

ON

V

—

V



OL

OH

ON

(R +R

Output High Voltage

V

– ((V

/ 2)*

DDQ

V

R

—

4

(R /(R +R ))

VTT_TERM

ON

DDR3 Clock Buffer On

Resistance

21

16

25

21

—

31

24

75

31

DDR3 Command Buffer

On Resistance

ON

DDR3 Reset Buffer On

Resistance

DDR3 Control Buffer On

Resistance

DDR3 Data Buffer On

Resistance

I

Input Leakage Current

COMP Resistance

N/A

99

N/A

100

24.9

130

± 1

101

mA



LI

5

DDR_COMP0

DDR_COMP1

DDR_COMP2

24.65

128.7

25.15



131.30



Notes:

1.

2.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low

V

IL

value.

is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high

3.

V

IH

value.

Datasheet

27

Electrical Specifications

4.

5.

V

and V

may experience excursions above V . However, input signal drivers must comply with the

DDQ

IH

OH

signal quality specifications.

COMP resistance must be provided on the system board with 1% resistors.

Table 2-12. RESET# Signal DC Specifications

1

Symbol

Parameter

Min

Typ

Max

Units

Notes

V

Input Low Voltage

Input High Voltage

Input Leakage Current

—

0.80 * V

—

0.40 * V

—

V

2

2,4

3

IL

IH

LI

TTA

V

TTA

I

± 200

A

Notes:

1.

2.

3.

4.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

The V

referred to in these specifications refers to instantaneous V

.

TTA

For Vin between 0 V and V . Measured when the driver is tristated.

TTA

V

and V

may experience excursions above V .

IH

O

H

T

Table 2-13. TAP Signal Group DC Specifications

1

Symbol

Parameter

Min

Typ

Max

Units

Notes

V

Input Low Voltage

Input High Voltage

Output Low Voltage

—

0.40

V

TTA

V

2

2,4

2

IL

IH

OL

*

V

0.75 * V

—

TTA

V

ON

* R

/

ON

)

sys_term

V

TTA

—

(R

+ R

V

Output High Voltage

Buffer on Resistance

Input Leakage Current

V

—

V



2,4

3

OH

TTA

Ron

10

—

18

I

± 200

A

LI

Notes:

1.

2.

3.

4.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

The V referred to in these specifications refers to instantaneous V

.

TTA

For Vin between 0 V and V . Measured when the driver is tristated.

TTA

V

and V

may experience excursions above V .

IH

OH TT

Table 2-14. PWRGOOD Signal Group DC Specifications

1

Symbol

Parameter

Min

Typ

Max

Units

Notes

Input Low Voltage for VCCPWRGOOD

and VTTPWRGOOD Signals

V

—

0.25 * V

0.29

—

V

2,5

IL

TTA

Input Low Voltage for VDDPWRGOOD

Signal

—

0.75 * V

0.87

—

V

6

IL

Input High Voltage for VCCPWRGOOD

and VTTPWRGOOD Signals

V

2,5

5

IH

TTA

Input High Voltage for VDDPWRGOOD

Signal

—

Ron

Buffer on Resistance

10

—

18



I

Input Leakage Current

± 200

A

4

LI

Notes:

1.

2.

3.

4.

5.

6.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

The V referred to in these specifications refers to instantaneous V

For Vin between 0 V and V . Measured when the driver is tristated.

.

TTA

V

and V

may experience excursions above V .

IH

OH TT

This specification applies to VCCPWRGOOD and VTTPWRGOOD

This specification applies to VDDPWRGOOD

28

Datasheet

Electrical Specifications

Table 2-15. Control Sideband Signal Group DC Specifications

1

Symbol

Parameter

Min

Typ

Max

Units

Notes

V

Input Low Voltage

Input High Voltage

Output Low Voltage

—

0.64

V

2

IL

*

TTA

V

0.76

V

TTA

—

IH

*

V

* R

sys_term

/ (R

ON

2,4

TTA

ON

V

—

OL

+ R

)

V

Output High Voltage

Buffer on Resistance

V

—

V



2,4

OH

TTA

Ron

10

18

—

Buffer on Resistance for

VID[7:0]

—

100

I

Input Leakage Current

COMP Resistance

—

± 200

50.40

A

3

5

LI

COMP0

49.4

49.9



Notes:

1.

2.

3.

4.

5.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

The V referred to in these specifications refers to instantaneous V

For Vin between 0 V and V . Measured when the driver is tristated.

.

TTA

V

and V

may experience excursions above V .

IH

OH TT

COMP resistance must be provided on the system board with 1% resistors.

2.11.2

V

Overshoot Specification

CC

The processor can tolerate short transient overshoot events where V_CCexceeds the VID

voltage when transitioning from a high-to-low current load condition. This overshoot

cannot exceed VID + V_{OS_MAX}(V_{OS_MAX}is the maximum allowable overshoot above

VID). These specifications apply to the processor die voltage as measured across the

VCC_SENSE and VSS_SENSE lands.

Table 2-16. V_CCOvershoot Specifications

Symbol

Parameter

overshoot above VID

CCP

Min

Max

Units

Figure

Notes

V

Magnitude of V

—

50

25

mV

µs

2-5

OS_MAX

T

Time duration of V

overshoot above VID

CCP

OS_MAX

Datasheet

29

Electrical Specifications

Figure 2-5. V_CCOvershoot Example Waveform

Example Overshoot Waveform

V_OS

VID + V_OS

VID

T_OS

Time

T_OS: Overshoot time above VID

V_OS: Overshoot above VID

2.11.3

Die Voltage Validation

Core voltage (V_CC) overshoot events at the processor must meet the specifications in

Table 2-16 when measured across the VCC_SENSE and VSS_SENSE lands. Overshoot

events that are < 10 ns in duration may be ignored. These measurements of processor

die level overshoot should be taken with a 100 MHz bandwidth limited oscilloscope.

§

30

Datasheet

Package Mechanical Specifications

3 Package Mechanical

Specifications

The processor is packaged in a Flip-Chip Land Grid Array package that interfaces with

the motherboard using an LGA1366 socket. The package consists of a processor

mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to

the package substrate and core and serves as the mating surface for processor thermal

solutions, such as a heatsink. Figure 3-1 shows a sketch of the processor package

components and how they are assembled together. Refer to the appropriate processor

Thermal and Mechanical Design Guidelines (see Section 1.2) for complete details on

the LGA1366 socket.

The package components shown in Figure 3-1 include the following:

• Integrated Heat Spreader (IHS)

• Thermal Interface Material (TIM)

• Processor core (die)

• Package substrate

• Capacitors

Figure 3-1. Processor Package Assembly Sketch

TIM

Die

IHS

Substrate

Capacitors

LGA1366 Socket

System Board

Note:

1.

Socket and motherboard are included for reference and are not part of the processor package.

3.1

Package Mechanical Drawing

The package mechanical drawings are shown in Figure 3-2 and Figure 3-3. The

drawings include dimensions necessary to design a thermal solution for the processor.

These dimensions include:

• Package reference with tolerances (total height, length, width, etc.)

• IHS parallelism and tilt

• Land dimensions

• Top-side and back-side component keep-out dimensions

• Reference datums

• All drawing dimensions are in mm.

• Guidelines on potential IHS flatness variation with socket load plate actuation and

installation of the cooling solution is available in the appropriate processor Thermal

and Mechanical Design Guidelines (see Section 1.2).

Datasheet

31

Package Mechanical Specifications

Figure 3-2. Processor Package Drawing (Sheet 1 of 2)

32

Datasheet

Package Mechanical Specifications

Figure 3-3. Processor Package Drawing (Sheet 2 of 2)

Datasheet

33

Package Mechanical Specifications

3.2

3.3

Processor Component Keep-Out Zones

The processor may contain components on the substrate that define component keep-

out zone requirements. A thermal and mechanical solution design must not intrude into

the required keep-out zones. Decoupling capacitors are typically mounted to either the

top-side or land-side of the package substrate. See Figure 3-2 and Figure 3-3 for keep-

out zones. The location and quantity of package capacitors may change due to

manufacturing efficiencies but will remain within the component keep-in.

Package Loading Specifications

Table 3-1 provides dynamic and static load specifications for the processor package.

These mechanical maximum load limits should not be exceeded during heatsink

assembly, shipping conditions, or standard use condition. Also, any mechanical system

or component testing should not exceed the maximum limits. The processor package

substrate should not be used as a mechanical reference or load-bearing surface for

thermal and mechanical solution.

.

Table 3-1.

Processor Loading Specifications

Parameter

Maximum

Notes

Static Compressive Load

934 N [210 lbf]

1, 2, 3

1, 3, 4

Dynamic Compressive Load

1834 N [410 lbf] [max static

compressive + dynamic load]

Notes:

1.

2.

These specifications apply to uniform compressive loading in a direction normal to the processor IHS.

This is the minimum and maximum static force that can be applied by the heatsink and retention solution

to maintain the heatsink and processor interface.

3.

4.

These specifications are based on limited testing for design characterization. Loading limits are for the

package only and do not include the limits of the processor socket.

Dynamic loading is defined as an 11 ms duration average load superimposed on the static load

requirement.

3.4

Package Handling Guidelines

Table 3-2 includes a list of guidelines on package handling in terms of recommended

maximum loading on the processor IHS relative to a fixed substrate. These package

handling loads may be experienced during heatsink removal.

Table 3-2.

Package Handling Guidelines

Parameter

Maximum Recommended

Notes

Shear

Tensile

Torque

70 lbs

25 lbs

—

35 in.lbs

3.5

Package Insertion Specifications

The processor can be inserted into and removed from an LGA1366 socket 15 times. The

socket should meet the LGA1366 requirements detailed in the appropriate processor

Thermal and Mechanical Design Guidelines (see Section 1.2)

34

Datasheet

Package Mechanical Specifications

3.6

Processor Mass Specification

The typical mass of the processor is 35g. This mass [weight] includes all the

components that are included in the package.

3.7

Processor Materials

Table 3-3 lists some of the package components and associated materials.

Table 3-3.

Processor Materials

Component

Material

Integrated Heat Spreader (IHS)

Substrate

Nickel Plated Copper

Fiber Reinforced Resin

Gold Plated Copper

Substrate Lands

3.8

Processor Markings

Figure 3-4 shows the top-side markings on the processor. This diagram is to aid in the

identification of the processor.

Figure 3-4. Processor Top-side Markings

M

INTEL ©'07 PROC#

BRAND

SLxxx [COO]

SPEED/CACHE/INTC/FMB

e4

[FPO]

Datasheet

35

Package Mechanical Specifications

3.9

Processor Land Coordinates

Figure 3-5 shows the top view of the processor land coordinates. The coordinates are

referred to throughout the document to identify processor lands.

Figure 3-5. Processor Land Coordinates and Quadrants (Bottom View)

§

36

Datasheet

Land Listing

4 Land Listing

This section provides sorted land lists in Table 4-1 and Table 4-2. Table 4-1 is a listing

of all processor lands ordered alphabetically by land name. Table 4-2 is a listing of all

processor lands ordered by land number.

Table 4-1. Land Listing by Land Name

(Sheet 2 of 29)

Table 4-1. Land Listing by Land Name

(Sheet 1 of 29)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

DDR0_CS#[5]

A7

CMOS

O

BCLK_DN

AH35

AJ35

AA4

AA5

B3

CMOS

GTL

I

DDR0_DQ[0]

DDR0_DQ[1]

DDR0_DQ[10]

DDR0_DQ[11]

DDR0_DQ[12]

DDR0_DQ[13]

DDR0_DQ[14]

DDR0_DQ[15]

DDR0_DQ[16]

DDR0_DQ[17]

DDR0_DQ[18]

DDR0_DQ[19]

DDR0_DQ[2]

DDR0_DQ[20]

DDR0_DQ[21]

DDR0_DQ[22]

DDR0_DQ[23]

DDR0_DQ[24]

DDR0_DQ[25]

DDR0_DQ[26]

DDR0_DQ[27]

DDR0_DQ[28]

DDR0_DQ[29]

DDR0_DQ[3]

DDR0_DQ[30]

DDR0_DQ[31]

DDR0_DQ[32]

DDR0_DQ[33]

DDR0_DQ[34]

DDR0_DQ[35]

DDR0_DQ[36]

DDR0_DQ[37]

DDR0_DQ[38]

DDR0_DQ[39]

DDR0_DQ[4]

DDR0_DQ[40]

DDR0_DQ[41]

DDR0_DQ[42]

W41

V41

K42

K43

P42

P41

L43

L42

H41

H43

E42

E43

R43

J42

J41

F43

F42

D40

C41

A38

D37

D41

D42

R42

C38

B38

B5

I/O

BCLK_DP

I

BCLK_ITP_DN

BCLK_ITP_DP

BPM#[0]

O

I/O

BPM#[1]

A5

GTL

BPM#[2]

C2

GTL

BPM#[3]

B4

GTL

BPM#[4]

D1

GTL

BPM#[5]

C3

GTL

BPM#[6]

D2

GTL

BPM#[7]

E2

GTL

CAT_ERR#

AC37

AB41

AF10

AA8

Y7

GTL

COMP0

Analog

Asynch

Analog

CMOS

CLOCK

CMOS

DBR#

I

DDR_COMP[0]

DDR_COMP[1]

DDR_COMP[2]

DDR_VREF

AC1

L23

B16

A16

C28

C12

C29

A30

B30

B31

K19

C19

E18

E19

J19

D19

F18

E20

G15

B10

B15

I

DDR0_BA[0]

DDR0_BA[1]

DDR0_BA[2]

DDR0_CAS#

DDR0_CKE[0]

DDR0_CKE[1]

DDR0_CKE[2]

DDR0_CKE[3]

DDR0_CLK_N[0]

DDR0_CLK_N[1]

DDR0_CLK_N[2]

DDR0_CLK_N[3]

DDR0_CLK_P[0]

DDR0_CLK_P[1]

DDR0_CLK_P[2]

DDR0_CLK_P[3]

DDR0_CS#[0]

DDR0_CS#[1]

DDR0_CS#[4]

O

C4

F1

G3

B6

C6

F3

F2

W40

H2

H1

L1

Datasheet

37

Land Listing

Table 4-1. Land Listing by Land Name

(Sheet 3 of 29)

Table 4-1. Land Listing by Land Name

(Sheet 4 of 29)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

DDR0_DQ[43]

M1

CMOS

I/O

O

DDR0_MA[14]

DDR0_MA[15]

DDR0_MA[2]

DDR0_MA[3]

DDR0_MA[4]

DDR0_MA[5]

DDR0_MA[6]

DDR0_MA[7]

DDR0_MA[8]

DDR0_MA[9]

DDR0_ODT[0]

DDR0_ODT[1]

DDR0_ODT[2]

DDR0_ODT[3]

DDR0_RAS#

A28

CMOS

CLOCK

CMOS

O

DDR0_DQ[44]

DDR0_DQ[45]

DDR0_DQ[46]

DDR0_DQ[47]

DDR0_DQ[48]

DDR0_DQ[49]

DDR0_DQ[5]

G1

B29

C23

D24

B23

B24

C24

A25

B25

C26

F12

C9

O

H3

O

L3

O

L2

O

N1

O

N2

O

W42

T1

O

DDR0_DQ[50]

DDR0_DQ[51]

DDR0_DQ[52]

DDR0_DQ[53]

DDR0_DQ[54]

DDR0_DQ[55]

DDR0_DQ[56]

DDR0_DQ[57]

DDR0_DQ[58]

DDR0_DQ[59]

DDR0_DQ[6]

O

T2

O

M3

N3

O

R4

B11

C7

O

T3

O

U4

A15

D32

B13

C18

K13

H27

E14

H28

E27

D27

C27

D21

G20

L18

H19

C21

G19

K18

H18

D12

A8

O

V1

DDR0_RESET#

DDR0_WE#

O

Y2

O

Y3

DDR1_BA[0]

O

U41

U1

DDR1_BA[1]

O

DDR0_DQ[60]

DDR0_DQ[61]

DDR0_DQ[62]

DDR0_DQ[63]

DDR0_DQ[7]

DDR1_BA[2]

O

U3

DDR1_CAS#

O

V4

DDR1_CKE[0]

DDR1_CKE[1]

DDR1_CKE[2]

DDR1_CKE[3]

DDR1_CLK_N[0]

DDR1_CLK_N[1]

DDR1_CLK_N[2]

DDR1_CLK_N[3]

DDR1_CLK_P[0]

DDR1_CLK_P[1]

DDR1_CLK_P[2]

DDR1_CLK_P[3]

DDR1_CS#[0]

DDR1_CS#[1]

DDR1_CS#[4]

DDR1_CS#[5]

DDR1_DQ[0]

DDR1_DQ[1]

DDR1_DQ[10]

DDR1_DQ[11]

DDR1_DQ[12]

DDR1_DQ[13]

DDR1_DQ[14]

DDR1_DQ[15]

DDR1_DQ[16]

DDR1_DQ[17]

DDR1_DQ[18]

O

W4

T42

N41

N43

U43

M41

G41

B40

E4

O

DDR0_DQ[8]

O

DDR0_DQ[9]

O

DDR0_DQS_N[0]

DDR0_DQS_N[1]

DDR0_DQS_N[2]

DDR0_DQS_N[3]

DDR0_DQS_N[4]

DDR0_DQS_N[5]

DDR0_DQS_N[6]

DDR0_DQS_N[7]

DDR0_DQS_P[0]

DDR0_DQS_P[1]

DDR0_DQS_P[2]

DDR0_DQS_P[3]

DDR0_DQS_P[4]

DDR0_DQS_P[5]

DDR0_DQS_P[6]

DDR0_DQS_P[7]

DDR0_MA[0]

O

K3

O

R3

O

W1

T43

L41

F41

B39

E3

O

C17

E10

AA37

AA36

P39

N39

R34

R35

N37

N38

M35

M34

K35

O

I/O

K2

R2

W2

A20

B21

B19

A26

B26

A10

DDR0_MA[1]

O

DDR0_MA[10]

DDR0_MA[11]

DDR0_MA[12]

DDR0_MA[13]

O

38

Datasheet

Land Listing

Table 4-1. Land Listing by Land Name

(Sheet 5 of 29)

Table 4-1. Land Listing by Land Name

(Sheet 6 of 29)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

DDR1_DQ[19]

J35

CMOS

I/O

DDR1_DQ[62]

AA7

CMOS

I/O

O

DDR1_DQ[2]

DDR1_DQ[20]

DDR1_DQ[21]

DDR1_DQ[22]

DDR1_DQ[23]

DDR1_DQ[24]

DDR1_DQ[25]

DDR1_DQ[26]

DDR1_DQ[27]

DDR1_DQ[28]

DDR1_DQ[29]

DDR1_DQ[3]

DDR1_DQ[30]

DDR1_DQ[31]

DDR1_DQ[32]

DDR1_DQ[33]

DDR1_DQ[34]

DDR1_DQ[35]

DDR1_DQ[36]

DDR1_DQ[37]

DDR1_DQ[38]

DDR1_DQ[39]

DDR1_DQ[4]

DDR1_DQ[40]

DDR1_DQ[41]

DDR1_DQ[42]

DDR1_DQ[43]

DDR1_DQ[44]

DDR1_DQ[45]

DDR1_DQ[46]

DDR1_DQ[47]

DDR1_DQ[48]

DDR1_DQ[49]

DDR1_DQ[5]

DDR1_DQ[50]

DDR1_DQ[51]

DDR1_DQ[52]

DDR1_DQ[53]

DDR1_DQ[54]

DDR1_DQ[55]

DDR1_DQ[56]

DDR1_DQ[57]

DDR1_DQ[58]

DDR1_DQ[59]

DDR1_DQ[6]

DDR1_DQ[60]

DDR1_DQ[61]

Y35

N34

M36

J36

H36

H33

L33

K32

J32

J34

H34

Y34

L32

K30

E9

DDR1_DQ[63]

DDR1_DQ[7]

W9

Y39

P34

P35

Y37

R37

L36

L31

D7

DDR1_DQ[8]

DDR1_DQ[9]

DDR1_DQS_N[0]

DDR1_DQS_N[1]

DDR1_DQS_N[2]

DDR1_DQS_N[3]

DDR1_DQS_N[4]

DDR1_DQS_N[5]

DDR1_DQS_N[6]

DDR1_DQS_N[7]

DDR1_DQS_P[0]

DDR1_DQS_P[1]

DDR1_DQS_P[2]

DDR1_DQS_P[3]

DDR1_DQS_P[4]

DDR1_DQS_P[5]

DDR1_DQS_P[6]

DDR1_DQS_P[7]

DDR1_MA[0]

G6

L5

Y9

Y38

R38

L35

L30

E7

E8

E5

F5

H6

F10

G8

L6

Y8

D6

J14

J16

H14

E23

E24

B14

H26

F26

J17

L28

K28

F22

J27

D22

E22

G24

D11

C8

F6

DDR1_MA[1]

O

AA35

H8

DDR1_MA[10]

DDR1_MA[11]

DDR1_MA[12]

DDR1_MA[13]

DDR1_MA[14]

DDR1_MA[15]

DDR1_MA[2]

O

J6

O

G4

O

H4

O

G9

O

H9

O

G5

DDR1_MA[3]

O

J5

DDR1_MA[4]

O

K4

DDR1_MA[5]

O

K5

DDR1_MA[6]

O

AB36

R5

DDR1_MA[7]

O

DDR1_MA[8]

O

T5

DDR1_MA[9]

O

J4

DDR1_ODT[0]

DDR1_ODT[1]

DDR1_ODT[2]

DDR1_ODT[3]

DDR1_RAS#

O

M6

R8

O

D14

F11

G14

D29

G13

A17

F17

L26

F16

O

R7

O

W6

W7

Y10

W10

Y40

V9

O

DDR1_RESET#

DDR1_WE#

O

DDR2_BA[0]

O

DDR2_BA[1]

O

DDR2_BA[2]

O

W5

DDR2_CAS#

O

Datasheet

39

Land Listing

Table 4-1. Land Listing by Land Name

(Sheet 7 of 29)

Table 4-1. Land Listing by Land Name

(Sheet 8 of 29)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

DDR2_CKE[0]

J26

CMOS

CLOCK

CMOS

O

DDR2_DQ[38]

DDR2_DQ[39]

DDR2_DQ[4]

H12

CMOS

I/O

DDR2_CKE[1]

DDR2_CKE[2]

DDR2_CKE[3]

DDR2_CLK_N[0]

DDR2_CLK_N[1]

DDR2_CLK_N[2]

DDR2_CLK_N[3]

DDR2_CLK_P[0]

DDR2_CLK_P[1]

DDR2_CLK_P[2]

DDR2_CLK_P[3]

DDR2_CS#[0]

DDR2_CS#[1]

DDR2_CS#[4]

DDR2_CS#[5]

DDR2_DQ[0]

G26

D26

L27

J21

O

L12

U34

L10

K10

M9

O

DDR2_DQ[40]

DDR2_DQ[41]

DDR2_DQ[42]

DDR2_DQ[43]

DDR2_DQ[44]

DDR2_DQ[45]

DDR2_DQ[46]

DDR2_DQ[47]

DDR2_DQ[48]

DDR2_DQ[49]

DDR2_DQ[5]

O

K20

G21

L21

J22

O

N9

O

L11

M10

L8

O

L20

H21

L22

G16

K14

E17

D9

O

M8

O

P7

O

N6

O

V34

P9

O

DDR2_DQ[50]

DDR2_DQ[51]

DDR2_DQ[52]

DDR2_DQ[53]

DDR2_DQ[54]

DDR2_DQ[55]

DDR2_DQ[56]

DDR2_DQ[57]

DDR2_DQ[58]

DDR2_DQ[59]

DDR2_DQ[6]

O

P10

N8

W34

W35

R39

T36

W39

V39

T41

R40

M39

M40

J40

I/O

DDR2_DQ[1]

N7

DDR2_DQ[10]

DDR2_DQ[11]

DDR2_DQ[12]

DDR2_DQ[13]

DDR2_DQ[14]

DDR2_DQ[15]

DDR2_DQ[16]

DDR2_DQ[17]

DDR2_DQ[18]

DDR2_DQ[19]

DDR2_DQ[2]

R10

R9

U5

U6

T10

U10

V37

T6

DDR2_DQ[60]

DDR2_DQ[61]

DDR2_DQ[62]

DDR2_DQ[63]

DDR2_DQ[7]

T7

J39

V8

V36

P40

N36

L40

K38

G40

F40

J37

U9

DDR2_DQ[20]

DDR2_DQ[21]

DDR2_DQ[22]

DDR2_DQ[23]

DDR2_DQ[24]

DDR2_DQ[25]

DDR2_DQ[26]

DDR2_DQ[27]

DDR2_DQ[28]

DDR2_DQ[29]

DDR2_DQ[3]

V38

U38

U39

W36

T38

K39

E40

J9

DDR2_DQ[8]

DDR2_DQ[9]

DDR2_DQS_N[0]

DDR2_DQS_N[1]

DDR2_DQS_N[2]

DDR2_DQS_N[3]

DDR2_DQS_N[4]

DDR2_DQS_N[5]

DDR2_DQS_N[6]

DDR2_DQS_N[7]

DDR2_DQS_P[0]

DDR2_DQS_P[1]

DDR2_DQS_P[2]

DDR2_DQS_P[3]

DDR2_DQS_P[4]

DDR2_DQS_P[5]

DDR2_DQS_P[6]

DDR2_DQS_P[7]

H37

H39

G39

U36

F38

E38

K12

J12

K7

P5

T8

DDR2_DQ[30]

DDR2_DQ[31]

DDR2_DQ[32]

DDR2_DQ[33]

DDR2_DQ[34]

DDR2_DQ[35]

DDR2_DQ[36]

DDR2_DQ[37]

W37

T37

K40

E39

J10

L7

H13

L13

G11

G10

P6

U8

40

Datasheet

Land Listing

Table 4-1. Land Listing by Land Name

(Sheet 9 of 29)

Table 4-1. Land Listing by Land Name

(Sheet 10 of 29)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

DDR2_MA[0]

A18

CMOS

O

QPI_DRX_DN[3]

QPI_DRX_DN[4]

QPI_DRX_DN[5]

QPI_DRX_DN[6]

QPI_DRX_DN[7]

QPI_DRX_DN[8]

QPI_DRX_DN[9]

QPI_DRX_DP[0]

QPI_DRX_DP[1]

QPI_DRX_DP[10]

QPI_DRX_DP[11]

QPI_DRX_DP[12]

QPI_DRX_DP[13]

QPI_DRX_DP[14]

QPI_DRX_DP[15]

QPI_DRX_DP[16]

QPI_DRX_DP[17]

QPI_DRX_DP[18]

QPI_DRX_DP[19]

QPI_DRX_DP[2]

QPI_DRX_DP[3]

QPI_DRX_DP[4]

QPI_DRX_DP[5]

QPI_DRX_DP[6]

QPI_DRX_DP[7]

QPI_DRX_DP[8]

QPI_DRX_DP[9]

QPI_DTX_DN[0]

QPI_DTX_DN[1]

QPI_DTX_DN[10]

QPI_DTX_DN[11]

QPI_DTX_DN[12]

QPI_DTX_DN[13]

QPI_DTX_DN[14]

QPI_DTX_DN[15]

QPI_DTX_DN[16]

QPI_DTX_DN[17]

QPI_DTX_DN[18]

QPI_DTX_DN[19]

QPI_DTX_DN[2]

QPI_DTX_DN[3]

QPI_DTX_DN[4]

QPI_DTX_DN[5]

QPI_DTX_DN[6]

QPI_DTX_DN[7]

QPI_DTX_DN[8]

QPI_DTX_DN[9]

QPI_DTX_DP[0]

AY36

BA37

AW38

AY38

AT39

AV40

AU41

AT37

AU38

AU42

AT43

AT40

AP42

AN43

AN40

AM42

AP41

AN39

AP38

AV36

AW36

BA36

AW37

BA38

AU39

AW40

AU40

AH38

AG39

AE43

AE41

AC42

AB43

AD39

AC40

AC38

AB38

AE38

AF40

AK38

AJ39

AJ40

AK41

AH42

AJ42

AH43

AG41

AG38

QPI

I

DDR2_MA[1]

DDR2_MA[10]

DDR2_MA[11]

DDR2_MA[12]

DDR2_MA[13]

DDR2_MA[14]

DDR2_MA[15]

DDR2_MA[2]

DDR2_MA[3]

DDR2_MA[4]

DDR2_MA[5]

DDR2_MA[6]

DDR2_MA[7]

DDR2_MA[8]

DDR2_MA[9]

DDR2_ODT[0]

DDR2_ODT[1]

DDR2_ODT[2]

DDR2_ODT[3]

DDR2_RAS#

DDR2_RESET#

DDR2_WE#

K17

I

H17

I

H23

I

G23

F15

I

H24

I

G25

G18

J20

I

F20

I

K23

I

K22

I

J24

I

L25

I

H22

I

L16

I

F13

I

D15

I

D10

I

D17

I

E32

I

C16

I

FC_AH5

AH5

AK8

I

ISENSE

Analog

I

PECI

AH36

B41

Asynch I/O

I

PRDY#

GTL

CMOS

QPI

Analog

QPI

O

I

PREQ#

C42

O

PROCHOT#

AG35

AP7

I/O

O

I

PSI#

QPI_CLKRX_DN

QPI_CLKRX_DP

QPI_CLKTX_DN

QPI_CLKTX_DP

QPI_CMP[0]

AR42

AR41

AF42

AG42

AL43

AU37

AV38

AT42

AR43

AR40

AN42

AM43

AM40

AM41

AP40

AP39

AR38

AV37

I

O

QPI_DRX_DN[0]

QPI_DRX_DN[1]

QPI_DRX_DN[10]

QPI_DRX_DN[11]

QPI_DRX_DN[12]

QPI_DRX_DN[13]

QPI_DRX_DN[14]

QPI_DRX_DN[15]

QPI_DRX_DN[16]

QPI_DRX_DN[17]

QPI_DRX_DN[18]

QPI_DRX_DN[19]

QPI_DRX_DN[2]

I

Datasheet

41

Land Listing

Table 4-1. Land Listing by Land Name

(Sheet 11 of 29)

Table 4-1. Land Listing by Land Name

(Sheet 12 of 29)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

QPI_DTX_DP[1]

QPI_DTX_DP[10]

QPI_DTX_DP[11]

QPI_DTX_DP[12]

QPI_DTX_DP[13]

QPI_DTX_DP[14]

QPI_DTX_DP[15]

QPI_DTX_DP[16]

QPI_DTX_DP[17]

QPI_DTX_DP[18]

QPI_DTX_DP[19]

QPI_DTX_DP[2]

QPI_DTX_DP[3]

QPI_DTX_DP[4]

QPI_DTX_DP[5]

QPI_DTX_DP[6]

QPI_DTX_DP[7]

QPI_DTX_DP[8]

QPI_DTX_DP[9]

RESET#

AF39

AF43

AE42

AD42

AC43

AD40

AC41

AC39

AB39

AD38

AE40

AK37

AJ38

AH40

AK40

AH41

AK42

AJ43

AG40

AL39

D35

D34

C36

QPI

Asynch

O

I

RSVD

F31

F30

AB5

C13

B9

C11

B8

M43

G43

C39

D4

J1

P1

V3

B35

V42

N42

H42

D39

D5

RSVD

J2

RSVD

P2

RSVD

V2

RSVD

A36

B36

V43

B20

D25

B28

A27

E15

E13

C14

E12

P37

E35

K37

K33

F7

RSVD

F32

RSVD

C33

RSVD

C37

RSVD

A37

RSVD

B34

RSVD

C34

RSVD

G34

G33

D36

F36

RSVD

E33

RSVD

G36

E37

RSVD

F37

RSVD

E34

J7

RSVD

G35

G30

G29

H32

M4

RSVD

Y5

RSVD

AA41

P36

L37

K34

F8

RSVD

F33

RSVD

E29

RSVD

E30

RSVD

J31

H7

RSVD

J30

M5

42

Datasheet

Land Listing

Table 4-1. Land Listing by Land Name

(Sheet 13 of 29)

Table 4-1. Land Listing by Land Name

(Sheet 14 of 29)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

RSVD

Y4

RSVD

AD8

F35

AA40

D20

C22

E25

F25

D16

H16

L17

J15

T40

L38

G38

J11

K8

AE1

AE3

AE4

AE5

AE6

AF1

AF2

AF3

AF4

AF6

AG1

AG2

AG4

AG5

AG6

AG7

AG8

AH2

AH3

AH4

AH6

AH8

AJ1

P4

V7

G31

T35

U40

M38

H38

H11

K9

AJ2

N4

AJ3

V6

AJ37

AJ4

H31

U35

B18

F21

J25

F23

A31

A40

AB3

AB6

AC3

AC4

AC6

AC8

AD1

AD2

AD3

AD4

AD5

AD6

AD7

AJ6

AJ7

AJ8

AK1

AK2

AK35

AK36

AK4

AK5

AK6

AL3

AL38

AL4

AL40

AL41

AL5

AL6

AL8

AM1

AM2

Datasheet

43

Land Listing

Table 4-1. Land Listing by Land Name

(Sheet 15 of 29)

Table 4-1. Land Listing by Land Name

(Sheet 16 of 29)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

RSVD

AM3

AM36

AM38

AM4

AM6

AM7

AM8

AN1

AN2

AN36

AN38

AN4

AN5

AN6

AP2

RSVD

AW41

AW42

AW5

AW7

AY3

AY35

AY39

AY4

AY40

AY41

AY5

AY6

AY8

B33

BA4

BA40

BA6

BA7

BA8

C31

AP3

AP4

AR1

AR36

AR37

AR4

AR5

AR6

AT1

C32

D30

D31

E28

AT2

F27

AT3

F28

AT36

AT4

G28

H29

J29

AT5

AT6

K15

AU2

AU3

AU4

AU6

AU7

AU8

AV1

K24

K25

K27

K29

L15

U11

V11

AV2

AK7

AG36

AH10

AJ9

AV35

AV42

AV43

AV5

SKTOCC#

TCK

GTL

O

I

TAP

GTL

TAP

PWR

TDI

I

TDO

AJ10

AG37

AG10

AH9

AH11

AH33

AJ11

O

I

AV7

THERMTRIP#

TMS

AV8

AW2

AW3

AW39

AW4

TRST#

VCC

I

VCC

44

Datasheet

Land Listing

Table 4-1. Land Listing by Land Name

(Sheet 17 of 29)

Table 4-1. Land Listing by Land Name

(Sheet 18 of 29)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

VCC

AJ33

AK11

AK12

AK13

AK15

AK16

AK18

AK19

AK21

AK24

AK25

AK27

AK28

AK30

AK31

AK33

AL12

AL13

AL15

AL16

AL18

AL19

AL21

AL24

AL25

AL27

AL28

AL30

AL31

AL33

AL34

AM12

AM13

AM15

AM16

AM18

AM19

AM21

AM24

AM25

AM27

AM28

AM30

AM31

AM33

AM34

AN12

AN13

PWR

VCC

AN15

AN16

AN18

AN19

AN21

AN24

AN25

AN27

AN28

AN30

AN31

AN33

AN34

AP12

AP13

AP15

AP16

AP18

AP19

AP21

AP24

AP25

AP27

AP28

AP30

AP31

AP33

AP34

AR10

AR12

AR13

AR15

AR16

AR18

AR19

AR21

AR24

AR25

AR27

AR28

AR30

AR31

AR33

AR34

AT10

AT12

AT13

AT15

PWR

Datasheet

45

Land Listing

Table 4-1. Land Listing by Land Name

(Sheet 19 of 29)

Table 4-1. Land Listing by Land Name

(Sheet 20 of 29)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

VCC

AT16

AT18

AT19

AT21

AT24

AT25

AT27

AT28

AT30

AT31

AT33

AT34

AT9

PWR

VCC

AW12

AW13

AW15

AW16

AW18

AW19

AW21

AW24

AW25

AW27

AW28

AW30

AW31

AW33

AW34

AW9

PWR

AU10

AU12

AU13

AU15

AU16

AU18

AU19

AU21

AU24

AU25

AU27

AU28

AU30

AU31

AU33

AU34

AU9

AY10

AY12

AY13

AY15

AY16

AY18

AY19

AY21

AY24

AY25

AY27

AY28

AY30

AY31

AY33

AY34

AY9

AV10

AV12

AV13

AV15

AV16

AV18

AV19

AV21

AV24

AV25

AV27

AV28

AV30

AV31

AV33

AV34

AV9

BA10

BA12

BA13

BA15

BA16

BA18

BA19

BA24

BA25

BA27

BA28

BA30

BA9

M11

AW10

M13

46

Datasheet

Land Listing

Table 4-1. Land Listing by Land Name

(Sheet 21 of 29)

Table 4-1. Land Listing by Land Name

(Sheet 22 of 29)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

VCC

M15

PWR

Analog

PWR

Asynch

PWR

VDDQ

F24

PWR

CMOS

GND

M19

M21

M23

M25

M29

M31

M33

N11

N33

R11

R33

T11

T33

W11

AR9

U33

V33

W33

AR7

AA6

A14

A19

A24

A29

A9

G17

G22

G27

H15

H20

H25

J18

J23

J28

K16

K21

K26

L14

L19

VCC_SENSE

VCCPLL

VCCPWRGOOD

VDDPWRGOOD

VDDQ

L24

M17

M27

AL10

AL9

VID[0]/MSID[0]

I/O

O

I

VID[1]/MSID[1]

VID[2]/MSID[2]

AN9

AM10

AN10

AP9

AP8

AN8

A35

A39

A4

VID[3]/CSC[0]

VID[4]/CSC[1]

VID[5]/CSC[2]

VID[6]

VID[7]

VSS

VDDQ

O

VDDQ

B12

B17

B22

B27

B32

B7

VDDQ

VSS

VDDQ

VSS

VDDQ

VSS

A41

A6

VDDQ

VSS

VDDQ

VSS

AA3

AA34

AA38

AA39

AA9

AB37

AB4

AB40

AB42

AB7

AC2

AC36

AC5

AC7

AC9

AD11

AD33

VDDQ

C10

C15

C20

C25

C30

D13

D18

D23

D28

E11

E16

E21

E26

E31

F14

F19

VSS

VDDQ

VSS

VDDQ

VSS

VDDQ

VSS

VDDQ

VSS

VDDQ

VSS

VDDQ

VSS

VDDQ

VSS

VDDQ

VSS

VDDQ

VSS

VDDQ

VSS

VDDQ

VSS

VDDQ

VSS

VDDQ

VSS

VDDQ

VSS

VDDQ

VSS

Datasheet

47

Land Listing

Table 4-1. Land Listing by Land Name

(Sheet 23 of 29)

Table 4-1. Land Listing by Land Name

(Sheet 24 of 29)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

VSS

AD37

AD41

AD43

AE2

GND

VSS

AL32

AL35

AL36

AL37

AL42

AL7

GND

AE39

AE7

AF35

AF38

AF41

AF5

AM11

AM14

AM17

AM20

AM22

AM23

AM26

AM29

AM32

AM35

AM37

AM39

AM5

AG11

AG3

AG33

AG43

AG9

AH1

AH34

AH37

AH39

AH7

AM9

AJ34

AJ36

AJ41

AJ5

AN11

AN14

AN17

AN20

AN22

AN23

AN26

AN29

AN3

AK10

AK14

AK17

AK20

AK22

AK23

AK26

AK29

AK3

AN32

AN35

AN37

AN41

AN7

AK32

AK34

AK39

AK43

AK9

AP1

AP10

AP11

AP14

AP17

AP20

AP22

AP23

AP26

AP29

AP32

AP35

AP36

AP37

AL1

AL11

AL14

AL17

AL2

AL20

AL22

AL23

AL26

AL29

48

Datasheet

Land Listing

Table 4-1. Land Listing by Land Name

(Sheet 25 of 29)

Table 4-1. Land Listing by Land Name

(Sheet 26 of 29)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

VSS

AP43

AP5

GND

VSS

AV22

AV23

AV26

AV29

AV32

AV39

AV4

GND

AP6

AR11

AR14

AR17

AR2

AR20

AR22

AR23

AR26

AR29

AR3

AV41

AW1

AW11

AW14

AW17

AW20

AW22

AW23

AW26

AW29

AW32

AW35

AW6

AW8

AY11

AY14

AY17

AY2

AR32

AR35

AR39

AT11

AT14

AT17

AT20

AT22

AT23

AT26

AT29

AT32

AT35

AT38

AT41

AT7

AY20

AY22

AY23

AY26

AY29

AY32

AY37

AY42

AY7

AT8

AU1

AU11

AU14

AU17

AU20

AU22

AU23

AU26

AU29

AU32

AU35

AU36

AU43

AU5

B2

B37

B42

BA11

BA14

BA17

BA20

BA26

BA29

BA3

AV11

AV14

AV17

AV20

BA35

BA39

BA5

C35

Datasheet

49

Land Listing

Table 4-1. Land Listing by Land Name

(Sheet 27 of 29)

Table 4-1. Land Listing by Land Name

(Sheet 28 of 29)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Land Name

Direction

Land Name

Direction

VSS

C40

GND

VSS

M18

GND

C43

C5

M2

M20

M22

M24

M26

M28

M30

M32

M37

M42

M7

D3

D33

D38

D43

D8

E1

E36

E41

E6

F29

F34

F39

F4

N10

N35

N40

N5

F9

P11

P3

G12

G2

P33

P38

P43

P8

G32

G37

G42

G7

R1

H10

H30

H35

H40

H5

R36

R41

R6

T34

T39

T4

J13

J3

T9

J33

J38

J43

J8

U2

U37

U42

U7

K1

V10

V35

V40

V5

K11

K31

K36

K41

K6

W3

W38

W43

W8

L29

L34

L39

L4

Y1

Y11

Y33

Y36

Y41

Y6

L9

M12

M14

M16

50

Datasheet

Land Listing

Table 4-1. Land Listing by Land Name

(Sheet 29 of 29)

Land

No.

Buffer

Type

Land Name

Direction

VSS_SENSE

AR8

Analog

CMOS

PWR

Asynch

VSS_SENSE_VTT

VTT_SENSE

VTT_VID2

VTT_VID3

VTT_VID4

VTTA

AE37

AE36

AV3

O

AF7

AV6

AD10

AE10

AE11

AE33

AF11

AF33

AF34

AG34

AA10

AA11

AA33

AB10

AB11

AB33

AB34

AB8

VTTA

VTTD

AB9

VTTD

AC10

AC11

AC33

AC34

AC35

AD34

AD35

AD36

AD9

VTTD

AE34

AE35

AE8

VTTD

AE9

VTTD

AF36

AF37

AF8

VTTD

AF9

VTTPWRGOOD

AB35

I

Datasheet

51

Land Listing

Table 4-2. Land Listing by Land Number

(Sheet 2 of 29)

Table 4-2. Land Listing by Land Number

(Sheet 1 of 29)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Pin Name

Direction

Pin Name

Direction

AB11

AB3

VTTD

RSVD

VTTD

PWR

A10

A14

A15

A16

A17

A18

A19

A20

A24

A25

A26

A27

A28

A29

A30

A31

A35

A36

A37

A38

A39

A4

DDR0_MA[13]

VDDQ

CMOS

PWR

O

AB33

AB34

AB35

AB36

AB37

AB38

AB39

AB4

PWR

Asynch

CMOS

GND

QPI

DDR0_RAS#

DDR0_BA[1]

DDR2_BA[0]

DDR2_MA[0]

VDDQ

CMOS

PWR

O

VTTPWRGOOD

DDR1_DQ[5]

VSS

I

I/O

QPI_DTX_DN[17]

QPI_DTX_DP[17]

VSS

O

DDR0_MA[0]

VDDQ

CMOS

PWR

O

QPI

GND

Analog

GND

QPI

DDR0_MA[7]

DDR0_MA[11]

RSVD

CMOS

O

AB40

AB41

AB42

AB43

AB5

VSS

COMP0

VSS

DDR0_MA[14]

VDDQ

CMOS

PWR

O

QPI_DTX_DN[13]

RSVD

O

DDR0_CKE[1]

RSVD

CMOS

AB6

RSVD

AB7

VSS

GND

PWR

Analog

PWR

GND

VSS

GND

AB8

VTTD

RSVD

AB9

VTTD

RSVD

AC1

DDR_COMP[2]

VTTD

DDR0_DQ[26]

VSS

CMOS

GND

I/O

AC10

AC11

AC2

VTTD

VSS

GND

VSS

A40

A41

A5

RSVD

AC3

RSVD

VSS

GND

GTL

AC33

AC34

AC35

AC36

AC37

AC38

AC39

AC4

VTTD

PWR

GND

GTL

QPI

BPM#[1]

VSS

I/O

VTTD

A6

GND

VTTD

A7

DDR0_CS#[5]

DDR1_CS#[1]

VDDQ

CMOS

PWR

O

VSS

A8

CAT_ERR#

QPI_DTX_DN[16]

QPI_DTX_DP[16]

RSVD

I/O

O

A9

AA10

AA11

AA3

AA33

AA34

AA35

AA36

AA37

AA38

AA39

AA4

AA40

AA41

AA5

AA6

AA7

AA8

AA9

AB10

VTTD

PWR

QPI

O

VTTD

PWR

VSS

GND

AC40

AC41

AC42

AC43

AC5

QPI_DTX_DN[15]

QPI_DTX_DP[15]

QPI_DTX_DN[12]

QPI_DTX_DP[13]

VSS

QPI

GND

O

VTTD

PWR

VSS

GND

DDR1_DQ[4]

DDR1_DQ[1]

DDR1_DQ[0]

VSS

CMOS

GND

I/O

AC6

RSVD

AC7

VSS

GND

VSS

GND

AC8

RSVD

BCLK_ITP_DN

RSVD

CMOS

O

AC9

VSS

AD1

RSVD

AD10 VTTA

AD11 VSS

PWR

GND

BCLK_ITP_DP

VDDPWRGOOD

DDR1_DQ[62]

DDR_COMP[0]

VSS

CMOS

Asynch

CMOS

Analog

GND

O

I

AD2

AD3

RSVD

I/O

AD33 VSS

AD34 VTTD

GND

PWR

VTTD

PWR

52

Datasheet

Land Listing

Table 4-2. Land Listing by Land Number

(Sheet 3 of 29)

Table 4-2. Land Listing by Land Number

(Sheet 4 of 29)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Pin Name

Direction

Pin Name

Direction

AD35 VTTD

AD36 VTTD

AD37 VSS

PWR

GND

QPI

AF39

AF4

QPI_DTX_DP[1]

RSVD

QPI

O

AF40

AF41

AF42

AF43

AF5

QPI_DTX_DN[19]

VSS

QPI

O

AD38 QPI_DTX_DP[18]

AD39 QPI_DTX_DN[14]

O

GND

QPI

QPI_CLKTX_DN

QPI_DTX_DP[10]

VSS

O

AD4

RSVD

QPI

AD40 QPI_DTX_DP[14]

AD41 VSS

QPI

O

GND

QPI

AF6

RSVD

AD42 QPI_DTX_DP[12]

AD43 VSS

AF7

VTT_VID3

VTTD

CMOS

PWR

O

I

GND

AF8

AD5

RSVD

AF9

VTTD

PWR

AD6

RSVD

AG1

RSVD

AD7

RSVD

AG10 TMS

AG11 VSS

TAP

AD8

RSVD

GND

AD9

VTTD

PWR

AG2

AG3

RSVD

VSS

AE1

RSVD

GND

PWR

GTL

QPI

AE10

AE11

AE2

VTTA

PWR

GND

AG33 VSS

VTTA

AG34 VTTA

VSS

AG35 PROCHOT#

AG36 SKTOCC#

AG37 THERMTRIP#

AG38 QPI_DTX_DP[0]

AG39 QPI_DTX_DN[1]

I/O

O

AE3

RSVD

AE33

AE34

AE35

AE36

AE37

AE38

AE39

AE4

VTTA

PWR

O

VTTD

PWR

O

VTTD

PWR

QPI

O

VTT_SENSE

VSS_SENSE_VTT

QPI_DTX_DN[18]

VSS

Analog

QPI

AG4

RSVD

AG40 QPI_DTX_DP[9]

AG41 QPI_DTX_DN[9]

AG42 QPI_CLKTX_DP

AG43 VSS

QPI

GND

O

GND

RSVD

AE40

AE41

AE42

AE43

AE5

QPI_DTX_DP[19]

QPI_DTX_DN[11]

QPI_DTX_DP[11]

QPI_DTX_DN[10]

RSVD

QPI

O

AG5

AG6

AG7

AG8

AG9

AH1

RSVD

VSS

GND

TAP

AE6

RSVD

VSS

AE7

VSS

GND

PWR

AH10 TCK

AH11 VCC

I

AE8

VTTD

PWR

AE9

VTTD

AH2

AH3

RSVD

AF1

RSVD

AF10

AF11

AF2

DBR#

Asynch

PWR

I

AH33 VCC

PWR

VTTA

AH34 VSS

GND

RSVD

AH35 BCLK_DN

AH36 PECI

CMOS

AF3

RSVD

Asynch I/O

GND

AF33

AF34

AF35

AF36

AF37

AF38

VTTA

PWR

GND

PWR

GND

AH37 VSS

VTTA

AH38 QPI_DTX_DN[0]

AH39 VSS

QPI

O

VSS

GND

VTTD

AH4

RSVD

VTTD

AH40 QPI_DTX_DP[4]

AH41 QPI_DTX_DP[6]

QPI

O

VSS

Datasheet

53

Land Listing

Table 4-2. Land Listing by Land Number

(Sheet 5 of 29)

Table 4-2. Land Listing by Land Number

(Sheet 6 of 29)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Pin Name

Direction

Pin Name

Direction

AH42 QPI_DTX_DN[6]

AH43 QPI_DTX_DN[8]

QPI

O

AK27

AK28

AK29

AK3

VCC

VSS

VCC

VSS

VCC

VSS

RSVD

PWR

GND

PWR

GND

PWR

GND

AH5

FC_AH5

RSVD

VSS

AH6

AH7

GND

TAP

AK30

AK31

AK32

AK33

AK34

AK35

AK36

AK37

AK38

AK39

AK4

AH8

RSVD

TRST#

RSVD

TDO

AH9

I

AJ1

AJ10

AJ11

AJ2

TAP

O

VCC

PWR

RSVD

VCC

AJ3

QPI_DTX_DP[2]

QPI

GND

O

AJ33

AJ34

AJ35

AJ36

AJ37

AJ38

AJ39

AJ4

PWR

GND

CMOS

GND

QPI_DTX_DN[2]

VSS

BCLK_DP

VSS

I

RSVD

AK40

AK41

AK42

AK43

AK5

QPI_DTX_DP[5]

QPI

GND

O

RSVD

QPI_DTX_DP[3]

QPI_DTX_DN[3]

RSVD

QPI_DTX_DN[4]

VSS

QPI_DTX_DN[5]

QPI_DTX_DP[7]

VSS

QPI

O

RSVD

ISENSE

VSS

AJ40

AJ41

AJ42

AJ43

AJ5

QPI

O

AK6

GND

QPI

AK7

QPI_DTX_DN[7]

QPI_DTX_DP[8]

VSS

O

AK8

Analog

GND

CMOS

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

I

QPI

AK9

GND

AL1

VSS

AJ6

RSVD

TDI

AL10

AL11

AL12

AL13

AL14

AL15

AL16

AL17

AL18

AL19

AL2

VID[0]/MSID[0]

VSS

I/O

AJ7

AJ8

VCC

AJ9

TAP

I

VCC

AK1

RSVD

VSS

AK10

AK11

AK12

AK13

AK14

AK15

AK16

AK17

AK18

AK19

AK2

GND

PWR

GND

PWR

GND

PWR

VCC

VSS

VCC

VSS

VCC

VSS

VCC

AL20

AL21

AL22

AL23

AL24

AL25

AL26

AL27

AL28

AL29

AL3

VSS

VCC

VSS

VCC

VSS

RSVD

VSS

VCC

AK20

AK21

AK22

AK23

AK24

AK25

AK26

GND

PWR

GND

PWR

GND

VCC

VSS

VCC

VSS

VCC

VSS

VCC

RSVD

VCC

VSS

AL30

PWR

54

Datasheet

Land Listing

Table 4-2. Land Listing by Land Number

(Sheet 7 of 29)

Table 4-2. Land Listing by Land Number

(Sheet 8 of 29)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Pin Name

Direction

Pin Name

Direction

AL31

AL32

AL33

AL34

AL35

AL36

AL37

AL38

AL39

AL4

VCC

VSS

VCC

VSS

RSVD

PWR

GND

PWR

GND

AM36 RSVD

AM37 VSS

AM38 RSVD

AM39 VSS

GND

AM4

RSVD

AM40 QPI_DRX_DN[15]

AM41 QPI_DRX_DN[16]

AM42 QPI_DRX_DP[16]

AM43 QPI_DRX_DN[14]

QPI

GND

I

RESET#

RSVD

Asynch

I

AM5

AM6

AM7

AM8

AM9

AN1

VSS

AL40

AL41

AL42

AL43

AL5

RSVD

VSS

RSVD

VSS

GND

QPI_CMP[0]

RSVD

Analog

GND

RSVD

AL6

RSVD

AN10 VID[4]/CSC[1]

AN11 VSS

AN12 VCC

AN13 VCC

AN14 VSS

AN15 VCC

AN16 VCC

AN17 VSS

AN18 VCC

AN19 VCC

CMOS

GND

PWR

GND

PWR

GND

PWR

I/O

AL7

VSS

GND

AL8

RSVD

AL9

VID[1]/MSID[1]

RSVD

CMOS

I/O

AM1

AM10 VID[3]/CSC[0]

AM11 VSS

AM12 VCC

AM13 VCC

AM14 VSS

AM15 VCC

AM16 VCC

AM17 VSS

AM18 VCC

AM19 VCC

CMOS

GND

PWR

GND

PWR

GND

PWR

AN2

RSVD

AN20 VSS

AN21 VCC

AN22 VSS

AN23 VSS

AN24 VCC

AN25 VCC

AN26 VSS

AN27 VCC

AN28 VCC

AN29 VSS

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

AM2

RSVD

AM20 VSS

AM21 VCC

AM22 VSS

AM23 VSS

AM24 VCC

AM25 VCC

AM26 VSS

AM27 VCC

AM28 VCC

AM29 VSS

GND

PWR

GND

PWR

GND

PWR

GND

AN3

VSS

AN30 VCC

AN31 VCC

AN32 VSS

AN33 VCC

AM3

RSVD

AN34 VCC

AM30 VCC

AM31 VCC

AM32 VSS

AM33 VCC

AM34 VCC

AM35 VSS

PWR

GND

PWR

GND

AN35 VSS

AN36 RSVD

AN37 VSS

GND

QPI

AN38 RSVD

AN39 QPI_DRX_DP[18]

I

AN4

RSVD

Datasheet

55

Land Listing

Table 4-2. Land Listing by Land Number

(Sheet 9 of 29)

Table 4-2. Land Listing by Land Number

(Sheet 10 of 29)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Pin Name

Direction

Pin Name

Direction

AN40 QPI_DRX_DP[15]

AN41 VSS

QPI

GND

QPI

I

AP6

VSS

GND

AP7

PSI#

CMOS

O

AN42 QPI_DRX_DN[13]

AN43 QPI_DRX_DP[14]

I

AP8

VID[6]

O

AP9

VID[5]/CSC[2]

I/O

AN5

RSVD

AR1

RSVD

AN6

RSVD

AR10

AR11

AR12

AR13

AR14

AR15

AR16

AR17

AR18

AR19

AR2

VCC

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

AN7

VSS

GND

CMOS

GND

PWR

GND

PWR

GND

PWR

VSS

AN8

VID[7]

O

VCC

AN9

VID[2]/MSID[2]

I/O

VCC

AP1

VSS

AP10

AP11

AP12

AP13

AP14

AP15

AP16

AP17

AP18

AP19

AP2

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

AR20

AR21

AR22

AR23

AR24

AR25

AR26

AR27

AR28

AR29

AR3

VSS

VCC

VSS

VCC

VSS

RSVD

VCC

AP20

AP21

AP22

AP23

AP24

AP25

AP26

AP27

AP28

AP29

AP3

VSS

GND

PWR

GND

PWR

GND

PWR

GND

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

AR30

AR31

AR32

AR33

AR34

AR35

AR36

AR37

AR38

AR39

AR4

VCC

VSS

VCC

RSVD

VCC

AP30

AP31

AP32

AP33

AP34

AP35

AP36

AP37

AP38

AP39

AP4

VCC

PWR

GND

PWR

GND

QPI

VSS

VCC

RSVD

VSS

RSVD

VCC

QPI_DRX_DN[19]

VSS

QPI

I

VCC

GND

VSS

RSVD

VSS

AR40

AR41

AR42

AR43

AR5

QPI_DRX_DN[12]

QPI_CLKRX_DP

QPI_CLKRX_DN

QPI_DRX_DN[11]

RSVD

QPI

I

VSS

QPI_DRX_DP[19]

QPI_DRX_DN[18]

RSVD

I

QPI

AP40

AP41

AP42

AP43

AP5

QPI_DRX_DN[17]

QPI_DRX_DP[17]

QPI_DRX_DP[13]

VSS

QPI

I

AR6

RSVD

QPI

AR7

VCCPWRGOOD

VSS_SENSE

VCC_SENSE

RSVD

Asynch

Analog

I

QPI

AR8

GND

AR9

VSS

AT1

56

Datasheet

Land Listing

Table 4-2. Land Listing by Land Number

(Sheet 11 of 29)

Table 4-2. Land Listing by Land Number

(Sheet 12 of 29)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Pin Name

Direction

Pin Name

Direction

AT10

AT11

AT12

AT13

AT14

AT15

AT16

AT17

AT18

AT19

AT2

VCC

VSS

VCC

VSS

VCC

VSS

VCC

RSVD

VSS

VCC

VSS

VCC

VSS

VCC

VSS

RSVD

VCC

VSS

VCC

VSS

RSVD

PWR

GND

PWR

GND

PWR

GND

PWR

AU15 VCC

AU16 VCC

AU17 VSS

AU18 VCC

AU19 VCC

PWR

GND

PWR

AU2

RSVD

AU20 VSS

AU21 VCC

AU22 VSS

AU23 VSS

AU24 VCC

AU25 VCC

AU26 VSS

AU27 VCC

AU28 VCC

AU29 VSS

GND

PWR

GND

PWR

GND

PWR

GND

AT20

AT21

AT22

AT23

AT24

AT25

AT26

AT27

AT28

AT29

AT3

GND

PWR

GND

PWR

GND

PWR

GND

AU3

RSVD

AU30 VCC

AU31 VCC

AU32 VSS

AU33 VCC

AU34 VCC

AU35 VSS

AU36 VSS

PWR

GND

PWR

GND

QPI

AT30

AT31

AT32

AT33

AT34

AT35

AT36

AT37

AT38

AT39

AT4

PWR

GND

PWR

GND

AU37 QPI_DRX_DN[0]

AU38 QPI_DRX_DP[1]

AU39 QPI_DRX_DP[7]

I

QPI

AU4

RSVD

AU40 QPI_DRX_DP[9]

AU41 QPI_DRX_DN[9]

AU42 QPI_DRX_DP[10]

AU43 VSS

QPI

I

QPI_DRX_DP[0]

QPI

GND

QPI

I

QPI

VSS

QPI

QPI_DRX_DN[7]

GND

RSVD

AU5

VSS

AT40

AT41

AT42

AT43

AT5

QPI_DRX_DP[12]

QPI

GND

QPI

AU6

RSVD

VCC

RSVD

VCC

VSS

AU7

QPI_DRX_DN[10]

I

AU8

QPI_DRX_DP[11]

AU9

PWR

RSVD

VSS

AV1

AT6

AV10

AV11

AV12

AV13

AV14

AV15

AV16

AV17

AV18

AV19

PWR

GND

PWR

GND

PWR

GND

PWR

AT7

GND

PWR

GND

PWR

GND

PWR

GND

AT8

VSS

VCC

VSS

AT9

VCC

AU1

VSS

AU10 VCC

AU11 VSS

AU12 VCC

AU13 VCC

AU14 VSS

VCC

VSS

VCC

Datasheet

57

Land Listing

Table 4-2. Land Listing by Land Number

(Sheet 13 of 29)

Table 4-2. Land Listing by Land Number

(Sheet 14 of 29)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Pin Name

Direction

Pin Name

Direction

AV2

RSVD

VSS

VCC

VSS

VCC

VSS

VCC

VSS

AW24 VCC

AW25 VCC

AW26 VSS

AW27 VCC

AW28 VCC

AW29 VSS

PWR

GND

PWR

GND

AV20

AV21

AV22

AV23

AV24

AV25

AV26

AV27

AV28

AV29

AV3

GND

PWR

GND

PWR

GND

PWR

GND

CMOS

PWR

GND

PWR

AW3

RSVD

AW30 VCC

AW31 VCC

AW32 VSS

AW33 VCC

AW34 VCC

AW35 VSS

PWR

GND

PWR

GND

QPI

VTT_VID2

VCC

O

AV30

AV31

AV32

AV33

AV34

AV35

AV36

AV37

AV38

AV39

AV4

VCC

AW36 QPI_DRX_DP[3]

AW37 QPI_DRX_DP[5]

AW38 QPI_DRX_DN[5]

AW39 RSVD

I

VSS

QPI

VCC

QPI

VCC

RSVD

AW4

RSVD

QPI_DRX_DP[2]

QPI_DRX_DN[2]

QPI_DRX_DN[1]

VSS

QPI

I

AW40 QPI_DRX_DP[8]

AW41 RSVD

QPI

I

QPI

AW42 RSVD

GND

QPI

AW5

AW6

AW7

AW8

AW9

AY10

AY11

AY12

AY13

AY14

AY15

AY16

AY17

AY18

AY19

AY2

RSVD

VSS

RSVD

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

RSVD

VSS

GND

AV40

AV41

AV42

AV43

AV5

QPI_DRX_DN[8]

VSS

I

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

RSVD

AV6

VTT_VID4

RSVD

CMOS

O

AV7

AV8

RSVD

AV9

VCC

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

AW1

VSS

AW10 VCC

AW11 VSS

AW12 VCC

AW13 VCC

AW14 VSS

AW15 VCC

AW16 VCC

AW17 VSS

AW18 VCC

AW19 VCC

AY20

AY21

AY22

AY23

AY24

AY25

AY26

AY27

AY28

AY29

AY3

AW2

RSVD

AW20 VSS

AW21 VCC

AW22 VSS

AW23 VSS

GND

PWR

GND

58

Datasheet

Land Listing

Table 4-2. Land Listing by Land Number

(Sheet 15 of 29)

Table 4-2. Land Listing by Land Number

(Sheet 16 of 29)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Pin Name

Direction

Pin Name

Direction

AY30

AY31

AY32

AY33

AY34

AY35

AY36

AY37

AY38

AY39

AY4

AY40

AY41

AY42

AY5

AY6

AY7

AY8

AY9

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B2

VCC

VSS

VCC

RSVD

PWR

GND

PWR

B37

VSS

GND

B38

DDR0_DQ[31]

DDR0_DQS_P[3]

BPM#[3]

DDR0_DQS_N[3]

PRDY#

VSS

CMOS

GTL

I/O

O

B39

B4

B40

CMOS

GTL

B41

QPI_DRX_DN[3]

VSS

QPI

GND

QPI

I

B42

GND

B5

DDR0_DQ[32]

DDR0_DQ[36]

VDDQ

CMOS

PWR

I/O

QPI_DRX_DN[6]

RSVD

B6

B7

RSVD

B8

RSVD

B9

RSVD

BA10

BA11

BA12

BA13

BA14

BA15

BA16

BA17

BA18

BA19

BA20

BA24

BA25

BA26

BA27

BA28

BA29

BA3

VCC

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

QPI

VSS

GND

VSS

RSVD

VCC

RSVD

VCC

VSS

RSVD

VCC

PWR

VCC

DDR0_CS#[1]

DDR0_ODT[2]

VDDQ

CMOS

PWR

O

VSS

VCC

DDR0_WE#

DDR1_MA[13]

DDR0_CS#[4]

DDR0_BA[0]

VDDQ

CMOS

PWR

O

VSS

VCC

VSS

VCC

RSVD

VCC

DDR0_MA[10]

VSS

CMOS

GND

O

VSS

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B3

RSVD

BA30

BA35

BA36

BA37

BA38

BA39

BA4

VCC

DDR0_MA[1]

VDDQ

CMOS

PWR

VSS

QPI_DRX_DP[4]

QPI_DRX_DN[4]

QPI_DRX_DP[6]

VSS

I

DDR0_MA[4]

DDR0_MA[5]

DDR0_MA[8]

DDR0_MA[12]

VDDQ

CMOS

PWR

O

QPI

GND

RSVD

BA40

BA5

RSVD

VSS

GND

DDR0_MA[15]

BPM#[0]

DDR0_CKE[2]

DDR0_CKE[3]

VDDQ

CMOS

GTL

O

BA6

RSVD

I/O

O

BA7

RSVD

B30

B31

B32

B33

B34

B35

B36

CMOS

PWR

BA8

RSVD

O

BA9

VCC

PWR

C10

VDDQ

RSVD

C11

RSVD

C12

DDR0_CAS#

RSVD

CMOS

O

RSVD

C13

RSVD

C14

RSVD

Datasheet

59

Land Listing

Table 4-2. Land Listing by Land Number

(Sheet 17 of 29)

Table 4-2. Land Listing by Land Number

(Sheet 18 of 29)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Pin Name

Direction

Pin Name

Direction

C15

C16

C17

C18

C19

C2

VDDQ

PWR

D2

BPM#[6]

GTL

I/O

DDR2_WE#

DDR1_CS#[4]

DDR1_BA[0]

DDR0_CLK_N[1]

BPM#[2]

CMOS

CLOCK

GTL

O

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D3

RSVD

O

DDR1_CLK_N[0]

DDR1_MA[7]

VDDQ

CLOCK

CMOS

PWR

O

I/O

DDR0_MA[3]

RSVD

CMOS

O

C20

C21

C22

C23

C24

C25

C26

C27

C28

C29

C3

VDDQ

PWR

DDR1_CLK_P[0]

RSVD

CLOCK

O

DDR2_CKE[2]

DDR1_CKE[2]

VDDQ

CMOS

PWR

O

DDR0_MA[2]

DDR0_MA[6]

VDDQ

CMOS

PWR

O

DDR1_RESET#

VSS

CMOS

GND

O

DDR0_MA[9]

DDR1_CKE[3]

DDR0_BA[2]

DDR0_CKE[0]

BPM#[5]

CMOS

GTL

O

D30

D31

D32

D33

D34

D35

D36

D37

D38

D39

D4

RSVD

O

RSVD

O

DDR0_RESET#

VSS

CMOS

GND

O

I/O

RSVD

C30

C31

C32

C33

C34

C35

C36

C37

C38

C39

C4

VDDQ

PWR

RSVD

DDR0_DQ[27]

VSS

CMOS

GND

I/O

RSVD

VSS

GND

RSVD

D40

D41

D42

D43

D5

DDR0_DQ[24]

DDR0_DQ[28]

DDR0_DQ[29]

VSS

CMOS

GND

I/O

RSVD

DDR0_DQ[30]

RSVD

CMOS

I/O

DDR0_DQ[33]

VSS

CMOS

GND

RSVD

C40

C41

C42

C43

C5

D6

DDR1_DQ[38]

DDR1_DQS_N[4]

VSS

CMOS

GND

I/O

DDR0_DQ[25]

PREQ#

CMOS

GTL

I/O

I

D7

D8

VSS

GND

D9

DDR2_CS#[5]

VSS

CMOS

GND

O

VSS

GND

E1

C6

DDR0_DQ[37]

DDR0_ODT[3]

DDR1_ODT[1]

DDR0_ODT[1]

BPM#[4]

CMOS

GTL

I/O

O

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E2

DDR1_CS#[5]

VDDQ

CMOS

PWR

C7

C8

O

RSVD

C9

O

RSVD

D1

I/O

O

DDR1_CAS#

RSVD

CMOS

O

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

DDR2_ODT[3]

DDR1_ODT[0]

DDR1_CS#[0]

VDDQ

CMOS

PWR

O

VDDQ

PWR

O

DDR2_CS#[4]

DDR0_CLK_N[2]

DDR0_CLK_N[3]

BPM#[7]

DDR0_CLK_P[3]

VDDQ

CMOS

CLOCK

GTL

O

DDR1_ODT[2]

DDR2_ODT[2]

RSVD

CMOS

O

I/O

O

E20

E21

E22

E23

CLOCK

PWR

DDR2_RAS#

VDDQ

CMOS

PWR

O

DDR1_MA[8]

DDR1_MA[11]

CMOS

O

DDR0_CLK_P[1]

CLOCK

60

Datasheet

Land Listing

Table 4-2. Land Listing by Land Number

(Sheet 19 of 29)

Table 4-2. Land Listing by Land Number

(Sheet 20 of 29)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Pin Name

Direction

Pin Name

Direction

E24

E25

E26

E27

E28

E29

E3

DDR1_MA[12]

RSVD

CMOS

O

F29

F3

VSS

GND

DDR0_DQ[38]

RSVD

CMOS

I/O

VDDQ

PWR

F30

F31

F32

F33

F34

F35

F36

F37

F38

F39

F4

DDR1_CKE[1]

RSVD

CMOS

O

RSVD

DDR0_DQS_P[4]

RSVD

CMOS

I/O

O

VSS

GND

E30

E31

E32

E33

E34

E35

E36

E37

E38

E39

E4

RSVD

VDDQ

PWR

RSVD

DDR2_RESET#

RSVD

CMOS

RSVD

DDR2_DQ[30]

VSS

CMOS

GND

I/O

RSVD

VSS

GND

VSS

GND

F40

F41

F42

F43

F5

DDR2_DQ[25]

DDR0_DQS_P[2]

DDR0_DQ[23]

DDR0_DQ[22]

DDR1_DQ[35]

DDR1_DQ[39]

RSVD

CMOS

I/O

RSVD

DDR2_DQ[31]

DDR2_DQS_P[3]

DDR0_DQS_N[4]

DDR2_DQS_N[3]

VSS

CMOS

GND

I/O

E40

E41

E42

E43

E5

F6

F7

DDR0_DQ[18]

DDR0_DQ[19]

DDR1_DQ[34]

VSS

CMOS

GND

I/O

F8

RSVD

F9

VSS

GND

G1

DDR0_DQ[44]

DDR2_DQ[37]

DDR2_DQ[36]

VSS

CMOS

GND

I/O

E6

G10

G11

G12

G13

G14

G15

G16

G17

G18

G19

G2

E7

DDR1_DQS_P[4]

DDR1_DQ[33]

DDR1_DQ[32]

DDR0_DQ[34]

DDR1_DQ[36]

DDR1_ODT[3]

DDR0_ODT[0]

DDR2_ODT[1]

VDDQ

CMOS

PWR

I/O

O

E8

E9

DDR1_WE#

DDR1_RAS#

DDR0_CS#[0]

DDR2_CS#[0]

VDDQ

CMOS

PWR

O

F1

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

F2

O

DDR2_MA[2]

DDR1_CLK_P[1]

VSS

CMOS

CLOCK

GND

O

DDR2_MA[13]

DDR2_CAS#

DDR2_BA[1]

DDR0_CLK_P[2]

VDDQ

CMOS

CLOCK

PWR

O

G20

G21

G22

G23

G24

G25

G26

G27

G28

G29

G3

DDR1_CLK_N[1]

DDR2_CLK_N[2]

VDDQ

CLOCK

PWR

O

DDR2_MA[12]

DDR1_MA[9]

DDR2_MA[15]

DDR2_CKE[1]

VDDQ

CMOS

PWR

O

DDR0_DQ[39]

DDR2_MA[4]

RSVD

CMOS

I/O

O

F20

F21

F22

F23

F24

F25

F26

F27

F28

DDR1_MA[5]

RSVD

CMOS

PWR

O

RSVD

VDDQ

RSVD

DDR0_DQ[35]

RSVD

CMOS

GND

I/O

DDR1_MA[15]

RSVD

CMOS

O

G30

G31

G32

RSVD

VSS

Datasheet

61

Land Listing

Table 4-2. Land Listing by Land Number

(Sheet 21 of 29)

Table 4-2. Land Listing by Land Number

(Sheet 22 of 29)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Pin Name

Direction

Pin Name

Direction

G33

G34

G35

G36

G37

G38

G39

G4

RSVD

VSS

H38

H39

H4

RSVD

DDR2_DQ[28]

DDR1_DQ[43]

VSS

CMOS

GND

I/O

H40

H41

H42

H43

H5

GND

DDR0_DQ[16]

RSVD

CMOS

I/O

RSVD

DDR2_DQ[29]

DDR1_DQ[42]

DDR2_DQ[24]

DDR0_DQS_N[2]

VSS

CMOS

GND

I/O

DDR0_DQ[17]

VSS

CMOS

GND

G40

G41

G42

G43

G5

H6

DDR1_DQS_P[5]

RSVD

CMOS

H7

H8

DDR1_DQ[40]

DDR1_DQ[45]

RSVD

CMOS

I/O

RSVD

H9

DDR1_DQ[46]

DDR1_DQS_N[5]

VSS

CMOS

GND

I/O

J1

G6

J10

J11

J12

J13

J14

J15

J16

J17

J18

J19

J2

DDR2_DQS_P[4]

RSVD

CMOS

I/O

O

G7

G8

DDR1_DQ[37]

DDR1_DQ[44]

DDR0_DQ[41]

VSS

CMOS

GND

I/O

DDR2_DQ[33]

VSS

CMOS

GND

G9

H1

DDR1_MA[0]

RSVD

CMOS

H10

H11

H12

H13

H14

H15

H16

H17

H18

H19

H2

RSVD

DDR1_MA[1]

DDR1_MA[2]

VDDQ

CMOS

PWR

O

DDR2_DQ[38]

DDR2_DQ[34]

DDR1_MA[10]

VDDQ

CMOS

PWR

I/O

O

DDR0_CLK_P[0]

RSVD

CLOCK

O

RSVD

J20

J21

J22

J23

J24

J25

J26

J27

J28

J29

J3

DDR2_MA[3]

DDR2_CLK_N[0]

DDR2_CLK_P[0]

VDDQ

CMOS

CLOCK

PWR

O

DDR2_MA[10]

DDR1_CLK_P[3]

DDR1_CLK_N[3]

DDR0_DQ[40]

VDDQ

CMOS

CLOCK

CMOS

PWR

O

I/O

DDR2_MA[7]

RSVD

CMOS

O

H20

H21

H22

H23

H24

H25

H26

H27

H28

H29

H3

DDR2_CLK_P[2]

DDR2_MA[9]

DDR2_MA[11]

DDR2_MA[14]

VDDQ

CLOCK

CMOS

PWR

O

DDR2_CKE[0]

DDR1_MA[6]

VDDQ

CMOS

PWR

O

RSVD

VSS

GND

DDR1_MA[14]

DDR1_BA[2]

DDR1_CKE[0]

RSVD

CMOS

O

J30

J31

J32

J33

J34

J35

J36

J37

J38

J39

J4

RSVD

DDR1_DQ[27]

VSS

CMOS

GND

I/O

DDR0_DQ[45]

VSS

CMOS

GND

I/O

DDR1_DQ[28]

DDR1_DQ[19]

DDR1_DQ[22]

DDR2_DQ[26]

VSS

CMOS

GND

I/O

H30

H31

H32

H33

H34

H35

H36

H37

RSVD

DDR1_DQ[24]

DDR1_DQ[29]

VSS

CMOS

GND

I/O

DDR2_DQ[19]

DDR1_DQ[52]

DDR2_DQ[18]

DDR0_DQ[21]

CMOS

I/O

DDR1_DQ[23]

DDR2_DQ[27]

CMOS

I/O

J40

J41

62

Datasheet

Land Listing

Table 4-2. Land Listing by Land Number

(Sheet 23 of 29)

Table 4-2. Land Listing by Land Number

(Sheet 24 of 29)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Pin Name

Direction

Pin Name

Direction

J42

J43

J5

DDR0_DQ[20]

VSS

CMOS

GND

I/O

K8

RSVD

K9

DDR1_DQ[47]

DDR1_DQ[41]

RSVD

CMOS

I/O

L1

DDR0_DQ[42]

DDR2_DQ[40]

DDR2_DQ[44]

DDR2_DQ[39]

DDR2_DQ[35]

VDDQ

CMOS

PWR

I/O

J6

L10

L11

L12

L13

L14

L15

L16

L17

L18

L19

L2

J7

J8

VSS

GND

J9

DDR2_DQS_N[4]

VSS

CMOS

GND

I/O

K1

K10

K11

K12

K13

K14

K15

K16

K17

K18

K19

K2

DDR2_DQ[41]

VSS

CMOS

GND

RSVD

DDR2_ODT[0]

RSVD

CMOS

O

DDR2_DQ[32]

DDR1_BA[1]

DDR2_CS#[1]

RSVD

CMOS

I/O

O

DDR1_CLK_N[2]

VDDQ

CLOCK

PWR

O

DDR0_DQ[47]

DDR2_CLK_P[1]

DDR2_CLK_N[3]

DDR2_CLK_P[3]

DDR_VREF

CMOS

CLOCK

Analog

PWR

I/O

O

VDDQ

PWR

L20

L21

L22

L23

L24

L25

L26

L27

L28

L29

L3

DDR2_MA[1]

DDR1_CLK_P[2]

DDR0_CLK_N[0]

DDR0_DQS_P[5]

DDR2_CLK_N[1]

VDDQ

CMOS

CLOCK

CMOS

CLOCK

PWR

O

I

I/O

O

VDDQ

K20

K21

K22

K23

K24

K25

K26

K27

K28

K29

K3

DDR2_MA[8]

DDR2_BA[2]

DDR2_CKE[3]

DDR1_MA[3]

VSS

CMOS

GND

O

DDR2_MA[6]

DDR2_MA[5]

RSVD

CMOS

O

RSVD

DDR0_DQ[46]

DDR1_DQS_P[3]

DDR1_DQS_N[3]

DDR1_DQ[30]

DDR1_DQ[25]

VSS

CMOS

GND

I/O

VDDQ

PWR

L30

L31

L32

L33

L34

L35

L36

L37

L38

L39

L4

RSVD

DDR1_MA[4]

RSVD

CMOS

O

DDR0_DQS_N[5]

DDR1_DQ[31]

VSS

CMOS

GND

I/O

K30

K31

K32

K33

K34

K35

K36

K37

K38

K39

K4

DDR1_DQS_P[2]

DDR1_DQS_N[2]

RSVD

CMOS

I/O

DDR1_DQ[26]

RSVD

CMOS

I/O

RSVD

VSS

GND

DDR1_DQ[18]

VSS

CMOS

GND

VSS

GND

L40

L41

L42

L43

L5

DDR2_DQ[22]

DDR0_DQS_P[1]

DDR0_DQ[15]

DDR0_DQ[14]

DDR1_DQS_N[6]

DDR1_DQS_P[6]

DDR2_DQS_P[5]

DDR2_DQ[46]

VSS

CMOS

GND

I/O

RSVD

DDR2_DQ[23]

DDR2_DQS_N[2]

DDR1_DQ[48]

DDR2_DQS_P[2]

VSS

CMOS

GND

I/O

K40

K41

K42

K43

K5

L6

L7

DDR0_DQ[10]

DDR0_DQ[11]

DDR1_DQ[49]

VSS

CMOS

GND

I/O

L8

L9

M1

DDR0_DQ[43]

DDR2_DQ[45]

VCC

CMOS

PWR

I/O

K6

M10

M11

K7

DDR2_DQS_N[5]

CMOS

I/O

Datasheet

63

Land Listing

Table 4-2. Land Listing by Land Number

(Sheet 25 of 29)

Table 4-2. Land Listing by Land Number

(Sheet 26 of 29)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Pin Name

Direction

Pin Name

Direction

M12

M13

M14

M15

M16

M17

M18

M19

M2

VSS

VCC

VSS

VCC

VSS

VDDQ

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VDDQ

VSS

VCC

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

CMOS

GND

PWR

GND

PWR

CMOS

GND

N36

N37

N38

N39

N4

DDR2_DQ[21]

DDR1_DQ[14]

DDR1_DQ[15]

DDR1_DQ[11]

RSVD

CMOS

I/O

N40

N41

N42

N43

N5

VSS

GND

DDR0_DQ[8]

RSVD

CMOS

I/O

DDR0_DQ[9]

VSS

CMOS

GND

M20

M21

M22

M23

M24

M25

M26

M27

M28

M29

M3

N6

DDR2_DQ[49]

DDR2_DQ[53]

DDR2_DQ[52]

DDR2_DQ[43]

RSVD

CMOS

I/O

N7

N8

N9

P1

P10

P11

P2

DDR2_DQ[51]

VSS

CMOS

GND

I/O

RSVD

P3

VSS

GND

DDR0_DQ[52]

VSS

I/O

P33

P34

P35

P36

P37

P38

P39

P4

VSS

GND

M30

M31

M32

M33

M34

M35

M36

M37

M38

M39

M4

DDR1_DQ[8]

DDR1_DQ[9]

RSVD

CMOS

I/O

VCC

VSS

VCC

RSVD

DDR1_DQ[17]

DDR1_DQ[16]

DDR1_DQ[21]

VSS

I/O

VSS

GND

DDR1_DQ[10]

RSVD

CMOS

I/O

P40

P41

P42

P43

P5

DDR2_DQ[20]

DDR0_DQ[13]

DDR0_DQ[12]

VSS

CMOS

GND

I/O

RSVD

DDR2_DQ[16]

RSVD

CMOS

I/O

M40

M41

M42

M43

M5

DDR2_DQ[17]

DDR0_DQS_N[1]

VSS

CMOS

GND

I/O

DDR2_DQS_N[6]

DDR2_DQS_P[6]

DDR2_DQ[48]

VSS

CMOS

GND

I/O

P6

P7

RSVD

P8

RSVD

P9

DDR2_DQ[50]

VSS

CMOS

GND

I/O

M6

DDR1_DQ[53]

VSS

CMOS

GND

I/O

R1

M7

R10

R11

R2

DDR2_DQ[54]

VCC

CMOS

PWR

M8

DDR2_DQ[47]

DDR2_DQ[42]

DDR0_DQ[48]

VSS

CMOS

GND

I/O

M9

DDR0_DQS_P[6]

DDR0_DQS_N[6]

VCC

CMOS

PWR

I/O

N1

R3

N10

N11

N2

R33

R34

R35

R36

R37

R38

R39

VCC

PWR

DDR1_DQ[12]

DDR1_DQ[13]

VSS

CMOS

GND

I/O

DDR0_DQ[49]

DDR0_DQ[53]

VCC

CMOS

PWR

I/O

N3

N33

N34

N35

DDR1_DQS_N[1]

DDR1_DQS_P[1]

DDR2_DQ[10]

CMOS

I/O

DDR1_DQ[20]

VSS

CMOS

GND

I/O

64

Datasheet

Land Listing

Table 4-2. Land Listing by Land Number

(Sheet 27 of 29)

Table 4-2. Land Listing by Land Number

(Sheet 28 of 29)

Land

No.

Buffer

Type

Land

No.

Buffer

Type

Pin Name

Direction

Pin Name

Direction

R4

DDR0_DQ[54]

DDR2_DQ[15]

VSS

CMOS

GND

I/O

U43

U5

DDR0_DQS_N[0]

DDR2_DQ[56]

DDR2_DQ[57]

VSS

CMOS

GND

I/O

R40

R41

R42

R43

R5

U6

DDR0_DQ[3]

DDR0_DQ[2]

DDR1_DQ[50]

VSS

CMOS

GND

I/O

U7

U8

DDR2_DQS_P[7]

DDR2_DQ[63]

DDR0_DQ[57]

VSS

CMOS

GND

I/O

U9

R6

V1

R7

DDR1_DQ[55]

DDR1_DQ[54]

DDR2_DQ[55]

DDR0_DQ[50]

DDR2_DQ[58]

VCC

CMOS

PWR

I/O

V10

V11

V2

R8

RSVD

R9

RSVD

T1

V3

RSVD

T10

T11

T2

V33

V34

V35

V36

V37

V38

V39

V4

VCCPLL

PWR

DDR2_DQ[5]

VSS

CMOS

GND

I/O

DDR0_DQ[51]

DDR0_DQ[55]

VCC

CMOS

PWR

I/O

T3

DDR2_DQ[2]

DDR2_DQ[6]

DDR2_DQ[7]

DDR2_DQ[13]

DDR0_DQ[62]

VSS

CMOS

GND

I/O

T33

T34

T35

T36

T37

T38

T39

T4

VSS

GND

RSVD

DDR2_DQ[11]

DDR2_DQS_P[1]

DDR2_DQS_N[1]

VSS

CMOS

GND

I/O

V40

V41

V42

V43

V5

DDR0_DQ[1]

RSVD

CMOS

I/O

VSS

GND

RSVD

T40

T41

T42

T43

T5

RSVD

VSS

GND

DDR2_DQ[14]

DDR0_DQ[7]

DDR0_DQS_P[0]

DDR1_DQ[51]

DDR2_DQ[60]

DDR2_DQ[61]

DDR2_DQS_N[7]

VSS

CMOS

GND

I/O

V6

RSVD

V7

RSVD

V8

DDR2_DQ[62]

DDR1_DQ[60]

DDR0_DQS_N[7]

DDR1_DQ[59]

VCC

CMOS

PWR

I/O

V9

T6

W1

T7

W10

W11

W2

T8

T9

DDR0_DQS_P[7]

VSS

CMOS

GND

I/O

U1

DDR0_DQ[60]

DDR2_DQ[59]

RSVD

CMOS

I/O

W3

U10

U11

U2

W33

W34

W35

W36

W37

W38

W39

W4

VCCPLL

PWR

DDR2_DQ[0]

DDR2_DQ[1]

DDR2_DQS_N[0]

DDR2_DQS_P[0]

VSS

CMOS

GND

I/O

VSS

GND

U3

DDR0_DQ[61]

VCCPLL

CMOS

PWR

I/O

U33

U34

U35

U36

U37

U38

U39

U4

DDR2_DQ[4]

RSVD

CMOS

DDR2_DQ[12]

DDR0_DQ[63]

DDR0_DQ[4]

DDR0_DQ[0]

DDR0_DQ[5]

VSS

CMOS

GND

I/O

DDR2_DQ[3]

VSS

CMOS

GND

W40

W41

W42

W43

W5

DDR2_DQ[8]

DDR2_DQ[9]

DDR0_DQ[56]

RSVD

CMOS

I/O

U40

U41

U42

DDR1_DQ[61]

DDR1_DQ[56]

DDR1_DQ[57]

CMOS

I/O

DDR0_DQ[6]

VSS

CMOS

GND

I/O

W6

W7

Datasheet

65

Land Listing

Table 4-2. Land Listing by Land Number

(Sheet 29 of 29)

Land

No.

Buffer

Type

Pin Name

Direction

W8

W9

Y1

VSS

GND

DDR1_DQ[63]

VSS

CMOS

GND

I/O

Y10

Y11

Y2

DDR1_DQ[58]

VSS

CMOS

GND

DDR0_DQ[58]

DDR0_DQ[59]

VSS

CMOS

GND

I/O

Y3

Y33

Y34

Y35

Y36

Y37

Y38

Y39

Y4

DDR1_DQ[3]

DDR1_DQ[2]

VSS

CMOS

GND

I/O

DDR1_DQS_N[0]

DDR1_DQS_P[0]

DDR1_DQ[7]

RSVD

CMOS

I/O

Y40

Y41

Y5

DDR1_DQ[6]

VSS

CMOS

GND

I/O

RSVD

Y6

VSS

GND

Y7

DDR_COMP[1]

DDR1_DQS_P[7]

DDR1_DQS_N[7]

Analog

CMOS

Y8

I/O

Y9

§

66

Datasheet

Signal Descriptions

5 Signal Descriptions

This chapter provides a description of each processor signal.

Table 5-1.

Signal Definitions (Sheet 1 of 4)

Name

Type

Description

Notes

BCLK_DN

BCLK_DP

I

Differential bus clock input to the processor.

Buffered differential bus clock pair to ITP.

BCLK_ITP_DN

BCLK_ITP_DP

O

BPM#[7:0] are breakpoint and performance monitor signals. They are outputs

from the processor that indicate the status of breakpoints and programmable

counters used for monitoring processor performance. BPM#[7:0] should be

connected in a wired OR topology between all packages on a platform. The end

points for the wired OR connections must be terminated.

BPM#[7:0]

I/O

CAT_ERR# indicates that the system has experienced a catastrophic error and

cannot continue to operate. The processor will set this for non-recoverable

machine check errors and other internal unrecoverable error. Since this is an I/

O pin, external agents are allowed to assert this pin which will cause the

processor to take a machine check exception.

CAT_ERR#

COMP0

I/O

I

Impedance compensation must be terminated on the system board using a

precision resistor.

I

QPI_CLKRX_DN

QPI_CLKRX_DP

Intel QPI received clock is the input clock that corresponds to the received data.

QPI_CLKTX_DN

QPI_CLKTX_DP

O

Intel QPI forwarded clock sent with the outbound data.

QPI_CMP[0]

I

Must be terminated on the system board using a precision resistor.

QPI_DRX_DN[19:0] and QPI_DRX_DP[19:0] comprise the differential receive

data for the QPI port. The inbound 20 lanes are connected to another

component’s outbound direction.

QPI_DRX_DN[19:0]

QPI_DRX_DP[19:0]

I

QPI_DTX_DN[19:0] and QPIQPI_DTX_DP[19:0] comprise the differential

transmit data for the QPI port. The outbound 20 lanes are connected to another

component’s inbound direction.

QPI_DTX_DN[19:0]

QPI_DTX_DP[19:0]

O

DBR# is used only in systems where no debug port is implemented on the

system board. DBR# is used by a debug port interposer so that an in-target

probe can drive system reset. If a debug port is implemented in the system,

DBR# is a no connect in the system. DBR# is not a processor signal.

DBR#

I

DDR_COMP[2:0]

DDR_VREF

I

Must be terminated on the system board using precision resistors.

Voltage reference for DDR3

Defines the bank which is the destination for the current Activate, Read, Write,

or Precharge command.

1

DDR{0/1/2}_BA[2:0]

O

DDR{0/1/2}_CAS#

O

Column Address Strobe.

Clock Enable.

DDR{0/1/2}_CKE[3:0]

DDR{0/1/2}_CLK_N[2:0]

DDR{0/1/2}_CLK_P[2:0]

Differential clocks to the DIMM. All command and control signals are valid on

the rising edge of clock.

O

DDR{0/1/2}_CS[1:0]#

DDR{0/1/2}_CS[5:4]#

O

Each signal selects one rank as the target of the command and address.

DDR3 Data bits.

DDR{0/1/2}_DQ[63:0]

I/O

Differential pair, Data Strobe x8. Differential strobes latch data for each DRAM.

Different numbers of strobes are used depending on whether the connected

DRAMs are x4 or x8. Driven with edges in center of data, receive edges are

aligned with data edges.

DDR{0/1/2}_DQS_N[7:0]

DDR{0/1/2}_DQS_P[7:0]

I/O

Datasheet

67

Signal Descriptions

Table 5-1.

Signal Definitions (Sheet 2 of 4)

Name

Type

Description

Notes

Selects the Row address for Reads and writes, and the column address for

activates. Also used to set values for DRAM configuration registers.

DDR{0/1/2}_MA[15:0]

O

Enables various combinations of termination resistance in the target and non-

target DIMMs when data is read or written

DDR{0/1/2}_ODT[3:0]

DDR{0/1/2}_RAS#

O

Row Address Strobe.

Resets DRAMs. Held low on power up, held high during self refresh, otherwise

controlled by configuration register.

DDR{0/1/2}_RESET#

DDR{0/1/2}_WE#

ISENSE

O

I

Write Enable.

Current sense from VRD11.1.

PECI (Platform Environment Control Interface) is the serial sideband interface to

the processor and is used primarily for thermal, power and error management.

Details regarding the PECI electrical specifications, protocols and functions can

be found in the Platform Environment Control Interface Specification.

PECI

I/O

PRDY# is a processor output used by debug tools to determine processor debug

readiness.

PRDY#

PREQ#

O

I/O

PREQ# is used by debug tools to request debug operation of the processor.

PROCHOT# will go active when the processor temperature monitoring sensor

detects that the processor has reached its maximum safe operating

temperature. This indicates that the processor Thermal Control Circuit has been

activated, if enabled. This signal can also be driven to the processor to activate

the Thermal Control Circuit. This signal does not have on-die termination and

must be terminated on the system board.

PROCHOT#

I/O

Processor Power Status Indicator signal. This signal is asserted when maximum

possible processor core current consumption is less than 20A. Assertion of this

signal is an indication that the VR controller does not currently need to be able

to provide ICC above 20A, and the VR controller can use this information to

move to more efficient operation point. This signal will de-assert at least 3.3 us

before the current consumption will exceed 20A. The minimum PSI#

assertion and de-assertion time is 1 BCLK.

PSI#

O

Asserting the RESET# signal resets the processor to a known state and

invalidates its internal caches without writing back any of their contents. Note

some PLL, QPI and error states are not effected by reset and only

VCCPWRGOOD forces them to a known state. For a power-on Reset, RESET#

must stay active for at least one millisecond after VCC and BCLK have reached

their proper specifications. RESET# must not be kept asserted for more than

10 ms while VCCPWRGOOD is asserted. RESET# must be held de-asserted for

at least 1 ms before it is asserted again. RESET# must be held asserted before

VCCPWRGOOD is asserted. This signal does not have on-die termination and

must be terminated on the system board. RESET# is a common clock signal.

RESET#

I

SKTOCC# (Socket Occupied) will be pulled to ground on the processor package.

There is no connection to the processor silicon for this signal. System board

designers may use this signal to determine if the processor is present.

SKTOCC#

O

TCK (Test Clock) provides the clock input for the processor Test Bus (also known

as the Test Access Port).

TCK

I

TDI (Test Data In) transfers serial test data into the processor. TDI provides the

serial input needed for JTAG specification support.

TDI

TDO (Test Data Out) transfers serial test data out of the processor. TDO

provides the serial output needed for JTAG specification support.

TDO

O

I

TESTLOW must be connected to ground through a resistor for proper processor

operation.

TESTLOW

68

Datasheet

Signal Descriptions

Table 5-1.

Signal Definitions (Sheet 3 of 4)

Name

Type

Description

Notes

Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction

temperature has reached a level beyond which permanent silicon damage may

occur. Measurement of the temperature is accomplished through an internal

thermal sensor. Upon assertion of THERMTRIP#, the processor will shut off its

internal clocks (thus halting program execution) in an attempt to reduce the

processor junction temperature. To further protect the processor, its core

THERMTRIP#

O

voltage (V ), V

V

, and V

must be removed following the assertion of

CC

TTA TTD

DDQ

THERMTRIP#. Once activated, THERMTRIP# remains latched until RESET# is

asserted. While the assertion of the RESET# signal may de-assert

THERMTRIP#, if the processor junction temperature remains at or above the

trip level, THERMTRIP# will again be asserted after RESET# is de-asserted.

TMS (Test Mode Select) is a JTAG specification support signal used by debug

tools.

TMS

I

TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be

driven low during power on Reset.

TRST#

VCC

I

Power for processor core.

VCC_SENSE and VSS_SENSE provide an isolated, low impedance connection to

the processor core power and ground. They can be used to sense or measure

voltage near the silicon.

VCC_SENSE

VSS_SENSE

O

VCCPLL

I

Power for on-die PLL filter.

VCCPWRGOOD (Power Good) is a processor input. The processor requires this

signal to be a clean indication that BCLK, V , V

, V

and V

supplies

CC

CCPLL

TTA

TTD

are stable and within their specifications. 'Clean' implies that the signal will

remain low (capable of sinking leakage current), without glitches, from the time

that the power supplies are turned on until they come within specification. The

signal must then transition monotonically to a high state. VCCPWRGOOD can be

driven inactive at any time, but BCLK and power must again be stable before a

subsequent rising edge of VCCPWRGOOD. In addition at the time

VCCPWRGOOD is asserted RESET# must be active. The PWRGOOD signal must

be supplied to the processor. It should be driven high throughout boundary scan

operation.

VCCPWRGOOD

I

VDDPWRGOOD is an input that indicates the V

power supply is good. The

DDQ

processor requires this signal to be a clean indication that the V

power

DDQ

supply is stable and within specifications. "Clean" implies that the signal will

remain low (capable of sinking leakage current), without glitches, from the time

that the Vddq supply is turned on until it comes within specification. The signals

must then transition monotonically to a high state.

VDDPWRGOOD

I

The PwrGood signal must be supplied to the processor.

VID[7:0] (Voltage ID) are used to support automatic selection of power supply

voltages (V ). The voltage supply for these signals must be valid before the VR

CC

can supply V to the processor. Conversely, the VR output must be disabled

CC

until the voltage supply for the VID signals become valid. The VR must supply

the voltage that is requested by the signals, or disable itself.

VID7 and VID6 should be tied separately to V using a 1 kresistor during

SS

VID[7:6]

reset (This value is latched on the rising edge of VTTPWRGOOD)

VID[5:3]/CSC[2:0]

VID[2:0]/MSID[2:0]

I/O

MSID[2:0] — MSID[2:0] is used to indicate to the processor whether the

platform supports a particular TDP. A processor will only boot if the MSID[2:0]

pins are strapped to the appropriate setting on the platform (see Table 2-2 for

MSID encodings). In addition, MSID protects the platform by preventing a

higher power processor from booting in a platform designed for lower power

processors.

CSC[2:0] — Current Sense Configuration bits, for ISENSE gain setting. This

value is latched on the rising edge of VTTPWRGOOD.

Power for the analog portion of the integrated memory controller, QPI and

Shared Cache.

VTTA

VTTD

I

Power for the digital portion of the integrated memory controller, QPI and

Shared Cache.

Datasheet

69

Signal Descriptions

Table 5-1.

Signal Definitions (Sheet 4 of 4)

Name

Type

Description

Notes

VTT_VID[2:4] (VTTVoltage ID) are used to support automatic selection of power

supply voltages (V ).

TT

VTT_VID[4:2]

O

VTT_SENSE and VSS_SENSE_VTT provide an isolated, low impedance

VTT_SENSE

VSS_SENSE_VTT

O

connection to the processor V voltage and ground. They can be used to sense

TT

or measure voltage near the silicon.

The processor requires this input signal to be a clean indication that the V

TT

power supply is stable and within specifications. 'Clean' implies that the signal

will remain low (capable of sinking leakage current), without glitches, from the

time that the power supplies are turned on until they come within specification.

The signal must then transition monotonically to a high state. Note that it is not

valid for VTTPWRGOOD to be de-asserted while VCCPWRGOOD is asserted.

VTTPWRGOOD

I

Notes:

1.

DDR{0/1/2} refers to DDR3 Channel 0, DDR3 Channel 1, and DDR3 Channel 2.

§

70

Datasheet

Thermal Specifications

6 Thermal Specifications

6.1

Package Thermal Specifications

The processor requires a thermal solution to maintain temperatures within its operating

limits. Any attempt to operate the processor outside these operating limits may result

in permanent damage to the processor and potentially other components within the

system. Maintaining the proper thermal environment is key to reliable, long-term

system operation.

A complete solution includes both component and system level thermal management

features. Component level thermal solutions can include active or passive heatsinks

attached to the processor integrated heat spreader (IHS).

This chapter provides data necessary for developing a complete thermal solution. For

more information on designing a component level thermal solution, refer to the

appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2).

6.1.1

Thermal Specifications

The processor thermal specification uses the on-die Digital Thermal Sensor (DTS) value

reported using the PECI interface for all processor temperature measurements. The

DTS is a factory calibrated, analog to digital thermal sensor. As a result, it will no longer

be necessary to measure the processors case temperature. Consequently, there will be

no need for a Thermal Profile specification defining the relationship between the

processors T_CASEand power dissipation.

Note:

Unless otherwise specified, the term “DTS” refers to the DTS value returned by the

PECI interface gettemp command.

A thermal solution that was verified compliant to the processor case temperature

thermal profile at the customer defined boundary conditions is expected to be

compliant with this update. No redesign of the thermal solution should be necessary. A

fan speed control algorithms that was compliant to the previous thermal requirements

is also expected to be compliant with this specification. The fan speed control algorithm

can be updated to use the additional information to optimize acoustics.

To allow the optimal operation and long-term reliability of Intel processor-based

systems, the processor thermal solution must deliver the specified thermal solution

performance in response to the DTS sensor value. The thermal solution performance

will be measured using a Thermal Test Vehicle (TTV). See Table 6-1 and Figure 6-1 for

the TTV thermal profile and Table 6-3 for the required thermal solution performance

table when DTS values are greater than T_CONTROL. Thermal solutions not designed to

provide this level of thermal capability may affect the long-term reliability of the

processor and system. When the DTS value is less than T_CONTROL, the thermal solution

performance is not defined and the fans may be slowed down. This is unchanged from

the prior specification. For more details on thermal solution design, refer to the

appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2).

The processors implement a methodology for managing processor temperatures, which

is intended to support acoustic noise reduction through fan speed control and to assure

processor reliability. Selection of the appropriate fan speed is based on the relative

temperature data reported by the processor’s Digital Temperature Sensor (DTS). The

DTS can be read using the Platform Environment Control Interface (PECI) as described

Datasheet

71

Thermal Specifications

in Section 6.3. The temperature reported over PECI is always a negative value and

represents a delta below the onset of thermal control circuit (TCC) activation, as

indicated by PROCHOT# (see Section 6.2, Processor Thermal Features). Systems that

implement fan speed control must be designed to use this data. Systems that do not

alter the fan speed only need to ensure the thermal solution provides the _CAthat

meets the TTV thermal profile specifications.

A single integer change in the PECI value corresponds to approximately 1 °C change in

processor temperature. Although each processors DTS is factory calibrated, the

accuracy of the DTS will vary from part to part and may also vary slightly with

temperature and voltage. In general, each integer change in PECI should equal a

temperature change between 0.9 °C and 1.1 °C.

Analysis indicates that real applications are unlikely to cause the processor to consume

maximum power dissipation for sustained time periods. Intel recommends that

complete thermal solution designs target the Thermal Design Power (TDP), instead of

the maximum processor power consumption. The Adaptive Thermal Monitor feature is

intended to help protect the processor in the event that an application exceeds the TDP

recommendation for a sustained time period. For more details on this feature, refer to

Section 6.2. Refer to the appropriate processor Thermal and Mechanical Design Guide

(see Section 1.2) for details on system thermal solution design, thermal profiles and

environmental considerations.

Table 6-1.

Processor Thermal Specifications

Target Psi-ca

Thermal

Design Power

(W)

Idle

Minimum

TTV T

Maximum TTV

Core

Frequency

Using

Processor

Power

T

Notes

CASE

(°C)

Processor TTV

6

(W)

(°C)

5

(°C/W)

i7-975

i7-965

i7-960

i7-950

i7-940

i7-930

i7-920

3.33 GHz

3.20 GHz

3.06 GHz

2.93 GHz

2.80 GHz

2.66 GHz

130

12

15

5

0.222

See Figure 6-1;

Table 6-2

1, 2, 3, 4,

5

Notes:

1.

These values are specified at V

for all processor frequencies. Systems must be designed to ensure

CC_MAX

the processor is not to be subjected to any static V and I combination wherein V exceeds V at

specified I . Refer to the loadline specifications in Chapter 2.

CC

CC_MAX

CC

2.

3.

4.

Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the

maximum power that the processor can dissipate. TDP is measured at the TCC activation temperature.

These specifications are based on initial silicon characterization. These specifications may be further

updated as more characterization data becomes available.

Power specifications are defined at all VIDs found in Table 2-1. The processor may be shipped under

multiple VIDs for each frequency.

5.

6.

Target -ca Using the processor TTV (°C/W) is based on a T

of 39 °C.

AMBIENT

Processor idle power is specified under the lowest possible idle state: processor package C6 state.

Achieving processor package C6 state is not supported by all chipsets. See the Intel X58 Express Chipset

Datasheet for more details.

72

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Thermal Specifications

Figure 6-1. Processor Thermal Profile

70.0

y = 43.2 + 0.19 * P

65.0

60.0

55.0

50.0

45.0

40.0

0

10

20

30

40

50

60

70

80

90

100

110

120

130

TTV Power (W)

Notes:

1.

2.

Refer to Table 6-2 for discrete points that constitute the thermal profile.

Refer to the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2) for system

and environmental implementation details.

3.

The thermal profile is based on data from the Thermal Test Vehicle (TTV).

Table 6-2.

Processor Thermal Profile

Power

(W)

T

Power

(W)

T

Power

(W)

T

Power

(W)

T

CASE_MAX

(C)

CASE_MAX

(C)

CASE_MAX

(C)

0

43.2

43.6

44.0

44.3

44.7

45.1

45.5

45.9

46.2

46.6

47.0

47.4

47.8

48.1

48.5

48.9

49.3

34

36

38

40

42

44

46

48

50

52

54

56

58

60

62

64

66

49.7

50.0

50.4

50.8

51.2

51.6

51.9

52.3

52.7

53.1

53.5

53.8

54.2

54.6

55.0

55.4

55.7

68

70

72

74

76

78

80

82

84

86

88

90

92

94

96

98

56.1

56.5

56.9

57.3

57.6

58.0

58.4

58.8

59.2

59.5

59.9

60.3

60.7

61.1

61.4

61.8

100

102

104

106

108

110

112

114

116

118

120

122

124

126

128

130

62.2

62.6

63.0

63.3

63.7

64.1

64.5

64.9

65.2

65.6

66.0

66.4

66.8

67.1

67.5

67.9

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

Datasheet

73

Thermal Specifications

6.1.1.1

Specification for Operation Where Digital Thermal Sensor Exceeds

CONTROL

T

When the DTS value is less than T_CONTROL, the fan speed control algorithm can reduce

the speed of the thermal solution fan. This remains the same as with the previous

guidance for fan speed control.

During operation where the DTS value is greater than T_CONTROL, the fan speed control

algorithm must drive the fan speed to meet or exceed the target thermal solution

performance (_CA) shown in Table 6-3. The ability to monitor the inlet temperature

(T_AMBIENT) is required to fully implement the specification as the target _CAis explicitly

defined for various ambient temperature conditions. See the appropriate processor

Thermal and Mechanical Design Guidelines (see Section 1.2) for details on

characterizing the fan speed to _CAand ambient temperature measurement.

Table 6-3.

Thermal Solution Performance above T_CONTROL

1

2

3

T



at DTS = T

 at DTS = -1

CA

AMBIENT

43.2

42.0

41.0

40.0

39.0

38.0

37.0

36.0

35.0

34.0

33.0

32.0

31.0

30.0

29.0

28.0

27.0

26.0

25.0

24.0

23.0

22.0

21.0

20.0

19.0

18.0

CA

CONTROL

0.190

0.206

0.219

0.232

0.245

0.258

0.271

0.284

0.297

0.310

0.323

0.336

0.349

0.362

0.375

0.388

0.401

0.414

0.427

0.440

0.453

0.466

0.479

0.492

0.505

0.519

0.190

0.199

0.207

0.215

0.222

0.230

0.238

0.245

0.253

0.261

0.268

0.276

0.284

0.292

0.299

0.307

0.315

0.322

0.330

0.338

0.345

0.353

0.361

0.368

0.376

0.384

Notes:

1.

2.

The ambient temperature is measured at the inlet to the processor thermal solution.

This column can be expressed as a function of T

by the following equation:

AMBIENT

Y

= 0.19 + (43.2 – T

) * 0.013

CA

AMBIENT

3.

This column can be expressed as a function of T

= 0.19 + (43.2 – T ) * 0.0077

by the following equation:

AMBIENT

Y

CA

AMBIENT

74

Datasheet

Thermal Specifications

6.1.2

Thermal Metrology

The minimum and maximum TTV case temperatures (T_CASE) are specified in Table 6-1,

and Table 6-2 and are measured at the geometric top center of the thermal test vehicle

integrated heat spreader (IHS). Figure 6-2 illustrates the location where T_CASE

temperature measurements should be made. For detailed guidelines on temperature

measurement methodology and attaching the thermocouple, refer to the appropriate

processor Thermal and Mechanical Design Guidelines (see Section 1.2).

Figure 6-2. Thermal Test Vehicle (TTV) Case Temperature (T_CASE) Measurement Location

Notes:

1.

2.

3.

4.

5.

6.

7.

8.

Figure is not to scale and is for reference only.

B1: Max = 45.07 mm, Min = 44.93 mm.

B2: Max = 42.57 mm, Min = 42.43 mm.

C1: Max = 39.1 mm, Min = 38.9 mm.

C2: Max = 36.6 mm, Min = 36.4 mm.

C3: Max = 2.3 mm, Min = 2.2 mm

C4: Max = 2.3 mm, Min = 2.2 mm.

Refer to the appropriate Thermal and Mechanical Design Guide (see Section 1.2) for instructions on

thermocouple installation on the processor TTV package.

Datasheet

75

Thermal Specifications

6.2

Processor Thermal Features

6.2.1

Processor Temperature

A new feature in the Intel Core™ i7-900 desktop processor Extreme Edition series and

Intel Core™ i7-900 desktop processor series is a software readable field in the

IA32_TEMPERATURE_TARGET register that contains the minimum temperature at

which the TCC will be activated and PROCHOT# will be asserted. The TCC activation

temperature is calibrated on a part-by-part basis and normal factory variation may

result in the actual TCC activation temperature being higher than the value listed in the

register. TCC activation temperatures may change based on processor stepping,

frequency or manufacturing efficiencies.

Note:

There is no specified correlation between DTS temperatures and processor case

temperatures; therefore it is not possible to use this feature to ensure the processor

case temperature meets the Thermal Profile specifications.

6.2.2

Adaptive Thermal Monitor

The Adaptive Thermal Monitor feature provides an enhanced method for controlling the

processor temperature when the processor silicon exceeds the Thermal Control Circuit

(TCC) activation temperature. Adaptive Thermal Monitor uses TCC activation to reduce

processor power using a combination of methods. The first method (Frequency/VID

control, similar to Thermal Monitor 2 (TM2) in previous generation processors) involves

the processor reducing its operating frequency (using the core ratio multiplier) and

input voltage (using the VID signals). This combination of lower frequency and VID

results in a reduction of the processor power consumption. The second method (clock

modulation, known as Thermal Monitor 1 (TM1) in previous generation processors)

reduces power consumption by modulating (starting and stopping) the internal

processor core clocks. The processor intelligently selects the appropriate TCC method

to use on a dynamic basis. BIOS is not required to select a specific method (as with

previous-generation processors supporting TM1 or TM2). The temperature at which

Adaptive Thermal Monitor activates the Thermal Control Circuit is factory calibrated and

is not user configurable. Snooping and interrupt processing are performed in the

normal manner while the TCC is active.

When the TCC activation temperature is reached, the processor will initiate TM2 in

attempt to reduce its temperature. If TM2 is unable to reduce the processor

temperature then TM1 will be also be activated. TM1 and TM2 will work together (clocks

will be modulated at the lowest frequency ratio) to reduce power dissipation and

temperature.

With a properly designed and characterized thermal solution, it is anticipated that the

TCC would only be activated for very short periods of time when running the most

power intensive applications. The processor performance impact due to these brief

periods of TCC activation is expected to be so minor that it would be immeasurable. An

under-designed thermal solution that is not able to prevent excessive activation of the

TCC in the anticipated ambient environment may cause a noticeable performance loss,

and in some cases may result in a T_CASEthat exceeds the specified maximum

temperature and may affect the long-term reliability of the processor. In addition, a

thermal solution that is significantly under-designed may not be capable of cooling the

processor even when the TCC is active continuously. Refer to the appropriate processor

Thermal and Mechanical Design Guide (see Section 1.2) for information on designing a

compliant thermal solution.

The Thermal Monitor does not require any additional hardware, software drivers, or

interrupt handling routines. The following sections provide more details on the different

TCC mechanisms used by the Intel Core™ i7-900 desktop processor Extreme Edition

series and Intel Core™ i7-900 desktop processor series.

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Datasheet

Thermal Specifications

6.2.2.1

Frequency/VID Control

When the Digital Temperature Sensor (DTS) reaches a value of 0 (DTS temperatures

reported using PECI may not equal zero when PROCHOT# is activated, see Section 6.3

for further details), the TCC will be activated and the PROCHOT# signal will be

asserted. This indicates the processor temperature has met or exceeded the factory

calibrated trip temperature and it will take action to reduce the temperature.

Upon activation of the TCC, the processor will stop the core clocks, reduce the core

ratio multiplier by 1 ratio and restart the clocks. All processor activity stops during this

frequency transition, which occurs within 2 us. Once the clocks have been restarted at

the new lower frequency, processor activity resumes while the voltage requested by the

VID lines is stepped down to the minimum possible for the particular frequency.

Running the processor at the lower frequency and voltage will reduce power

consumption and should allow the processor to cool off. If after 1 ms the processor is

still too hot (the temperature has not dropped below the TCC activation point, DTS

still = 0 and PROCHOT is still active), then a second frequency and voltage transition

will take place. This sequence of temperature checking and Frequency/VID reduction

will continue until either the minimum frequency has been reached or the processor

temperature has dropped below the TCC activation point.

If the processor temperature remains above the TCC activation point even after the

minimum frequency has been reached, then clock modulation (described below) at that

minimum frequency will be initiated.

There is no end user software or hardware mechanism to initiate this automated TCC

activation behavior.

A small amount of hysteresis has been included to prevent rapid active/inactive

transitions of the TCC when the processor temperature is near the TCC activation

temperature. Once the temperature has dropped below the trip temperature, and the

hysteresis timer has expired, the operating frequency and voltage transition back to

the normal system operating point using the intermediate VID/frequency points.

Transition of the VID code will occur first, to insure proper operation as the frequency is

increased. Refer to Table 6-3 for an illustration of this ordering.

Figure 6-3. Frequency and Voltage Ordering

Temperature

Frequency

f_MAX

f₁

f₂

VIDf_MAX

VIDf₁

VIDf₂

VID

PROCHOT#

Datasheet

77

Thermal Specifications

6.2.2.2

Clock Modulation

Clock modulation is a second method of thermal control available to the processor.

Clock modulation is performed by rapidly turning the clocks off and on at a duty cycle

that should reduce power dissipation by about 50% (typically a 30–50% duty cycle).

Clocks often will not be off for more than 32 µs when the TCC is active. Cycle times are

independent of processor frequency. The duty cycle for the TCC, when activated by the

Thermal Monitor, is factory configured and cannot be modified.

It is possible for software to initiate clock modulation with configurable duty cycles.

A small amount of hysteresis has been included to prevent rapid active/inactive

transitions of the TCC when the processor temperature is near its maximum operating

temperature. Once the temperature has dropped below the maximum operating

temperature, and the hysteresis timer has expired, the TCC goes inactive and clock

modulation ceases.

6.2.2.3

Immediate Transiton to combined TM1 and TM2

As mentioned above, when the TCC is activated, the processor will sequentially step

down the ratio multipliers and VIDs in an attempt to reduce the silicon temperature. If

the temperature continues to increase and exceeds the TCC activation temperature by

approximately 5 °C before the lowest ratio/VID combination has been reached, then

the processor will immediately transition to the combined TM1/TM2 condition. The

processor will remain in this state until the temperature has dropped below the TCC

activation point. Once below the TCC activation temperature, TM1 will be discontinued

and TM2 will be exited by stepping up to the appropriate ratio/VID state.

6.2.2.4

Critical Temperature Flag

If TM2 is unable to reduce the processor temperature, then TM1 will be also be

activated. TM1 and TM2 will then work together to reduce power dissipation and

temperature. It is expected that only a catastrophic thermal solution failure would

create a situation where both TM1 and TM2 are active.

If TM1 and TM2 have both been active for greater than 20 ms and the processor

temperature has not dropped below the TCC activation point, then the Critical

Temperature Flag in the IA32_THERM_STATUS MSR will be set. This flag is an indicator

of a catastrophic thermal solution failure and that the processor cannot reduce its

temperature. Unless immediate action is taken to resolve the failure, the processor will

probably reach the Thermtrip temperature (see Section 6.2.3 Thermtrip Signal) within

a short time. To prevent possible permanent silicon damage, Intel recommends

removing power from the processor within ½ second of the Critical Temperature Flag

being set.

6.2.2.5

PROCHOT# Signal

An external signal, PROCHOT# (processor hot), is asserted when the processor core

temperature has exceeded its specification. If Adaptive Thermal Monitor is enabled

(note it must be enabled for the processor to be operating within specification), the

TCC will be active when PROCHOT# is asserted.

The processor can be configured to generate an interrupt upon the assertion or de-

assertion of PROCHOT#.

Although the PROCHOT# signal is an output by default, it may be configured as bi-

directional. When configured in bi-directional mode, it is either an output indicating the

processor has exceeded its TCC activation temperature or it can be driven from an

78

Datasheet

Thermal Specifications

external source (e.g., a voltage regulator) to activate the TCC. The ability to activate

the TCC using PROCHOT# can provide a means for thermal protection of system

components.

As an output, PROCHOT# (Processor Hot) will go active when the processor

temperature monitoring sensor detects that one or more cores has reached its

maximum safe operating temperature. This indicates that the processor Thermal

Control Circuit (TCC) has been activated, if enabled. As an input, assertion of

PROCHOT# by the system will activate the TCC for all cores. TCC activation when

PROCHOT# is asserted by the system will result in the processor immediately

transitioning to the minimum frequency and corresponding voltage (using Freq/VID

control). Clock modulation is not activated in this case. The TCC will remain active until

the system de-asserts PROCHOT#.

Use of PROCHOT# in bi-directional mode can allow VR thermal designs to target

maximum sustained current instead of maximum current. Systems should still provide

proper cooling for the VR, and rely on PROCHOT# only as a backup in case of system

cooling failure. The system thermal design should allow the power delivery circuitry to

operate within its temperature specification even while the processor is operating at its

Thermal Design Power.

6.2.3

THERMTRIP# Signal

Regardless of whether or not Adaptive Thermal Monitor is enabled, in the event of a

catastrophic cooling failure, the processor will automatically shut down when the silicon

has reached an elevated temperature (refer to the THERMTRIP# definition in

Table 5-1). THERMTRIP# activation is independent of processor activity. The

temperature at which THERMTRIP# asserts is not user configurable and is not software

visible.

6.3

Platform Environment Control Interface (PECI)

6.3.1

Introduction

The Platform Environment Control Interface (PECI) is a one-wire interface that provides

a communication channel between the Intel processor and chipset components to

external monitoring devices. The processor implements a PECI interface to allow

communication of processor thermal and other information to other devices on the

platform. The processor provides a digital thermal sensor (DTS) for fan speed control.

The DTS is calibrated at the factory to provide a digital representation of relative

processor temperature. Instantaneous temperature readings from the DTS are

available using the IA32_THERM_STATUS MSR; averaged DTS values are read using

the PECI interface.

The PECI physical layer is a self-clocked one-wire bus that begins each bit with a

driven, rising edge from an idle level near zero volts. The duration of the signal driven

high depends on whether the bit value is a logic '0' or logic '1'. PECI also includes

variable data transfer rate established with every message. The single wire interface

provides low board routing overhead for the multiple load connections in the congested

routing area near the processor and chipset components. Bus speed, error checking,

and low protocol overhead provides adequate link bandwidth and reliability to transfer

critical device operating conditions and configuration information.

Datasheet

79

Thermal Specifications

6.3.1.1

6.3.1.2

Fan Speed Control with Digital Thermal Sensor

Fan speed control solutions use a value stored in the static variable, T_CONTROL. The DTS

temperature data, which is delivered over PECI (in response to a GetTemp0()

command), is compared to this T_CONTROLreference. The DTS temperature is reported

as a relative value versus an absolute value. The temperature reported over PECI is

always a negative value and represents a delta below the onset of thermal control

circuit (TCC) activation, as indicated by PROCHOT#. Therefore, as the temperature

approaches TCC activation, the value approaches zero degrees.

Processor Thermal Data Sample Rate and Filtering

The processor digital thermal sensor (DTS) provides an improved capability to monitor

device hot spots, which inherently leads to more varying temperature readings over

short time intervals. To reduce the sample rate requirements on PECI and improve

thermal data stability versus. time the processor DTS implements an averaging

algorithm that filters the incoming data. This filter is expressed mathematically as:

PECI(t) = PECI(t–1)+1/(2^^X)*[Temp – PECI(t–1)]

Where: PECI(t) is the new averaged temperature; PECI(t-1) is the previous

averaged temperature; Temp is the raw temperature data from the DTS; X is the

Thermal Averaging Constant (TAC)

Note:

Only values read using the PECI interface are averaged. Temperature values read using

the IA32_THERM_STATUS MSR are not averaged.

The Thermal Averaging Constant is a BIOS configurable value that determines the time

in milliseconds over which the DTS temperature values are averaged. Short averaging

times will make the averaged temperature values respond more quickly to DTS

changes. Long averaging times will result in better overall thermal smoothing but also

incur a larger time lag between fast DST temperature changes and the value read using

PECI. Refer to the appropriate processor Thermal and Mechanical Design Guidelines

(see Section 1.2) for further details on the Data Filter and the Thermal Averaging

Constant.

Within the processor, the DTS converts an analog signal into a digital value

representing the temperature relative to TCC activation. The conversions are in

integers with each single number change corresponding to approximately 1 °C. DTS

values reported using the internal processor MSR will be in whole integers.

As a result of the averaging function described above, DTS values reported over PECI

will include a 6-bit fractional value. Under typical operating conditions, where the

temperature is close to T_CONTROL, the fractional values may not be of interest. But when

the temperature approaches zero, the fractional values can be used to detect the

activation of the TCC. An averaged temperature value between 0 and 1 can only occur

if the TCC has been activated during the averaging window. As TCC activation time

increases, the fractional value will approach zero. Fan control circuits can detect this

situation and take appropriate action as determined by the system designers. Of

course, fan control chips can also monitor the PROCHOT# pin to detect TCC activation

using a dedicated input pin on the package. Further details on how the Thermal

Averaging Constant influences the fractional temperature values are available in the

Thermal Design Guide.

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Datasheet

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6.3.2

PECI Specifications

6.3.2.1

PECI Device Address

The PECI register resides at address 30h.

6.3.2.2

PECI Command Support

The processor supports the PECI commands listed in Table 6-4.

Table 6-4.

Supported PECI Command Functions and Codes

Command

Code

Comments

Function

Ping()

N/A

This command targets a valid PECI device address followed by zero Write

Length and zero Read Length.

GetTemp0()

01h

Write Length: 1

Read Length: 2

Returns the temperature of the processor in Domain 0

6.3.2.3

PECI Fault Handling Requirements

PECI is largely a fault tolerant interface, including noise immunity and error checking

improvements over other comparable industry standard interfaces. The PECI client is

as reliable as the device that it is embedded in, and thus given operating conditions

that fall under the specification. The PECI will always respond to requests and the

protocol itself can be relied upon to detect any transmission failures. There are,

however, certain scenarios where the PECI is know to be unresponsive. Prior to a power

on RESET# and during RESET# assertion, PECI is not ensured to provide reliable

thermal data. System designs should implement a default power-on condition that

ensures proper processor operation during the time frame when reliable data is not

available using PECI.

To protect platforms from potential operational or safety issues due to an abnormal

condition on PECI, the Host controller should take action to protect the system from

possible damaging states. If the Host controller cannot complete a valid PECI

transactions of GetTemp0() with a given PECI device over 3 consecutive failed

transactions or a one second maximum specified interval, then it should take

appropriate actions to protect the corresponding device and/or other system

components from overheating. The host controller may also implement an alert to

software in the event of a critical or continuous fault condition.

6.3.2.4

PECI GetTemp0() Error Code Support

The error codes supported for the processor GetTemp() command are listed in

Table 6-5.

GetTemp0() Error Codes

Error Code

8000h

Description

General sensor error

Datasheet

81

Thermal Specifications

6.4

Storage Conditions Specifications

Environmental storage condition limits define the temperature and relative humidity

limits to which the device is exposed to while being stored. The specified storage

conditions are for component level prior to board attach (see following notes on post

board attach limits).

Table 6-6 specifies absolute maximum and minimum storage temperature limits which

represent the maximum or minimum device condition beyond which damage, latent or

otherwise, may occur. The table also specifies sustained storage temperature, relative

humidity, and time-duration limits. At conditions outside sustained limits, but within

absolute maximum and minimum ratings, quality and reliability may be affected. These

conditions should not be exceeded in storage or transportation.

Table 6-6.

Storage Conditions

Symbol

Parameter

Min

Max

Notes

T

The non-operating device storage

temperature. Damage (latent or otherwise)

may occur when subjected to for any length

of time.

ABSOLUTE STORAGE

-55 °C

125 °C

1, 2, 3

T

The ambient storage temperature limit (in

shipping media) for a sustained period of

time

SUSTAINED STORAGE

-5 °C

40 °C

4, 5

RH

The maximum device storage relative

humidity for a sustained period of time

SUSTAINED STORAGE

60% @ 24°C

5, 6

6

Time

A prolonged or extended period of time;

typically associated with customer shelf life.

SUSTAINED STORAGE

0 months

6 months

Notes:

1.

2.

3.

4.

Refers to a component device that is not assembled in a board or socket that is not to be electrically

connected to a voltage reference or I/O signals.

Specified temperatures are based on data collected. Exceptions for surface mount reflow are specified in by

applicable JEDEC standard and MAS document. Non-adherence may affect processor reliability.

T

applies to unassembled component only and does not apply to the shipping media,

ABSOLUTE STORAGE

moisture barrier bags, or desiccant.

Intel branded board products are certified to meet the following temperature and humidity limits that are

given as an example only (Non-Operating Temperature limit: -40° C to 70° C and Humidity: 50% to 90%

non-condensing with a maximum wet bulb of 28° C) Post board attach storage temperature limits are not

specified for non-Intel branded boards.

5.

6.

The JEDEC, J-JSTD-020 moisture level rating and associated handling practices apply to all moisture

sensitive devices removed from the moisture barrier bag.

Nominal temperature and humidity conditions and durations are given and tested within the constraints

imposed by T

and customer shelf live in appl9icable Intel box and bags.

SUSTAINED

§

82

Datasheet

Features

7 Features

7.1

Power-On Configuration (POC)

Several configuration options can be configured by hardware. For electrical

specifications on these options, refer to Chapter 2. Note that request to execute BIST is

not selected by hardware but is passed across the Intel QPI link during initialization.

The sampled information configures the processor for subsequent operation. These

configuration options cannot be changed except by another reset. All resets reconfigure

the processor; for reset purposes, the processor does not distinguish between a

"warm" reset and a “power-on” reset.

Table 7-1.

Power On Configuration Signal Options

Configuration Option

Signal

1, 2

MSID

CSC

VID[2:0]/MSID[2:0]

1, 2

VID[5:3]/CSC[2:0]

Notes:

1.

2.

Latched when VTTPWRGOOD is asserted and all internal power good conditions are met.

See the signal definitions in Table 6-1 for the description of MSID and CSC.

7.2

Clock Control and Low Power States

The processor supports low power states at the individual thread, core, and package

level for optimal power management. The processor implements software interfaces for

requesting low power states: MWAIT instruction extensions with sub-state hints, the

HLT instruction (for C1 and C1E) and P_LVLx reads to the ACPI P_BLK register block

mapped in the processor’s I/O address space. The P_LVLx I/O reads are converted to

equivalent MWAIT C-state requests inside the processor and do not directly result in

I/O reads to the system. The P_LVLx I/O Monitor address does not need to be set up

before using the P_LVLx I/O read interface.

Software may make C-state requests by using a legacy method involving I/O reads

from the ACPI-defined processor clock control registers, referred to as P_LVLx. This

feature is designed to provide legacy support for operating systems that initiate C-state

transitions using access to pre-defined ICH registers. The base P_LVLx register is

P_LVL2, corresponding to a C3 request; P_LVL3 is C6.

P_LVLx is limited to a subset of C-states. For Example, P_LVL8 is not supported and will

not cause an I/O redirection to a C8 request. Instead, it will fall through like a normal

I/O instruction. The range of I/O addresses that may be converted into C-state

requests is also defined in the PMG_IO_CAPTURE MSR, in the ‘C-state Range’ field. This

field maybe written by BIOS to restrict the range of I/O addresses that are trapped and

redirected to MWAIT instructions. Note that when I/O instructions are used, no MWAIT

substates can be defined, as therefore the request defaults to have a sub-state or zero,

but always assumes the ‘break on IF==0’ control that can be selected using ECX with

an MWAIT instruction.

Datasheet

83

Features

Figure 7-1. Power States

C0

MWAIT C1,

HLT

MWAIT C6,

2

I/O C6

2

MWAIT C1,

HLT (C1E

enabled)

MWAIT C3,

I/O C3

C E¹

C1¹

1

C3

C6

1. No transition to C0 is needed to service a snoop when in C1 or C1E.

,

.

2. Transitions back to C0 occur on an interrupt or on access to monitored address (if state was entered via MWAIT).

.

7.2.1

Thread and Core Power State Descriptions

Individual threads may request low power states. Core power states are automatically

resolved by the processor as shown in Table 7-2.

Table 7-2.

Coordination of Thread Power States at the Core Level

Thread1 State

Core State

C0

C1¹

C3

C6

C0

C1¹

C3

1

C1

Thread0

State

1

C1

C3

C6

1

C1

C6

Notes:

1. If enabled, state will be C1E.

7.2.1.1

7.2.1.2

C0 State

This is the normal operating state in the processor.

C1/C1E State

C1/C1E is a low power state entered when all threads within a core execute a HLT or

MWAIT(C1E) instruction. The processor thread will transition to the C0 state upon

occurrence of an interrupt or an access to the monitored address if the state was

entered using the MWAIT instruction. RESET# will cause the processor to initialize

itself.

A System Management Interrupt (SMI) handler will return execution to either Normal

state or the C1 state. See the Intel^®64 and IA-32 Architecture Software Developer's

Manuals, Volume III: System Programmer's Guide for more information.

84

Datasheet

Features

While in C1/C1E state, the processor will process bus snoops and snoops from the

other threads.

7.2.1.3

C3 State

Individual threads of the processor can enter the C3 state by initiating a P_LVL2 I/O

read to the P_BLK or an MWAIT(C3) instruction. Before entering core C3, the processor

flushes the contents of its caches. Except for the caches, the processor core maintains

all its architectural state while in the C3 state. All of the clocks in the processor core are

stopped in the C3 state.

Because the core’s caches are flushed, the processor keeps the core in the C3 state

when the processor detects a snoop on the Intel QPI Link or when another logical

processor in the same package accesses cacheable memory. The processor core will

transition to the C0 state upon occurrence of an interrupt. RESET# will cause the

processor core to initialize itself.

7.2.1.4

C6 State

Individual threads of the processor can enter the C6 state by initiating a P_LVL3 read to

the P_BLK or an MWAIT(C6) instruction. Before entering Core C6, the processor saves

core state data (such as, registers) to the last level cache. This data is retired after

exiting core C6. The processor achieves additional power savings in the core C6 state.

7.2.2

Package Power State Descriptions

The package supports C0, C3, and C6 power states. Note that there is no package C1

state. The package power state is automatically resolved by the processor depending

on the core power states and permission from the rest of the system as described in

the following sections.

7.2.2.1

Package C0 State

This is the normal operating state for the processor. The processor remains in the

Normal state when at least one of its cores is in the C0 or C1 state or when another

component in the system has not granted permission to the processor to go into a low

power state. Individual components of the processor may be in low power states while

the package is in C0.

7.2.2.2

Package C1/C1E State

The package will enter the C1/C1E low power state when at least one core is in the

C1/C1E state and the rest of the cores are in the C1/C1E or lower power state. The

processor will also enter the C1/C1E state when all cores are in a power state lower

than C1/C1E but the package low power state is limited to C1/C1E using the

PMG_CST_CONFIG_CONTROL MSR. In the C1E state, the processor will automatically

transition to the lowest power operating point (lowest supported voltage and associated

frequency). When entering the C1E state, the processor will first switch to the lowest

bus ratio and then transition to the lower VID. No notification to the system occurs

upon entry to C1/C1E.

7.2.2.3

Package C3 State

The package will enter the C3 low power state when all cores are in the C3 or lower

power state and the processor has been granted permission by the other component(s)

in the system to enter the C3 state. The package will also enter the C3 state when all

cores are in an idle state lower than C3 but other component(s) in the system have

only granted permission to enter C3.

Datasheet

85

Features

If Intel QPI L1 has been granted, the processor will disable some clocks and PLLs and

for processors with an integrated memory controller, the DRAM will be put into self-

refresh.

7.2.2.4

Package C6 State

The package will enter the C6 low power state when all cores are in the C6 or lower

power state and the processor has been granted permission by the other component(s)

in the system to enter the C6 state. The package will also enter the C6 state when all

cores are in an idle state lower than C6 but the other component(s) have only granted

permission to enter C6.

If Intel QPI L1 has been granted, the processor will disable some clocks and PLLs and

the shared cache will enter a deep sleep state. Additionally, for processors with an

integrated memory controller, the DRAM will be put into self-refresh.

7.3

Sleep States

The processor supports the ACPI sleep states S0, S1, S3, and S4/S5 as shown in

Table 7-3. For information on ACPI S-states and related terminology, refer to ACPI

Specification. The S-state transitions are coordinated by the processor in response PM

Request (PMReq) messages from the chipset. The processor itself will never request a

particular S-state.

Table 7-3.

Processor S-States

S-State

Power Reduction

Allowed Transitions

S0

S1

Normal Code Execution

S1 (using PMReq)

Cores in C1E like state, processor responds with

CmpD(S1) message.

S0 (using reset or PMReq)

S3, S4 (using PMReq)

S3

Memory put into self-refresh, processor responds with

CmpD(S3) message.

S0 (using reset)

S4/S5

Processor responds with CmpD(S4/S5) message.

S0 (using reset)

Notes:

1.

If the chipset requests an S-state transition, which is not allowed, a machine check error

will be generated by the processor.

7.4

ACPI P-States (Intel^®Turbo Boost Technology)

The processor supports ACPI P-States. A new feature is that the P0 ACPI state will be a

request for Intel Turbo Boost Technology. This technology opportunistically and

automatically allows the processor to run faster than its marked frequency if the

processor is operating below power, thermal, and current specifications. Maximum

turbo frequency is dependant on the processor component and number of active cores.

No special hardware support is necessary for Intel Turbo Boost Technology. BIOS and

the operating system can enable or disable Intel Turbo Boost Technology.

86

Datasheet

Features

7.5

Enhanced Intel^®SpeedStep^®Technology

The processor features Enhanced Intel SpeedStep Technology. Following are the key

features of Enhanced Intel SpeedStep Technology:

• Multiple voltage and frequency operating points provide optimal performance at the

lowest power.

• Voltage and frequency selection is software controlled by writing to processor

MSRs:

— If the target frequency is higher than the current frequency, V_CCis ramped up

in steps by placing new values on the VID pins and the PLL then locks to the

new frequency.

— If the target frequency is lower than the current frequency, the PLL locks to the

new frequency and the V_CCis changed through the VID pin mechanism.

— Software transitions are accepted at any time. If a previous transition is in

progress, the new transition is deferred until the previous transition completes.

• The processor controls voltage ramp rates internally to ensure smooth transitions.

• Low transition latency and large number of transitions possible per second:

— Processor core (including shared cache) is unavailable for less than 5 µs during

the frequency transition.

§

Datasheet

87

Features

88

Datasheet

Boxed Processor Specifications

8

Boxed Processor Specifications

8.1

Introduction

The processor will also be offered as an Intel boxed processor. Intel boxed processors

are intended for system integrators who build systems from baseboards and standard

components. The boxed processor will be supplied with a cooling solution. This chapter

documents baseboard and system requirements for the cooling solution that will be

supplied with the boxed processor. This chapter is particularly important for OEMs that

manufacture baseboards for system integrators.

Note:

Unless otherwise noted, all figures in this chapter are dimensioned in millimeters and

inches [in brackets]. Figure 8-1 shows a mechanical representation of a boxed

processor.

Drawings in this section reflect only the specifications on the Intel boxed processor

product. These dimensions should not be used as a generic keep-out zone for all

cooling solutions. It is the system designers’ responsibility to consider their proprietary

cooling solution when designing to the required keep-out zone on their system

platforms and chassis. Refer to the appropriate processor Thermal and Mechanical

Design Guidelines (see Section 1.2) for further guidance. Contact your local Intel Sales

Representative for this document.

Figure 8-1. Mechanical Representation of the Boxed Processor

NOTE: The airflow of the fan heatsink is into the center and out of the sides of the fan heatsink.

Datasheet

89

Boxed Processor Specifications

8.2

Mechanical Specifications

8.2.1

Boxed Processor Cooling Solution Dimensions

This section documents the mechanical specifications of the boxed processor. The

boxed processor will be shipped with an unattached fan heatsink. Figure 8-1 shows a

mechanical representation of the boxed processor.

Clearance is required around the fan heatsink to ensure unimpeded airflow for proper

cooling. The physical space requirements and dimensions for the boxed processor with

assembled fan heatsink are shown in Figure 8-2 (Side View), and Figure 8-3 (Top

View). The airspace requirements for the boxed processor fan heatsink must also be

incorporated into new baseboard and system designs. Airspace requirements are

shown in Figure 8-7 and Figure 8-8. Note that some figures have centerlines shown

(marked with alphabetic designations) to clarify relative dimensioning.

Figure 8-2. Space Requirements for the Boxed Processor (side view)

90

Datasheet

Boxed Processor Specifications

Figure 8-3. Space Requirements for the Boxed Processor (top view)

NOTES:

1.

Diagram does not show the attached hardware for the clip design and is provided only as a

mechanical representation.

Figure 8-4. Space Requirements for the Boxed Processor (overall view)

Datasheet

91

Boxed Processor Specifications

8.2.2

8.2.3

Boxed Processor Fan Heatsink Weight

The boxed processor fan heatsink will not weigh more than 550 grams. See Chapter 6

and the appropriate processor Thermal and Mechanical Design Guidelines (see

Section 1.2). for details on the processor weight and heatsink requirements.

Boxed Processor Retention Mechanism and Heatsink

Attach Clip Assembly

The boxed processor thermal solution requires a heatsink attach clip assembly, to

secure the processor and fan heatsink in the baseboard socket. The boxed processor

will ship with the heatsink attach clip assembly.

8.3

Electrical Requirements

8.3.1

Fan Heatsink Power Supply

The boxed processor fan heatsink requires a +12 V power supply. A fan power cable

will be shipped with the boxed processor to draw power from a power header on the

baseboard. The power cable connector and pinout are shown in Figure 8-5. Baseboards

must provide a matched power header to support the boxed processor. Table 8-1

contains specifications for the input and output signals at the fan heatsink connector.

The fan heatsink outputs a SENSE signal, which is an open- collector output that pulses

at a rate of 2 pulses per fan revolution. A baseboard pull-up resistor provides V_OHto

match the system board-mounted fan speed monitor requirements, if applicable. Use of

the SENSE signal is optional. If the SENSE signal is not used, pin 3 of the connector

should be tied to GND.

The fan heatsink receives a PWM signal from the motherboard from the 4th pin of the

connector labeled as CONTROL.

The boxed processor's fanheat sink requires a constant +12 V supplied to pin 2 and

does not support variable voltage control or 3-pin PWM control.

The power header on the baseboard must be positioned to allow the fan heatsink power

cable to reach it. The power header identification and location should be documented in

the platform documentation, or on the system board itself. Figure 8-6 shows the

location of the fan power connector relative to the processor socket. The baseboard

power header should be positioned within 110 mm [4.33 inches] from the center of the

processor socket.

Figure 8-5. Boxed Processor Fan Heatsink Power Cable Connector Description

Signal

Straight square pin, 4-pin terminal housing with

polarizing ribs and friction locking ramp.

1

2

3

4

GND

+12 V

0.100" pitch, 0.025" square pin width.

SENSE

CONTROL

Match with straight pin, friction lock header on

mainboard.

3

2

4

1

92

Datasheet

Boxed Processor Specifications

Table 8-1.

Fan Heatsink Power and Signal Specifications

Description

Min

Typ

Max

Unit

Notes

+12 V: 12 volt fan power supply

10.8

12

13.2

V

-

IC:

- Peak steady-state fan current draw

- Average steady-state fan current draw

—

3.0

2.0

A

-

pulses per fan

revolution

1

SENSE: SENSE frequency

—

2

—

2, 3

CONTROL

21

25

28

kHz

Notes:

1. Baseboard should pull this pin up to 5V with a resistor.

2. Open drain type, pulse width modulated.

3. Fan will have pull-up resistor for this signal to maximum of 5.25 V.

Figure 8-6. Baseboard Power Header Placement Relative to Processor Socket

R110

[4.33]

B

C

8.4

Thermal Specifications

This section describes the cooling requirements of the fan heatsink solution used by the

boxed processor.

8.4.1

Boxed Processor Cooling Requirements

The boxed processor may be directly cooled with a fan heatsink. However, meeting the

processor's temperature specification is also a function of the thermal design of the

entire system, and ultimately the responsibility of the system integrator. The processor

temperature specification is found in Chapter 6 of this document. The boxed processor

fan heatsink is able to keep the processor temperature within the specifications (see

Table 6-1) in chassis that provide good thermal management. For the boxed processor

fan heatsink to operate properly, it is critical that the airflow provided to the fan

heatsink is unimpeded. Airflow of the fan heatsink is into the center and out of the

sides of the fan heatsink. Airspace is required around the fan to ensure that the airflow

through the fan heatsink is not blocked. Blocking the airflow to the fan heatsink

reduces the cooling efficiency and decreases fan life. Figure 8-7 and Figure 8-8

illustrate an acceptable airspace clearance for the fan heatsink. The air temperature

entering the fan should be kept below 40 ºC. Again, meeting the processor's

temperature specification is the responsibility of the system integrator.

Datasheet

93

Boxed Processor Specifications

Figure 8-7. Boxed Processor Fan Heatsink Airspace Keepout Requirements (top view)

Figure 8-8. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side view)

94

Datasheet

Boxed Processor Specifications

8.4.2

Variable Speed Fan

If the boxed processor fan heatsink 4-pin connector is connected to a 3-pin

motherboard header it will operate as follows:

The boxed processor fan will operate at different speeds over a short range of

internal chassis temperatures. This allows the processor fan to operate at a lower

speed and noise level, while internal chassis temperatures are low. If internal

chassis temperature increases beyond a lower set point, the fan speed will rise

linearly with the internal temperature until the higher set point is reached. At that

point, the fan speed is at its maximum. As fan speed increases, so does fan noise

levels. Systems should be designed to provide adequate air around the boxed

processor fan heatsink that remains cooler then lower set point. These set points,

represented in Figure 8-9 and Table 8-2, can vary by a few degrees from fan

heatsink to fan heatsink. The internal chassis temperature should be kept below

40 ºC. Meeting the processor temperature specification (see Chapter 6) is the

responsibility of the system integrator.

The motherboard must supply a constant +12 V to the processor's power header to

ensure proper operation of the variable speed fan for the boxed processor. Refer to

Table 8-1 for the specific requirements.

Figure 8-9. Boxed Processor Fan Heatsink Set Points

Higher Set Point

Highest Noise Level

Increasing Fan

Speed & Noise

Lowest Noise Level

X

Z

Internal Chassis Temperature (Degrees C)

Table 8-2.

Fan Heatsink Power and Signal Specifications

Boxed Processor Fan

Heatsink Set Point

(°C)

Boxed Processor Fan Speed

Notes

When the internal chassis temperature is below or equal to this set point,

the fan operates at its lowest speed. Recommended maximum internal

chassis temperature for nominal operating environment.

1

X  30

When the internal chassis temperature is above or equal to this set point,

the fan operates at its highest speed. Recommended maximum internal

chassis temperature for worst-case operating environment.

Z  40

-

Notes:

1. Set point variance is approximately ± 1 C from fan heatsink to fan heatsink.

Datasheet

95

Boxed Processor Specifications

If the boxed processor fan heatsink 4-pin connector is connected to a 4-pin

motherboard header and the motherboard is designed with a fan speed controller with

PWM output (CONTROL see Table 8-1) and remote thermal diode measurement

capability the boxed processor will operate as follows:

As processor power has increased the required thermal solutions have generated

increasingly more noise. Intel has added an option to the boxed processor that allows

system integrators to have a quieter system in the most common usage.

The 4th wire PWM solution provides better control over chassis acoustics. This is

achieved by more accurate measurement of processor die temperature through the

processor's Digital Thermal Sensors (DTS) and PECI. Fan RPM is modulated through the

use of an ASIC located on the motherboard that sends out a PWM control signal to the

4th pin of the connector labeled as CONTROL. The fan speed is based on actual

processor temperature instead of internal ambient chassis temperatures.

If the new 4-pin active fan heat sink solution is connected to an older 3-pin baseboard

processor fan header it will default back to a thermistor controlled. Under thermistor

controlled mode, the fan RPM is automatically varied based on the Tinlet temperature

measured by a thermistor located at the fan inlet.

For more details on specific motherboard requirements for 4-wire based fan speed

control, see the appropriate processor Thermal and Mechanical Design Guidelines (see

Section 1.2).

96

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“Announced” SKUs are not yet available. Please refer to the Launch Date for market availability.

Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check with your PC

manufacturer on whether your system delivers Execute Disable Bit functionality.

64-bit computing on Intel® architecture requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications enabled for Intel® 64

architecture. Processors will not operate (including 32-bit operation) without an Intel 64 architecture-enabled BIOS. Performance will vary depending on your hardware and

software configurations. Consult with your system vendor for more information.

Hyper-Threading Technology (HT Technology) requires a computer system with an Intel® processor supporting HT Technology and an HT Technology enabled chipset, BIOS

and operating system. Performance will vary depending on the specific hardware and software you use. See www.intel.com/products/ht/hyperthreading_more.htm for more

information including details on which processors support HT Technology.

Intel® Virtualization Technology requires a computer system with a processor, chipset, BIOS, virtual machine monitor (VMM) and for some uses, certain platform software,

enabled for it. Functionality, performance or other benefit will vary depending on hardware and software configurations. Intel Virtualization Technology-enabled VMM

applications are currently in development.

Note: Prices subject to change without notice. Prices are for direct Intel customers in 1000-unit bulk quantities and, unless specified, represent the latest technology versions

of the products. Taxes and shipping, etc. not included. Prices may vary for other package types and shipment quantities, and special promotional arrangements may apply.

Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See

http://www.intel.com/products/processor_number for details.

System and Maximum TDP is based on worst case scenarios. Actual TDP may be lower if not all I/Os for chipsets are used.

All information provided is subject to change at any time, without notice. Intel may make changes to manufacturing life cycle, specifications, and product descriptions at any

time, without notice. The information herein is provided "as-is" and Intel does not make any representations or warranties whatsoever regarding accuracy of the information,

nor on the product features, availability, functionality, or compatibility of the products listed. Please contact system vendor for more information on specific products or

systems.

Low Halogen implies the following:

Bromine and/or chlorine in materials that may be used during processing, but do not remain within the final product are not included in this definition. The halogens fluorine

(F), iodine (I), and astatine (At) are not restricted by this standard.

“BFR/CFR and PVC-Free” Definition: :

All PCB laminates must meet Br and Cl requirements for low halogen as defined in IPC-4101B

For components other than PCB laminates, all homogeneous materials must contain < 900 ppm (0.09%) of Bromine [if the Bromine (Br)

source is from BFRs] and < 900 ppm (0.09%) of Chlorine [if the Chlorine (Cl) source is from CFRs or PVC. Higher concentrations of Br and Cl

are allowed in homogenous materials of components other than PCB laminates as long as their sources are not BFRs, CFRs, PVC.

Although the elemental analysis for Br and Cl in homogeneous materials can be performed by any analytical method with sufficient sensitivity

and selectivity, the presence or absence of BFRs, CFRs or PVC must be verified by any acceptable analytical techniques that allow for the

unequivocal identification of the specific Br or Cl compounds, or by appropriate material declarations agreed to between customer and

supplier.

Max Turbo Frequency refers to the maximum single-core frequency that can be achieved with Intel® Turbo Boost Technology, which requires a PC with a processor with Intel

Turbo Boost Technology capability. Intel Turbo Boost Technology performance varies depending on hardware, software, and overall system configuration. Check with your PC

manufacturer on whether your system delivers Intel Turbo Boost Technology. See www.intel.com/technology/turboboost/ for more information.

Some products can support AES New Instructions with a Processor Configuration update, in particular, i7-2630QM/i7-2635QM, i7-2670QM/i7-2675QM, i5-2430M/i5-2435M,

i5-2410M/i5-2415M. Please contact OEM for the BIOS that includes the latest Processor configuration update.

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Intel® Core™ i7-930 Processor (8M Cache, 2.80 GHz, 4.80 GT/s Intel®...

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型号：	AT80601000897AA
厂家：	INTEL
描述：	Microprocessor, 64-Bit, 2800MHz, CMOS, PBGA1366, HALOGEN FREE, FC-LGA-1366 外围集成电路
文件：	总100页 (文件大小：963K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AT80601000897AA [INTEL]

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