AT80570PJ0936M/SLB9L [INTEL]
RISC Microprocessor, 64-Bit, 3330MHz, CMOS, PBGA775;型号: | AT80570PJ0936M/SLB9L |
厂家: | INTEL |
描述: | RISC Microprocessor, 64-Bit, 3330MHz, CMOS, PBGA775 外围集成电路 |
文件: | 总102页 (文件大小:1407K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
®
Δ
Intel Core™2 Duo Processor E8000
Δ
and E7000 Series
Datasheet
January 2009
Document Number: 318732-005
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS
OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING
TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE
FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel Core™2 Duo processor E8000 and E7000 series may contain design defects or errors known as errata which may cause the product to deviate
from published specifications.
Δ
Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different
processor families. See http://www.intel.com/products/processor_number for details. Over time processor numbers will increment based on changes in
clock, speed, cache, FSB, or other features, and increments are not intended to represent proportional or quantitative increases in any particular
feature. Current roadmap processor number progression is not necessarily representative of future roadmaps. See www.intel.com/products/
processor_number for details.
Φ
®
Intel 64 requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications enabled for Intel 64. Processor
will not operate (including 32-bit operation) without an Intel 64-enabled BIOS. Performance will vary depending on your hardware and software
configurations. See http://developer.intel.com/technology/intel64/ for more information including details on which processors support Intel 64 or consult
with your system vendor for more information.
Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check
with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.
®
Intel Virtualization Technology requires a computer system with a processor, chipset, BIOS, virtual machine monitor (VMM) and for some uses, certain
platform software enabled for it. Functionality, performance or other benefit will vary depending on hardware and software configurations and may
require a BIOS update. Software applications may not be compatible with all operating systems. Please check with your application vendor.
See the Processor Spec Finder or contact your Intel representative for more information.
No computer system can provide absolute security under all conditions. Intel® Trusted Execution Technology (Intel® TXT) requires a computer system
with Intel® Virtualization Technology, an Intel TXT-enabled processor, chipset, BIOS, Authenticated Code Modules and an Intel TXT-compatible
measured launched environment (MLE). The MLE could consist of a virtual machine monitor, an OS or an application. In addition, Intel TXT requires the
system to contain a TPM v1.2, as defined by the Trusted Computing Group and specific software for some uses. For more information, see here
®
Not all specified units of this processor support Thermal Monitor 2, Enhanced HALT State and Enhanced Intel SpeedStep Technology. See the Processor
Spec Finder at http://processorfinder.intel.com or contact your Intel representative for more information.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Intel, Pentium, Intel Core, Intel SpeedStep, and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries.
* Other names and brands may be claimed as the property of others.
Copyright © 2008–2009, Intel Corporation. All rights reserved.
2
Datasheet
Contents
1
Introduction..............................................................................................................9
1.1
Terminology ..................................................................................................... 10
1.1.1 Processor Terminology Definitions ............................................................ 10
References ....................................................................................................... 12
1.2
2
Electrical Specifications........................................................................................... 13
2.1
2.2
Power and Ground Lands.................................................................................... 13
Decoupling Guidelines........................................................................................ 13
2.2.1 VCC Decoupling ..................................................................................... 13
2.2.2 VTT Decoupling...................................................................................... 13
2.2.3 FSB Decoupling...................................................................................... 14
Voltage Identification......................................................................................... 14
Reserved, Unused, and TESTHI Signals ................................................................ 16
Power Segment Identifier (PSID)......................................................................... 16
Voltage and Current Specification........................................................................ 17
2.6.1 Absolute Maximum and Minimum Ratings .................................................. 17
2.6.2 DC Voltage and Current Specification........................................................ 18
2.6.3 VCC Overshoot ...................................................................................... 22
2.6.4 Die Voltage Validation............................................................................. 23
Signaling Specifications...................................................................................... 23
2.7.1 FSB Signal Groups.................................................................................. 24
2.7.2 CMOS and Open Drain Signals ................................................................. 25
2.7.3 Processor DC Specifications ..................................................................... 26
2.7.3.1 Platform Environment Control Interface (PECI)
2.3
2.4
2.5
2.6
2.7
2.8
DC Specifications...................................................................... 27
2.7.3.2 GTL+ Front Side Bus Specifications ............................................. 28
Clock Specifications........................................................................................... 29
2.8.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking............................ 29
2.8.2 FSB Frequency Select Signals (BSEL[2:0])................................................. 30
2.8.3 Phase Lock Loop (PLL) and Filter .............................................................. 31
2.8.4 BCLK[1:0] Specifications......................................................................... 31
3
Package Mechanical Specifications ................................................................................. 35
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
Package Mechanical Drawing............................................................................... 35
Processor Component Keep-Out Zones................................................................. 39
Package Loading Specifications ........................................................................... 39
Package Handling Guidelines............................................................................... 39
Package Insertion Specifications.......................................................................... 40
Processor Mass Specification............................................................................... 40
Processor Materials............................................................................................ 40
Processor Markings............................................................................................ 40
Processor Land Coordinates................................................................................ 41
4
5
Land Listing and Signal Descriptions ............................................................................... 43
4.1
4.2
Processor Land Assignments............................................................................... 43
Alphabetical Signals Reference............................................................................ 66
Thermal Specifications and Design Considerations ............................................................. 77
5.1
Processor Thermal Specifications......................................................................... 77
5.1.1 Thermal Specifications ............................................................................ 77
5.1.2 Thermal Metrology ................................................................................. 81
Processor Thermal Features................................................................................ 81
5.2
Datasheet
3
5.2.1 Thermal Monitor .....................................................................................81
5.2.2 Thermal Monitor 2 ..................................................................................82
5.2.3 On-Demand Mode...................................................................................83
5.2.4 PROCHOT# Signal ..................................................................................83
5.2.5 THERMTRIP# Signal................................................................................84
Platform Environment Control Interface (PECI) ......................................................85
5.3.1 Introduction...........................................................................................85
5.3.1.1 TCONTROL and TCC activation on PECI-Based Systems ..................85
5.3.2 PECI Specifications .................................................................................86
5.3.2.1 PECI Device Address..................................................................86
5.3.2.2 PECI Command Support.............................................................86
5.3.2.3 PECI Fault Handling Requirements...............................................86
5.3.2.4 PECI GetTemp0() Error Code Support ..........................................86
5.3
6
Features ..................................................................................................................87
6.1
6.2
Power-On Configuration Options ..........................................................................87
Clock Control and Low Power States.....................................................................87
6.2.1 Normal State .........................................................................................88
6.2.2 HALT and Extended HALT Powerdown States ..............................................88
6.2.2.1 HALT Powerdown State ..............................................................88
6.2.2.2 Extended HALT Powerdown State ................................................89
6.2.3 Stop Grant and Extended Stop Grant States...............................................89
6.2.3.1 Stop-Grant State.......................................................................89
6.2.3.2 Extended Stop Grant State.........................................................90
6.2.4 Extended HALT Snoop State, HALT Snoop State, Extended
Stop Grant Snoop State, and Stop Grant Snoop State..................................90
6.2.4.1 HALT Snoop State, Stop Grant Snoop State ..................................90
6.2.4.2 Extended HALT Snoop State, Extended Stop Grant
Snoop State .............................................................................90
6.2.5 Sleep State............................................................................................90
6.2.6 Deep Sleep State....................................................................................91
6.2.7 Deeper Sleep State.................................................................................91
6.2.8 Enhanced Intel SpeedStep® Technology ....................................................92
Processor Power Status Indicator (PSI) Signal .......................................................92
6.3
7
Boxed Processor Specifications......................................................................................93
7.1
7.2
Introduction......................................................................................................93
Mechanical Specifications....................................................................................94
7.2.1 Boxed Processor Cooling Solution Dimensions.............................................94
7.2.2 Boxed Processor Fan Heatsink Weight .......................................................95
7.2.3 Boxed Processor Retention Mechanism and Heatsink Attach
Clip Assembly.........................................................................................95
Electrical Requirements ......................................................................................95
7.3.1 Fan Heatsink Power Supply ......................................................................95
Thermal Specifications........................................................................................97
7.4.1 Boxed Processor Cooling Requirements......................................................97
7.4.2 Variable Speed Fan.................................................................................99
7.3
7.4
8
Debug Tools Specifications..........................................................................................101
8.1
Logic Analyzer Interface (LAI) ...........................................................................101
8.1.1 Mechanical Considerations .....................................................................101
8.1.2 Electrical Considerations........................................................................101
4
Datasheet
Figures
1
2
3
4
5
6
7
8
9
Intel® Core™2 Duo Processor E8000 Series VCC Static and Transient Tolerance................ 20
Intel® Core™2 Duo Processor E7000 Series VCC Static and Transient Tolerance................ 22
VCC Overshoot Example Waveform ............................................................................. 23
Differential Clock Waveform ...................................................................................... 33
Measurement Points for Differential Clock Waveforms ................................................... 33
Processor Package Assembly Sketch........................................................................... 35
Processor Package Drawing Sheet 1 of 3 ..................................................................... 36
Processor Package Drawing Sheet 2 of 3 ..................................................................... 37
Processor Package Drawing Sheet 3 of 3 ..................................................................... 38
10 Processor Top-Side Markings Example ........................................................................ 40
11 Processor Land Coordinates and Quadrants, Top View................................................... 41
12 land-out Diagram (Top View – Left Side)..................................................................... 44
13 land-out Diagram (Top View – Right Side)................................................................... 45
14 Intel® Core™2 Duo Processor E8000 Series Thermal Profile........................................... 79
15 Intel® Core™2 Duo Processor E7000 Series Thermal Profile........................................... 80
16 Case Temperature (TC) Measurement Location ............................................................ 81
17 Thermal Monitor 2 Frequency and Voltage Ordering...................................................... 83
18 Conceptual Fan Control Diagram on PECI-Based Platforms............................................. 85
19 Processor Low Power State Machine ........................................................................... 88
20 Mechanical Representation of the Boxed Processor ....................................................... 93
21 Space Requirements for the Boxed Processor (Side View).............................................. 94
22 Space Requirements for the Boxed Processor (Top View)............................................... 94
23 Overall View Space Requirements for the Boxed Processor............................................. 95
24 Boxed Processor Fan Heatsink Power Cable Connector Description.................................. 96
25 Baseboard Power Header Placement Relative to Processor Socket................................... 97
26 Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view) ................... 98
27 Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 2 view) ................... 98
28 Boxed Processor Fan Heatsink Set Points..................................................................... 99
Datasheet
5
Tables
1
2
3
4
5
6
7
8
9
References ..............................................................................................................12
Voltage Identification Definition..................................................................................15
Absolute Maximum and Minimum Ratings ....................................................................17
Voltage and Current Specifications..............................................................................18
Intel® Core™2 Duo Processor E8000 Series VCC Static and Transient Tolerance ................19
Intel® Core™2 Duo Processor E7000 Series VCC Static and Transient Tolerance ................21
VCC Overshoot Specifications......................................................................................22
FSB Signal Groups....................................................................................................24
Signal Characteristics................................................................................................25
10 Signal Reference Voltages .........................................................................................25
11 GTL+ Signal Group DC Specifications ..........................................................................26
12 Open Drain and TAP Output Signal Group DC Specifications ...........................................26
13 CMOS Signal Group DC Specifications..........................................................................27
14 PECI DC Electrical Limits ...........................................................................................28
15 GTL+ Bus Voltage Definitions.....................................................................................29
16 Core Frequency to FSB Multiplier Configuration.............................................................30
17 BSEL[2:0] Frequency Table for BCLK[1:0] ...................................................................31
18 Front Side Bus Differential BCLK Specifications.............................................................31
19 FSB Differential Clock Specifications (1333 MHz FSB) ....................................................32
20 FSB Differential Clock Specifications (1066 MHz FSB) ....................................................32
21 Processor Loading Specifications.................................................................................39
22 Package Handling Guidelines......................................................................................39
23 Processor Materials...................................................................................................40
24 Alphabetical Land Assignments...................................................................................46
25 Numerical Land Assignment.......................................................................................56
26 Signal Description.....................................................................................................66
27 Processor Thermal Specifications................................................................................78
28 Intel® Core™2 Duo Processor E8000 Series Thermal Profile ...........................................79
29 Intel® Core™2 Duo Processor E7000 Series Thermal Profile ...........................................80
30 GetTemp0() Error Codes ...........................................................................................86
31 Power-On Configuration Option Signals .......................................................................87
32 Fan Heatsink Power and Signal Specifications...............................................................96
33 Fan Heatsink Power and Signal Specifications.............................................................100
6
Datasheet
®
Intel Core™2 Duo Processor E8000
and E7000 Series Features
• Available at 3.33 GHz, 3.16 GHz, 3.00 GHz,
2.83 GHz, and 2.66 GHz for the Intel
Core™2 Duo processor E8000 series
• Advance Dynamic Execution
• Very deep out-of-order execution
• Enhanced branch prediction
• Optimized for 32-bit applications running on
advanced 32-bit operating systems
• Available at 2.93 GHz, 2.80 GHz, 2.66 GHz
and 2.53 GHz for the Intel Core™2 Duo
processor E7000 series
• Enhanced Intel Speedstep® Technology
• Supports Intel® 64Φ architecture
• Supports Intel® Virtualization Technology
(Intel® VT) (Intel Core™2 Duo processors
E8600, E8500, E8400, E8300, and E8200
only)
• Intel® Advanced Smart Cache
• 6 MB Level 2 cache (Intel Core™2 Duo
processor E8000 series only)
• 3 MB Level 2 cache (Intel Core™2 Duo
processor E7000 series only)
• Intel® Advanced Digital Media Boost
• Enhanced floating point and multimedia unit
for enhanced video, audio, encryption, and
3D performance
• Power Management capabilities
• System Management mode
• Multiple low-power states
• 8-way cache associativity provides improved
cache hit rate on load/store operations
• 775-land Package
• Supports Intel® Trusted Execution
Technology (Intel® TXT) (Intel Core™2 Duo
processors E8600, E8500, E8400, E8300,
and E8200 only)
• Supports Execute Disable Bit capability
• FSB frequency at 1333 MHz
• FSB frequency at 1066 MHz (Intel Core™2
Duo processor E7000 series only)
• Binary compatible with applications running
on previous members of the Intel
microprocessor line
The Intel® Core™2 Duo processor E8000 and E7000 series are based on the Enhanced Intel® Core™
microarchitecture. The Enhanced Intel® Core™ microarchitecture combines the performance across
applications and usages where end-users can truly appreciate and experience the performance. These
applications include Internet audio and streaming video, image processing, video content creation,
speech, 3D, CAD, games, multimedia, and multitasking user environments.
Intel® 64Φ architecture enables the processor to execute operating systems and applications written
to take advantage of the Intel 64 architecture. The processor, supporting Enhanced Intel Speedstep®
technology, allows tradeoffs to be made between performance and power consumption.
The Intel Core™2 Duo processor E8000 and E7000 series also includes the Execute Disable Bit
capability. This feature, combined with a supported operating system, allows memory to be marked
as executable or non-executable.
Virtualization Technology provides silicon-based functionality that works together with compatible
Virtual Machine Monitor (VMM) software to improve on software-only solutions.
The Intel® Trusted Execution Technology (Intel TXT) is a key element in Intel's safer computing
initiative that defines a set of hardware enhancements that interoperate with an Intel TXT enabled
operating system to help protect against software-based attacks. It creates a hardware foundation
that builds on Intel's Virtualization Technology to help protect the confidentiality and integrity of data
stored/created on the client PC.
Datasheet
7
Revision History
Revision
Number
Description
Revision Date
January 2008
-001
• Initial release
• Added Intel® Core™2 Duo processor E8300 and E7200
• Updated VID information. Updated Table 2-1.
• Added the PSI# signal
April 2008
-002
• Added Intel® Core™2 Duo processor E8600 and E7300
-003
August 2008
• Updated FSB termination voltage in Table 2-3.
• Added Intel® Core™2 Duo processor E7400
• Added Intel® Core™2 Duo processor E7500
October 2008
January 2009
-004
-005
§ §
8
Datasheet
Introduction
1 Introduction
The Intel® Core™2 Duo processor E8000 and E7000 series is based on the Enhanced
Intel® Core™ microarchitecture. The Intel Enhanced Core™ microarchitecture combines
the performance of previous generation Desktop products with the power efficiencies of
a low-power microarchitecture to enable smaller, quieter systems. The Intel® Core™2
Duo processor E8000 and E7000 series are 64-bit processors that maintain
compatibility with IA-32 software.
Note:
Note:
In this document, the Intel® Core™2 Duo processor E8000 and E7000 series may be
referred to as "the processor."
In this document, unless otherwise specified, the Intel® Core™2 Duo processor E8000
series refers to the Intel® Core™2 Duo processors E8600, E8500, E8400, E8300,
E8200, and E8190.
Note:
In this document, unless otherwise specified, the Intel® Core™2 Duo processor E7000
series refers to the Intel® Core™2 Duo processors E7500, E7400, E7300 and E7200.
The processors use Flip-Chip Land Grid Array (FC-LGA8) package technology, and plugs
into a 775-land surface mount, Land Grid Array (LGA) socket, referred to as the
LGA775 socket.
The processors are based on 45 nm process technology. The processors feature the
Intel® Advanced Smart Cache, a shared multi-core optimized cache that significantly
reduces latency to frequently used data. The Intel® Core™2 Duo processor E8000
series features a 1333 MHz front side bus (FSB) and 6 MB of L2 cache. The Intel®
Core™2 Duo processor E7000 series features a 1333 MHz and 1066 MHz front side bus
(FSB) and 3 MB of L2 cache. The processors support all the existing Streaming SIMD
Extensions 2 (SSE2), Streaming SIMD Extensions 3 (SSE3), Supplemental Streaming
SIMD Extension 3 (SSSE3), and the Streaming SIMD Extensions 4.1 (SSE4.1). The
processors support several Advanced Technologies: Execute Disable Bit, Intel® 64
architecture, and Enhanced Intel SpeedStep® Technology. The Intel® Core™2 Duo
processor E8600, E8500, E8400, E8300, and E8200 support Intel® Trusted Execution
Technology (Intel® TXT) and Intel® Virtualization Technology (Intel® VT).
The processor's front side bus (FSB) use a split-transaction, deferred reply protocol.
The FSB uses Source-Synchronous Transfer of address and data to improve
performance by transferring data four times per bus clock (4X data transfer rate).
Along with the 4X data bus, the address bus can deliver addresses two times per bus
clock and is referred to as a "double-clocked" or 2X address bus. Working together, the
4X data bus and 2X address bus provide a data bus bandwidth of up to 10.7 GB/s.
Intel has enabled support components for the processor including heatsink, heatsink
retention mechanism, and socket. Manufacturability is a high priority; hence,
mechanical assembly may be completed from the top of the baseboard and should not
require any special tooling.
Datasheet
9
Introduction
1.1
Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in
the active state when driven to a low level. For example, when RESET# is low, a reset
has been requested. Conversely, when NMI is high, a nonmaskable interrupt has
occurred. In the case of signals where the name does not imply an active state but
describes part of a binary sequence (such as address or data), the ‘#’ symbol implies
that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and
D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).
“Front Side Bus” refers to the interface between the processor and system core logic
(a.k.a. the chipset components). The FSB is a multiprocessing interface to processors,
memory, and I/O.
1.1.1
Processor Terminology Definitions
Commonly used terms are explained here for clarification:
• Intel® Core™2 Duo processor E8000 series — Dual core processor in the FC-
LGA8 package with a 6 MB L2 cache.
• Intel® Core™2 Duo processor E7000 series — Dual core processor in the FC-
LGA8 package with a 3 MB L2 cache.
• Processor — For this document, the term processor is the generic form of the
Intel® Core™2 Duo processor E8000 series and Intel® Core™2 Duo processor
E7000 series.
• Voltage Regulator Design Guide — For this document “Voltage Regulator Design
Guide” may be used in place of:
— Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design
Guidelines For Desktop LGA775 Socket
• Enhanced Intel® Core™ microarchitecture — A new foundation for Intel®
architecture-based desktop, mobile and mainstream server multi-core processors.
For additional information refer to: http://www.intel.com/technology/architecture/
coremicro/
• Keep-out zone — The area on or near the processor that system design can not
use.
• Processor core — Processor die with integrated L2 cache.
• LGA775 socket — The processors mate with the system board through a surface
mount, 775-land, LGA socket.
• Integrated heat spreader (IHS) —A component of the processor package used
to enhance the thermal performance of the package. Component thermal solutions
interface with the processor at the IHS surface.
• Retention mechanism (RM) — Since the LGA775 socket does not include any
mechanical features for heatsink attach, a retention mechanism is required.
Component thermal solutions should attach to the processor via a retention
mechanism that is independent of the socket.
• FSB (Front Side Bus) — The electrical interface that connects the processor to
the chipset. Also referred to as the processor system bus or the system bus. All
memory and I/O transactions as well as interrupt messages pass between the
processor and chipset over the FSB.
10
Datasheet
Introduction
• Storage conditions — Refers to a non-operational state. The processor may be
installed in a platform, in a tray, or loose. Processors may be sealed in packaging or
exposed to free air. Under these conditions, processor lands should not be
connected to any supply voltages, have any I/Os biased, or receive any clocks.
Upon exposure to “free air”(i.e., unsealed packaging or a device removed from
packaging material) the processor must be handled in accordance with moisture
sensitivity labeling (MSL) as indicated on the packaging material.
• Functional operation — Refers to normal operating conditions in which all
processor specifications, including DC, AC, system bus, signal quality, mechanical
and thermal are satisfied.
• Execute Disable Bit — Execute Disable Bit allows memory to be marked as
executable or non-executable, when combined with a supporting operating system.
If code attempts to run in non-executable memory the processor raises an error to
the operating system. This feature can prevent some classes of viruses or worms
that exploit buffer over run vulnerabilities and can thus help improve the overall
security of the system. See the Intel® Architecture Software Developer's Manual
for more detailed information.
• Intel® 64 Architecture— An enhancement to Intel's IA-32 architecture, allowing
the processor to execute operating systems and applications written to take
advantage of the Intel 64 architecture. Further details on Intel 64 architecture and
programming model can be found in the Intel Extended Memory 64 Technology
Software Developer Guide at http://developer.intel.com/technology/
64bitextensions/.
• Enhanced Intel SpeedStep® Technology — Enhanced Intel SpeedStep
Technology allows trade-offs to be made between performance and power
consumptions, based on processor utilization. This may lower average power
consumption (in conjunction with OS support).
• Intel® Virtualization Technology (Intel® VT) — A set of hardware
enhancements to Intel server and client platforms that can improve virtualization
solutions. Intel VT will provide a foundation for widely-deployed virtualization
solutions and enables more robust hardware assisted virtualization solutions. More
information can be found at: http://www.intel.com/technology/virtualization/
• Intel® Trusted Execution Technology (Intel® TXT) — A key element in Intel's
safer computing initiative which defines a set of hardware enhancements that
interoperate with an Intel TXT enabled OS to help protect against software-based
attacks. Intel TXT creates a hardware foundation that builds on Intel's
Virtualization Technology (Intel VT) to help protect the confidentiality and integrity
of data stored/created on the client PC.
• Platform Environment Control Interface (PECI) — A proprietary one-wire bus
interface that provides a communication channel between the processor and
chipset components to external monitoring devices.
Datasheet
11
Introduction
1.2
References
Material and concepts available in the following documents may be beneficial when
reading this document.
Table 1.
References
Document
Location
www.intel.com/design/
processor/specupdt/
318733.htm
Intel® Core™2 Duo Processor E8000 and E7000 Series Specification
Update
Intel® Core™2 Duo Processor E8000 and E7000 Series and Intel®
Pentium Dual-Core Processor E5000 Series Thermal and Mechanical
Design Guidelines
www.intel.com/design/
processor/designex/
318734.htm
http://www.intel.com/
design/processor/
applnots/313214.htm
Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design
Guidelines For Desktop LGA775 Socket
http://intel.com/design/
Pentium4/guides/
302666.htm
LGA775 Socket Mechanical Design Guide
Intel® 64 and IA-32 Intel Architecture Software Developer's Manuals
Volume 1: Basic Architecture
Volume 2A: Instruction Set Reference, A-M
Volume 2B: Instruction Set Reference, N-Z
Volume 3A: System Programming Guide, Part 1
Volume 3B: System Programming Guide, Part 2
http://www.intel.com/
products/processor/
manuals/
§
12
Datasheet
Electrical Specifications
2 Electrical Specifications
This chapter describes the electrical characteristics of the processor interfaces and
signals. DC electrical characteristics are provided.
2.1
Power and Ground Lands
The processor has VCC (power), VTT, and VSS (ground) inputs for on-chip power
distribution. All power lands must be connected to VCC, while all VSS lands must be
connected to a system ground plane. The processor VCC lands must be supplied the
voltage determined by the Voltage IDentification (VID) lands.
The signals denoted as VTT provide termination for the front side bus and power to the
I/O buffers. A separate supply must be implemented for these lands, that meets the
VTT specifications outlined in Table 4.
2.2
Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is
capable of generating large current swings. This may cause voltages on power planes
to sag below their minimum specified values if bulk decoupling is not adequate. Larger
bulk storage (CBULK), such as electrolytic or aluminum-polymer capacitors, supply
current during longer lasting changes in current demand by the component, such as
coming out of an idle condition. Similarly, they act as a storage well for current when
entering an idle condition from a running condition. The motherboard must be designed
to ensure that the voltage provided to the processor remains within the specifications
listed in Table 4. Failure to do so can result in timing violations or reduced lifetime of
the component.
2.2.1
2.2.2
V
Decoupling
CC
VCC regulator solutions need to provide sufficient decoupling capacitance to satisfy the
processor voltage specifications. This includes bulk capacitance with low effective series
resistance (ESR) to keep the voltage rail within specifications during large swings in
load current. In addition, ceramic decoupling capacitors are required to filter high
frequency content generated by the front side bus and processor activity. Consult the
Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For
Desktop LGA775 Socket for further information. Contact your Intel field representative
for additional information.
V Decoupling
TT
Decoupling must be provided on the motherboard. Decoupling solutions must be sized
to meet the expected load. To ensure compliance with the specifications, various
factors associated with the power delivery solution must be considered including
regulator type, power plane and trace sizing, and component placement. A
conservative decoupling solution would consist of a combination of low ESR bulk
capacitors and high frequency ceramic capacitors.
Datasheet
13
Electrical Specifications
2.2.3
FSB Decoupling
The processor integrates signal termination on the die. In addition, some of the high
frequency capacitance required for the FSB is included on the processor package.
However, additional high frequency capacitance must be added to the motherboard to
properly decouple the return currents from the front side bus. Bulk decoupling must
also be provided by the motherboard for proper [A]GTL+ bus operation.
2.3
Voltage Identification
The Voltage Identification (VID) specification for the processor is defined by the Voltage
Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop
LGA775 Socket. The voltage set by the VID signals is the reference VR output voltage
to be delivered to the processor VCC lands (see Chapter 2.6.3 for VCC overshoot
specifications). Refer to Table 13 for the DC specifications for these signals. Voltages
for each processor frequency is provided in Table 4.
Note:
To support the Deeper Sleep State the platform must use a VRD 11.1 compliant
solution. The Deeper Sleep State also requires additional platform support.
Individual processor VID values may be calibrated during manufacturing such that two
devices at the same core speed may have different default VID settings. This is
reflected by the VID Range values provided in Table 4. Refer to the Intel® Core™2 Duo
Processor E8000 and E7000 Series Specification Update for further details on specific
valid core frequency and VID values of the processor. Note that this differs from the
VID employed by the processor during a power management event (Thermal Monitor 2,
Enhanced Intel SpeedStep® technology, or Extended HALT State).
The processor uses eight voltage identification signals, VID[7:0], to support automatic
selection of power supply voltages. Table 2 specifies the voltage level corresponding to
the state of VID[7:0]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers to
a low voltage level. If the processor socket is empty (VID[7:0] = 11111110), or the
voltage regulation circuit cannot supply the voltage that is requested, it must disable
itself.
The processor provides the ability to operate while transitioning to an adjacent VID and
its associated processor core voltage (VCC). This will represent a DC shift in the load
line. It should be noted that a low-to-high or high-to-low voltage state change may
result in as many VID transitions as necessary to reach the target core voltage.
Transitions above the specified VID are not permitted. Table 4 includes VID step sizes
and DC shift ranges. Minimum and maximum voltages must be maintained as shown in
Table 5, Figure 1, Table 6, and Figure 2, as measured across the VCC_SENSE and
VSS_SENSE lands.
The VRM or VRD utilized must be capable of regulating its output to the value defined
by the new VID. DC specifications for dynamic VID transitions are included in Table 4
and Table 5. Refer to the Voltage Regulator Design Guide for further details.
14
Datasheet
Electrical Specifications
Table 2.
Voltage Identification Definition
VID VID VID VID VID VID VID VID
VID VID VID VID VID VID VID VID
Voltage
Voltage
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OFF
1.6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1.0375
1.025
1.0125
1
1.5875
1.575
1.5625
1.55
0.9875
0.975
0.9625
0.95
1.5375
1.525
1.5125
1.5
0.9375
0.925
0.9125
0.9
1.4875
1.475
1.4625
1.45
0.8875
0.875
0.8625
0.85
1.4375
1.425
1.4125
1.4
0.8375
0.825
0.8125
0.8
1.3875
1.375
1.3625
1.35
0.7875
0.775
0.7625
0.75
1.3375
1.325
1.3125
1.3
0.7375
0.725
0.7125
0.7
1.2875
1.275
1.2625
1.25
0.6875
0.675
0.6625
0.65
1.2375
1.225
1.2125
1.2
0.6375
0.625
0.6125
0.6
1.1875
1.175
1.1625
1.15
0.5875
0.575
0.5625
0.55
1.1375
1.125
1.1125
1.1
0.5375
0.525
0.5125
0.5
1.0875
1.075
1.0625
1.05
OFF
Datasheet
15
Electrical Specifications
2.4
Reserved, Unused, and TESTHI Signals
All RESERVED lands must remain unconnected. Connection of these lands to VCC, VSS,
VTT, or to any other signal (including each other) can result in component malfunction
or incompatibility with future processors. See Chapter 4 for a land listing of the
processor and the location of all RESERVED lands.
In a system level design, on-die termination has been included by the processor to
allow signals to be terminated within the processor silicon. Most unused GTL+ inputs
should be left as no connects as GTL+ termination is provided on the processor silicon.
However, see Table 8 for details on GTL+ signals that do not include on-die termination.
Unused active high inputs, should be connected through a resistor to ground (VSS).
Unused outputs can be left unconnected, however this may interfere with some TAP
functions, complicate debug probing, and prevent boundary scan testing. A resistor
must be used when tying bidirectional signals to power or ground. When tying any
signal to power or ground, a resistor will also allow for system testability. Resistor
values should be within ± 20% of the impedance of the motherboard trace for front
side bus signals. For unused GTL+ input or I/O signals, use pull-up resistors of the
same value as the on-die termination resistors (RTT). For details see Table 15.
TAP and CMOS signals do not include on-die termination. Inputs and utilized outputs
must be terminated on the motherboard. Unused outputs may be terminated on the
motherboard or left unconnected. Note that leaving unused outputs unterminated may
interfere with some TAP functions, complicate debug probing, and prevent boundary
scan testing.
All TESTHI[12,10:0] lands should be individually connected to VTT via a pull-up resistor
which matches the nominal trace impedance.
The TESTHI signals may use individual pull-up resistors or be grouped together as
detailed below. A matched resistor must be used for each group:
• TESTHI[1:0]
• TESTHI[7:2]
• TESTHI8/FC42 – cannot be grouped with other TESTHI signals
• TESTHI9/FC43 – cannot be grouped with other TESTHI signals
• TESTHI10 – cannot be grouped with other TESTHI signals
• TESTHI12/FC44 – cannot be grouped with other TESTHI signals
Terminating multiple TESTHI pins together with a single pull-up resistor is not
recommended for designs supporting boundary scan for proper Boundary Scan testing
of the TESTHI signals. For optimum noise margin, all pull-up resistor values used for
TESTHI[12,10:0] lands should have a resistance value within ± 20% of the impedance
of the board transmission line traces. For example, if the nominal trace impedance is
50 Ω, then a value between 40 Ω and 60 Ω should be used.
2.5
Power Segment Identifier (PSID)
Power Segment Identifier (PSID) is a mechanism to prevent booting under mismatched
power requirement situations. The PSID mechanism enables BIOS to detect if the
processor in use requires more power than the platform voltage regulator (VR) is
capable of supplying. For example, a 130 W TDP processor installed in a board with a
65 W or 95 W TDP capable VR may draw too much power and cause a potential VR
issue.
16
Datasheet
Electrical Specifications
2.6
Voltage and Current Specification
2.6.1
Absolute Maximum and Minimum Ratings
Table 3 specifies absolute maximum and minimum ratings only and lie outside the
functional limits of the processor. Within functional operation limits, functionality and
long-term reliability can be expected.
At conditions outside functional operation condition limits, but within absolute
maximum and minimum ratings, neither functionality nor long-term reliability can be
expected. If a device is returned to conditions within functional operation limits after
having been subjected to conditions outside these limits, but within the absolute
maximum and minimum ratings, the device may be functional, but with its lifetime
degraded depending on exposure to conditions exceeding the functional operation
condition limits.
At conditions exceeding absolute maximum and minimum ratings, neither functionality
nor long-term reliability can be expected. Moreover, if a device is subjected to these
conditions for any length of time then, when returned to conditions within the
functional operating condition limits, it will either not function, or its reliability will be
severely degraded.
Although the processor contains protective circuitry to resist damage from static
electric discharge, precautions should always be taken to avoid high static voltages or
electric fields.
Table 3.
Absolute Maximum and Minimum Ratings
Symbol
VCC
Parameter
Min
Max
Unit Notes1, 2
Core voltage with respect to VSS
–0.3
1.45
V
V
-
-
FSB termination voltage with
respect to VSS
VTT
–0.3
1.45
See
Section 5
See
Section 5
TCASE
Processor case temperature
°C
°C
-
TSTORAGE
Processor storage temperature
–40
85
3, 4, 5
NOTES:
1.
2.
3.
For functional operation, all processor electrical, signal quality, mechanical and thermal
specifications must be satisfied.
Excessive overshoot or undershoot on any signal will likely result in permanent damage to
the processor.
Storage temperature is applicable to storage conditions only. In this scenario, the
processor must not receive a clock, and no lands can be connected to a voltage bias.
Storage within these limits will not affect the long-term reliability of the device. For
functional operation, refer to the processor case temperature specifications.
This rating applies to the processor and does not include any tray or packaging.
Failure to adhere to this specification can affect the long term reliability of the processor.
4.
5.
Datasheet
17
Electrical Specifications
2.6.2
DC Voltage and Current Specification
Table 4.
Voltage and Current Specifications
Symbol
VID Range
Parameter
Min
Typ
Max
1.3625
Unit Notes2, 10
VID
0.8500
—
V
1
Processor Number
(6 MB Cache):
VCC for
775_VR_CONFIG_06:
E8600
E8500
E8400
E8300
E8200
E8190
3.33 GHz
3.16 GHz
3 GHz
Refer to Table 5, Figure 1
2.83 GHz
2.66 GHz
2.66 GHz
Core VCC
V
3, 4, 5
Processor Number
(3 MB Cache):
VCC for
775_VR_CONFIG_06:
E7500
E7400
E7300
E7200
2.93 GHz
2.80 GHz
2.66 GHz
2.53 GHz
Refer to Table 6, Figure 2
VCC_BOOT
VCCPLL
Default VCC voltage for initial power up
PLL VCC
—
1.10
1.50
—
V
V
- 5%
+ 5%
Product Number
(6 MB Cache):
ICC for
775_VR_CONFIG_06:
E8600
E8500
E8400
E8300
E8200
E8190
3.33 GHz
3.16 GHz
3 GHz
75
75
75
75
75
75
—
—
—
—
A
6
2.83 GHz
2.66 GHz
2.66 GHz
ICC
Processor Number
(3 MB Cache):
VCC for
775_VR_CONFIG_06:
E7500
E7400
E7300
E7200
2.93 GHz
2.80 GHz
2.66 GHz
2.53 GHz
75
75
75
75
A
V
on Intel 3 series
Chipset family boards
FSB termination
voltage
1.045
1.14
1.1
1.2
1.155
1.26
VTT
7, 8
(DC + AC
specifications)
on Intel 4 series
Chipset family boards
VTT_OUT_LEFT
and
VTT_OUT_RIGHT
ICC
DC Current that may be drawn from
VTT_OUT_LEFT and VTT_OUT_RIGHT per
land
—
—
580
mA
A
ICC for VTT supply before VCC stable
ICC for VTT supply after VCC stable
4.5
4.6
ITT
—
—
9
ICC_VCCPLL
ICC_GTLREF
I
CC for PLL land
—
—
—
—
130
200
mA
µA
ICC for GTLREF
18
Datasheet
Electrical Specifications
NOTES:
1.
Each processor is programmed with a maximum valid voltage identification value (VID),
which is set at manufacturing and can not be altered. Individual maximum VID values are
calibrated during manufacturing such that two processors at the same frequency may have
different settings within the VID range. Note that this differs from the VID employed by the
processor during a power management event (Thermal Monitor 2, Enhanced Intel
SpeedStep® technology, or Extended HALT State).
2.
3.
4.
Unless otherwise noted, all specifications in this table are based on estimates and
simulations or empirical data. These specifications will be updated with characterized data
from silicon measurements at a later date.
These voltages are targets only. A variable voltage source should exist on systems in the
event that a different voltage is required. See Section 2.3 and Table 2 for more
information.
The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE
lands at the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe
capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the
probe should be less than 5 mm. Ensure external noise from the system is not coupled into
the oscilloscope probe.
5.
Refer to Table 5, Figure 1, Table 6, and Figure 2 for the minimum, typical, and maximum
V
CC allowed for a given current. The processor should not be subjected to any VCC and ICC
combination wherein VCC exceeds VCC_MAX for a given current.
CC_MAX specification is based on VCC_MAX loadline. Refer to Figure 1 for details.
6.
7.
I
V
TT must be provided via a separate voltage source and not be connected to VCC. This
specification is measured at the land.
8.
9.
Baseboard bandwidth is limited to 20 MHz.
This is the maximum total current drawn from the VTT plane by only the processor. This
specification does not include the current coming from on-board termination (RTT),
through the signal line. Refer to the Voltage Regulator Design Guide to determine the total
I
TT drawn by the system. This parameter is based on design characterization and is not
tested.
10.
Adherence to the voltage specifications for the processor are required to ensure reliable
processor operation.
Table 5.
Intel® Core™2 Duo Processor E8000 Series VCC Static and Transient
Tolerance
Voltage Deviation from VID Setting (V)1, 2, 3, 4
ICC (A)
Maximum Voltage
Typical Voltage
Minimum Voltage
1.40 mΩ
1.48 mΩ
1.55 mΩ
0
0.000
-0.007
-0.014
-0.021
-0.028
-0.035
-0.042
-0.049
-0.056
-0.063
-0.070
-0.077
-0.084
-0.019
-0.026
-0.034
-0.041
-0.049
-0.056
-0.063
-0.071
-0.078
-0.085
-0.093
-0.100
-0.108
-0.038
-0.046
-0.054
-0.061
-0.069
-0.077
-0.085
-0.092
-0.100
-0.108
-0.116
-0.123
-0.131
5
10
15
20
25
30
35
40
45
50
55
60
Datasheet
19
Electrical Specifications
Table 5.
Intel® Core™2 Duo Processor E8000 Series VCC Static and Transient Tolerance
(Continued)
Voltage Deviation from VID Setting (V)1, 2, 3, 4
ICC (A)
Maximum Voltage
Typical Voltage
Minimum Voltage
1.40 mΩ
1.48 mΩ
1.55 mΩ
65
70
75
-0.091
-0.098
-0.105
-0.115
-0.122
-0.130
-0.139
-0.147
-0.154
NOTES:
1.
The loadline specification includes both static and transient limits except for overshoot
allowed as shown in Section 2.6.3.
2.
3.
This table is intended to aid in reading discrete points on Figure 1.
The loadlines specify voltage limits at the die measured at the VCC_SENSE and
VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must be taken
from processor VCC and VSS lands. Refer to the Voltage Regulator Design Guide for socket
loadline guidelines and VR implementation details.
4.
Adherence to this loadline specification is required to ensure reliable processor operation.
Figure 1.
Intel® Core™2 Duo Processor E8000 Series VCC Static and Transient
Tolerance
Icc [A]
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
VID - 0.000
VID - 0.013
VID - 0.025
VID - 0.038
VID - 0.050
VID - 0.063
VID - 0.075
VID - 0.088
VID - 0.100
VID - 0.113
VID - 0.125
VID - 0.138
VID - 0.150
VID - 0.163
Vcc Maximum
Vcc Typical
Vcc Minimum
NOTES:
1.
The loadline specification includes both static and transient limits except for overshoot
allowed as shown in Section 2.6.3.
2.
3.
This loadline specification shows the deviation from the VID set point.
The loadlines specify voltage limits at the die measured at the VCC_SENSE and
VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must be taken
from processor VCC and VSS lands. Refer to the Voltage Regulator Design Guide for socket
loadline guidelines and VR implementation details.
20
Datasheet
Electrical Specifications
Table 6.
Intel® Core™2 Duo Processor E7000 Series VCC Static and Transient
Tolerance
1, 2, 3, 4
Voltage Deviation from VID Setting (V)
I
(A)
CC
Maximum Voltage
Typical Voltage
Minimum Voltage
1.65 mΩ
1.73 mΩ
1.80 mΩ
0
0.000
-0.008
-0.017
-0.025
-0.033
-0.041
-0.050
-0.058
-0.066
-0.074
-0.083
-0.091
-0.099
-0.107
-0.116
-0.124
-0.019
-0.028
-0.036
-0.045
-0.054
-0.062
-0.071
-0.079
-0.088
-0.097
-0.105
-0.114
-0.123
-0.131
-0.140
-0.148
-0.038
-0.047
-0.056
-0.065
-0.074
-0.083
-0.092
-0.101
-0.110
-0.119
-0.128
-0.137
-0.146
-0.155
-0.164
-0.173
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
NOTES:
1.
The loadline specification includes both static and transient limits except for overshoot allowed as shown in
Section 2.6.3.
2.
3.
This table is intended to aid in reading discrete points on Figure 1.
The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage
regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands. Refer
to the Voltage Regulator Design Guide for socket loadline guidelines and VR implementation details.
Adherence to this loadline specification is required to ensure reliable processor operation.
4.
Datasheet
21
Electrical Specifications
Figure 2.
Intel® Core™2 Duo Processor E7000 Series VCC Static and Transient
Tolerance
Icc [A]
35 40
0
5
10
15
20
25
30
45
50
55
60
65
70
75
VID - 0.000
VID - 0.013
VID - 0.025
VID - 0.038
VID - 0.050
VID - 0.063
VID - 0.075
VID - 0.088
VID - 0.100
VID - 0.113
VID - 0.125
VID - 0.138
VID - 0.150
VID - 0.163
VID - 0.175
VID - 0.188
Vcc Maximum
Vcc Typical
Vcc Minimum
NOTES:
1.
The loadline specification includes both static and transient limits except for overshoot allowed as shown in
Section 2.6.3.
2.
3.
This loadline specification shows the deviation from the VID set point.
The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage
regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands. Refer
to the Voltage Regulator Design Guide for socket loadline guidelines and VR implementation details.
2.6.3
V
Overshoot
CC
The processor can tolerate short transient overshoot events where VCC exceeds the VID
voltage when transitioning from a high to low current load condition. This overshoot
cannot exceed VID + VOS_MAX (VOS_MAX is the maximum allowable overshoot voltage).
The time duration of the overshoot event must not exceed TOS_MAX (TOS_MAX is the
maximum allowable time duration above VID). These specifications apply to the
processor die voltage as measured across the VCC_SENSE and VSS_SENSE lands.
Table 7.
VCC Overshoot Specifications
Symbol
Parameter
Min
Max
Unit
Figure Notes
Magnitude of VCC overshoot above
VID
1
VOS_MAX
—
50
mV
3
Time duration of VCC overshoot above
VID
1
TOS_MAX
—
25
µs
3
NOTES:
1.
Adherence to these specifications is required to ensure reliable processor operation.
22
Datasheet
Electrical Specifications
Figure 3.
VCC Overshoot Example Waveform
Example Overshoot Waveform
VOS
VID + 0.050
VID - 0.000
TOS
0
5
10
15
20
25
Time [us]
TOS: Overshoot time above VID
OS: Overshoot above VID
V
NOTES:
1.
2.
V
OS is measured overshoot voltage.
TOS is measured time duration above VID.
2.6.4
Die Voltage Validation
Overshoot events on processor must meet the specifications in Table 7 when measured
across the VCC_SENSE and VSS_SENSE lands. Overshoot events that are < 10 ns in
duration may be ignored. These measurements of processor die level overshoot must
be taken with a bandwidth limited oscilloscope set to a greater than or equal to 100
MHz bandwidth limit.
2.7
Signaling Specifications
Most processor Front Side Bus signals use Gunning Transceiver Logic (GTL+) signaling
technology. This technology provides improved noise margins and reduced ringing
through low voltage swings and controlled edge rates. Platforms implement a
termination voltage level for GTL+ signals defined as VTT. Because platforms implement
separate power planes for each processor (and chipset), separate VCC and VTT supplies
are necessary. This configuration allows for improved noise tolerance as processor
frequency increases. Speed enhancements to data and address busses have caused
signal integrity considerations and platform design methods to become even more
critical than with previous processor families.
The GTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to
determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the
motherboard (see Table 15 for GTLREF specifications). Termination resistors (RTT) for
GTL+ signals are provided on the processor silicon and are terminated to VTT. Intel
chipsets will also provide on-die termination, thus eliminating the need to terminate the
bus on the motherboard for most GTL+ signals.
Datasheet
23
Electrical Specifications
2.7.1
FSB Signal Groups
The front side bus signals have been combined into groups by buffer type. GTL+ input
signals have differential input buffers, which use GTLREF[1:0] as a reference level. In
this document, the term “GTL+ Input” refers to the GTL+ input group as well as the
GTL+ I/O group when receiving. Similarly, “GTL+ Output” refers to the GTL+ output
group as well as the GTL+ I/O group when driving.
With the implementation of a source synchronous data bus comes the need to specify
two sets of timing parameters. One set is for common clock signals which are
dependent upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second
set is for the source synchronous signals which are relative to their respective strobe
lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are
still present (A20M#, IGNNE#, etc.) and can become active at any time during the
clock cycle. Table 8 identifies which signals are common clock, source synchronous,
and asynchronous.
Table 8.
FSB Signal Groups
Signal Group
Type
Signals1
GTL+ Common
Clock Input
Synchronous to
BCLK[1:0]
BPRI#, DEFER#, RESET#, RS[2:0]#, TRDY#
GTL+ Common
Clock I/O
Synchronous to
BCLK[1:0]
ADS#, BNR#, BPM[5:0]#, BR0#3, DBSY#, DRDY#,
HIT#, HITM#, LOCK#
Signals
Associated Strobe
REQ[4:0]#, A[16:3]#3 ADSTB0#
A[35:17]#3
ADSTB1#
GTL+ Source
Synchronous I/O
Synchronous to
assoc. strobe
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
DSTBP0#, DSTBN0#
DSTBP1#, DSTBN1#
DSTBP2#, DSTBN2#
DSTBP3#, DSTBN3#
Synchronous to
BCLK[1:0]
GTL+ Strobes
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
A20M#, DPRSTP#. DPSLP#, IGNNE#, INIT#, LINT0/
INTR, LINT1/NMI, SMI#3, STPCLK#, PWRGOOD, SLP#,
TCK, TDI, TMS, TRST#, BSEL[2:0], VID[7:0], PSI#
CMOS
Open Drain Output
FERR#/PBE#, IERR#, THERMTRIP#, TDO
PROCHOT#4
Open Drain Input/
Output
FSB Clock
Clock
BCLK[1:0], ITP_CLK[1:0]2
VCC, VTT, VCCA, VCCIOPLL, VCCPLL, VSS, VSSA,
GTLREF[1:0], COMP[8,3:0], RESERVED,
TESTHI[12,10:0], VCC_SENSE,
Power/Other
VCC_MB_REGULATION, VSS_SENSE,
VSS_MB_REGULATION, DBR#2, VTT_OUT_LEFT,
VTT_OUT_RIGHT, VTT_SEL, FCx, PECI, MSID[1:0]
NOTES:
1.
2.
Refer to Section 4.2 for signal descriptions.
In processor systems where no debug port is implemented on the system board, these
signals are used to support a debug port interposer. In systems with the debug port
implemented on the system board, these signals are no connects.
24
Datasheet
Electrical Specifications
3.
The value of these signals during the active-to-inactive edge of RESET# defines the
processor configuration options. See Section 6.1 for details.
4.
PROCHOT# signal type is open drain output and CMOS input.
.
Table 9.
Signal Characteristics
Signals with RTT
Signals with No RTT
A20M#, BCLK[1:0], BPM[5:0]#, BSEL[2:0],
COMP[8,3:0], FERR#/PBE#, IERR#, IGNNE#,
INIT#, ITP_CLK[1:0], LINT0/INTR, LINT1/
NMI, MSID[1:0], PWRGOOD, RESET#, SMI#,
STPCLK#, TDO, TESTHI[12,10:0],
A[35:3]#, ADS#, ADSTB[1:0]#, BNR#, BPRI#,
D[63:0]#, DBI[3:0]#, DBSY#, DEFER#,
DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, HIT#,
HITM#, LOCK#, PROCHOT#, REQ[4:0]#,
RS[2:0]#, TRDY#
THERMTRIP#, VID[7:0], GTLREF[1:0], TCK,
TDI, TMS, TRST#, VTT_SEL
Open Drain Signals1
THERMTRIP#, FERR#/PBE#, IERR#, BPM[5:0]#,
BR0#, TDO, FCx
NOTES:
1.
Signals that do not have RTT, nor are actively driven to their high-voltage level.
Table 10.
Signal Reference Voltages
GTLREF
VTT/2
BPM[5:0]#, RESET#, BNR#, HIT#, HITM#, BR0#,
A[35:0]#, ADS#, ADSTB[1:0]#, BPRI#, D[63:0]#,
DBI[3:0]#, DBSY#, DEFER#, DRDY#, DSTBN[3:0]#,
DSTBP[3:0]#, LOCK#, REQ[4:0]#, RS[2:0]#,
TRDY#
A20M#, LINT0/INTR, LINT1/NMI,
IGNNE#, INIT#, PROCHOT#,
PWRGOOD1, SMI#, STPCLK#, TCK1,
TDI1, TMS1, TRST#1
NOTE:
1.
See Table 12 for more information.
2.7.2
CMOS and Open Drain Signals
Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS
input buffers. All of the CMOS and Open Drain signals are required to be asserted/de-
asserted for at least eight BCLKs in order for the processor to recognize the proper
signal state. See Section 2.7.3 for the DC specifications. See Section 6.2 for additional
timing requirements for entering and leaving the low power states.
Datasheet
25
Electrical Specifications
2.7.3
Processor DC Specifications
The processor DC specifications in this section are defined at the processor core (pads)
unless otherwise stated. All specifications apply to all frequencies and cache sizes
unless otherwise stated.
Table 11.
GTL+ Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit Notes1
VIL
VIH
VOH
Input Low Voltage
Input High Voltage
Output High Voltage
-0.10
GTLREF – 0.10
VTT + 0.10
VTT
V
V
V
2, 5
3, 4, 5
4, 5
GTLREF + 0.10
VTT – 0.10
VTT_MAX
[(RTT_MIN) + (2 * RON_MIN)]
/
IOL
ILI
ILO
RON
Output Low Current
N/A
N/A
A
-
Input Leakage
Current
± 100
µA
6
7
Output Leakage
Current
N/A
± 100
9.16
µA
Buffer On Resistance
7.49
Ω
NOTES:
1.
2.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
IL is defined as the voltage range at a receiving agent that will be interpreted as a logical
low value.
IH is defined as the voltage range at a receiving agent that will be interpreted as a logical
high value.
IH and VOH may experience excursions above VTT.
The VTT referred to in these specifications is the instantaneous VTT.
Leakage to VSS with land held at VTT.
Leakage to VTT with land held at 300 mV.
V
3.
V
4.
5.
6.
7.
V
Table 12.
Open Drain and TAP Output Signal Group DC Specifications
Symbol
Parameter
Output Low Voltage
Min
Max
Unit Notes1
VOL
IOL
ILO
0
0.20
50
V
-
Output Low Current
16
mA
µA
2
3
Output Leakage Current
N/A
± 200
NOTES:
1.
2.
3.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
Measured at VTT * 0.2 V.
For Vin between 0 and VOH
.
26
Datasheet
Electrical Specifications
Table 13.
CMOS Signal Group DC Specifications
Symb
ol
Parameter
Min
Max
Unit Notes1
VIL
VIH
VOL
VOH
IOL
IOH
ILI
Input Low Voltage
-0.10
VTT * 0.70
-0.10
VTT * 0.30
VTT + 0.10
VTT * 0.10
VTT + 0.10
V
V
3, 6
4, 5, 6
6
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Current
Output Low Current
Input Leakage Current
Output Leakage Current
V
0.90 * VTT
V
2, 5, 6
6, 7
6, 7
8
VTT * 0.10 / 67 VTT * 0.10 / 27
VTT * 0.10 / 67 VTT * 0.10 / 27
A
A
N/A
N/A
± 100
± 100
µA
µA
ILO
9
NOTES:
1.
2.
3.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
All outputs are open drain.
V
IL is defined as the voltage range at a receiving agent that will be interpreted as a logical
low value.
IH is defined as the voltage range at a receiving agent that will be interpreted as a logical
high value.
IH and VOH may experience excursions above VTT.
The VTT referred to in these specifications refers to instantaneous VTT.
OL is measured at 0.10 * VTT. IOH is measured at 0.90 * VTT.
4.
V
5.
6.
7.
8.
9.
V
I
Leakage to VSS with land held at VTT.
Leakage to VTT with land held at 300 mV.
2.7.3.1
Platform Environment Control Interface (PECI) DC Specifications
PECI is an Intel proprietary one-wire interface that provides a communication channel
between Intel processors, chipsets, and external thermal monitoring devices. The
processor contains Digital Thermal Sensors (DTS) distributed throughout die. These
sensors are implemented as analog-to-digital converters calibrated at the factory for
reasonable accuracy to provide a digital representation of relative processor
temperature. PECI provides an interface to relay the highest DTS temperature within a
die to external management devices for thermal/fan speed control. More detailed
information may be found in the Platform Environment Control Interface (PECI)
Specification.
Datasheet
27
Electrical Specifications
Table 14.
PECI DC Electrical Limits
Symbol
Definition and Conditions
Input Voltage Range
Min
Max
Units
Notes1
Vin
-0.15
VTT
—
V
V
V
V
2
Vhysteresis Hysteresis
0.1 * VTT
Vn
Vp
Negative-edge threshold voltage
0.275 * VTT 0.500 * VTT
0.550 * VTT 0.725 * VTT
Positive-edge threshold voltage
High level output source
(VOH = 0.75 * VTT)
Isource
-6.0
0.5
N/A
1.0
mA
mA
Low level output sink
(VOL = 0.25 * VTT)
Isink
3
Ileak+
Ileak-
Cbus
High impedance state leakage to VTT
High impedance leakage to GND
Bus capacitance per node
N/A
N/A
N/A
50
10
10
µA
µA
pF
3
4
Signal noise immunity above 300
MHz
Vnoise
0.1 * VTT
—
Vp-p
NOTES:
1. V supplies the PECI interface. PECI behavior does not affect V min/max specifications. Refer to Table 4 for
TT
TT
TT
V
specifications.
2. The leakage specification applies to powered devices on the PECI bus.
3. The input buffers use a Schmitt-triggered input design for improved noise immunity.
4. One node is counted for each client and one node for the system host. Extended trace lengths might appear
as additional nodes.
.
2.7.3.2
GTL+ Front Side Bus Specifications
In most cases, termination resistors are not required as these are integrated into the
processor silicon. See Table 9 for details on which GTL+ signals do not include on-die
termination.
Valid high and low levels are determined by the input buffers by comparing with a
reference voltage called GTLREF. Table 15 lists the GTLREF specifications. The GTL+
reference voltage (GTLREF) should be generated on the system board using high
precision voltage divider circuits.
28
Datasheet
Electrical Specifications
Table 15.
GTL+ Bus Voltage Definitions
Symbol
Parameter
Min
Typ
Max
Units Notes1
GTLREF pull up on Intel®
3 Series Chipset family
boards
GTLREF_PU
57.6 * 0.99
57.6
57.6 * 1.01
Ω
Ω
2
2
GTLREF pull down on
Intel® 3 Series Chipset
family boards
100 * 0.99
100
100 * 1.01
GTLREF_PD
RTT
Termination Resistance
COMP Resistance
45
50
55
Ω
Ω
Ω
3
4
4
COMP[3:0]
COMP8
49.40
24.65
49.90
24.90
50.40
25.15
COMP Resistance
NOTES:
1.
2.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
GTLREF is to be generated from VTT by a voltage divider of 1% resistors. If an Adjustable
GTLREF circuit is used on the board (for Quad-Core processors compatibility) the two
GTLREF lands connected to the Adjustable GTLREF circuit require the following:
GTLREF_PU = 50 Ω, GTLREF_PD = 100 Ω.
3.
4.
R
TT is the on-die termination resistance measured at VTT/3 of the GTL+ output driver.
COMP resistance must be provided on the system board with 1% resistors. COMP[3:0] and
COMP8 resistors are to VSS
.
2.8
Clock Specifications
2.8.1
Front Side Bus Clock (BCLK[1:0]) and Processor Clocking
BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the
processor. As in previous generation processors, the processor’s core frequency is a
multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its
default ratio during manufacturing. The processor supports Half Ratios between 7.5
and 13.5, refer to Table 16 for the processor supported ratios.
The processor uses a differential clocking implementation. For more information on the
processor clocking, contact your Intel field representative.
Datasheet
29
Electrical Specifications
Table 16.
Core Frequency to FSB Multiplier Configuration
Multiplication of
Core Frequency
(333 MHz BCLK/
1333 MHz FSB)
Core Frequency
System Core
Frequency to FSB
FSB)
Notes1, 2
(266 MHz BCLK/1066 MHz
Frequency
1.60 GHz
1.86 GHz
2 GHz
1/6
1/7
2 GHz
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2.33 GHz
2.50 GHz
2.66 GHz
2.83 GHz
3 GHz
1/7.5
1/8
2.13 GHz
2.26 GHz
2.40 GHz
2.53 GHz
2.66 GHz
2.80 GHz
2.93 GHz
3.06 GHz
3.20 GHz
3.33 GHz
3.46 GHz
3.60GHz
3.73 GHz
4 GHz
1/8.5
1/9
1/9.5
1/10
1/10.5
1/11
1/11.5
1/12
1/12.5
1/13
1/13.5
1/14
1/15
3.16 GHz
3.33 GHz
3.50 GHz
3.66 GHz
3.83 GHz
4 GHz
4.16 GHz
4.33 GHz
4.50 GHz
4.66 GHz
5 GHz
NOTES:
1.
2.
Individual processors operate only at or below the rated frequency.
Listed frequencies are not necessarily committed production frequencies.
2.8.2
FSB Frequency Select Signals (BSEL[2:0])
The BSEL[2:0] signals are used to select the frequency of the processor input clock
(BCLK[1:0]). Table 17 defines the possible combinations of the signals and the
frequency associated with each combination. The required frequency is determined by
the processor, chipset, and clock synthesizer. All agents must operate at the same
frequency.
The Intel® Core™2 Duo processor E7000 series operates at a 1333 MHz FSB and
1066 MHz FSB frequency (selected by a 333 MHz BCLK[1:0] or 266 MHz BCLK[1:0]
frequency) and the Intel® Core™2 Duo processor E8000 series operates at a 1333 MHz
FSB frequency (selected by a 333 MHz BCLK[1:0] frequency). Individual processors will
only operate at their specified FSB frequency.
For more information about these signals, refer to Section 4.2.
30
Datasheet
Electrical Specifications
Table 17.
BSEL[2:0] Frequency Table for BCLK[1:0]
BSEL2
BSEL1
BSEL0
FSB Frequency
L
L
L
L
L
H
H
L
266 MHz
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
333 MHz
L
H
H
H
H
L
L
H
H
H
H
L
H
H
L
L
2.8.3
Phase Lock Loop (PLL) and Filter
An on-die PLL filter solution will be implemented on the processor. The VCCPLL input is
used for the PLL. Refer to Table 4 for DC specifications.
2.8.4
BCLK[1:0] Specifications
Table 18.
Front Side Bus Differential BCLK Specifications
Symbol
Parameter
Min
Typ
Max
Unit Figure Notes1
VL
Input Low Voltage
Input High Voltage
-0.30
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1.15
0.550
0.140
1.4
V
V
V
V
V
V
V
4
4
4
4
4
4
5
VH
VCROSS(abs) Absolute Crossing Point
0.300
N/A
2
-
ΔVCROSS Range of Crossing Points
VOS
VUS
Overshoot
N/A
3
3
4
Undershoot
-0.300
0.300
N/A
VSWING
Differential Output Swing
N/A
NOTES:
1.
2.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
Crossing voltage is defined as the instantaneous voltage value when the rising edge of
BCLK0 equals the falling edge of BCLK1.
3.
4.
“Steady state” voltage, not including overshoot or undershoot.
Overshoot is defined as the absolute value of the maximum voltage. Undershoot is defined
as the absolute value of the minimum voltage.
5.
Measurement taken from differential waveform.
Datasheet
31
Electrical Specifications
Table 19.
FSB Differential Clock Specifications (1333 MHz FSB)
T# Parameter
BCLK[1:0] Frequency
Min
Nom
Max
Unit
Figure Notes1
331.633
2.99970
—
—
—
—
333.367
3.01538
150
MHz
ns
-
4
4
6
2
3
T1: BCLK[1:0] Period
T2: BCLK[1:0] Period Stability
ps
T5: BCLK[1:0] Rise and Fall Slew
Rate
2.5
—
8
V/ns
%
5
4
5
Slew Rate Matching
N/A
N/A
20
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all processor core
frequencies based on a 333 MHz BCLK[1:0].
2.
The period specified here is the average period. A given period may vary from this
specification as governed by the period stability specification (T2). Min period specification
is based on -300 PPM deviation from a 3 ns period. Max period specification is based on
the summation of +300 PPM deviation from a 3 ns period and a +0.5% maximum variance
due to spread spectrum clocking.
3.
In this context, period stability is defined as the worst case timing difference between
successive crossover voltages. In other words, the largest absolute difference between
adjacent clock periods must be less than the period stability.
4.
5.
Slew rate is measured through the VSWING voltage range centered about differential zero.
Measurement taken from differential waveform.
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is
measured using a ±75 mV window centered on the average cross point where Clock rising
meets Clock# falling. The median cross point is used to calculate the voltage thresholds
the oscilloscope is to use for the edge rate calculations.
6.
Duty Cycle (High time/Period) must be between 40 and 60%
Table 20.
FSB Differential Clock Specifications (1066 MHz FSB)
1
T# Parameter
BCLK[1:0] Frequency
Min
Nom
Max
Unit
Figure
Notes
265.307
3.74963
-
-
-
-
266.693
3.76922
150
MHz
ns
-
4
4
5
-
6
T1: BCLK[1:0] Period
2
3
4
5
T2: BCLK[1:0] Period Stability
T5: BCLK[1:0] Rise and Fall Slew Rate
Slew Rate Matching
ps
2.5
-
8
V/ns
%
N/A
N/A
20
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all processor core
frequencies based on a 266 MHz BCLK[1:0].
2.
The period specified here is the average period. A given period may vary from this
specification as governed by the period stability specification (T2). Min period specification
is based on -300 PPM deviation from a 3.75 ns period. Max period specification is based on
the summation of +300 PPM deviation from a 3.75 ns period and a +0.5% maximum
variance due to spread spectrum clocking.
3.
In this context, period stability is defined as the worst case timing difference between
successive crossover voltages. In other words, the largest absolute difference between
adjacent clock periods must be less than the period stability.
4.
5.
Slew rate is measured through the VSWING voltage range centered about differential zero.
Measurement taken from differential waveform.
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is
measured using a ±75mV window centered on the average cross point where Clock rising
32
Datasheet
Electrical Specifications
meets Clock# falling. The median cross point is used to calculate the voltage thresholds
the oscilloscope is to use for the edge rate calculations.
6.
Duty Cycle (High time/Period) must be between 40 and 60%
Figure 4.
Differential Clock Waveform
Tph
Overshoot
VH
BCLK1
Rising Edge
Ringback
Ringback
Margin
VCROSS (ABS
)
VCROSS (ABS)
Threshold
Region
Falling Edge
Ringback
BCLK0
VL
Undershoot
Tpl
Tp
Tp = T1: BCLK[1:0] period
T2: BCLK[1:0] period stability (not shown)
Tph = T3: BCLK[1:0] pulse high time
Tpl = T4: BCLK[1:0] pulse low time
T5: BCLK[1:0] rise time through the threshold region
T6: BCLK[1:0] fall time through the threshold region
Figure 5.
Measurement Points for Differential Clock Waveforms
Slew_rise
Slew _fall
+150 mV
+150mV
0.0V
V_swing
0.0V
-150 mV
-150mV
Diff
T5 = BCLK[1:0] rise and fall time through the swing region
§ §
Datasheet
33
Electrical Specifications
34
Datasheet
Package Mechanical Specifications
3 Package Mechanical
Specifications
The processor is packaged in a Flip-Chip Land Grid Array (FC-LGA8) package that
interfaces with the motherboard via an LGA775 socket. The package consists of a
processor core mounted on a substrate land-carrier. An integrated heat spreader (IHS)
is attached to the package substrate and core and serves as the mating surface for
processor component thermal solutions, such as a heatsink. Figure 6 shows a sketch of
the processor package components and how they are assembled together. Refer to the
LGA775 Socket Mechanical Design Guide for complete details on the LGA775 socket.
The package components shown in Figure 6 include the following:
• Integrated Heat Spreader (IHS)
• Thermal Interface Material (TIM)
• Processor core (die)
• Package substrate
• Capacitors
Figure 6.
Processor Package Assembly Sketch
Core (die)
IHS
TIM
Substrate
Capacitors
LGA775 Socket
System Board
Processor_Pkg_Assembly_775
NOTE:
1.
Socket and motherboard are included for reference and are not part of processor package.
3.1
Package Mechanical Drawing
The package mechanical drawings are shown in Figure 7 and Figure 8. The drawings
include dimensions necessary to design a thermal solution for the processor. These
dimensions include:
• Package reference with tolerances (total height, length, width, etc.)
• IHS parallelism and tilt
• Land dimensions
• Top-side and back-side component keep-out dimensions
• Reference datums
• All drawing dimensions are in mm [in].
• Guidelines on potential IHS flatness variation with socket load plate actuation and
installation of the cooling solution is available in the processor Thermal and
Mechanical Design Guidelines.
Datasheet
35
Package Mechanical Specifications
Figure 7.
Processor Package Drawing Sheet 1 of 3
36
Datasheet
Package Mechanical Specifications
Figure 8.
Processor Package Drawing Sheet 2 of 3
Datasheet
37
Package Mechanical Specifications
Figure 9.
Processor Package Drawing Sheet 3 of 3
38
Datasheet
Package Mechanical Specifications
3.2
3.3
Processor Component Keep-Out Zones
The processor may contain components on the substrate that define component keep-
out zone requirements. A thermal and mechanical solution design must not intrude into
the required keep-out zones. Decoupling capacitors are typically mounted to either the
topside or land-side of the package substrate. See Figure 7 and Figure 8 for keep-out
zones. The location and quantity of package capacitors may change due to
manufacturing efficiencies but will remain within the component keep-in.
Package Loading Specifications
Table 21 provides dynamic and static load specifications for the processor package.
These mechanical maximum load limits should not be exceeded during heatsink
assembly, shipping conditions, or standard use condition. Also, any mechanical system
or component testing should not exceed the maximum limits. The processor package
substrate should not be used as a mechanical reference or load-bearing surface for
thermal and mechanical solution. The minimum loading specification must be
maintained by any thermal and mechanical solutions.
.
Table 21.
Processor Loading Specifications
Parameter
Minimum
Maximum
Notes
Static
80 N [17 lbf]
-
311 N [70 lbf]
756 N [170 lbf]
1, 2, 3
1, 3, 4
Dynamic
NOTES:
1.
2.
3.
4.
These specifications apply to uniform compressive loading in a direction normal to the
processor IHS.
This is the maximum force that can be applied by a heatsink retention clip. The clip must
also provide the minimum specified load on the processor package.
These specifications are based on limited testing for design characterization. Loading limits
are for the package only and do not include the limits of the processor socket.
Dynamic loading is defined as an 11 ms duration average load superimposed on the static
load requirement.
3.4
Package Handling Guidelines
Table 22 includes a list of guidelines on package handling in terms of recommended
maximum loading on the processor IHS relative to a fixed substrate. These package
handling loads may be experienced during heatsink removal.
Table 22.
Package Handling Guidelines
Parameter
Maximum Recommended
Notes
Shear
Tensile
Torque
311 N [70 lbf]
111 N [25 lbf]
1, 4
2, 4
3, 4
3.95 N-m [35 lbf-in]
NOTES:
1.
2.
3.
4.
A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top
surface.
A tensile load is defined as a pulling load applied to the IHS in a direction normal to the
IHS surface.
A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal
to the IHS top surface.
These guidelines are based on limited testing for design characterization.
Datasheet
39
Package Mechanical Specifications
3.5
3.6
Package Insertion Specifications
The processor can be inserted into and removed from a LGA775 socket 15 times. The
socket should meet the LGA775 requirements detailed in the LGA775 Socket
Mechanical Design Guide.
Processor Mass Specification
The typical mass of the processor is 21.5 g [0.76 oz]. This mass [weight] includes all
the components that are included in the package.
3.7
Processor Materials
Table 23 lists some of the package components and associated materials.
Table 23.
Processor Materials
Component
Material
Integrated Heat Spreader
(IHS)
Nickel Plated Copper
Substrate
Fiber Reinforced Resin
Gold Plated Copper
Substrate Lands
3.8
Processor Markings
Figure 10 shows the topside markings on the processor. This diagram is to aid in the
identification of the processor.
Figure 10.
Processor Top-Side Markings Example
M
INTEL ©'06 E8500
Intel® Core®2 Duo
SLxxx [COO]
3.16GHZ/6M/1333/06
e4
[FPO]
ATPO
S/N
40
Datasheet
Package Mechanical Specifications
3.9
Processor Land Coordinates
Figure 11 shows the top view of the processor land coordinates. The coordinates are
referred to throughout the document to identify processor lands.
.
Figure 11.
Processor Land Coordinates and Quadrants, Top View
VCC / VSS
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
W
V
W
V
Address/
Common Clock/
Async
Socket 775
Quadrants
Top View
U
U
T
T
R
R
P
P
N
N
M
M
L
L
K
K
J
J
H
H
G
G
F
F
E
E
D
D
C
C
B
B
A
A
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
VTT / Clocks
Data
§
Datasheet
41
Package Mechanical Specifications
42
Datasheet
Land Listing and Signal Descriptions
4 Land Listing and Signal
Descriptions
This chapter provides the processor land assignment and signal descriptions.
4.1
Processor Land Assignments
This section contains the land listings for the processor. The land-out footprint is shown
in Figure 12 and Figure 13. These figures represent the land-out arranged by land
number and they show the physical location of each signal on the package land array
(top view). Table 24 lists the processor lands ordered alphabetically by land (signal)
name. Table 25 lists the processor lands ordered numerically by land number.
Datasheet
43
Land Listing and Signal Descriptions
Figure 12.
land-out Diagram (Top View – Left Side)
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AN
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
AM
AL
AK
AJ
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AH
AG
AF
AE
AD
AC
AB
AA
Y
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
W
V
U
T
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
R
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
P
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
N
M
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
L
K
J
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
FC34
VSS
FC31
FC33
VCC
H
BSEL1
FC15
FC32
G
F
BSEL2 BSEL0 BCLK1 TESTHI4 TESTHI5 TESTHI3 TESTHI6 RESET#
RSVD BCLK0 VTT_SEL TESTHI0 TESTHI2 TESTHI7 RSVD
D47#
VSS
D44# DSTBN2# DSTBP2# D35#
D36#
D37#
VSS
D32#
VSS
D31#
D30#
D33#
VSS
D43#
D42#
VSS
D41#
VSS
VSS
D40#
DBI2#
D38#
D39#
VSS
E
D
FC26
VTT
VSS
VTT
VSS
VTT
VSS
VTT
VSS
VTT
FC10
VSS
RSVD
D45#
D46#
D34#
RSVD
VTT
VTT
VCCPLL
D48#
D49#
VCCIO
PLL
C
VTT
VTT
VTT
VTT
VTT
VSS
VSS
D58#
DBI3#
VSS
D54# DSTBP3#
VSS
D51#
B
A
VTT
VTT
30
VTT
VTT
29
VTT
VTT
28
VTT
VTT
27
VTT
VTT
26
VTT
VTT
25
VSS
FC23
24
VSSA
VCCA
23
D63#
D62#
22
D59#
VSS
21
VSS
RSVD
20
D60#
D61#
19
D57#
VSS
18
VSS
D56#
17
D55#
DSTBN3#
16
D53#
VSS
15
44
Datasheet
Land Listing and Signal Descriptions
Figure 13.
land-out Diagram (Top View – Right Side)
14
13
12
11
10
9
8
7
6
5
4
3
2
1
VID_SEL VSS_MB_RE VCC_MB_
VSS_
VCC_
SENSE
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VID0
VSS
AN
ECT
VID7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GULATION REGULATION SENSE
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
FC40
VID3
FC8
VID6
VID1
VSS
VID5
VID4
VSS
VID2
VSS
FC25
FC24
BPM1#
VSS
AM
AL
AK
AJ
VRDSEL PROCHOT#
VCC
VSS
ITP_CLK0
ITP_CLK1
VSS
VSS
VCC
A35#
VSS
A34#
A33#
A31#
A27#
VSS
BPM0#
RSVD
BPM3#
BPM4#
VSS
VCC
A32#
A30#
A28#
RSVD
VSS
AH
AG
AF
AE
AD
AC
AB
VCC
A29#
VSS
BPM5#
VSS
TRST#
TDO
VCC
SKTOCC#
VCC
RSVD
A22#
VSS
FC18
TCK
ADSTB1#
A25#
A24#
FC36
BPM2#
DBR#
IERR#
TDI
VCC
RSVD
A26#
VSS
TMS
VCC
A17#
FC37
VSS
VTT_OUT_
RIGHT
VCC
VCC
VCC
VSS
VSS
VSS
VSS
A19#
A18#
A23#
VSS
A21#
A20#
VSS
VSS
PSII#
FC39
VSS
AA
Y
FC0/
BOOTSELECT
TESTHI12/
FC44
A16#
TESTHI1
MSID0
W
VCC
VCC
VCC
VSS
VSS
VSS
VSS
A10#
VSS
A14#
A12#
A9#
A15#
A13#
A11#
VSS
FC30
VSS
RSVD
FC29
MSID1
FC28
V
U
T
DPRSTP#
COMP1
FERR#/
PBE#
VCC
VSS
ADSTB0#
VSS
A8#
VSS
COMP3
R
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
A4#
VSS
RSVD
RSVD
A5#
VSS
RSVD
A7#
INIT#
VSS
SMI#
DPSLP#
PWRGOOD
VSS
P
N
M
L
IGNNE#
REQ2#
VSS
STPCLK# THERMTRIP#
A3#
A6#
VSS
SLP#
VSS
LINT1
REQ3#
VSS
REQ0#
A20M#
LINT0
K
VTT_OUT_
LEFT
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VSS
VSS
REQ4#
VSS
REQ1#
TESTHI10
PECI
VSS
FC22
VSS
FC3
J
H
FC35
GTLREF1
COMP2
GTLREF0
FC27
TESTHI9/ TESTHI8/
FC43
D29#
D27#
DSTBN1# DBI1#
FC38
D16#
BPRI#
DEFER#
RSVD
G
FC42
BR0#
TRDY#
VSS
D28#
VSS
VSS
D26#
D25#
D24#
DSTBP1#
VSS
D23#
VSS
VSS
D21#
D22#
D18#
D19#
VSS
D17#
VSS
VSS
RSVD
D20#
FC21
RSVD
VSS
RS1#
FC20
VSS
VSS
FC5
VSS
F
HITM#
HIT#
E
D
C
RSVD
D15#
D12#
ADS#
RSVD
DRDY#
VSS
D52#
VSS
VSS
D14#
D11#
VSS
FC41
DSTBN0#
VSS
D3#
D1#
VSS
LOCK#
BNR#
COMP8
D13#
VSS
12
VSS
D9#
11
D10#
D8#
10
DSTBP0#
VSS
VSS
DBI0#
8
D6#
D7#
7
D5#
VSS
6
VSS
D4#
5
D0#
D2#
4
RS0#
RS2#
3
DBSY#
VSS
2
B
A
D50# COMP0
14 13
9
1
Datasheet
45
Land Listing and Signal Descriptions
Table 24.
Alphabetical Land
Assignments
Table 24.
Alphabetical Land
Assignments
Land Signal Buffer
Land Signal Buffer
Land Name
Direction
Land Name
Direction
#
Type
#
Type
A3#
A4#
L5
P6
M5
L4
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
BNR#
BPM0#
BPM1#
BPM2#
BPM3#
BPM4#
BPM5#
BPRI#
BR0#
BSEL0
BSEL1
BSEL2
COMP0
COMP1
COMP2
COMP3
COMP8
D0#
C2 Common Clock Input/Output
AJ2 Common Clock Input/Output
AJ1 Common Clock Input/Output
AD2 Common Clock Input/Output
AG2 Common Clock Input/Output
AF2 Common Clock Input/Output
AG3 Common Clock Input/Output
A5#
A6#
A7#
M4
R4
T5
U6
T4
U5
U4
V5
V4
W5
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
A32#
A33#
A34#
A35#
A20M#
ADS#
ADSTB0#
ADSTB1#
BCLK0
BCLK1
G8 Common Clock
Input
F3 Common Clock Input/Output
G29 Asynch CMOS
H30 Asynch CMOS
G30 Asynch CMOS
Output
Output
Output
Input
A13
T1
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Input
AB6 Source Synch Input/Output
G2
R1
B13
B4
C5
A4
C6
A5
B6
B7
A7
Input
W6
Y6
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Input
Input
Y4
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
AA4 Source Synch Input/Output
AD6 Source Synch Input/Output
AA5 Source Synch Input/Output
AB5 Source Synch Input/Output
AC5 Source Synch Input/Output
AB4 Source Synch Input/Output
AF5 Source Synch Input/Output
AF4 Source Synch Input/Output
AG6 Source Synch Input/Output
AG4 Source Synch Input/Output
AG5 Source Synch Input/Output
AH4 Source Synch Input/Output
AH5 Source Synch Input/Output
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
A10 Source Synch Input/Output
A11 Source Synch Input/Output
B10 Source Synch Input/Output
C11 Source Synch Input/Output
D9#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D8
Source Synch Input/Output
B12 Source Synch Input/Output
C12 Source Synch Input/Output
D11 Source Synch Input/Output
AJ5
AJ6
K3
Source Synch Input/Output
Source Synch Input/Output
Asynch CMOS
Input
G9
F8
F9
E9
D7
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
D2 Common Clock Input/Output
R6 Source Synch Input/Output
AD5 Source Synch Input/Output
F28
Clock
Clock
Input
Input
G28
E10 Source Synch Input/Output
46
Datasheet
Land Listing and Signal Descriptions
Table 24.
Alphabetical Land
Assignments
Table 24.
Alphabetical Land
Assignments
Land Signal Buffer
Land Signal Buffer
Land Name
Direction
Land Name
Direction
#
Type
#
Type
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D10 Source Synch Input/Output
D61#
D62#
A19 Source Synch Input/Output
A22 Source Synch Input/Output
B22 Source Synch Input/Output
F11
F12
Source Synch Input/Output
Source Synch Input/Output
D63#
D13 Source Synch Input/Output
E13 Source Synch Input/Output
G13 Source Synch Input/Output
DBI0#
A8
Source Synch Input/Output
DBI1#
G11 Source Synch Input/Output
D19 Source Synch Input/Output
C20 Source Synch Input/Output
DBI2#
F14
G14 Source Synch Input/Output
F15 Source Synch Input/Output
Source Synch Input/Output
DBI3#
DBR#
AC2
Power/Other
Output
DBSY#
B2 Common Clock Input/Output
G15 Source Synch Input/Output
G16 Source Synch Input/Output
E15 Source Synch Input/Output
E16 Source Synch Input/Output
G18 Source Synch Input/Output
G17 Source Synch Input/Output
DEFER#
DPRSTP#
DPSLP#
DRDY#
G7 Common Clock
Input
Input
Input
T2
P1
Asynch CMOS
Asynch CMOS
C1 Common Clock Input/Output
C8 Source Synch Input/Output
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
G12 Source Synch Input/Output
G20 Source Synch Input/Output
A16 Source Synch Input/Output
F17
F18
Source Synch Input/Output
Source Synch Input/Output
E18 Source Synch Input/Output
E19 Source Synch Input/Output
B9
Source Synch Input/Output
E12 Source Synch Input/Output
G19 Source Synch Input/Output
C17 Source Synch Input/Output
F20
E21 Source Synch Input/Output
F21 Source Synch Input/Output
Source Synch Input/Output
FC0/
BOOTSELECT
Y1
Power/Other
G21 Source Synch Input/Output
E22 Source Synch Input/Output
D22 Source Synch Input/Output
G22 Source Synch Input/Output
D20 Source Synch Input/Output
D17 Source Synch Input/Output
A14 Source Synch Input/Output
C15 Source Synch Input/Output
C14 Source Synch Input/Output
B15 Source Synch Input/Output
C18 Source Synch Input/Output
B16 Source Synch Input/Output
A17 Source Synch Input/Output
B18 Source Synch Input/Output
C21 Source Synch Input/Output
B21 Source Synch Input/Output
B19 Source Synch Input/Output
FC3
J2
F2
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
FC5
FC8
AK6
E24
H29
AE3
E5
FC10
FC15
FC18
FC20
FC21
FC22
FC23
FC24
FC25
FC26
FC27
FC28
FC29
FC30
F6
J3
A24
AK1
AL1
E29
G1
U1
U2
U3
Datasheet
47
Land Listing and Signal Descriptions
Table 24.
Alphabetical Land
Assignments
Table 24.
Alphabetical Land
Assignments
Land Signal Buffer
Land Signal Buffer
Land Name
Direction
Land Name
Direction
#
Type
#
Type
FC31
FC32
J16
H15
H16
J17
H4
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Asynch CMOS
Power/Other
Power/Other
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESET#
RS0#
AE6
AH2
D1
FC33
FC34
D14
D16
E23
E6
FC35
FC36
AD3
AB3
G10
AA2
AM6
C9
FC37
FC38
E7
FC39
F23
F29
G6
FC40
FC41
FERR#/PBE#
GTLREF0
GTLREF1
HIT#
R3
Output
Input
Input
N4
H1
N5
H2
P5
D4 Common Clock Input/Output
E4 Common Clock Input/Output
G23 Common Clock
B3 Common Clock
Input
Input
Input
Input
Output
Input
Input
Input
Input
Input
Output
Input
Input
Input
HITM#
IERR#
AB2 Asynch CMOS
Output
Input
Input
Input
Input
Input
Input
RS1#
F5
Common Clock
IGNNE#
INIT#
N2
P3
Asynch CMOS
Asynch CMOS
TAP
RS2#
A3 Common Clock
SKTOCC#
SLP#
AE8
L2
Power/Other
Asynch CMOS
Asynch CMOS
Asynch CMOS
TAP
ITP_CLK0
ITP_CLK1
LINT0
AK3
AJ3
K1
TAP
SMI#
P2
Asynch CMOS
Asynch CMOS
STPCLK#
TCK
M3
LINT1
L1
AE1
AD1
AF1
F26
W3
H5
LOCK#
MSID0
MSID1
PECI
C3 Common Clock Input/Output
TDI
TAP
W1
V1
Power/Other
Power/Other
Output
Output
TDO
TAP
TESTHI0
TESTHI1
TESTHI10
Power/Other
Power/Other
Power/Other
G5
Power/Other Input/Output
PROCHOT#
PSI#
AL2 Asynch CMOS Input/Output
Y3
N1
K4
Asynch CMOS
Power/Other
Output
Input
TESTHI12/
FC44
W2
Power/Other
Input
PWRGOOD
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
RESERVED
RESERVED
RESERVED
RESERVED
TESTHI2
TESTHI3
F25
G25
G27
G26
G24
F24
G3
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Asynch CMOS
TAP
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
J5
TESTHI4
M6
K6
TESTHI5
TESTHI6
J6
TESTHI7
V2
TESTHI8/FC42
TESTHI9/FC43
THERMTRIP#
TMS
A20
AC4
AE4
G4
M2
AC1
48
Datasheet
Land Listing and Signal Descriptions
Table 24.
Alphabetical Land
Assignments
Table 24.
Alphabetical Land
Assignments
Land Signal Buffer
Land Signal Buffer
Land Name
Direction
Land Name
Direction
#
Type
#
Type
TRDY#
TRST#
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
E3 Common Clock
Input
Input
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AF22 Power/Other
AG1
AA8
AB8
TAP
AF8
AF9
Power/Other
Power/Other
Power/Other
Power/Other
AG11 Power/Other
AG12 Power/Other
AG14 Power/Other
AG15 Power/Other
AG18 Power/Other
AG19 Power/Other
AG21 Power/Other
AG22 Power/Other
AG25 Power/Other
AG26 Power/Other
AG27 Power/Other
AG28 Power/Other
AG29 Power/Other
AG30 Power/Other
AC23 Power/Other
AC24 Power/Other
AC25 Power/Other
AC26 Power/Other
AC27 Power/Other
AC28 Power/Other
AC29 Power/Other
AC30 Power/Other
AC8
Power/Other
AD23 Power/Other
AD24 Power/Other
AD25 Power/Other
AD26 Power/Other
AD27 Power/Other
AD28 Power/Other
AD29 Power/Other
AD30 Power/Other
AG8
AG9
Power/Other
Power/Other
AH11 Power/Other
AH12 Power/Other
AH14 Power/Other
AH15 Power/Other
AH18 Power/Other
AH19 Power/Other
AH21 Power/Other
AH22 Power/Other
AH25 Power/Other
AH26 Power/Other
AH27 Power/Other
AH28 Power/Other
AH29 Power/Other
AH30 Power/Other
AD8
Power/Other
AE11 Power/Other
AE12 Power/Other
AE14 Power/Other
AE15 Power/Other
AE18 Power/Other
AE19 Power/Other
AE21 Power/Other
AE22 Power/Other
AE23 Power/Other
AE9
Power/Other
AF11 Power/Other
AF12 Power/Other
AF14 Power/Other
AF15 Power/Other
AF18 Power/Other
AF19 Power/Other
AF21 Power/Other
AH8
AH9
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AJ11
AJ12
AJ14
AJ15
Datasheet
49
Land Listing and Signal Descriptions
Table 24.
Alphabetical Land
Assignments
Table 24.
Alphabetical Land
Assignments
Land Signal Buffer
Land Signal Buffer
Land Name
Direction
Land Name
Direction
#
Type
#
Type
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AJ18
AJ19
AJ21
AJ22
AJ25
AJ26
AJ8
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AM19 Power/Other
AM21 Power/Other
AM22 Power/Other
AM25 Power/Other
AM26 Power/Other
AM29 Power/Other
AM30 Power/Other
AJ9
AM8
AM9
Power/Other
Power/Other
AK11 Power/Other
AK12 Power/Other
AK14 Power/Other
AK15 Power/Other
AK18 Power/Other
AK19 Power/Other
AK21 Power/Other
AK22 Power/Other
AK25 Power/Other
AK26 Power/Other
AN11 Power/Other
AN12 Power/Other
AN14 Power/Other
AN15 Power/Other
AN18 Power/Other
AN19 Power/Other
AN21 Power/Other
AN22 Power/Other
AN25 Power/Other
AN26 Power/Other
AN29 Power/Other
AN30 Power/Other
AK8
AK9
Power/Other
Power/Other
AL11 Power/Other
AL12 Power/Other
AL14 Power/Other
AL15 Power/Other
AL18 Power/Other
AL19 Power/Other
AL21 Power/Other
AL22 Power/Other
AL25 Power/Other
AL26 Power/Other
AL29 Power/Other
AL30 Power/Other
AN8
AN9
J10
J11
J12
J13
J14
J15
J18
J19
J20
J21
J22
J23
J24
J25
J26
J27
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AL8
AL9
Power/Other
Power/Other
AM11 Power/Other
AM12 Power/Other
AM14 Power/Other
AM15 Power/Other
AM18 Power/Other
50
Datasheet
Land Listing and Signal Descriptions
Table 24.
Alphabetical Land
Assignments
Table 24.
Alphabetical Land
Assignments
Land Signal Buffer
Land Signal Buffer
Land Name
Direction
Land Name
Direction
#
Type
#
Type
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
J28
J29
J30
J8
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
T27
T28
T29
T30
T8
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
J9
K23
K24
K25
K26
K27
K28
K29
K30
K8
U23
U24
U25
U26
U27
U28
U29
U30
U8
L8
V8
M23
M24
M25
M26
M27
M28
M29
M30
M8
W23
W24
W25
W26
W27
W28
W29
W30
W8
N23
N24
N25
N26
N27
N28
N29
N30
N8
Y23
Y24
Y25
Y26
Y27
Y28
Y29
Y30
Y8
P8
VCC_MB_
REGULATION
AN5
Power/Other
Output
Output
R8
VCC_SENSE
VCCA
AN3
A23
C23
D23
AN7
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
T23
T24
T25
T26
VCCIOPLL
VCCPLL
VID_SELECT
Output
Datasheet
51
Land Listing and Signal Descriptions
Table 24.
Alphabetical Land
Assignments
Table 24.
Alphabetical Land
Assignments
Land Signal Buffer
Land Signal Buffer
Land Name
Direction
Land Name
Direction
#
Type
#
Type
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
VRDSEL
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AM2 Asynch CMOS
AL5 Asynch CMOS
AM3 Asynch CMOS
AL6 Asynch CMOS
AK4 Asynch CMOS
AL4 Asynch CMOS
AM5 Asynch CMOS
AM7 Asynch CMOS
Output
Output
Output
Output
Output
Output
Output
Output
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AB26 Power/Other
AB27 Power/Other
AB28 Power/Other
AB29 Power/Other
AB30 Power/Other
AB7
AC3
AC6
AC7
AD4
AD7
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AL3
B1
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
B11
B14
B17
B20
B24
B5
AE10 Power/Other
AE13 Power/Other
AE16 Power/Other
AE17 Power/Other
AE2
Power/Other
B8
AE20 Power/Other
AE24 Power/Other
AE25 Power/Other
AE26 Power/Other
AE27 Power/Other
AE28 Power/Other
AE29 Power/Other
AE30 Power/Other
A12
A15
A18
A2
A21
A6
A9
AA23 Power/Other
AA24 Power/Other
AA25 Power/Other
AA26 Power/Other
AA27 Power/Other
AA28 Power/Other
AA29 Power/Other
AE5
AE7
Power/Other
Power/Other
AF10 Power/Other
AF13 Power/Other
AF16 Power/Other
AF17 Power/Other
AF20 Power/Other
AF23 Power/Other
AF24 Power/Other
AF25 Power/Other
AF26 Power/Other
AF27 Power/Other
AF28 Power/Other
AF29 Power/Other
AA3
Power/Other
AA30 Power/Other
AA6
AA7
AB1
Power/Other
Power/Other
Power/Other
AB23 Power/Other
AB24 Power/Other
AB25 Power/Other
AF3
Power/Other
52
Datasheet
Land Listing and Signal Descriptions
Table 24.
Alphabetical Land
Assignments
Table 24.
Alphabetical Land
Assignments
Land Signal Buffer
Land Signal Buffer
Land Name
Direction
Land Name
Direction
#
Type
#
Type
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AF30 Power/Other
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AK2
Power/Other
AF6
AF7
Power/Other
Power/Other
AK20 Power/Other
AK23 Power/Other
AK24 Power/Other
AK27 Power/Other
AK28 Power/Other
AK29 Power/Other
AK30 Power/Other
AG10 Power/Other
AG13 Power/Other
AG16 Power/Other
AG17 Power/Other
AG20 Power/Other
AG23 Power/Other
AG24 Power/Other
AK5
AK7
Power/Other
Power/Other
AG7
AH1
Power/Other
Power/Other
AL10 Power/Other
AL13 Power/Other
AL16 Power/Other
AL17 Power/Other
AL20 Power/Other
AL23 Power/Other
AL24 Power/Other
AL27 Power/Other
AL28 Power/Other
AH10 Power/Other
AH13 Power/Other
AH16 Power/Other
AH17 Power/Other
AH20 Power/Other
AH23 Power/Other
AH24 Power/Other
AH3
AH6
AH7
AJ10
AJ13
AJ16
AJ17
AJ20
AJ23
AJ24
AJ27
AJ28
AJ29
AJ30
AJ4
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AL7
Power/Other
Power/Other
AM1
AM10 Power/Other
AM13 Power/Other
AM16 Power/Other
AM17 Power/Other
AM20 Power/Other
AM23 Power/Other
AM24 Power/Other
AM27 Power/Other
AM28 Power/Other
AM4
AN1
Power/Other
Power/Other
AN10 Power/Other
AN13 Power/Other
AN16 Power/Other
AN17 Power/Other
AJ7
AK10 Power/Other
AK13 Power/Other
AK16 Power/Other
AK17 Power/Other
AN2
Power/Other
AN20 Power/Other
AN23 Power/Other
Datasheet
53
Land Listing and Signal Descriptions
Table 24.
Alphabetical Land
Assignments
Table 24.
Alphabetical Land
Assignments
Land Signal Buffer
Land Signal Buffer
Land Name
Direction
Land Name
Direction
#
Type
#
Type
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AN24 Power/Other
AN27 Power/Other
AN28 Power/Other
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H12
H13
H14
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H3
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
C10
C13
C16
C19
C22
C24
C4
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
C7
D12
D15
D18
D21
D24
D3
H6
D5
H7
D6
H8
D9
H9
E11
E14
E17
E2
J4
J7
K2
K5
E20
E25
E26
E27
E28
E8
K7
L23
L24
L25
L26
L27
L28
L29
L3
F10
F13
F16
F19
F22
F4
L30
L6
L7
F7
M1
H10
H11
M7
N3
54
Datasheet
Land Listing and Signal Descriptions
Table 24.
Alphabetical Land
Assignments
Table 24.
Alphabetical Land
Assignments
Land Signal Buffer
Land Signal Buffer
Land Name
Direction
Land Name
Direction
#
Type
#
Type
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
N6
N7
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
VSS
VSS
VSS
W7
Y2
Y5
Y7
Power/Other
Power/Other
Power/Other
Power/Other
P23
P24
P25
P26
P27
P28
P29
P30
P4
VSS_MB_
REGULATION
AN6
Power/Other
Output
Output
VSS_SENSE
VSSA
VTT
AN4
B23
B25
B26
B27
B28
B29
B30
A25
A26
A27
A28
A29
A30
C25
C26
C27
C28
C29
C30
D25
D26
D27
D28
D29
D30
J1
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VTT
VTT
VTT
P7
VTT
R2
VTT
R23
R24
R25
R26
R27
R28
R29
R30
R5
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
R7
VTT
T3
VTT
T6
VTT
T7
VTT
U7
VTT
V23
V24
V25
V26
V27
V28
V29
V3
VTT
VTT
VTT
VTT
VTT_OUT_LEFT
Output
Output
Output
VTT_OUT_RIG
HT
AA1
F27
Power/Other
Power/Other
VTT_SEL
V30
V6
V7
W4
Datasheet
55
Land Listing and Signal Descriptions
Table 25.
Numerical Land
Assignment
Table 25.
Numerical Land
Assignment
Signal Buffer
Signal Buffer
Land # Land Name
Direction
Land # Land Name
Direction
Type
Type
A2
A3
VSS
RS2#
D02#
D04#
VSS
Power/Other
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
C1
VSS
D13#
COMP8
VSS
Power/Other
Common Clock
Input
Source Synch Input/Output
A4
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Input
A5
A6
D53#
D55#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
A7
D07#
DBI0#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
A8
A9
D57#
D60#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
B1
D08#
D09#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
D59#
D63#
VSSA
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
COMP0
D50#
VSS
Power/Other
Input
Source Synch Input/Output
Power/Other
Power/Other
DSTBN3#
D56#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
VTT
Power/Other
VTT
Power/Other
VTT
Power/Other
D61#
RESERVED
VSS
Source Synch Input/Output
VTT
Power/Other
VTT
Power/Other
Power/Other
VTT
Power/Other
D62#
VCCA
FC23
VTT
Source Synch Input/Output
Power/Other
DRDY#
BNR#
LOCK#
VSS
Common Clock Input/Output
Common Clock Input/Output
Common Clock Input/Output
Power/Other
C2
Power/Other
C3
Power/Other
C4
VTT
Power/Other
C5
D01#
D03#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
VTT
Power/Other
C6
VTT
Power/Other
C7
VTT
Power/Other
C8
DSTBN0#
FC41
VSS
Source Synch Input/Output
Power/Other
VTT
Power/Other
C9
VSS
Power/Other
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
Power/Other
B2
DBSY#
RS0#
D00#
VSS
Common Clock Input/Output
D11#
D14#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
B3
Common Clock
Input
B4
Source Synch Input/Output
Power/Other
B5
D52#
D51#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
B6
D05#
D06#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
B7
B8
DSTBP3#
D54#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
B9
DSTBP0#
D10#
Source Synch Input/Output
Source Synch Input/Output
B10
56
Datasheet
Land Listing and Signal Descriptions
Table 25.
Numerical Land
Assignment
Table 25.
Numerical Land
Assignment
Signal Buffer
Signal Buffer
Land # Land Name
Direction
Land # Land Name
Direction
Type
Type
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
D1
DBI3#
D58#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
D29
D30
E2
VTT
VTT
Power/Other
Power/Other
Power/Other
Common Clock
VSS
VCCIOPLL
VSS
Power/Other
E3
TRDY#
HITM#
FC20
Input
Power/Other
E4
Common Clock Input/Output
Power/Other
VTT
Power/Other
E5
VTT
Power/Other
E6
RESERVED
RESERVED
VSS
VTT
Power/Other
E7
VTT
Power/Other
E8
Power/Other
VTT
Power/Other
E9
D19#
D21#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
VTT
Power/Other
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
E27
E28
E29
F2
RESERVED
ADS#
VSS
D2
Common Clock Input/Output
Power/Other
DSTBP1#
D26#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
D3
D4
HIT#
VSS
Common Clock Input/Output
Power/Other
D5
D33#
D34#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
D6
VSS
Power/Other
D7
D20#
D12#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
D8
D39#
D40#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D22#
D15#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
D42#
D45#
RESERVED
FC10
Source Synch Input/Output
Source Synch Input/Output
D25#
RESERVED
VSS
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
VSS
RESERVED
D49#
VSS
VSS
Power/Other
Source Synch Input/Output
Power/Other
VSS
Power/Other
VSS
Power/Other
DBI2#
D48#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
FC26
Power/Other
FC5
Power/Other
F3
BR0#
VSS
Common Clock Input/Output
Power/Other
D46#
VCCPLL
VSS
Source Synch Input/Output
Power/Other
F4
F5
RS1#
FC21
Common Clock
Power/Other
Power/Other
Input
Power/Other
F6
VTT
Power/Other
F7
VSS
VTT
Power/Other
F8
D17#
D18#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
VTT
Power/Other
F9
VTT
Power/Other
F10
Datasheet
57
Land Listing and Signal Descriptions
Table 25.
Numerical Land
Assignment
Table 25.
Numerical Land
Assignment
Signal Buffer
Signal Buffer
Land # Land Name
Direction
Land # Land Name
Direction
Type
Type
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
F27
F28
F29
G1
D23#
D24#
Source Synch Input/Output
Source Synch Input/Output
Power/Other
G20
G21
G22
G23
G24
G25
G26
G27
G28
G29
G30
H1
DSTBN2#
D44#
D47#
RESET#
TESTHI6
TESTHI3
TESTHI5
TESTHI4
BCLK1
BSEL0
BSEL2
GTLREF0
GTLREF1
VSS
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
VSS
D28#
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Common Clock
Power/Other
Power/Other
Power/Other
Power/Other
Clock
Input
Input
Input
Input
Input
Input
Output
Output
Input
Input
D30#
VSS
D37#
Source Synch Input/Output
Source Synch Input/Output
Power/Other
D38#
VSS
D41#
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Asynch CMOS
Asynch CMOS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
D43#
VSS
RESERVED
TESTHI7
TESTHI2
TESTHI0
VTT_SEL
BCLK0
RESERVED
FC27
H2
Power/Other
Power/Other
Power/Other
Power/Other
Clock
Input
Input
Input
Output
Input
H3
H4
FC35
TESTHI10
VSS
H5
Input
H6
H7
VSS
H8
VSS
Power/Other
Power/Other
H9
VSS
G2
COMP2
Input
Input
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
VSS
TESTHI8/
FC42
VSS
G3
G4
Power/Other
Power/Other
VSS
TESTHI9/
FC43
Input
VSS
VSS
G5
G6
PECI
RESERVED
DEFER#
BPRI#
D16#
Power/Other Input/Output
FC32
FC33
VSS
G7
Common Clock
Common Clock
Input
Input
G8
VSS
G9
Source Synch Input/Output
Power/Other
VSS
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
FC38
VSS
DBI1#
DSTBN1#
D27#
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
VSS
VSS
VSS
D29#
VSS
D31#
VSS
D32#
VSS
D36#
VSS
D35#
VSS
DSTBP2#
58
Datasheet
Land Listing and Signal Descriptions
Table 25.
Numerical Land
Assignment
Table 25.
Numerical Land
Assignment
Signal Buffer
Signal Buffer
Land # Land Name
Direction
Land # Land Name
Direction
Type
Type
H29
H30
FC15
Power/Other
Asynch CMOS
K8
K23
K24
K25
K26
K27
K28
K29
K30
L1
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
LINT1
SLP#
VSS
A06#
A03#
VSS
VSS
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Asynch CMOS
Asynch CMOS
Power/Other
BSEL1
Output
Output
VTT_OUT_LE
FT
J1
Power/Other
J2
J3
FC3
FC22
VSS
Power/Other
Power/Other
Power/Other
J4
J5
REQ1#
REQ4#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
J6
J7
Input
Input
J8
VCC
Power/Other
L2
J9
VCC
Power/Other
L3
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
J23
J24
J25
J26
J27
J28
J29
J30
K1
VCC
Power/Other
L4
Source Synch Input/Output
Source Synch Input/Output
Power/Other
VCC
Power/Other
L5
VCC
Power/Other
L6
VCC
Power/Other
L7
Power/Other
VCC
Power/Other
L8
Power/Other
VCC
Power/Other
L23
L24
L25
L26
L27
L28
L29
L30
M1
Power/Other
FC31
FC34
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
Power/Other
Power/Other
VCC
Power/Other
Power/Other
VCC
Power/Other
Power/Other
VCC
Power/Other
Power/Other
VCC
Power/Other
Power/Other
VCC
Power/Other
THERMTRIP
#
M2
Asynch CMOS
Asynch CMOS
Output
Input
VCC
Power/Other
VCC
Power/Other
M3
M4
STPCLK#
A07#
A05#
REQ2#
VSS
VCC
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Power/Other
VCC
Power/Other
M5
VCC
Power/Other
M6
VCC
Power/Other
M7
LINT0
VSS
Asynch CMOS
Power/Other
Asynch CMOS
Input
Input
M8
VCC
Power/Other
K2
M23
M24
M25
M26
M27
M28
VCC
Power/Other
K3
A20M#
REQ0#
VSS
VCC
Power/Other
K4
Source Synch Input/Output
Power/Other
VCC
Power/Other
K5
VCC
Power/Other
K6
REQ3#
VSS
Source Synch Input/Output
Power/Other
VCC
Power/Other
K7
VCC
Power/Other
Datasheet
59
Land Listing and Signal Descriptions
Table 25.
Numerical Land
Assignment
Table 25.
Numerical Land
Assignment
Signal Buffer
Signal Buffer
Land # Land Name
Direction
Land # Land Name
Direction
Type
Type
M29
M30
N1
VCC
VCC
Power/Other
Power/Other
Power/Other
Asynch CMOS
Power/Other
R6
R7
ADSTB0#
VSS
Source Synch Input/Output
Power/Other
PWRGOOD
IGNNE#
VSS
Input
Input
R8
VCC
Power/Other
N2
R23
R24
R25
R26
R27
R28
R29
R30
T1
VSS
Power/Other
N3
VSS
Power/Other
N4
RESERVED
RESERVED
VSS
VSS
Power/Other
N5
VSS
Power/Other
N6
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Asynch CMOS
Asynch CMOS
Asynch CMOS
Power/Other
VSS
Power/Other
N7
VSS
VSS
Power/Other
N8
VCC
VSS
Power/Other
N23
N24
N25
N26
N27
N28
N29
N30
P1
VCC
VSS
Power/Other
VCC
COMP1
DPRSTP#
VSS
Power/Other
Asynch CMOS
Power/Other
Input
Input
VCC
T2
VCC
T3
VCC
T4
A11#
A09#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
VCC
T5
VCC
T6
VCC
T7
VSS
Power/Other
DPSLP#
SMI#
INIT#
VSS
Input
Input
Input
T8
VCC
Power/Other
P2
T23
T24
T25
T26
T27
T28
T29
T30
U1
VCC
Power/Other
P3
VCC
Power/Other
P4
VCC
Power/Other
P5
RESERVED
A04#
VSS
VCC
Power/Other
P6
Source Synch Input/Output
Power/Other
VCC
Power/Other
P7
VCC
Power/Other
P8
VCC
Power/Other
VCC
Power/Other
P23
P24
P25
P26
P27
P28
P29
P30
R1
VSS
Power/Other
VCC
Power/Other
VSS
Power/Other
FC28
FC29
FC30
A13#
A12#
A10#
VSS
Power/Other
VSS
Power/Other
U2
Power/Other
VSS
Power/Other
U3
Power/Other
VSS
Power/Other
U4
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Power/Other
VSS
Power/Other
U5
VSS
Power/Other
U6
VSS
Power/Other
U7
COMP3
VSS
Power/Other
Power/Other
Input
U8
VCC
Power/Other
R2
U23
U24
U25
U26
VCC
Power/Other
R3
FERR#/PBE# Asynch CMOS
Output
VCC
Power/Other
R4
A08#
VSS
Source Synch Input/Output
Power/Other
VCC
Power/Other
R5
VCC
Power/Other
60
Datasheet
Land Listing and Signal Descriptions
Table 25.
Numerical Land
Assignment
Table 25.
Numerical Land
Assignment
Signal Buffer
Signal Buffer
Land # Land Name
Direction
Land # Land Name
Direction
Type
Type
U27
U28
U29
U30
V1
VCC
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Y3
Y4
PSI#
A20#
VSS
A19#
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Asynch CMOS
Output
Source Synch Input/Output
Power/Other
VCC
Y5
VCC
Y6
Source Synch Input/Output
Power/Other
MSID1
RESERVED
VSS
Output
Y7
V2
Y8
Power/Other
V3
Power/Other
Y23
Y24
Y25
Y26
Y27
Y28
Y29
Y30
Power/Other
V4
A15#
A14#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
V5
Power/Other
V6
Power/Other
V7
VSS
Power/Other
Power/Other
V8
VCC
Power/Other
Power/Other
V23
V24
V25
V26
V27
V28
V29
V30
W1
VSS
Power/Other
Power/Other
VSS
Power/Other
Power/Other
VSS
Power/Other
VTT_OUT_RI
GHT
AA1
Power/Other
Output
VSS
Power/Other
AA2
AA3
FC39
VSS
Power/Other
Power/Other
VSS
Power/Other
VSS
Power/Other
AA4
A21#
A23#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
VSS
Power/Other
AA5
VSS
Power/Other
AA6
MSID0
Power/Other
Power/Other
Output
Input
Input
AA7
VSS
Power/Other
TESTHI12/
FC44
W2
AA8
VCC
Power/Other
W3
W4
TESTHI1
VSS
Power/Other
Power/Other
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AA30
AB1
VSS
Power/Other
VSS
Power/Other
W5
A16#
A18#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
VSS
Power/Other
W6
VSS
Power/Other
W7
VSS
Power/Other
W8
VCC
Power/Other
VSS
Power/Other
W23
W24
W25
W26
W27
W28
W29
W30
VCC
Power/Other
VSS
Power/Other
VCC
Power/Other
VSS
Power/Other
VCC
Power/Other
VSS
Power/Other
VCC
Power/Other
AB2
IERR#
FC37
A26#
A24#
A17#
VSS
Asynch CMOS
Power/Other
Output
VCC
Power/Other
AB3
VCC
Power/Other
AB4
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Power/Other
VCC
Power/Other
AB5
VCC
Power/Other
AB6
FC0/
BOOTSELECT
AB7
Y1
Y2
Power/Other
Power/Other
AB8
VCC
Power/Other
VSS
AB23
VSS
Power/Other
Datasheet
61
Land Listing and Signal Descriptions
Table 25.
Numerical Land
Assignment
Table 25.
Numerical Land
Assignment
Signal Buffer
Signal Buffer
Land # Land Name
Direction
Land # Land Name
Direction
Type
Type
AB24
AB25
AB26
AB27
AB28
AB29
AB30
AC1
VSS
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
TAP
AE1
AE2
TCK
VSS
TAP
Input
Power/Other
Power/Other
VSS
AE3
FC18
RESERVED
VSS
VSS
AE4
VSS
AE5
Power/Other
VSS
AE6
RESERVED
VSS
VSS
AE7
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
TAP
TMS
Input
AE8
SKTOCC#
VCC
Output
AC2
DBR#
VSS
Power/Other
Power/Other
Output
AE9
AC3
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
AE27
AE28
AE29
AE30
AF1
VSS
AC4
RESERVED
A25#
VSS
VCC
AC5
Source Synch Input/Output
Power/Other
VCC
AC6
VSS
AC7
VSS
Power/Other
VCC
AC8
VCC
Power/Other
VCC
AC23
AC24
AC25
AC26
AC27
AC28
AC29
AC30
AD1
VCC
Power/Other
VSS
VCC
Power/Other
VSS
VCC
Power/Other
VCC
VCC
Power/Other
VCC
VCC
Power/Other
VSS
VCC
Power/Other
VCC
VCC
Power/Other
VCC
VCC
Power/Other
VCC
TDI
TAP
Input
VSS
AD2
BPM2#
FC36
VSS
Common Clock Input/Output
Power/Other
VSS
AD3
VSS
AD4
Power/Other
VSS
AD5
ADSTB1#
A22#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
VSS
AD6
VSS
AD7
VSS
AD8
VCC
Power/Other
TDO
Output
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
VCC
Power/Other
AF2
BPM4#
VSS
Common Clock Input/Output
Power/Other
VCC
Power/Other
AF3
VCC
Power/Other
AF4
A28#
A27#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
VCC
Power/Other
AF5
VCC
Power/Other
AF6
VCC
Power/Other
AF7
VSS
Power/Other
VCC
Power/Other
AF8
VCC
Power/Other
VCC
Power/Other
AF9
VCC
Power/Other
62
Datasheet
Land Listing and Signal Descriptions
Table 25.
Numerical Land
Assignment
Table 25.
Numerical Land
Assignment
Signal Buffer
Signal Buffer
Land # Land Name
Direction
Land # Land Name
Direction
Type
Type
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
AF27
AF28
AF29
AF30
AG1
VSS
VCC
VCC
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
TAP
AG19
AG20
AG21
AG22
AG23
AG24
AG25
AG26
AG27
AG28
AG29
AG30
AH1
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
RESERVED
VSS
A32#
A33#
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
AH2
VSS
AH3
Power/Other
VSS
AH4
Source Synch Input/Output
Source Synch Input/Output
Power/Other
VSS
AH5
VSS
AH6
VSS
AH7
Power/Other
VSS
AH8
Power/Other
VSS
AH9
Power/Other
TRST#
BPM3#
BPM5#
A30#
A31#
A29#
VSS
Input
AH10
AH11
AH12
AH13
AH14
AH15
AH16
AH17
AH18
AH19
AH20
AH21
AH22
AH23
AH24
AH25
AH26
AH27
Power/Other
AG2
Common Clock Input/Output
Common Clock Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
AG3
Power/Other
AG4
Power/Other
AG5
Power/Other
AG6
Power/Other
AG7
Power/Other
AG8
VCC
VCC
VSS
Power/Other
Power/Other
AG9
Power/Other
Power/Other
AG10
AG11
AG12
AG13
AG14
AG15
AG16
AG17
AG18
Power/Other
Power/Other
VCC
VCC
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
VCC
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
Power/Other
Power/Other
VCC
Power/Other
Power/Other
Datasheet
63
Land Listing and Signal Descriptions
Table 25.
Numerical Land
Assignment
Table 25.
Numerical Land
Assignment
Signal Buffer
Signal Buffer
Land # Land Name
Direction
Land # Land Name
Direction
Type
Type
AH28
AH29
AH30
AJ1
VCC
VCC
Power/Other
Power/Other
Power/Other
AK7
AK8
VSS
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
AK9
VCC
BPM1#
BPM0#
ITP_CLK1
VSS
Common Clock Input/Output
Common Clock Input/Output
AK10
AK11
AK12
AK13
AK14
AK15
AK16
AK17
AK18
AK19
AK20
AK21
AK22
AK23
AK24
AK25
AK26
AK27
AK28
AK29
AK30
AL1
VSS
AJ2
VCC
AJ3
TAP
Input
VCC
AJ4
Power/Other
VSS
AJ5
A34#
A35#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
AJ6
VCC
AJ7
VSS
AJ8
VCC
VSS
AJ9
VCC
VCC
AJ10
AJ11
AJ12
AJ13
AJ14
AJ15
AJ16
AJ17
AJ18
AJ19
AJ20
AJ21
AJ22
AJ23
AJ24
AJ25
AJ26
AJ27
AJ28
AJ29
AJ30
AK1
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VSS
VSS
VCC
VSS
VCC
FC25
PROCHOT#
VRDSEL
VID5
VID1
VID3
VSS
VSS
AL2
Asynch CMOS Input/Output
Power/Other
VSS
AL3
VCC
AL4
Asynch CMOS
Asynch CMOS
Asynch CMOS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Output
Output
Output
VCC
AL5
VSS
AL6
VSS
AL7
VSS
AL8
VCC
VSS
AL9
VCC
FC24
VSS
AL10
AL11
AL12
AL13
AL14
AL15
VSS
AK2
VCC
AK3
ITP_CLK0
VID4
VSS
TAP
Input
VCC
AK4
Asynch CMOS
Power/Other
Power/Other
Output
VSS
AK5
VCC
AK6
FC8
VCC
64
Datasheet
Land Listing and Signal Descriptions
Table 25.
Numerical Land
Assignment
Table 25.
Numerical Land
Assignment
Signal Buffer
Signal Buffer
Land # Land Name
Direction
Land # Land Name
Direction
Type
Type
AL16
AL17
AL18
AL19
AL20
AL21
AL22
AL23
AL24
AL25
AL26
AL27
AL28
AL29
AL30
AM1
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VID0
VID2
VSS
VID6
FC40
VID7
VCC
VCC
VSS
VCC
VCC
VSS
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Asynch CMOS
Asynch CMOS
Power/Other
Asynch CMOS
Power/Other
Asynch CMOS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AM25
AM26
AM27
AM28
AM29
AM30
AN1
VCC
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
VSS
VCC
VCC
VSS
AN2
VSS
AN3
VCC_SENSE
VSS_SENSE
Output
Output
AN4
VCC_MB_
REGULATION
AN5
AN6
Power/Other
Power/Other
Output
VSS_MB_
REGULATION
Output
Output
AN7
VID_SELECT
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AN8
AN9
AM10
AM11
AM12
AM13
AM14
AM15
AM16
AM17
AM18
AM19
AM2
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
AN28
AN29
AN30
Output
Output
AM3
AM4
AM5
Output
Output
AM6
AM7
AM8
AM9
AM20
AM21
AM22
AM23
AM24
Datasheet
65
Land Listing and Signal Descriptions
4.2
Alphabetical Signals Reference
Table 26.
Signal Description (Sheet 1 of 10)
Name
Type
Description
A[35:3]# (Address) define a 236-byte physical memory address
space. In sub-phase 1 of the address phase, these signals transmit
the address of a transaction. In sub-phase 2, these signals transmit
transaction type information. These signals must connect the
appropriate pins/lands of all agents on the processor FSB.
A[35:3]# are source synchronous signals and are latched into the
receiving buffers by ADSTB[1:0]#.
Input/
Output
A[35:3]#
On the active-to-inactive transition of RESET#, the processor
samples a subset of the A[35:3]# signals to determine power-on
configuration. See Section 6.1 for more details.
If A20M# (Address-20 Mask) is asserted, the processor masks
physical address bit 20 (A20#) before looking up a line in any
internal cache and before driving a read/write transaction on the
bus. Asserting A20M# emulates the 8086 processor's address
wrap-around at the 1-MB boundary. Assertion of A20M# is only
supported in real mode.
A20M#
Input
A20M# is an asynchronous signal. However, to ensure recognition
of this signal following an Input/Output write instruction, it must be
valid along with the TRDY# assertion of the corresponding Input/
Output Write bus transaction.
ADS# (Address Strobe) is asserted to indicate the validity of the
transaction address on the A[35:3]# and REQ[4:0]# signals. All
bus agents observe the ADS# activation to begin protocol checking,
address decode, internal snoop, or deferred reply ID match
operations associated with the new transaction.
Input/
Output
ADS#
Address strobes are used to latch A[35:3]# and REQ[4:0]# on
their rising and falling edges. Strobes are associated with signals as
shown below.
Input/
Output
ADSTB[1:0]#
Signals
Associated Strobe
REQ[4:0]#, A[16:3]#
A[35:17]#
ADSTB0#
ADSTB1#
The differential pair BCLK (Bus Clock) determines the FSB
frequency. All processor FSB agents must receive these signals to
drive their outputs and latch their inputs.
BCLK[1:0]
BNR#
Input
All external timing parameters are specified with respect to the
rising edge of BCLK0 crossing VCROSS
.
BNR# (Block Next Request) is used to assert a bus stall by any bus
agent unable to accept new bus transactions. During a bus stall,
the current bus owner cannot issue any new transactions.
Input/
Output
66
Datasheet
Land Listing and Signal Descriptions
Table 26.
Signal Description (Sheet 2 of 10)
Name
Type
Description
BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance
monitor signals. They are outputs from the processor which
indicate the status of breakpoints and programmable counters used
for monitoring processor performance. BPM[5:0]# should connect
the appropriate pins/lands of all processor FSB agents.
BPM4# provides PRDY# (Probe Ready) functionality for the TAP
port. PRDY# is a processor output used by debug tools to
determine processor debug readiness.
Input/
Output
BPM[5:0]#
BPM5# provides PREQ# (Probe Request) functionality for the TAP
port. PREQ# is used by debug tools to request debug operation of
the processor.
These signals do not have on-die termination. Refer to
Section 2.6.2 for termination requirements.
BPRI# (Bus Priority Request) is used to arbitrate for ownership of
the processor FSB. It must connect the appropriate pins/lands of all
processor FSB agents. Observing BPRI# active (as asserted by the
priority agent) causes all other agents to stop issuing new
requests, unless such requests are part of an ongoing locked
operation. The priority agent keeps BPRI# asserted until all of its
requests are completed, then releases the bus by de-asserting
BPRI#.
BPRI#
Input
BR0# drives the BREQ0# signal in the system and is used by the
processor to request the bus. During power-on configuration this
signal is sampled to determine the agent ID = 0.
Input/
Output
BR0#
This signal does not have on-die termination and must be
terminated.
The BCLK[1:0] frequency select signals BSEL[2:0] are used to
select the processor input clock frequency. Table 17 defines the
possible combinations of the signals and the frequency associated
with each combination. The required frequency is determined by
the processor, chipset, and clock synthesizer. All agents must
operate at the same frequency. For more information about these
signals, including termination recommendations refer to
Section 2.8.2.
BSEL[2:0]
Output
Analog
COMP[3:0],
COMP8
COMP[3:0] and COMP8 must be terminated to VSS on the system
board using precision resistors.
Datasheet
67
Land Listing and Signal Descriptions
Table 26.
Signal Description (Sheet 3 of 10)
Name
Type
Description
D[63:0]# (Data) are the data signals. These signals provide a 64-
bit data path between the processor FSB agents, and must connect
the appropriate pins/lands on all such agents. The data driver
asserts DRDY# to indicate a valid data transfer.
D[63:0]# are quad-pumped signals and will, thus, be driven four
times in a common clock period. D[63:0]# are latched off the
falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of
16 data signals correspond to a pair of one DSTBP# and one
DSTBN#. The following table shows the grouping of data signals to
data strobes and DBI#.
Quad-Pumped Signal Groups
Input/
Output
D[63:0]#
Data Group
DSTBN#/DSTBP#
DBI#
D[15:0]#
D[31:16]#
D[47:32]#
D[63:48]#
0
1
2
3
0
1
2
3
Furthermore, the DBI# signals determine the polarity of the data
signals. Each group of 16 data signals corresponds to one DBI#
signal. When the DBI# signal is active, the corresponding data
group is inverted and therefore sampled active high.
DBI[3:0]# (Data Bus Inversion) are source synchronous and
indicate the polarity of the D[63:0]# signals.The DBI[3:0]# signals
are activated when the data on the data bus is inverted. If more
than half the data bits, within a 16-bit group, would have been
asserted electrically low, the bus agent may invert the data bus
signals for that particular sub-phase for that 16-bit group.
DBI[3:0] Assignment To Data Bus
Input/
Output
DBI[3:0]#
Bus Signal
Data Bus Signals
DBI3#
DBI2#
DBI1#
DBI0#
D[63:48]#
D[47:32]#
D[31:16]#
D[15:0]#
DBR# (Debug Reset) is used only in processor systems where no
debug port is implemented on the system board. DBR# is used by a
DBR#
Output debug port interposer so that an in-target probe can drive system
reset. If a debug port is implemented in the system, DBR# is a no
connect in the system. DBR# is not a processor signal.
DBSY# (Data Bus Busy) is asserted by the agent responsible for
driving data on the processor FSB to indicate that the data bus is in
use. The data bus is released after DBSY# is de-asserted. This
signal must connect the appropriate pins/lands on all processor FSB
Input/
Output
DBSY#
agents.
68
Datasheet
Land Listing and Signal Descriptions
Table 26.
Signal Description (Sheet 4 of 10)
Name
Type
Description
DEFER# is asserted by an agent to indicate that a transaction
cannot be ensured in-order completion. Assertion of DEFER# is
DEFER#
Input normally the responsibility of the addressed memory or input/
output agent. This signal must connect the appropriate pins/lands
of all processor FSB agents.
DPRSTP#, when asserted on the platform, causes the processor to
transition from the Deep Sleep State to the Deeper Sleep state. To
return to the Deep Sleep State, DPRSTP# must be deasserted. Use
of the DPRSTP# pin, and corresponding low power state, requires
chipset support and may not be available on all platforms.
DPRSTP#
Input
NOTE: Some processors may not have the Deeper Sleep State
enabled, refer to the Specification Update for specific sku
and stepping guidance.
DPSLP#, when asserted on the platform, causes the processor to
transition from the Sleep State to the Deep Sleep state. To return
to the Sleep State, DPSLP# must be deasserted. Use of the
DPSLP# pin, and corresponding low power state, requires chipset
support and may not be available on all platforms.
NOTE: Some processors may not have the Deep Sleep State
enabled, refer to the Specification Update for specific
processor and stepping guidance.
DPSLP#
DRDY#
Input
DRDY# (Data Ready) is asserted by the data driver on each data
transfer, indicating valid data on the data bus. In a multi-common
Input/
clock data transfer, DRDY# may be de-asserted to insert idle
Output
clocks. This signal must connect the appropriate pins/lands of all
processor FSB agents.
DSTBN[3:0]# are the data strobes used to latch in D[63:0]#.
Signals
Associated Strobe
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
Input/
Output
DSTBN[3:0]#
DSTBP[3:0]# are the data strobes used to latch in D[63:0]#.
Signals
Associated Strobe
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
Input/
Output
DSTBP[3:0]#
FC0/BOOTSELECT is not used by the processor. When this land is
FC0/BOOTSELECT Other tied to VSS previous processors based on the Intel NetBurst®
microarchitecture should be disabled and prevented from booting.
FC signals are signals that are available for compatibility with other
processors.
FCx
Other
Datasheet
69
Land Listing and Signal Descriptions
Table 26.
Signal Description (Sheet 5 of 10)
Name
Type
Description
FERR#/PBE# (floating point error/pending break event) is a
multiplexed signal and its meaning is qualified by STPCLK#. When
STPCLK# is not asserted, FERR#/PBE# indicates a floating-point
error and will be asserted when the processor detects an unmasked
floating-point error. When STPCLK# is not asserted, FERR#/PBE# is
similar to the ERROR# signal on the Intel 387 coprocessor, and is
included for compatibility with systems using MS-DOS*-type
floating-point error reporting. When STPCLK# is asserted, an
assertion of FERR#/PBE# indicates that the processor has a
pending break event waiting for service. The assertion of FERR#/
PBE# indicates that the processor should be returned to the Normal
state. For additional information on the pending break event
functionality, including the identification of support of the feature
and enable/disable information, refer to volume 3 of the Intel
Architecture Software Developer's Manual and the Intel Processor
Identification and the CPUID Instruction application note.
FERR#/PBE#
Output
GTLREF[1:0] determine the signal reference level for GTL+ input
GTLREF[1:0]
Input signals. GTLREF is used by the GTL+ receivers to determine if a
signal is a logical 0 or logical 1.
Input/
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction
Output
HIT#
snoop operation results. Any FSB agent may assert both HIT# and
HITM# together to indicate that it requires a snoop stall, which can
HITM#
Input/
be continued by reasserting HIT# and HITM# together.
Output
IERR# (Internal Error) is asserted by a processor as the result of
an internal error. Assertion of IERR# is usually accompanied by a
SHUTDOWN transaction on the processor FSB. This transaction
may optionally be converted to an external error signal (e.g., NMI)
IERR#
Output
by system core logic. The processor will keep IERR# asserted until
the assertion of RESET#.
This signal does not have on-die termination. Refer to Section 2.6.2
for termination requirements.
IGNNE# (Ignore Numeric Error) is asserted to the processor to
ignore a numeric error and continue to execute noncontrol floating-
point instructions. If IGNNE# is de-asserted, the processor
generates an exception on a noncontrol floating-point instruction if
a previous floating-point instruction caused an error. IGNNE# has
IGNNE#
Input
no effect when the NE bit in control register 0 (CR0) is set.
IGNNE# is an asynchronous signal. However, to ensure recognition
of this signal following an Input/Output write instruction, it must be
valid along with the TRDY# assertion of the corresponding Input/
Output Write bus transaction.
INIT# (Initialization), when asserted, resets integer registers inside
the processor without affecting its internal caches or floating-point
registers. The processor then begins execution at the power-on
Reset vector configured during power-on configuration. The
processor continues to handle snoop requests during INIT#
assertion. INIT# is an asynchronous signal and must connect the
appropriate pins/lands of all processor FSB agents.
INIT#
Input
If INIT# is sampled active on the active to inactive transition of
RESET#, then the processor executes its Built-in Self-Test (BIST).
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Datasheet
Land Listing and Signal Descriptions
Table 26.
Signal Description (Sheet 6 of 10)
Name
Type
Description
ITP_CLK[1:0] are copies of BCLK that are used only in processor
systems where no debug port is implemented on the system board.
ITP_CLK[1:0] are used as BCLK[1:0] references for a debug port
implemented on an interposer. If a debug port is implemented in
the system, ITP_CLK[1:0] are no connects in the system. These are
not processor signals.
ITP_CLK[1:0]
Input
LINT[1:0] (Local APIC Interrupt) must connect the appropriate
pins/lands of all APIC Bus agents. When the APIC is disabled, the
LINT0 signal becomes INTR, a maskable interrupt request signal,
and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI
are backward compatible with the signals of those names on the
Pentium processor. Both signals are asynchronous.
LINT[1:0]
Input
Both of these signals must be software configured via BIOS
programming of the APIC register space to be used either as NMI/
INTR or LINT[1:0]. Because the APIC is enabled by default after
Reset, operation of these signals as LINT[1:0] is the default
configuration.
LOCK# indicates to the system that a transaction must occur
atomically. This signal must connect the appropriate pins/lands of
all processor FSB agents. For a locked sequence of transactions,
LOCK# is asserted from the beginning of the first transaction to the
end of the last transaction.
Input/
Output
LOCK#
When the priority agent asserts BPRI# to arbitrate for ownership of
the processor FSB, it will wait until it observes LOCK# de-asserted.
This enables symmetric agents to retain ownership of the processor
FSB throughout the bus locked operation and ensure the atomicity
of lock.
On the processor these signals are connected on the package to
VSS. As an alternative to MSID, Intel has implemented the Power
MSID[1:0]
PECI
Output Segment Identifier (PSID) to report the maximum Thermal Design
Power of the processor. Refer to Section 2.5 for additional
information regarding PSID.
Input/ PECI is a proprietary one-wire bus interface. See Chapter 5.3 for
Output details.
As an output, PROCHOT# (Processor Hot) will go active when the
processor temperature monitoring sensor detects that the
processor has reached its maximum safe operating temperature.
Input/ This indicates that the processor Thermal Control Circuit (TCC) has
Output been activated, if enabled. As an input, assertion of PROCHOT# by
the system will activate the TCC, if enabled. The TCC will remain
active until the system de-asserts PROCHOT#. See Section 5.2.4
for more details.
PROCHOT#
Processor Power Status Indicator Signal. This signal may be
asserted when the processor is in the Deeper Sleep State. PSI# can
be used to improve load efficiency of the voltage regulator,
PSI#
Output
resulting in platform power savings.
Datasheet
71
Land Listing and Signal Descriptions
Table 26.
Signal Description (Sheet 7 of 10)
Name
Type
Description
PWRGOOD (Power Good) is a processor input. The processor
requires this signal to be a clean indication that the clocks and
power supplies are stable and within their specifications. ‘Clean’
implies that the signal will remain low (capable of sinking leakage
current), without glitches, from the time that the power supplies
are turned on until they come within specification. The signal must
then transition monotonically to a high state. PWRGOOD can be
driven inactive at any time, but clocks and power must again be
stable before a subsequent rising edge of PWRGOOD.
PWRGOOD
Input
The PWRGOOD signal must be supplied to the processor; it is used
to protect internal circuits against voltage sequencing issues. It
should be driven high throughout boundary scan operation.
REQ[4:0]# (Request Command) must connect the appropriate
Input/ pins/lands of all processor FSB agents. They are asserted by the
Output current bus owner to define the currently active transaction type.
These signals are source synchronous to ADSTB0#.
REQ[4:0]#
Asserting the RESET# signal resets the processor to a known state
and invalidates its internal caches without writing back any of their
contents. For a power-on Reset, RESET# must stay active for at
least one millisecond after VCC and BCLK have reached their proper
specifications. On observing active RESET#, all FSB agents will de-
assert their outputs within two clocks. RESET# must not be kept
RESET#
Input
asserted for more than 10 ms while PWRGOOD is asserted.
A number of bus signals are sampled at the active-to-inactive
transition of RESET# for power-on configuration. These
configuration options are described in the Section 6.1.
This signal does not have on-die termination and must be
terminated on the system board.
All RESERVED lands must remain unconnected. Connection of these
lands to VCC, VSS, VTT, or to any other signal (including each other)
can result in component malfunction or incompatibility with future
processors.
RESERVED
RS[2:0]# (Response Status) are driven by the response agent (the
agent responsible for completion of the current transaction), and
must connect the appropriate pins/lands of all processor FSB
agents.
RS[2:0]#
SKTOCC#
Input
SKTOCC# (Socket Occupied) will be pulled to ground by the
Output processor. System board designers may use this signal to
determine if the processor is present.
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Datasheet
Land Listing and Signal Descriptions
Table 26.
Signal Description (Sheet 8 of 10)
Name
Type
Description
SLP# (Sleep), when asserted in Extended Stop Grant or Stop Grant
state, causes the processor to enter the Sleep state. In the Sleep
state, the processor stops providing internal clock signals to all
units, leaving only the Phase-Locked Loop (PLL) still operating.
Processors in this state will not recognize snoops or interrupts. The
processor will recognize only assertion of the RESET# signal,
deassertion of SLP#, and removal of the BCLK input while in Sleep
state. If SLP# is de-asserted, the processor exits Sleep state and
SLP#
Input returns to Extended Stop Grant or Stop Grant state, restarting its
internal clock signals to the bus and processor core units. If
DPSLP# is asserted while in the Sleep state, the processor will exit
the Sleep state and transition to the Deep Sleep state. Use of the
SLP# pin, and corresponding low power state, requires chipset
support and may not be available on all platforms.
NOTE: Some processors may not have the Sleep State enabled,
refer to the Specification Update for specific processor and
stepping guidance.
SMI# (System Management Interrupt) is asserted asynchronously
by system logic. On accepting a System Management Interrupt, the
processor saves the current state and enter System Management
Mode (SMM). An SMI Acknowledge transaction is issued, and the
processor begins program execution from the SMM handler.
SMI#
Input
If SMI# is asserted during the de-assertion of RESET#, the
processor will tri-state its outputs.
STPCLK# (Stop Clock), when asserted, causes the processor to
enter a low power Stop-Grant state. The processor issues a Stop-
Grant Acknowledge transaction, and stops providing internal clock
signals to all processor core units except the FSB and APIC units.
STPCLK#
Input The processor continues to snoop bus transactions and service
interrupts while in Stop-Grant state. When STPCLK# is de-
asserted, the processor restarts its internal clock to all units and
resumes execution. The assertion of STPCLK# has no effect on the
bus clock; STPCLK# is an asynchronous input.
TCK (Test Clock) provides the clock input for the processor Test Bus
(also known as the Test Access Port).
TCK
TDI
Input
TDI (Test Data In) transfers serial test data into the processor. TDI
Input
provides the serial input needed for JTAG specification support.
TDO (Test Data Out) transfers serial test data out of the processor.
Output TDO provides the serial output needed for JTAG specification
support.
TDO
The TESTHI[12,10:0] lands must be connected to the processor’s
appropriate power source (refer to VTT_OUT_LEFT and
VTT_OUT_RIGHT signal description) through a resistor for proper
TESTHI[12,10:0]
Input
processor operation. See Section 2.4 for more details.
Datasheet
73
Land Listing and Signal Descriptions
Table 26.
Signal Description (Sheet 9 of 10)
Name
Type
Description
In the event of a catastrophic cooling failure, the processor will
automatically shut down when the silicon has reached a
temperature approximately 20 °C above the maximum TC.
Assertion of THERMTRIP# (Thermal Trip) indicates the processor
junction temperature has reached a level beyond where permanent
silicon damage may occur. Upon assertion of THERMTRIP#, the
processor will shut off its internal clocks (thus, halting program
execution) in an attempt to reduce the processor junction
temperature. To protect the processor, its core voltage (VCC) must
be removed following the assertion of THERMTRIP#. Driving of the
THERMTRIP# signal is enabled within 10 μs of the assertion of
PWRGOOD (provided VTT and VCC are asserted) and is disabled on
de-assertion of PWRGOOD (if VTT or VCC are not valid, THERMTRIP#
may also be disabled). Once activated, THERMTRIP# remains
latched until PWRGOOD, VTT or VCC is de-asserted. While the de-
assertion of the PWRGOOD, VTT or VCC signal will de-assert
THERMTRIP#, if the processor’s junction temperature remains at or
above the trip level, THERMTRIP# will again be asserted within
10 μs of the assertion of PWRGOOD (provided VTT and VCC are
valid).
THERMTRIP#
Output
TMS (Test Mode Select) is a JTAG specification support signal used
by debug tools.
TMS
Input
TRDY# (Target Ready) is asserted by the target to indicate that it is
TRDY#
Input ready to receive a write or implicit writeback data transfer. TRDY#
must connect the appropriate pins/lands of all FSB agents.
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST#
must be driven low during power on Reset.
TRST#
VCC
Input
VCC are the power pins for the processor. The voltage supplied to
these pins is determined by the VID[7:0] pins.
Input
VCCA provides isolated power for internal PLLs on previous
Input generation processors. It may be left as a No-Connect on boards
supporting the processor.
VCCA
VCCIOPLL provides isolated power for internal processor FSB PLLs
Input on previous generation processors. It may be left as a No-Connect
on boards supporting the processor.
VCCIOPLL
VCCPLL
Input VCCPLL provides isolated power for internal processor FSB PLLs.
VCC_SENSE is an isolated low impedance connection to processor
Output core power (VCC). It can be used to sense or measure voltage near
the silicon with little noise.
VCC_SENSE
This land is provided as a voltage regulator feedback sense point
VCC_MB_
REGULATION
for VCC. It is connected internally in the processor package to the
sense point land U27 as described in the Voltage Regulator Design
Output
Guide.
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Datasheet
Land Listing and Signal Descriptions
Table 26.
Signal Description (Sheet 10 of 10)
Name
Type
Description
The VID (Voltage ID) signals are used to support automatic
selection of power supply voltages (VCC). Refer to the Voltage
Regulator Design Guide for more information. The voltage supply
for these signals must be valid before the VR can supply VCC to the
VID[7:0]
Output processor. Conversely, the VR output must be disabled until the
voltage supply for the VID signals becomes valid. The VID signals
are needed to support the processor voltage specification
variations. See Table 2 for definitions of these signals. The VR must
supply the voltage that is requested by the signals, or disable itself.
This land is tied high on the processor package and is used by the
Output VR to choose the proper VID table. Refer to the Voltage Regulator
Design Guide for more information.
VID_SELECT
This input should be left as a no connect in order for the processor
VRDSEL
VSS
Input to boot. The processor will not boot on legacy platforms where this
land is connected to VSS
.
VSS are the ground pins for the processor and should be connected
to the system ground plane.
Input
Input
VSSA provides isolated ground for internal PLLs on previous
generation processors. It may be left as a No-Connect on boards
supporting the processor.
VSSA
VSS_SENSE is an isolated low impedance connection to processor
VSS_SENSE
Output core VSS. It can be used to sense or measure ground near the
silicon with little noise.
This land is provided as a voltage regulator feedback sense point
VSS_MB_
REGULATION
for VSS. It is connected internally in the processor package to the
sense point land V27 as described in the Voltage Regulator Design
Output
Guide.
VTT
Miscellaneous voltage supply.
VTT_OUT_LEFT
The VTT_OUT_LEFT and VTT_OUT_RIGHT signals are included to
Output provide a voltage supply for some signals that require termination
to VTT on the motherboard.
VTT_OUT_RIGHT
VTT_SEL
The VTT_SEL signal is used to select the correct VTT voltage level
Output for the processor. This land is connected internally in the package
to VSS
.
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Datasheet
Land Listing and Signal Descriptions
76
Datasheet
Thermal Specifications and Design Considerations
5 Thermal Specifications and
Design Considerations
5.1
Processor Thermal Specifications
The processor requires a thermal solution to maintain temperatures within the
operating limits as set forth in Section 5.1.1. Any attempt to operate the processor
outside these operating limits may result in permanent damage to the processor and
potentially other components within the system. As processor technology changes,
thermal management becomes increasingly crucial when building computer systems.
Maintaining the proper thermal environment is key to reliable, long-term system
operation.
A complete thermal solution includes both component and system level thermal
management features. Component level thermal solutions can include active or passive
heatsinks attached to the processor Integrated Heat Spreader (IHS). Typical system
level thermal solutions may consist of system fans combined with ducting and venting.
For more information on designing a component level thermal solution, refer to the
appropriate Thermal and Mechanical Design Guidelines (see Section 1.2).
Note:
The boxed processor will ship with a component thermal solution. Refer to Chapter 7
for details on the boxed processor.
5.1.1
Thermal Specifications
To allow for the optimal operation and long-term reliability of Intel processor-based
systems, the system/processor thermal solution should be designed such that the
processor remains within the minimum and maximum case temperature (TC)
specifications when operating at or below the Thermal Design Power (TDP) value listed
per frequency in Table 27. Thermal solutions not designed to provide this level of
thermal capability may affect the long-term reliability of the processor and system. For
more details on thermal solution design, refer to the appropriate Thermal and
Mechanical Design Guidelines (see Section 1.2).
The processor uses a methodology for managing processor temperatures which is
intended to support acoustic noise reduction through fan speed control. Selection of the
appropriate fan speed is based on the relative temperature data reported by the
processor’s Platform Environment Control Interface (PECI) bus as described in
Section 5.3. If the value reported via PECI is less than TCONTROL, then the case
temperature is permitted to exceed the Thermal Profile. If the value reported via PECI
is greater than or equal to TCONTROL, then the processor case temperature must remain
at or below the temperature as specified by the thermal profile. The temperature
reported over PECI is always a negative value and represents a delta below the onset of
thermal control circuit (TCC) activation, as indicated by PROCHOT# (see Section 5.2).
Systems that implement fan speed control must be designed to take these conditions in
to account. Systems that do not alter the fan speed only need to ensure the case
temperature meets the thermal profile specifications.
In order to determine a processor's case temperature specification based on the
thermal profile, it is necessary to accurately measure processor power dissipation. Intel
has developed a methodology for accurate power measurement that correlates to Intel
test temperature and voltage conditions. Refer to the appropriate Thermal and
Mechanical Design Guidelines (see Section 1.2) for the details of this methodology.
Datasheet
77
Thermal Specifications and Design Considerations
The case temperature is defined at the geometric top center of the processor. Analysis
indicates that real applications are unlikely to cause the processor to consume
maximum power dissipation for sustained time periods. Intel recommends that
complete thermal solution designs target the Thermal Design Power (TDP) indicated in
Table 27 instead of the maximum processor power consumption. The Thermal Monitor
feature is designed to protect the processor in the unlikely event that an application
exceeds the TDP recommendation for a sustained periods of time. For more details on
the usage of this feature, refer to Section 5.2. In all cases the Thermal Monitor or
Thermal Monitor 2 feature must be enabled for the processor to remain within
specification.
Table 27.
Processor Thermal Specifications
Thermal Extended
Deeper
Sleep
Power
(W)2
Core
Frequency
(GHz)
775_VR_
CONFIG_06
Guidance5
Processor
Number
Design
Power
(W)3,4
HALT
Power
(W)1
Minimum Maximum
Notes
TC (°C)
TC (°C)
E8600
E8500
E8400
E8300
E8200
E8190
3.33
3.16
3
65.0
65.0
65.0
65.0
65.0
65.0
8
8
8
8
8
8
6
6
6
6
6
6
5
5
5
5
5
5
See
Table 28
and
775_VR_
CONFIG_06
(65 W)
2.83
2.66
2.66
Figure 14
E7500
E7400
E7300
E7200
2.93
2.80
2.66
2.53
65.0
65.0
65.0
65.0
8
8
8
8
6
6
6
6
5
5
5
5
See
Table 29
and
775_VR_CONFIG
_06
(65 W)
Figure 15
NOTES:
1.
2.
3.
4.
Specification is at 36 °C TC and minimum voltage loadline. Specification is ensured by
design characterization and not 100% tested.
Specification is at 34 °C TC and minimum voltage loadline. Specification is ensured by
design characterization and not 100% tested.
Thermal Design Power (TDP) should be used for processor thermal solution design targets.
The TDP is not the maximum power that the processor can dissipate.
This table shows the maximum TDP for a given frequency range. Individual processors
may have a lower TDP. Therefore, the maximum TC will vary depending on the TDP of the
individual processor. Refer to thermal profile figure and associated table for the allowed
combinations of power and TC.
5.
775_VR_CONFIG_06 guidelines provide a design target for meeting future thermal
requirements.
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Datasheet
Thermal Specifications and Design Considerations
Table 28.
Intel® Core™2 Duo Processor E8000 Series Thermal Profile
Power
(W)
MaximumTc
(°C)
Power
(W)
MaximumTc
(°C)
Power
(W)
MaximumTc
(°C)
0
2
45.1
45.9
46.8
47.6
48.5
49.3
50.1
51.0
51.8
52.7
53.5
54.3
24
26
28
30
32
34
36
38
40
42
44
46
55.2
56.0
56.9
57.7
58.5
59.4
60.2
61.1
61.9
62.7
63.6
64.4
48
50
52
54
56
58
60
62
64
65
65.3
66.1
66.9
67.8
68.6
69.5
70.3
71.1
72.0
72.4
4
6
8
10
12
14
16
18
20
22
Figure 14.
Intel® Core™2 Duo Processor E8000 Series Thermal Profile
72.0
68.0
64.0
y = 0.42x + 45.1
60.0
56.0
52.0
48.0
44.0
0
10
20
30
Power (W)
40
50
60
Datasheet
79
Thermal Specifications and Design Considerations
Table 29.
Intel® Core™2 Duo Processor E7000 Series Thermal Profile
Maximum Tc
(°C)
Maximum Tc
(°C)
Maximum Tc
(°C)
Power (W)
Power
Power
0
2
44.9
45.8
46.7
47.6
48.5
49.4
50.3
51.2
52.1
53.0
53.9
54.8
24
26
28
30
32
34
36
38
40
42
44
46
55.7
56.6
57.5
58.4
59.3
60.2
61.1
62.0
62.9
63.8
64.7
65.6
48
50
52
54
56
58
60
62
64
65
66.5
67.4
68.3
69.2
70.1
71.0
71.9
72.8
73.7
74.1
4
6
8
10
12
14
16
18
20
22
Figure 15.
Intel® Core™2 Duo Processor E7000 Series Thermal Profile
72.0
68.0
64.0
y = 0.45x + 44.9
60.0
56.0
52.0
48.0
44.0
0
10
20
30
Power (W)
40
50
60
80
Datasheet
Thermal Specifications and Design Considerations
5.1.2
Thermal Metrology
The maximum and minimum case temperatures (TC) for the processor is specified in
Table 27. This temperature specification is meant to help ensure proper operation of
the processor. Figure 16 illustrates where Intel recommends TC thermal measurements
should be made. For detailed guidelines on temperature measurement methodology,
refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2).
Figure 16.
Case Temperature (TC) Measurement Location
Measure TC at this point
(geometric center of the package)
37.5 mm
5.2
Processor Thermal Features
5.2.1
Thermal Monitor
The Thermal Monitor feature helps control the processor temperature by activating the
thermal control circuit (TCC) when the processor silicon reaches its maximum operating
temperature. The TCC reduces processor power consumption by modulating (starting
and stopping) the internal processor core clocks. The Thermal Monitor feature must
be enabled for the processor to be operating within specifications. The
temperature at which Thermal Monitor activates the thermal control circuit is not user
configurable and is not software visible. Bus traffic is snooped in the normal manner,
and interrupt requests are latched (and serviced during the time that the clocks are on)
while the TCC is active.
When the Thermal Monitor feature is enabled, and a high temperature situation exists
(i.e., TCC is active), the clocks will be modulated by alternately turning the clocks off
and on at a duty cycle specific to the processor (typically 30–50%). Clocks often will
not be off for more than 3.0 microseconds when the TCC is active. Cycle times are
processor speed dependent and will decrease as processor core frequencies increase. A
small amount of hysteresis has been included to prevent rapid active/inactive
transitions of the TCC when the processor temperature is near its maximum operating
temperature. Once the temperature has dropped below the maximum operating
temperature, and the hysteresis timer has expired, the TCC goes inactive and clock
modulation ceases.
With a properly designed and characterized thermal solution, it is anticipated that the
TCC would only be activated for very short periods of time when running the most
power intensive applications. The processor performance impact due to these brief
Datasheet
81
Thermal Specifications and Design Considerations
periods of TCC activation is expected to be so minor that it would be immeasurable. An
under-designed thermal solution that is not able to prevent excessive activation of the
TCC in the anticipated ambient environment may cause a noticeable performance loss,
and in some cases may result in a TC that exceeds the specified maximum temperature
and may affect the long-term reliability of the processor. In addition, a thermal solution
that is significantly under-designed may not be capable of cooling the processor even
when the TCC is active continuously. Refer to the appropriate Thermal and Mechanical
Design Guidelines (see Section 1.2) for information on designing a thermal solution.
The duty cycle for the TCC, when activated by the Thermal Monitor, is factory
configured and cannot be modified. The Thermal Monitor does not require any
additional hardware, software drivers, or interrupt handling routines.
5.2.2
Thermal Monitor 2
The processor also supports an additional power reduction capability known as Thermal
Monitor 2. This mechanism provides an efficient means for limiting the processor
temperature by reducing the power consumption within the processor.
When Thermal Monitor 2 is enabled, and a high temperature situation is detected, the
Thermal Control Circuit (TCC) will be activated. The TCC causes the processor to adjust
its operating frequency (via the bus multiplier) and input voltage (via the VID signals).
This combination of reduced frequency and VID results in a reduction to the processor
power consumption.
A processor enabled for Thermal Monitor 2 includes two operating points, each
consisting of a specific operating frequency and voltage. The first operating point
represents the normal operating condition for the processor. Under this condition, the
core-frequency-to-FSB multiple used by the processor is that contained in the
CLK_GEYSIII_STAT MSR and the VID is that specified in Table 4. These parameters
represent normal system operation.
The second operating point consists of both a lower operating frequency and voltage.
When the TCC is activated, the processor automatically transitions to the new
frequency. This transition occurs very rapidly (on the order of 5 μs). During the
frequency transition, the processor is unable to service any bus requests, and
consequently, all bus traffic is blocked. Edge-triggered interrupts will be latched and
kept pending until the processor resumes operation at the new frequency.
Once the new operating frequency is engaged, the processor will transition to the new
core operating voltage by issuing a new VID code to the voltage regulator. The voltage
regulator must support dynamic VID steps in order to support Thermal Monitor 2.
During the voltage change, it will be necessary to transition through multiple VID codes
to reach the target operating voltage. Each step will likely be one VID table entry (see
Table 4). The processor continues to execute instructions during the voltage transition.
Operation at the lower voltage reduces the power consumption of the processor.
A small amount of hysteresis has been included to prevent rapid active/inactive
transitions of the TCC when the processor temperature is near its maximum operating
temperature. Once the temperature has dropped below the maximum operating
temperature, and the hysteresis timer has expired, the operating frequency and
voltage transition back to the normal system operating point. Transition of the VID code
will occur first, in order to ensure proper operation once the processor reaches its
normal operating frequency. Refer to Figure 17 for an illustration of this ordering.
82
Datasheet
Thermal Specifications and Design Considerations
Figure 17.
Thermal Monitor 2 Frequency and Voltage Ordering
TTM2
Temperature
Frequency
fMAX
fTM2
VID
VIDTM2
VID
PROCHOT#
The PROCHOT# signal is asserted when a high temperature situation is detected,
regardless of whether Thermal Monitor or Thermal Monitor 2 is enabled.
It should be noted that the Thermal Monitor 2 TCC cannot be activated via the on
demand mode. The Thermal Monitor TCC, however, can be activated through the use of
the on demand mode.
5.2.3
On-Demand Mode
The processor provides an auxiliary mechanism that allows system software to force
the processor to reduce its power consumption. This mechanism is referred to as “On-
Demand” mode and is distinct from the Thermal Monitor feature. On-Demand mode is
intended as a means to reduce system level power consumption. Systems using the
processor must not rely on software usage of this mechanism to limit the processor
temperature.
If bit 4 of the ACPI P_CNT Control Register (located in the processor
IA32_THERM_CONTROL MSR) is written to a '1', the processor will immediately reduce
its power consumption via modulation (starting and stopping) of the internal core clock,
independent of the processor temperature. When using On-Demand mode, the duty
cycle of the clock modulation is programmable via bits 3:1 of the same ACPI P_CNT
Control Register. In On-Demand mode, the duty cycle can be programmed from 12.5%
on/87.5% off, to 87.5% on/12.5% off in 12.5% increments. On-Demand mode may be
used in conjunction with the Thermal Monitor. If the system tries to enable On-Demand
mode at the same time the TCC is engaged, the factory configured duty cycle of the
TCC will override the duty cycle selected by the On-Demand mode.
5.2.4
PROCHOT# Signal
An external signal, PROCHOT# (processor hot), is asserted when the processor core
temperature has reached its maximum operating temperature. If the Thermal Monitor
is enabled (note that the Thermal Monitor must be enabled for the processor to be
Datasheet
83
Thermal Specifications and Design Considerations
operating within specification), the TCC will be active when PROCHOT# is asserted. The
processor can be configured to generate an interrupt upon the assertion or de-
assertion of PROCHOT#.
PROCHOT# is a bi-directional signal. As an output, PROCHOT# (Processor Hot) will go
active when the processor temperature monitoring sensor detects that one or both
cores has reached its maximum safe operating temperature. This indicates that the
processor Thermal Control Circuit (TCC) has been activated, if enabled. As an input,
assertion of PROCHOT# by the system will activate the TCC, if enabled, for both cores.
The TCC will remain active until the system de-asserts PROCHOT#.
Note:
PROCHOT# will not be asserted (as an output) or observed (as an input) when the
processor is in the Stop Grant, Sleep, Deep Sleep, and Deeper Sleep low-power states,
hence the thermal solution must be designed to ensure the processor remains within
specification. If the processor enters one of the above low-power states with
PROCHOT# already asserted, PROCHOT# will remain asserted until the processor exits
the low-power state and the processor DTS temperature drops below the thermal trip
point.
PROCHOT# allows for some protection of various components from over-temperature
situations. The PROCHOT# signal is bi-directional in that it can either signal when the
processor (either core) has reached its maximum operating temperature or be driven
from an external source to activate the TCC. The ability to activate the TCC via
PROCHOT# can provide a means for thermal protection of system components.
Bi-directional PROCHOT# can allow VR thermal designs to target maximum sustained
current instead of maximum current. Systems should still provide proper cooling for the
VR, and rely on bi-directional PROCHOT# only as a backup in case of system cooling
failure. The system thermal design should allow the power delivery circuitry to operate
within its temperature specification even while the processor is operating at its Thermal
Design Power. With a properly designed and characterized thermal solution, it is
anticipated that bi-directional PROCHOT# would only be asserted for very short periods
of time when running the most power intensive applications. An under-designed
thermal solution that is not able to prevent excessive assertion of PROCHOT# in the
anticipated ambient environment may cause a noticeable performance loss. Refer to
the Voltage Regulator Design Guide for details on implementing the bi-directional
PROCHOT# feature.
5.2.5
THERMTRIP# Signal
Regardless of whether or not Thermal Monitor or Thermal Monitor 2 is enabled, in the
event of a catastrophic cooling failure, the processor will automatically shut down when
the silicon has reached an elevated temperature (refer to the THERMTRIP# definition in
Table 26). At this point, the FSB signal THERMTRIP# will go active and stay active as
described in Table 26. THERMTRIP# activation is independent of processor activity and
does not generate any bus cycles. If THERMTRIP# is asserted, processor core voltage
(VCC) must be removed within the timeframe defined in Table 11.
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Thermal Specifications and Design Considerations
5.3
Platform Environment Control Interface (PECI)
5.3.1
Introduction
PECI offers an interface for thermal monitoring of Intel processor and chipset
components. It uses a single wire, thus alleviating routing congestion issues. PECI uses
CRC checking on the host side to ensure reliable transfers between the host and client
devices. Also, data transfer speeds across the PECI interface are negotiable within a
wide range (2 Kbps to 2 Mbps). The PECI interface on the processor is disabled by
default and must be enabled through BIOS. More information can be found in the
Platform Environment Control Interface (PECI) Specification.
5.3.1.1
T
and TCC activation on PECI-Based Systems
CONTROL
Fan speed control solutions based on PECI utilize a TCONTROL value stored in the
processor IA32_TEMPERATURE_TARGET MSR. The TCONTROL MSR uses the same offset
temperature format as PECI though it contains no sign bit. Thermal management
devices should infer the TCONTROL value as negative. Thermal management algorithms
should utilize the relative temperature value delivered over PECI in conjunction with the
T
CONTROL MSR value to control or optimize fan speeds. Figure 18 shows a conceptual
fan control diagram using PECI temperatures.
The relative temperature value reported over PECI represents the delta below the onset
of thermal control circuit (TCC) activation as indicated by PROCHOT# assertions. As the
temperature approaches TCC activation, the PECI value approaches zero. TCC activates
at a PECI count of zero.
Figure 18.
Conceptual Fan Control Diagram on PECI-Based Platforms
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Thermal Specifications and Design Considerations
5.3.2
PECI Specifications
5.3.2.1
PECI Device Address
The PECI register resides at address 30h.
5.3.2.2
5.3.2.3
PECI Command Support
PECI command support is covered in detail in the Platform Environment Control
Interface Specification. Refer to this document for details on supported PECI command
function and codes.
PECI Fault Handling Requirements
PECI is largely a fault tolerant interface, including noise immunity and error checking
improvements over other comparable industry standard interfaces. The PECI client is
as reliable as the device that it is embedded in, and thus given operating conditions
that fall under the specification, the PECI will always respond to requests and the
protocol itself can be relied upon to detect any transmission failures. There are,
however, certain scenarios where the PECI is know to be unresponsive.
Prior to a power-on RESET# and during RESET# assertion, PECI is not assured to
provide reliable thermal data. System designs should implement a default power-on
condition that ensures proper processor operation during the time frame when reliable
data is not available via PECI.
To protect platforms from potential operational or safety issues due to an abnormal
condition on PECI, the Host controller should take action to protect the system from
possible damage. It is recommended that the PECI host controller take appropriate
action to protect the client processor device if valid temperature readings have not
been obtained in response to three consecutive GetTemp()s or for a one second time
interval. The host controller may also implement an alert to software in the event of a
critical or continuous fault condition.
5.3.2.4
PECI GetTemp0() Error Code Support
The error codes supported for the processor GetTemp() command are listed in
Table 30:
Table 30.
GetTemp0() Error Codes
Error Code
8000h
Description
General sensor error
Sensor is operational, but has detected a temperature below its operational
range (underflow)
8002h
§ §
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6 Features
6.1
Power-On Configuration Options
Several configuration options can be configured by hardware. The processor samples
the hardware configuration at reset, on the active-to-inactive transition of RESET#. For
specifications on these options, refer to Table 31.
The sampled information configures the processor for subsequent operation. These
configuration options cannot be changed except by another reset. All resets reconfigure
the processor; for configuration purposes, the processor does not distinguish between
a "warm" reset and a "power-on" reset.
Table 31.
Power-On Configuration Option Signals
Configuration Option
Output tristate
Signal1,2
SMI#
Execute BIST
A3#
A25#
Disable dynamic bus parking
Symmetric agent arbitration ID
RESERVED
BR0#
A[24:4]#, A[35:26]#
NOTE:
1.
2.
Asserting this signal during RESET# will select the corresponding option.
Address signals not identified in this table as configuration options should not be asserted
during RESET#.
3.
Disabling of any of the cores within the processors must be handled by configuring the
EXT_CONFIG Model Specific Register (MSR). This MSR will allow for the disabling of a
single core per die within the processor package.
6.2
Clock Control and Low Power States
The processor allows the use of AutoHALT and Stop-Grant states to reduce power
consumption by stopping the clock to internal sections of the processor, depending on
each particular state. See Figure 19 for a visual representation of the processor low
power states.
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Features
Figure 19.
Processor Low Power State Machine
HALT or MWAIT Instruction and
HALT Bus Cycle Generated
Extended HALT or HALT
State
- BCLK running
- Snoops and interrupts
allowed
Normal State
INIT#, INTR, NMI, SMI#, RESET#,
FSB interrupts
- Normal Execution
Snoop
Event
Occurs
Snoop
Event
Serviced
STPCLK#
Asserted
STPCLK#
De-asserted
STPCLK#
De-asserted
STPCLK#
Asserted
Extended HALT Snoop or
HALT Snoop State
- BCLK running
- Service Snoops to caches
Stop Grant State
- BCLK running
- Snoops and interrupts
allowed
Snoop Event Occurs
Extended Stop Grant or
Stop Grant Snoop State
- BCLK running
Snoop Event Serviced
- Service Snoops to caches
SLP#
Asserted
SLP#
De-asserted
DPRSTP#
Asserted
DPSLP#
Asserted
Deeper Sleep State
- BCLK can be stopped
- No Snoops or
interrupts allowed
- PECI unavailable in
this state
Sleep State
Deep Sleep State
- BCLK can be stopped
- No Snoops or
interrupts allowed
- PECI unavailable in
this state
- BCLK running
- No Snoops or
interrupts allowed
- PECI unavailable in
this state
DPSLP#
De-asserted
DPRSTP#
De-asserted
6.2.1
6.2.2
Normal State
This is the normal operating state for the processor.
HALT and Extended HALT Powerdown States
The processor supports the HALT or Extended HALT powerdown state. The Extended
HALT powerdown state must be configured and enabled via the BIOS for the processor
to remain within specification.
The Extended HALT state is a lower power state as compared to the Stop Grant State.
If Extended HALT is not enabled, the default powerdown state entered will be HALT.
Refer to the sections below for details about the HALT and Extended HALT states.
6.2.2.1
HALT Powerdown State
HALT is a low power state entered when all the processor cores have executed the HALT
or MWAIT instructions. When one of the processor cores executes the HALT instruction,
that processor core is halted, however, the other processor continues normal operation.
The halted core will transition to the Normal state upon the occurrence of SMI#, INIT#,
or LINT[1:0] (NMI, INTR). RESET# will cause the processor to immediately initialize
itself.
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The return from a System Management Interrupt (SMI) handler can be to either
Normal Mode or the HALT powerdown state. See the Intel Architecture Software
Developer's Manual, Volume 3B: System Programming Guide, Part 2 for more
information.
The system can generate a STPCLK# while the processor is in the HALT powerdown
state. When the system deasserts the STPCLK# interrupt, the processor will return
execution to the HALT state.
While in HALT powerdown state, the processor will process bus snoops.
6.2.2.2
Extended HALT Powerdown State
Extended HALT is a low power state entered when all processor cores have executed
the HALT or MWAIT instructions and Extended HALT has been enabled via the BIOS.
When one of the processor cores executes the HALT instruction, that logical processor
is halted; however, the other processor continues normal operation. The Extended
HALT powerdown state must be enabled via the BIOS for the processor to remain
within its specification.
The processor will automatically transition to a lower frequency and voltage operating
point before entering the Extended HALT state. Note that the processor FSB frequency
is not altered; only the internal core frequency is changed. When entering the low
power state, the processor will first switch to the lower bus ratio and then transition to
the lower VID.
While in Extended HALT state, the processor will process bus snoops.
The processor exits the Extended HALT state when a break event occurs. When the
processor exits the Extended HALT state, it will resume operation at the lower
frequency, transition the VID to the original value, and then change the bus ratio back
to the original value.
6.2.3
Stop Grant and Extended Stop Grant States
The processor supports the Stop Grant and Extended Stop Grant states. The Extended
Stop Grant state is a feature that must be configured and enabled via the BIOS. Refer
to the sections below for details about the Stop Grant and Extended Stop Grant states.
6.2.3.1
Stop-Grant State
When the STPCLK# signal is asserted, the Stop Grant state of the processor is entered
20 bus clocks after the response phase of the processor-issued Stop Grant
Acknowledge special bus cycle.
Since the GTL+ signals receive power from the FSB, these signals should not be driven
(allowing the level to return to VTT) for minimum power drawn by the termination
resistors in this state. In addition, all other input signals on the FSB should be driven to
the inactive state.
RESET# will cause the processor to immediately initialize itself, but the processor will
stay in Stop-Grant state. A transition back to the Normal state will occur with the de-
assertion of the STPCLK# signal.
A transition to the Grant Snoop state will occur when the processor detects a snoop on
the FSB (see Section 6.2.4).
While in the Stop-Grant State, SMI#, INIT# and LINT[1:0] will be latched by the
processor, and only serviced when the processor returns to the Normal State. Only one
occurrence of each event will be recognized upon return to the Normal state.
While in Stop-Grant state, the processor will process a FSB snoop.
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Features
6.2.3.2
Extended Stop Grant State
Extended Stop Grant is a low power state entered when the STPCLK# signal is asserted
and Extended Stop Grant has been enabled via the BIOS.
The processor will automatically transition to a lower frequency and voltage operating
point before entering the Extended Stop Grant state. When entering the low power
state, the processor will first switch to the lower bus ratio and then transition to the
lower VID.
The processor exits the Extended Stop Grant state when a break event occurs. When
the processor exits the Extended Stop Grant state, it will resume operation at the lower
frequency, transition the VID to the original value, and then change the bus ratio back
to the original value.
6.2.4
Extended HALT Snoop State, HALT Snoop State, Extended
Stop Grant Snoop State, and Stop Grant Snoop State
The Extended HALT Snoop State is used in conjunction with the Extended HALT state. If
Extended HALT state is not enabled in the BIOS, the default Snoop State entered will
be the HALT Snoop State. Refer to the sections below for details on HALT Snoop State,
Stop Grant Snoop State, Extended HALT Snoop State, Extended Stop Grant Snoop
State.
6.2.4.1
6.2.4.2
HALT Snoop State, Stop Grant Snoop State
The processor will respond to snoop transactions on the FSB while in Stop-Grant state
or in HALT powerdown state. During a snoop transaction, the processor enters the HALT
Snoop State:Stop Grant Snoop state. The processor will stay in this state until the
snoop on the FSB has been serviced (whether by the processor or another agent on the
FSB). After the snoop is serviced, the processor will return to the Stop Grant state or
HALT powerdown state, as appropriate.
Extended HALT Snoop State, Extended Stop Grant Snoop State
The processor will remain in the lower bus ratio and VID operating point of the
Extended HALT state or Extended Stop Grant state.
While in the Extended HALT Snoop State or Extended Stop Grant Snoop State, snoops
are handled the same way as in the HALT Snoop State or Stop Grant Snoop State. After
the snoop is serviced the processor will return to the Extended HALT state or Extended
Stop Grant state.
6.2.5
Sleep State
The Sleep state is a low power state in which the processor maintains its context,
maintains the phase-locked loop (PLL), and stops all internal clocks. The Sleep state is
entered through assertion of the SLP# signal while in the Extended Stop Grant or Stop
Grant state. The SLP# pin should only be asserted when the processor is in the
Extended Stop Grant or Stop Grant state. SLP# assertions while the processor is not in
these states is out of specification and may result in unapproved operation.
In the Sleep state, the processor is incapable of responding to snoop transactions or
latching interrupt signals. No transitions or assertions of signals (with the exception of
SLP#, DPSLP# or RESET#) are allowed on the FSB while the processor is in Sleep
state. Snoop events that occur while in Sleep state or during a transition into or out of
Sleep state will cause unpredictable behavior. Any transition on an input signal before
the processor has returned to the Stop-Grant state will result in unpredictable
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behavior.If RESET# is driven active while the processor is in the Sleep state, and held
active as specified in the RESET# pin specification, then the processor will reset itself,
ignoring the transition through the Stop-Grant state.
If RESET# is driven active while the processor is in the Sleep state, the SLP# and
STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure
the processor correctly executes the Reset sequence.
While in the Sleep state, the processor is capable of entering an even lower power
state, the Deep Sleep state, by asserting the DPSLP# pin (See Section Section 6.2.6).
While the processor is in the Sleep state, the SLP# pin must be deasserted if another
asynchronous FSB event needs to occur. PECI is not available and will not respond
while in the Sleep State. Refer to the appropriate Thermal and Mechanical Design
Guidelines (see Section 1.2) for guidance on how to ensure PECI thermal data is
available when the Sleep State is enabled.
6.2.6
Deep Sleep State
The Deep Sleep state is entered through assertion of the DPSLP# pin while in the Sleep
state. BCLK may be stopped during the Deep Sleep state for additional platform level
power savings. BCLK stop/restart timings on appropriate chipset-based platforms with
the CK505 clock chip are as follows:
• Deep Sleep entry: the system clock chip may stop/tristate BCLK within two BCLKs
of DPSLP# assertion. It is permissible to leave BCLK running during Deep Sleep.
• Deep Sleep exit: the system clock chip must drive BCLK to differential DC levels
within 2-3 ns of DPSLP# deassertion and start toggling BCLK within 10 BCLK
periods.
To re-enter the Sleep state, the DPSLP# pin must be deasserted. BCLK can be restarted
after DPSLP# deassertion as described above. A period of 15 microseconds (to allow for
PLL stabilization) must occur before the processor can be considered to be in the Sleep
state. Once in the Sleep state, the SLP# pin must be deasserted to re-enter the Stop-
Grant state.
While in the Deep Sleep state the processor is incapable of responding to snoop
transactions or latching interrupt signals. No transitions of signals are allowed on the
FSB while the processor is in the Deep Sleep state. When the processor is in the Deep
Sleep state it will not respond to interrupts or snoop transactions. Any transition on an
input signal before the processor has returned to the Stop-Grant state will result in
unpredictable behavior. PECI is not available and will not respond while in the Deep
Sleep State. Refer to the appropriate Thermal and Mechanical Design Guidelines (see
Section 1.2) for guidance on how to ensure PECI thermal data is available when the
Deep Sleep State is enabled.
6.2.7
Deeper Sleep State
The Deeper Sleep state is similar to the Deep Sleep state but the core voltage is
reduced to a lower level. The Deeper Sleep state is entered through assertion of the
DPRSTP# pin while in the Deep Sleep state. Exit from Deeper Sleep is initiated by
DPRSTP# deassertion. PECI is not available and will not respond while in the Deeper
Sleep State. Refer to the appropriate Thermal and Mechanical Design Guidelines (see
Section 1.2) for guidance on how to ensure PECI thermal data is available when the
Deeper Sleep State is enabled.
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Features
In response to entering Deeper Sleep, the processor drives the VID code corresponding
to the Deeper Sleep core voltage on the VID pins. Unlike typical Dynamic VID changes
(where the steps are single VID steps) the processor will perform a VID jump on the
order of 100 mV. To support the Deeper Sleep State the platform must use a VRD 11.1
compliant solution.
®
6.2.8
Enhanced Intel SpeedStep Technology
The processor supports Enhanced Intel SpeedStep Technology. This technology enables
the processor to switch between frequency and voltage points, which may result in
platform power savings. To support this technology, the system must support dynamic
VID transitions. Switching between voltage/frequency states is software controlled.
Enhanced Intel SpeedStep Technology is a technology that creates processor
performance states (P states). P states are power consumption and capability states
within the Normal state as shown in Figure 19. Enhanced Intel SpeedStep Technology
enables real-time dynamic switching between frequency and voltage points. It alters
the performance of the processor by changing the bus to core frequency ratio and
voltage. This allows the processor to run at different core frequencies and voltages to
best serve the performance and power requirements of the processor and system. Note
that the front side bus is not altered; only the internal core frequency is changed. In
order to run at reduced power consumption, the voltage is altered in step with the bus
ratio.
The following are key features of Enhanced Intel SpeedStep Technology:
• Voltage/Frequency selection is software controlled by writing to processor MSR's
(Model Specific Registers), thus eliminating chipset dependency.
— If the target frequency is higher than the current frequency, Vcc is incriminated
in steps (+12.5 mV) by placing a new value on the VID signals after which the
processor shifts to the new frequency. Note that the top frequency for the
processor can not be exceeded.
— If the target frequency is lower than the current frequency, the processor shifts
to the new frequency and Vcc is then decremented in steps (-12.5 mV) by
changing the target VID through the VID signals.
6.3
Processor Power Status Indicator (PSI) Signal
The processor incorporates the PSI# signal that is asserted when the processor is in a
reduced power consumption state. PSI# can be used to improve efficiency of the
voltage regulator, resulting in platform power savings.
PSI# may be asserted only when the processor is in the Deeper Sleep state.
§
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Boxed Processor Specifications
7 Boxed Processor Specifications
7.1
Introduction
The processor will also be offered as an Intel boxed processor. Intel boxed processors
are intended for system integrators who build systems from baseboards and standard
components. The boxed processor will be supplied with a cooling solution. This chapter
documents baseboard and system requirements for the cooling solution that will be
supplied with the boxed processor. This chapter is particularly important for OEMs that
manufacture baseboards for system integrators.
Note:
Note:
Unless otherwise noted, all figures in this chapter are dimensioned in millimeters and
inches [in brackets]. Figure 20 shows a mechanical representation of a boxed
processor.
Drawings in this section reflect only the specifications on the Intel boxed processor
product. These dimensions should not be used as a generic keep-out zone for all
cooling solutions. It is the system designers’ responsibility to consider their proprietary
cooling solution when designing to the required keep-out zone on their system
platforms and chassis. Refer to the appropriate Thermal and Mechanical Design
Guidelines (see Section 1.2) for further guidance. Contact your local Intel Sales
Representative for this document.
Figure 20.
Mechanical Representation of the Boxed Processor
NOTE: The airflow of the fan heatsink is into the center and out of the sides of the fan heatsink.
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Boxed Processor Specifications
7.2
Mechanical Specifications
7.2.1
Boxed Processor Cooling Solution Dimensions
This section documents the mechanical specifications of the boxed processor. The
boxed processor will be shipped with an unattached fan heatsink. Figure 20 shows a
mechanical representation of the boxed processor.
Clearance is required around the fan heatsink to ensure unimpeded airflow for proper
cooling. The physical space requirements and dimensions for the boxed processor with
assembled fan heatsink are shown in Figure 21 (Side View), and Figure 22 (Top View).
The airspace requirements for the boxed processor fan heatsink must also be
incorporated into new baseboard and system designs. Airspace requirements are
shown in Figure 26 and Figure 27. Note that some figures have centerlines shown
(marked with alphabetic designations) to clarify relative dimensioning.
Figure 21.
Space Requirements for the Boxed Processor (Side View)
95.0
[3.74]
81.3
[3.2]
10.0
25.0
[0.39]
[0.98]
Figure 22.
Space Requirements for the Boxed Processor (Top View)
95.0
[3.74]
95.0
[3.74]
NOTES:
1.
Diagram does not show the attached hardware for the clip design and is provided only as a
mechanical representation.
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Boxed Processor Specifications
Figure 23.
Overall View Space Requirements for the Boxed Processor
7.2.2
7.2.3
Boxed Processor Fan Heatsink Weight
The boxed processor fan heatsink will not weigh more than 450 grams. See Chapter 5
and the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2) for
details on the processor weight and heatsink requirements.
Boxed Processor Retention Mechanism and Heatsink
Attach Clip Assembly
The boxed processor thermal solution requires a heatsink attach clip assembly, to
secure the processor and fan heatsink in the baseboard socket. The boxed processor
will ship with the heatsink attach clip assembly.
7.3
Electrical Requirements
7.3.1
Fan Heatsink Power Supply
The boxed processor's fan heatsink requires a +12 V power supply. A fan power cable
will be shipped with the boxed processor to draw power from a power header on the
baseboard. The power cable connector and pinout are shown in Figure 24. Baseboards
must provide a matched power header to support the boxed processor. Table 32
contains specifications for the input and output signals at the fan heatsink connector.
The fan heatsink outputs a SENSE signal, which is an open- collector output that pulses
at a rate of 2 pulses per fan revolution. A baseboard pull-up resistor provides VOH to
match the system board-mounted fan speed monitor requirements, if applicable. Use of
the SENSE signal is optional. If the SENSE signal is not used, pin 3 of the connector
should be tied to GND.
The fan heatsink receives a PWM signal from the motherboard from the 4th pin of the
connector labeled as CONTROL.
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Boxed Processor Specifications
The boxed processor's fanheat sink requires a constant +12 V supplied to pin 2 and
does not support variable voltage control or 3-pin PWM control.
The power header on the baseboard must be positioned to allow the fan heatsink power
cable to reach it. The power header identification and location should be documented in
the platform documentation, or on the system board itself. Figure 25 shows the
location of the fan power connector relative to the processor socket. The baseboard
power header should be positioned within 110 mm [4.33 inches] from the center of the
processor socket.
Figure 24.
Boxed Processor Fan Heatsink Power Cable Connector Description
Signal
Pin
Straight square pin, 4-pin terminal housing with
polarizing ribs and friction locking ramp.
1
2
3
4
GND
+12 V
0.100" pitch, 0.025" square pin width.
SENSE
CONTROL
Match with straight pin, friction lock header on
mainboard.
3 4
1 2
Table 32.
Fan Heatsink Power and Signal Specifications
Description
Min
Typ
Max
Unit
Notes
+12 V: 12 volt fan power supply
11.4
12
12.6
V
-
IC:
• Maximum fan steady-state current draw
• Average fan steady-state current draw
• Maximum fan start-up current draw
—
—
—
—
1.2
0.5
2.2
1.0
—
—
—
—
A
A
A
-
• Fan start-up current draw maximum
duration
Second
pulses per
fan
1
SENSE: SENSE frequency
—
2
—
revolution
2, 3
CONTROL
21
25
28
kHz
NOTES:
1. Baseboard should pull this pin up to 5 V with a resistor.
2. Open drain type, pulse width modulated.
3. Fan will have pull-up resistor for this signal to maximum of 5.25 V.
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Figure 25.
Baseboard Power Header Placement Relative to Processor Socket
R110
[4.33]
B
C
7.4
Thermal Specifications
This section describes the cooling requirements of the fan heatsink solution used by the
boxed processor.
7.4.1
Boxed Processor Cooling Requirements
The boxed processor may be directly cooled with a fan heatsink. However, meeting the
processor's temperature specification is also a function of the thermal design of the
entire system, and ultimately the responsibility of the system integrator. The processor
temperature specification is provided in Chapter 5. The boxed processor fan heatsink is
able to keep the processor temperature within the specifications (see Table 27) in
chassis that provide good thermal management. For the boxed processor fan heatsink
to operate properly, it is critical that the airflow provided to the fan heatsink is
unimpeded. Airflow of the fan heatsink is into the center and out of the sides of the fan
heatsink. Airspace is required around the fan to ensure that the airflow through the fan
heatsink is not blocked. Blocking the airflow to the fan heatsink reduces the cooling
efficiency and decreases fan life. Figure 26 and Figure 27 illustrate an acceptable
airspace clearance for the fan heatsink. The air temperature entering the fan should be
kept below 38 ºC. Again, meeting the processor's temperature specification is the
responsibility of the system integrator.
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Boxed Processor Specifications
Figure 26.
Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view)
Figure 27.
Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 2 view)
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Boxed Processor Specifications
7.4.2
Variable Speed Fan
If the boxed processor fan heatsink 4-pin connector is connected to a 3-pin
motherboard header it will operate as follows:
The boxed processor fan will operate at different speeds over a short range of
internal chassis temperatures. This allows the processor fan to operate at a lower
speed and noise level, while internal chassis temperatures are low. If internal
chassis temperature increases beyond a lower set point, the fan speed will rise
linearly with the internal temperature until the higher set point is reached. At that
point, the fan speed is at its maximum. As fan speed increases, so does fan noise
levels. Systems should be designed to provide adequate air around the boxed
processor fan heatsink that remains cooler then lower set point. These set points,
represented in Figure 28 and Table 33, can vary by a few degrees from fan heatsink
to fan heatsink. The internal chassis temperature should be kept below 38 ºC.
Meeting the processor's temperature specification (see Chapter 5) is the
responsibility of the system integrator.
The motherboard must supply a constant +12 V to the processor's power header to
ensure proper operation of the variable speed fan for the boxed processor. Refer to
Table 32 for the specific requirements.
Figure 28.
Boxed Processor Fan Heatsink Set Points
Higher Set Point
Highest Noise Level
Increasing Fan
Speed & Noise
Lower Set Point
Lowest Noise Level
X
Y
Z
Internal Chassis Temperature (Degrees C)
Datasheet
99
Boxed Processor Specifications
Table 33.
Fan Heatsink Power and Signal Specifications
Boxed Processor
Fan Heatsink Set
Point (°C)
Boxed Processor Fan Speed
Notes
When the internal chassis temperature is below or equal to
this set point, the fan operates at its lowest speed.
Recommended maximum internal chassis temperature for
nominal operating environment.
1
X ≤ 30
When the internal chassis temperature is at this point, the fan
operates between its lowest and highest speeds.
Recommended maximum internal chassis temperature for
worst-case operating environment.
Y = 35
-
-
When the internal chassis temperature is above or equal to
this set point, the fan operates at its highest speed.
Z ≥ 38
NOTES:
1. Set point variance is approximately ± 1 °C from fan heatsink to fan heatsink.
If the boxed processor fan heatsink 4-pin connector is connected to a 4-pin
motherboard header and the motherboard is designed with a fan speed controller with
PWM output (CONTROL see Table 32) and remote thermal diode measurement
capability the boxed processor will operate as follows:
As processor power has increased the required thermal solutions have generated
increasingly more noise. Intel has added an option to the boxed processor that allows
system integrators to have a quieter system in the most common usage.
The 4th wire PWM solution provides better control over chassis acoustics. This is
achieved by more accurate measurement of processor die temperature through the
processor's Digital Thermal Sensors (DTS) and PECI. Fan RPM is modulated through the
use of an ASIC located on the motherboard that sends out a PWM control signal to the
4th pin of the connector labeled as CONTROL. The fan speed is based on actual
processor temperature instead of internal ambient chassis temperatures.
If the new 4-pin active fan heat sink solution is connected to an older 3-pin baseboard
processor fan header, it will default back to a thermistor controlled mode, allowing
compatibility with existing 3-pin baseboard designs. Under thermistor controlled mode,
the fan RPM is automatically varied based on the Tinlet temperature measured by a
thermistor located at the fan inlet.
For more details on specific motherboard requirements for 4-wire based fan speed
control, refer to the appropriate Thermal and Mechanical Design Guidelines (see
Section 1.2).
§
100
Datasheet
Debug Tools Specifications
8 Debug Tools Specifications
8.1
Logic Analyzer Interface (LAI)
Intel is working with two logic analyzer vendors to provide logic analyzer interfaces
(LAIs) for use in debugging Intel Core™2 Duo processor E8000 and E7000 series
systems. Tektronix and Agilent should be contacted to get specific information about
their logic analyzer interfaces. The following information is general in nature. Specific
information must be obtained from the logic analyzer vendor.
Due to the complexity of Intel Core™2 Duo processor E8000 and E7000 series systems,
the LAI is critical in providing the ability to probe and capture FSB signals. There are
two sets of considerations to keep in mind when designing an Intel Core™2 Duo
processor E8000 and E7000 series system that can make use of an LAI: mechanical
and electrical.
8.1.1
Mechanical Considerations
The LAI is installed between the processor socket and the processor. The LAI lands plug
into the processor socket, while the processor lands plug into a socket on the LAI.
Cabling that is part of the LAI egresses the system to allow an electrical connection
between the processor and a logic analyzer. The maximum volume occupied by the LAI,
known as the keepout volume, as well as the cable egress restrictions, should be
obtained from the logic analyzer vendor. System designers must make sure that the
keepout volume remains unobstructed inside the system. Note that it is possible that
the keepout volume reserved for the LAI may differ from the space normally occupied
by the processor heatsink. If this is the case, the logic analyzer vendor will provide a
cooling solution as part of the LAI.
8.1.2
Electrical Considerations
The LAI will also affect the electrical performance of the FSB; therefore, it is critical to
obtain electrical load models from each of the logic analyzers to be able to run system
level simulations to prove that their tool will work in the system. Contact the logic
analyzer vendor for electrical specifications and load models for the LAI solution it
provides.
§
Datasheet
101
Debug Tools Specifications
102
Datasheet
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