9000 [INTEL]
Dual-Core Intel Itanium Processor; 双核英特尔®安腾®处理器
| 型号： | 9000 |
| 厂家： | 
INTEL |
| 描述： | Dual-Core Intel Itanium Processor |
| 文件： | 总108页 (文件大小：1808K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
®
Dual-Core Intel Itanium Processor
9000 and 9100 Series
Dual-Core Intel® Itanium® Processor 1.6 GHz with 24 MB L3 Cache 9050
Dual-Core Intel® Itanium® Processor 1.6 GHz with 18 MB L3 Cache 9040
Dual-Core Intel® Itanium® Processor 1.6 GHz with 8 MB L3 Cache 9030
Dual-Core Intel® Itanium® Processor 1.42 GHz with 12 MB L3 Cache 9020
Dual-Core Intel® Itanium® Processor 1.4 GHz with 12 MB L3 Cache 9015
Intel® Itanium® Processor 1.6 GHz with 6 MB L3 Cache 9010
Dual-Core Intel® Itanium® Processor 1.66/1.6 GHz with 24 MB L3 Cache 9152
Dual-Core Intel® Itanium® Processor 1.66 GHz with 24 MB L3 Cache 9150M
Dual-Core Intel® Itanium® Processor 1.6 GHz with 24 MB L3 Cache 9150N
Dual-Core Intel® Itanium® Processor 1.66 GHz with 18 MB L3 Cache 9140M
Dual-Core Intel® Itanium® Processor 1.6 GHz with 18 MB L3 Cache 9140N
Dual-Core Intel® Itanium® Processor 1.42 GHz with 12 MB L3 Cache 9120N
Dual-Core Intel® Itanium® Processor 1.66 GHz with 8 MB L3 Cache 9130M
Intel® Itanium® Processor 1.6 GHz with 12 MB L3 Cache 9110N
Datasheet
October 2007
Document Number: 314054-002
®
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED,
BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS
PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER,
AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING
LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY
PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving,
life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future
changes to them
®
®
The Dual-Core Intel Itanium 9000 and 9100 series processor may contain design defects or errors known as errata which may
cause the product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained
by calling1-800-548-4725, or by visiting Intel's website at http://www.intel.com.
Intel, Itanium, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United
States and other countries.
Copyright © 2002-2007, Intel Corporation
*Other names and brands may be claimed as the property of others.
I2C is a two-wire communication bus /protocol developed by Phillips. SMBus is a subset of the I2C bus/protocol developed by Intel.
Implementation of the I2C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including Phillips
Electronics, N.V. and North American Phillips Corporation.
®
®
2
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Contents
1
Introduction............................................................................................................... 11
1.1
1.2
1.3
1.4
1.5
1.6
Overview ......................................................................................................... 11
Processor Abstraction Layer................................................................................ 11
Mixing Processors of Different Frequencies and Cache Sizes .................................... 12
Terminology ..................................................................................................... 12
State of Data.................................................................................................... 12
Reference Documents........................................................................................ 13
2
Electrical Specifications ............................................................................................... 15
2.1
Dual-Core Intel® Itanium® Processor 9000 and 9100 Series System Bus.................. 15
2.1.1
2.1.2
System Bus Power Pins ........................................................................ 15
System Bus No Connect ....................................................................... 15
2.2
System Bus Signals ........................................................................................... 15
2.2.1
2.2.2
Signal Groups ..................................................................................... 15
Signal Descriptions .............................................................................. 17
2.3
2.4
Package Specifications ....................................................................................... 18
Signal Specifications.......................................................................................... 18
2.4.1
Maximum Ratings................................................................................ 22
2.5
System Bus Signal Quality Specifications and Measurement Guidelines..................... 23
2.5.1
2.5.2
2.5.3
2.5.4
2.5.5
Overshoot/Undershoot Magnitude.......................................................... 23
Overshoot/Undershoot Pulse Duration .................................................... 24
Activity Factor..................................................................................... 24
Reading Overshoot/Undershoot Specification Tables................................. 24
Determining if a System Meets the Overshoot/Undershoot
Specifications...................................................................................... 25
Wired-OR Signals ................................................................................ 25
2.5.6
2.6
2.7
2.8
Voltage Regulator Connector Signals.................................................................... 27
System Bus Clock and Processor Clocking............................................................. 31
Recommended Connections for Unused Pins.......................................................... 33
3
4
Pinout Specifications................................................................................................... 35
Mechanical Specifications............................................................................................. 65
4.1
Processor Package Dimensions............................................................................ 65
4.1.1 Voltage Regulator (MVR) to Processor Package Interface........................... 71
Package Marking............................................................................................... 72
4.2
4.2.1
4.2.2
Processor Top-Side Marking .................................................................. 72
Processor Bottom-Side Marking ............................................................. 73
5
6
Thermal Specifications ................................................................................................ 75
5.1
Thermal Features .............................................................................................. 75
5.1.1
5.1.2
5.1.3
5.1.4
Thermal Alert...................................................................................... 75
Enhanced Thermal Management ............................................................ 76
Power Trip.......................................................................................... 76
Thermal Trip....................................................................................... 76
5.2
Case Temperature............................................................................................. 76
System Management Feature Specifications................................................................... 79
6.1
System Management Bus ................................................................................... 79
6.1.1
6.1.2
6.1.3
System Management Bus Interface........................................................ 79
System Management Interface Signals ................................................... 79
SMBus Device Addressing..................................................................... 81
6.2
6.3
Processor Information ROM ................................................................................ 82
Scratch EEPROM ............................................................................................... 85
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
3
6.4
Processor Information ROM and Scratch EEPROM Supported SMBus
Transactions .....................................................................................................85
Thermal Sensing Device .....................................................................................86
Thermal Sensing Device Supported SMBus Transactions..........................................87
Thermal Sensing Device Registers........................................................................88
6.5
6.6
6.7
6.7.1
6.7.2
6.7.3
6.7.4
6.7.5
Thermal Reference Registers .................................................................88
Thermal Limit Registers ........................................................................89
Status Register....................................................................................89
Configuration Register ..........................................................................89
Conversion Rate Register ......................................................................90
A
Signals Reference .......................................................................................................91
A.1
Alphabetical Signals Reference ............................................................................91
A.1.1 A[49:3]# (I/O).......................................................................................91
A.1.2 A20M# (I) .............................................................................................91
A.1.3 ADS# (I/O)............................................................................................91
A.1.4 AP[1:0]# (I/O).......................................................................................91
A.1.5 ASZ[1:0]# (I/O).....................................................................................91
A.1.6 ATTR[3:0]# (I/O) ...................................................................................92
A.1.7 BCLKp/BCLKn (I)....................................................................................92
A.1.8 BE[7:0]# (I/O).......................................................................................92
A.1.9 BERR# (I/O)..........................................................................................93
A.1.10 BINIT# (I/O)..........................................................................................94
A.1.11 BNR# (I/O)............................................................................................94
A.1.12 BPM[5:0]# (I/O) ....................................................................................94
A.1.13 BPRI# (I) ..............................................................................................94
A.1.14 BR[0]# (I/O) and BR[3:1]# (I).................................................................94
A.1.15 BREQ[3:0]# (I/O)...................................................................................95
A.1.16 CCL# (I/O) ............................................................................................96
A.1.17 CPUPRES# (O) .......................................................................................96
A.1.18 D[127:0]# (I/O).....................................................................................96
A.1.19 D/C# (I/O) ............................................................................................96
A.1.20 DBSY# (I/O)..........................................................................................96
A.1.21 DBSY_C1# (O).......................................................................................96
A.1.22 DBSY_C2# (O).......................................................................................96
A.1.23 DEFER# (I)............................................................................................96
A.1.24 DEN# (I/O)............................................................................................97
A.1.25 DEP[15:0]# (I/O)...................................................................................97
A.1.26 DHIT# (I)..............................................................................................97
A.1.27 DPS# (I/O)............................................................................................98
A.1.28 DRDY# (I/O)..........................................................................................98
A.1.29 DRDY_C1# (O).......................................................................................98
A.1.30 DRDY_C2# (O).......................................................................................98
A.1.31 DSZ[1:0]# (I/O) ....................................................................................98
A.1.32 EXF[4:0]# (I/O).....................................................................................98
A.1.33 FCL# (I/O) ............................................................................................99
A.1.34 FERR# (O).............................................................................................99
A.1.35 GSEQ# (I).............................................................................................99
A.1.36 HIT# (I/O) and HITM# (I/O)....................................................................99
A.1.37 ID[9:0]# (I) ..........................................................................................99
A.1.38 IDS# (I)................................................................................................99
A.1.39 IGNNE# (I)............................................................................................99
A.1.40 INIT# (I)...............................................................................................99
A.1.41 INT (I) ................................................................................................100
A.1.42 IP[1:0]# (I).........................................................................................100
A.1.43 LEN[2:0]# (I/O)...................................................................................100
A.1.44 LINT[1:0] (I) .......................................................................................100
®
®
4
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
A.1.45 LOCK# (I/O)........................................................................................ 100
A.1.46 NMI (I) ............................................................................................... 101
A.1.47 OWN# (I/O) ........................................................................................ 101
A.1.48 PMI# (I) ............................................................................................. 101
A.1.49 PWRGOOD (I)...................................................................................... 101
A.1.50 REQ[5:0]# (I/O).................................................................................. 101
A.1.51 RESET# (I) ......................................................................................... 102
A.1.52 RP# (I/O) ........................................................................................... 102
A.1.53 RS[2:0]# (I) ....................................................................................... 103
A.1.54 RSP# (I)............................................................................................. 103
A.1.55 SBSY# (I/O)........................................................................................ 103
A.1.56 SBSY_C1# (O)..................................................................................... 103
A.1.57 SBSY_C2# (O)..................................................................................... 103
A.1.58 SPLCK# (I/O) ...................................................................................... 103
A.1.59 STBn[7:0]# and STBp[7:0]# (I/O)......................................................... 103
A.1.60 TCK (I) ............................................................................................... 104
A.1.61 TDI (I)................................................................................................ 104
A.1.62 TDO (O).............................................................................................. 104
A.1.63 THRMTRIP# (O)................................................................................... 104
A.1.64 THRMALERT# (O)................................................................................. 104
A.1.65 TMS (I)............................................................................................... 104
A.1.66 TND# (I/O) ......................................................................................... 104
A.1.67 TRDY# (I)........................................................................................... 105
A.1.68 TRST# (I) ........................................................................................... 105
A.1.69 WSNP# (I/O)....................................................................................... 105
Signal Summaries ........................................................................................... 105
A.2
Figures
2-1
Generic Clock Waveform .................................................................................... 21
SMSC Clock Waveform....................................................................................... 22
System Bus Signal Waveform Exhibiting Overshoot/Undershoot............................... 23
Processors Power Tab Physical Layout.................................................................. 28
System Bus Reset and Configuration Timings for Cold Reset.................................... 31
System Bus Reset and Configuration Timings for Warm Reset ................................. 32
Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Pinout.......................... 35
Processor Package............................................................................................. 66
Package Height and Pin Dimensions..................................................................... 67
Processor Package Mechanical Interface Dimensions .............................................. 69
Processor Package Top-Side Components Height Dimensions .................................. 70
Processor Package Bottom-Side Components Height Dimensions ............................. 70
Processor to MVR Interface Loads........................................................................ 71
Processor Top-Side Marking on IHS ..................................................................... 73
Processor Bottom-Side Marking Placement on Interposer........................................ 74
Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Thermal
2-2
2-3
2-4
2-5
2-6
3-1
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
5-1
Features .......................................................................................................... 75
Itanium® Processor Package Thermocouple Location.............................................. 77
Logical Schematic of SMBus Circuitry ................................................................... 80
5-2
6-1
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
5
Tables
2-1
Itanium® Processor System Bus Signal Groups......................................................16
Nominal Resistance Values for Tuner1, Tuner2, and Tuner3.....................................17
Processor Package Specifications .........................................................................18
AGTL+ Signals DC Specifications..........................................................................19
Power Good Signal DC Specifications....................................................................19
System Bus Clock Differential HSTL DC Specifications.............................................19
TAP Connection DC Specifications ........................................................................19
SMBus DC Specifications.....................................................................................20
LVTTL Signal DC Specifications ............................................................................20
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10 System Bus Clock Differential HSTL AC Specifications .............................................20
2-11 SMBus AC Specifications.....................................................................................21
2-12 Dual-Core Intel® Itanium® Processor Absolute Maximum Ratings.............................22
2-13 Source Synchronous AGTL+ Signal Group and Wired-OR Signal Group
Absolute Overshoot/Undershoot Tolerance ............................................................25
2-14 Source Synchronous AGTL+ Signal Group Time-Dependent Overshoot/
Undershoot Tolerance for 400-MHz System Bus .....................................................26
2-15 Wired-OR Signal Group (BINIT#, HIT#, HITM#, BNR#, TND#, BERR#)
Overshoot/Undershoot Tolerance for 400-MHz System Bus......................................26
2-16 Source Synchronous AGTL+ Signal Group Time-Dependent Overshoot/
Undershoot Tolerance for 533-MHz System Bus .....................................................26
2-17 Wired-OR Signal Group (BINIT#, HIT#, HITM#, BNR#, TND#, BERR#)
Overshoot/Undershoot Tolerance for 533-MHz System Bus......................................27
2-18 VR Connector Signals.........................................................................................27
2-19 Power Connector Pinouts ....................................................................................28
2-20 Processors Core Voltage Identification Code (VCORE and VCACHE)...........................30
2-21 Connection for Unused Pins.................................................................................33
2-22 TUNER1/TUNER3 Translation Table.......................................................................34
3-1
3-2
4-1
4-2
4-3
5-1
6-1
6-2
Pin/Signal Information Sorted by Pin Name ...........................................................36
Pin/Signal Information Sorted by Pin Location........................................................50
Processor Package Dimensions ............................................................................67
Processor Package Mechanical Interface Dimensions...............................................68
Processor Package Load Limits at Power Tab .........................................................71
Case Temperature Specification...........................................................................77
System Management Interface Signal Descriptions.................................................79
Thermal Sensing Device SMBus Addressing on the Dual-Core Intel®
Itanium® Processor 9000 and 9100 series.............................................................81
EEPROM SMBus Addressing on the Dual-Core Intel® Itanium® Processor
6-3
9000 and 9100 Series ........................................................................................82
Processor Information ROM Format ......................................................................82
Current Address Read SMBus Packet ....................................................................85
Random Address Read SMBus Packet ...................................................................86
Byte Write SMBus Packet....................................................................................86
Write Byte SMBus Packet....................................................................................87
Read Byte SMBus Packet ....................................................................................87
6-4
6-5
6-6
6-7
6-8
6-9
6-10 Send Byte SMBus Packet ....................................................................................87
6-11 Receive Byte SMBus Packet.................................................................................87
6-12 ARA SMBus Packet.............................................................................................87
6-13 Command Byte Bit Assignment............................................................................88
6-14 Thermal Sensing Device Status Register ...............................................................89
6-15 Thermal Sensing Device Configuration Register......................................................89
6-16 Thermal Sensing Device Conversion Rate Register..................................................90
®
®
6
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
A-1
A-2
A-3
A-5
A-4
A-6
A-7
A-8
A-9
Address Space Size ........................................................................................... 92
Effective Memory Type Signal Encoding................................................................ 92
Special Transaction Encoding on Byte Enables....................................................... 93
BR0# (I/O), BR1#, BR2#, BR3# Signals for 2P Rotating Interconnect ...................... 95
BR0# (I/O), BR1#, BR2#, BR3# Signals for 4P Rotating Interconnect ...................... 95
BR[3:0]# Signals and Agent IDs ......................................................................... 95
DID[9:0]# Encoding.......................................................................................... 97
Extended Function Signals.................................................................................. 98
Length of Data Transfers.................................................................................. 100
A-10 Transaction Types Defined by REQa#/REQb# Signals........................................... 102
A-11 STBp[7:0]# and STBn[7:0]# Associations.......................................................... 104
A-12 Output Signals................................................................................................ 105
A-13 Input Signals.................................................................................................. 105
A-14 Input/Output Signals (Single Driver).................................................................. 106
A-15 Input/Output Signals (Multiple Driver)................................................................ 107
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
7
Revision History
Document
Number
Revision
Number
Description
Date
•
•
Updated with 9100 series product information; updated brand name from
“Itanium 2” to “Itanium”.
314054
314054
-002
-001
October 2007
July 2006
Initial release of the document.
®
®
8
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
®
®
Dual-Core Intel Itanium Processor 9000 and
9100 Series
Dual-Core Intel® Itanium® Processor 1.6 GHz with 24 MB L3 Cache 9050
Dual-Core Intel® Itanium® Processor 1.6 GHz with 18 MB L3 Cache 9040
Dual-Core Intel® Itanium® Processor 1.6 GHz with 8 MB L3 Cache 9030
Dual-Core Intel® Itanium® Processor 1.42 GHz with 12 MB L3 Cache 9020
Dual-Core Intel® Itanium® Processor 1.4 GHz with 12 MB L3 Cache 9015
Intel® Itanium® Processor 1.6 GHz with 6 MB L3 Cache 9010
Dual-Core Intel® Itanium® Processor 1.66 GHz with 24 MB L3 Cache 9150M
Dual-Core Intel® Itanium® Processor 1.6 GHz with 24 MB L3 Cache 9150N
Dual-Core Intel® Itanium® Processor 1.66 GHz with 18 MB L3 Cache 9140M
Dual-Core Intel® Itanium® Processor 1.6 GHz with 18 MB L3 Cache 9140N
Dual-Core Intel® Itanium® Processor 1.42 GHz with 12 MB L3 Cache 9120N
Dual-Core Intel® Itanium® Processor 1.66 GHz with 8 MB L3 Cache 9130M
Intel® Itanium® Processor 1.6 GHz with 12 MB L3 Cache 9110N
Product Features
Dual Core
Intel® Virtualization Technology for virtualization for
data-intensive applications.
— Two complete 64-bit processing cores on one
processor.
— Reduces virtualization complexity.
— Improves virtualization performance.
— Increases operating system compatibility.
EPIC (Explicitly Parallel Instruction Computing)
Technology for current and future requirements of
high-end enterprise and technical workloads
— Provide a variety of advanced
Intel® Cache Safe Technology ensures mainframe-
caliber availability.
implementations of parallelism, predication,
and speculation, resulting in superior
Instruction-Level Parallelism (ILP).
— Minimize L3 cache errors.
Outstanding Energy Efficiency.
— 20 percent less power than previous Intel
Itanium processor.
Hyper-Threading Technology
— Two times the number of OS threads per core
provided by earlier single-thread
implementations.
— 2.5 times higher performance per watt.
High-bandwidth system bus for multiprocessor
scalability:
Wide, parallel hardware based on Intel® Itanium®
— Up to 8.53GB/s bandwidth.
— 128-bit wide data bus.
architecture for high performance:
— Integrated on-die L3 cache of up to 24MB;
cache hints for L1, L2, and L3 caches for
reduced memory latency.
— 50-bits of physical memory addressing and
64-bits of virtual addressing.
— Up to four physical processors on the same
system bus at 400-MHz or 533-MHz data bus
frequency.
— 128 general and 128 floating-point registers
supporting register rotation.
— Register stack engine for effective
management of processor resources.
— Support for predication and speculation.
— Expandable to systems with multiple system
buses.
Features to support flexible platform environments:
— IA-32 Execution Layer supports IA-32
application binaries.
Extensive RAS features for business-critical
applications:
— Full SMBus compatibility.
— Bi-endian support.
— Enhanced machine check architecture with
extensive ECC and parity protection.
— Enhanced thermal management.
— Built-in processor information ROM (PIROM).
— Built-in programmable EEPROM.
— Socket Level Lockstep
— Processor abstraction layer eliminates
processor dependencies.
667-MHz, 1.66-GHz, 3-load busa
— This feature enables increased bandwidth for
Enterprise and HPC.
Demand Based Switching (DBS)a
— Provides additional power management
capability.
— Core Level Lockstep
a. This feature is applicable to only the 9100 series processors
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
9
The Dual-Core Intel® Itanium® processor 9000 and 9100 series delivers new levels of flexibility,
reliability, performance, and cost-effective scalability for your most data-intensive business and
technical applications. With double the performance of previous Intel Itanium processors, the Dual-
Core Intel Itanium processor 9000 and 9100 series provides more reasons than ever to migrate your
business-critical applications off RISC and mainframe systems and onto cost-effective Intel
architecture servers. The Dual-Core Intel Itanium processor 9000 and 9100 series provides close to
triple the amount of L3 cache (24 megabytes), Hyper-Threading Technology for increased
performance, Intel® Virtualization Technology for improved virtualization, Intel® Cache Safe
Technology for increased availability, and 20 percent lower power consumption.
Dual-Core Itanium®-based systems are available from leading OEMs worldwide and run popular 64-
bit operating systems such as Microsoft* Windows Server* 2003; Linux* from SuSE, Red Hat, Red
Flag, and other distributions; HP NonStop*; OpenVMS*; and HP-UX*. More than 7,000 applications
are available for Itanium-based systems, from vendors such as Microsoft, BEA, IBM, Ansys, Gaussian,
Symantec/VERITAS, Oracle, SAP, and SAS. And with industry support growing and future Intel
Itanium processor family advances already in development, your Itanium-based server investment
will continue to deliver performance advances and savings for your most demanding applications.
§
®
®
10
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Introduction
1 Introduction
1.1
Overview
The Dual-Core Intel Itanium processor 9000 and 9100 series employs Explicitly Parallel
Instruction Computing (EPIC) design concepts for a tighter coupling between hardware
and software. In this design style, the interface between hardware and software is
engineered to enable the software to exploit all available compile-time information and
efficiently deliver this information to the hardware. It addresses several fundamental
performance bottlenecks in modern computers, such as memory latency, memory
address disambiguation, and control flow dependencies. The EPIC constructs provide
powerful architectural semantics and enable the software to make global optimizations
across a large scheduling scope, thereby exposing available Instruction Level
Parallelism (ILP) to the hardware. The hardware takes advantage of this enhanced ILP,
and provides abundant execution resources. Additionally, it focuses on dynamic run-
time optimizations to enable the compiled code schedule to flow at high throughput.
This strategy increases the synergy between hardware and software, and leads to
greater overall performance.
The Dual-Core Intel Itanium processor 9000 and 9100 series provides a 6-wide and 8-
stage deep pipeline, running at up to 1.6 GHz. This provides a combination of abundant
resources to exploit ILP as well as increased frequency for minimizing the latency of
each instruction. The resources consist of six integer units, six multimedia units, two
load and two store units, three branch units, two extended-precision floating-point
units, and one additional single-precision floating-point unit per core. The hardware
employs dynamic prefetch, branch prediction, a register scoreboard, and non-blocking
caches to optimize for compile-time non-determinism. Three levels of on-die cache
minimize overall memory latency. This includes up to a 24 MB L3 cache, accessed at
core speed, providing up to 8.53 GB/sec. of data bandwidth. The system bus is
designed to support up to four physical processors (on a single system bus), and can
be used as an effective building block for very large systems. The balanced core and
memory subsystem provide high performance for a wide range of applications ranging
from commercial workloads to high-performance technical computing.
The Dual-Core Intel Itanium processor 9000 and 9100 series supports a range of
computing needs and configurations from a two-way to large SMP servers. This
document provides the electrical, mechanical and thermal specifications for the Dual-
Core Intel Itanium processor 9000 and 9100 series for use while employing systems
with the processors.
1.2
Processor Abstraction Layer
The Dual-Core Intel Itanium processor 9000 and 9100 series requires implementation-
specific Processor Abstraction Layer (PAL) firmware. PAL firmware supports processor
initialization, error recovery, and other functionality. It provides a consistent interface
to system firmware and operating systems across processor hardware
implementations. The Intel® Itanium® Architecture Software Developer’s Manual,
Volume 2: System Architecture, describes PAL. Platforms must provide access to the
firmware address space and PAL at reset to allow the processors to initialize.
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
11
Introduction
The System Abstraction Layer (SAL) firmware contains platform-specific firmware to
initialize the platform, boot to an operating system, and provide runtime functionality.
Further information about SAL is available in the Intel® Itanium® Processor Family
System Abstraction Layer Specification.
1.3
Mixing Processors of Different Frequencies and
Cache Sizes
All Dual-Core Intel Itanium processor 9000 and 9100 series on the same system bus
are required to have the same cache size (24 MB, 18 MB, 12 MB, 8 MB or 6 MB) and
identical core frequency. Mixing components of different core frequencies and cache
sizes is not supported and has not been validated by Intel. Operating system support
for multiprocessing with mixed components should also be considered.
While Intel has done nothing to specifically prevent processors within a multiprocessor
environment from operating at differing frequencies and differing cache sizes, there
may be uncharacterized errata that exist in such configurations. Customers would be
fully responsible for validation of system configurations with mixed components other
than the supported configurations described above.
1.4
Terminology
In this document, “the processor” refers to the “Dual-Core Intel Itanium processor
9000 and 9100 series” processor, unless otherwise indicated.
A ‘#’ symbol after a signal name refers to an active low signal. This means that a signal
is in the active state (based on the name of the signal) when driven to a low level. For
example, when RESET# is low, a processor reset has been requested. When NMI is
high, a non-maskable interrupt has occurred. In the case of lines where the name does
not imply an active state but describes part of a binary sequence (such as address or
data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’
refers to a hex ‘A’, and D [3:0] # = ‘LHLH’ also refers to a hex ‘A’ (H = High logic level,
L = Low logic level).
The term “system bus” refers to the interface between the processor, system core logic,
and other bus agents. The system bus is a multiprocessing interface to processors,
memory, and I/O.
A signal name has all capitalized letters, for example, VCTERM.
A symbol referring to a voltage level, current level, or a time value carries a plain
subscript, for example, Vcore, or a capitalized, abbreviated subscript, for example, TCO
.
1.5
State of Data
The data contained in this document is subject to change. It is the best information
that Intel is able to provide at the publication date of this document.
®
®
12
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Introduction
1.6
Reference Documents
The reader of this specification should also be familiar with material and concepts
presented in the following documents:
®
®
Intel Itanium 2 Processor Specification Update
®
®
Intel Itanium Architecture Software Developer’s Manual, Volume 1:
Application Architecture
®
®
Intel Itanium Architecture Software Developer’s Manual, Volume 2: System
Architecture
®
®
Intel Itanium Architecture Software Developer’s Manual,
Volume 3: Instruction Set Reference
®
®
Intel Itanium 2 Processor Reference Manual for Software Development and
Optimization
®
®
Intel Itanium Processor Family System Abstraction Layer Specification
ITP700 Debug Port Design Guide
System Management Bus Specification
Note:
Contact your Intel representative or check http://developer.intel.com for the latest
revision of the reference documents.
§
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
13
Introduction
®
®
14
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Electrical Specifications
2 Electrical Specifications
This chapter describes the electrical specifications of the Dual-Core Intel Itanium
Processor 9000 and 9100 series.
2.1
Dual-Core Intel® Itanium® Processor 9000 and
9100 Series System Bus
Most Dual-Core Intel Itanium processor 9000 and 9100 series signals use the Itanium
processor’s assisted gunning transceiver logic (AGTL+) signaling technology. The
termination voltage, VCTERM, is generated on the baseboard and is the system bus high
reference voltage. The buffers that drive most of the system bus signals on the
processor are actively driven to VCTERM during a low-to-high transition to improve rise
times and reduce noise. These signals should still be considered open-drain and require
termination to VCTERM which provides the high level. The processor system bus is
terminated to VCTERM at each end of the bus. There is also support of off-die
termination, in which case, the termination is provided by external resistors connected
to VCTERM
.
AGTL+ inputs use differential receivers which require a reference signal (VREF). VREF is
used by the receivers to determine if a signal is a logical 0 or a logical 1. The processor
generates VREF on-die, thereby eliminating the need for an off-chip reference voltage
source.
2.1.1
2.1.2
System Bus Power Pins
VCTERM (1.2 V) input pins on the processor provide power to the driver buffers and on-
die termination. The GND pins, in addition to the GND input at the power tab connector,
provide ground to the processor. Power for the processor core is supplied through the
power tab connector by VCore, VCache, Vfixed. The 3.3 V pin is included on the processor
to provide power to the system management bus (SMBus). The VCTERM, 3.3 V, and GND
pins must remain electrically separated from each other.
System Bus No Connect
All pins designated as “N/C” or “No Connect” must remain unconnected.
2.2
System Bus Signals
2.2.1
Signal Groups
Table 2-1 shows processor system bus signals that have been combined into groups by
buffer type and whether they are inputs, outputs, or bidirectional, with respect to the
processor.
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
15
Electrical Specifications
..
Table 2-1.
Itanium® Processor System Bus Signal Groups
Group Name
Signals
1
AGTL+ Input Signals
AGTL+ I/O Signals
BPRI#, BR[3:1]#, DEFER#, GSEQ#, ID[9:0]#, IDS#, RESET# , RS[2:0]#,
RSP#, TRDY#
1
A[49:3]#, ADS#, AP[1:0]#, BERR#, BINIT#, BNR#, BPM[5:0]# , BR0#,
D[127:0]#, DBSY#, DEP[15:0]#, DRDY#, HIT#, HITM#, LOCK#,
REQ[5:0]#, RP#, SBSY#, STBN[7:0]#, STBP[7:0]#, TND#
AGTL+ Output Signals
FERR#, THRMTRIP#, DBSY[1:0]#, DRDY[1:0]#, SBSY[1:0]#
A20M#, IGNNE#, INIT#, LINT[1,0], PMI#
Special AGTL+ Asynchronous
Interrupt Input Signals
1
Power Good Signal
PWRGOOD
HSTL Clock Signals
BCLKn, BCLKp
1
TAP Input Signals
TCK, TDI, TMS, TRST#
1
TAP Output Signals
TDO
1
System Management Signals
Power Signals
3.3 V, SMA[2:0], SMSC, SMSD, SMWP, THRMALERT#
GND, VCTERM
1
LVTTL Power Pod Signals
CPUPRES#, OUTEN, PPODGD#
Other
TERMA, TERMB, TUNER1, TUNER2, TUNER3, VCCMON, VSSMON
Notes:
®
®
1. Signals will not be terminated on-die even when on-die termination (ODT) is enabled. See the Intel Itanium
2 Processor Hardware Developer’s Manual for further details.
All system bus outputs should be treated as open drain signals and require a high-level
source provided by the VCTERM supply.
AGTL+ inputs have differential input buffers which use VREF as a reference level. AGTL+
output signals require termination to VCTERM. In this document, “AGTL+ Input Signals”
refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving.
Similarly, “AGTL+ Output Signals” refers to the AGTL+ output group as well as the
AGTL+ I/O group when driving.
The Test Access Port (TAP) connection input signals use a non-differential receiver with
levels that are similar to AGTL+. No reference voltage is required for these signals. The
TAP Connection Output signals are AGTL+ output signals.
The processor system bus requires termination on both ends of the bus. The processor
system bus supports both on-die and off-die termination controlled by two pins, TERMA
and TERMB. Please see the TERMA and TERMB pin description in Section 2.2.2.
The HSTL clock signals are the differential clock inputs for the processor. The SMBus
signals and LVTTL power pod signals are driven using the 3.3 V CMOS logic levels listed
in Table 2-8 and Table 2-9, respectively.
®
®
16
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Electrical Specifications
2.2.2
Signal Descriptions
Appendix A, “Signals Reference”, contains functional descriptions of all system bus
signals and LVTTL power pod signals. Further descriptions of the system management
signals are contained in Chapter 6. The signals listed under the “Power” and “Other”
group are described here:
VCTERM
System bus termination voltage.
System ground.
GND
N/C
No connection can be made to these pins.
TERMA, TERMB
The processor uses two pins to control the on-die termination
function: TERMA and TERMB. Both of these termination pins
must be pulled to VCTERM in order to terminate the system bus
using the on-die termination resistors. Both of these termination
pins must be pulled to GND in order to use off-die termination.
TUNER1, TUNER2,
TUNER3
The TUNER1 Pin can either be left as a no-connect or left
connected to VCTERM via resistor for the majority of platforms
supporting the Dual-Core Intel Itanium processor 9000 and
9100 series. The TUNER2 resistor is used to control the
termination resistance for the system bus I/O buffers. A lower
resistance will cause a lower on-die termination resistance. On-
die termination mode will only be selected if the TERMA and
TERMB pins are terminated as indicated above. The TUNER3 pin
will not be required for the majority of platforms supporting the
Dual-Core Intel Itanium processor 9000 and 9100 series. The
TUNER3 pin is used only in the case where A[21:17]# are driven
to all zeros or all ones during the configuration cycles at reset.
When all zeros or all ones are observed by the processor the
presence of the TUNER3 and TUNER1 pins is used to determine
system bus frequency. See Table 2-22 for the various TUNER pin
combinations and resulting system bus frequency and slew rate
combination.
VCCMON, VSSMON
These pins allows remote measurement of on-die Vcore voltage.
No connections that constitute a current load can be made to
these pins.
Table 2-2.
Nominal Resistance Values for Tuner1, Tuner2, and Tuner3
400 MHz
5-Load Platform (Ohms)
400 MHz
3-Load Platform (Ohms)
533 MHz
3-Load Platform (Ohms)
1
1
1
Tuner1: NC
Tuner1: NC
Tuner1: NC
Tuner2: 150
Tuner2: 150
Tuner2: 150
1
1
1
Tuner3: NC
Tuner3: NC
Tuner3: NC
Notes:
1. Depending on system configuration, the processor may or may not require a resistor on the
TUNER pin. OEMs may leave the pin unconnected or connect it to VCTERM through a 150
or 100 ohm resistor. If A[21:17]:# are driven to all 0’s or all 1’s at reset, see Table 2-22
for proper use of the TUNER Pins.
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
17
Electrical Specifications
2.3
Package Specifications
Table 2-3 through Table 2-9 list the DC voltage, current, and power specifications for
the processor. The voltage and current specifications are defined at the processor pins.
Operational specifications listed in Table 2-3 through Table 2-9 are only valid while
meeting specifications for case temperature, clock frequency, and input voltages.
Table 2-3.
Processor Package Specifications
Core
Frequency
Symbol
Parameter
Minimum
Typ
Maximum
Unit Notes
1
V
V
from the Voltage
CC
All
VID-17 mV
VID
VID+17 mV
V
core, PS
cache, PS
fixed, PS
Regulator
2
V
V
V
from the Voltage
All
All
VID-17 mV
1.25-20 mV
VID
VID+17 mV
V
cache
Regulator
V
from the Voltage
1.25 1.25+20 mV
V
V
fixed
Regulator
V
R
Termination Voltage
All
All
1.2-1.5%
45-15%
1.2
45
1.2+1.5%
45+15%
CTERM
3
Recommended Termination
Resistance
Ohm
TERM
V
Test Access Port Voltage
All
All
All
All
1.2-1.5%
2.8
1.2
89
1.5
121
18
V
A
A
A
TAP
(VCC
)
TAP
I
I
I
I
Core Current Required from
Power Supply
core,PS
cache,PS
fixed,PS
CTERM
Cache Current Required from
Power Supply
2.0
17
Fixed Current Required from
Power Supply
0.7
9.2
11
4
Termination Voltage Current
All
All
7.2
A
PS
Power Supply Slew Rate for
the Termination Voltage at the
Processor Pins
0.05
A/ns
TT
5
PWR
PWR
PWR
Max Power
All
All
All
177
130
104
W
max
TPE
TDP
Thermal Power Envelope
W
6
Thermal Design Power – dual
core
W
Thermal Design Power –
single core
1.6 GHz
75
W
Notes:
1. The range for Vcore is 1.0875 V to 1.25 V.
2. Vcache typical is 1.025 V.
3. The processor system bus is terminated at each end of the system bus. The processor supports both on-die
and off-die termination which is selected by the TERMA and TERMB pins. Termination tolerance is ±15% for
on-die termination measured at V and ±1% for off-die termination.
OL
4. This is measured for On-Die Termination with a 45-ohm pull up resistor.
5. Max power is peak electrical power that must be provided for brief periods by the VR.
6. Represents the TDP level that should be used for system thermal design. Sustained power for all real-world
applications will remain at or below this power level.
2.4
Signal Specifications
This section describes the DC specifications of the system bus signals. The processor
signal’s DC specifications are defined at the processor pins. Table 2-4 through Table 2-9
describe the DC specifications for the AGTL+, PWRGOOD, HSTL clock, TAP port, system
management, and LVTTL signals. Please refer to the ITP700 Debug Port Design Guide
for the TAP connection signals’ DC specifications at the debug port.
®
®
18
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Electrical Specifications
Table 2-4.
AGTL+ Signals DC Specifications
Core
Frequency
Symbol
Parameter
Minimum
Typ
Maximum
Unit Notes
1
V
V
V
V
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
All
All
All
All
0.625
V
IL
1
0.875
V
IH
OL
OH
2
0.3
0.4
V
V
,
V
V ,
CTERM
maximum
V
CTERM
CTERM
minimum
3
I
I
I
Output Low Current @ 0.3 V
Output Low Current @ 0.3 V
Leakage Current
All
All
All
All
34
17
mA
OL
OL
L
4
mA
5
±100
2
µA
6
C
AGTL+ Pad Capacitance
pF
AGTL+
Notes:
1. The typical transition point between V and V assuming 125 mV V
uncertainty for ODT. V and
REF_high
IL
IH
REF
V
levels are V
REF_low
±100 mV, respectively, for a system bus agent using on-board termination. V
REF_low
REF REF_high
and V
levels are V
±125 mV, respectively, for a system bus agent using on-die termination.
REF
2. Parameter measured into a 22.5 ohm resistor to 1.2 V. Minimum V and I are guaranteed by design/
OL
OL
characterization.
3. Calculated using off-die termination through two 45 ohm ±1% resistors in parallel.
4. Calculated using on-die termination to a 45 ±15% resistor measured at V
.
OL
5. At 1.2 V ±1.5%. V
, minimum ≤Vpin ≤V
, maximum.
CTERM
CTERM
6. Total of I/O buffer with ESD structure and processor parasitics if applicable. Capacitance values guaranteed
by design for all AGTL+ buffers.
Table 2-5.
Table 2-6.
Power Good Signal DC Specifications
Symbol
Parameter
Input Low Voltage
Input High Voltage
Minimum
Maximum
Unit
Notes
V
0.440
V
V
IL
V
0.875
IH
System Bus Clock Differential HSTL DC Specifications
Symbol
Parameter
Input High Voltage
Minimum
Maximum
Unit
Notes
V
0.78
–0.3
0.55
1.3
0.5
V
V
IH
IL
V
V
C
Input Low Voltage
Input Crossover Voltage
Input (Pad) Capacitance
0.85
1.75
V
X
pF
CLK
Table 2-7.
TAP Connection DC Specifications
Symbol
Parameter
Input Low Voltage
Minimum
Maximum
Unit
Notes
1
V
–0.3
1.1
0.5
1.57
0.3
V
V
IL
IH
1, 2
V
V
V
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Current
Input Current
V
OL
OH
OL
IC
2, 3
4
1.2
20
V
I
I
mA
uA
690
Notes:
1. There is a 100 mV hysteresis on TCK.
2. VIH, MAX = 1.5 V + 5%, VOH, MAX = 1.2 V +5%.
3. There is no internal pull-up. An external pull-up is always assumed. Max voltage tolerated at TDO is 1.5 V.
4. Per input pin.
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
19
Electrical Specifications
Table 2-8.
SMBus DC Specifications
Symbol
Parameter
Minimum
Typ
Maximum
Unit
Notes
3.3V
V
for the System Management
3.14
3.3
3.47
V
3.3 V ±5
CC
Components
V
V
Input Low Voltage
Input High Voltage
–0.3
2.31
0.3*3.3 V
3.47
V
V
IL
Max =
3.3 +5%
Min +
IH
0.7*3.3V
V
Output Low Voltage
3.3V Supply Current
Output Low Current
Output Low Current
Input Leakage Current
Output Leakage Current
0.4
30.0
3
V
OL
3.3V
OL
I
I
I
I
I
5.0
mA
mA
mA
µA
1
2
6
OL2
LI
10
10
µA
LO
Notes:
1. The value specified for I applies to all signals except for THRMALERT#.
OL
OL2
2. The value specified for I
applies only to THRMALERT#, which is an open drain signal.
Table 2-9.
LVTTL Signal DC Specifications
Symbol
Parameter
Input Low Voltage
Minimum
Maximum
Unit
Notes
V
0.8
3.63
0.4
V
V
V
V
IL
V
V
V
Input High Voltage
Output Low Voltage
Output High Voltage
2.0
2.4
IH
OL
OH
Table 2-10 through Table 2-11 list the AC specifications for the processor’s clock and
SMBus (timing diagrams begin with Figure 2-1). The processor uses a differential HSTL
clocking scheme with a frequency of 200, 266, or 333 MHz. The SMBus is a subset of
the I2C* interface which supports operation of up to 100 kHz.
Table 2-10.System Bus Clock Differential HSTL AC Specifications (Sheet 1 of 2)
System
Bus
Clock
(MHz)
Symbol
Parameter
Minimum
Typ
Maximum
Unit
Figure
Notes
T
BCLKp Period
200
200
200
200
200
200
266
266
266
266
266
266
5.0
ns
ps
Figure 2-1
period
1
2
3
4
4
T
System Clock Skew
BCLKp Frequency
BCLKp Input Jitter
BCLKp High Time
BCLKp Low Time
BCLKp Period
100
skew
BCLK
f
200
200
100
MHz
ps
Figure 2-1
Figure 2-1
Figure 2-1
Figure 2-1
Figure 2-1
T
T
T
T
jitter
high
low
2.25
2.25
2.5
2.5
2.75
2.75
ns
ns
3.75
ns
period
5
2
3
4
4
T
System Clock Skew
BCLKp Frequency
BCLKp Input Jitter
BCLKp High Time
BCLKp Low Time
60
266
50
ps
skew
BCLK
f
266
MHz
ps
Figure 2-1
Figure 2-1
Figure 2-1
Figure 2-1
T
T
T
jitter
high
low
1.69
1.69
1.88
1.88
2.06
2.06
ns
ns
®
®
20
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Electrical Specifications
Table 2-10.System Bus Clock Differential HSTL AC Specifications (Sheet 2 of 2)
System
Bus
Clock
(MHz)
Symbol
Parameter
Minimum
Typ
Maximum
Unit
Figure
Notes
7
T
BCLKp Rise Time
All
All
All
333
333
500
500
600
667
667
ps
ps
Figure 2-1
Figure 2-1
Figure 2-1
20–80%
rise
7
T
BCLKp Fall Time
Minimum Input Swing
20–80%
6
fall
V
mV
PP
Notes:
1. The system clock skew is ±100 ps.
2. Measured on cross-point of rising edge of BCLKp and falling edge of BCLKn. Long-term jitter is defined as peak-to-peak variation
measured by accumulating a large number of clock cycles and recording peak-to-peak jitter.
3. Cycle-to-cycle jitter is defined as peak-to-peak variation measured over 10,000 cycles peak-to-peak jitter.
4. Measured on cross point of rising edge of BCLKp and falling edge of BCLKn.
5. The system clock skew is ±60 ps.
6.
V
is defined as the minimum input differential voltage which will cause no increase in the clock receiver timing.
PPmin
7. The measurement is taken at 40-60% of the signal and extrapolated to 20-80%.
Table 2-11. SMBus AC Specifications
Symbol
Parameter
SMSC Clock Frequency
Minimum
Maximum
Unit
Notes
f
100
kHz
µs
µs
µs
µs
µs
µs
ns
ns
µs
SMSC
T
SMSC Clock Period
10
4.0
4.7
SMSC
1
1
1
1
t
t
t
t
t
t
t
t
SMSC Clock High Time
SMSC Clock Low Time
SMSC Clock Rise Time
SMSC Clock Fall Time
SMBus Output Valid Delay
SMBus Input Setup Time
SMBus Input Hold Time
Bus Free Time
high
low
1.0
0.3
1.0
rise
fall
VALID
SU
250
0
HLD
FREE
2
4.7
Notes:
1. Please refer to Figure 2-2 for the Standard Microsystems Corporation (SMSC)* clock waveform.
2. Bus Free Time is the minimum time allowed between request cycles.
Figure 2-1. Generic Clock Waveform
T
high
T
low
T
jitter
T
T
fall
rise
BCLKN
BCLKP
80%
20%
V
pp
T
period
T
T
= Period
= Rise Time
= Fall Time
= High Time
= Low Time
period
rise
T
fall
T
jitter
= Long Term Peak-to-Peak Jitter
= Peak-to-Peak Swing
V
pp
T
high
T
low
000615
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
21
Electrical Specifications
Figure 2-2. SMSC Clock Waveform
T
high
T
rise
V
cc
(3.3V)
90% V
cc
75% V
cc
SMSC
25% V
cc
T
fall
T
low
T
T
T
T
= Rise Time
= Fall Time
= High Time
rise
high
= Low Time
fall
low
000618
2.4.1
Maximum Ratings
Table 2-12 contains the processor stress ratings. Functional operation at the absolute
maximum and minimum is neither implied nor guaranteed. The processor should not
receive a clock while subjected to these conditions. Functional operating conditions are
given in the DC tables. Extended exposure to the maximum ratings may affect device
reliability. Furthermore, although the processor contains protective circuitry to resist
damage from static electric discharge, one should always take precautions to avoid
static voltages or electric fields.
Table 2-12. Dual-Core Intel® Itanium® Processor Absolute Maximum Ratings
Symbol
Parameter
Minimum
Maximum
Unit
Notes
1
2
T
Processor Storage Temperature
Processor Shipping Temperature
–10
–45
-0.3
-0.3
-0.3
–0.3
45
75
°C
°C
V
storage
T
shipping
V
V
V
Any V
Any V
Any V
Voltage with Respect to GND
1.55
1.55
1.55
5.5
core
core
Voltage with Respect to GND
Voltage with Respect to GND
V
cache
fixed
cache
fixed
V
3
3
3.3V
Any 3.3 V Supply Voltage with Respect to
GND
V
V
V
SMBus Buffer DC Input Voltage with
Respect to GND
–0.1
6.0
V
V
in, SMBus
in, AGTL+
4,
5
AGTL+ Buffer DC Input Voltage with
Respect to GND
–0.45
1.65
V
V
Any V
Voltage with Respect to GND
CTERM
-0.45
-0.45
1.65
1.65
V
V
CTERM
in,TAP
4
TAP Buffer DC Input Voltage with Respect
to GND.
Notes:
1. Storage temperature is temperature in which the processor can be stored for up to one year.
2. Shipping temperature is temperature in which the processor can be shipped for up to 24 hours.
3. Parameters are from third-party vendor specifications.
4. Maximum instantaneous voltage at receiver buffer input.
5. Specification includes V
respect to GND.
and V
(AGTL+ asynchronous buffer DC input voltage with
in,AGTL+
in,AGTL+ ASYNCHRONOUS
®
®
22
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Electrical Specifications
2.5
System Bus Signal Quality Specifications and
Measurement Guidelines
Overshoot (or undershoot) is the absolute value of the maximum voltage above the
nominal VCTERM voltage (or below GND), as shown in Table 2-3. The overshoot/
undershoot specifications limit transitions beyond VCTERM or GND due to the fast signal
edge rates. The processor can be permanently damaged by repeated overshoot or
undershoot events on any input, output, or I/O buffer if the charge is large enough
(that is, if the overshoot/undershoot is great enough). Determining the impact of an
overshoot/undershoot condition requires knowledge of the magnitude, the pulse
duration, and the activity factor (AF).
2.5.1
Overshoot/Undershoot Magnitude
Magnitude describes the maximum potential difference between a signal and its voltage
reference level. For the processor, both are referenced to GND, as shown in Figure 2-3.
It is important to note that overshoot and undershoot conditions are separate and their
impact must be determined independently. Overshoot/undershoot magnitude levels
must observe the absolute maximum specifications listed in Table 2-13 through
Table 2-17. These specifications must not be violated at any time, regardless of bus
activity or system state. Within these specifications are threshold levels that define
different allowed pulse duration. Provided that the magnitude of the overshoot/
undershoot is within the absolute maximum specifications, the pulse magnitude,
duration, and activity factors must all be used to determine if the overshoot/
undershoot pulse is within specifications.
Figure 2-3. System Bus Signal Waveform Exhibiting Overshoot/Undershoot
Maximum
Absolute
Overshoot
Time-dependent
Overshoot
VMAX
VCTERM
VREF
VOL
GND
VMIN
Time-dependent
Undershoot
Maximum
Absolute
Undershoot
000588
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
23
Electrical Specifications
2.5.2
Overshoot/Undershoot Pulse Duration
Pulse duration describes the total time that an overshoot/undershoot event exceeds the
overshoot/undershoot reference voltage (VCTERM/GND). The total time could
encompass several oscillations above the reference voltage. Multiple overshoot/
undershoot pulses within a single overshoot/undershoot event may need to be
measured to determine the total pulse duration.
Note:
Oscillations below the reference voltage cannot be subtracted from the total overshoot/
undershoot pulse duration.
2.5.3
Activity Factor
Activity factor (AF) describes the frequency of overshoot (or undershoot) occurrence
relative to a clock. Since the highest frequency of assertion of any common clock signal
is every other clock, an AF = 1 indicates that the specific overshoot (or undershoot)
waveform occurs every other clock cycle. Thus, an AF = 0.01 indicates that the specific
overshoot (or undershoot) waveform occurs one time in every 200 clock cycles. For
source synchronous signals (data, and associated strobes), the activity factor is in
reference to the strobe edge. The highest frequency of assertion of any source
synchronous signal is every active edge of its associated strobe. So, an AF = 1
indicates that the specific overshoot (or undershoot) waveform occurs every other
strobe cycle. The specifications provided in Table 2-14 through Table 2-17 show the
maximum pulse duration allowed for a given overshoot/undershoot magnitude at a
specific activity factor. Each table entry is independent of all others, meaning that the
pulse duration reflects the existence of overshoot/undershoot events of that magnitude
ONLY. A platform with an overshoot/undershoot that just meets the pulse duration for a
specific magnitude where the AF <1, means that there can be no other overshoot/
undershoot events, even of lesser magnitude (if AF = 1, then the event occurs at all
times and no other events can occur).
Note:
AF for the common clock AGTL+ signals is referenced to BCLKn, and BCLKp frequency.
The wired-OR Signals (BINIT#, HIT#, HITM#, BNR#, TND#, BERR#) are common
clock AGTL+ signals.
Note:
AF for source synchronous (2x) signals is referenced to STBP#[7:0], and STBN#[7:0].
2.5.4
Reading Overshoot/Undershoot Specification Tables
The overshoot/undershoot specification for the processor is not a simple single value.
Instead, many factors are needed in order to correctly interpret the overshoot/
undershoot specification. In addition to the magnitude of the overshoot, the following
parameters must also be known: the width of the overshoot and the AF. To determine
the allowed overshoot for a particular overshoot event, the following must be done:
1. Determine the signal group that the particular signal falls into. For AGTL+ signals
operating in the 2x source synchronous domain, use Table 2-14 through
Table 2-16. If the signal is a wired-OR AGTL+ signal operating in the common clock
domain, use Table 2-15 through Table 2-17.
2. Determine the magnitude of the overshoot, or the undershoot (relative to GND).
3. Determine the activity factor (how often does this overshoot occur?).
4. Next, from the appropriate specification table, determine the maximum pulse
duration (in nanoseconds) allowed. The pulse duration shown in the table refers to
the period where either the maximum overshoot (for high phase) and undershoot
(for low phase) occurred.
®
®
24
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Electrical Specifications
5. Compare the specified maximum pulse duration to the signal being measured. If
the pulse duration measured is less than the pulse duration shown in the table,
then the signal meets the specifications.
6. Undershoot events must be analyzed separately from overshoot events, as they are
mutually exclusive.
2.5.5
Determining if a System Meets the Overshoot/Undershoot
Specifications
The overshoot/undershoot specifications listed in Table 2-13 through Table 2-17 specify
the allowable overshoot/undershoot for a single overshoot/undershoot event. However,
most systems will have multiple overshoot and/or undershoot events that each has
their own set of parameters (duration, AF and magnitude). While each overshoot on its
own may meet the overshoot specification, the total impact of all overshoot events may
cause the system to fail. A guideline to ensure a system passes the overshoot and
undershoot specifications is shown below:
1. Ensure that no signal ever exceeds VCTERM or GND.
2. If only one overshoot/undershoot event magnitude occurs, ensure that it meets the
specifications listed in Table 2-13 through Table 2-17.
3. If multiple overshoots and/or multiple undershoots occur, measure the worst-case
pulse duration for each magnitude and compare the results against the AF = 1
specifications. If all of these worst-case overshoot or undershoot events meet the
specifications (measured time < specifications) in the table (where AF = 1), then
the system passes.
2.5.6
Wired-OR Signals
To ensure platform compatibility between the processors, system bus signals must
meet certain overshoot and undershoot requirements. The system bus wired-OR
signals (BINIT#, HIT#, HITM#, BNR#, TND#, BERR#) have the same absolute
overshoot and undershoot specification as the Source Synchronous AGTL+ Signals, but
they have different time-dependent overshoot/undershoot requirements.
Table 2-13. Source Synchronous AGTL+ Signal Group and Wired-OR Signal Group Absolute
Overshoot/Undershoot Tolerance
Parameter
Description
Specification
Units
V
V
I/O power supply voltage (nominal).
1.20
1.65
V
V
CTERM
MAX
Maximum absolute voltage for system bus signals at the input
of the receiver buffers.
V
Minimum absolute voltage for system bus signals at the input
of the receiver buffers.
–0.45
V
MIN
1
1
Overshoot
Time dependent overshoot amount above V
CTERM .
Undershoot
Time dependent undershoot amount below GND.
Notes:
1. These parameters cannot be specified in absolute terms.
Notes: The following notes apply to Table 2-14 through Table 2-17:
1.
2.
Absolute Maximum Overshoot magnitude of 1.65 V must never be exceeded.
Absolute Maximum Overshoot is measured referenced to GND. Pulse duration of overshoot is measured
relative to V
.
CTERM
3.
4.
5.
6.
Absolute Maximum Undershoot and Pulse Duration of undershoot is measured relative to GND.
Ringback below V cannot be subtracted from overshoots/undershoots.
Lesser undershoot does not allocate overshoot with longer duration or greater magnitude.
All values specified by design characterization.
CTERM
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
25
Electrical Specifications
Table 2-14. Source Synchronous AGTL+ Signal Group Time-Dependent Overshoot/
Undershoot Tolerance for 400-MHz System Bus
Absolute
Maximum (V)
Pulse Duration (ns)
Over-
shoot
Under-
shoot
1
AF = 1
AF = 0.75
AF = 0.5
AF = 0.25
AF = 0.1
AF = 0.05 AF = 0.01
1.65
1.6
–0.45
–0.4
0.0035
0.0039
0.0124
0.0405
0.1304
0.4136
1.3163
2.5
0.0036
0.0040
0.0168
0.0546
0.1755
0.5581
1.7815
2.5
0.0037
0.0045
0.0255
0.0833
0.2671
0.8524
2.5
0.0040
0.0157
0.0520
0.1682
0.5438
1.7215
2.5
0.0121
0.0396
0.1309
0.4279
1.3629
2.5
0.0241
0.0799
0.2626
0.8546
2.5
0.1207
0.3996
1.3107
2.5
1.55
1.5
–0.35
–0.3
1.45
1.4
–0.25
–0.2
2.5
2.5
2.5
1.35
1.3
–0.15
–0.1
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
1.25
–0.05
2.5
2.5
2.5
2.5
2.5
2.5
2.5
Notes:
1. Activity Factor = 1 means signal toggles every 5 ns.
Table 2-15. Wired-OR Signal Group (BINIT#, HIT#, HITM#, BNR#, TND#, BERR#)
Overshoot/Undershoot Tolerance for 400-MHz System Bus
Absolute
Pulse Duration (ns)
Maximum (V)
Over-
shoot
Under-
shoot
1
AF = 1
AF = 0.75
AF = 0.5
AF = 0.25
AF = 0.1
AF = 0.05 AF = 0.01
1.65
1.6
–0.45
–0.4
0.0166
0.0506
0.1659
0.5413
1.7343
5
0.0192
0.0674
0.2216
0.7218
2.3194
5
0.0306
0.1017
0.3342
1.0840
3.4995
5
0.0614
0.2032
0.6676
2.1814
5
0.1539
0.3067
1.5374
0.5090
1.0213
5
5
5
5
5
5
1.55
1.5
–0.35
–0.3
1.6734
3.3413
5
5
5
5
5
5
5
5
1.45
1.4
–0.25
–0.2
5
1.35
–0.15
5
5
5
5
Notes:
1. Activity Factor = 1 means signal toggles every 10 ns.
Table 2-16. Source Synchronous AGTL+ Signal Group Time-Dependent Overshoot/
Undershoot Tolerance for 533-MHz System Bus (Sheet 1 of 2)
Absolute
Pulse Duration (ns)
Maximum (V)
Over-
shoot
Under-
shoot
1
AF = 1
AF = 0.75
AF = 0.5
AF = 0.25
AF = 0.1
AF = 0.05 AF = 0.01
1.65
1.6
–0.45
–0.4
0.0026
0.0029
0.0093
0.0303
0.3095
0.0027
0.0030
0.0126
0.0409
0.4191
0.0028
0.0034
0.0191
0.0625
0.6366
0.0030
0.0118
0.0387
0.1268
1.2965
0.0091
0.0297
0.0980
0.3178
1.875
0.0181
0.0600
0.1963
0.6406
1.875
0.0902
0.2989
0.9822
1.875
1.55
1.5
–0.35
–0.3
1.45
–0.25
1.875
®
®
26
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Electrical Specifications
Table 2-16. Source Synchronous AGTL+ Signal Group Time-Dependent Overshoot/
Undershoot Tolerance for 533-MHz System Bus (Sheet 2 of 2)
Absolute
Pulse Duration (ns)
Maximum (V)
1.4
1.35
–0.2
–0.15
–0.10
0.9925
1.875
1.875
1.3358
1.875
1.875
1.875
1.875
1.875
1.875
1.875
1.875
1.875
1.875
1.875
1.875
1.875
1.875
1.875
1.875
1.875
1.3
Notes:
1. Activity Factor = 1 means signal toggles every 3.75 ns.
Table 2-17. Wired-OR Signal Group (BINIT#, HIT#, HITM#, BNR#, TND#, BERR#)
Overshoot/Undershoot Tolerance for 533-MHz System Bus
Absolute
Pulse Duration (ns)
Maximum (V)
Over-
shoot
Under-
shoot
1
AF = 1
AF = 0.75
AF = 0.5
AF = 0.25
AF = 0.1
AF = 0.05 AF = 0.01
1.65
1.6
–0.45
–0.4
0.01248
0.0380
0.1250
0.4054
1.3013
3.75
0.0144
0.0507
0.1668
0.5424
1.7396
3.75
0.0230
0.0763
0.2507
0.8163
2.6246
3.75
0.0461
0.1522
0.5004
1.6302
3.75
0.1155
0.3814
1.2537
3.75
0.2301
0.7627
2.5059
3.75
1.1530
3.75
3.75
3.75
3.75
3.75
3.75
1.55
1.5
-0.35
–0.3
1.45
1.4
–0.25
-0.2
3.75
3.75
3.75
3.75
3.75
1.35
–0.15
3.75
3.75
3.75
3.75
3.75
3.75
Notes:
1. Activity Factor = 1 means signal toggles every 7.5 ns.
2.6
Voltage Regulator Connector Signals
The VR module consists of three DC-DC converters, Vcore, Vcache, and Vfixed
.
Table 2-18 lists all of the signals which are part of the processor package VR output
connector.
Table 2-18. VR Connector Signals
Group Name
Signals
Voltage Regulator
Connector
PPODGD#, CPUPRES#, GND, Vid_valid, Vid_Core[5:0],
Vid_cache [5:0], Vcache_sense, Gnd_sense, Vcore_sense,
Vfixed_sense, OUTEN.
Warning:
If the VR cannot supply the voltages requested by the components in the processor
package, then it must disable itself.
Figure 2-4 shows the top view of the processor package power tab. See Table 2-19 for
power tab connector signals.
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
27
Electrical Specifications
Figure 2-4. Processors Power Tab Physical Layout
001356
Table 2-19. Power Connector Pinouts (Sheet 1 of 2)
Power Tab VR Pads
Description
A1 - C1
GND
GND
L1 - N1
A2
PPODGD#
CPUPRES#
Vfixed
B2
D1, K1, C2, D2, E2
H2 - N2
A3
Vfixed
Vid_valid
Vid_core [0]
Vid_core [1]
Vid_core [2]
Vid_core [3]
Vid_core [4]
Vid_core [5]
Vid_cache [0]
Vid_cache [1]
Vid_cache [2]
Vid_cache [3]
Vid_cache [4]
Vid_cache [5]
GND
B3
C3
D3
E3
F3
G3
H3
J3
K3
L3
M3
N3
A4 - N4
A5 - N5
A6 - N6
A7 - N7
A8 - N8
A9 - N9
Vcache
GND
Vcore
GND
Vcore
®
®
28
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Electrical Specifications
Table 2-19. Power Connector Pinouts (Sheet 2 of 2)
Power Tab VR Pads
Description
A10 - N10
A11 - N11
A12 - N12
A13 - N13
A14 - N14
A15 - N15
A16 - N16
A17 - N17
A18 - N18
A19 - N19
A20 - N20
A21 - N21
A22 - N22
A23 - N23
A24 - N24
A25 - N25
A26 - N26
A27 - N27
A28 - N28
A29
GND
Vcore
GND
Vcore
GND
Vcore
GND
Vcore
GND
Vcore
GND
Vcore
GND
Vcore
GND
Vcore
GND
Vcache
GND
Vcache_sense
Gnd_sense
Vcore_sense
Vfixed_sense
GND
B29
C29
D29
K29
L29
Reserved
Reserved
OUTEN
GND
M29
N29
A30 - D30
L30 - N30
GND
The VR shall provide a selectable output voltage controlled via multiple binary weighted
Voltage Identification (VID) inputs. The VID value (high = 1; low = 0) is defined in
Table 2-20. VID pins will be controlled by the processor.
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
29
Electrical Specifications
Table 2-20. Processors Core Voltage Identification Code (VCORE and VCACHE)
Processor Pins (0 = low, 1 = high)
400
200
100
50
25
12.5
(mV)
400
200
100
50
25
12.5
(mV)
VID
5
VID
4
VID
3
VID
2
VID
1
VID
0
Vout
(V)
VID
5
VID
4
VID
3
VID
2
VID
1
VID
0
Vout
(V)
1
1
1
1
1
1
OFF
0
1
1
1
1
1
0.9125
0.9
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1.3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1.2875
1.275
1.2625
1.25
0.8875
0.875
0.8625
0.85
1.2375
1.225
1.2125
1.2
0.8375
0.825
0.8125
0.8
1.1875
1.175
1.1625
1.15
0.7875
0.775
0.7625
0.75
1.1375
1.125
1.1125
1.1
0.7375
0.725
0.7125
0.7
1.0875
1.075
1.0625
1.05
0.6875
0.675
0.6625
0.65
1.0375
1.025
1.0125
1
0.6375
0.625
0.6125
0.6
0.9875
0.975
0.9625
0.95
0.5875
0.575
0.5625
0.55
0.9375
0.925
0.5375
0.525
®
®
30
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Electrical Specifications
2.7
System Bus Clock and Processor Clocking
The BCLKn and BCLKp inputs control the operating frequency of the processor system
bus interface. All processor system bus timing parameters are specified with respect to
the falling edge of BCLKn and rising edge of BCLKp. The address pins A[21:17]# will be
used to specify the system bus frequency during reset. The processor will ensure that
the correct bus/core ratio is elected based on the bus frequency that is specified during
reset.
Cold Reset Sequence:
• The configuration pins (A[21:17]#) must be asserted the entire time RESET# is
asserted.
• RESET# must be asserted before PWRGOOD is asserted.
• The duration from the assertion of PWRGOOD to the deassertion of RESET# must
be 1 millisecond minimum.
• After RESET# is deasserted, all the configuration, including pins A[21:17]#, must
remain valid for 2 BCLKs (minimum) to 3 BCLKs (maximum).
• BCLK is shown as a time reference to the BCLK period. It is not a requirement that
this is BCLKn or BCLKp signal.
• Configuration signals other than A[21:17]# must be asserted 4 BCLKs prior to the
deasserted edge of RESET# and must remain valid for 2 BCLKs (minimum) to 3
BCLKs (maximum) after the deasserted edge of RESET#.
Figure 2-5 outlines the timing relationship between the configuration pins, RESET# and
PWRGOOD for cold reset.
Figure 2-5. System Bus Reset and Configuration Timings for Cold Reset
t-4
t-3
t-2
t-1
t0
t1
t2
t3
BCLK
PWRGOOD
RESET#
T
A
T
C
T
B
T
D
Bus Ratio
(A[21:17]#)
T
T
F
E
Additional
Configuration
Signals
T
= 1.15 ns minimum; (set up time to BCLK for deassertion edge of RESET#)
= 1 ms minimum for cold reset
A
T
B
T
= Bus ratio signals must be asserted no later than RESET#
= 2 BCLKs minimum, 3 BCLKs maximum
= 4 BCLKs minimum
C
T
D
T
E
T
F
= 2 BCLKs minimum, 3 BCLKs maximum
000859b
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
31
Electrical Specifications
Warm Reset Sequence:
• PWRGOOD remains high throughout the entire sequence, as power is already
available and stable to the processor.
• The configuration pins (A[21:17]#) must be asserted the entire time RESET# is
asserted.
• The duration from the assertion of RESET# to the deassertion of RESET# must be 1
millisecond minimum.
• After RESET# is deasserted, the configuration pins must remain valid for two
BCLKs (minimum) to three BCLKs (maximum).
• BCLK is shown as a time reference to the BCLK period. It is not a requirement that
this is BCLKn or BCLKp signal.
• Configuration signals other than A[21:17]# must be asserted four BCLKs prior to
the deasserted edge of RESET# and must remain valid for two BCLKs (minimum) to
three BCLKs (maximum) after the deasserted edge of RESET#.
Figure 2-6 outlines the timing relationship between the configuration pins, RESET# and
PWRGOOD for warm reset.
Figure 2-6. System Bus Reset and Configuration Timings for Warm Reset
t-4
t-3
t-2
t-1
t0
t1
t2
t3
BCLK
PWRGOOD
RESET#
T
A
T
T
T
D
C
B
Bus Ratio
(A[21:17]#)
T
T
E
F
Additional
Configuration
Signals
T
= 1.15 ns minimum; (set up time to BCLK for deassertion edge of RESET#)
= 1 ms minimum for warm reset
A
T
B
T
= Bus ratio signals must be asserted no later than RESET#
= 2 BCLKs minimum, 3 BCLKs maximum
= 4 BCLKs minimum
C
T
D
T
E
T
F
= 2 BCLKs minimum, 3 BCLKs maximum
000777b
®
®
32
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Electrical Specifications
2.8
Recommended Connections for Unused Pins
Pins that are unused in an application environment (as opposed to testing
environment) should be connected to the states listed in Table 2-21. Pins that must be
used in an application are stated as such and do not have a recommended state for
unused connection.
Table 2-21. Connection for Unused Pins
Recommended
Connections
Pins/Pin Groups
Notes
1,
2
AGTL+ pins
H
HSTL Clock Signals
All Power Signals
PWRGOOD
Must be used
Must be used
Must be used
TAP Signals
1, 3
1, 3
1, 3
1, 3
1, 3
TCK
L
L
TRST#
TDI
H
H
H
TDO
TMS
System Management Signals
3.3V
GND
N/C
N/C
N/C
N/C
H
SMA[2:0]
SMSC
SMSD
SMWP
1, 4
THRMALERT#
LVTTL Power Pod Signals
OUTEN
Must be used
Must be used
Must be used
PPODGD#
PROCPRES#
Other Pins
N/C
N/C
N/C
A20M#
IGNNE#
LOCK#
FERR#
TUNER1
TUNER2
TUNER3
Notes:
N/C
N/C
N/C
3,5
1
N/C or H
H
3,5
N/C or H
1. L = GND, H = V
.
CTERM
2. AGTL+ output signals SBSY[0:1]#, DBSY[0:1]#, and DRDY[0,1]# may be left as N/C
if not used on platform.
3. Can be No-Connect or connected to V
via a 100ohm or 150 ohm resistor.
CTERM
4. THRMALERT# should be pulled up to 3.3 V through a resistor.
5. With A[21;17] settings to all 0’ or all 1’s, please refer to Table 2-22 for proper
connection.
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
33
Electrical Specifications
Table 2-22. TUNER1/TUNER3 Translation Table
System
Bus (MHz)
Slew Rate
(V/ns)
1
2
2
A[21:17}#
TUNER1
TUNER3
0
0
0
1
0
0
1
0
1
667
533
400
667
533
400
1.7
1.4
0
0
N/A
0
0.8
1
1.92
1.7
1
1
1
N/A
0.82
Notes:
1. 0 = V
, 1 = GND
CTERM
2. 0 = Resistor not present, 1 = Resistor present
§
®
®
34
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Pinout Specifications
3 Pinout Specifications
This chapter describes the Dual-Core Intel Itanium processor 9000 and 9100 series
signals and pinout.
Note:
The pins labeled “N/C” must remain unconnected. The processor uses a JEDEC
standard pin naming convention.
In this chapter, pin names are the actual names given to each physical pin of the
processor. System bus signal names are the names associated with the functions of
those pins. For those pins associated with multiple functions, their pin names and
system bus signal names are not necessarily identical.
Figure 3-1 shows the processor pin location diagram from the top view.
Figure 3-1. Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Pinout
AH AG AF AE AD AC AB AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
2
1
GND
GND
GND
GND
GND
GND
GND VC GND
TERM
GND VC
TERM
GND
VC GND
TERM
GND VC
TERM
GND
2
GND TERMA GND ID0# GND ID1# GND A07# GND A04# VC D30# GND D27# VC D20# GND NC VC D11# GND D07# VC D04# GND 3.3V VC
TERM TERM TERM TERM TERM
3
3
TUNER[1] TUNER[2]
TERMB GND ID2# GND ID3# GND A06# GND A05# GND D25# GND D23# GND D17# GND D13# GND D14# GND D01# GND NC GND GND
4
4
GND OUTEN
ID4#
ID5#
A13#
A10# GND DEP3# VC D24# GND STBP1# VC D16# GND D12# VC STBN0# GND D03# VC NC NC
TERM TERM TERM TERM
5
5
NC
NC
ID6# GND ID7# GND A11# GND A12# GND NC GND D29# GND STBN1# GND D19# GND DEP1# GND D08# GND STBP0# GND D02# GND GND
GND
6
6
GND RSP#
ID8#
GND
ID9#
A08#
A03# VC DEP2#
TERM
D26# VC D28#
TERM
D18# VC D09#
TERM
D06# VC D05# GND NC VC
TERM TERM
7
7
TDO
TDI
RS0#
IDS# GND DRDY0# GND A14# GND A09# GND D31# GND D22# GND D21# GND DEP0# GND D15# GND D10# GND D00# GND THRM
ALERT#
GND
8
8
GND INIT#
RS1#
RS2#
A17#
A15#
DEP6# VC D54#
TERM
D48# VC D49# GND D42# VC D45# GND D37# VC NC GND
TERM
TERM
TERM
9
9
REQ0# GND DBSY# GND
GND D63# GND
GND D53#
DEP4#
GND GND
D38#
TMS TCK
DSBY0# GND A21# GND A18#
D58#
GND D40# GND D35# GND VSSMON
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
GND REQ1#
REQ2#
HIT#
A24#
A20# VC DEP7#
TERM
D61# VC STBP3#
TERM
D50# VC D32#
TERM
STBN2# VC D34# GND GND VCTERM
TERM
NC
NC GND REQ3# GND DRDY# GND A23# GND A26# GND NC GND D60# GND STBN3# GND D56# GND DEP5# GND D41# GND STBP2# GND D33# GND VCCMON
GND REQ4#
REQ5#
HITM#
A25#
A19#
D62# VC D57#
TERM
D51# VC NC GND D46# VC D44# GND D36# VC
TERM TERM TERM
BCLKN BCLKP
SBSY# GND RP# GND SBSY0# GND A22# GND A16# GND D59# GND D55# GND D52# GND D47# GND D43# GND D39# GND NC GND GND
GND
GND TRDY#
GSEQ#
DEFER#
A34#
A31# VC D94#
TERM
D87# VC D84#
TERM
NC VC D75#
TERM
D68# VC D65# GND NC VC
TERM TERM
PWR PROC GND LOCK# GND TND# GND BINIT# GND A37# GND A28# GND D92# GND D91# GND D81# GND D78# GND D71# GND D67# GND NC GND SMA2
GOOD PRES#
GND BREQ0#
BREQ1#
NC
A36#
A38#
DEP11# VC D93#
TERM
STBP5# VC D83# GND D76# VC STBN4# GND D66# VC NC GND
TERM TERM TERM
NC
NC GND NC GND NC GND A33# GND A32# GND BNR# GND D89# GND STBN5# GND D88# GND DEP9# GND D72# GND STBP4# GND D73# GND SMA1
GND BREQ3#
NC
BREQ2#
A35#
A29# VC DEP10#
TERM
D95# VC D86#
TERM
D80# VC D77#
TERM
D69# VC D64# GND SMA0 VC
TERM TERM
NC
NC
NC GND BPRI# GND SBSY1# GND DBSY1# GND A30# GND A27# GND D90# GND D85# GND D82# GND DEP8# GND D79# GND D74# GND D70# GND GND
GND PPOD
GD#
RESET#
ADS# GND A39#
A45# GND DEP14# VC D122# GND D118# VC D117# GND D111# VC D106# GND D102# VC NC GND
TERM TERM TERM TERM
NC
TRST# GND NC GND DRDY1# GND A44# GND A48# GND D124# GND D127# GND D112# GND DEP12# GND D101# GND D96# GND D99# GND SMWP
GND
GND LINT0
A20M# IGNNE#
GND LINT1 GND BPM4# GND BPM5# GND A43#
BPM0#
BERR#
A49#
A47# VC DEP15#
TERM
D125# VC STBP7#
TERM
D114# VC D105#
TERM
STBN6# VC D98# GND SMSD VC
TERM TERM
BPM2# GND BPM3# GND AP1# GND A46# GND A42# GND D126# GND STBN7# GND D116# GND DEP13# GND D108# GND STBP6# GND D97# GND GND
A40# GND D123# VC D120# GND D115# VC NC GND D109# VC D103# GND D104# VC SMSC GND
TERM TERM TERM TERM
FERR# TH_TRIP#
PMI# GND BPM1# GND AP0# GND A41# GND VC GND D121# GND D119# GND D113# GND D110# GND D107# GND D100# GND NC GND VC
TERM TERM
AH AG AF AE AD AC AB AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
Power Pod
000638b
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
35
Pinout Specifications
Table 3-1 provides the Dual-Core Intel Itanium processor 9000 and 9100 series pin list
in alphabetical order.
Table 3-2 provides the Dual-Core Intel Itanium processor 9000 and 9100 series pin list
by pin location.
Table 3-1.
Pin/Signal Information Sorted by Pin Name (Sheet 1 of 15)
System Bus
Signal Name
Pin
Location
Pin Name
Input/Output
Notes
3.3V
B02
V06
V02
U03
W03
Y02
IN
SMBus supply voltage
A003#
A004#
A005#
A006#
A007#
A008#
A009#
A010#
A011#
A012#
A013#
A014#
A015#
A016#
A017#
A018#
A019#
A020#
A021#
A022#
A023#
A024#
A025#
A026#
A027#
A028#
A029#
A030#
A031#
A032#
A033#
A034#
A035#
A036#
A037#
A038#
A039#
A040#
AA03#/EXF0#
AA04#/EXF1#
AA05#/EXF2#
AA06#/EXF3#
AA07#/EXF4#
AA08#/BE0#
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
Y06
AA09#/BE1#
U07
V04
AA05
W05
Y04
AA10#/BE2#
AA11#/BE3#
AA12#/BE4#
AA13#/BE5#
AA14#/BE6#
W07
V08
U13
Y08
AA15#/BE7#
AA16#/DID0#
AA17#/DID1#
AA18#/DID2#
AA19#/DID3#
AA20#/DID4#
AA21#/DID5#
AA22#/DID6#
AA23#/DID7#
AA24#/DID8#
AA25#/DID9#
AA26#/AB26#
AA27#/xTPRValue0#
AA28#/xTPRValue1#
AA29#/xTPRValue2#
AA30#/xTPRValue3#
AA31#/xTPRDisable#
AA32#/ATTR0#
AA33#/ATTR1#
AA34#/ATTR2#
AA35#/ATTR3#
AA36#/AB36#
AA37#/AB37#
AA38#/AB38#
AA39#/AB39#
AA40#/AB40#
U09
V12
V10
W09
W13
AA11
Y10
Y12
W11
U19
U15
V18
W19
V14
W17
AA17
Y14
Y18
Y16
W15
V16
Y20
V24
®
®
36
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Pinout Specifications
Table 3-1.
Pin/Signal Information Sorted by Pin Name (Sheet 2 of 15)
System Bus
Signal Name
Pin
Location
Pin Name
Input/Output
Notes
A041#
A042#
A043#
A044#
A045#
A046#
A047#
A048#
A049#
A20M#
ADS#
AA41#/AB41#
AA42#/AB42#
AA43#/AB43#
AA44#/AB44#
AA45#/AB45#
AA46#/AB46#
AA47#/AB47#
AA48#/AB48#
AA49#/AB49#
A20M#
W25
U23
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
N/C
Y24
W21
V20
W23
V22
U21
Y22
AH23
AB20
AA25
AA23
AH13
AG13
AB22
AA15
U17
ADS#
IN/OUT
IN/OUT
IN/OUT
IN
AP0#
AP0#
AP1#
AP1#
BCLKn
BCLKp
BERR#
BINIT#
BNR#
BCLKN
BCLK
IN
BERR#
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN
BINIT#
BNR#
BPM0#
BPM1#
BPM2#
BPM3#
BPM4#
BPM5#
BPRI#
BR0#
BPM0#
AD22
AC25
AE23
AC23
AD24
AB24
AE19
AF16
AD16
AB18
AF18
AG15
C07
BPM1#
BPM2#
BPM3#
BPM4#
BPM5#
BPRI#
BREQ0#
BREQ1#
BREQ2#
BREQ3#
CPUPRES#
D00#
IN/OUT
IN
BR1#
BR2#
IN
BR3#
IN
CPUPRES#
D000#
D001#
D002#
D003#
D004#
D005#
D006#
D007#
D008#
D009#
D010#
D011#
D012#
D013#
OUT
Power pod signal
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
D01#
E03
D02#
C05
D03#
D04
D04#
D02
D05#
D06
D06#
F06
D07#
F02
D08#
G05
D09#
H06
D10#
E07
D11#
H02
D12#
H04
D13#
J03
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
37
Pinout Specifications
Table 3-1.
Pin/Signal Information Sorted by Pin Name (Sheet 3 of 15)
System Bus
Signal Name
Pin
Location
Pin Name
Input/Output
Notes
D014#
D015#
D016#
D017#
D018#
D019#
D020#
D021#
D022#
D023#
D024#
D025#
D026#
D027#
D028#
D029#
D030#
D031#
D032#
D033#
D034#
D035#
D036#
D037#
D038#
D039#
D040#
D041#
D042#
D043#
D044#
D045#
D046#
D047#
D048#
D049#
D050#
D051#
D052#
D053#
D054#
D055#
D056#
D057#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
G03
G07
K04
L03
K06
L05
M02
L07
N07
N03
P04
R03
P06
P02
M06
R05
T02
R07
H10
C11
D10
C09
D12
D08
G09
E13
E09
G11
H08
G13
F12
F08
H12
J13
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
M08
K08
K10
M12
L13
L09
P08
N13
L11
P12
®
®
38
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Pinout Specifications
Table 3-1.
Pin/Signal Information Sorted by Pin Name (Sheet 4 of 15)
System Bus
Signal Name
Pin
Location
Pin Name
Input/Output
Notes
D058#
D059#
D060#
D061#
D062#
D063#
D064#
D065#
D066#
D067#
D068#
D069#
D070#
D071#
D072#
D073#
D074#
D075#
D076#
D077#
D078#
D079#
D080#
D081#
D082#
D083#
D084#
D085#
D086#
D087#
D088#
D089#
D090#
D091#
D092#
D093#
D094#
D095#
D096#
D097#
D098#
D099#
D100#
D101#
D58#
D59#
D60#
D61#
D62#
D63#
D64#
D65#
D66#
D67#
D68#
D69#
D70#
D71#
D72#
D73#
D74#
D75#
D76#
D77#
D78#
D79#
D80#
D81#
D82#
D83#
D84#
D85#
D86#
D87#
D88#
D89#
D90#
D91#
D92#
D93#
D94#
D95#
D96#
D97#
D98#
D99#
D100#
D101#
N09
R13
R11
P10
T12
R09
D18
D14
D16
E15
F14
F18
C19
G15
G17
C17
E19
H14
H16
H18
J15
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
G19
K18
L15
L19
K16
M14
N19
M18
P14
L17
R17
R19
N15
R15
P16
T14
P18
E21
C23
D22
C21
E25
G21
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
39
Pinout Specifications
Table 3-1.
Pin/Signal Information Sorted by Pin Name (Sheet 5 of 15)
System Bus
Signal Name
Pin
Location
Pin Name
Input/Output
Notes
D102#
D103#
D104#
D105#
D106#
D107#
D108#
D109#
D110#
D111#
D112#
D113#
D114#
D115#
D116#
D117#
D118#
D119#
D120#
D121#
D122#
D123#
D124#
D125#
D126#
D127#
DBSY#
DBSY0#
DBSY1#
DEFER#
DEP00#
DEP01#
DEP02#
DEP03#
DEP04#
DEP05#
DEP06#
DEP07#
DEP08#
DEP09#
DEP10#
DEP11#
DEP12#
DEP13#
D102#
D103#
D104#
D105#
D106#
D107#
D108#
D109#
D110#
D111#
D112#
D113#
D114#
D115#
D116#
D117#
D118#
D119#
D120#
D121#
D122#
D123#
D124#
D125#
D126#
D127#
DBSY#
DBSY_C1#
DBSY_C2#
DEFER#
DEP0#
DEP1#
DEP2#
DEP3#
DEP4#
DEP5#
DEP6#
DEP7#
DEP8#
DEP9#
DEP10#
DEP11#
DEP12#
DEP13#
D20
F24
D24
H22
F20
G25
G23
H24
J25
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
OUT
H20
L21
L25
K22
M24
L23
K20
M20
N25
P24
R25
P20
T24
R21
P22
R23
N21
AC09
AA09
AA19
AB14
J07
OUT
IN
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
J05
T06
T04
J09
J11
T08
T10
J19
J17
T18
T16
J21
J23
®
®
40
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Pinout Specifications
Table 3-1.
Pin/Signal Information Sorted by Pin Name (Sheet 6 of 15)
System Bus
Signal Name
Pin
Location
Pin Name
Input/Output
Notes
DEP14#
DEP15#
DRDY#
DRDY0#
DRDY1#
FERR#
GND
DEP14#
DEP15#
DRDY#
DRDY_C1#
DRDY_C2#
FERR#
GND
T20
T22
IN/OUT
IN/OUT
IN/OUT
OUT
OUT
OUT
IN
AC11
AA07
AA21
AH25
A01
GND
GND
A03
IN
GND
GND
A05
IN
GND
GND
A08
IN
GND
GND
A13
IN
GND
GND
A16
IN
GND
GND
A19
IN
GND
GND
A20
IN
GND
GND
A23
IN
GND
GND
A24
IN
GND
GND
AA02
AA20
AA24
AB01
AB03
AB05
AB07
AB09
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB25
AC02
AC24
AD01
AD03
AD05
AD07
AD09
AD11
AD13
AD15
AD17
AD19
IN
GND
GND
IN
GND
GND
IN
GND
GND
IN
GND
GND
IN
GND
GND
IN
GND
GND
IN
GND
GND
IN
GND
GND
IN
GND
GND
IN
GND
GND
IN
GND
GND
IN
GND
GND
IN
GND
GND
IN
GND
GND
IN
GND
GND
IN
GND
GND
IN
GND
GND
IN
GND
GND
IN
GND
GND
IN
GND
GND
IN
GND
GND
IN
GND
GND
IN
GND
GND
IN
GND
GND
IN
GND
GND
IN
GND
GND
IN
GND
GND
IN
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
41
Pinout Specifications
Table 3-1.
Pin/Signal Information Sorted by Pin Name (Sheet 7 of 15)
System Bus
Signal Name
Pin
Location
Pin Name
Input/Output
Notes
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AD21
AD23
AD25
AE02
AE24
AF01
AF05
AF07
AF09
AF11
AF13
AF15
AF17
AF19
AF21
AG02
AG04
AG06
AG08
AG10
AG12
AG14
AG16
AG18
AG20
AG22
AG24
AH01
B03
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
B05
B07
B09
B10
B11
B13
B15
B17
B19
B21
B23
B25
C02
C06
C10
®
®
42
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Pinout Specifications
Table 3-1.
Pin/Signal Information Sorted by Pin Name (Sheet 8 of 15)
System Bus
Signal Name
Pin
Location
Pin Name
Input/Output
Notes
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
C14
C18
C22
D01
D03
D05
D07
D09
D11
D13
D15
D17
D19
D21
D23
D25
E04
E08
E12
E16
E20
E24
F01
F03
F05
F07
F09
F11
F13
F15
F17
F19
F21
F23
F25
G02
H03
H05
H07
H09
H11
H13
H15
H17
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
43
Pinout Specifications
Table 3-1.
Pin/Signal Information Sorted by Pin Name (Sheet 9 of 15)
System Bus
Signal Name
Pin
Location
Pin Name
Input/Output
Notes
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
H19
H21
H23
H25
J01
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
J04
J08
J12
J16
J20
J24
K03
K05
K07
K09
K11
K13
K15
K17
K19
K21
K23
K25
L02
M01
M03
M05
M07
M09
M11
M13
M15
M17
M19
M21
M23
M25
N04
N20
N24
P01
P03
P05
P07
®
®
44
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Pinout Specifications
Table 3-1.
Pin/Signal Information Sorted by Pin Name (Sheet 10 of 15)
System Bus
Signal Name
Pin
Location
Pin Name
Input/Output
Notes
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
P09
P11
P13
P15
P17
P19
P21
P23
P25
R02
T01
T03
T05
T07
T09
T11
T13
T15
T17
T19
T21
T23
T25
U04
U20
U24
V01
V03
V05
V07
V09
V11
V13
V15
V17
V19
V21
V23
V25
W02
Y01
Y03
Y05
Y07
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
45
Pinout Specifications
Table 3-1.
Pin/Signal Information Sorted by Pin Name (Sheet 11 of 15)
System Bus
Signal Name
Pin
Location
Pin Name
Input/Output
Notes
GND
GND
GND
GND
GND
GND
GND
GND
GND
GSEQ#
HIT#
HITM#
ID0#
ID1#
ID2#
ID3#
ID4#
ID5#
ID6#
ID7#
ID8#
ID9#
IDS#
IGNNE#
INIT#
LINT0
LINT1
LOCK#
N/C
GND
GND
Y09
Y11
IN
IN
GND
Y13
IN
GND
Y15
IN
GND
Y17
IN
GND
Y19
IN
GND
Y21
IN
GND
Y23
IN
GND
Y25
IN
GSEQ#
AD14
AB10
AB12
AD02
AB02
AC03
AA03
AD04
AB04
AE05
AC05
AD06
AB06
AC07
AG23
AF08
AF22
AF24
AE15
A04
IN
HIT#
IN/OUT
IN/OUT
IN
HITM#
IDA0#/IP0#
IDA1#/IP1#
IDA2#/DHIT#
IDA3#/IDB3#
IDA4#/IDB4#
IDA5#/IDB5#
IDA6#/IDB6#
IDA7#/IDB7#
IDA8#/IDB8#
IDA9#/IDB9#
IDS#
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IGNNE#
INIT#
N/C
IN
INT
IN
NMI
IN
LOCK#
N/C
N/C
AB16
AC17
AC21
AD18
AE17
AG05
AG11
AG17
AG19
AG21
AH05
AH11
AH17
AH19
AH21
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
®
®
46
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Pinout Specifications
Table 3-1.
Pin/Signal Information Sorted by Pin Name (Sheet 12 of 15)
System Bus
Signal Name
Pin
Location
Pin Name
Input/Output
Notes
N/C
N/C
B04
B06
N/C
B08
N/C
B14
N/C
B16
N/C
B20
N/C
C03
N/C
C13
N/C
C15
N/C
C25
N/C
K02
N/C
K12
N/C
K14
N/C
K24
N/C
U05
N/C
U11
OUTEN
PMI#
PPODGD#
PWRGOOD
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
REQ5#
RESET#
RP#
OUTEN
PMI#
AF04
AE25
AF20
AH15
AE09
AF10
AD10
AE11
AF12
AD12
AD20
AC13
AE07
AD08
AB08
AF06
AE13
AA13
AC19
B18
IN
IN
Power pod signal
Power pod signal
PPODGD#
PWRGOOD
REQA0#/LEN0#
WSNP#, D/C#/LEN1#
REQA2#/ REQB2#
ASZ0#/DSZ0#
ASZ1#/DSZ1#
REQ5#
OUT
IN
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN
RESET#
RP#
IN/OUT
IN
RS0#
RS1#
RS2#
RSP#
SBSY#
SBSY0#
SBSY1#
SMA0
SMA1
SMA2
SMSC
SMSD
SMWP
STBN0#
STBN1#
STBN2#
RS0#
RS1#
IN
RS2#
IN
RSP#
IN
SBSY#
IN/OUT
OUT
SBSY_C1#
SBSY_C2#
SMA0
OUT
IN
SMBus signal
SMBus signal
SMBus signal
SMBus signal
SMBus signal
SMBus signal
SMA1
A17
IN
SMA2
A15
IN
SMSC
B24
IN
SMSD
B22
IN/OUT
IN
SMWP
A21
STBN0#
F04
IN/OUT
IN/OUT
IN/OUT
STBN1#
N05
STBN2#
F10
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
47
Pinout Specifications
Table 3-1.
Pin/Signal Information Sorted by Pin Name (Sheet 13 of 15)
System Bus
Signal Name
Pin
Location
Pin Name
Input/Output
Notes
STBN3#
STBN4#
STBN5#
STBN6#
STBN7#
STBP0#
STBP1#
STBP2#
STBP3#
STBP4#
STBP5#
STBP6#
STBP7#
TCK
STBN3#
STBN4#
STBN5#
STBN6#
STBN7#
STBP0#
STBP1#
STBP2#
STBP3#
STBP4#
STBP5#
STBP6#
STBP7#
TCK
N11
F16
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OuT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN
N17
F22
N23
E05
M04
E11
M10
E17
M16
E23
M22
AG09
AG07
AH07
AF02
AE03
AG25
A07
JTAG
JTAG
JTAG
TDI
TDI
IN
TDO
TDO
OUT
IN
TERMA
FSBT1
TERMB
FSBT2
IN
THRMTRIP#
THRMALERT#
TMS
THRMTRIP#
THRMALERT#
TMS
OUT
OUT
IN
AH09
AC15
AF14
AE21
AH03
AG03
B08
JTAG
JTAG
TND#
TND#
IN/OUT
IN
TRDY#
TRDY#
TRST#
TRST#
IN
TUNER[1]
TUNER[2]
TUNER[3]
VCCMON
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
TUNER[1]
TUNER[2]
TUNER[3]
VCCMON
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
IN
IN
IN
A11
N/C
IN
A02
A06
IN
A10
IN
A14
IN
A18
IN
A22
IN
A25
IN
C01
C04
C08
C12
C16
C20
C24
E02
IN
IN
IN
IN
IN
IN
IN
IN
E06
IN
®
®
48
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Pinout Specifications
Table 3-1.
Pin/Signal Information Sorted by Pin Name (Sheet 14 of 15)
System Bus
Signal Name
Pin
Location
Pin Name
Input/Output
Notes
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
VCTERM
E10
E14
E18
E22
G01
G04
G08
G12
G16
G20
G24
J02
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
J06
J10
J14
J18
J22
L01
L04
L08
L12
L16
L20
L24
N02
N06
N10
N14
N18
N22
R01
R04
R08
R12
R16
R20
R24
U02
U06
U10
U14
U18
U22
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
49
Pinout Specifications
Table 3-1.
Table 3-2.
Pin/Signal Information Sorted by Pin Name (Sheet 15 of 15)
System Bus
Signal Name
Pin
Location
Pin Name
Input/Output
Notes
VCTERM
VSSMON
VCTERM
VSSMON
U25
A09
IN
N/C
Pin/Signal Information Sorted by Pin Location (Sheet 1 of 15)
System Bus
Signal Name
Pin
Location
Pin Name
Input/Output
Notes
GND
VCTERM
GND
GND
VCTERM
GND
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B13
B14
B15
B16
IN
IN
IN
N/C
GND
GND
VCTERM
THRMALERT#
GND
IN
IN
VCTERM
THRMALERT#
GND
OUT
IN
VSSMON
VCTERM
VCCMON
GND
VSSMON
VCTERM
VCCMON
GND
N/C
IN
N/C
IN
VCTERM
SMA2
GND
VCTERM
SMA2
IN
IN
SMBus signal
SMBus signal
GND
IN
SMA1
VCTERM
GND
SMA1
IN
VCTERM
GND
IN
IN
GND
GND
IN
SMWP
VCTERM
GND
SMWP
IN
SMBus signal
VCTERM
GND
IN
IN
GND
GND
IN
VCTERM
3.3V
VCTERM
IN
IN
SMBus supply voltage
GND
GND
GND
IN
N/C
GND
IN
N/C
GND
GND
Tuner[3]
GND
IN
IN
IN
IN
IN
IN
Tuner[3]
GND
GND
GND
GND
GND
GND
GND
N/C
GND
GND
IN
N/C
®
®
50
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Pinout Specifications
Table 3-2.
Pin/Signal Information Sorted by Pin Location (Sheet 2 of 15)
System Bus
Signal Name
Pin
Location
Pin Name
Input/Output
Notes
GND
SMA0
GND
GND
SMA0
GND
B17
B18
B19
B20
B21
B22
B23
B24
B25
C01
C02
C03
C04
C05
C06
C07
C08
C09
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
IN
IN
IN
SMBus signal
N/C
GND
GND
SMSD
GND
IN
IN/OUT
IN
SMSD
GND
SMBus signal
SMBus signal
SMSC
GND
SMSC
GND
IN
IN
VCTERM
GND
VCTERM
GND
IN
IN
N/C
VCTERM
D002#
GND
VCTERM
D02#
IN
IN/OUT
IN
GND
D000#
VCTERM
D035#
GND
D00#
IN/OUT
IN
VCTERM
D35#
IN/OUT
IN
GND
D033#
VCTERM
N/C
D33#
IN/OUT
IN
VCTERM
GND
GND
IN
N/C
VCTERM
D073#
GND
VCTERM
D73#
IN
IN/OUT
IN
GND
D070#
VCTERM
D099#
GND
D70#
IN/OUT
IN
VCTERM
D99#
IN/OUT
IN
GND
D097#
VCTERM
N/C
D97#
IN/OUT
IN
VCTERM
GND
GND
D04#
GND
IN
IN/OUT
IN
D004#
GND
D003#
GND
D03#
GND
IN/OUT
IN
D005#
GND
D05#
GND
IN/OUT
IN
D037#
GND
D37#
GND
IN/OUT
IN
D034#
D34#
IN/OUT
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
51
Pinout Specifications
Table 3-2.
Pin/Signal Information Sorted by Pin Location (Sheet 3 of 15)
System Bus
Signal Name
Pin
Location
Pin Name
Input/Output
Notes
GND
D036#
GND
GND
D36#
GND
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
E02
E03
E04
E05
E06
E07
E08
E09
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
F01
F02
F03
F04
F05
IN
IN/OUT
IN
D065#
GND
D65#
GND
IN/OUT
IN
D066#
GND
D66#
GND
IN/OUT
IN
D064#
GND
D64#
GND
IN/OUT
IN
D102#
GND
D102#
GND
IN/OUT
IN
D098#
GND
D98#
GND
IN/OUT
IN
D104#
GND
D104#
GND
IN/OUT
IN
VCTERM
D001#
GND
VCTERM
D01#
GND
IN
IN/OUT
IN
STBP0#
VCTERM
D010#
GND
STBP0#
VCTERM
D10#
GND
IN/OUT
IN
IN/OUT
IN
D040#
VCTERM
STBP2#
GND
D40#
VCTERM
STBP2#
GND
IN/OUT
IN
IN/OUT
IN
D039#
VCTERM
D067#
GND
D39#
VCTERM
D67#
GND
IN/OUT
IN
IN/OUT
IN
STBP4#
VCTERM
D074#
GND
STBP4#
VCTERM
D74#
GND
IN/OUT
IN
IN/OUT
IN
D096#
VCTERM
STBP6#
GND
D96#
VCTERM
STBP6#
GND
IN/OUT
IN
IN/OUT
IN
D100#
GND
D100#
GND
IN/OUT
IN
D007#
GND
D07#
GND
IN/OUT
IN
STBN0#
GND
STBN0#
GND
IN/OUT
IN
®
®
52
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Pinout Specifications
Table 3-2.
Pin/Signal Information Sorted by Pin Location (Sheet 4 of 15)
System Bus
Signal Name
Pin
Location
Pin Name
Input/Output
Notes
D006#
GND
D06#
GND
F06
F07
F08
F09
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
G01
G02
G03
G04
G05
G07
G08
G09
G11
G12
G13
G15
G16
G17
G19
G20
G21
G23
G24
G25
H02
H03
H04
H05
IN/OUT
IN
D045#
GND
D45#
GND
IN/OUT
IN
STBN2#
GND
STBN2#
GND
IN/OUT
IN
D044#
GND
D44#
GND
IN/OUT
IN
D068#
GND
D68#
GND
IN/OUT
IN
STBN4#
GND
STBN4#
GND
IN/OUT
IN
D069#
GND
D69#
GND
IN/OUT
IN
D106#
GND
D106#
GND
IN/OUT
IN
STBN6#
GND
STBN6#
GND
IN/OUT
IN
D103#
GND
D103#
GND
IN/OUT
IN
VCTERM
GND
VCTERM
GND
IN
IN
D014#
VCTERM
D008#
D015#
VCTERM
D038#
D041#
VCTERM
D043#
D071#
VCTERM
D072#
D079#
VCTERM
D101#
D108#
VCTERM
D107#
D011#
GND
D14#
VCTERM
D08#
D15#
VCTERM
D38#
D41#
VCTERM
D43#
D71#
VCTERM
D72#
D79#
VCTERM
D101#
D108#
VCTERM
D107#
D11#
GND
IN/OUT
IN
IN/OUT
IN/OUT
IN
IN/OUT
IN/OUT
IN
IN/OUT
IN/OUT
IN
IN/OUT
IN/OUT
IN
IN/OUT
IN/OUT
IN
IN/OUT
IN/OUT
IN
D012#
GND
D12#
GND
IN/OUT
IN
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
53
Pinout Specifications
Table 3-2.
Pin/Signal Information Sorted by Pin Location (Sheet 5 of 15)
System Bus
Signal Name
Pin
Location
Pin Name
Input/Output
Notes
D009#
GND
D09#
GND
H06
H07
H08
H09
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
J01
J02
J03
J04
J05
J06
J07
J08
J09
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
J23
J24
IN/OUT
IN
D042#
GND
D42#
GND
IN/OUT
IN
D032#
GND
D32#
GND
IN/OUT
IN
D046#
GND
D46#
GND
IN/OUT
IN
D075#
GND
D75#
GND
IN/OUT
IN
D076#
GND
D76#
GND
IN/OUT
IN
D077#
GND
D77#
GND
IN/OUT
IN
D111#
GND
D111#
GND
IN/OUT
IN
D105#
GND
D105#
GND
IN/OUT
IN
D109#
GND
D109#
GND
IN/OUT
IN
GND
GND
IN
VCTERM
D013#
GND
VCTERM
D13#
GND
IN
IN/OUT
IN
DEP01#
VCTERM
DEP00#
GND
DEP1#
VCTERM
DEP0#
GND
IN/OUT
IN
IN/OUT
IN
DEP04#
VCTERM
DEP05#
GND
DEP4#
VCTERM
DEP5#
GND
IN/OUT
IN
IN/OUT
IN
D047#
VCTERM
D078#
GND
D47#
VCTERM
D78#
GND
IN/OUT
IN
IN/OUT
IN
DEP09#
VCTERM
DEP08#
GND
DEP9#
VCTERM
DEP8#
GND
IN/OUT
IN
IN/OUT
IN
DEP12#
VCTERM
DEP13#
GND
DEP12#
VCTERM
DEP13#
GND
IN/OUT
IN
IN/OUT
IN
®
®
54
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Pinout Specifications
Table 3-2.
Pin/Signal Information Sorted by Pin Location (Sheet 6 of 15)
System Bus
Signal Name
Pin
Location
Pin Name
Input/Output
Notes
D110#
N/C
D110#
J25
K02
K03
K04
K05
K06
K07
K08
K09
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
K23
K24
K25
L01
L02
L03
L04
L05
L07
L08
L09
L11
L12
L13
L15
L16
L17
L19
L20
L21
L23
L24
IN/OUT
GND
GND
D16#
GND
IN
IN/OUT
IN
D016#
GND
D018#
GND
D18#
GND
IN/OUT
IN
D049#
GND
D49#
GND
IN/OUT
IN
D050#
GND
D50#
GND
IN/OUT
IN
N/C
GND
GND
IN
N/C
GND
GND
D83#
GND
IN
IN/OUT
IN
D083#
GND
D080#
GND
D80#
GND
IN/OUT
IN
D117#
GND
D117#
GND
IN/OUT
IN
D114#
GND
D114#
GND
IN/OUT
IN
N/C
GND
GND
VCTERM
GND
IN
IN
VCTERM
GND
IN
D017#
VCTERM
D019#
D021#
VCTERM
D053#
D056#
VCTERM
D052#
D081#
VCTERM
D088#
D082#
VCTERM
D112#
D116#
VCTERM
D17#
IN/OUT
IN
VCTERM
D19#
IN/OUT
IN/OUT
IN
D21#
VCTERM
D53#
IN/OUT
IN/OUT
IN
D56#
VCTERM
D52#
IN/OUT
IN/OUT
IN
D81#
VCTERM
D88#
IN/OUT
IN/OUT
IN
D82#
VCTERM
D112#
D116#
VCTERM
IN/OUT
IN/OUT
IN
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
55
Pinout Specifications
Table 3-2.
Pin/Signal Information Sorted by Pin Location (Sheet 7 of 15)
System Bus
Signal Name
Pin
Location
Pin Name
Input/Output
Notes
D113#
GND
D113#
GND
L25
M01
M02
M03
M04
M05
M06
M07
M08
M09
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
M23
M24
M25
N02
N03
N04
N05
N06
N07
N09
N10
N11
N13
N14
N15
N17
N18
N19
N20
N21
N22
IN/OUT
IN
D020#
GND
D20#
GND
IN/OUT
IN
STBP1#
GND
STBP1#
GND
IN/OUT
IN
D028#
GND
D28#
GND
IN/OUT
IN
D048#
GND
D48#
GND
IN/OUT
IN
STBP3#
GND
STBP3#
GND
IN/OUT
IN
D051#
GND
D51#
GND
IN/OUT
IN
D084#
GND
D84#
GND
IN/OUT
IN
STBP5#
GND
STBP5#
GND
IN/OUT
IN
D086#
GND
D86#
GND
IN/OUT
IN
D118#
GND
D118#
GND
IN/OUT
IN
STBP7#
GND
STBP7#
GND
IN/OUT
IN
D115#
GND
D115#
GND
IN/OUT
IN
VCTERM
D023#
GND
VCTERM
D23#
GND
IN
IN/OUT
IN
STBN1#
VCTERM
D022#
D058#
VCTERM
STBN3#
D055#
VCTERM
D091#
STBN5#
VCTERM
D085#
GND
STBN1#
VCTERM
D22#
D58#
VCTERM
STBN3#
D55#
VCTERM
D91#
STBN5#
VCTERM
D85#
GND
IN/OUT
IN
IN/OUT
IN/OUT
IN
IN/OUT
IN/OUT
IN
IN/OUT
IN/OUT
IN
IN/OUT
IN
D127#
VCTERM
D127#
VCTERM
IN/OUT
IN
®
®
56
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Pinout Specifications
Table 3-2.
Pin/Signal Information Sorted by Pin Location (Sheet 8 of 15)
System Bus
Signal Name
Pin
Location
Pin Name
Input/Output
Notes
STBN7#
GND
STBN7#
GND
N23
N24
N25
P01
P02
P03
P04
P05
P06
P07
P08
P09
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
R01
R02
R03
R04
R05
R07
R08
R09
R11
R12
R13
R15
R16
R17
R19
R20
IN/OuT
IN
D119#
GND
D119#
GND
IN/OUT
IN
D027#
GND
D27#
GND
IN/OUT
IN
D024#
GND
D24#
GND
IN/OUT
IN
D026#
GND
D26#
GND
IN/OUT
IN
D054#
GND
D54#
GND
IN/OUT
IN
D061#
GND
D61#
GND
IN/OUT
IN
D057#
GND
D57#
GND
IN/OUT
IN
D087#
GND
D87#
GND
IN/OUT
IN
D093#
GND
D93#
GND
IN/OUT
IN
D095#
GND
D95#
GND
IN/OUT
IN
D122#
GND
D122#
GND
IN/OUT
IN
D125#
GND
D125#
GND
IN/OUT
IN
D120#
GND
D120#
GND
IN/OUT
IN
VCTERM
GND
VCTERM
GND
IN
IN
D025#
VCTERM
D029#
D031#
VCTERM
D063#
D060#
VCTERM
D059#
D092#
VCTERM
D089#
D090#
VCTERM
D25#
VCTERM
D29#
D31#
VCTERM
D63#
D60#
VCTERM
D59#
D92#
VCTERM
D89#
D90#
VCTERM
IN/OUT
IN
IN/OUT
IN/OUT
IN
IN/OUT
IN/OUT
IN
IN/OUT
IN/OUT
IN
IN/OUT
IN/OUT
IN
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
57
Pinout Specifications
Table 3-2.
Pin/Signal Information Sorted by Pin Location (Sheet 9 of 15)
System Bus
Signal Name
Pin
Location
Pin Name
Input/Output
Notes
D124#
D126#
VCTERM
D121#
GND
D124#
D126#
VCTERM
D121#
GND
R21
R23
R24
R25
T01
T02
T03
T04
T05
T06
T07
T08
T09
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
U02
U03
U04
U05
U06
U07
U09
U10
U11
U13
U14
U15
U17
U18
U19
IN/OUT
IN/OUT
IN
IN/OUT
IN
D030#
GND
D30#
IN/OUT
IN
GND
DEP03#
GND
DEP3#
GND
IN/OUT
IN
DEP02#
GND
DEP2#
GND
IN/OUT
IN
DEP06#
GND
DEP6#
GND
IN/OUT
IN
DEP07#
GND
DEP7#
GND
IN/OUT
IN
D062#
GND
D62#
IN/OUT
IN
GND
D094#
GND
D94#
IN/OUT
IN
GND
DEP11#
GND
DEP11#
GND
IN/OUT
IN
DEP10#
GND
DEP10#
GND
IN/OUT
IN
DEP14#
GND
DEP14#
GND
IN/OUT
IN
DEP15#
GND
DEP15#
GND
IN/OUT
IN
D123#
GND
D123#
GND
IN/OUT
IN
VCTERM
A005#
GND
VCTERM
AA05#/EXF2#
GND
IN
IN/OUT
IN
N/C
VCTERM
A009#
A018#
VCTERM
N/C
VCTERM
AA09#/BE1#
AA18#/DID2#
VCTERM
IN
IN/OUT
IN/OUT
IN
A016#
VCTERM
A028#
BNR#
VCTERM
A027#
AA16#/DID0#
VCTERM
IN/OUT
IN
AA28#/xTPRValue1#
BNR#
IN/OUT
IN/OUT
IN
VCTERM
AA27#/xTPRValue0#
IN/OUT
®
®
58
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Pinout Specifications
Table 3-2.
Pin/Signal Information Sorted by Pin Location (Sheet 10 of 15)
System Bus
Signal Name
Pin
Location
Pin Name
Input/Output
Notes
GND
A048#
VCTERM
A042#
GND
GND
AA48#/AB48#
VCTERM
U20
U21
U22
U23
U24
U25
V01
V02
V03
V04
V05
V06
V07
V08
V09
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
V23
V24
V25
W02
W03
W05
W07
W09
W11
W13
W15
W17
W19
W21
W23
W25
IN
IN/OUT
IN
AA42#/AB42#
GND
IN/OUT
IN
VCTERM
GND
VCTERM
IN
GND
IN
A004#
GND
AA04#/EXF1#
GND
IN/OUT
IN
A010#
GND
AA10#/BE2#
GND
IN/OUT
IN
A003#
GND
AA03#/EXF0#
GND
IN/OUT
IN
A015#
GND
AA15#/BE7#
GND
IN/OUT
IN
A020#
GND
AA20#/DID4#
GND
IN/OUT
IN
A019#
GND
AA19#/DID3#
GND
IN/OUT
IN
A031#
GND
AA31#/xTPRDisable#
GND
IN/OUT
IN
A038#
GND
AA38#/AB38#
GND
IN/OUT
IN
A029#
GND
AA29#/xTPRValue2#
GND
IN/OUT
IN
A045#
GND
AA45#/AB45#
GND
IN/OUT
IN
A047#
GND
AA47#/AB47#
GND
IN/OUT
IN
A040#
GND
AA40#/AB40#
GND
IN/OUT
IN
GND
GND
IN
A006#
A012#
A014#
A021#
A026#
A022#
A037#
A032#
A030#
A044#
A046#
A041#
AA06#/EXF3#
AA12#/BE4#
AA14#/BE6#
AA21#/DID5#
AA26#/AB26#
AA22#/DID6#
AA37#/AB37#
AA32#/ATTR0#
AA30#/xTPRValue3#
AA44#/AB44#
AA46#/AB46#
AA41#/AB41#
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
59
Pinout Specifications
Table 3-2.
Pin/Signal Information Sorted by Pin Location (Sheet 11 of 15)
System Bus
Signal Name
Pin
Location
Pin Name
Input/Output
Notes
GND
A007#
GND
GND
AA07#/EXF4#
GND
Y01
Y02
IN
IN/OUT
IN
Y03
A013#
GND
AA13#/BE5#
GND
Y04
IN/OUT
IN
Y05
A008#
GND
AA08#/BE0#
GND
Y06
IN/OUT
IN
Y07
A017#
GND
AA17#/DID1#
GND
Y08
IN/OUT
IN
Y09
A024#
GND
AA24#/DID8#
GND
Y10
IN/OUT
IN
Y11
A025#
GND
AA25#/DID9#
GND
Y12
IN/OUT
IN
Y13
A034#
GND
AA34#/ATTR2#
GND
Y14
IN/OUT
IN
Y15
A036#
GND
AA36#/AB36#
GND
Y16
IN/OUT
IN
Y17
A035#
GND
AA35#/ATTR3#
GND
Y18
IN/OUT
IN
Y19
A039#
GND
AA39#/AB39#
GND
Y20
IN/OUT
IN
Y21
A049#
GND
AA49#/AB49#
GND
Y22
IN/OUT
IN
Y23
A043#
GND
AA43#/AB43#
GND
Y24
IN/OUT
IN
Y25
GND
GND
AA02
AA03
AA05
AA07
AA09
AA11
AA13
AA15
AA17
AA19
AA20
AA21
AA23
AA24
AA25
AB01
AB02
AB03
AB04
IN
ID3#
IDA3#/IDB3#
AA11#/BE3#
DRDY_C1#
DBSY_C1#
AA23#/DID7#
SBSY_C1#
BINIT#
IN
A011#
DRDY0#
DBSY0#
A023#
SBSY0#
BINIT#
A033#
DBSY1#
GND
IN/OUT
OUT
OUT
IN/OUT
OUT
IN/OUT
IN/OUT
OUT
AA33#/ATTR1#
DBSY_C2#
GND
IN
DRDY1#
AP1#
GND
DRDY_C2#
AP1#
OUT
IN/OUT
IN
GND
AP0#
GND
AP0#
IN/OUT
IN
GND
ID1#
IDA1#/IP1#
GND
IN
GND
IN
ID5#
IDA5#/IDB5#
IN
®
®
60
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Pinout Specifications
Table 3-2.
Pin/Signal Information Sorted by Pin Location (Sheet 12 of 15)
System Bus
Signal Name
Pin
Location
Pin Name
Input/Output
Notes
GND
ID9#
GND
GND
IDA9#/IDB9#
GND
AB05
AB06
AB07
AB08
AB09
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AB24
AB25
AC02
AC03
AC05
AC07
AC09
AC11
AC13
AC15
AC17
AC19
AC21
AC23
AC24
AC25
AD01
AD02
AD03
AD04
AD05
AD06
AD07
AD08
AD09
IN
IN
IN
RS2#
GND
RS2#
IN
GND
IN
HIT#
GND
HIT#
IN/OUT
IN
GND
HITM#
GND
HITM#
GND
IN/OUT
IN
DEFER#
GND
DEFER#
GND
IN
IN
N/C
GND
GND
BREQ2#
GND
IN
IN
BR2#
GND
IN
ADS#
GND
ADS#
IN/OUT
IN
GND
BERR#
GND
BERR#
GND
IN/OUT
IN
BPM5#
GND
BPM5#
GND
IN/OUT
IN
GND
GND
IN
ID2#
ID7#
IDS#
DBSY#
DRDY#
RP#
IDA2#/DHIT#
IDA7#/IDB7#
IDS#
IN
IN
IN
DBSY#
DRDY#
RP#
IN/OUT
IN/OUT
IN/OUT
IN/OUT
TND#
N/C
TND#
SBSY1#
N/C#
BPM3#
GND
SBSY_C2#
OUT
BPM3#
GND
IN/OUT
IN
BPM1#
GND
BPM1#
GND
IN/OUT
IN
ID0#
GND
IDA0#/IP0#
GND
IN
IN
ID4#
GND
IDA4#/IDB4#
GND
IN
IN
ID8#
GND
IDA8#/IDB8#
GND
IN
IN
RS1#
GND
RS1#
IN
GND
IN
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
61
Pinout Specifications
Table 3-2.
Pin/Signal Information Sorted by Pin Location (Sheet 13 of 15)
System Bus
Signal Name
Pin
Location
Pin Name
Input/Output
Notes
REQ2#
GND
REQA2#/ REQB2#
GND
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AE02
AE03
AE05
AE07
AE09
AE11
AE13
AE15
AE17
AE19
AE21
AE23
AE24
AE25
AF01
AF02
AF04
AF05
AF06
AF07
AF08
AF09
AF10
AF11
AF12
AF13
AF14
AF15
IN/OUT
IN
REQ5#
GND
REQ5#
GND
IN/OUT
IN
GSEQ#
GND
GSEQ#
GND
IN
IN
BR1#
GND
BREQ1#
GND
IN
IN
N/C
GND
GND
RESET#
GND
IN
IN
RESET#
GND
IN
BPM0#
GND
BPM0#
IN/OUT
IN
GND
BPM4#
GND
BPM4#
IN/OUT
IN
GND
GND
GND
IN
TERMB
ID6#
RS0#
REQ0#
REQ3#
SBSY#
LOCK#
N/C
FSBT2
IDA6#/IDB6#
RS0#
IN
IN
REQA0#/LEN0#
ASZ0#/DSZ0#
SBSY#
IN/OUT
IN/OUT
IN/OUT
N/C
LOCK#
BPRI#
TRST#
BPM2#
GND
BPRI#
TRST#
BPM2#
GND
IN
IN
IN/OUT
IN
PMI#
GND
PMI#
IN
GND
IN
TERM
OUTEN
GND
FSBT
IN
OUTEN
GND
IN
Power pod signal
IN
RSP#
GND
RSP#
IN
GND
IN
INIT#
GND
INIT#
IN
GND
IN
REQ1#
GND
WSNP#, D/C#/LEN1#
GND
IN/OUT
IN
REQ4#
GND
ASZ1#/DSZ1#
GND
IN/OUT
IN
TRDY#
GND
TRDY#
GND
IN
IN
®
®
62
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Pinout Specifications
Table 3-2.
Pin/Signal Information Sorted by Pin Location (Sheet 14 of 15)
System Bus
Signal Name
Pin
Location
Pin Name
Input/Output
Notes
BR0#
GND
BREQ0#
GND
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AF24
AG02
AG03
AG04
AG05
AG06
AG07
AG08
AG09
AG10
AG11
AG12
AG13
AG14
AG15
AG16
AG17
AG18
AG19
AG20
AG21
AG22
AG23
AG24
AG25
AH01
AH03
AH05
AH07
AH09
AH11
AH13
AH15
AH17
AH19
AH21
IN/OUT
IN
BR3#
GND
BREQ3#
GND
IN
IN
PPODGD#
GND
PPODGD#
GND
OUT
IN
Power pod signal
LINT0
LINT1
GND
INT
IN
NMI
IN
GND
IN
TUNER[2]
GND
IN
GND
IN
N/C
GND
GND
TDI
IN
IN
IN
IN
IN
TDI
JTAG
JTAG
GND
GND
TCK
GND
TCK
GND
N/C
GND
GND
CLK
IN
IN
BCLKp
GND
GND
IN
CPUPRES#
GND
CPUPRES#
GND
OUT
IN
Power pod signal
N/C
GND
GND
GND
IN
IN
N/C
GND
N/C
GND
GND
IGNNE#
GND
IN
N/C
IN
IGNNE#
GND
THRMTRIP#
GND
THRMTRIP#
GND
OUT
IN
Thermal trip
TUNER[1]
N/C
IN
TDO
TDO
TMS
OUT
IN
JTAG
JTAG
TMS
N/C
BCLKn
PWRGOOD
N/C
BCLKN
IN
IN
PWRGOOD
N/C
N/C
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
63
Pinout Specifications
Table 3-2.
Pin/Signal Information Sorted by Pin Location (Sheet 15 of 15)
System Bus
Signal Name
Pin
Location
Pin Name
Input/Output
Notes
A20M#
FERR#
A20M#
FERR#
AH23
AH25
N/C
OUT
§
®
®
64
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Mechanical Specifications
4 Mechanical Specifications
This chapter provides the mechanical specifications of the Dual-Core Intel Itanium
processor 9000 and 9100 series.
4.1
Processor Package Dimensions
Figure 4-1 through Figure 4-5 provide package mechanical drawings and dimensions of
the processor. Table 4-1 and Table 4-2 provide additional details on the package
dimensions. The main components of processor package are identified in Figure 4-2. All
specified package dimensions are in millimeters.
Figure 4-1 illustrates key package mechanical features. These features enable package
integration with socket, power pod, and cooling solution.
• Vcore, Vcache, Vfixed, GND, and VID Pads: Contact pads for delivering power
and I/O signals from the voltage regulator to the processor through its substrate.
• Socket Alignment Keyways: They define package position in X and Y direction
with respect to socket for proper alignment of package pins to socket contact holes.
• Pin Shroud Alignment Keyways: They define pin shroud position in X and Y
direction with respect to processor.
• Pin 1 Indicators: Identifies package orientation with respect to socket and
motherboard.
• Integrated Heat Spreader (IHS): Enhances dissipation of heat generated by the
processor. Provides interface surface between processor and cooling solution.
• Substrate: Processor mechanical and electrical integration vehicle with the
motherboard and processor enabling components.
• Pin Field (Grid): 28 x 25 partially-filled pin field for transmitting signals to and
from processor to motherboard.
• Voltage Regulator Connector Back Plate Keyway: It defines the VR connector
back plate position in X and Y direction with respect to the processor.
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
65
Mechanical Specifications
Figure 4-1. Processor Package
G1
H1
AH1
A1
H2
G2
J2
A25
AH25
Side View
J1
Bottom View
B1
B
C1
C2
B2
A1
Package
IHS
L
A
C
C
L
D1
Top View
A
Front View
001349
®
®
66
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Mechanical Specifications
Table 4-1.
Processor Package Dimensions
Figure 4-2. Package Height and Pin Dimensions
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
67
Mechanical Specifications
Table 4-2.
Processor Package Mechanical Interface Dimensions
®
®
68
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Mechanical Specifications
Figure 4-3. Processor Package Mechanical Interface Dimensions
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
69
Mechanical Specifications
Figure 4-4. Processor Package Top-Side Components Height Dimensions
Note: Keepout zones indicate no components will be on the processor package.
Figure 4-5. Processor Package Bottom-Side Components Height Dimensions
Note: Keepout zones indicate no components will be on the processor package.
®
®
70
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Mechanical Specifications
4.1.1
Voltage Regulator (MVR) to Processor Package Interface
Critical package mechanical requirements at its interface with the MVR are identified in
Figure 4-6 and Table 4-3. The processor interface boundary conditions with which MVR
must comply during and after installation are outlined in Table 4-3. These requirements
are intended to minimize potential damage to the processor that may result from
installation of the MVR.
Figure 4-6. Processor to MVR Interface Loads
Y
Processor Heatsink
TZ
X
Z
P-z
Processor Heatsink
IHS
Ty
90
Substrate
X
A
Socket
Mother Board
P+z
Table 4-3.
Processor Package Load Limits at Power Tab (Sheet 1 of 2)
1
Parameter
Description
Value
Comments
A
Final position of the package at the
power tab (unloaded) with respect to
system board
3.8+/-
0.1mm
Position of the processor power tab is
based on the height of the mPGA700
ZIF socket height from the mother
post SMT
P
d
Allowable load on the package in +z
and -z direction
22.25N max
Allowable displacement at the
processor power tab in z direction
under load P
+/- 0.3 mm
max
Tz
Allowable torque on the package tip in
z axis
0
Package loading in Y direction is not
allowed. Hence, zero torque in Z-axis
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
71
Mechanical Specifications
Table 4-3.
Processor Package Load Limits at Power Tab (Sheet 2 of 2)
1
Parameter
Description
Value
Comments
Tx
Allowable torque at the package power 0.57Nm max
tab in X axis
T+y
Allowable torque at the package power 1.24 Nm max Torque on the package edge in +Y
tab in +y direction
direction is determined by the load
applied in -Z and the distance from the
edge the package to the socket.
Torque on the package edge in -Y
direction is determined by the load
applied in +Z and the distance from
the edge the package to the heatsink
base.
Allowable torque at the package power
tab in -y direction
0.93Nm
max
T-y
To determine T+y, distance from the
edge the package to the socket of
55.7mm is applied
To determine T-y, distance from the
edge the package to the heatsink
pedestal of 42mm is applied
Notes:
1. Load determination done with 100-lb. load on the processor heatsink.
4.2
Package Marking
The following section details the processor top-side and bottom-side markings for
engineering samples and production units. This is provided to aid in identification.
Specific details regarding individual fields in the product markings will be furnished in a
future release of this document.
4.2.1
Processor Top-Side Marking
The top-side mark is a laser marking on the IHS. Figure 4-7 shows the general location
of the processor top-side mark that provides the following information:
• Intel ®
• Itanium® Processor Family Legal Mark
• Assembly Process Order (APO) Number
• Unit Serial Number
• 2D Matrix Mark
®
®
72
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Mechanical Specifications
Figure 4-7. Processor Top-Side Marking on IHS
4.2.2
Processor Bottom-Side Marking
The processor bottom-side mark for the product is a laser marking on the pin side of
the interposer. Figure 4-8 shows the placement of the laser marking on the pin side of
interposer. The processor bottom-side mark provides the following information:
• Product ID
• S-Spec
• Finish Process Order (FPO)
• 2D Matrix Mark
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
73
Mechanical Specifications
Figure 4-8. Processor Bottom-Side Marking Placement on Interposer
Laser Marking
2D Matrix Mark (see notes)
§
®
®
74
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Thermal Specifications
5 Thermal Specifications
This chapter provides a description of the thermal features relating to the Dual-Core
Intel Itanium processor 9000 and 9100 series.
5.1
Thermal Features
The processor has an internal thermal circuit which senses when a certain temperature
is reached on the processor core. This circuit is used for controlling various thermal
states. In addition, an on-chip thermal diode is available for use by the thermal sensing
device on the processor. Figure 5-1 shows the relationship between temperature, time,
and the thermal alert, enhanced thermal management (ETM), and thermal trip points.
Note:
Figure 5-1 is not intended to show a linear relationship in time or temperature as a
processor's thermal state advances from one state to the next state when the cooling
solution fails to control the processor temperature, as this is affected by many factors
such as cooling solution performance degradation and processor workload variations.
Figure 5-1. Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Thermal Features
Thermal Trip
ETM
Thermal Alert
Time
000653b
5.1.1
Thermal Alert
THRMALERT# is a programmable thermal alert signal which is part of the processor
system management feature. THRMALERT# is asserted when the measured
temperature from the processor thermal diode equals or exceeds the temperature
threshold data programmed in the high temp (THIGH) or low temp (TLOW) registers on
the sensor. Intel recommends using the upper temperature reference byte listed in the
Processor Information ROM when programming the THIGH register (see Chapter 6 for
more details). This signal can be used by the platform to implement thermal regulation
features such as generating an external interrupt to tell the operating system that the
processor core die temperature is increasing.
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
75
Thermal Specifications
5.1.2
Enhanced Thermal Management
ETM is a power and thermal protection feature. On the Dual-Core Intel Itanium
processor 9000 and 9100 series, ETM uses power and thermal sensing devices on the
die to monitor entry points, indicating dangerous operation exceeding the thermal or
power specification. Once the sensing devices observe the temperature rising above
the power or thermal entry point, the processor will enter a low power mode of
execution and notify the system by sending a Correctable Machine Check Interrupt
(CMCI). The processor will remain in this low power mode until the power and
temperature decrease below the entry points and remain there for approximately one
second, at which point it will send another CMCI and resume normal operation. If the
power and temperature cannot be reduced, and continue to rise to critical levels, the
processor will assert Power Trip or Thermal Trip. The ETM feature may be disabled
through the PAL.
5.1.3
Power Trip
The Dual-Core Intel Itanium processor 9000 and 9100 series protects itself and the
MVR from catastrophic over power by use of an internal power sensor. The sensor trip
point is set above the normal operating power to ensure that there are no false trips.
The processor will signal a continuable MCA when the power draw exceeds a safe
operating level.
Warning:
Data will be lost if the MVR overheats and shuts down as a result of an extended over
power condition.
Once power trip is activated, the processor can continue operation, but may continue to
signal continuable MCAs as long as the over power condition exists.
5.1.4
Thermal Trip
The Dual-Core Intel Itanium processor 9000 and 9100 series protects itself from
catastrophic overheating by use of an internal thermal sensor. The sensor trip point is
set well above the normal operating temperature to ensure that there are no false trips.
The processor will stop all execution when the junction temperature exceeds a safe
operating level.
Warning:
Data will be lost if the processor goes into thermal trip (signaled to the system by the
THRMTRIP# pin).
Once thermal trip is activated, the processor remains stopped until RESET# is asserted.
The processor case temperature must drop below the specified maximum before
issuing a reset to the processor. Please see Section 5.2 for details on case temperature.
5.2
Case Temperature
See Table 5-1 for the case temperature specifications for the Dual-Core Intel Itanium
processor 9000 and 9100 series. The case temperature is defined as the temperature
measured at the center of the top surface of the IHS.
Warning:
Data may be lost if the case temperature exceeds the specified maximum.
®
®
76
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Thermal Specifications
Table 5-1.
Case Temperature Specification
Core
Frequency
Symbol
Parameter
Minimum
Maximum
Unit
Notes
Tcase
Case Temperature
1.6GHz/24MB
1.6GHz/18MB
1.6GHz/9MB
1.42GHz/12MB
1.4GHz/12MB
1.6GHz/6MB
5
5
5
5
5
5
76
76
76
76
76
74
°C
°C
°C
°C
°C
°C
Figure 5-2 contains dimensions for the thermocouple location on the processor
package. This is the recommended location for placement of a thermocouple for case
temperature measurement.
Figure 5-2. Itanium® Processor Package Thermocouple Location
24.13
45.00
Thermocouple Location
All dimensions are measured in mm. Not to scale.
001103a
§
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
77
Thermal Specifications
®
®
78
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
System Management Feature Specifications
6 System Management Feature
Specifications
The Dual-Core Intel Itanium processor 9000 and 9100 series includes a system
management bus (SMBus) interface. This chapter describes the features of the SMBus
and SMBus components.
6.1
System Management Bus
6.1.1
System Management Bus Interface
The processor includes an Itanium processor family SMBus interface which allows
access to several processor features. The system management components on the
processor include two memory components (EEPROMs) and a thermal sensing device
(digital thermometer). The processor information EEPROM (PIROM) is programmed by
Intel with manufacturing and feature information specific to the Dual-Core Intel
Itanium processor 9000 and 9100 series. This information is permanently write-
protected. Section 6.2 provides details on the PIROM. The other EEPROM is a scratch
EEPROM that is available for other data at the system vendor’s discretion. The thermal
sensor can be used in conjunction with the information in the PIROM and/or the Scratch
EEPROM for system thermal monitoring and management. The thermal sensing device
on the processor provides an accurate means of acquiring an indicator of the junction
temperature of the processor core die. The thermal sensing device is connected to the
anode and cathode of the processor on-die thermal diode. SMBus implementation on
the processor uses the clock and data signals as defined by SMBus specifications.
6.1.2
System Management Interface Signals
Table 6-1 lists the system management interface signals and their descriptions. These
signals are used by the system to access the system management components via the
SMBus.
Table 6-1.
System Management Interface Signal Descriptions
Signal Name
3.3V
Pin Count
Description
1
3
1
1
1
1
Voltage supply for EEPROMs and thermal sensor.
Address select passed through from socket.
System management bus clock.
SMA[2:0]
SMSC
SMSD
System management serial address/data bus.
Scratch EEPROM write protect.
SMWP
THRMALERT#
Temperature alert from the thermal sensor.
Figure 6-1 shows the logical schematics of SMBus circuitry on the processor and shows
how the various system management components are connected to the SMBus. The
reference to the System Board at the lower left corner of Figure 6-1 shows how SMBus
address configuration for multiple processors can be realized with resistor stuffing
options.
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
79
System Management Feature Specifications
Figure 6-1. Logical Schematic of SMBus Circuitry
Intel® Itanium® 2 Processor
3.3V
Core
THERMDA
THERMDC
10K
10K
10K
VCC
A0
A1
A2
SC
SD
Processor
Information
ROM
VCC
A0
STBY
SC
Thermal
Sensing
Device
A1
SD
10K
ALERT
VCC
A0
A1
A2
SC
SD
Scratch
EEPROM
10K
10K
WP
SMA0
SMA1
SMA2
SMWP
SMSD
SMSC
3.3V
THRMALERT#
3.3V
3.3V
10K
Stuffing
Options
System Board
System Board
NOTE:
1. Actual implementation may vary.
2. For use in general understanding of the architecture.
000668b
®
®
80
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
System Management Feature Specifications
6.1.3
SMBus Device Addressing
Of the addresses broadcast across the SMBus, the memory components claim those of
the form “1010XXYZb”. The “XX” and “Y” bits are used to enable the devices on the
processor at adjacent addresses. The Y bit is hard-wired on the processor to GND (‘0’)
for the Scratch EEPROM and pulled to 3.3 V (‘1’) for the processor information ROM.
The “XX” bits are defined by the processor socket via the SMA0 and SMA1 pins on the
processor connector. These address pins have a weak pull-down (10 kΩ) to ensure that
the memory components are in a known state in systems which do not support the
SMBus, or only support a partial implementation. The “Z” bit is the read/write bit for
the serial bus transaction.
The thermal sensing device internally decodes one of three upper address patterns
from the bus of the form “0011XXXZb”, “1001XXXZb” or “0101XXXZb”. The device’s
addressing, as implemented, uses SMA2 and SMA1 and includes a Hi-Z state for the
SMA2 address pin. Therefore, the thermal sensing device supports six unique resulting
addresses. To set the Hi-Z state for SMA2, the pin must be left floating. The system
should drive SMA1 and SMA0, and will be pulled low (if not driven) by the 10 kΩ pull-
down resistor on the processor substrate. Attempting to drive either of these signals to
a Hi-Z state would cause ambiguity in the memory device address decode, possibly
resulting in the devices not responding, thus timing out or hanging the SMBus. As
before, the “Z” bit is the read/write bit for the serial bus transaction.
Figure 6-1 shows a logical diagram of the pin connections. Table 6-2 and Table 6-3
describe the address pin connections and how they affect the addressing of the
devices.
Note:
Addresses of the form “0000XXXXb” are Reserved and should not be generated by an
SMBus master. Also, system management software must be aware of the processor
select in the address for the thermal sensing device.
Table 6-2.
Thermal Sensing Device SMBus Addressing on the Dual-Core Intel® Itanium®
Processor 9000 and 9100 series
1
Address (Hex)
Upper Address
Processor Select
8-Bit Address Word on Serial Bus
b[7:0]
SMA2
SMA1
3Xh
5Xh
9Xh
0011
0011
0101
0101
1001
1001
0
0
0
1
0
1
0
1
0011000Xb
0011010Xb
0101001Xb
0101011Xb
1001100Xb
1001110Xb
2
Z
b
Z
1
1
Notes:
1. Upper address bits are decoded in conjunction with the select pins.
2. A tri-state or “Z” state on this pin is achieved by leaving this pin unconnected.
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
81
System Management Feature Specifications
Table 6-3.
EEPROM SMBus Addressing on the Dual-Core Intel® Itanium® Processor 9000
and 9100 Series
Memory
Device
Select
Upper
Address
Read/
Write
Processor Select
1
Address
(Hex)
Device Addressed
(SMA1)
Bit 3
(SMA0)
Bit 2
Bits 7–4
Bit 1
Bit 0
A0h/A1h
A2h/A3h
A4h/A5h
A6h/A7h
A8h/A9h
AAh/ABh
ACh/ADh
AEh/AFh
Notes:
1010
1010
1010
1010
1010
1010
1010
1010
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
Scratch EEPROM 1
Processor Information ROM 1
Scratch EEPROM 2
Processor Information ROM 2
Scratch EEPROM 3
Processor Information ROM 3
Scratch EEPROM 4
Processor Information ROM 4
1. Although this addressing scheme is targeted for up to four-way MP systems, more processors can be supported
by using a multiplexed (or separate) SMBus implementation.
6.2
Processor Information ROM
An electrically programmed read-only memory (ROM) provides information about the
processor. The checksum bits for each category provide error correction and serve as a
mechanism to check whether data is corrupted or not. This information is permanently
write-protected. Table 6-4 shows the data fields and formats provided in the memory.
Note:
The data, in byte format, is written and read serially, with the most significant bit first.
Table 6-4.
Processor Information ROM Format (Sheet 1 of 3)
Offset/
Section
# of
Bits
Function
Notes
Examples
Header
00h
01h
8
Data Format Revision
EEPROM Size
Two 4-bit hex digits
Start with 00h
16
Size in bytes (MSB first)
Use a decimal to hex
transfer; 128 bytes =
0080h:
•
•
•
•
02h[7:4] = 0000
02h[3:0] = 0000
01h[7:4] = 1000
01h[3:0] = 0000
03h
04h
05h
06h
07h
08h
8
8
8
8
8
8
Processor Data Address
Processor Core Address
Processor Cache Address
Processor Data Address
Part Number Data Address
Byte pointer, 00h if not present
Byte pointer, 00h if not present
Byte pointer, 00h if not present
Byte pointer, 00h if not present
Byte pointer, 00h if not present
Byte pointer, 00h if not present
0Eh
17h
28h
37h
3Eh
63h
Thermal Reference Data
Address
09h
0Ah
8
8
Feature Data Address
Other Data Address
Byte pointer, 00h if not present
Byte pointer, 00h if not present
67h
7Ah
®
®
82
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
System Management Feature Specifications
Table 6-4.
Processor Information ROM Format (Sheet 2 of 3)
Offset/
Section
# of
Bits
Function
Notes
Examples
0Bh
16
8
Reserved
Reserved for future use
1 byte checksum
0000h
0Dh
Checksum
Add up by byte and take
2’s complement.
Processor
0Eh
48
S-spec Number
Six 8-bit ASCII characters
S-spec number of S123
would be:
•
•
•
•
•
•
13h = 00h
12h = 00h
11h = “3”
10h = “2”
0Fh = “1”
0Eh = “S”
14h
15h
16h
2
8
8
Sample/Production
Reserved
00b = Sample only (MSB First)
Reserved for future use
1 byte checksum
00000001b = Production
00h
Checksum
Add up by byte and take
2’s complement.
Core
1
17h
8
8
8
8
Architecture Revision
Processor Core Family
Processor Core Model
Processor Core Stepping
From CPUID
Taken from
CPUID[3].archrev.
18h
19h
1Ah
From CPUID
From CPUID
From CPUID
Taken from
CPUID[3].family.
Taken from
CPUID[3].model.
Taken from
CPUID[3].revision.
1Bh
1Eh
20h
24
16
12
Reserved
Reserved for future use
000000h
2
Maximum Core Frequency
Four 4-bit hex digits (in MHz)
Three 4-bit hex digits (in MHz)
1 GHz = 1000h
1
Maximum System Bus
Frequency
200 MHz = 200h
1
22h
24h
25h
16
8
Core Voltage ID
Voltage in four 4-bit hex digits
(in mV)
1500 mV = 1500h
1
Core Voltage Tolerance, High Edge finger tolerance in mV, +
two 4-bit hex digits
1.5% = 22 mV = 22h
1
8
Core Voltage Tolerance, Low
Edge finger tolerance in mV, –
two 4-bit hex digits
1.5% = 22 mV = 22h
26h
27h
8
8
Reserved
Reserved for future use
1 byte checksum
00h
Checksum
Add up by byte and take
2’s complement.
Cache
28h
2Ch
2Eh
36h
32
16
64
8
Reserved
Cache Size
Reserved
Checksum
Reserved for future use
Four 4-bit hex digits (in Kbytes)
Reserved for future use
1 byte checksum
00000000h
1,3
3072 Kbytes = 3072h
x0h
Package
37h
32
Package Revision
Four 8-bit ASCII characters
NE:
•
•
•
•
37h = N
38h = E
39h = 0
3Ah = 0
3Bh
2
Substrate Revision Software
ID
2-bit revision number
00
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
83
System Management Feature Specifications
Table 6-4.
Processor Information ROM Format (Sheet 3 of 3)
Offset/
Section
# of
Bits
Function
Notes
Examples
3Ch
3Dh
8
8
Reserved
Reserved for future use
1 byte checksum
00h
Checksum
Add up by byte and take
2’s complement
Part Numbers
3Eh 56
Processor Part Number
Seven 8-bit ASCII characters
80549KC
•
•
•
•
•
•
•
3Eh = “8”
3Fh = “0”
40h = “5”
41h = “4”
42h = “2”
43h = “K”
44h = “C”
45h
64
Processor Electronic
Signature
64-bit identification number
May have padded zeros
4Dh
62h
168
8
Reserved
Reserved for future use
1 byte checksum
x0h
Checksum
Add up by byte and take
2’s complement
Thermal Reference
63h
64h
8
8
Upper Temp Reference Byte
Hex value of thermal upper temp Default = 92 = 5Ch
limit
Thermal Calibration Offset
Byte Present
Number of degrees in error (±)
will be set per
part and expected to be
~ +12C
65h
66h
8
8
Reserved
Reserved for future use
1 byte checksum
00h
Checksum
Add up by byte and take
2’s complement.
Features
67h
32
64
IA-32 Processor Core
Feature Flags
From 32 bit CPUID
4387FBFFh
6Bh
73h
Reserved
Reserved (Processor core feature 0000 0000 6380 811Bh
flags implemented in the
®
Itanium processor family)
32
Processor Feature Flags
All others are reserved:
[9] = Demand Based Switching
Enabled
1 indicates EEPROM data
for specified field is valid.
[8] = Core Level Lockstep
Enabled
[7] = Socket Level Lockstep
Enabled
[6] = Dual Core Enabled
[5] = Hyper-Threading Enabled
[4] = Upper temp reference byte
[3] = Thermal calibration offset
byte present
[2] = Scratch EERPOM present
[1] = Core VID Present
77h
4
Number of Devices in TAP
Chain
One 4-bit hex digit
2h for dual-core
processor
78h
79h
4
8
Reserved
Reserved for future use
1 byte checksum
0h
Checksum
Add up by byte and take
2’s complement.
Other
7Ah
16
Reserved
Reserved for future use
0000h
®
®
84
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
System Management Feature Specifications
Notes:
1. Refer to the Intel® Itanium™ Architecture Software Developer’s Manual for details on CPUID registers.
2. The translation is using BCD.
3. Itanium 9000 and 9100 series use a hex-to-decimal conversion
6.3
6.4
Scratch EEPROM
Also available on the SMBus interface on the processor is an EEPROM which may be
used for other data at the system vendor’s discretion (Intel will not be using the scratch
EEPROM). The data in this EEPROM, once programmed, can be write-protected by
asserting the active-high SMWP signal. This signal has a weak pull-down (10 kΩ) to
allow the EEPROM to be programmed in systems with no implementation of this signal.
Processor Information ROM and Scratch EEPROM
Supported SMBus Transactions
The processor information ROM and scratch EEPROM responds to three of the SMBus
packet types: current address read, random address read, and sequential read.
Table 6-5 shows the format of the current address read SMBus packet. The internal
address counter keeps track of the address accessed during the last read or write
operation, incremented by one. Address “roll over” during reads is from the last byte of
the last eight byte page to the first byte of the first page. “Roll over” during writes is
from the last byte of the current eight byte page to the first byte of the same page.
Table 6-6 shows the format of the random read SMBus packet. The write with no data
loads the address desired to be read. Sequential reads may begin with a current
address read or a random address read. After the SMBus host controller receives the
data word, it responds with an acknowledge. This will continue until the SMBus host
controller responds with a negative acknowledge and a stop.
Table 6-7 shows the format of the byte write SMBus packet. The page write operates
the same way as the byte write, except that the SMBus host controller does not send a
stop after the first data byte and acknowledge. The Scratch EEPROM internally
increments its address. The SMBus host controller continues to transmit data bytes
until it terminates the sequence with a stop. All data bytes will result in an acknowledge
from the Scratch EEPROM. If more than eight bytes are written, the internal address
will “roll over” and the previous data will be overwritten.
In Table 6-5 through Table 6-7, ‘S’ represents the SMBus start bit, ‘P’ represents a stop
bit, ‘R’ represents a read, ‘W’ represents a write bit, ‘A’ represents an acknowledge, and
‘///’ represents a negative acknowledge. The shaded bits are transmitted by the
processor information ROM or Scratch EEPROM and the bits that are not shaded are
transmitted by the SMBus host controller. In the tables, the data addresses indicate
eight bits. The SMBus host controller should transmit eight bits, but as there are only
128 addresses, the most significant bit is a don’t care.
Table 6-5.
Current Address Read SMBus Packet
Device
Address
S
R
A
Data
///
P
1
7 bits
1
1
8 bits
1
1
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
85
System Management Feature Specifications
Table 6-6.
Table 6-7.
Random Address Read SMBus Packet
Device
Address
Data
Address
Device
S
W
A
A
S
R
A
Data
///
P
Address
1
7 bits
1
1
8 bits
1
1
7 bits
1
1
8 bits
1
1
Byte Write SMBus Packet
Device
Address
Data
Address
S
W
A
A
Data
A
P
1
7 bits
0
1
8 bits
1
8 bits
1
1
6.5
Thermal Sensing Device
The Dual-Core Intel Itanium processor 9000 and 9100 series thermal sensing device
provides a means of acquiring thermal data from the processor. The accuracy of the
thermal reading is expected to be better than ±5 °C. The thermal sensing device is
composed of control logic, SMBus interface logic, a precision analog to digital converter,
and a precision current source. The thermal sensing device drives a small current
through a thermal diode located on the processor core and measures the voltage
generated across the thermal diode by the current. With this information, the thermal
sensing device computes a byte of temperature data. Software running on the
processor or on a micro-controller can use the temperature data from the thermal
sensing device to thermally manage the system.
The thermal sensing device provides a register with a data byte (seven bits plus sign)
which contains a value corresponding to the sampled output of the thermal diode in the
processor core. The value of the byte read from the thermal sensor is always higher
than the actual processor core temperature; therefore, the offset from the reading
needs to be subtracted to obtain an accurate reading of the processor core
temperature. This data can be used in conjunction with the upper temperature
reference byte (provided in the Processor Information ROM) for thermal management
purposes. The temperature data from the thermal sensor can be read out digitally
using an SMBus read command (see Section 6.6). The thermal sensor detects when
SMBus power is applied to the processor, and resets itself at power-up.
The thermal sensing device also contains alarm registers to store thermal reference
threshold data. These values can be individually programmed on the thermal sensor. If
the measured temperature equals or exceeds the alarm threshold value, the
appropriate bit is set in the thermal sensing device status register, which is also
brought out to the processor system bus via the THRMALERT# signal (see
Section 6.1.1 for more details). At power-up, the appropriate alarm register values
need to be programmed into the thermal sensing device via the SMBus. It is
recommended that the upper thermal reference threshold byte (provided in the
processor information ROM) be used for setting the upper threshold value in the alarm
register. To account for the offset inherent in the thermal sensing device reading, the
actual programmed value of the upper threshold value in the alarm register should be
the sum of the upper thermal reference threshold byte and the thermal calibration
offset byte (both provided in the PIROM).
When polling the thermal sensing device on the processor to read the processor
temperatures, it is recommended that the polling frequency be every 0.5 to 1 second.
®
®
86
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
System Management Feature Specifications
6.6
Thermal Sensing Device Supported SMBus
Transactions
The thermal sensing device responds to five of the SMBus packet types: write byte,
read byte, send byte, receive byte, and alert response address (ARA). The send byte
packet is used for sending one-shot commands only. The receive byte packet accesses
the register commanded by the last read byte packet. If a receive byte packet was
preceded by a write byte or send byte packet more recently than a read byte packet,
then the behavior is undefined. Table 6-8 through Table 6-12 diagram the five packet
types. In these tables, ‘S’ represents the SMBus start bit, ‘P’ represents a stop bit, ‘Ack’
represents an acknowledge, and ‘///’ represents a negative acknowledge. The shaded
bits are transmitted by the thermal sensor and the unshaded bits are transmitted by
the SMBus host controller. Table 6-13 shows the encoding of the command byte.
Table 6-8.
Table 6-9.
Write Byte SMBus Packet
S
Address
Write
Ack
Command
Ack
Data
Ack
P
1
7 bits
1
1
8 bits
1
8 bits
1
1
Read Byte SMBus Packet
//
/
S
Address
Write
Ack
Command
Ack
S
Address
7 bits
Read
Ack
Data
P
1
7 bits
0
1
8 bits
1
1
1
1
8 bits
1
1
Table 6-10. Send Byte SMBus Packet
S
Address
Write
Ack
Command
Ack
P
1
7 bits
1
1
8 bits
1
Table 6-11. Receive Byte SMBus Packet
S
Address
Read
Ack
Data
///
P
1
7 bits
1
1
8 bits
1
1
Table 6-12. ARA SMBus Packet
S
ARA
Read
Ack
Address
///
P
1
0001 100
1
1
1001 1011
1
1
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
87
System Management Feature Specifications
Table 6-13. Command Byte Bit Assignment
Register
Command
Reset State
Function
RESERVED
RRT
00h
01h
N/A
N/A
Reserved for future use.
Read processor core thermal data.
Read status byte (flags, busy signal).
Read configuration byte.
RS
02h
N/A
RC
03h
0000 0000
0000 0010
0111 1111
1100 1001
0111 1111
1100 1001
N/A
RCR
04h
Read conversion rate byte.
Reserved for future use.
RESERVED
RESERVED
RRHL
05h
06h
Reserved for future use.
07h
Read processor core thermal diode T
Read processor core thermal diode T
Write configuration byte.
limit.
limit.
HIGH
LOW
RRLL
08h
WC
09h
WCR
0Ah
N/A
Write conversion rate byte.
Reserved for future use.
RESERVED
RESERVED
WRHL
0Bh
N/A
0Ch
N/A
Reserved for future use.
0Dh
0Eh
N/A
Write processor core thermal diode T
Write processor core thermal diode T
limit.
limit.
HIGH
LOW
WRLL
N/A
OSHT
0Fh
N/A
One shot command (use send byte packet).
Reserved for future use.
RESERVED
10h – FFh
N/A
All of the commands are for reading or writing registers in the thermal sensor except
the one-shot command (OSHT). The one-shot command forces the immediate start of
a new voltage-to-temperature conversion cycle. If a conversion is in progress when the
one-shot command is received, then the command is ignored. If the thermal sensing
device is in standby mode when the one-shot command is received, a conversion is
performed and the sensor returns to standby mode. If the thermal sensor is in auto-
convert mode and is between conversions, then the conversion rate timer resets, and
the next automatic conversion takes place after a full delay elapses. Please refer to
Section 6.7.4 for further detail on standby and auto-convert modes.
The default command after reset is the reserved value (00h). After reset, receive byte
packets will return invalid data until another command is sent to the thermal sensing
device.
6.7
Thermal Sensing Device Registers
The system management software can configure and control the thermal sensor by
writing to and interacting with different registers in the thermal sensor. These registers
include a thermal reference register, two thermal limit registers, a status register, a
configuration register, a conversion rate register, and other reserved registers. The
following subsections describe the registers in detail.
6.7.1
Thermal Reference Registers
The processor core and thermal sensing device internal thermal reference registers
contain the thermal reference value of the thermal sensing device and the processor
core thermal diodes. This value ranges from +127 to –128 decimal and is expressed as
a two’s complement, eight-bit number. These registers are saturating, that is, values
above 127 are represented at 127 decimal, and values below –128 are represented as
–128 decimal.
®
®
88
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
System Management Feature Specifications
6.7.2
6.7.3
Thermal Limit Registers
The thermal sensing device has two thermal limit registers; they define high and low
limits for the processor core thermal diode. The encoding for these registers is the
same as for the thermal reference registers. If the diode thermal value equals or
exceeds one of its limits, then its alarm bit in the status register is triggered. This
indication is also brought out to the processor system bus via the THRMALERT# signal.
Status Register
The status register shown in Table 6-14 indicates which (if any) of the thermal value
thresholds have been exceeded. It also indicates if a conversion is in progress or if an
open circuit has been detected in the processor core thermal diode connection. Once
set, alarm bits stay set until they are cleared by a status register read. A successful
read to the status register will clear any alarm bits that may have been set, unless the
alarm condition persists. Note that the THRMALERT# interrupt signal is latched and is
not automatically cleared when the status flag bit is cleared. The latch is cleared by
sending the Alert Response Address (0001100) on the SMBus.
Table 6-14. Thermal Sensing Device Status Register
Bit
Name
Function
7 (MSB) BUSY
A one indicates that the device’s analog to digital converter is busy converting.
Reserved for future use.
6
5
4
RESERVED
RESERVED
RHIGH
Reserved for future use.
A one indicates that the processor core thermal diode high temperature alarm has
been activated.
3
RLOW
A one indicates that the processor core thermal diode low temperature alarm has
been activated.
2
OPEN
A one indicates an open fault in the connection to the processor core diode.
Reserved for future use.
1
RESERVED
RESERVED
0 (LSB)
Reserved for future use.
6.7.4
Configuration Register
The configuration register controls the operating mode (standby vs. auto-convert) of
the thermal sensing device. Table 6-15 shows the format of the configuration register.
If the RUN/STOP bit is set (high) then the thermal sensing device immediately stops
converting and enters standby mode. The thermal sensing device will still perform
analog-to-digital conversions in standby mode when it receives a one-shot command.
If the RUN/STOP bit is clear (low) then the thermal sensor enters auto-conversion
mode. The thermal sensing device starts operating in free running mode, auto-
converting at 0.25 Hz after power-up.
Table 6-15. Thermal Sensing Device Configuration Register
Reset
State
Bit
Name
Function
7 (MSB)
6
RESERVED
RUN/STOP
0
0
Reserved for future use.
Standby mode control bit. If high, the device immediately stops
converting, and enters standby mode. If low, the device converts in
either one-shot or timer mode.
5–0
RESERVED
0
Reserved for future use.
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
89
System Management Feature Specifications
6.7.5
Conversion Rate Register
The contents of the conversion rate register determine the nominal rate at which
analog-to-digital conversions happen when the thermal sensing device is in auto-
convert mode. Table 6-16 shows the mapping between conversion rate register values
and the conversion rate. As indicated in Table 6-16, the conversion rate register is set
to its default state of 02h (0.25 Hz nominally) when the thermal sensing device is
powered-up. There is a ±25% error tolerance between the conversion rate indicated in
the conversion rate register and the actual conversion rate.
Table 6-16. Thermal Sensing Device Conversion Rate Register
Register Contents
Conversion Rate (Hz)
00h
01h
0.0625
0.125
02h
0.25
03h
0.5
04h
1
05h
2
06h
4
07h
8
08h to FFh
Reserved for future use
§
®
®
90
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Signals Reference
A Signals Reference
This appendix provides an alphabetical listing of all Dual-Core Intel Itanium 9000 and
9100 series processor system bus signals. The tables at the end of this appendix
summarize the signals by direction: output, input, and I/O.
For a complete pinout listing including processor specific pins, please refer to
Chapter 3, “Pinout Specifications.”
A.1
Alphabetical Signals Reference
A.1.1
A[49:3]# (I/O)
The Address (A[49:3]#) signals, with byte enables, define a 250 Byte physical memory
address space. When ADS# is active, these pins transmit the address of a transaction.
These pins are also used to transmit other transaction related information such as
transaction identifiers and external functions in the cycle following ADS# assertion.
These signals must connect the appropriate pins of all agents on the processor system
bus. The A[49:27]# signals are parity-protected by the AP1# parity signal, and the
A[26:3]# signals are parity-protected by the AP0# parity signal.
On the active-to-inactive transition of RESET#, the processors sample the A[49:3]#
pins to determine their power-on configuration.
A.1.2
A.1.3
A20M# (I)
A20M# is no connect and is ignored in the processor system environment.
ADS# (I/O)
The Address Strobe (ADS#) signal is asserted to indicate the validity of the transaction
address on the A[49:3]#, REQ[5:0]#, AP[1:0]# and RP#pins. All bus agents observe
the ADS# activation to begin parity checking, protocol checking, address decode,
internal snoop, or deferred reply ID match operations associated with the new
transaction.
A.1.4
A.1.5
AP[1:0]# (I/O)
The Address Parity (AP[1:0]#) signals can be driven by the request initiator along with
ADS# and A[49:3]#. AP[1]# covers A[49:27]#, and AP[0]# covers A[26:3]#. A
correct parity signal is high if an even number of covered signals are low and low if an
odd number of covered signals are low. This allows parity to be high when all the
covered signals are high.
ASZ[1:0]# (I/O)
The ASZ[1:0]# signals are the memory address-space size signals. They are driven by
the request initiator during the first Request Phase clock on the REQa[4:3]# pins. The
ASZ[1:0]# signals are valid only when REQa[2:1]# signals equal 01B, 10B, or 11B,
indicating a memory access transaction. The ASZ[1:0]# decode is defined in Table A-1.
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
91
Signals Reference
Table A-1.
Address Space Size
Memory Address
Space
Memory Access
Range
ASZ[1:0]#
0
0
1
0
1
0
Reserved
36-bit
Reserved
0 to (64 GByte - 1)
50-bit
64 GByte to
(1 Pbyte –1)
1
1
Reserved
Reserved
Any memory access transaction addressing a memory region that is less than 64 GB
(that is, Aa[49:36]# are all zeroes) must set ASZ[1:0]# to 01. Any memory access
transaction addressing a memory region that is equal to or greater than 64 GB (that is,
Aa[49:36]# are not all zeroes) must set ASZ[1:0]# to 10. All observing bus agents
that support the 64 GByte (36-bit) address space must respond to the transaction
when ASZ[1:0]# equals 01. All observing bus agents that support larger than the 64
GByte (36-bit) address space must respond to the transaction when ASZ[1:0]# equals
01 or 10.
A.1.6
ATTR[3:0]# (I/O)
The ATTR[3:0]# signals are the attribute signals. They are driven by the request
initiator during the second clock of the Request Phase on the Ab[35:32]# pins. The
ATTR[3:0]# signals are valid for all transactions. The ATTR[3]# signal is reserved. The
ATTR[2:0]# are driven based on the memory type. Please refer to Table A-2.
Table A-2.
Effective Memory Type Signal Encoding
ATTR[2:0]#
Description
000
100
101
110
111
Uncacheable
Write Coalescing
Write-Through
Write-Protect
Writeback
A.1.7
A.1.8
92
BCLKp/BCLKn (I)
The BCLKp and BCLKn differential clock signals determine the bus frequency. All agents
drive their outputs and latch their inputs on the differential crossing of BCLKp and
BCLKn on the signals that are using the common clock latched protocol.
BCLKp and BCLKn indirectly determine the internal clock frequency of the processor.
Each processor derives its internal clock by multiplying the BCLKp and BCLKn
frequency by a ratio that is defined and allowed by the power-on configuration.
BE[7:0]# (I/O)
The BE[7:0]# signals are the byte-enable signals for partial transactions. They are
driven by the request initiator during the second Request Phase clock on the Ab[15:8]#
pins.
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Signals Reference
For memory or I/O transactions, the byte-enable signals indicate that valid data is
requested or being transferred on the corresponding byte on the 128-bit data bus.
BE[0]# indicates that the least significant byte is valid, and BE[7]# indicates that the
most significant byte is valid. Since BE[7:0]# specifies the validity of only 8 bytes on
the 16 byte wide bus, A[3]# is used to determine which half of the data bus is validated
by BE[7:0]#.
For special transactions ((REQa[5:0]# = 001000B) and (REQb[1:0]# = 01B)), the
BE[7:0]# signals carry special cycle encodings as defined in Table A-3. All other
encodings are reserved.
Table A-3.
Special Transaction Encoding on Byte Enables
Special Transaction
Byte Enables[7:0]#
NOP
0000 0000
0000 0001
0000 0010
0000 0011
0000 0100
0000 0101
0000 0110
0000 0111
0000 1000
Shutdown
Flush (INVD)
Halt
Sync (WBINVD)
Reserved
StopGrant Acknowledge
Reserved
xTPR Update
For Deferred Reply transactions, BE[7:0]# signals are reserved. The Defer Phase
transfer length is always the same length as that specified in the Request Phase except
the Bus Invalidate Line (BIL) transaction.
A BIL transaction may return one cache line (128 bytes).
A.1.9
BERR# (I/O)
The Bus Error (BERR#) signal can be asserted to indicate a recoverable error with
global MCA. BERR# assertion conditions are configurable at the system level.
Configuration options enable BERR# to be driven as follows:
• Asserted by the requesting agent of a bus transaction after it observes an internal
error.
• Asserted by any bus agent when it observes an error in a bus transaction.
When the bus agent samples an asserted BERR# signal and BERR# sampling is
enabled, the processor enters a Machine Check Handler.
BERR# is a wired-OR signal to allow multiple bus agents to drive it at the same time.
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
93
Signals Reference
A.1.10
BINIT# (I/O)
If enabled by configuration, the Bus Initialization (BINIT#) signal is asserted to signal
any bus condition that prevents reliable future operation.
If BINIT# observation is enabled during power-on configuration, and BINIT# is
sampled asserted, all bus state machines are reset. All agents reset their rotating IDs
for bus arbitration to the same state as that after reset, and internal count information
is lost. The L2 and L3 caches are not affected.
If BINIT# observation is disabled during power-on configuration, BINIT# is ignored by
all bus agents with the exception of the priority agent. The priority agent must handle
the error in a manner that is appropriate to the system architecture.
BINIT# is a wired-OR signal.
A.1.11
BNR# (I/O)
The Block Next Request (BNR#) signal is used to assert a bus stall by any bus agent
that is unable to accept new bus transactions to avoid an internal transaction queue
overflow. During a bus stall, the current bus owner cannot issue any new transactions.
Since multiple agents might need to request a bus stall at the same time, BNR# is a
wired-OR signal. In order to avoid wired-OR glitches associated with simultaneous edge
transitions driven by multiple drivers, BNR# is asserted and sampled on specific clock
edges.
A.1.12
A.1.13
BPM[5:0]# (I/O)
The BPM[5:0]# signals are system support signals used for inserting breakpoints and
for performance monitoring. They can be configured as outputs from the processor that
indicate programmable counters used for monitoring performance, or inputs from the
processor to indicate the status of breakpoints.
BPRI# (I)
The Bus Priority-agent Request (BPRI#) signal is used by the priority agent to arbitrate
for ownership of the system bus. Observing BPRI# asserted causes all other agents to
stop issuing new requests, unless such requests are part of an ongoing locked
operation.The priority agent keeps BPRI# asserted until all of its requests are
completed, then releases the bus by deasserting BPRI#.
A.1.14
BR[0]# (I/O) and BR[3:1]# (I)
BR[3:0]# are the physical bus request pins that drive the BREQ[3:0]# signals in the
system. The BREQ[3:0]# signals are interconnected in a rotating manner to individual
processor pins. Table A-4 and Table A-4 give the rotating interconnection between the
processor and bus signals for both the 4P and 2P system bus topologies.
®
®
94
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Signals Reference
Table A-4.
BR0# (I/O), BR1#, BR2#, BR3# Signals for 4P Rotating Interconnect
Bus Signal
Agent 0 Pins
Agent 1 Pins
Agent 2 Pins
Agent 3 Pins
BREQ[0]#
BREQ[1]#
BREQ[2]#
BREQ[3]#
BR[0]#
BR[1]#
BR[2]#
BR[3]#
BR[3]#
BR[0]#
BR[1]#
BR[2]#
BR[2]#
BR[3]#
BR[0]#
BR[1]#
BR[1]#
BR[2]#
BR[3]#
BR[0]#
Table A-5.
BR0# (I/O), BR1#, BR2#, BR3# Signals for 2P Rotating Interconnect
Bus Signal
Agent 0 Pins
Agent 3 Pins
BREQ[0]#
BREQ[1]#
BREQ[2]#
BREQ[3]#
BR[0]#
BR[1]#
BR[1]#
BR[0]#
Not Used
Not Used
Not Used
Not Used
During power-on configuration, the priority agent must assert the BR[0]# bus signal.
All symmetric agents sample their BR[3:0]# pins on asserted-to-deasserted transition
of RESET#. The pin on which the agent samples an asserted level determines its agent
ID. All agents then configure their pins to match the appropriate bus signal protocol as
shown in Table A-6.
Table A-6.
BR[3:0]# Signals and Agent IDs
Pin Sampled
Agent ID
Asserted on
RESET#
Arbitration ID
Reported
BR[0]#
BR[3]#
BR[2]#
BR[1]#
0
1
2
3
0
2
4
6
A.1.15
BREQ[3:0]# (I/O)
The BREQ[3:0]# signals are the symmetric agent arbitration bus signals (called bus
request). A symmetric agent n arbitrates for the bus by asserting its BREQn# signal.
Agent n drives BREQn# as an output and receives the remaining BREQ[3:0]# signals
as inputs.
The symmetric agents support distributed arbitration based on a round-robin
mechanism. The rotating ID is an internal state used by all symmetric agents to track
the agent with the lowest priority at the next arbitration event. At power-on, the
rotating ID is initialized to three, allowing agent 0 to be the highest priority symmetric
agent. After a new arbitration event, the rotating ID of all symmetric agents is updated
to the agent ID of the symmetric owner. This update gives the new symmetric owner
lowest priority in the next arbitration event.
A new arbitration event occurs either when a symmetric agent asserts its BREQn# on
an Idle bus (all BREQ[3:0]# previously deasserted), or the current symmetric owner
deasserts BREQn# to release the bus ownership to a new bus owner n. On a new
arbitration event, all symmetric agents simultaneously determine the new symmetric
owner using BREQ[3:0]# and the rotating ID. The symmetric owner can park on the
bus (hold the bus) provided that no other symmetric agent is requesting its use. The
symmetric owner parks by keeping its BREQn# signal asserted. On sampling BREQn#
asserted by another symmetric agent, the symmetric owner deasserts BREQn# as soon
as possible to release the bus. A symmetric owner stops issuing new requests that are
not part of an existing locked operation on observing BPRI# asserted.
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
95
Signals Reference
A symmetric agent can deassert BREQn# before it becomes a symmetric owner. A
symmetric agent can reassert BREQn# after keeping it deasserted for one clock.
A.1.16
CCL# (I/O)
CCL# is the Cache Cleanse signal. It is driven on the second clock of the Request Phase
on the EXF[2]#/Ab[5]# pin. CCL# is asserted for Memory Write transaction to indicate
that a modified line in a processor may be written to memory without being invalidated
in its caches.
A.1.17
A.1.18
CPUPRES# (O)
CPUPRES# can be used to detect the presence of a processor in a socket. A ground
indicates that a processor is installed, while an open indicates that a processor is not
installed.
D[127:0]# (I/O)
The Data (D[127:0]#) signals provide a 128-bit data path between various system bus
agents. Partial transfers require one data transfer clock with valid data on the byte(s)
indicated by asserted byte enables BE[7:0]# and A[3]#. Data signals that are not valid
for a particular transfer must still have correct ECC (if data bus error checking is
enabled). The data driver asserts DRDY# to indicate a valid data transfer.
A.1.19
A.1.20
D/C# (I/O)
The Data/Code (D/C#) signal is used to indicate data (1) or code (0) on REQa[1]#,
only during Memory Read transactions.
DBSY# (I/O)
The Data Bus Busy (DBSY#) signal is asserted by the agent that is responsible for
driving data on the system bus to indicate that the data bus is in use. The data bus is
released after DBSY# is deasserted.
DBSY# is replicated three times to enable partitioning of the data paths in the system
agents. This copy of the Data Bus Busy signal (DBSY#) is an input as well as an output.
A.1.21
A.1.22
A.1.23
DBSY_C1# (O)
DBSY# is a copy of the Data Bus Busy signal. This copy of the Data Bus Busy signal
(DBSY_C1#) is an output only.
DBSY_C2# (O)
DBSY# is a copy of the Data Bus Busy signal. This copy of the Data Bus Busy signal
(DBSY_C2#) is an output only.
DEFER# (I)
The DEFER# signal is asserted by an agent to indicate that the transaction cannot be
guaranteed in-order completion. Assertion of DEFER# is normally the responsibility of
the priority agent.
®
®
96
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Signals Reference
A.1.24
A.1.25
DEN# (I/O)
The Defer Enable (DEN#) signal is driven on the bus on the second clock of the Request
Phase on the Ab[4]# pin. DEN# is asserted to indicate that the transaction can be
deferred by the responding agent.
DEP[15:0]# (I/O)
The Data Bus ECC Protection (DEP[15:0]#) signals provide optional ECC protection for
Data Bus (D[127:0]#). They are driven by the agent responsible for driving
D[127:0]#. During power-on configuration, bus agents can be enabled for either ECC
checking or no checking.
The ECC error correcting code can detect and correct single-bit errors and detect
double-bit or nibble errors.
A.1.26
DHIT# (I)
The Deferred Hit (DHIT#) signal is driven during the Deferred Phase by the deferring
agent. For read transactions on the bus DHIT# returns the final cache status that would
have been indicated on HIT# for a transaction which was not deferred. DID[9:0]# (I/
O)
DID[9:0]# are Deferred Identifier signals. The requesting agent transfers these signals
by using A[25:16]#. They are transferred on Ab[25:16]# during the second clock of
the Request Phase on all transactions, but Ab[20:16]# is only defined for deferrable
transactions (DEN# asserted). DID[9:0]# is also transferred on Aa[25:16]# during the
first clock of the Request Phase for Deferred Reply transactions.
The Deferred Identifier defines the token supplied by the requesting agent. DID[9]#
and DID[8:5]# carry the agent identifiers of the requesting agents (always valid) and
DID[4:0]# carry a transaction identifier associated with the request (valid only with
DEN# asserted). This configuration limits the bus specification to 32 logical bus agents
with each one of the bus agents capable of making up to 32 requests. Table A-7 shows
the DID encodings.
Table A-7.
DID[9:0]# Encoding
DID[9]#
DID[8:5]#
DID[4:0]#
Agent Type
Agent ID[3:0]
Transaction ID[4:0]
DID[9]# indicates the agent type. Symmetric agents use 0. Priority agents use 1.
DID[8:5]# indicates the agent ID. Symmetric agents use their arbitration ID.
DID[4:0]# indicates the transaction ID for an agent. The transaction ID must be
unique for all deferrable transactions issued by an agent which have not reported their
snoop results.
The Deferred Reply agent transmits the DID[9:0]# (Ab[25:16]#) signals received
during the original transaction on the Aa[25:16]# signals during the Deferred Reply
transaction. This process enables the original requesting agent to make an identifier
match with the original request that is awaiting completion.
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
97
Signals Reference
A.1.27
A.1.28
DPS# (I/O)
The Deferred Phase Enable (DPS#) signal is driven to the bus on the second clock of
the Request Phase on the Ab[3]# pin. DPS# is asserted if a requesting agent supports
transaction completion using the Deferred Phase. A requesting agent that supports the
Deferred Phase will always assert DPS#. A requesting agent that does not support the
Deferred Phase will always deassert DPS#.
DRDY# (I/O)
The Data Ready (DRDY#) signal is asserted by the data driver on each data transfer,
indicating valid data on the data bus. In a multi-cycle data transfer, DRDY# can be
deasserted to insert idle clocks.
DRDY# is replicated three times to enable partitioning of data paths in the system
agents. This copy of the Data Ready signal (DRDY#) is an input as well as an output.
A.1.29
A.1.30
A.1.31
DRDY_C1# (O)
DRDY# is a copy of the Data Ready signal. This copy of the Data Phase data-ready
signal (DRDY_C1#) is an output only.
DRDY_C2# (O)
DRDY# is a copy of the Data Ready signal. This copy of the Data Phase data-ready
signal (DRDY_C2#) is an output only.
DSZ[1:0]# (I/O)
The Data Size (DSZ[1:0]#) signals are transferred on REQb[4:3]# signals in the
second clock of the Request Phase by the requesting agent. The DSZ[1:0]# signals
define the data transfer capability of the requesting agent. For the processor, DSZ# =
01, always.
A.1.32
EXF[4:0]# (I/O)
The Extended Function (EXF[4:0]#) signals are transferred on the A[7:3]# pins by the
requesting agent during the second clock of the Request Phase. The signals specify any
special functional requirement associated with the transaction based on the requestor
mode or capability. The signals are defined in Table A-8.
Table A-8.
Extended Function Signals
Extended Function
Signal Name Alias
Function
Signal
EXF[4]#
Reserved
SPLCK#/FCL#
OWN#/CCL#
DEN#
Reserved
EXF[3]#
EXF[2]#
EXF[1]#
EXF[0]#
Split Lock / Flush Cache Line
Memory Update Not Needed / Cache Cleanse
Defer Enable
DPS#
Deferred Phase Supported
®
®
98
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Signals Reference
A.1.33
A.1.34
A.1.35
A.1.36
FCL# (I/O)
The Flush Cache Line (FCL#) signal is driven to the bus on the second clock of the
Request Phase on the A[6]# pin. FCL# is asserted to indicate that the memory
transaction is initiated by the global Flush Cache (FC) instruction.
FERR# (O)
The FERR# signal may be asserted to indicate a processor detected error when IERR
mode is enabled. If IERR mode is disabled, the FERR# signal will not be asserted in the
processor system environment.
GSEQ# (I)
Assertion of the Guaranteed Sequentiality (GSEQ#) signal indicates that the platform
guarantees completion of the transaction without a retry while maintaining
sequentiality.
HIT# (I/O) and HITM# (I/O)
The Snoop Hit (HIT#) and Hit Modified (HITM#) signals convey transaction snoop
operation results. Any bus agent can assert both HIT# and HITM# together to indicate
that it requires a snoop stall. The stall can be continued by reasserting HIT# and
HITM# together.
A.1.37
ID[9:0]# (I)
The Transaction ID (ID[9:0]#) signals are driven by the deferring agent. The signals in
the two clocks are referenced IDa[9:0]# and IDb[9:0]#. During both clocks, ID[9:0]#
signals are protected by the IP0# parity signal for the first clock, and by the IP[1]#
parity signal on the second clock.
IDa[9:0]# returns the ID of the deferred transaction which was sent on Ab[25:16]#
(DID[9:0]#).
A.1.38
IDS# (I)
The ID Strobe (IDS#) signal is asserted to indicate the validity of ID[9:0]# in that clock
and the validity of DHIT# and IP[1:0]# in the next clock.
A.1.39
A.1.40
IGNNE# (I)
IGNNE# is no connect and is ignored in the processor system environment.
INIT# (I)
The Initialization (INIT#) signal triggers an unmasked interrupt to the processor. INIT#
is usually used to break into hanging or idle processor states. Semantics required for
platform compatibility are supplied in the PAL firmware interrupt service routine.
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
99
Signals Reference
A.1.41
INT (I)
INT is the 8259-compatible Interrupt Request signal which indicates that an external
interrupt has been generated. The interrupt is maskable. The processor vectors to the
interrupt handler after the current instruction execution has been completed. An
interrupt acknowledge transaction is generated by the processor to obtain the interrupt
vector from the interrupt controller.
The LINT[0] pin can be software configured to be used either as the INT signal or
another local interrupt.
A.1.42
A.1.43
IP[1:0]# (I)
The ID Parity (IP[1:0]#) signals are driven on the second clock of the Deferred Phase
by the deferring agent. IP0# protects the IDa[9:0]# and IDS# signals for the first
clock, and IP[1]# protects the IDb[9:2, 0]# and IDS# signals on the second clock.
LEN[2:0]# (I/O)
The Data Length (LEN[2:0]#) signals are transmitted using REQb[2:0]# signals by the
requesting agent in the second clock of Request Phase. LEN[2:0]# defines the length of
the data transfer requested by the requesting agent as shown in Table A-9. The
LEN[2:0]#, HITM#, and RS[2:0]# signals together define the length of the actual data
transfer.
Table A-9.
Length of Data Transfers
LEN[2:0]#
Length
000
001
010
011
100
101
110
111
0 – 8 bytes
16 bytes
32 bytes
64 bytes
128 bytes
Reserved
Reserved
Reserved
A.1.44
A.1.45
LINT[1:0] (I)
LINT[1:0] are local interrupt signals. These pins are disabled after RESET#. LINT[0] is
typically software configured as INT, an 8259-compatible maskable interrupt request
signal. LINT[1] is typically software configured as NMI, a non-maskable interrupt.Both
signals are asynchronous inputs.
LOCK# (I/O)
LOCK# is no connect and is ignored in the processor system environment.
®
®
100
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Signals Reference
A.1.46
NMI (I)
The NMI signal is the Non-maskable Interrupt signal. Asserting NMI causes an interrupt
with an internally supplied vector value of 2. An external interrupt-acknowledge
transaction is not generated. If NMI is asserted during the execution of an NMI service
routine, it remains pending and is recognized after the EOI is executed by the NMI
service routine. At most, one assertion of NMI is held pending.
NMI is rising-edge sensitive. Recognition of NMI is guaranteed in a specific clock if it is
asserted synchronously and meets the setup and hold times. If asserted
asynchronously, asserted and deasserted pulse widths of NMI must be a minimum of
two clocks.This signal must be software configured to be used either as NMI or as
another local interrupt (LINT1 pin).
A.1.47
A.1.48
OWN# (I/O)
The Guaranteed Cache Line Ownership (OWN#) signal is driven to the bus on the
second clock of the Request Phase on the Ab[5]# pin. OWN# is asserted if cache line
ownership is guaranteed. This allows a memory controller to ignore memory updates
due to implicit writebacks.
PMI# (I)
The Platform Management Interrupt (PMI#) signal triggers the highest priority
interrupt to the processor. PMI# is usually used by the system to trigger system events
that will be handled by platform specific firmware.
A.1.49
A.1.50
PWRGOOD (I)
The Power Good (PWRGOOD) signal must be deasserted (L) during power-on, and must
be asserted (H) after RESET# is first asserted by the system.
REQ[5:0]# (I/O)
The REQ[5:0]# are the Request Command signals. They are asserted by the current
bus owner in both clocks of the Request Phase. In the first clock, the REQa[5:0]#
signals define the transaction type to a level of detail that is sufficient to begin a snoop
request. In the second clock, REQb[5:0]# signals carry additional information to define
the complete transaction type. REQb[4:3]# signals transmit DSZ[1:0]# or the data
transfer information of the requestor for transactions that involve data transfer.
REQb[2:0]# signals transmit LEN[2:0]# (the data transfer length information). In both
clocks, REQ[5:0]# and ADS# are protected by parity RP#.
All receiving agents observe the REQ[5:0]# signals to determine the transaction type
and participate in the transaction as necessary, as shown in Table A-10.
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
101
Signals Reference
Table A-10. Transaction Types Defined by REQa#/REQb# Signals
REQa[5:0]#
Transaction
REQb[5:0]#
5
4
3
2
1
0
5
4
3
2
1
0
Deferred Reply
Reserved
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
x
x
x
x
x
x
0
x
x
0
x
x
0
Interrupt
Acknowledge
DSZ[1:0]#
Special
Transactions
0
0
1
0
0
0
0
DSZ[1:0]#
0
0
1
Reserved
Reserved
Interrupt
Purge TC
Reserved
I/O Read
I/O Write
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
0
1
x
0
0
0
0
0
0
0
0
0
0
DSZ[1:0]#
DSZ[1:0]#
DSZ[1:0]#
DSZ[1:0]#
DSZ[1:0]#
DSZ[1:0]#
DSZ[1:0]#
DSZ[1:0]#
DSZ[1:0]#
0
0
1
1
1
x
x
x
1
x
x
0
1
x
x
x
x
x
0
0
1
x
x
x
Memory Read &
Invalidate
ASZ[1:0]#
LEN[2:0]#
Reserved
0
0
1
ASZ[1:0]#
ASZ[1:0]#
ASZ[1:0]#
0
1
1
1
D/C#
0
1
0
0
0
0
0
DSZ[1:0]#
DSZ[1:0]#
DSZ[1:0]#
LEN[2:0]#
LEN[2:0]#
LEN[2:0]#
Memory Read
Memory Read
Current
Reserved
1
0
1
ASZ[1:0]#
ASZ[1:0]#
ASZ[1:0]#
1
1
1
1
0
1
1
0
0
0
DSZ[1:0]#
DSZ[1:0]#
DSZ[1:0]#
LEN[2:0]#
LEN[2:0]#
0
Memory Write
WSNP#
WSNP#
Cache Line
Replacement
0
0
A.1.51
RESET# (I)
Asserting the RESET# signal resets all processors to known states and invalidates all
caches without writing back Modified (M state) lines. RESET# must remain asserted for
one millisecond for a “warm” reset; for a power-on reset, RESET# must stay asserted
for at least one millisecond after PWRGOOD and BCLKp have reached their proper
specifications. On observing asserted RESET#, all system bus agents must deassert
their outputs within two clocks.
A number of bus signals are sampled at the asserted-to-deasserted transition of
RESET# for the power-on configuration.
Unless its outputs are tristated during power-on configuration, after asserted-to-
deasserted transition of RESET#, the processor begins program execution at the reset-
vector
A.1.52
RP# (I/O)
The Request Parity (RP#) signal is driven by the requesting agent, and provides parity
protection for ADS# and REQ[5:0]#.
A correct parity signal is high if an even number of covered signals are low and low if an
odd number of covered signals are low. This definition allows parity to be high when all
covered signals are high.
®
®
102
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Signals Reference
A.1.53
A.1.54
RS[2:0]# (I)
The Response Status (RS[2:0]#) signals are driven by the responding agent (the agent
responsible for completion of the transaction).
RSP# (I)
The Response Parity (RSP#) signal is driven by the responding agent (the agent
responsible for completion of the current transaction) during assertion of RS[2:0]#, the
signals for which RSP# provides parity protection.
A correct parity signal is high if an even number of covered signals are low and low if an
odd number of covered signals are low. During the Idle state of RS[2:0]#
(RS[2:0]#=000), RSP# is also high since it is not driven by any agent guaranteeing
correct parity.
A.1.55
SBSY# (I/O)
The Strobe Bus Busy (SBSY#) signal is driven by the agent transferring data when it
owns the strobe bus. SBSY# holds the strobe bus before the first DRDY# and between
DRDY# assertions for a multiple clock data transfer. SBSY# is deasserted before
DBSY# to allow the next data transfer agent to predrive the strobes before the data
bus is released.
SBSY# is replicated three times to enable partitioning of data paths in the system
agents. This copy of the Strobe Bus Busy signal (SBSY#) is an input as well as an
output.
A.1.56
A.1.57
A.1.58
SBSY_C1# (O)
SBSY# is a copy of the Strobe Bus Busy signal. This copy of the Strobe Bus Busy signal
(SBSY_C1#) is an output only.
SBSY_C2# (O)
SBSY# is a copy of the Strobe Bus Busy signal. This copy of the Strobe Bus Busy signal
(SBSY_C2#) is an output only.
SPLCK# (I/O)
The Split Lock (SPLCK#) signal is driven in the second clock of the Request Phase on
the Ab[6]# pin of the first transaction of a locked operation. It is driven to indicate that
the locked operation will consist of four locked transactions.
A.1.59
STBn[7:0]# and STBp[7:0]# (I/O)
STBp[7:0]# and STBn[7:0]# (and DRDY#) are used to transfer data at the 2x transfer
rate in lieu of BCLKp. They are driven by the data transfer agent with a tight skew
relationship with respect to its corresponding bus signals, and are used by the receiving
agent to capture valid data in its latches. This functions like an independent double
frequency clock constructed from a falling edge of either STBp[7:0]# or STBn[7:0]#.
The data is synchronized by DRDY#. Each strobe pair is associated with 16 data bus
signals and two ECC signals as shown in Table A-11.
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
103
Signals Reference
Table A-11. STBp[7:0]# and STBn[7:0]# Associations
Strobe Bits
Data Bits
ECC Bits
STBp[7]#, STBn[7]#
STBp[6]#, STBn[6]#
STBp[5]#, STBn[5]#
STBp[4]#, STBn[4]#
STBp[3]#, STBn[3]#
STBp[2]#, STBn[2]#
STBp[1]#, STBn[1]#
STBp[0]#, STBn[0]#
D[127:112]#
D[111:96]#
D[95:80]#
D[79:64]#
D[63:48]#
D[47:32]#
D[31:16]#
D[15:0]#
DEP[15:14]#
DEP[13:12]#
DEP[11:10]#
DEP[9:8]#
DEP[7:6]#
DEP[5:4]#
DEP[3:2]#
DEP[1:0]#
A.1.60
A.1.61
TCK (I)
The Test Clock (TCK) signal provides the clock input for the IEEE 1149.1 compliant TAP.
TDI (I)
The Test Data In (TDI) signal transfers serial test data into the processor. TDI provides
the serial input needed for IEEE 1149.1 compliant TAP.
A.1.62
A.1.63
TDO (O)
The Test Data Out (TDO) signal transfers serial test data out from the processor. TDO
provides the serial output needed for IEEE 1149.1 compliant TAP.
THRMTRIP# (O)
The Thermal Trip (THRMTRIP#) signal protects the processor from catastrophic
overheating by use of an internal thermal sensor. This sensor is set well above the
normal operating temperature to ensure that there are no false trips. Data will be lost if
the processor goes into thermal trip (signaled to the system by the assertion of the
THRMTRIP# signal). Once THRMTRIP# is asserted, the platform must assert RESET# to
protect the physical integrity of the processor.
A.1.64
THRMALERT# (O)
THRMALERT# is asserted when the measured temperature from the processor thermal
diode equals or exceeds the temperature threshold data programmed in the high-temp
(THIGH) or low-temp (TLOW) registers on the sensor. This signal can be used by the
platform to implement thermal regulation features.
A.1.65
A.1.66
TMS (I)
The Test Mode Select (TMS) signal is an IEEE 1149.1 compliant TAP specification
support signal used by debug tools.
TND# (I/O)
The TLB Purge Not Done (TND#) signal is asserted to delay completion of a TLB Purge
instruction, even after the TLB Purge transaction completes on the system bus.
®
®
104
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Signals Reference
A.1.67
A.1.68
A.1.69
TRDY# (I)
The Target Ready (TRDY#) signal is asserted by the target to indicate that it is ready to
receive a write or implicit writeback data transfer.
TRST# (I)
The TAP Reset (TRST#) signal is an IEEE 1149.1 compliant TAP support signal used by
debug tools.
WSNP# (I/O)
The Write Snoop (WSNP#) signal indicates that snooping agents will snoop the memory
write transaction
A.2
Signal Summaries
Table A-12 through Table A-15 list attributes of the processor output, input, and I/O
signals.
Table A-12. Output Signals
Name
Active Level
Clock
Signal Group
CPUPRES#
DBSY_C1#
DBSY_C2#
DRDY_C1#
DRDY_C2#
FERR#
Low
Low
Low
Low
Low
Low
—
BCLKp
Platform
Data
BCLKp
Data
BCLKp
Data
BCLKp
Data
Asynchronous
PC Compatibility,
IERR Mode
SBSY_C1#
SBSY_C2#
TDO
Low
Low
High
Low
Low
BCLKp
BCLKp
Data
Data
TAP
TCK
THRMTRIP#
THRMALERT#
Asynchronous
Asynchronous
Error
Error
Table A-13. Input Signals (Sheet 1 of 2)
Name
Active Level
Clock
Signal Group
Qualified
BPRI#
BR1#
Low
Low
Low
Low
High
High
Low
Low
Low
Low
BCLKp
BCLKp
BCLKp
BCLKp
—
Arbitration
Arbitration
Arbitration
Arbitration
Control
Always
Always
BR2#
Always
BR3#
Always
BCLKp
BCLKn
D/C#
Always
—
Control
Always
BCLKp
BCLKp
BCLKp
BCLKp
System Bus
Snoop
Request Phase (Mem Rd)
Snoop Phase
IDS#+1
DEFER#
DHIT#
GSEQ#
System Bus
Snoop
Snoop Phase
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
105
Signals Reference
Table A-13. Input Signals (Sheet 2 of 2)
Name
Active Level
Clock
Signal Group
Qualified
ID[9:0]#
IDS#
Low
Low
Low
High
Low
High
Low
Low
Low
Low
High
High
High
High
Low
Low
BCLKp
BCLKp
Asynch
Asynch
BCLKp
Asynch
BCLKp
BCLKp
BCLKp
Asynch
Asynch
—
Defer
IDS#, IDS#+1
Always
Defer
1
INIT#
Exec Control
Exec Control
System Bus
Exec Control
Control
Always
INT (LINT0)
IP[1:0]#
NMI (LINT1)
RESET#
RS[2:0]#
RSP#
IDS#+1
Always
Always
Always
Response
Response
Exec Control
Control
PMI#
PWRGOOD
TCK
—
Always
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Response
TDI
TCK
Always
TMS
TCK
Always
TRST#
Asynch
BCLKp
Always
TRDY#
Response Phase
Notes:
1. Synchronous assertion with asserted RS[2:0]# guarantees synchronization.
Table A-14. Input/Output Signals (Single Driver) (Sheet 1 of 2)
Name
Active Level
Clock
Signal Group
Qualified
A[49:3]#
ADS#
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
BCLKp
BCLKp
BCLKp
BCLKp
BCLKp
BCLKp
BCLKp
BCLKp
BCLKp
BCLKp
BCLKp
BCLKp
BCLKp
BCLKp
BCLKp
BCLKp
BCLKp
BCLKp
BCLKp
BCLKp
BCLKp
BCLKp
Request
Request
ADS#, ADS#+1
Always
AP[1:0]#
ASZ[1:0]#
ATTR[3:0]#
BE[7:0]#
BR0#
Request
ADS#, ADS#+1
ADS#
System Bus
System Bus
System Bus
System Bus
Diagnostic
System Bus
Data
ADS#+1
ADS#+1
Always
BPM[5:0]#
CCL#
Always
ADS#+1
DRDY#
D[127:0]#
DBSY#
Data
Always
D/C#
System Bus
System Bus
System Bus
System Bus
Data
ADS#
DEN#
ADS#+1
DRDY#
DEP[15:0]#
DID[9:0]#
DRDY#
ADS#+1
Always
DPS#
System Bus
System Bus
System Bus
System Bus
System Bus
System Bus
ADS#+1
ADS#+1
ADS#+1
ADS#+1
ADS#+1
ADS#+1
DSZ[1:0]#
EXF[4:0]#
FCL#
LEN[2:0]#
OWN#
®
®
106
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Signals Reference
Table A-14. Input/Output Signals (Single Driver) (Sheet 2 of 2)
Name
Active Level
Clock
Signal Group
Qualified
REQ[5:0]#
RP#
Low
Low
Low
Low
Low
Low
Low
BCLKp
BCLKp
BCLKp
BCLKp
—
Request
Request
Data
ADS#, ADS#+1
ADS#, ADS#+1
Always
SBSY#
SPLCK#
System Bus
Data
ADS#+1
STBn[7:0]#
STBp[7:0]#
WSNP#
Always
—
Data
Always
BCLKp
System Bus
ADS#
Table A-15. Input/Output Signals (Multiple Driver)
Name
Active Level
Clock
Signal Group
Qualified
BNR#
BERR#
BINIT#
HIT#
Low
Low
Low
Low
Low
Low
BCLKp
BCLKp
BCLKp
BCLKp
BCLKp
BCLKp
System Bus
Error
Always
Always
Error
Always
Snoop
Snoop
Snoop
Snoop Phase
Snoop Phase
Always
HITM#
TND#
§
®
®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
107
Signals Reference
®
®
108
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
相关型号：
©2020 ICPDF网 联系我们和版权申明