80C51GB_技术文档

8XC51GB

CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER

Commercial/Express

87C51GBÐ8 Kbytes OTP/8 Kbytes Internal Program Memory

83C51GBÐ8 Kbytes Factory Programmable ROM

80C51GBÐCPU with RAM and I/O

g

8XC51GBÐ3.5 MHz to 12 MHz 20% V

8XC51GB-1Ð3.5 MHz to 16 MHz 20% V

CC

g

CC

Y

8 Kbytes On-Chip ROM/OTP ROM

256 Bytes of On-Chip Data RAM

48 Programmable I/O Lines with

40 Schmitt Trigger Inputs

Y

15 Interrupt Sources with:

Ð 7 External, 8 Internal Sources

Ð 4 Programmable Priority Levels

Two Programmable Counter Arrays

with:

Ð 2 x 5 High Speed Input/Output

Channels Compare/Capture

Ð Pulse Width Modulators

Ð Watchdog Timer Capabilities

Y

Pre-Determined Port States on Reset

High Performance CHMOS Process

TTL and CHMOS Compatible Logic

Levels

Y

Three 16-Bit Timer/Counters with

Ð Four Programmable Modes:

Ð Capture, Baud Rate Generation

(Timer 2)

Y

Power Saving Modes

64K External Data Memory Space

64K External Program Memory Space

Three Level Program Lock System

ONCE (ON-Circuit Emulation) Mode

Quick Pulse Programming Algorithm

Y

Dedicated Watchdog Timer

8-Bit, 8-Channel A/D with:

Ð Eight 8-Bit Result Registers

Ð Four Programmable Modes

Y

Programmable Serial Channel with:

Ð Framing Error Detection

Ð Automatic Address Recognition

MCS 51 Microcontroller Fully

É

Compatible Instruction Set

Y

Serial Expansion Port

Boolean Processor

Programmable Clock Out

Extended Temperature Range:

Oscillator Fail Detect

Available in 68-Pin PLCC

b

a

40 C to 85 C)

(

§

MEMORY ORGANIZATION

PROGRAM MEMORY: Up to 8 Kbytes of the program memory can reside in the on-chip ROM. Also, the device

can address up to 64K of program memory external to the chip.

DATA MEMORY: This microcontroller has a 256 x 8 on-chip RAM. In addition it can address up to 64 Kbytes of

external data memory.

The Intel 8XC51GB is a single-chip control oriented microcontroller which is fabricated on Intel’s CHMOS III-E

technology. The 8XC51GB is an enhanced version of the 8XC51FA and uses the same powerful instruction

set and architecture as existing MCS 51 microcontroller products. Added features make it an even more

powerful microcontroller for applications that require On-Chip A/D, Pulse Width Modulation, High Speed I/O,

up/down counting capabilities and memory protection features. It also has a more versatile serial channel that

facilitates multi-processor communications.

*Other brands and names are the property of their respective owners.

Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or

copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make

changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.

©

COPYRIGHT INTEL CORPORATION, 1995

November 1994

Order Number: 272337-002

8XC51GB

272337–1

Figure 1. 8XC51GB Block Diagram

PROCESS INFORMATION

PACKAGES

Part

Prefix

Package Type

This device is manufactured on P629.0, a CHMOS

III-E process. Additional process and reliability infor-

mation is available in Intel’s Components Quality

and Reliability Handbook, Order No. 210997.

8XC51GB

N

68-Pin PLCC

2

8XC51GB

PARALLEL I/O PORTS

Port Pins as Inputs

The 8XC51GB contains six 8-bit parallel I/O ports.

All six ports are bidirectional and consist of a latch,

an output driver, and an input buffer. Many of the

port pins have multiplexed I/O and control functions.

The pins of all six ports are configured as inputs by

writing a logic 1 to them. Since Port 0 is an open

drain port, it provides a very high input impedance.

Since pins of Port 1, 2, 3, 4 and 5 have weak pullups

(which are always on), they source a small current

when driven low externally. All ports except Port 0

have Schmitt trigger inputs.

Port Pins as Outputs

Port 0 has open drain outputs when it is not serving

as the external data bus. The internal pullup is active

only when the pin is outputting a logic 1 during exter-

nal memory access. An external pullup resistor is

required on Port 0 when it is serving as an output

port.

Port States During Reset

Ports 0 and 3 reset asynchronously to a one and

Ports 1, 2, 4, and 5 reset to a zero asynchronously.

Ports 1, 2, 3, 4, and 5 have quasi-bidirectional out-

puts. A strong pullup provides a fast rise time when

the pin is set to a logic 1. This pullup turns on for two

oscillator periods to drive the pin high and then turns

off. The pin is held high by a weak pullup.

PIN DESCRIPTIONS

The 8XC51GB will be packaged in the 68-lead PLCC

package. Its pin assignment is shown in Figure 2.

V

: Supply Voltage.

CC

Writing the P0, P1, P2, P3, P4 or P5 Special Function

Register sets the corresponding port pins. All six

port registers are bit addressable.

V

SS

: Circuit Ground.

Diagram is for Pin Reference Only. Package Size is Not to Scale.

272337–2

*OTP only

Figure 2. Pin Connections

3

8XC51GB

ALTERNATE PORT FUNCTIONS

Ports 0, 1, 2, 3, 4 and 5 have alternate functions as well as their I/O function as described below.

Port Pin

P0.0/ADO–P0.7/AD7

P1.0/T2

Alternate Function

Multiplexed Address/Data for External Memory

Timer 2 External Clock Input/Clock-Out

Timer 2 Reload/Capture/Direction Control

PCA External Clock Input

P1.1/T2EX

P1.2/ECI

P1.3/CEXO–P1.7/CEX4

P2.0/A8–P2.7/A15

P3.0/RXD

PCA Capture Input, Compare/PWM Output

High Byte of Address for External Memory

Serial Port Input

P3.1/TXD

Serial Port Output

P3.2/INT0

External Interrupt 0

P3.3/INT1

External Interrupt 1

P3.4/T0

Timer 0 External Clock Input

P3.5/T1

Timer 1 External Clock Input

P3.6/WR

Write Strobe for External Memory

Read Strobe for External Memory

Clock Source for Serial Expansion Port

Data I/O for the Serial Expansion Port

PCA1 External Clock Input

P3.7/RD

P4.0/SEPCLK

P4.1/SEPDAT

P4.2/ECI1

P4.3/C1EX0–P4.7/C1EX4

P5.2/INT2–P5.6/INT6

PCA1 Capture Input, Compare/PWM Output

External Interrupt INT2–INT6

RST: Reset input. A low on this pin for two machine

cycles while the oscillator is running resets the de-

vice. The port pins will be driven to their reset condi-

terminated, the ALE pin will no longer be pulled up

weakly. Setting the ALE-disable bit has no affect if

the microcontroller is in external execution mode.

tion when a voltage below V max voltage is ap-

IL

plied, whether the oscillator is running or not. An

internal pullup resistor permits a power-on reset with

Throughout the remainder of this data sheet, ALE

will refer to the signal coming out of the ALE/PROG

pin, and the pin will be referred to as the ALE/PROG

pin.

only a capacitor connected to V

.

SS

ALE/PROG: Address Latch Enable output pulse for

latching the low byte of the address during accesses

to external memory. This pin (ALE/PROG) is also

the program pulse input during programming of the

87C51GB.

PSEN: Program Store Enable is the read strobe to

external Program Memory.

When the 8XC51GB is executing code from external

Program Memory, PSEN is activated twice each ma-

chine cycle, except that two PSEN activations are

skipped during each access to external Data Memo-

ry.

In normal operation ALE is emitted at a constant

rate of (/6 the oscillator frequency, and may be used

for external timing or clocking purposes. Note, how-

ever, that one ALE pulse is skipped during each ac-

cess to external Data Memory.

EA/V

:

External Access enable. EA must be

strapped to V in order to enable the device to

PP

SS

If desired, ALE operation can be disabled by setting

bit 0 of SFR location 8EH. With this bit set, the pin is

weakly pulled high. However, the ALE disable fea-

ture will be suspended during a MOVX or MOVC in-

struction, idle mode, power down mode and ICE

mode. The ALE disable feature will be terminated by

reset. When the ALE disable feature is suspended or

fetch code from external Program Memory locations

0000H to 1FFFH. Note, however, that if either of the

Program Lock bits are programmed, EA will be inter-

nally latched on reset.

EA should be strapped to V

executions.

for internal program

CC

4

8XC51GB

This pin also receives the 12.75V programming sup-

ply voltage (V ) during programming (OTP only).

PP

common timing reference. Each Register/Compara-

tor Module is associated with a pin of Port 1 or Port 4

and is capable of performing input capture, output

compare and pulse width modulation functions. The

PCAs are exactly the same in function except for the

addition of clock input sources on PCA1.

XTAL1: Input to the inverting oscillator amplifier.

XTAL2: Output from the inverting oscillator amplifi-

er.

The PCA Counter and five Register/Comparator

Modules each have a status bit in the CCON/

C1CON Special Function Registers. These six

status bits are set according to the selected modes

of operation described below. The CCON/C1CON

Register provides a convenient means to determine

which of the six PCA/PCA1 interrupts has occurred.

The EC Bit in the IE (Interrupt Enable) Special Func-

tion Register is a global interrupt enable for the PCA.

A/D CONVERTER

The 8XC51GB A/D converter has a resolution of 8

g

bits and an accuracy of 1 LSB ( 2 LSB for chan-

nels 0 and 1). The conversion time for a single chan-

nel is 20 ms at a clock frequency of 16 MHz with the

sample and hold function included. Independent

supply voltages are provided for the A/D. Also, the

A/D operates both in Normal Mode or in Idle Mode.

The A/D has 8 analog input pins; ACH0 (A/D CHan-

nel 0) . . . ACH7, 1 reference input pin; COMPREF

(COMParison REFerence), 1 control input pin; TRI-

GIN (TRIGger IN), and 2 power pins; AVREF (Volt-

age REFerence) and analog ground (ANalog

GrouND). In addition, the A/D has 8 conversion re-

sult registers; ADRES0 (A/D result for channel 0) . . .

ADRES7, 1 comparison result register; ACMP (Ana-

log Comparison), and 1 control register; ACON (A/D

Control).

The control bit ACE (A/D Conversion Enable) in

ACON controls whether the A/D is in operation or

272337–3

e

conversion. The control bit AIM (A/D Input mode) in

not. ACE

0 idles the A/D. ACE

1 enables A/D

Figure 3. Programmable Counter Arrays

ACON controls the mode of channel selection. AIM

e

1 is the Select

e

0 is the Scan Mode, and AIM

OSCILLATOR CHARACTERISTICS

Mode. The result registers ADRES4 . . . ADRES7 al-

ways contain the result of a conversion from the cor-

responding channels ACH4 . . . CH7. However, the

result registers ADRES0 . . . ADRES3 depend on the

mode selected. In the scan mode, ADRES0 . . . AD-

RES3 contain the values from ACH0 . . . ACH3. In

the Select Mode, one of the four channels ACH0 . . .

ACH3 is converted four times, and the four values

are stored sequentially in locations ADRES0 . . . AD-

RES3. Its channel is selected by bits ACS1 and

ACS0 (A/D Channel Select 1 and 0) in ACON.

XTAL1 and XTAL2 are the input and output, respec-

tively, of an inverting amplifier which can be config-

ured for use as an on-chip oscillator, as shown in

Figure 4. Either a quartz crystal or ceramic resonator

may be used. More detailed information concerning

the use of the on-chip oscillator is available in Appli-

cation Note AP-155, ‘‘Oscillators for Microcontrol-

lers,’’ Order No. 230659.

To drive the device from an external clock source,

XTAL should be driven, while XTAL2 floats, as

shown in Figure 5. There are no requirements on the

duty cycle of the external clock signal, since the in-

put to the internal clocking circuitry is through a di-

vide-by-two flip-flop, but minimum and maximum

high and low times specified on the data sheet must

be observed.

PROGRAMMABLE COUNTER ARRAYS

The Programmable Counter Arrays (PCA–PCA1) are

each made up of a Counter Module and five Regis-

ter/Comparator Modules as shown below. The

16-bit output of the counter module is available to all

five Register/Comparator Modules, providing one

5

8XC51GB

POWER DOWN MODE

To save even more power, a Power Down mode can

be invoked by software. In this mode, the oscillator

is stopped and the instruction that invoked Power

Down is the last instruction executed. The on-chip

RAM and Special Function Registers retain their val-

ues until the Power Down mode is terminated.

On the 8XC51GB either a hardware reset or an ex-

ternal interrupt can cause an exit from Power Down.

Reset redefines all the SFRs but does not change

the on-chip RAM. An external interrupt does not re-

define the SFR’s or change the on-chip RAM. An

external interrupt will modify the interrupt associated

SFR’s in the same way an interrupt will in all other

modes. The interrupt must be enabled and config-

ured as level sensitive. To properly terminate Power

Down the reset or external interrupt should not be

272337–4

e

g

30 pF 10 pF for Crystals

C1, C2

For Ceramic Resonators contact resonator

manufacturer.

Figure 4. Oscillator Connections

executed before V

is restored to its normal oper-

CC

ating level. The reset or external interrupt must be

held active long enough for the oscillator to restart

and stabilize. The Oscillator Fail Detect must be dis-

abled prior to entering Power Down.

272337–5

DESIGN CONSIDERATIONS

Figure 5. External Clock Drive Configuration

When the idle mode is terminated by a hardware

#

reset, the device normally resumes program exe-

cution, from where it left off, up to two machine

cycles before the internal reset algorithm takes

control. On-chip hardware inhibits access to inter-

nal RAM in this event, but access to the port pins

is not inhibited. To eliminate the possibility of an

unexpected write when Idle is terminated by re-

set, the instruction following the one that invokes

Idle should not be one that writes to a port pin or

to external memory.

IDLE MODE

The user’s software can invoke the Idle Mode. When

the microcontroller is in this mode, power consump-

tion is reduced. The Special Function Registers and

the onboard RAM retain their values during idle, pe-

ripherals continue to operate, but the processor

stops executing instructions. Idle Mode will be exited

if the chip is reset or if an enabled interrupt occurs.

The PCA timer/counter can optionally be left run-

ning or paused during Idle Mode. The Watchdog

Timer continues to count in Idle Mode and must be

serviced to prevent a device RESET while in Idle.

As RESET rises, the 8XC51GB will remain in re-

set for up to 5 machine cycles (60 oscillator peri-

#

ods) after RESET reaches V

.

IH1

Table 1. Status of the External Pins during Idle and Power Down

Program

Mode

Idle

ALE

PSEN

PORT0

PORT1

PORT2

PORT3

Memory

Internal

External

Internal

External

1

0

1

0

Data

Float

Data

Float

Data

Address

Data

Power Down

Data

NOTE:

For more detailed information on the reduced power modes refer to current Embedded Microcontrollers

and Processors Handbook Volume I (Order No. 270645), and Application Note AP-252 (Embedded

Applications Handbook, Order No. 270648), ‘‘Designing with the 80C51BH.’’

6

8XC51GB

ONCE MODE

Serial Expansion Port (SEP)

The ONCE (‘‘On-Circuit Emulation’’) Mode facilitates

testing and debugging of systems using the

8XC51GB without removing it from the circuit. The

ONCE Mode is invoked by:

The Serial Expansion Port is a half-duplex synchro-

nous serial interface with the following features:

Four Clock FrequenciesÐ XTAL/12, 24, 48, 96.

1) Pulling ALE low while the device is in reset and

PSEN is high;

Four Interface ModesÐ High/Low/Falling/Rising

Edges.

2) Holding ALE low as RESET is deactivated.

Interrupt Driven.

While the device is in ONCE Mode, the Port 0 pins

float, and the other port pins and ALE and PSEN are

weakly pulled high. The oscillator circuit remains ac-

tive. While the 8XC51GB is in this mode, an emula-

tor or test CPU can be used to drive the circuit. Nor-

mal operation is restored when a normal reset is ap-

plied.

Oscillator Fail Detect (OFD)

The Oscillator Fail Detect circuitry triggers a reset if

the oscillator frequency is lower than the OFD trig-

ger frequency. It can be disabled by software by writ-

ing E1H followed by 1EH to the OFDCON register.

Before going into Power Down Mode, the OFD must

be disabled or it will force the GB out of Power

Down. The OFD has the following features.

Watchdog Timer (WDT)

The 8XC51GB contains a dedicated Watchdog Tim-

er (WDT) to allow recovery from a software or hard-

ware upset. The WDT consists of a 14-bit counter

which is cleared on Reset, and subsequently incre-

mented every machine cycle. While the oscillator is

running, the WDT will be incrementing and cannot

be disabled. The counter may be reset by writing

1EH and E1H in sequence to the WDTRST Special

Function Register. If the counter is not reset before

it reaches 3FFFH (16383D), the chip will be forced

into a reset sequence by the WDT. This works out to

OFD Trigger Frequency: Below 20 KHz, the

8XC51GB will be held in reset. Above 400 KHz,

the 8XC51GB will not be held is reset.

Functions in Normal and Idle Modes.

Reactivated by Reset (or External Interrupt Ze-

ro/One Pins) after Software Disable.

8XC51GB EXPRESS

The Intel EXPRESS products are designed to meet

the needs of those applications whose operating re-

quirements exceed commercial standards.

@

12.28 ms 16 MHz. WDTRST is a write only regis-

ter. The WDT does not force the external reset pin

low.

With the commercial standard temperature range,

operational characteristics are guaranteed over the

While in Idle mode the WDT continues to count. If

the user does not wish to exit Idle with a reset, then

the processor must be periodically ‘‘woken up’’ to

service the WDT. In Power Down mode, the WDT

stops counting and holds its current value.

a

tended temperature range option, operational char-

temperature range of 0 C to

70 C. With the ex-

§

b

acteristics are guaranteed over the range of 40 C

to 85 C. The 87C51GB EXPRESS is packaged in

§

a

§

the 68-lead PLCC package. In order to designate a

part as an EXPRESS part, a ‘‘T’’ is added as a prefix

to the part number. TN87C51GB denotes an EX-

PRESS part in a PLCC package.

All AC and DC parameters in this data sheet apply to

the EXPRESS devices.

7

8XC51GB

ABSOLUTE MAXIMUM RATINGS*

NOTICE: This data sheet contains preliminary infor-

mation on new products in production. The specifica-

tions are subject to change without notice. Verify with

your local Intel Sales office that you have the latest

data sheet before finalizing a design.

a

Ambient Temperature under Bias ÀÀÀÀ0 C to 70 C

§

Storage Temperature ÀÀÀÀÀÀÀÀÀÀ 65 C to 150 C

§

b

a

§

Voltage on EA/V

PP

*WARNING: Stressing the device beyond the ‘‘Absolute

Maximum Ratings’’ may cause permanent damage.

These are stress ratings only. Operation beyond the

‘‘Operating Conditions’’ is not recommended and ex-

tended exposure beyond the ‘‘Operating Conditions’’

may affect device reliability.

a

Pin to V ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0V to 13.0V*

SS

I

per I/O Pin ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ15 mA

OL

Voltage on Any Other

b

a

Pin to V ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 0.5V to 6.5V

SS

Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5W

(Based on Package heat transfer limitations, not de-

vice power consumption)

*OTP only.

OPERATING CONDITIONS

Symbol

Description

Min

Max

Units

T

A

Ambient Temperature Under Bias

Commercial

Express

a

0

70

85

C

§

b

40

C

V

CC

Supply Voltage

4.0

6.0

V

f

Oscillator Frequency

8XC51GB

8XC51GB-1

OSC

3.5

12

16

MHz

DC CHARACTERISTICS (Over Operating Conditions)

(1)

Typ

Symbol

Parameter

Min

Max

Unit

Test Conditions

b

V

Input Low Voltage

(except Port 2 and EA)

0.5

0.2 V

0.1

0.3

V

IL

CC

b

Input Low Voltage

(Port 2)

0.5

V

IL1

IL2

IH

Input Low Voltage

(EA)

0

a

0.5

Input High Voltage

(except XTAL1 and RST)

0.2 V

0.9

V

CC

a

0.5

Input High Voltage

(XTAL1, RST)

0.7 V

V

IH1

OL

CC

(2,3)

e

Output Low Voltage

(Ports 1, 2, 3, 4 and 5)

0.3

0.45

1.0

V

I

100 mA

1.6 mA

3.5 mA

200 mA

3.2 mA

7.0 mA

OL

(2,3)

V

Output Low Voltage

(Port 0, PSEN, ALE)

0.3

OL1

0.45

1.0

8

8XC51GB

DC CHARACTERISTICS (Over Operating Conditions) (Continued)

(1)

Typ

Symbol

Parameter

Min

Max

Unit

V

Test Conditions

(4)

b

e b

V

OH

Output High Voltage

(Ports 1, 2, 3, 4 and 5,

ALE, PSEN)

V

0.3

0.7

1.5

0.3

0.7

1.5

I

10 mA

30 mA

60 mA

CC

OH

(4)

b

V

CC

V

OH1

Output High Voltage

(Port 0 in External

Bus Mode)

V

200 mA

3.2 mA

7.0 mA

V

b

e

I

Logical 0 Input Current

(Ports 1, 2, 3, 4, 5)

50

mA

V

0.45V

IL

IN

b

e

Logical 1-to-0 Transition

Current (Ports 1, 2, 3, 4, 5)

650

mA

V

IN

2.0V

TL

LI

k

V

g

Input Leakage Current

(Port 0)

10

0.45

Freq

V

IN

CC

RRST

RST Pullup Resistor

Pin Capacitance

50

300

kX

e

C

10

pF

1 MHz

IO

e

T

25 C

§

A

I

Power Down Current

Idle Mode Current

50

18

50

5

mA

(5)

PD

DL

@

Operating Current 16 MHz

CC

REF

A/D Converter Reference

Current

NOTES:

1. Typical values are obtained using V

e

2. Under steady state (non-transient) conditions, I must be externally limited as follows:

5.0V, T

25 C, and are not guaranteed.

§

CC

A

OL

Maximum I per Port Pin:

OL

Maximum I per 8-Bit PortÐ

10 mA

OL

Port 0:

26 mA

15 mA

Maximum Total I for All Outputs Pins: 101 mA

Ports 1–5:

OL

If I exceeds the test conditions, V may exceed the related specification. Pins are not guaranteed to sink current

OL OL

greater than the listed test conditions.

3. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4V on the low level outputs of ALE and

Ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins

change from 1 to 0. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed

0.8V. It may be desirable to qualify ALE or other signals with a Schmitt Trigger, or CMOS-level input logic.

4. Capacitive loading on Ports 0 and 2 cause the V

OH

address lines are stabilizing.

5. See Figures 6–10 for test conditions. Minimum V

on ALE and PSEN to drop below the 0.9 V

specification when the

CC

for Power Down is 2V.

CC

9

8XC51GB

272337–7

All other pins disconnected.

e

TCLCH

TCHCL

5 ns

272337–6

Figure 7. I Test Condition,

CC

Active Mode

I

Max at other frequencies is given by:

CC

Active Mode

I

e

c

a

4

Max

(Osc Freq

3)

CC

Idle Mode

Max

e

c

a

4

is in mA. T

I

(Osc Freq

0.5)

CC

e

5 ns

Where Osc Freq is in MHz, I

T

CHCL

CC

CLCH

Figure 6. I vs Frequency

CC

272337–8

272337–9

All other pins disconnected.

e

All other pins disconnected.

e

TCLCH

TCHCL

5 ns

Figure 9. I Test Condition, Power Down Mode

CC

Figure 8. I Test Condition Idle Mode

CC

e

V

2.0V to 5.5V

CC

272337–10

e

5 ns.

Figure 10. Clock Signal Waveform for I Tests in Active and Idle Modes. TCLCH

CC

TCHCL

10

8XC51GB

L: Logic Level LOW, or ALE

P: PSEN

EXPLANATION OF THE AC SYMBOLS

Each timing symbol has 5 characters. The first char-

acter is always a ‘‘T’’ (stands for time). The other

characters, depending on their positions, stand for

the name of a signal or the logical status of that

signal. The following is a list of all the characters and

what they stand for:

Q: Output Data

R: RD Signal

T: Time

V: Valid

W: WR Signal

X: No Longer a Valid Logic Level

Z: Float

A: Address

C: Clock

D: Input Data

For Example:

H: Logic Level HIGH

I: Instruction (Program Memory Contents)

e

TAVLL

TLLPL

Time from Address Valid to ALE Low

Time from ALE Low to PSEN Low

AC SPECIFICATIONS

e

Over Operating Conditions, Load Capacitance on Port 0, ALE, and PSEN

e

100 pF, Load Capacitance on all

other outputs

80 pF

EXTERNAL PROGRAM AND DATA MEMORY CHARACTERISTICS

12 MHz Osc.

Variable Osc.

Symbol

Parameter

Units

Min

Max

Min

3.5

Max

1/TCLCL Osc. Freq.

16

MHz

ns

b

40

TLHLL

TAVLL

TLLAX

TLLIV

ALE Pulse Width

127

43

2TCLCL

b

40

ADDR Valid to ALE Low

ADDR Hold after ALE Low

ALE Low to Valid Inst. IN

ALE LOW to PSEN LOW

PSEN Pulse Width

TCLCL

b

53

30

b

100

234

145

4TCLCL

b

TLLPL

TPLPH

TPLIV

53

TCLCL

30

b

45

205

3TCLCL

b

3TCLCL 105

PSEN Low to Valid Instr In

Input Instr. Hold after PSEN

Input Instr. Float after PSEN

ADDR to Valid Instr. In

PSEN Low to ADDR Float

RD Pulse Width

TPXIX

0

b

TPXIZ

59

312

10

TCLCL

25

TAVIV

5TCLCL

105

TPLAZ

TRLRH

TWLWH

TRLDV

TRHDX

TRHDZ

TLLDV

TAVDV

TLLWL

TAVWL

TQVWX

TWHQX

TQVWH

TRLAZ

TWHLH

10

b

400

6TCLCL

100

WR Pulse Width

b

5TCLCL 165

RD Low to Valid Data In

Data Hold after RD

252

0

b

Data Float after RD

107

517

585

300

2TCLCL

8TCLCL

9TCLCL

3TCLCL

60

150

165

50

b

ALE Low to Valid Data In

ADDR to Valid Data In

ALE Low to RD or WR Low

ADDR Valid to RD or WR Low

Data Valid to WR Transition

Data Hold after WR

b

a

200

203

33

3TCLCL

4TCLCL

TCLCL

50

130

50

b

33

TCLCL

50

Data Valid to WR High

RD Low to Addr Float

RD or WR High to ALE High

433

7 TCLCL

150

0

b

a

40

43

123

TCLCL

40

TCLCL

11

8XC51GB

EXTERNAL PROGRAM MEMORY READ CYCLE

272337–11

EXTERNAL DATA MEMORY READ CYCLE

272337–12

EXTERNAL DATA MEMORY WRITE CYCLE

272337–13

12

8XC51GB

SERIAL PORT TIMINGÐSHIFT REGISTER MODE

e

Test Conditions: Over Operating Conditions, Load Capacitance

80 pF

12 MHz

Oscillator

Variable

Oscillator

Symbol

Parameter

Units

Min Max

Min

12TCLCL

Max

TXLXL

TQVXH

TXHQX

TXHDX

TXHDV

Serial Port Clock

Cycle Time

1

700

50

0

ms

ns

b

Output Data Setup to

Clock Rising Edge

10TCLCL

2TCLCL

0

133

117

b

Output Data Hold after

Clock Rising Edge

Input Data Hold after

Clock Rising Edge

b

133

Clock Rising Edge to

Input Data Valid

700

10TCLCL

SHIFT REGISTER MODE TIMING WAVEFORMS

272337–14

EXTERNAL CLOCK DRIVE

Symbol

1/TCLCL

TCHCX

TCLCX

Parameter

Oscillator Frequency

High Time

Min

3.5

20

Max

Units

MHz

ns

16

Low Time

20

ns

TCLCH

TCHCL

Rise Time

20

ns

Fall Time

ns

EXTERNAL CLOCK DRIVE WAVEFORM

272337–15

13

8XC51GB

SEP AC TIMING SPECIFICATIONS

Test Conditions: Over Operating Conditions, Load Capacitance

e

80 pF

12 MHz

Variable

Oscillator

Symbol

Parameter

Units

Min

1

Max

Min

Max

TXSXL

TXSST

TXSOH

TXSIH

SEPCLK Cycle Time

12 TCLCL

ms

ns

b

a

Output Data Setup to SEPCLK

Output Data Hold after SEPCLK

435

445

210

6 TCLCL

2 TCLCL

65

55

43

Input Data Hold after SEPCLK

Sampling Edge

b

TXSDV

Input Data Valid to SEPCLK

Sampling Edge

947

12 TCLCL

53

ns

e

SEP Waveform (SEPS1 0; SEPS0 0; CLKPOL 0; CLKPH 0)

272337–16

272337–17

14

8XC51GB

AC TESTING INPUT, OUTPUT WAVEFORMS

FLOAT WAVEFORMS

272337–19

272337–18

For timing purposes a port pin is no longer floating

when a 100 mV change from load voltage occurs,

and begins to float when a 100 mV change from

b

‘‘1’’ and 0.5V for a Logic ‘‘0’’. Timing measurements are

made at V for a Logic ‘‘1’’ and V max for a Logic ‘‘0’’.

IH OL

AC inputs during testing are driven at V

CC

0.5V for a Logic

t

g

20

the loaded V /V level occurs. I /I

OH OL OL OH

mA.

A TO D CHARACTERISTICS

OPERATING CONDITIONS

The absolute conversion accuracy is dependent on

. The specifications given be-

V

ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ4.0V to 6.0V

CC

the accuracy of AV

low assume adherence to the Operating Conditions

REF

AV

ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ4.5V to 5.5V

REF

V

, AV ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0V

SS SS

section of this data sheet. Testing is done at

e

5.0V.

e

AV

5.12V, and V

ACH0–7 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀAV to V

SS REF

REF

CC

a

ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0 C to 70 C Ambient

T

§

A

FOSC (STD Version)ÀÀÀÀÀÀÀÀÀÀÀ3.5 MHz to 12 MHz

FOSC (-1 Version) ÀÀÀÀÀÀÀÀÀÀÀÀÀ3.5 MHz to 16 MHz

e

a

0 C to 70 C

A/D CONVERTER SPECIFICATIONS T

§

A

Parameter

Resolution

Min

Typ*

Max

Units**

Notes

256

8

256

8

Levels

Bits

g

Absolute Error (Ch 2–7)

Absolute Error (Ch 0 and 1)

Full Scale Error

0

1

2

LSB

g

1

Zero Offset Error

g

Non-Linearity

0

1

Differential Non-Linearity

Channel-to-Channel Matching

Repeatability

g

0.25

15

8XC51GB

e

a

0 C to 70 C (Continued)

A/D CONVERTER SPECIFICATIONS T

§

A

Parameter

Min

Typ*

Max

Units**

Notes

Temperature Coefficients:

Offset

Full Scale

0.003

LSB/ C

§

LSB/ C

§

Differential Non-Linearity

LSB/ C

§

Input Capacitance

Off Isolation

3

pF

dB

X

b

60

(8, 9)

(8)

b

Feedthrough

60

V

Power Supply Rejection

(8)

CC

Input Resistance to

Sample-and-Hold Capacitor

750

0

1.2K

3.0

DC Input Leakage

mA

NOTES:

*These values are expected for most parts at 25 C

§

**AN ‘‘LSB’’ as used here, has a value of approximately 20 mV.

8. DC to 100 KHz

9. Multiplexer Break-Before-Make Guaranteed.

10. There is no indication when a single A/D conversion is complete. Please refer to the 8XC51GB Hardware Description on

how to read a single A/D conversion.

e

11. T

12 TCLCL

CY

A/D Conversion Time

Per Channel 26 T

8 Conversions

Notes

(10, 11)

(11)

CY

208 T

CY

16

8XC51GB

PROGRAMMING THE OTP

DEFINITION OF TERMS

The part must be running with a 4 MHz to 6 MHz

oscillator. The address of a location to be pro-

grammed is applied to address lines while the code

byte to be programmed in that location is applied to

data lines. Control and program signals must be held

ADDRESS LINES: P1.0–P1.7, P2.0–P2.4, respec-

tively for A0–A12.

DATA LINES: P0.0–P0.7 for D0–D7.

at the levels indicated in Table 2. Normally EA/V

CONTROL SIGNALS: RST, PSEN, P2.6, P2.7, P3.3,

P3.6, P3.7

PP

is held at logic high until just before ALE/PROG is to

be pulsed. The EA/V is raised to V , ALE/PROG

is pulsed low and then EA/V is returned to a high

PP

PROGRAM SIGNALS: ALE/PROG, EA/V

PP

(also refer to timing diagrams).

NOTE:

maximum for any amount of

Exceeding the V

PP

time could damage the device permanently. The

source must be well regulated and free of

glitches.

V

PP

272337–20

*See Table 2 for proper input on these pins.

Figure 11. Programming the OTP

Table 2. OTP Programming Modes

ALE/

EA/

Mode

RST

PSEN

P2.6

P2.7

P3.3

P3.6

P3.7

PROG

V

PP

Program Code Data

Verify Code Data

L

ß

H

12.75V

H

L

H

L

H

L

H

L

H

Program Encryption

Array Address 0–3FH

ß

12.75V

H

Program Lock

Bits

Bit 1

L

ß

H

12.75V

H

L

H

L

H

L

H

L

H

L

Bit 2

Bit 3

L

H

L

Read Signature Byte

H

L

17

8XC51GB

Repeat 1 through 5 changing the address and data

for the entire array or until the end of the object file is

reached.

PROGRAMMING ALGORITHM

Refer to Table 2 and Figures 11 and 12 for address,

data, and control signals set up. To program the

87C51GB the following sequence must be exer-

cised.

PROGRAM VERIFY

1. Input the valid address on the address lines.

2. Input the appropriate data byte on the data lines.

Program verify may be done after each byte that is

programmed, or after a block of bytes that is pro-

grammed. In either case a complete verify of the

array will ensure that it has been programmed cor-

rectly.

3. Activate the correct combination of control sig-

nals.

g

to 12.75V 0.25V.

4. Raise EA/V from V

PP

CC

5. Pulse ALE/PROG 5 times for the OTP array, and

25 times for the encryption table and the lock

bits.

The lock bits cannot be directly verified. Verification

of the lock bits is done by observing that their fea-

tures are enabled. Refer to the Program Lock sec-

tion in this data sheet.

272337–21

Figure 12. Programming Signal’s Waveforms

18

8XC51GB

When using the encryption array feature, one impor-

tant factor needs to be considered. If a code byte

has the value 0FFH, verification of the byte will pro-

ROM and EPROM Lock System

The 87C51GB and the 83C51GB program lock sys-

tems, when programmed, protect the on-board pro-

gram against software piracy.

l

duce the encryption byte value. If a large block ( 64

bytes) of code is left unprogrammed, a verification

routine will display the contents of the encryption

array. For this reason it is strongly recommended

that all unused code bytes be programmed with

some value other than 0FFH, and not all of them the

same value. This practice will ensure the maximum

possible program protection.

The 83C51GB has a one-level program lock system

and a 64-byte encryption table. See line 2 of Table

3. If program protection is desired, the user submits

the encryption table with their code, and both the

lock bit and encryption array are programmed by the

factory. The encryption array is not available without

the lock bit. For the lock bit to be programmed, the

user must submit an encryption table.

Program Lock Bits

The 87C51GB has 3 programmable lock bits that

when programmed according to Table 3 will provide

different levels of protection for the on-chip code

and data. The 83C51GB has 1 program lock bit.

See line 2 of Table 3.

The 87C51GB has a 3-level program lock system

and a 64-byte encryption array. Since this is an

EPROM device, all locations are user programma-

ble. See Table 3.

Encryption Array

Reading the Signature Bytes

Within the programmable array are 64 bytes of En-

cryption Array that are initially unprogrammed (all

1’s). Every time that a byte is addressed during a

verify, 5 address lines are used to select a byte of

the Encryption Array. This byte is then exclusive-

NOR’ed (XNOR) with the code byte, creating an En-

cryption Verify byte. The algorithm, with the array in

the unprogrammed state (all 1’s), will return the

code in its original, unmodified form. For program-

ming the Encryption Array, refer to Table 2.

The 8XC51GB has 3 signature bytes in locations

30H, 31H, and 60H. To read these bytes follow the

procedure for verify, but activate the control lines

provided in Table 2 for Read Signature Byte.

Contents

Location

87C51GB

83C51GB

30H

31H

60H

89H

58H

EBH

EBH/6BH

Table 3. Program Lock Bits and the Features

*Program Lock Bits

Protection Type

LB1

LB2

LB3

1

2

U

No Program Lock features enabled. (Code verify will

still be encrypted by the Encryption Array if

programmed).

P

U

MOVC instructions executed from external program

memory are disabled from fetching code bytes from

internal memory, EA is sampled and latched on

Reset, and further programming of the EPROM is

disabled.

3

4

P

U

P

Same as 2, also verify is disabled.

Same as 3, also external execution is disabled.

*Any other combination of lock bits is not defined.

19

8XC51GB

OTP PROGRAMMING AND VERIFICATION CHARACTERISTICS

e

0V)

SS

g

(T

A

21 C to 27 C; V

5V

20%; V

§

CC

Symbol

Parameter

Min

Max

13.0

75

Units

V

Programming Supply Voltage

Programming Supply Current

Oscillator Frequency

12.5

PP

I

mA

PP

1/TCLCL

TAVGL

TGHAX

TDVGL

TGHDX

TEHSH

TSHGL

TGHSL

TGLGH

TAVQV

TELQV

TEHQZ

TGHGL

4

6

MHz

Address Setup to PROG Low

Address Hold after PROG

Data Setup to PROG Low

Data Hold after PROG

48TCLCL

10

(Enable) High to V

PP

V

Setup to PROG Low

ms

PP

Hold after PROG

10

PROG Width

90

110

Address to Data Valid

ENABLE Low to Data Valid

Data Float after ENABLE

PROG High to PROG Low

48TCLCL

0

10

ms

PROGRAMMING AND VERIFICATION WAVEFORMS

272337–22

*25 Pulses for Encryption Table and Lock Bits.

20

8XC51GB

Ideal CharacteristicÐA characteristic with its first

e

A/D Glossary of Terms

code transition at V

0.5 LSB, its last code tran-

b

IN

e

widths equal to one LSB.

sition at V

(V

1.5 LSB) and all code

Absolute ErrorÐThe maximum difference between

corresponding actual and ideal code transitions. Ab-

solute Error accounts for all deviations of an actual

converter from an ideal converter.

IN

REF

Input ResistanceÐThe effective series resistance

from the analog input pin to the sample capacitor.

Actual CharacteristicÐThe characteristic of an ac-

tual converter. The characteristic of a given convert-

er may vary over temperature, supply voltage, and

frequency conditions. An actual characteristic rarely

has ideal first and last transition locations or ideal

code widths. It may even vary over multiple conver-

sions under the same conditions.

LSBÐLeast Significant BitÐThe voltage corre-

n

sponding to the full scale voltage divided by 2 ,

where n is the number of bits of resolution of the

converter. For an 8-bit converter with a reference

voltage of 5.12V, one LSB is 20 mV. Note that this is

different than digital LSBs since an uncertainty of

two LSBs, when referring to an A/D converter,

equals 40 mV. (This has been confused with an un-

certainty of two digital bits, which would mean four

counts, or 80 mV).

Break-Before-MakeÐThe property of a multiplexer

which guarantees that a previously selected channel

will be deselected before a new channel is selected

(e.g., the converter will not short inputs together).

MonotonicÐThe property of successive approxi-

mation converters which guarantees that increasing

input voltages produce adjacent codes of increasing

value, and that decreasing input voltages produce

adjacent codes of decreasing value.

Channel-to-Channel MatchingÐThe difference be-

tween corresponding code transitions of actual char-

acteristics taken from different channels under the

same temperature, voltage and frequency condi-

tions.

No Missed CodesÐFor each and every output

code, there exists a unique input voltage range

which produces that code only.

CharacteristicÐA graph of input voltage versus the

resultant output code for an A/D converter. It de-

scribes the transfer function of the A/D converter.

Non-LinearityÐThe maximum deviation of code

transitions of the terminal based characteristic from

the corresponding code transitions of the ideal char-

acteristic.

CodeÐThe digital value output by the converter.

Code CenterÐThe voltage corresponding to the

midpoint between two adjacent code transitions.

Off-IsolationÐAttenuation of a voltage applied on a

deselected channel of the A/D converter. (Also re-

ferred to as Crosstalk.)

Code TransitionÐThe point at which the converter

a

changes from an output code of Q, to a code of Q

1. The input voltage corresponding to a code tran-

sition is defined to be that voltage which is equally

likely to produce either of two adjacent codes.

RepeatabilityÐThe difference between corre-

sponding code transitions from different actual char-

acteristics taken from the same converter on the

same channel at the same temperature, voltage and

frequency conditions.

Code WidthÐThe voltage corresponding to the dif-

ference between two adjacent code transitions.

ResolutionÐThe number of input voltage levels

that the converter can unambiguously distinguish

between. Also defines the number of useful bits of

information which the converter can return.

CrosstalkÐSee ‘‘Off-Isolation’’.

DC Input LeakageÐLeakage current to ground

from an analog input pin.

Sample DelayÐThe delay from receiving the start

conversion signal to when the sample window

opens.

Differential Non-LinearityÐThe difference be-

tween the ideal and actual code widths of the termi-

nal based characteristic.

Sample Delay UncertaintyÐThe variation in the

sample delay.

FeedthroughÐAttenuation of a voltage applied on

the selected channel of the A/D Converter after the

sample window closes.

Sample TimeÐThe time that the sample window is

open.

Full Scale ErrorÐThe difference between the ex-

pected and actual input voltage corresponding to

the full scale code transition.

Sample Time UncertaintyÐThe variation in the

sample time.

21

8XC51GB

Sample WindowÐBegins when the sample capaci-

tor is attached to a selected channel and ends when

the sample capacitor is disconnected from the se-

lected channel.

The following differences exist between the

270869-002 data sheet and the previous version

(270869-001):

1. Changed data sheet status from ‘‘Product Pre-

view’’ to ‘‘Advance Information’’ and updated as-

sociated notices.

Successive ApproximationÐAn A/D conversion

method which uses a binary search to arrive at the

best digital representation of an analog input.

2. Asynchronous port reset was added to RESET

pin description.

Temperature CoefficientsÐChange in the stated

variable per degree centrigrade temperature

change. Temperature coefficients are added to the

typical values of a specification to see the effect of

temperature drift.

3. ALE disable paragraph was added to ALE pin de-

scription.

4. C , C guidelines clarified in Figure 4.

2

1

5. Operating Conditions heading was added.

6. Maximum I per I/O pin was added to Absolute

OL

Maximum Ratings.

Terminal Based CharacteristicÐAn actual charac-

teristic which has been rotated and translated to re-

move zero offset and full scale error.

7. VT , VT , V

b

, V , and V removed.

HYS OL2 TL

a

8. V value for ALE included with V

OL

.

OL1

V

CC

line to the A/D converter.

RejectionÐAttenuation of noise on the V

9. V

and V

added.

CC

IL1

IL2

10. RRST minimum changed from 40K to 50K.

RRST maximum changed from 225K to 300K.

Zero OffsetÐThe difference between the expected

and actual input voltage corresponding to the first

code transition.

11. I maximum changed from 200 mA to 50 mA.

PD

12. I maximum changed from 15 mA to 18 mA.

DL

13. Typical values for I , I , I , and I

PD DL CC

re-

REF

moved.

DATA SHEET REVISION SUMMARY

14. Note 3 (page 9) was reworded.

15. SEP AC Timings added.

The following differences exist between this data-

sheet and the previous version (270869-003):

16. A/D Absolute Error for Channels

g

changed to 2 LSB.

0 and

1

1. Merged 87C51GB Express (270889-001).

2. New order number 272337-001.

17. T clarified.

CY

18. Encryption array paragraph was added.

The following differences exist between the 270869-

003 data sheet and the previous version (270869-

002):

19. Corrected pin numbers on Figure 11 to reflect

PLCC package.

1. Changed data sheet status from ‘‘Advance Infor-

mation’’ to ‘‘Preliminary’’ and updated associated

notices.

2. Added 83C51GB throughout.

3. Added Package and Process Information.

g

4. Clarified 2 LSB accuracy for channels 0 and 1

in A/D Converter Section.

5. Added ‘‘ROM and EPROM Lock System’’ section

and added 83C51GB to ‘‘Program Lock Bits’’

section.

6. Modified Signature Bytes Table.

22


型号：	80C51GB
厂家：	INTEL
描述：	CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER CHMOS单片8位微控制器微控制器
文件：	总22页 (文件大小：313K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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