80C187_技术文档

80C187

80-BIT MATH COPROCESSOR

Y

High Performance 80-Bit Internal

Architecture

Expands 80C186’s Data Types to

Include 32-, 64-, 80-Bit Floating-Point,

32-, 64-Bit Integers and 18-Digit BCD

Operands

Implements ANSI/IEEE Standard 754-

1985 for Binary Floating-Point

Arithmetic

Y

Directly Extends 80C186’s Instruction

Set to Trigonometric, Logarithmic,

Exponential, and Arithmetic

Y

Upward Object-Code Compatible from

8087

Instructions for All Data Types

Fully Compatible with 387DX and 387SX

Math Coprocessors. Implements all 387

Architectural Enhancements over 8087

Full-Range Transcendental Operations

for SINE, COSINE, TANGENT,

ARCTANGENT, and LOGARITHM

Y

Directly Interfaces with 80C186 CPU

Y

Built-In Exception Handling

80C186/80C187 Provide a Software/

Binary Compatible Upgrade from

80186/82188/8087 Systems

Eight 80-Bit Numeric Registers, Usable

as Individually Addressable General

Registers or as a Register Stack

Y

Available in 40-Pin CERDIP and 44-Pin

PLCC Package

Ý

(See Packaging Outlines and Dimensions, Order 231369)

The Intel 80C187 is a high-performance math coprocessor that extends the architecture of the 80C186 with

floating-point, extended integer, and BCD data types. A computing system that includes the 80C187 fully

conforms to the IEEE Floating-Point Standard. The 80C187 adds over seventy mnemonics to the instruction

set of the 80C186, including support for arithmetic, logarithmic, exponential, and trigonometric mathematical

operations. The 80C187 is implemented with 1.5 micron, high-speed CHMOS III technology and packaged in

both a 40-pin CERDIP and a 44-pin PLCC package. The 80C187 is upward object-code compatible from the

8087 math coprocessor and will execute code written for the 80387DX and 80387SX math coprocessors.

*Other brands and names are the property of their respective owners.

Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or

copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make

changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.

©

COPYRIGHT INTEL CORPORATION, 1995

November 1992

Order Number: 270640-004

80C187

Figure 1. 80C187 Block Diagram

2

80C187

80C187 Data Registers

64 63

79

78

EXPONENT

0

R0

R1

R2

R3

R4

R5

R6

R7

SIGN

SIGNIFICAND

15

0

15

0

CONTROL REGISTER

STATUS REGISTER

TAG WORD

INSTRUCTION POINTER

DATA POINTER

Figure 2. Register Set

CPU automatically controls the 80C187 whenever a

numerics instruction is executed. All physical memo-

ry and virtual memory of the CPU are available for

storage of the instructions and operands of pro-

grams that use the 80C187. All memory addressing

modes are available for addressing numerics oper-

ands.

FUNCTIONAL DESCRIPTION

The 80C187 Math Coprocessor provides arithmetic

instructions for a variety of numeric data types. It

also executes numerous built-in transcendental

functions (e.g. tangent, sine, cosine, and log func-

tions). The 80C187 effectively extends the register

and instruction set of the 80C186 CPU for existing

data types and adds several new data types as well.

Figure 2 shows the additional registers visible to pro-

grams in a system that includes the 80C187. Essen-

tially, the 80C187 can be treated as an additional

resource or an extension to the CPU. The 80C186

CPU together with an 80C187 can be used as a sin-

gle unified system.

The end of this data sheet lists by class the instruc-

tions that the 80C187 adds to the instruction set.

NOTE:

The 80C187 Math Coprocessor is also referred to

as a Numeric Processor Extension (NPX) in this

document.

A 80C186 system that includes the 80C187 is com-

pletely upward compatible with software for the

8086/8087.

Data Types

Table 1 lists the seven data types that the 80C187

supports and presents the format for each type. Op-

erands are stored in memory with the least signifi-

cant digit at the lowest memory address. Programs

retrieve these values by generating the lowest ad-

dress. For maximum system performance, all oper-

ands should start at even physical-memory address-

es; operands may begin at odd addresses, but will

require extra memory cycles to access the entire op-

erand.

The 80C187 interfaces only with the 80C186 CPU.

The interface hardware for the 80C187 is not imple-

mented on the 80C188.

PROGRAMMING INTERFACE

The 80C187 adds to the CPU additional data types,

registers, instructions, and interrupts specifically de-

signed to facilitate high-speed numerics processing.

All new instructions and data types are directly sup-

ported by the assembler and compilers for high-level

languages. The 80C187 also supports the full

80387DX instruction set.

Internally, the 80C187 holds all numbers in the ex-

tended-precision real format. Instructions that load

operands from memory automatically convert oper-

ands represented in memory as 16-, 32-, or 64-bit

integers, 32- or 64-bit floating-point numbers, or 18-

digit packed BCD numbers into extended-precision

real format. Instructions that store operands in mem-

ory perform the inverse type conversion.

All communication between the CPU and the

80C187 is transparent to applications software. The

3

80C187

Numeric Operands

Register Set

A typical NPX instruction accepts one or two oper-

ands and produces one (or sometimes two) results.

In two-operand instructions, one operand is the con-

tents of an NPX register, while the other may be a

memory location. The operands of some instructions

are predefined; for example, FSQRT always takes

the square root of the number in the top stack ele-

ment (refer to the section on Data Registers).

Figure 2 shows the 80C187 register set. When an

80C187 is present in a system, programmers may

use these registers in addition to the registers nor-

mally available on the CPU.

DATA REGISTERS

80C187 computations use the extended-precision

real data type.

Table 1. Data Type Representation in Memory

270640–2

NOTES:

e

Decimal digit (two per byte)

e

Negative)

1. S

2. d

Sign bit (0

e

Positive, 1

n

e

3. X

U

4.

5. I

Bits have no significance; 80C187 ignores when loading, zeros when storing

Position of implicit binary point

Integer bit of significand; stored in temporary real, implicit in single and double precision

e

6. Exponent Bias (normalized values):

Single: 127 (7FH)

Double: 1023 (3FFH)

Extended Real: 16383 (3FFFH)

S

b

7. Packed BCD: ( 1) (D . . . D )

17

0

S

8. Real: ( 1) (2

E-BIAS

b

) (F , F . . . )

1

0

4

80C187

The 80C187 register set can be accessed either as

a stack, with instructions operating on the top one or

two stack elements, or as individually addressable

registers. The TOP field in the status word identifies

the current top-of-stack register. A ‘‘push’’ operation

decrements TOP by one and loads a value into the

new top register. A ‘‘pop’’ operation stores the value

from the current top register and then increments

TOP by one. The 80C187 register stack grows

‘‘down’’ toward lower-addressed registers.

Bit 15, the B-bit (busy bit) is included for 8087 com-

patibility only. It always has the same value as the

ES bit (bit 7 of the status word); it does not indicate

the status of the BUSY output of 80C187.

Bits 13–11 (TOP) point to the 80C187 register that

is the current top-of-stack.

The four numeric condition code bits (C –C ) are

0

3

similar to the flags in a CPU; instructions that per-

form arithmetic operations update these bits to re-

flect the outcome. The effects of these instructions

on the condition code are summarized in Tables 2

through 5.

Instructions may address the data registers either

implicitly or explicitly. Many instructions operate on

the register at the TOP of the stack. These instruc-

tions implicitly address the register at which TOP

points. Other instructions allow the programmer to

explicitly specify which register to use. This explicit

addressing is also relative to TOP.

Bit 7 is the error summary (ES) status bit. This bit is

set if any unmasked exception bit is set; it is clear

otherwise. If this bit is set, the ERROR signal is as-

serted.

TAG WORD

Bit 6 is the stack flag (SF). This bit is used to distin-

guish invalid operations due to stack overflow or un-

derflow from other kinds of invalid operations. When

The tag word marks the content of each numeric

data register, as Figure 3 shows. Each two-bit tag

represents one of the eight data registers. The prin-

cipal function of the tag word is to optimize the

NPX’s performance and stack handling by making it

possible to distinguish between empty and nonemp-

ty register locations. It also enables exception han-

dlers to identify special values (e.g. NaNs or denor-

mals) in the contents of a stack location without the

need to perform complex decoding of the actual

data.

SF is set, bit 9 (C ) distinguishes between stack

e

1

1) and underflow (C

e

overflow (C

0).

1

Figure 4 shows the six exception flags in bits 5–0 of

the status word. Bits 5–0 are set to indicate that the

80C187 has detected an exception while executing

an instruction. A later section entitled ‘‘Exception

Handling’’ explains how they are set and used.

Note that when a new value is loaded into the status

word by the FLDENV or FRSTOR instruction, the

value of ES (bit 7) and its reflection in the B-bit (bit

15) are not derived from the values loaded from

memory but rather are dependent upon the values of

the exception flags (bits 5–0) in the status word and

their corresponding masks in the control word. If ES

is set in such a case, the ERROR output of the

80C187 is activated immediately.

STATUS WORD

The 16-bit status word (in the status register) shown

in Figure 4 reflects the overall state of the 80C187. It

may be read and inspected by programs.

15

0

TAG (7)

TAG (6)

TAG (5)

TAG (4)

TAG (3)

TAG (2)

TAG (1)

TAG (0)

NOTE:

The index i of tag(i) is not top-relative. A program typically uses the ‘‘top’’ field of Status Word to determine

which tag(i) field refers to logical top of stack.

TAG VALUES:

e

00

01

10

11

Valid

Zero

QNaN, SNaN, Infinity, Denormal and Unsupported Formats

Empty

Figure 3. Tag Word

5

80C187

270640–3

ES is set if any unmasked exception bit is set; cleared otherwise.

See Table 2 for interpretation of condition code.

TOP values:

e

000

001

Register 0 is Top of Stack

Register 1 is Top of Stack

#

Register 7 is Top of Stack

e

111

For definitions of exceptions, refer to the section entitled,

‘‘Exception Handling’’

Figure 4. Status Word

6

80C187

CONTROL WORD

The NPX provides several processing options that are selected by loading a control word from memory into

the control register. Figure 5 shows the format and encoding of fields in the control word.

Table 2. Condition Code Interpretation

Instruction

C0(S)

Three Least Significant

Bits of Quotient

C3(Z)

C1(A)

C2(C)

Reduction

FPREM, FPREM1

(See Table 3)

e

0

1

Complete

Incomplete

Q2

Q0

Q1

or O/U

FCOM, FCOMP,

FCOMPP, FTST

FUCOM, FUCOMP,

FUCOMPP, FICOM,

FICOMP

Result of Comparison

(See Table 4)

Zero or

O/U

Operand is not

Comparable (Table 4)

FXAM

Operand Class

(See Table 5)

Sign

or O/U

Operand Class

(Table 5)

FCHS, FABS, FXCH,

FINCSTP, FDECSTP,

Constant Loads,

FXTRACT, FLD,

FILD, FBLD,

Zero

or O/U

UNDEFINED

FSTP (Ext Real)

FIST, FBSTP,

FRNDINT, FST,

FSTP, FADD, FMUL,

FDIV, FDIVR,

Roundup

or O/U

UNDEFINED

Reduction

FSUB, FSUBR,

FSCALE, FSQRT,

FPATAN, F2XM1,

FYL2X, FYL2XP1

FPTAN, FSIN,

FCOS, FSINCOS

Roundup

or O/U,

Undefined

e

0

1

Complete

Incomplete

e

if C2

1

FLDENV, FRSTOR

Each Bit Loaded from Memory

FLDCW, FSTENV,

FSTCW, FSTSW,

FCLEX, FINIT,

FSAVE

UNDEFINED

O/U

When both IE and SF bits of status word are set, indicating a stack exception, this bit distinguishes between

e

stack overflow (C1

1) and underflow (C1

0).

Reduction

If FPREM or FPREM1 produces a remainder that is less than the modulus, reduction is complete. When

reduction is incomplete the value at the top of the stack is a partial remainder, which can be used as input to

further reduction. For FPTAN, FSIN, FCOS, and FSINCOS, the reduction bit is set if the operand at the top of

the stack is too large. In this case the original operand remains at the top of the stack.

When the PE bit of the status word is set, this bit indicates whether one was added to the least significant bit of

the result during the last rounding.

Roundup

UNDEFINED Do not rely on finding any specific value in these bits.

7

80C187

The low-order byte of this control word configures

exception masking. Bits 5–0 of the control word

contain individual masks for each of the six excep-

tions that the 80C187 recognizes.

as the unbiased round to nearest even mode

specified in the IEEE standard. Rounding control

affects only those instructions that perform

rounding at the end of the operation (and thus

can generate a precision exception); namely,

FST, FSTP, FIST, all arithmetic instructions (ex-

cept FPREM, FPREM1, FXTRACT, FABS, and

FCHS), and all transcendental instructions.

The high-order byte of the control word configures

the 80C187 operating mode, including precision,

rounding, and infinity control.

The ‘‘infinity control bit’’ (bit 12) is not meaningful

The precision control (PC) bits (bits 9–8) can be

used to set the 80C187 internal operating preci-

sion of the significand at less than the default of

64 bits (extended precision). This can be useful in

providing compatibility with early generation arith-

metic processors of smaller precision. PC affects

only the instructions ADD, SUB, DIV, MUL, and

SQRT. For all other instructions, either the preci-

sion is determined by the opcode or extended

precision is used.

#

to the 80C187, and programs must ignore its val-

ue. To maintain compatibility with the 8087, this

bit can be programmed; however, regardless of

its value, the 80C187 always treats infinity in the

k

b%

a%

affine sense (

). This bit is initialized

to zero both after a hardware reset and after the

FINIT instruction.

The rounding control (RC) bits (bits 11–10) pro-

vide for directed rounding and true chop, as well

#

Table 3. Condition Code Interpretation after FPREM and FPREM1 Instructions

Condition Code

Interpretation after

FPREM and FPREM1

C2

C3

C1

C0

X

Incomplete Reduction:

Further Iteration Required

for Complete Reduction

1

X

Q1

Q0

Q2

Q MOD 8

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

Complete Reduction:

C0, C3, C1 Contain Three Least

Significant Bits of Quotient

0

Table 4. Condition Code Resulting from Comparison

Order

C3

C2

C0

l

TOP Operand

0

1

0

1

0

1

0

1

k

TOP Operand

e

Unordered

TOP

Operand

8

80C187

Table 5. Condition Code Defining Operand Class

C3

C2

C1

C0

Value at TOP

a

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Unsupported

NaN

a

b

a

b

a

b

a

b

Unsupported

NaN

Normal

Infinity

Normal

Infinity

0

Empty

0

Empty

Denormal

rupt. The CPU return address pushed onto the stack

of the exception handler points to an ESC instruction

(including prefixes). This instruction can be restarted

after clearing the exception condition in the NPX.

FNINIT, FNCLEX, FNSTSW, FNSTENV, and

FNSAVE cannot cause this interrupt.

INSTRUCTION AND DATA POINTERS

Because the NPX operates in parallel with the CPU,

any exceptions detected by the NPX may be report-

ed after the CPU has executed the ESC instruction

which caused it. To allow identification of the failing

numerics instruction, the 80C187 contains registers

that aid in diagnosis. These registers supply the op-

code of the failing numerics instruction, the address

of the instruction, and the address of its numerics

memory operand (if appropriate).

Exception Handling

The 80C187 detects six different exception condi-

tions that can occur during instruction execution. Ta-

ble 6 lists the exception conditions in order of prece-

dence, showing for each the cause and the default

action taken by the 80C187 if the exception is

masked by its corresponding mask bit in the control

word.

The instruction and data pointers are provided for

user-written exception handlers. Whenever the

80C187 executes a new ESC instruction, it saves

the address of the instruction (including any prefixes

that may be present), the address of the operand (if

present), and the opcode.

Any exception that is not masked by the control

word sets the corresponding exception flag of the

status word, sets the ES bit of the status word, and

asserts the ERROR signal. When the CPU attempts

to execute another ESC instruction, interrupt 16 oc-

curs. The exception condition must be resolved via

an interrupt service routine. The return address

pushed onto the CPU stack upon entry to the serv-

ice routine does not necessarily point to the failing

instruction nor to the following instruction. The

80C187 saves the address of the floating-point in-

struction that caused the exception and the address

of any memory operand required by that instruction.

The instruction and data pointers appear in the for-

mat shown by Figure 6. The ESC instruction

FLDENV, FSTENV, FSAVE and FRSTOR are used

to transfer these values between the registers and

memory. Note that the value of the data pointer is

undefined if the prior ESC instruction did not have a

memory operand.

Interrupt Description

CPU interrupt 16 is used to report exceptional condi-

tions while executing numeric programs. Interrupt 16

indicates that the previous numerics instruction

caused an unmasked exception. The address of the

faulty instruction and the address of its operand are

stored in the instruction pointer and data pointer reg-

isters. Only ESC instructions can cause this inter-

If error trapping is required at the end of a series of

numerics instructions (specifically, when the last

ESC instruction modifies memory data and that data

is used in subsequent nonnumerics instructions), it is

necessary to insert the FNOP instruction to force the

80C187 to check its ERROR input.

9

80C187

270640–4

Precision Control

00Ð 24 Bits (Single Precision)

01Ð (Reserved)

10Ð 53 Bits (Double Precision)

11Ð 64 Bits (Extended Precision)

Rounding Control

00Ð Round to Nearest or Even

b%

01Ð Round Down (toward

10Ð Round Up (toward

)

a%

11Ð Chop (Truncate toward Zero)

)

*The ‘‘infinity control’’ bit is not meaningful to the 80C187. To maintain compatibility with the 8087, this bit can be

k

b%

a%

).

programmed; however, regardless of its value, the 80C187 treats infinity in the affine sense (

Figure 5. Control Word

15

7

0

a

CONTROL WORD

0

2

4

6

8

A

C

STATUS WORD

TAG WORD

INSTRUCTION POINTER

15..0

IP

19..16

0

OPCODE

10..0

OPERAND POINTER

15..0

OP

0

19..16

Figure 6. Instruction and Data Pointer Image in Memory

10

80C187

Table 6. Exceptions

Cause

Default Action

Exception

(If Exception is Masked)

Invalid

Operation

Operation on a signalling NaN,

unsupported format, indeterminate

a%

Result is a quiet NaN,

integer indefinite, or

BCD indefinite

%

form (0* , 0/0), (

b%

)

a

(

), etc.), or stack

overflow/underflow (SF is also set)

Denormalized

Operand

At least one of the operands is

denormalized, i.e. it has the smallest

exponent but a nonzero significand

The operand is normalized,

and normal processing

continues

%

Zero Divisor

Overflow

The divisor is zero while the dividend

is a noninfinite, nonzero number

Result is

The result is too large in magnitude

to fit in the specified format

Result is largest finite

%

value or

Underflow

The true result is nonzero but too small

to be represented in the specified format, and,

if underflow exception is masked, denormalization

causes loss of accuracy

Result is denormalized

or zero

Inexact

Result

(Precision)

The true result is not exactly representable

in the specified format (e.g. 1/3);

the result is rounded according to the

rounding mode

Normal processing

continues

Initialization

8087 Compatibility

After FNINIT or RESET, the control word contains

the value 037FH (all exceptions masked, precision

control 64 bits, rounding to nearest) the same values

as in an 8087 after RESET. For compatibility with the

8087, the bit that used to indicate infinity control (bit

12) is set to zero; however, regardless of its setting,

infinity is treated in the affine sense. After FNINIT or

RESET, the status word is initialized as follows:

This section summarizes the differences between

the 80C187 and the 8087. Many changes have been

designed into the 80C187 to directly support the

IEEE standard in hardware. These changes result in

increased performance by elminating the need for

software that supports the standard.

GENERAL DIFFERENCES

All exceptions are set to zero.

#

The 8087 instructions FENI/FNENI and FDISI/

FNDISI perform no useful function in the 80C187

Numeric Processor Extension. They do not alter the

state of the 80C187 Numeric Processor Extension.

(They are treated similarly to FNOP, except that

ERROR is not checked.) While 8086/8087 code

containing these instructions can be executed on

the 80C186/80C187, it is unlikely that the exception-

handling routines containing these instructions will

be completely portable to the 80C187 Numeric Proc-

essor Extension.

Stack TOP is zero, so that after the first push the

stack top will be register seven (111B).

#

The condition code C –C is undefined.

0

#

3

The B-bit is zero.

The tag word contains FFFFH (all stack locations

are empty).

80C186/80C187 initialization software should exe-

cute an FNINIT instruction (i.e. an FINIT without a

preceding WAIT) after RESET. The FNINIT is not

strictly required for 80C187 software, but Intel

recommends its use to help ensure upward compati-

bility with other processors.

The 80C187 differs from the 8087 with respect to

instruction, data, and exception synchronization. Ex-

cept for the processor control instructions, all of the

80C187 numeric instructions are automatically syn-

chronized by the 80C186 CPU. When necessary, the

11

80C187

80C186 automatically tests the BUSY line from the

80C187 Numeric Processor Extension to ensure that

the 80C187 Numeric Processor Extension has com-

pleted its previous instruction before executing the

next ESC instruction. No explicit WAIT instructions

are required to assure this synchronization. For the

8087 used with 8086 and 8088 CPUs, explicit WAITs

are required before each numeric instruction to en-

sure synchronization. Although 8086/8087 pro-

grams having explicit WAIT instructions will execute

on the 80C186/80C187, these WAIT instructions

are unnecessary.

2. The 80C187 Numeric Processor Extension sig-

nals exceptions through a dedicated ERROR line

to the CPU. The 80C187 error signal does not

pass through an interrupt controller (the 8087 INT

signal does). Therefore, any interrupt-controller-

oriented instructions in numerics exception han-

dlers for the 8086/8087 should be deleted.

3. Interrupt vector 16 must point to the numerics ex-

ception handling routine.

4. The ESC instruction address saved in the 80C187

Numeric Processor Extension includes any lead-

ing prefixes before the ESC opcode. The corre-

sponding address saved in the 8087 does not

include leading prefixes.

The 80C187 supports only affine closure for infinity

arithmetic, not projective closure.

5. When the overflow or underflow exception is

masked, the 80C187 differs from the 8087 in

rounding when overflow or underflow occurs. The

80C187 produces results that are consistent with

the rounding mode.

Operands for FSCALE and FPATAN are no longer

%

FPTAN accept a wider range of operands.

g

restricted in range (except for

); F2XM1 and

Rounding control is in effect for FLD constant.

6. When the underflow exception is masked, the

80C187 sets its underflow flag only if there is also

a loss of accuracy during denormalization.

Software cannot change entries of the tag word to

values (other than empty) that differ from actual reg-

ister contents.

7. Fewer invalid-operation exceptions due to denor-

mal operands, because the instructions FSQRT,

FDIV, FPREM, and conversions to BCD or to inte-

ger normalize denormal operands before pro-

ceeding.

After reset, FINIT, and incomplete FPREM, the

80C187 resets to zero the condition code bits C –

3

C

0

of the status word.

8. The FSQRT, FBSTP, and FPREM instructions

may cause underflow, because they support de-

normal operands.

In conformance with the IEEE standard, the 80C187

does not support the special data formats

pseudozero, pseudo-NaN, pseudoinfinity, and un-

normal.

9. The denormal exception can occur during the

transcendental instructions and the FXTRACT in-

struction.

The denormal exception has a different purpose on

the 80C187. A system that uses the denormal-ex-

ception handler solely to normalize the denormal op-

erands, would better mask the denormal exception

on the 80C187. The 80C187 automatically normal-

izes denormal operands when the denormal excep-

tion is masked.

10. The denormal exception no longer takes prece-

dence over all other exceptions.

11. When the denormal exception is masked, the

80C187 automatically normalizes denormal op-

erands. The 8087 performs unnormal arithmetic,

which might produce an unnormal result.

12. When the operand is zero, the FXTRACT in-

struction reports a zero-divide exception and

b%

EXCEPTIONS

leaves

in ST(1).

A number of differences exist due to changes in the

IEEE standard and to functional improvements to

the architecture of the 80C186/80C187:

13. The status word has a new bit (SF) that signals

when invalid-operation exceptions are due to

stack underflow or overflow.

1. The 80C186/80C187 traps exceptions only on

the next ESC instruction; i.e. the 80C186 does not

notice unmasked 80C187 exceptions on the

80C186 ERROR input line until a later numerics

instruction is executed. Because the 80C186

does not sample ERROR on WAIT and FWAIT

instructions, programmers should place an FNOP

instruction at the end of a sequence of numerics

instructions to force the 80C186 to sample its

ERROR input.

14. FLDextended precision no longer reports denor-

mal exceptions, because the instruction is not

numeric.

15. FLD single/double precision when the operand

is denormal converts the number to extended

precision and signals the denormalized oper-

12

80C187

and exception. When loading a signalling NaN,

FLD single/double precision signals an invalid-

operand exception.

(ST(0) and ST(1) contain the scaled and scaling

operands respectively):

%

FSCALE (0,

tion exception.

) generates the invalid opera-

#

16. The 80C187 only generates quiet NaNs (as on

the 8087); however, the 80C187 distinguishes

between quiet NaNs and signalling NaNs. Sig-

nalling NaNs trigger exceptions when they are

used as operands; quiet NaNs do not (except for

FCOM, FIST, and FBSTP which also raise IE for

quiet NaNs).

b%

FSCALE (finite,

same sign as the scaled operand.

) generates zero with the

a%

FSCALE (finite,

same sign as the scaled operand.

%

with the

) generates

The 8087 returns zero in the first case and rais-

es the invalid-operation exception in the other

cases.

17. When stack overflow occurs during FPTAN and

overflow is masked, both ST(0) and ST(1) con-

tain quiet NaNs. The 8087 leaves the original

operand in ST(1) intact.

19. The 80C187 returns signed infinity/zero as the

unmasked response to massive overflow/under-

flow. The 8087 supports a limited range for the

scaling factor; within this range either massive

overflow/underflow do not occur or undefined

results are produced.

%

(ST(0), ST(1) instruction behaves as follows

g

18. When the scaling factor is

, the FSCALE

Table 7. Pin Summary

Function

Active

State

Input/

Name

Output

CLK

CKM

RESET

CLocK

ClocKing Mode

System reset

I

High

PEREQ

Processor Extension

REQuest

Busy status

O

BUSY

ERROR

High

Low

O

Error status

D

–D

Data pins

Numeric Processor ReaD

Numeric Processor WRite

High

Low

I/O

15

0

NPRD

NPWR

I

Ý

NPS1

NPS2

CMD0

CMD1

NPX select

1

2

Low

High

I

CoMmanD 0

CoMmanD 1

V

System power

System ground

I

CC

SS

13

80C187

HARDWARE INTERFACE

In the following description of hardware interface, an

overbar above a signal name indicates that the ac-

tive or asserted state occurs when the signal is at a

low voltage. When no overbar is present above the

signal name, the signal is asserted when at the high

voltage level.

Signal Description

In the following signal descriptions, the 80C187 pins

are grouped by function as follows:

1. Execution ControlÐ CLK, CKM, RESET

2. NPX HandshakeÐ PEREQ, BUSY, ERROR

3. Bus Interface PinsÐ D –D , NPWR, NPRD

15 0

4. Chip/Port SelectÐ NPS1, NPS2, CMD0, CMD1

5. Power SuppliesÐ V , V

CC SS

Table 7 lists every pin by its identifier, gives a brief

description of its function, and lists some of its char-

acteristics. Figure 7 shows the locations of pins on

the CERDIP package, while Figure 8 shows the loca-

tions of pins on the PLCC package. Table 8 helps to

locate pin identifiers in Figures 7 and 8.

270640–5

e

*N.C.

Pin Not Connected

Clock (CLK)

Figure 7. CERDIP Pin Configuration

This input provides the basic timing for internal oper-

ation. This pin does not require MOS-level input; it

will operate at either TTL or MOS levels up to the

maximum allowed frequency. A minimum frequency

must be provided to keep the internal logic properly

functioning. Depending on the signal on CKM, the

signal on CLK can be divided by two to produce the

internal clock signal (in which case CLK may be up

to 32 MHz in frequency), or can be used directly (in

which case CLK may be up to 12.5 MHz).

Clocking Mode (CKM)

This pin is a strapping option. When it is strapped to

V

(HIGH), the CLK input is used directly; when

strapped to V (LOW), the CLK input is divided by

CC

SS

two to produce the internal clock signal. During the

RESET sequence, this input must be stable at least

four internal clock cycles (i.e. CLK clocks when CKM

c

RESET goes LOW.

is HIGH; 2

CLK clocks when CKM is LOW) before

270640–6

e

*N.C.

Pin Not Connected

**‘‘Top View’’ means as the package is seen from the

component side of the board.

Figure 8. PLCC Pin Configuration

14

80C187

Table 8. PLCC Pin Cross-Reference

CERDIP Package

Pin Name

PLCC Package

BUSY

CKM

CLK

25

39

28

44

32

29

36

32

CMD0

CMD1

31

23

35

26

D

0

22

21

25

24

1

2

20

19

22

21

3

4

18

17

20

19

5

6

16

15

18

17

7

8

14

12

16

14

9

10

11

12

13

14

15

11

8

13

9

7

8

6

7

5

26

5

29

ERROR

No Connect

NPRD

2

27

6, 11, 23, 33, 40

30

NPS1

NPS2

34

33

38

37

NPWR

PEREQ

RESET

28

24

31

27

35

3, 9, 13, 37, 40

1, 4, 10, 30, 36, 38

39

1, 3, 10, 15, 42

2, 4, 12, 34, 41, 43

V

CC

SS

Table 9. Output Pin Status during Reset

System Reset (RESET)

Output

Value

A LOW to HIGH transition on this pin causes the

80C187 to terminate its present activity and to enter

a dormant state. RESET must remain active (HIGH)

for at least four internal clock periods. (The relation

of the internal clock period to CLK depends on

CLKM; the internal clock may be different from that

of the CPU.) Note that the 80C187 is active internal-

ly for 25 clock periods after the termination of the

RESET signal (the HIGH to LOW transition of RE-

SET); therefore, the first instruction should not be

written to the 80C187 until 25 internal clocks after

the falling edge of RESET. Table 9 shows the status

of the output pins during the reset sequence. After a

reset, all output pins return to their inactive states.

Pin Name

during Reset

BUSY

HIGH

ERROR

PEREQ

LOW

D

–D

TRI-STATE OFF

15

0

Processor Extension Request (PEREQ)

When active, this pin signals to the CPU that the

80C187 is ready for data transfer to/from its data

FIFO. When there are more than five data transfers,

15

80C187

PEREQ is deactivated after the first three transfers

and subsequently after every four transfers. This sig-

nal always goes inactive before BUSY goes inactive.

data transfer involving the 80C187 occurs unless the

device is selected by these lines.

Command Selects (CMD0 and CMD1)

Busy Status (BUSY)

These pins along with the select pins allow the CPU

to direct the operation of the 80C187.

When active, this pin signals to the CPU that the

80C187 is currently executing an instruction. This

pin is active HIGH. It should be connected to the

80C186’s TEST/BUSY pin. During the RESET se-

quence this pin is HIGH. The 80C186 uses this

HIGH state to detect the presence of an 80C187.

System Power (V

)

CC

a

g

System power provides the 5V 10% DC supply

input. All V pins should be tied together on the

CC

circuit board and local decoupling capacitors should

be used between V and V

Error Status (ERROR)

.

SS

CC

This pin reflects the ES bit of the status register.

When active, it indicates that an unmasked excep-

tion has occurred. This signal can be changed to

inactive state only by the following instructions (with-

System Ground (V

)

SS

All V

pins should be tied together on the circuit

SS

board and local decoupling capacitors should be

used between V and V

out

a

preceding WAIT): FNINIT, FNCLEX,

.

SS

CC

FNSTENV, FNSAVE, FLDCW, FLDENV, and

FRSTOR. This pin should be connected to the

ERROR pin of the CPU. ERROR can change state

only when BUSY is active.

Processor Architecture

As shown by the block diagram (Figure 1), the

80C187 NPX is internally divided into three sections:

the bus control logic (BCL), the data interface and

control unit, and the floating-point unit (FPU). The

FPU (with the support of the control unit which con-

tains the sequencer and other support units) exe-

cutes all numerics instructions. The data interface

and control unit is responsible for the data flow to

and from the FPU and the control registers, for re-

ceiving the instructions, decoding them, and se-

quencing the microinstructions, and for handling

some of the administrative instructions. The BCL is

responsible for CPU bus tracking and interface.

Data Pins (D –D )

15 0

These bidirectional pins are used to transfer data

and opcodes between the CPU and 80C187. They

are normally connected directly to the correspond-

ing CPU data pins. Other buffers/drivers driving the

local data bus must be disabled when the CPU

reads from the NPX. High state indicates a value of

one. D is the least significant data bit.

0

Numeric Processor Write (NPWR)

A signal on this pin enables transfers of data from

the CPU to the NPX. This input is valid only when

NPS1 and NPS2 are both active.

BUS CONTROL LOGIC

The BCL communicates solely with the CPU using

I/O bus cycles. The BCL appears to the CPU as a

special peripheral device. It is special in two re-

spects: the CPU initiates I/O automatically when it

encounters ESC instructions, and the CPU uses re-

served I/O addresses to communicate with the BCL.

The BCL does not communicate directly with memo-

ry. The CPU performs all memory access, transfer-

ring input operands from memory to the 80C187 and

transferring outputs from the 80C187 to memory. A

dedicated communication protocol makes possible

high-speed transfer of opcodes and operands be-

tween the CPU and 80C187.

Numeric Processor Read (NPRD)

A signal on this pin enables transfers of data from

the NPX to the CPU. This input is valid only when

NPS1 and NPS2 are both active.

Numeric Processor Selects (NPS1 and NPS2)

Concurrent assertion of these signals indicates that

the CPU is performing an escape instruction and en-

ables the 80C187 to execute that instruction. No

16

80C187

Table 10. Bus Cycles Definition

NPS1

NPS2

CMD0

CMD1

NPRD

NPWR

Bus Cycle Type

x

1

0

x

80C187 Not Selected

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Opcode Write to 80C187

CW or SW Read from 80C187

Read Data from 80C187

Write Data to 80C187

Write Exception Pointers

Reserved

Read Opcode Status

Reserved

data path in the FPU is 84 bits wide (68 significant

bits, 15 exponent bits, and a sign bit) which allows

internal operand transfers to be performed at very

high speeds.

DATA INTERFACE AND CONTROL UNIT

The data interface and control unit latches the data

and, subject to BCL control, directs the data to the

FIFO or the instruction decoder. The instruction de-

coder decodes the ESC instructions sent to it by the

CPU and generates controls that direct the data flow

in the FIFO. It also triggers the microinstruction se-

quencer that controls execution of each instruction.

If the ESC instruction is FINIT, FCLEX, FSTSW,

FSTSW AX, FSTCW, FSETPM, or FRSTPM, the

control executes it independently of the FPU and the

sequencer. The data interface and control unit is the

one that generates the BUSY, PEREQ, and ERROR

signals that synchronize 80C187 activities with the

CPU.

Bus Cycles

The pins NPS1, NPS2, CMD0, CMD1, NPRD and

NPWR identify bus cycles for the NPX. Table 10 de-

fines the types of 80C187 bus cycles.

80C187 ADDRESSING

The NPS1, NPS2, CMD0, and CMD1 signals allow

the NPX to identify which bus cycles are intended for

the NPX. The NPX responds to I/O cycles when the

I/O address is 00F8H, 00FAH, 00FCH, or 00FEH.

The correspondence betwen I/O addresses and

control signals is defined by Table 11. To guarantee

correct operation of the NPX, programs must not

perform any I/O operations to these reserved port

addresses.

FLOATING-POINT UNIT

The FPU executes all instructions that involve the

register stack, including arithmetic, logical, transcen-

dental, constant, and data transfer instructions. The

Table 11. I/O Address Decoding

80C187 Select and Command Inputs

I/O Address

(Hexadecimal)

NPS2

NPS1

CMD1

CMD0

00F8

00FA

00FC

00FE

1

0

1

0

1

0

1

17

80C187

CPU/NPX SYNCHRONIZATION

OPCODE INTERPRETATION

The pins BUSY, PEREQ, and ERROR are used for

various aspects of synchronization between the

CPU and the NPX.

The CPU and the NPX use a bus protocol that

adapts to the numerics opcode being executed.

Only the NPX directly interprets the opcode. Some

of the results of this interpretation are relevant to the

CPU. The NPX records these results (opcode status

information) in an internal 16-bit register. The

80C186 accesses this register only via reads from

NPX port 00FEH. Tables 10 and 11 define the signal

combinations that correspond to each of the follow-

ing steps.

BUSY is used to synchronize instruction transfer

from the CPU to the 80C187. When the 80C187 rec-

ognizes an ESC instruction, it asserts BUSY. For

most ESC instructions, the CPU waits for the

80C187 to deassert BUSY before sending the new

opcode.

1. The CPU writes the opcode to NPX port 00F8H.

This write can occur even when the NPX is busy

or is signalling an exception. The NPX does not

necessarily begin executing the opcode immedi-

ately.

The NPX uses the PEREQ pin of the CPU to signal

that the NPX is ready for data transfer to or from its

data FIFO. The NPX does not directly access mem-

ory; rather, the CPU provides memory access serv-

ices for the NPX.

2. The CPU reads the opcode status information

from NPX port 00FEH.

Once the CPU initiates an 80C187 instruction that

has operands, the CPU waits for PEREQ signals that

indicate when the 80C187 is ready for operand

transfer. Once all operands have been transferred

(or if the instruction has no operands) the CPU con-

tinues program execution while the 80C187 exe-

cutes the ESC instruction.

3. The CPU initiates subsequent bus cycles accord-

ing to the opcode status information. The opcode

status information specifies whether to wait until

the NPX is not busy, when to transfer exception

pointers to port 00FCH, when to read or write op-

erands and results at port 00FAH, etc.

In 8086/8087 systems, WAIT instructions are re-

quired to achieve synchronization of both com-

mands and operands. The 80C187, however, does

not require WAIT instructions. The WAIT or FWAIT

instruction commonly inserted by high-level compil-

ers and assembly-language programmers for excep-

tion synchronization is not treated as an instruction

by the 80C186 and does not provide exception trap-

ping. (Refer to the section ‘‘System Configuration for

8087-Compatible Exception Trapping’’.)

For most instructions, the NPX does not start exe-

cuting the previously transferred opcode until the

CPU (guided by the opcode status information) first

writes exception pointer information to port 00FCH

of the NPX. This protocol is completely transparent

to programmers.

Bus Operation

With respect to bus interface, the 80C187 is fully

asynchronous with the CPU, even when it operates

from the same clock source as the CPU. The CPU

initiates a bus cycle for the NPX by activating both

NPS1 and NPS2, the NPX select signals. During the

CLK period in which NPS1 and NPS2 are activated,

the 80C187 also examines the NPRD and NPRW

Once it has started to execute a numerics instruction

and has transferred the operands from the CPU, the

80C187 can process the instruction in parallel with

and independent of the host CPU. When the NPX

detects an exception, it asserts the ERROR signal,

which causes a CPU interrupt.

18

80C187

input signals to determine whether the cycle is a

read or a write cycle and examines the CMD0 and

CMD1 inputs to determine whether an opcode, oper-

and, or control/status register transfer is to occur.

The 80C187 activates its BUSY output some time

after the leading edge of the NPRD or NPRW signal.

Input and ouput data are referenced to the trailing

edges of the NPRD and NPRW signals.

The 80C186 pin MCS3/NPS is connected to

NPS1; NPS2 is connected to V . Note that if the

80C186 CPU’s DEN signal is used to gate exter-

nal data buffers, it must be combined with the

NPS signal to insure numeric accesses will not

activate these buffers.

#

CC

The NPRD and NPRW pins are connected to the

RD and WR pins of the 80C186.

#

CMD1 and CMD0 come from the latched A and

2

The 80C187 activates the PEREQ signal when it is

ready for data transfer. The 80C187 deactivates

PEREQ automatically.

A

of the 80C186, respectively.

1

The 80C187 BUSY output connects to the

80C186 TEST/BUSY input. During RESET, the

signal at the 80C187 BUSY output automatically

programs the 80C186 to use the 80C187.

System Configuration

The 80C187 can use the CLKOUT signal of the

80C186 to conserve board space when operating

at 12.5 MHz or less. In this case, the 80C187

CKM input must be pulled HIGH. For operation in

excess of 12.5 MHz, a double-frequency external

oscillator for CLK input is needed. In this case,

CKM must be pulled LOW.

#

The 80C187 can be connected to the 80C186 CPU

as shown by Figure 9. (Refer to the 80C186 Data

Sheet for an explanation of the 80C186’s signals.)

This interface has the following characteristics:

The 80C187’s NPS1, ERROR, PEREQ, and

BUSY pins are connected directly to the corre-

sponding pins of the 80C186.

#

270640–7

Figure 9. 80C186/80C187 System Configuration

19

80C187

For exception handling compatible with the 80186/

82188/8087, the 80C186 can be wired to recognize

exceptions through an external interrupt pin, as Fig-

ure 10 shows. (Refer to the 80C186 Data Sheet for

an explanation of the 80C186’s signals.) With this

arrangement, a flip-flop is needed to latch BUSY

upon assertion of ERROR. The latch can then be

cleared during the exception-handler routine by forc-

ing a PCS pin active. The latch must also be cleared

at RESET in order for the 80C186 to work with the

80C187.

System Configuration for 80186/

80187-Compatible Exception Trapping

When the 80C187 ERROR output signal is connect-

ed directly to the 80C186 ERROR input, floating-

Ý

point exceptions cause interrupt 16. However, ex-

isting software may be programmed to expect float-

ing-point exceptions to be signalled over an external

interrupt pin via an interrupt controller.

270640–8

*For input clocking options, refer to Figure 9.

Figure 10. System Configuration for 8087-Compatible Exception Trapping

20

80C187

ELECTRICAL DATA

NOTICE: This is a production data sheet. The specifi-

cations are subject to change without notice.

*WARNING: Stressing the device beyond the ‘‘Absolute

Maximum Ratings’’ may cause permanent damage.

These are stress ratings only. Operation beyond the

‘‘Operating Conditions’’ is not recommended and ex-

tended exposure beyond the ‘‘Operating Conditions’’

may affect device reliability.

Absolute Maximum Ratings*

a

Case Temperature Under Bias (T )ÀÀÀ0 C to 85 C

§

Storage Temperature ÀÀÀÀÀÀÀÀÀÀ 65 C to 150 C

§

C

b

a

§

Voltage on Any Pin

with Respect to GroundÀÀÀÀ 0.5V to V

b

a

0.5V

CC

Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5W

Power and Frequency Requirements

The typical relationship between I

CC

quency of operation F is as follows:

and the fre-

e

a

5

I

55

F mA

*

where F is in MHz.

CC

typ

When the frequency is reduced below the minimum

operating frequency specified in the AC Characteris-

tics table, the internal states of the 80C187 may be-

come indeterminate. The 80C187 clock cannot be

stopped; otherwise, I

beyond what the equation above indicates.

would increase significantly

CC

e

a

0 C to 85 C, V

e a

CC

g

5V 10%

DC Characteristics T

§

C

Symbol

Parameter

Input LOW Voltage

Input HIGH Voltage

Min

Max

Units

Test Conditions

b

a

V

0.5

0.8

V

IL

a

0.5

0.8

2.0

V

IH

CC

b

a

Clock Input LOW Voltage

Clock Input HIGH Voltage

Output LOW Voltage

0.5

ICL

ICH

OL

OH

a

2.0

0.5

CC

e

0.45

I

3.0 mA

OL

e b

Output HIGH Voltage

Power Supply Current

2.4

0.4 mA

OH

I

156

135

mA

16 MHz

12.5 MHz

CC

s

g

I

Input Leakage Current

I/O Leakage Current

Input Capacitance

10

mA

pF

0V

V

CC

LI

IN

s

b

0.45V

V

CC

LO

OUT

e

C

10

F

C

F

C

F

C

1 MHz

IN

I/O or Output Capacitance

Clock Capacitance

12

20

O

CLK

21

80C187

AC Characteristics

e

a

e

All timings are measured at 1.5V unless otherwise specified

g

5V 10%

T

C

0 C to 85 C, V

§

CC

12.5 MHz

16 MHz

Test

Conditions

Symbol

Parameter

Min

Max

(ns)

Min

Max

(ns)

T

(t6)

(t7)

Data Setup to NPWR

Data Hold from NPWR

43

14

33

14

dvwh

whdx

T

(t8)

NPRD Active Time

NPWR Active Time

59

54

rlrh

(t9)

wlwh

T

(t10)

(t11)

Command Valid to NPWR

Command Valid to NPRD

0

avwl

avrl

T

(t12)

Min Delay from PEREQ Active

to NPRD Active

40

30

mhrl

T

(t18)

(t19)

Command Hold from NPWR

Command Hold from NPRD

12

8

whax

rhax

T

(t20)

(t21)

NPRD, NPWR, RESET to

CLK Setup Time

46

26

38

18

Note 1

ivcl

clih

T

NPRD, NPWR, RESET from

CLK Hold Time

T

(t24)

(t25)

RESET to CLK Setup

RESET from CLK Hold

21

14

19

9

Note 1

rscl

clrs

T

(t26)

Command Inactive Time

Write to Write

Read to Read

cmdi

69

59

Read to Write

Write to Read

NOTE:

1. This is an asynchronous input. This specification is given for testing purposes only, to assure recognition at a specific CLK

edge.

22

80C187

Timing Responses

All timings are measured at 1.5V unless otherwise specified

12.5 MHz

16 MHz

Test

Conditions

Symbol

Parameter

Min

Max

(ns)

Min

Max

(ns)

T

(t27)

(t28)

NPRD Inactive to Data Float*

NPRD Active to Data Valid

18

50

18

45

Note 2

Note 3

rhqz

T

rlqv

(t29)

ERROR Active to Busy Inactive

NPWR Active to Busy Active

104

Note 4

Note 5

ilbh

(t30)

(t31)

80

60

wlbv

klml

NPRD or NPWR Active

to PEREQ Inactive

T

(t32)

(t33)

Data Hold from NPRD Inactive

RESET Inactive to BUSY Inactive

2

Note 3

rhqh

80

60

rlbh

NOTES:

*The data float delay is not tested.

2. The float condition occurs when the measured output current is less than I on D –D .

OL 15

0

e

3. D –D loading: C

100 pF.

5. On last data transfer of numeric instruction.

15

0

L

e

4. BUSY loading: C

L

Clock Timings

12.5 MHz

16 MHz*

Test

Conditions

Symbol

Parameter

Min

(ns)

Max

(ns)

Min

Max

(ns)

e

T

(t1a)

(t1B)

CLK Period

CKM

1

0

80

40

250

125

N/A

31.25

N/A

125

Note 6

clcl

e

(t2a)

(t2b)

CLK Low Time

CLK High Time

CKM

1

0

35

9

N/A

7

Note 6

Note 7

clch

chcl

e

(t3a)

(t3b)

CKM

1

0

35

13

N/A

9

Note 6

Note 8

T

(t4)

10

8

Note 9

ch2ch1

ch1ch2

(t5)

Note 10

NOTES:

*16 MHz operation is available only in divide-by-2 mode (CKM strapped LOW).

6. At 1.5V

7. At 0.8V

8. At 2.0V

e

9. CKM

10. CKM

1: 3.7V to 0.8V at 16 MHz, 3.5V to 1.0V at 12.5 MHz

1: 0.8V to 3.7V at 16 MHz, 1.0V to 3.5V at 12.5 MHz

e

23

80C187

AC DRIVE AND MEASUREMENT

POINTSÐCLK INPUT

AC SETUP, HOLD, AND DELAY TIME

MEASUREMENTSÐGENERAL

270640–9

270640–10

AC TEST LOADING ON OUTPUTS

270640–11

DATA TRANSFER TIMING (INITIATED BY CPU)

270640–12

24

80C187

DATA CHANNEL TIMING (INITIATED BY 80C187)

270640–13

ERROR OUTPUT TIMING

270640–14

e

CLK, RESET TIMING (CKM

1)

270640–15

25

80C187

e

CLK, NPRD, NPWR TIMING (CKM

1)

270640–16

e

CLK, RESET TIMING (CKM

0)

270640–17

RESET must meet timing shown to guarantee known phase of internal divide by 2 circuits.

NOTE:

RESET, NPWR, NPRD inputs are asynchronous to CLK. Timing requirements are given for testing purposes only, to assure

recognition at a specific CLK edge.

e

CLK, NPRD, NPWR TIMING (CKM

0)

270640–18

RESET, BUSY TIMING

270640–19

26

80C187

DISP (displacement) is optionally present in instruc-

tions that have MOD and R/M fields. Its presence

depends on the values of MOD and R/M, as for in-

structions of the CPU.

80C187 EXTENSIONS TO THE CPU’s

INSTRUCTION SET

Instructions for the 80C187 assume one of the five

forms shown in Table 12. In all cases, instructions

are at least two bytes long and begin with the bit

pattern 11011B, which identifies the ESCAPE class

of instruction. Instructions that refer to memory oper-

ands specify addresses using the CPU’s addressing

modes.

The instruction summaries that follow assume that

the instruction has been prefetched, decoded, and is

ready for execution; that bus cycles do not require

wait states; that there are no local bus HOLD re-

quests delaying processor access to the bus; and

that no exceptions are detected during instruction

execution. Timings are given in internal 80C187

clocks and include the time for opcode and data

transfer between the CPU and the NPX. If the in-

struction has MOD and R/M fields that call for both

base and index registers, add one clock.

MOD (Mode field) and R/M (Register/Memory spec-

ifier) have the same interpretation as the corre-

sponding fields of CPU instructions (refer to Pro-

grammer’s Reference Manual for the CPU). The

Table 12. Instruction Formats

Instruction

Optional

Field

First Byte

OPA

Second Byte

1

2

3

4

5

11011

15–11

1

OPA

1

MOD

1

OPB

OPB *

R/M

ST (i)

DISP

MF

MOD

d

0

P

1

7

1

6

OPB *

0

1

9

1

5

OP

0

1

10

8

4

3

2

1

0

NOTES:

e

OP

Instruction opcode, possibly split into two fields OPA and OPB

e

MF

Memory Format

d

Destination

0Ð Destination is ST(0)

0Ð Destination is ST(i)

00Ð 32-Bit Real

01Ð 32-Bit Integer

10Ð 64-Bit Real

11Ð 16-Bit Integer

e

R XOR d

0Ð Destination (op) Source

1Ð Source (op) Destination

e

*In FSUB and FDIV, the low-order bit of OPB is the R (reversed) bit

e

Register Stack Element i

P

Pop

0Ð Do not pop stack

1Ð Pop stack after operation

ST(i)

e

000

001

Stack Top

Second Stack Element

e

#

e

ESC

11011

#

e

111

Eighth Stack Element

27

80C187

80C187 Extensions to the 80C186 Instruction Set

Encoding

Clock Count Range

Instruction

Byte

0

Byte

1

Optional

Bytes 2–3

32-Bit

Real

32-Bit

Integer

64-Bit

Real

16-Bit

Integer

DATA TRANSFER

a

e

FLD

Load

Integer/real memory to ST(0)

Long integer memory to ST(0)

Extended real memory to ST(0)

BCD memory to ST(0)

ESC MF 1

ESC 111

ESC 011

ESC 111

ESC 001

MOD 000 R/M

MOD 101 R/M

MOD 100 R/M

11000 ST(i)

DISP

40

65–72

90–101

74

59

67–71

296–305

16

ST(i) to ST(0)

e

FST

Store

ST(0) to integer/real memory

ST(0) to ST(i)

ESC MF 1

ESC 101

MOD 010 R/M

11010 ST(i)

DISP

58

93–107

13

73

80–93

e

FSTP

Store and Pop

ST(0) to integer/real memory

ST(0) to long integer memory

ST(0) to extended real

ST(0) to BCD memory

ST(0) to ST(i)

ESC MF 1

ESC 111

ESC 011

ESC 111

ESC 101

MOD 011 R/M

MOD 111 R/M

MOD 110 R/M

11001 ST (i)

DISP

93–107

116–133

83

542–564

14

e

FXCH

Exchange

ST(i) and ST(0)

ESC 001

11001 ST(i)

20

COMPARISON

e

FCOM

Compare

Integer/real memory to ST(0)

ST(i) to ST(0)

ESC MF 0

ESC 000

MOD 010 R/M

11010 ST(i)

DISP

48

78–85

26

67

77–81

e

FCOMP

Compare and pop

Integer/real memory to ST

ST(i) to ST(0)

ESC MF 0

ESC 000

MOD 011 R/M

11011 ST(i)

78–85

28

e

FCOMPP

Compare and pop twice

ST(1) to ST(0)

ESC 110

ESC 001

ESC 101

1101 1001

1110 0100

11100 ST(i)

28

30

26

e

FTST

Test ST(0)

e

FUCOM

Unordered compare

e

FUCOMP

and pop

Unordered compare

ESC 101

11101 ST(i)

28

e

and pop twice

FUCOMPP

Unordered compare

ESC 010

ESC 001

1110 1001

11100101

28

e

FXAM

Examine ST(0)

32-40

CONSTANTS

e

a

Load 0.0 into ST(0)

FLDZ

FLD1

ESC 001

1110 1110

1110 1000

1110 1011

1110 1001

22

26

42

a

Load 1.0 into ST(0)

e

FLDPI

Load pi into ST(0)

e

FLDL2T

Load log (10) into ST(0)

2

Shaded areas indicate instructions not available in 8087.

NOTE:

a. When loading single- or double-precision zero from memory, add 5 clocks.

28

80C187

80C187 Extensions to the 80C186 Instruction Set (Continued)

Encoding

Clock Count Range

Instruction

Byte

0

Byte

1

Optional

Bytes 2–3

32-Bit

Real

32-Bit

Integer

64-Bit

Real

16-Bit

Integer

CONSTANTS (Continued)

e

FLDL2E

FLDLG2

FLDLN2

Load log (e) into ST(0)

2

ESC 001

1110 1010

1110 1100

1110 1101

42

43

Load log (2) into ST(0)

10

Load log (2) into ST(0)

e

ARITHMETIC

e

FADD

Add

Integer/real memory with ST(0)

ST(i) and ST(0)

ESC MF 0

ESC d P 0

MOD 000 R/M

11000 ST(i)

DISP

44–52

47–57

108

77–92

65–73

b

77–91

25–33

e

FSUB

Subtract

c

Integer/real memory with ST(0)

ST(i) and ST(0)

ESC MF 0

ESC d P 0

MOD 10 R R/M

1110 R R/M

77–92

65–73

d

77–91

28–36

e

FMUL

Multiply

Integer/real memory with ST(0)

ST(i) and ST(0)

ESC MF 0

ESC d P 0

MOD 001 R/M

1100 1 R/M

81–102

68–93

e

82–93

31–59

e

FDIV

Divide

f

g

Integer/real memory with ST(0)

ESC MF 0

ESC d P 0

ESC 001

MOD 11 R R/M

1111 R R/M

1111 1010

140–147

128

142–146

h

ST(i) and ST(0)

90

i

e

FSQRT

Square root

124–131

69–88

e

FSCALE

Scale ST(0) by ST(1)

Partial remainder of

1111 1101

e

FPREM

d

ST(0)

ST(1)

ESC 001

1111 1000

1111 0101

1111 1100

76–157

97–187

68–82

e

FPREM1

(IEEE)

Partial remainder

e

FRNDINT

to integer

Round ST(0)

e

FXTRACT

of ST(0)

Extract components

ESC 001

1111 0100

1110 0001

1110 0000

72–78

24

e

FABS

FCHS

Absolute value of ST(0)

Change sign of ST(0)

26–27

Shaded areas indicate instructions not available in 8087.

NOTES:

b. Add 3 clocks to the range when d

c. Add 1 clock to each range when R

e

1.

e

1.

e

0, 48–56, typical 51).

d. Add 3 clocks to the range when d

0.

e

f. Add 1 clock to the range when R

e

e. typical

54 (When d

e

1.

e

h. Add 3 clocks to the range when d

g. 153–159 when R

1.

e

1.

s

a%

b

i.

0

ST(0)

.

29

80C187

80C187 Extensions to the 80C186 Instruction Set (Continued)

Encoding

Instruction

Clock Count Range

Byte

0

Byte

1

Optional

Bytes 2–3

TRANSCENDENTAL

j

e

FCOS

Cosine of ST(0)

ESC 001

1111 1111

1111 0010

1111 0011

1111 1110

1111 1011

1111 0000

1111 0001

1111 1001

125–774

k

j

e

FPTAN

Partial tangent of ST(0)

Partial arctangent

193–499

e

FPATAN

316–489

j

e

FSIN

Sine of ST(0)

124–773

j

e

FSINCOS

l

Sine and cosine of ST(0)

196–811

ST(0)

2

e

b

1

F2XM1

213–478

122–540

259–549

m

e

FYL2X

ST(1) * log (ST(0))

2

n

e

a

1.0)

FYL2XP1

ST(1) * log (ST(0)

2

PROCESSOR CONTROL

e

FINIT

Initialize NPX

ESC 011

ESC 111

ESC 001

ESC 101

1110 0011

1110 0000

35

17

23

21

e

FSTSW AX

Store status word

e

FLDCW

FSTCW

FSTSW

Load control word

Store control word

Store status word

MOD 101 R/M

MOD 111 R/M

DISP

e

FCLEX

Clear exceptions

ESC 011

ESC 001

ESC 101

ESC 001

ESC 101

ESC 001

1110 0010

MOD 110 R/M

MOD 100 R/M

MOD 110 R/M

MOD 100 R/M

1111 0111

13

146

113

550

482

23

e

FSTENV

FLDENV

Store environment

Load environment

DISP

e

FSAVE

Save state

e

FRSTOR

FINCSTP

FDECSTP

Restore state

e

Increment stack pointer

Decrement stack pointer

e

1111 0110

24

e

FFREE

Free ST(i)

1100 0 ST(i)

1101 0000

20

e

FNOP

No operations

14

Shaded areas indicate instructions not available in 8087.

NOTES:

j. These timings hold for operands in the range x

k

q/4. For operands not in this range, up to 78 clocks may be needed to

l

reduce the operand.

63

s

l. 1.0

k

2

k. 0

b

ST(0)

s

ST(0)

.

1.0.

b%

b

l

s

%

ST(0)

k

s

k

(2))/2,

k

ST(1)

a%

k

m. 0

n. 0

,

.

s

k

a%

.

b%

ST(0)

(2

S

ST(1)

l

DATA SHEET REVISION REVIEW

The following list represents the key differences between the -002 and the -001 version of the 80C187 data

sheet. Please review this summary carefully.

1. Figure 10, titled ‘‘System Configuration for 8087ÐCompatible Exception Trapping’’, was replaced with a

revised schematic. The previous configuration was faulty. Updated timing diagrams on Data Transfer Tim-

ing, Error Output, and RESET/BUSY.

30


型号：	80C187
厂家：	INTEL
描述：	80-BIT MATH COPROCESSOR 80位数学协处理器
文件：	总30页 (文件大小：324K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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