5M160ZM68A5N_技术文档

Section I. MAX V Device Core

This section provides a complete overview of all features relating to the MAX^®V

device family.

This section includes the following chapters:

■

Chapter 1, MAX V Device Family Overview

Chapter 2, MAX V Architecture

Chapter 3, DC and Switching Characteristics for MAX V Devices

May 2011 Altera Corporation

MAX V Device Handbook

I–2

Section I: MAX V Device Core

MAX V Device Handbook

May 2011 Altera Corporation

1. MAX V Device Family Overview

MV51001-1.2

The MAX^®V family of low cost and low power CPLDs offer more density and I/Os

per footprint versus other CPLDs. Ranging in density from 40 to 2,210 logic elements

(LEs) (32 to 1,700 equivalent macrocells) and up to 271 I/Os, MAX V devices provide

programmable solutions for applications such as I/O expansion, bus and protocol

bridging, power monitoring and control, FPGA configuration, and analog IC

interface.

MAX V devices feature on-chip flash storage, internal oscillator, and memory

functionality. With up to 50% lower total power versus other CPLDs and requiring as

few as one power supply, MAX V CPLDs can help you meet your low power design

requirement.

This chapter contains the following sections:

■

“Feature Summary” on page 1–1

“Integrated Software Platform” on page 1–3

“Device Pin-Outs” on page 1–3

“Ordering Information” on page 1–4

Feature Summary

The following list summarizes the MAX V device family features:

■

Low-cost, low-power, and non-volatile CPLD architecture

Instant-on (0.5 ms or less) configuration time

Standby current as low as 25 µA and fast power-down/reset operation

Fast propagation delay and clock-to-output times

Internal oscillator

Emulated RSDS output support with a data rate of up to 200 Mbps

Emulated LVDS output support with a data rate of up to 304 Mbps

Four global clocks with two clocks available per logic array block (LAB)

User flash memory block up to 8 Kbits for non-volatile storage with up to 1000

read/write cycles

■

Single 1.8-V external supply for device core

MultiVolt I/O interface supporting 3.3-V, 2.5-V, 1.8-V, 1.5-V, and 1.2-V logic levels

Bus-friendly architecture including programmable slew rate, drive strength,

bus-hold, and programmable pull-up resistors

■

Schmitt triggers enabling noise tolerant inputs (programmable per pin)

and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at

www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but

reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any

information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device

specifications before relying on any published information and before placing orders for products or services.

MAX V Device Handbook

May 2011

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Chapter 1: MAX V Device Family Overview

Feature Summary

■

I/Os are fully compliant with the PCI-SIG^®PCI Local Bus Specification, revision

2.2 for 3.3-V operation

■

Hot-socket compliant

Built-in JTAG BST circuitry compliant with IEEE Std. 1149.1-1990

Table 1–1 lists the MAX V family features.

Table 1–1. MAX V Family Features

Feature

5M40Z

40

5M80Z

80

5M160Z

160

128

8,192

4

5M240Z

240

192

8,192

4

5M570Z

570

440

8,192

4

5M1270Z 5M2210Z

LEs

1,270

980

8,192

4

2,210

1,700

8,192

4

Typical Equivalent Macrocells

User Flash Memory Size (bits)

Global Clocks

32

64

8,192

4

8,192

4

Internal Oscillator

Maximum User I/O pins

t_PD1(ns) (1)

1

54

79

114

7.5

159

9.0

271

6.2

271

7.0

7.5

152

2.3

6.5

7.5

152

2.3

6.5

7.5

f_CNT(MHz) (2)

152

2.3

152

2.3

152

2.2

304

1.2

304

1.2

t

_SU(ns)

t_CO(ns)

6.5

6.7

4.6

Notes to Table 1–1:

(1) t_PD1represents a pin-to-pin delay for the worst case I/O placement with a full diagonal path across the device and combinational logic

implemented in a single LUT and LAB that is adjacent to the output pin.

(2) The maximum global clock frequency, f_CNT, is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay will run faster

than this number.

MAX V devices accept 1.8 V on their VCCINTpins. The 1.8-V V_CCINTexternal supply

powers the device core directly. MAX V devices operate internally at 1.8 V. The

supported MultiVolt I/O interface voltage levels (V_CCIO) are 1.2 V, 1.5 V, 1.8 V, 2.5 V,

and 3.3 V.

MAX V devices are available in two speed grades: –4 and –5, with –4 being the fastest.

For commercial applications, speed grades –C4 and –C5 are available. For industrial

and automotive applications, speed grade –I5 and –A5 are available, respectively.

These speed grades represent the overall relative performance, not any specific timing

parameter.

f For propagation delay timing numbers within each speed grade and density, refer to

the DC and Switching Characteristics for MAX V Devices chapter.

MAX V devices are available in space-saving FineLine BGA (FBGA), Micro FineLine

BGA (MBGA), plastic enhanced quad flat pack (EQFP), and thin quad flat pack

(TQFP) packages (refer to Table 1–2 and Table 1–3). MAX V devices support vertical

migration within the same package (for example, you can migrate between the

5M570Z, 5M1270Z, and 5M2210Z devices in the 256-pin FineLine BGA package).

Vertical migration means that you can migrate to devices whose dedicated pins and

JTAG pins are the same and power pins are subsets or supersets for a given package

across device densities. The largest density in any package has the highest number of

power pins; you must lay out for the largest planned density in a package to provide

MAX V Device Handbook

May 2011 Altera Corporation

Chapter 1: MAX V Device Family Overview

1–3

Integrated Software Platform

the necessary power pins for migration. For I/O pin migration across densities, cross

reference the available I/O pins using the device pin-outs for all planned densities of

a given package type to identify which I/O pins can be migrated. The Quartus^®II

software can automatically cross-reference and place all pins for you when given a

device migration list.

Table 1–2. MAX V Packages and User I/O Pins (Note 1)

64-Pin

MBGA

64-Pin

EQFP

68-Pin

MBGA

100-Pin

TQFP

100-Pin

MBGA

144-Pin

TQFP

256-Pin

FBGA

324-Pin

FBGA

Device

5M40Z

30

—

54

—

52

—

79

74

—

79

74

—

5M80Z

5M160Z

—

5M240Z

114

—

5M570Z

159

211

203

—

5M1270Z

5M2210Z

Note to Table 1–2:

271

(1) Device packages under the same arrow sign have vertical migration capability.

Table 1–3. MAX V Package Sizes

64-Pin

MBGA

64-Pin

EQFP

68-Pin

MBGA

100-Pin

TQFP

100-Pin

MBGA

144-Pin

TQFP

256-Pin

FBGA

324-Pin

FBGA

Package

Pitch (mm)

Area (mm²)

0.5

0.4

81

0.5

25

0.5

36

0.5

1

20.25

256

484

289

361

Length × width

(mm × mm)

4.5 × 4.5

9 × 9

5 × 5

16 × 16

6 × 6

22 × 22

17 × 17

19 × 19

Integrated Software Platform

The Quartus II software provides an integrated environment for HDL and schematic

design entry, compilation and logic synthesis, full simulation and advanced timing

analysis, and programming of MAX V devices.

f For more information about the Quartus II software features, refer to the Quartus II

Handbook.

You can debug your MAX V designs using In-System Sources and Probes Editor in

the Quartus II software. This feature allows you to easily control any internal signal

and provides you with a completely dynamic debugging environment.

f For more information about the In-System Sources and Probes Editor, refer to the

Design Debugging Using In-System Sources and Probes chapter of the Quartus II

Handbook.

Device Pin-Outs

f For more information, refer to the MAX V Device Pin-Out Files page.

May 2011 Altera Corporation

MAX V Device Handbook

1–4

Chapter 1: MAX V Device Family Overview

Ordering Information

Figure 1–1 shows the ordering codes for MAX V devices.

Figure 1–1. MAX V Device Packaging Ordering Information

5M

40Z

E

64

C

4

N

Family Signature

Optional Suffix

5M: MAX V

Indicates specific device

options or shipment method

N: Lead-free packaging

Device Type

Speed Grade

40Z: 40 Logic Elements

80Z: 80 Logic Elements

160Z: 160 Logic Elements

240Z: 240 Logic Elements

570Z: 570 Logic Elements

4 or 5, with 4 being the fastest

1270Z: 1,270 Logic Elements

2210Z: 2,210 Logic Elements

Operating Temperature

C: Commercial temperature (T_J= 0

°

C to 85

C to 100

A: Automotive temperature (T_J= -40

°

C)

I: Industrial temperature (T_J= -40

°

C to 125

°

C)

Package Type

Pin Count

Number of pins for a particular package

T: Thin quad flat pack (TQFP)

F: FineLine BGA (FBGA)

M: Micro FineLine BGA (MBGA)

E: Plastic Enhanced Quad Flat Pack (EQFP)

Document Revision History

Table 1–4 lists the revision history for this chapter.

Table 1–4. Document Revision History

Date

May 2011

Version

Changes

■ Updated Figure 1–1.

■ Updated Table 1–3.

1.2

January 2011

1.1

1.0

Updated “Feature Summary” section.

Initial release.

December 2010

MAX V Device Handbook

May 2011 Altera Corporation

2. MAX V Architecture

MV51002-1.0

This chapter describes the architecture of the MAX^®V device and contains the

following sections:

■

“Functional Description” on page 2–1

“Logic Array Blocks” on page 2–4

“Logic Elements” on page 2–8

“MultiTrack Interconnect” on page 2–14

“Global Signals” on page 2–19

“User Flash Memory Block” on page 2–21

“Internal Oscillator” on page 2–22

“Core Voltage” on page 2–25

“I/O Structure” on page 2–26

Functional Description

MAX V devices contain a two-dimensional row- and column-based architecture to

implement custom logic. Row and column interconnects provide signal interconnects

between the logic array blocks (LABs).

Each LAB in the logic array contains 10 logic elements (LEs). An LE is a small unit of

logic that provides efficient implementation of user logic functions. LABs are grouped

into rows and columns across the device. The MultiTrack interconnect provides fast

granular timing delays between LABs. The fast routing between LEs provides

minimum timing delay for added levels of logic versus globally routed interconnect

structures.

The I/O elements (IOEs) located after the LAB rows and columns around the

periphery of the MAX V device feeds the I/O pins. Each IOE contains a bidirectional

I/O buffer with several advanced features. I/O pins support Schmitt trigger inputs

and various single-ended standards, such as 33-MHz, 32-bit PCI™, and LVTTL.

MAX V devices provide a global clock network. The global clock network consists of

four global clock lines that drive throughout the entire device, providing clocks for all

resources within the device. You can also use the global clock lines for control signals

such as clear, preset, or output enable.

and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at

www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but

reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any

information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device

specifications before relying on any published information and before placing orders for products or services.

MAX V Device Handbook

December 2010

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2–2

Chapter 2: MAX V Architecture

Functional Description

Figure 2–1 shows a functional block diagram of the MAX V device.

Figure 2–1. Device Block Diagram

IOE

Logic

Element

Logic

Element

Logic

Element

IOE

Logic

Element

Logic

Element

Logic

Element

Logic Array

BLock (LAB)

MultiTrack

Interconnect

Logic

Element

Logic

Element

Logic

Element

IOE

Logic

Element

Logic

Element

Logic

Element

IOE

MultiTrack

Interconnect

Each MAX V device contains a flash memory block within its floorplan. This block is

located on the left side of the 5M40Z, 5M80Z, 5M160Z, and 5M240Z devices. On the

5M240Z (T144 package), 5M570Z, 5M1270Z, and 5M2210Z devices, the flash memory

block is located on the bottom-left area of the device. The majority of this flash

memory storage is partitioned as the dedicated configuration flash memory (CFM)

block. The CFM block provides the non-volatile storage for all of the SRAM

configuration information. The CFM automatically downloads and configures the

logic and I/O at power-up, providing instant-on operation.

f For more information about configuration upon power-up, refer to the Hot Socketing

and Power-On Reset for MAX V Devices chapter.

A portion of the flash memory within the MAX V device is partitioned into a small

block for user data. This user flash memory (UFM) block provides 8,192 bits of

general-purpose user storage. The UFM provides programmable port connections to

the logic array for reading and writing. There are three LAB rows adjacent to this

block, with column numbers varying by device.

MAX V Device Handbook

December 2010 Altera Corporation

Chapter 2: MAX V Architecture

2–3

Functional Description

Table 2–1 lists the number of LAB rows and columns in each device, as well as the

number of LAB rows and columns adjacent to the flash memory area. The long LAB

rows are full LAB rows that extend from one side of row I/O blocks to the other. The

short LAB rows are adjacent to the UFM block; their length is shown as width in LAB

columns.

Table 2–1. Device Resources for MAX V Devices

LAB Rows

Device

5M40Z

UFM Blocks

LAB Columns

Total LABs

Long LAB Rows

Short LAB Rows (Width) (1)

1

6

4

—

24

5M80Z

5M160Z

6

4

—

24

5M240Z (2)

5M240Z (3)

5M570Z

6

4

—

24

12

16

20

4

3 (3)

3 (5)

3 (7)

57

4

57

5M1270Z (4)

5M1270Z (5)

5M2210Z

7

127

221

10

Notes to Table 2–1:

(1) The width is the number of LAB columns in length.

(2) Not applicable to T144 package of the 5M240Z device.

(3) Only applicable to T144 package of the 5M240Z device.

(4) Not applicable to F324 package of the 5M1270Z device.

(5) Only applicable to F324 package of the 5M1270Z device.

December 2010 Altera Corporation

MAX V Device Handbook

2–4

Chapter 2: MAX V Architecture

Logic Array Blocks

Figure 2–2 shows a floorplan of a MAX V device.

Figure 2–2. Device Floorplan for MAX V Devices (Note 1)

I/O Blocks

Logic Array

Blocks

Logic Array

Blocks

2 GCLK

Inputs

2 GCLK

Inputs

I/O Blocks

UFM Block

CFM Block

Note to Figure 2–2:

(1) The device shown is a 5M570Z device. 5M1270Z and 5M2210Z devices have a similar floorplan with more LABs. For 5M40Z, 5M80Z, 5M160Z,

and 5M240Z devices, the CFM and UFM blocks are located on the left side of the device.

Logic Array Blocks

Each LAB consists of 10 LEs, LE carry chains, LAB control signals, a local interconnect,

a look-up table (LUT) chain, and register chain connection lines. There are 26 possible

unique inputs into an LAB, with an additional 10 local feedback input lines fed by LE

outputs in the same LAB. The local interconnect transfers signals between LEs in the

same LAB. LUT chain connections transfer the LUT output from one LE to the

MAX V Device Handbook

December 2010 Altera Corporation

Chapter 2: MAX V Architecture

2–5

Logic Array Blocks

adjacent LE for fast sequential LUT connections within the same LAB. Register chain

connections transfer the output of one LE’s register to the adjacent LE’s register

within an LAB. The Quartus^®II software places associated logic within an LAB or

adjacent LABs, allowing the use of local, LUT chain, and register chain connections

for performance and area efficiency. Figure 2–3 shows the MAX V LAB.

Figure 2–3. LAB Structure for MAX V Devices

Row Interconnect

Column Interconnect

LE0

LE1

LE2

LE3

Fast I/O connection

to IOE (1)

Fast I/O connection

to IOE (1)

DirectLink

interconnect from

adjacent LAB

or IOE

interconnect from

adjacent LAB

or IOE

LE4

LE5

LE6

LE7

DirectLink

interconnect to

adjacent LAB

or IOE

interconnect to

adjacent LAB

or IOE

LE8

LE9

Logic Element

LAB

Local Interconnect

Note to Figure 2–3:

(1) Only from LABs adjacent to IOEs.

December 2010 Altera Corporation

MAX V Device Handbook

2–6

Chapter 2: MAX V Architecture

Logic Array Blocks

LAB Interconnects

Column and row interconnects and LE outputs within the same LAB drive the LAB

local interconnect. Adjacent LABs, from the left and right, can also drive an LAB’s

local interconnect through the DirectLink connection. The DirectLink connection

feature minimizes the use of row and column interconnects, providing higher

performance and flexibility. Each LE can drive 30 other LEs through fast local and

DirectLink interconnects. Figure 2–4 shows the DirectLink connection.

Figure 2–4. DirectLink Connection

DirectLink interconnect from

right LAB or IOE output

DirectLink interconnect from

left LAB or IOE output

LE0

LE1

LE2

LE3

LE4

LE5

LE6

LE7

LE8

LE9

DirectLink

interconnect

to left

DirectLink

interconnect

to right

Local

Interconnect

Logic Element

LAB

LAB Control Signals

Each LAB contains dedicated logic for driving control signals to its LEs. The control

signals include two clocks, two clock enables, two asynchronous clears, a

synchronous clear, an asynchronous preset/load, a synchronous load, and

add/subtract control signals, providing a maximum of 10 control signals at a time.

Synchronous load and clear signals are generally used when implementing counters

but they can also be used with other functions.

Each LAB can use two clocks and two clock enable signals. Each LAB’s clock and

clock enable signals are linked. For example, any LE in a particular LAB using the

labclk1signal also uses labclkena1. If the LAB uses both the rising and falling edges

of a clock, it also uses both LAB-wide clock signals. Deasserting the clock enable

signal turns off the LAB-wide clock.

Each LAB can use two asynchronous clear signals and an asynchronous load/preset

signal. By default, the Quartus II software uses a NOTgate push-back technique to

achieve preset. If you disable the NOTgate push-back option or assign a given register

to power-up high using the Quartus II software, the preset is then achieved using the

asynchronous load signal with asynchronous load data input tied high.

MAX V Device Handbook

December 2010 Altera Corporation

Chapter 2: MAX V Architecture

2–7

Logic Array Blocks

With the LAB-wide addnsubcontrol signal, a single LE can implement a one-bit adder

and subtractor. This signal saves LE resources and improves performance for logic

functions such as correlators and signed multipliers that alternate between addition

and subtraction depending on data.

The LAB column clocks [3..0], driven by the global clock network, and LAB local

interconnect generate the LAB-wide control signals. The MultiTrack interconnect

structure drives the LAB local interconnect for non-global control signal generation.

The MultiTrack interconnect’s inherent low skew allows clock and control signal

distribution in addition to data signals. Figure 2–5 shows the LAB control signal

generation circuit.

Figure 2–5. LAB-Wide Control Signals

Dedicated

LAB Column

Clocks

4

Local

Interconnect

Local

Interconnect

Local

Interconnect

Local

Interconnect

Local

Interconnect

labclkena2

labclkena1

syncload

labclr2

addnsub

Local

Interconnect

labclk1

labclk2

asyncload

or labpre

labclr1

synclr

December 2010 Altera Corporation

MAX V Device Handbook

2–8

Chapter 2: MAX V Architecture

Logic Elements

The smallest unit of logic in the MAX V architecture, the LE, is compact and provides

advanced features with efficient logic utilization. Each LE contains a four-input LUT,

which is a function generator that can implement any function of four variables. In

addition, each LE contains a programmable register and carry chain with carry-select

capability. A single LE also supports dynamic single-bit addition or subtraction mode

that is selected by an LAB-wide control signal. Each LE drives all types of

interconnects: local, row, column, LUT chain, register chain, and DirectLink

interconnects as shown in Figure 2–6.

Figure 2–6. LE for MAX V Devices

Register chain

routing from

previous LE

LAB-wide

Synchronous

Register Bypass

LAB Carry-In

Carry-In1

Load

Programmable

Register

LAB-wide

Synchronous

Packed

Register Select

addnsub

Carry-In0

Clear

LUT chain

routing to next LE

data1

Row, column,

and DirectLink

routing

PRN/ALD

data2

data3

Synchronous

Load and

Clear Logic

Look-Up

Table

(LUT)

Carry

Chain

D

Q

ADATA

data4

ENA

CLRN

Row, column,

and DirectLink

routing

labclr1

labclr2

Asynchronous

Clear/Preset/

Load Logic

Local routing

labpre/aload

Chip-Wide

Reset (DEV_CLRn)

Register chain

output

Register

Feedback

Clock and

Clock Enable

Select

labclk1

labclk2

labclkena1

labclkena2

Carry-Out0

Carry-Out1

LAB Carry-Out

You can configure each LE’s programmable register for D, T, JK, or SR operation. Each

register has data, true asynchronous load data, clock, clock enable, clear, and

asynchronous load/preset inputs. Global signals, general purpose I/O (GPIO) pins,

or any LE can drive the register’s clock and clear control signals. Either GPIO pins or

LEs can drive the clock enable, preset, asynchronous load, and asynchronous data.

The asynchronous load data input comes from the data3input of the LE. For

combinational functions, the LUT output bypasses the register and drives directly to

the LE outputs.

Each LE has three outputs that drive the local, row, and column routing resources. The

LUT or register output can drive these three outputs independently. Two LE outputs

drive either a column or row and DirectLink routing connections while one output

drives the local interconnect resources. This configuration allows the LUT to drive one

output while the register drives another output. This register packing feature

MAX V Device Handbook

December 2010 Altera Corporation

Chapter 2: MAX V Architecture

2–9

Logic Elements

improves device utilization because the device can use the register and the LUT for

unrelated functions. Another special packing mode allows the register output to feed

back into the LUT of the same LE so that the register is packed with its own fan-out

LUT. This mode provides another mechanism for improved fitting. The LE can also

drive out registered and unregistered versions of the LUT output.

LUT Chain and Register Chain

In addition to the three general routing outputs, the LEs within a LAB have LUT chain

and register chain outputs. LUT chain connections allow LUTs within the same LAB

to cascade together for wide input functions. Register chain outputs allow registers

within the same LAB to cascade together. The register chain output allows a LAB to

use LUTs for a single combinational function and the registers for an unrelated shift

register implementation. These resources speed up connections between LABs while

saving local interconnect resources. For more information about LUT chain and

register chain connections, refer to “MultiTrack Interconnect” on page 2–14.

addnsub Signal

The LE’s dynamic adder/subtractor feature saves logic resources by using one set of

LEs to implement both an adder and a subtractor. This feature is controlled by the

LAB-wide control signal addnsub. The addnsubsignal sets the LAB to perform either

A + B or A – B. The LUT computes addition; subtraction is computed by adding the

two’s complement of the intended subtractor. The LAB-wide signal converts to two’s

complement by inverting the B bits within the LAB and setting carry-in to 1, which

adds one to the LSB. The LSB of an adder/subtractor must be placed in the first LE of

the LAB, where the LAB-wide addnsubsignal automatically sets the carry-in to 1. The

Quartus II Compiler automatically places and uses the adder/subtractor feature

when using adder/subtractor parameterized functions.

LE Operating Modes

The MAX V LE can operate in one of the following modes:

■

“Normal Mode”

■

“Dynamic Arithmetic Mode”

Each mode uses LE resources differently. In each mode, eight available inputs to the

LE, the four data inputs from the LAB local interconnect, carry-in0 and carry-in1

from the previous LE, the LAB carry-in from the previous carry-chain LAB, and the

register chain connection are directed to different destinations to implement the

desired logic function. LAB-wide signals provide clock, asynchronous clear,

asynchronous preset/load, synchronous clear, synchronous load, and clock enable

control for the register. These LAB-wide signals are available in all LE modes. The

addnsubcontrol signal is allowed in arithmetic mode.

The Quartus II software, along with parameterized functions such as the library of

parameterized modules (LPM) functions, automatically chooses the appropriate

mode for common functions such as counters, adders, subtractors, and arithmetic

functions.

December 2010 Altera Corporation

MAX V Device Handbook

2–10

Chapter 2: MAX V Architecture

Logic Elements

Normal Mode

The normal mode is suitable for general logic applications and combinational

functions. In normal mode, four data inputs from the LAB local interconnect are

inputs to a four-input LUT as shown in Figure 2–7. The Quartus II Compiler

automatically selects the carry-in or the data3signal as one of the inputs to the LUT.

Each LE can use LUT chain connections to drive its combinational output directly to

the next LE in the LAB. Asynchronous load data for the register comes from the data3

input of the LE. LEs in normal mode support packed registers.

Figure 2–7. LE in Normal Mode

sload

sclear

aload

(LAB Wide) (LAB Wide)

(LAB Wide)

Register chain

connection

addnsub (LAB Wide)

ALD/PRE

(1)

Row, column, and

ADATA

D

Q

DirectLink routing

data1

data2

Row, column, and

DirectLink routing

ENA

CLRN

data3

cin (from cout

of previous LE)

4-Input

LUT

clock (LAB Wide)

Local routing

data4

ena (LAB Wide)

aclr (LAB Wide)

LUT chain

connection

Register

chain output

Register Feedback

Note to Figure 2–7:

(1) This signal is only allowed in normal mode if the LE is after an adder/subtractor chain.

Dynamic Arithmetic Mode

The dynamic arithmetic mode is ideal for implementing adders, counters,

accumulators, wide parity functions, and comparators. A LE in dynamic arithmetic

mode uses four 2-input LUTs configurable as a dynamic adder/subtractor. The first

two 2-input LUTs compute two summations based on a possible carry-in of 1 or 0; the

other two LUTs generate carry outputs for the two chains of the carry-select circuitry.

As shown in Figure 2–8, the LAB carry-in signal selects either the carry-in0or

carry-in1chain. The selected chain’s logic level in turn determines which parallel

sum is generated as a combinational or registered output. For example, when

implementing an adder, the sum output is the selection of two possible calculated

sums:

data1 + data2 + carry-in0

or

data1 + data2 + carry-in1

MAX V Device Handbook

December 2010 Altera Corporation

Chapter 2: MAX V Architecture

2–11

Logic Elements

The other two LUTs use the data1and data2signals to generate two possible

carry-out signals: one for a carry of 1 and the other for a carry of 0. The carry-in0

signal acts as the carry-select for the carry-out0output and carry-in1acts as the

carry-select for the carry-out1output. LEs in arithmetic mode can drive out

registered and unregistered versions of the LUT output.

The dynamic arithmetic mode also offers clock enable, counter enable, synchronous

up/down control, synchronous clear, synchronous load, and dynamic

adder/subtractor options. The LAB local interconnect data inputs generate the

counter enable and synchronous up/down control signals. The synchronous clear

and synchronous load options are LAB-wide signals that affect all registers in the

LAB. The Quartus II software automatically places any registers that are not used by

the counter into other LABs. The addnsubLAB-wide signal controls whether the LE

acts as an adder or subtractor.

Figure 2–8. LE in Dynamic Arithmetic Mode

LAB Carry-In

Carry-In0

sload

(LAB Wide) (LAB Wide)

Register chain

connection

sclear

aload

(LAB Wide)

Carry-In1

addnsub

(LAB Wide)

(1)

ALD/PRE

data1

data2

data3

LUT

ADATA

D

Row, column, and

direct link routing

Q

LUT

Row, column, and

direct link routing

ENA

CLRN

clock (LAB Wide)

ena (LAB Wide)

aclr (LAB Wide)

Local routing

LUT chain

connection

Register

chain output

Register Feedback

Carry-Out0 Carry-Out1

Note to Figure 2–8:

(1) The addnsubsignal is tied to the carry input for the first LE of a carry chain only.

Carry-Select Chain

The carry-select chain provides a very fast carry-select function between LEs in

dynamic arithmetic mode. The carry-select chain uses the redundant carry calculation

to increase the speed of carry functions. The LE is configured to calculate outputs for a

possible carry-in of 0 and carry-in of 1 in parallel. The carry-in0and carry-in1

signals from a lower-order bit feed forward into the higher-order bit via the parallel

carry chain and feed into both the LUT and the next portion of the carry chain.

Carry-select chains can begin in any LE within an LAB.

December 2010 Altera Corporation

MAX V Device Handbook

2–12

Chapter 2: MAX V Architecture

Logic Elements

The speed advantage of the carry-select chain is in the parallel pre-computation of

carry chains. Because the LAB carry-in selects the precomputed carry chain, not every

LE is in the critical path. Only the propagation delays between LAB carry-in

generation (LE5and LE10) are now part of the critical path. This feature allows the

MAX V architecture to implement high-speed counters, adders, multipliers, parity

functions, and comparators of arbitrary width.

Figure 2–9 shows the carry-select circuitry in an LAB for a 10-bit full adder. One

portion of the LUT generates the sum of two bits using the input signals and the

appropriate carry-in bit; the sum is routed to the output of the LE. The register can be

bypassed for simple adders or used for accumulator functions. Another portion of the

LUT generates carry-out bits. An LAB-wide carry-in bit selects which chain is used for

the addition of given inputs. The carry-in signal for each chain, carry-in0or

carry-in1, selects the carry-out to carry forward to the carry-in signal of the

next-higher-order bit. The final carry-out signal is routed to an LE, where it is fed to

local, row, or column interconnects.

Figure 2–9. Carry-Select Chain

LAB Carry-In

0

1

LAB Carry-In

Carry-In0

Sum1

Sum2

Sum3

Sum4

Sum5

A1

B1

LE0

LE1

LE2

LE3

LE4

Carry-In1

A2

B2

LUT

data1

data2

Sum

A3

B3

A4

B4

LUT

A5

B5

0

1

Carry-Out0

Carry-Out1

Sum6

Sum7

Sum8

Sum9

Sum10

A6

B6

LE5

LE6

LE7

LE8

LE9

A7

B7

A8

B8

A9

B9

A10

B10

To top of adjacent LAB

LAB Carry-Out

MAX V Device Handbook

December 2010 Altera Corporation

Chapter 2: MAX V Architecture

2–13

Logic Elements

The Quartus II software automatically creates carry chain logic during design

processing, or you can create it manually during design entry. Parameterized

functions such as LPM functions automatically take advantage of carry chains for the

appropriate functions. The Quartus II software creates carry chains longer than 10 LEs

by linking adjacent LABs within the same row together automatically. A carry chain

can extend horizontally up to one full LAB row, but does not extend between LAB

rows.

Clear and Preset Logic Control

LAB-wide signals control the logic for the register’s clear and preset signals. The LE

directly supports an asynchronous clear and preset function. The register preset is

achieved through the asynchronous load of a logic high. MAX V devices support

simultaneous preset/asynchronous load and clear signals. An asynchronous clear

signal takes precedence if both signals are asserted simultaneously. Each LAB

supports up to two clears and one preset signal.

In addition to the clear and preset ports, MAX V devices provide a chip-wide reset pin

(

DEV_CLRn) that resets all registers in the device. An option set before compilation in

the Quartus II software controls this pin. This chip-wide reset overrides all other

control signals and uses its own dedicated routing resources without using any of the

four global resources. Driving this signal low before or during power-up prevents

user mode from releasing clears within the design. This allows you to control when

clear is released on a device that has just been powered-up. If not set for its chip-wide

reset function, the DEV_CLRnpin is a regular I/O pin.

By default, all registers in MAX V devices are set to power-up low. However, this

power-up state can be set to high on individual registers during design entry using

the Quartus II software.

LE RAM

The Quartus II memory compiler can configure the unused LEs as LE RAM.

MAX V devices support the following memory types:

■

FIFO synchronous R/W

FIFO asynchronous R/W

1 port SRAM

2 port SRAM

3 port SRAM

shift registers

f For more information about memory, refer to the Internal Memory (RAM and ROM)

User Guide.

December 2010 Altera Corporation

MAX V Device Handbook

2–14

Chapter 2: MAX V Architecture

MultiTrack Interconnect

In the MAX V architecture, connections between LEs, the UFM, and device I/O pins

are provided by the MultiTrack interconnect structure. The MultiTrack interconnect

consists of continuous, performance-optimized routing lines used for inter- and

intra-design block connectivity. The Quartus II Compiler automatically places critical

design paths on faster interconnects to improve design performance.

The MultiTrack interconnect consists of row and column interconnects that span fixed

distances. A routing structure with fixed length resources for all devices allows

predictable and short delays between logic levels instead of large delays associated

with global or long routing lines. Dedicated row interconnects route signals to and

from LABs within the same row. These row resources include:

■

DirectLink interconnects between LABs

■

R4 interconnects traversing four LABs to the right or left

The DirectLink interconnect allows an LAB to drive into the local interconnect of its

left and right neighbors. The DirectLink interconnect provides fast communication

between adjacent LABs and blocks without using row interconnect resources.

The R4 interconnects span four LABs and are used for fast row connections in a

four-LAB region. Every LAB has its own set of R4 interconnects to drive either left or

right. Figure 2–10 shows R4 interconnect connections from an LAB. R4 interconnects

can drive and be driven by row IOEs. For LAB interfacing, a primary LAB or

horizontal LAB neighbor can drive a given R4 interconnect. For R4 interconnects that

drive to the right, the primary LAB and right neighbor can drive on to the

interconnect. For R4 interconnects that drive to the left, the primary LAB and its left

neighbor can drive on to the interconnect. R4 interconnects can drive other R4

interconnects to extend the range of LABs they can drive. R4 interconnects can also

drive C4 interconnects for connections from one row to another.

MAX V Device Handbook

December 2010 Altera Corporation

Chapter 2: MAX V Architecture

2–15

MultiTrack Interconnect

Figure 2–10. R4 Interconnect Connections

Adjacent LAB can

drive onto another

LAB’s R4 Interconnect

R4 Interconnect

Driving Right

C4 Column Interconnects (1)

R4 Interconnect

Driving Left

LAB

Neighbor

Primary

LAB (2)

LAB

Neighbor

Notes to Figure 2–10:

(1) C4 interconnects can drive R4 interconnects.

(2) This pattern is repeated for every LAB in the LAB row.

The column interconnect operates similarly to the row interconnect. Each column of

LABs is served by a dedicated column interconnect, which vertically routes signals to

and from LABs and row and column IOEs. These column resources include:

■

LUT chain interconnects within an LAB

Register chain interconnects within an LAB

C4 interconnects traversing a distance of four LABs in an up and down direction

MAX V devices include an enhanced interconnect structure within LABs for routing

LE output to LE input connections faster using LUT chain connections and register

chain connections. The LUT chain connection allows the combinational output of an

LE to directly drive the fast input of the LE right below it, bypassing the local

interconnect. These resources can be used as a high-speed connection for wide fan-in

functions from LE 1to LE 10in the same LAB. The register chain connection allows

the register output of one LE to connect directly to the register input of the next LE in

the LAB for fast shift registers. The Quartus II Compiler automatically takes

advantage of these resources to improve utilization and performance. Figure 2–11

shows the LUT chain and register chain interconnects.

December 2010 Altera Corporation

MAX V Device Handbook

2–16

Chapter 2: MAX V Architecture

MultiTrack Interconnect

Figure 2–11. LUT Chain and Register Chain Interconnects

Local Interconnect

Routing Among LEs

in the LAB

LE0

LUT Chain

Routing to

Adjacent LE

Register Chain

Routing to Adjacent

LE's Register Input

LE1

LE2

LE3

LE4

LE5

LE6

LE7

LE8

Local

Interconnect

LE9

The C4 interconnects span four LABs up or down from a source LAB. Every LAB has

its own set of C4 interconnects to drive either up or down. Figure 2–12 shows the C4

interconnect connections from an LAB in a column. The C4 interconnects can drive

and be driven by column and row IOEs. For LAB interconnection, a primary LAB or

its vertical LAB neighbor can drive a given C4 interconnect. C4 interconnects can

drive each other to extend their range as well as drive row interconnects for

column-to-column connections.

MAX V Device Handbook

December 2010 Altera Corporation

Chapter 2: MAX V Architecture

2–17

MultiTrack Interconnect

Figure 2–12. C4 Interconnect Connections (Note 1)

C4 Interconnect

Drives Local and R4

Interconnects

Up to Four Rows

C4 Interconnect

Driving Up

LAB

Row

Interconnect

Adjacent LAB can

drive onto neighboring

LAB's C4 interconnect

Local

Interconnect

C4 Interconnect

Driving Down

Note to Figure 2–12:

(1) Each C4 interconnect can drive either up or down four rows.

December 2010 Altera Corporation

MAX V Device Handbook

2–18

Chapter 2: MAX V Architecture

MultiTrack Interconnect

The UFM block communicates with the logic array similar to LAB-to-LAB interfaces.

The UFM block connects to row and column interconnects and has local interconnect

regions driven by row and column interconnects. This block also has DirectLink

interconnects for fast connections to and from a neighboring LAB. For more

information about the UFM interface to the logic array, refer too “User Flash Memory

Block” on page 2–21.

Table 2–2 lists the MAX V device routing scheme.

Table 2–2. Routing Scheme for MAX V Devices

Destination

Source

LUT

Register Local DirectLink

UFM

Column Row Fast I/O

R4 (1) C4 (1)

LE

Chain

(1)

—

(1)

—

Block

IOE

(1)

—

LUT Chain

—

v

—

Register Chain

—

Local

Interconnect

—

v

—

DirectLink

Interconnect

v

—

R4 Interconnect

C4 Interconnect

LE

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

UFM Block

Column IOE

Row IOE

Note to Table 2–2:

(1) These categories are interconnects.

MAX V Device Handbook

December 2010 Altera Corporation

Chapter 2: MAX V Architecture

2–19

Global Signals

Each MAX V device has four dual-purpose dedicated clock pins (GCLK[3..0], two

pins on the left side and two pins on the right side) that drive the global clock network

for clocking, as shown in Figure 2–13. These four pins can also be used as GPIOs if

they are not used to drive the global clock network.

The four global clock lines in the global clock network drive throughout the entire

device. The global clock network can provide clocks for all resources within the

device including LEs, LAB local interconnect, IOEs, and the UFM block. The global

clock lines can also be used for global control signals, such as clock enables,

synchronous or asynchronous clears, presets, output enables, or protocol control

signals such as TRDYand IRDYfor the PCI I/O standard. Internal logic can drive the

global clock network for internally-generated global clocks and control signals.

Figure 2–13 shows the various sources that drive the global clock network.

Figure 2–13. Global Clock Generation

GCLK0

GCLK1

GCLK2

4

Global Clock

Network

GCLK3

4

Logic Array(1)

Note to Figure 2–13:

(1) Any I/O pin can use a MultiTrack interconnect to route as a logic array-generated global clock signal.

The global clock network drives to individual LAB column signals, LAB column

clocks [3..0], that span an entire LAB column from the top to the bottom of the

device. Unused global clocks or control signals in an LAB column are turned off at the

LAB column clock buffers shown in Figure 2–14. The LAB column clocks [3..0]are

multiplexed down to two LAB clock signals and one LAB clear signal. Other control

signal types route from the global clock network into the LAB local interconnect. For

more information, refer to “LAB Control Signals” on page 2–6.

December 2010 Altera Corporation

MAX V Device Handbook

2–20

Chapter 2: MAX V Architecture

Global Signals

Figure 2–14. Global Clock Network (Note 1)

LAB Column

clock[3..0]

I/O Block Region

4

LAB Column

clock[3..0]

I/O Block Region

UFM Block (2)

CFM Block

Notes to Figure 2–14:

(1) LAB column clocks in I/O block regions provide high fan-out output enable signals.

(2) LAB column clocks drive to the UFM block.

MAX V Device Handbook

December 2010 Altera Corporation

Chapter 2: MAX V Architecture

2–21

User Flash Memory Block

MAX V devices feature a single UFM block, which can be used like a serial EEPROM

for storing non-volatile information up to 8,192 bits. The UFM block connects to the

logic array through the MultiTrack interconnect, allowing any LE to interface to the

UFM block. Figure 2–15 shows the UFM block and interface signals. The logic array is

used to create customer interface or protocol logic to interface the UFM block data

outside of the device. The UFM block offers the following features:

■

Non-volatile storage up to 16-bit wide and 8,192 total bits

Two sectors for partitioned sector erase

Built-in internal oscillator that optionally drives logic array

Program, erase, and busy signals

Auto-increment addressing

Serial interface to logic array with programmable interface

Figure 2–15. UFM Block and Interface Signals

UFM Block

PROGRAM

ERASE

RTP_BUSY

BUSY

Program

Erase

Control

_

:

OSC

4

OSC_ENA

OSC

UFM Sector 1

UFM Sector 0

9

ARCLK

Address

Register

16

ARSHFT

ARDin

DRDin

Data Register

DRDout

DRCLK

DRSHFT

December 2010 Altera Corporation

MAX V Device Handbook

2–22

Chapter 2: MAX V Architecture

User Flash Memory Block

UFM Storage

Each device stores up to 8,192 bits of data in the UFM block. Table 2–3 lists the data

size, sector, and address sizes for the UFM block.

Table 2–3. UFM Array Size

Device

5M40Z

Total Bits

8,192

Sectors

Address Bits

Data Width

2 (4,096 bits per sector)

9

16

5M80Z

5M160Z

5M240Z

5M570Z

5M1270Z

5M2210Z

There are 512 locations with 9-bit addressing ranging from 000hto 1FFh. The sector 0

address space is 000hto 0FFhand the sector 1 address space is from 100hto 1FFh. The

data width is up to 16 bits of data. The Quartus II software automatically creates logic

to accommodate smaller read or program data widths. Erasure of the UFM involves

individual sector erasing (that is, one erase of sector 0 and one erase of sector 1 is

required to erase the entire UFM block). Because sector erase is required before a

program or write operation, having two sectors enables a sector size of data to be left

untouched while the other sector is erased and programmed with new data.

Internal Oscillator

As shown in Figure 2–15, the dedicated circuitry within the UFM block contains an

oscillator. The dedicated circuitry uses this oscillator internally for its read and

program operations. This oscillator's divide by 4 output can drive out of the UFM

block as a logic interface clock source or for general-purpose logic clocking. The

typical OSC output signal frequency ranges from 3.9 to 5.3 MHz, and its exact

frequency of operation is not programmable.

The UFM internal oscillator can be instantiated using the MegaWizard^™Plug-In

Manager. You can also use the MAX II/MAX V Oscillator megafunction to instantiate

the UFM oscillator without using the UFM memory block.

MAX V Device Handbook

December 2010 Altera Corporation

Chapter 2: MAX V Architecture

2–23

User Flash Memory Block

Program, Erase, and Busy Signals

The UFM block’s dedicated circuitry automatically generates the necessary internal

program and erase algorithm after the PROGRAMor ERASEinput signals have been

asserted. The PROGRAMor ERASEsignal must be asserted until the busy signal deasserts,

indicating the UFM internal program or erase operation has completed. The UFM

block also supports JTAG as the interface for programming and reading.

f For more information about programming and erasing the UFM block, refer to the

User Flash Memory in MAX V Devices chapter.

Auto-Increment Addressing

The UFM block supports standard read or stream read operations. The stream read is

supported with an auto-increment address feature. Deasserting the ARSHIFTsignal

while clocking the ARCLKsignal increments the address register value to read

consecutive locations from the UFM array.

Serial Interface

The UFM block supports a serial interface with serial address and data signals. The

internal shift registers within the UFM block for address and data are 9 bits and 16 bits

wide, respectively. The Quartus II software automatically generates interface logic in

LEs for a parallel address and data interface to the UFM block. Other standard

protocol interfaces such as SPI are also automatically generated in LE logic by the

Quartus II software.

f For more information about the UFM interface signals and the Quartus II LE-based

alternate interfaces, refer to the User Flash Memory in MAX V Devices chapter.

December 2010 Altera Corporation

MAX V Device Handbook

2–24

Chapter 2: MAX V Architecture

User Flash Memory Block

UFM Block to Logic Array Interface

The UFM block is a small partition of the flash memory that contains the CFM block,

as shown in Figure 2–1 and Figure 2–2. The UFM block for the 5M40Z, 5M80Z,

5M160Z, and 5M240Z devices is located on the left side of the device adjacent to the

left most LAB column. The UFM blocks for the 5M570Z, 5M1270Z, and 5M2210Z

devices are located at the bottom left of the device. The UFM input and output signals

interface to all types of interconnects (R4 interconnect, C4 interconnect, and

DirectLink interconnect to/from adjacent LAB rows). The UFM signals can also be

driven from global clocks, GCLK[3..0]. The interface regions for the 5M40Z, 5M80Z,

5M160Z, and 5M240Z devices are shown in Figure 2–16. The interface regions for

5M570Z, 5M1270Z, and 5M2210Z devices are shown in Figure 2–17.

Figure 2–16. 5M40Z, 5M80Z, 5M160Z, and 5M240Z UFM Block LAB Row Interface (Note 1), (2)

CFM Block

UFM Block

LAB

PROGRAM

ERASE

OSC_ENA

LAB

RTP_BUSY

DRDin

DRCLK

DRSHFT

ARin

ARCLK

ARSHFT

DRDout

OSC

LAB

BUSY

Notes to Figure 2–16:

(1) The UFM block inputs and outputs can drive to and from all types of interconnects, not only DirectLink interconnects

from adjacent row LABs.

(2) Not applicable to the T144 package of the 5M240Z device.

MAX V Device Handbook

December 2010 Altera Corporation

Chapter 2: MAX V Architecture

2–25

Core Voltage

Figure 2–17. 5M240Z, 5M570Z, 5M1270Z, and 5M2210Z UFM Block LAB Row Interface (Note 1)

CFM Block

RTP_BUSY

BUSY

OSC

DRDout

DRDin

LAB

DRDCLK

DRDSHFT

ARDin

PROGRAM

ERASE

OSC_ENA

ARCLK

ARSHFT

LAB

UFM Block

LAB

Note to Figure 2–17:

(1) Only applicable to the T144 package of the 5M240Z device.

Core Voltage

The MAX V architecture supports a 1.8-V core voltage on the V_CCINTsupply. You must

use a 1.8-V V_CCexternal supply to power the VCCINTpins.

Figure 2–18. Core Voltage Feature in MAX V Devices

1.8-V Core

1.8-V on

Voltage

VCCINT Pins

MAX V Device

December 2010 Altera Corporation

MAX V Device Handbook

2–26

Chapter 2: MAX V Architecture

I/O Structure

IOEs support many features, including:

■

LVTTL, LVCMOS, LVDS, and RSDS I/O standards

3.3-V, 32-bit, 33-MHz PCI compliance

JTAG boundary-scan test (BST) support

Programmable drive strength control

Weak pull-up resistors during power-up and in system programming

Slew-rate control

Tri-state buffers with individual output enable control

Bus-hold circuitry

Programmable pull-up resistors in user mode

Unique output enable per pin

Open-drain outputs

Schmitt trigger inputs

Fast I/O connection

Programmable input delay

MAX V device IOEs contain a bidirectional I/O buffer. Figure 2–19 shows the MAX V

IOE structure. Registers from adjacent LABs can drive to or be driven from the IOE’s

bidirectional I/O buffers. The Quartus II software automatically attempts to place

registers in the adjacent LAB with fast I/O connection to achieve the fastest possible

clock-to-output and registered output enable timing. When the fast input registers

option is enabled, the Quartus II software automatically routes the register to

guarantee zero hold time. You can set timing assignments in the Quartus II software

to achieve desired I/O timing.

MAX V Device Handbook

December 2010 Altera Corporation

Chapter 2: MAX V Architecture

2–27

I/O Structure

Fast I/O Connection

A dedicated fast I/O connection from the adjacent LAB to the IOEs within an I/O

block provides faster output delays for clock-to-output and t_PDpropagation delays.

This connection exists for data output signals, not output enable signals or input

signals. Figure 2–20, Figure 2–21, and Figure 2–22 illustrate the fast I/O connection.

Figure 2–19. IOE Structure for MAX V Devices

Data_in Fast_out

Data_out OE

DEV_OE

Optional

PCI Clamp (1)

Programmable

Pull-Up (2)

V

CCIO

I/O Pin

Optional Bus-Hold

Circuit

Drive Strength Control

Open-Drain Output

Slew Control

Optional Schmitt

Trigger Input

Programmable

Input Delay

Notes to Figure 2–19:

(1) Available only in I/O bank 3 of 5M1270Z and 5M2210Z devices.

(2) The programmable pull-up resistor is active during power-up, in-system programming (ISP), and if the device is unprogrammed.

December 2010 Altera Corporation

MAX V Device Handbook

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Chapter 2: MAX V Architecture

I/O Structure

I/O Blocks

The IOEs are located in I/O blocks around the periphery of the MAX V device. There

are up to seven IOEs per row I/O block and up to four IOEs per column I/O block.

Each column or row I/O block interfaces with its adjacent LAB and MultiTrack

interconnect to distribute signals throughout the device. The row I/O blocks drive

row, column, or DirectLink interconnects. The column I/O blocks drive column

interconnects.

1

5M40Z, 5M80Z, 5M160Z, and 5M240Z devices have a maximum of five IOEs per row

I/O block.

Figure 2–20 shows how a row I/O block connects to the logic array.

Figure 2–20. Row I/O Block Connection to the Interconnect (Note 1)

R4 Interconnects

C4 Interconnects

I/O Block Local

Interconnect

data_out

[6..0]

7

OE

[6..0]

7

LAB

Row

I/O Block

fast_out

[6..0]

7

data_in[6..0]

Direct Link

Interconnect

from Adjacent LAB

Direct Link

Interconnect

Row I/O Block

Contains up to

Seven IOEs

to Adjacent LAB

LAB Column

clock [3..0]

LAB Local

Interconnect

Note to Figure 2–20:

(1) Each of the seven IOEs in the row I/O block can have one data_outor fast_outoutput, one OEoutput, and

one data_ininput.

MAX V Device Handbook

December 2010 Altera Corporation

Chapter 2: MAX V Architecture

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I/O Structure

Figure 2–21 shows how a column I/O block connects to the logic array.

Figure 2–21. Column I/O Block Connection to the Interconnect (Note 1)

Column I/O

Block Contains

Up To 4 IOEs

Column I/O Block

data_in

[3..0]

data_out

[3..0]

OE

[3..0]

fast_out

[3..0]

4

I/O Block

Local Interconnect

Fast I/O

Interconnect

Path

LAB Column

Clock [3..0]

R4 Interconnects

LAB

LAB Local

Interconnect

LAB Local

Interconnect

LAB Local

Interconnect

C4 Interconnects

Note to Figure 2–21:

(1) Each of the four IOEs in the column I/O block can have one data_outor fast_outoutput, one OEoutput, and

one data_ininput.

I/O Standards and Banks

Table 2–4 lists the I/O standards supported by MAX V devices.

Table 2–4. MAX V I/O Standards (Part 1 of 2)

Output Supply Voltage (V_CCIO

)

I/O Standard

Type

(V)

3.3-V LVTTL/LVCMOS

2.5-V LVTTL/LVCMOS

1.8-V LVTTL/LVCMOS

1.5-V LVCMOS

Single-ended

3.3

2.5

1.8

1.5

1.2

1.2-V LVCMOS

December 2010 Altera Corporation

MAX V Device Handbook

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Chapter 2: MAX V Architecture

I/O Structure

Table 2–4. MAX V I/O Standards (Part 2 of 2)

I/O Standard

Output Supply Voltage (V_CCIO

)

Type

(V)

3.3-V PCI (1)

LVDS (2)

Single-ended

Differential

3.3

2.5

RSDS (3)

Notes to Table 2–4:

(1) The 3.3-V PCI compliant I/O is supported in Bank 3 of the 5M1270Z and 5M2210Z devices.

(2) MAX V devices only support emulated LVDS output using a three resistor network (LVDS_E_3R).

(3) MAX V devices only support emulated RSDS output using a three resistor network (RSDS_E_3R).

The 5M40Z, 5M80Z, 5M160Z, 5M240Z, and 5M570Z devices support two I/O banks,

as shown in Figure 2–22. Each of these banks support all the LVTTL, LVCMOS, LVDS,

and RSDS standards shown in Table 2–4. PCI compliant I/O is not supported in these

devices and banks.

Figure 2–22. I/O Banks for 5M40Z, 5M80Z, 5M160Z, 5M240Z, and 5M570Z Devices (Note 1), (2)

I/O Bank 1

I/O Bank 2

All I/O Banks Support

3.3-V LVTTL/LVCMOS,

2.5-V LVTTL/LVCMOS,

1.8-V LVTTL/LVCMOS,

1.5-V LVCMOS,

1.2-V LVCMOS (3),

LVDS (4),

RSDS (5)

Notes to Figure 2–22:

(1) Figure 2–22 is a top view of the silicon die.

(2) Figure 2–22 is a graphical representation only. Refer to the pin list and the Quartus II software for exact pin locations.

(3) This I/O standard is not supported in Bank 1.

(4) Emulated LVDS output using a three resistor network (LVDS_E_3R).

(5) Emulated RSDS output using a three resistor network (RSDS_E_3R).

MAX V Device Handbook

December 2010 Altera Corporation

Chapter 2: MAX V Architecture

2–31

I/O Structure

The 5M1270Z and 5M2210Z devices support four I/O banks, as shown in Figure 2–23.

Each of these banks support all of the LVTTL, LVCMOS, LVDS, and RSDS standards

shown in Table 2–4. PCI compliant I/O is supported in Bank 3. Bank 3 supports the

PCI clamping diode on inputs and PCI drive compliance on outputs. You must use

Bank 3 for designs requiring PCI compliant I/O pins. The Quartus II software

automatically places I/O pins in this bank if assigned with the PCI I/O standard.

Figure 2–23. I/O Banks for 5M1270Z and 5M2210Z Devices (Note 1), (2)

I/O Bank 2

Also Supports

the 3.3-V PCI

I/O Standard

All I/O Banks Support

3.3-V LVTTL/LVCMOS,

2.5-V LVTTL/LVCMOS,

1.8-V LVTTL/LVCMOS,

1.5-V LVCMOS,

I/O Bank 1

I/O Bank 3

1.2-V LVCMOS (3),

LVDS (4),

RSDS(5)

I/O Bank 4

Notes to Figure 2–23:

(1) Figure 2–23 is a top view of the silicon die.

(2) Figure 2–23 is a graphical representation only. Refer to the pin list and the Quartus II software for exact pin locations.

(3) This I/O standard is not supported in Bank 1.

(4) Emulated LVDS output using a three resistor network (LVDS_E_3R).

(5) Emulated RSDS output using a three resistor network (RSDS_E_3R).

Each I/O bank has dedicated V_CCIOpins that determine the voltage standard support

in that bank. A single device can support 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V interfaces;

each individual bank can support a different standard. Each I/O bank can support

multiple standards with the same V_CCIOfor input and output pins. For example, when

V_CCIOis 3.3 V, Bank 3 can support LVTTL, LVCMOS, and 3.3-V PCI. V_CCIOpowers

both the input and output buffers in MAX V devices.

The JTAG pins for MAX V devices are dedicated pins that cannot be used as regular

I/O pins. The pins TMS, TDI, TDO, and TCKsupport all the I/O standards shown in

Table 2–4 on page 2–29 except for PCI and 1.2-V LVCMOS. These pins reside in Bank 1

for all MAX V devices and their I/O standard support is controlled by the V_CCIO

setting for Bank 1.

December 2010 Altera Corporation

MAX V Device Handbook

2–32

Chapter 2: MAX V Architecture

I/O Structure

PCI Compliance

The MAX V 5M1270Z and 5M2210Z devices are compliant with PCI applications as

well as all 3.3-V electrical specifications in the PCI Local Bus Specification Revision 2.2.

These devices are also large enough to support PCI intellectual property (IP) cores.

Table 2–5 shows the MAX V device speed grades that meet the PCI timing

specifications.

Table 2–5. 3.3-V PCI Electrical Specifications and PCI Timing Support for MAX V Devices

Device

5M1270Z

5M2210Z

33-MHz PCI

All Speed Grades

LVDS and RSDS Channels

The MAX V device supports emulated LVDS and RSDS outputs on both row and

column I/O banks. You can configure the rows and columns as emulated LVDS or

RSDS output buffers that use two single-ended output buffers with three external

resistor networks.

Table 2–6. LVDS and RSDS Channels supported in MAX V Devices (Note 1)

Device

5M40Z

64 MBGA

10 eTx

—

64 EQFP

20 eTx

—

68 MBGA

—

100 TQFP 100 MBGA 144 TQFP

256 FBGA

—

324 FBGA

—

5M80Z

20 eTx

—

33 eTx

28 eTx

—

5M160Z

5M240Z

5M570Z

5M1270Z

5M2210Z

33 eTx

28 eTx

—

49 eTx

42 eTx

—

75 eTx

90 eTx

83 eTx

—

115 eTx

—

Note to Table 2–6:

(1) eTx = emulated LVDS output buffers (LVDS_E_3R) or emulated RSDS output buffers (RSDS_E_3R).

Schmitt Trigger

The input buffer for each MAX V device I/O pin has an optional Schmitt trigger

setting for the 3.3-V and 2.5-V standards. The Schmitt trigger allows input buffers to

respond to slow input edge rates with a fast output edge rate. Most importantly,

Schmitt triggers provide hysteresis on the input buffer, preventing slow-rising noisy

input signals from ringing or oscillating on the input signal driven into the logic array.

This provides system noise tolerance on MAX V inputs, but adds a small, nominal

input delay.

The JTAG input pins (TMS, TCK, and TDI) have Schmitt trigger buffers that are always

enabled.

1

The TCKinput is susceptible to high pulse glitches when the input signal fall time is

greater than 200 ns for all I/O standards.

MAX V Device Handbook

December 2010 Altera Corporation

Chapter 2: MAX V Architecture

2–33

I/O Structure

Output Enable Signals

Each MAX V IOE output buffer supports output enable signals for tri-state control.

The output enable signal can originate from the GCLK[3..0]global signals or from the

MultiTrack interconnect. The MultiTrack interconnect routes output enable signals

and allows for a unique output enable for each output or bidirectional pin.

MAX V devices also provide a chip-wide output enable pin (DEV_OE) to control the

output enable for every output pin in the design. An option set before compilation in

the Quartus II software controls this pin. This chip-wide output enable uses its own

routing resources and does not use any of the four global resources. If this option is

turned on, all outputs on the chip operate normally when DEV_OEis asserted. When

the pin is deasserted, all outputs are tri-stated. If this option is turned off, the DEV_OE

pin is disabled when the device operates in user mode and is available as a user I/O

pin.

Programmable Drive Strength

The output buffer for each MAX V device I/O pin has two levels of programmable

drive strength control for each of the LVTTL and LVCMOS I/O standards.

Programmable drive strength provides system noise reduction control for high

performance I/O designs. Although a separate slew-rate control feature exists, using

the lower drive strength setting provides signal slew-rate control to reduce system

noise and signal overshoot without the large delay adder associated with the

slew-rate control feature. Table 2–7 lists the possible settings for the I/O standards

with drive strength control. The Quartus II software uses the maximum current

strength as the default setting. The PCI I/O standard is always set at 20 mA with no

alternate setting.

Table 2–7. Programmable Drive Strength (Note 1)

I/O Standard

3.3-V LVTTL

IOH/IOL Current Strength Setting (mA)

16

8

3.3-V LVCMOS

4

14

7

2.5-V LVTTL/LVCMOS

1.8-V LVTTL/LVCMOS

1.5-V LVCMOS

6

3

4

2

1.2-V LVCMOS

3

Note to Table 2–7:

(1) The I_OHcurrent strength numbers shown are for a condition of a V_OUT= V_OHminimum, where the V_OH

minimum is specified by the I/O standard. The I_OLcurrent strength numbers shown are for a condition of a

V_OUT= V_OLmaximum, where the V_OLmaximum is specified by the I/O standard. For 2.5-V LVTTL/LVCMOS,

the I_OHcondition is V_OUT= 1.7 V and the I_OLcondition is V_OUT= 0.7 V.

1

The programmable drive strength feature can be used simultaneously with the

slew-rate control feature.

December 2010 Altera Corporation

MAX V Device Handbook

2–34

Chapter 2: MAX V Architecture

I/O Structure

Slew-Rate Control

The output buffer for each MAX V device I/O pin has a programmable output

slew-rate control that can be configured for low noise or high-speed performance. A

faster slew rate provides high-speed transitions for high-performance systems.

However, these fast transitions may introduce noise transients into the system. A slow

slew rate reduces system noise, but adds a nominal output delay to rising and falling

edges. The lower the voltage standard (for example, 1.8-V LVTTL) the larger the

output delay when slow slew is enabled. Each I/O pin has an individual slew-rate

control, allowing you to specify the slew rate on a pin-by-pin basis. The slew-rate

control affects both the rising and falling edges. If no slew-rate control is specified, the

Quartus II software defaults to a fast slew rate.

1

The slew-rate control feature can be used simultaneously with the programmable

drive strength feature.

Open-Drain Output

MAX V devices provide an optional open-drain (equivalent to open-collector) output

for each I/O pin. This open-drain output enables the device to provide system-level

control signals (for example, interrupt and write enable signals) that can be asserted

by any of several devices. This output can also provide an additional wired-OR plane.

Programmable Ground Pins

Each unused I/O pin on MAX V devices can be used as an additional ground pin.

This programmable ground feature does not require the use of the associated LEs in

the device. In the Quartus II software, unused pins can be set as programmable GND

on a global default basis or they can be individually assigned. Unused pins also have

the option of being set as tri-stated input pins.

Bus-Hold

Each MAX V device I/O pin provides an optional bus-hold feature. The bus-hold

circuitry can hold the signal on an I/O pin at its last-driven state. Because the bus-

hold feature holds the last-driven state of the pin until the next input signal is present,

an external pull-up or pull-down resistor is not necessary to hold a signal level when

the bus is tri-stated.

The bus-hold circuitry also pulls un-driven pins away from the input threshold

voltage where noise can cause unintended high-frequency switching. You can select

this feature individually for each I/O pin. The bus-hold output will drive no higher

than V_CCIOto prevent overdriving signals. If the bus-hold feature is enabled, the

device cannot use the programmable pull-up option.

The bus-hold circuitry is only active after the device has fully initialized. The bus-hold

circuit captures the value on the pin present at the moment user mode is entered.

MAX V Device Handbook

December 2010 Altera Corporation

Chapter 2: MAX V Architecture

2–35

I/O Structure

Programmable Pull-Up Resistor

Each MAX V device I/O pin provides an optional programmable pull-up resistor

during user mode. If you enable this feature for an I/O pin, the pull-up resistor holds

the output to the V_CCIOlevel of the output pin’s bank.

1

The programmable pull-up resistor feature should not be used at the same time as the

bus-hold feature on a given I/O pin.

The programmable pull-up resistor is active during power-up, ISP, and if the device is

unprogrammed.

Programmable Input Delay

The MAX V IOE includes a programmable input delay that is activated to ensure zero

hold times. A path where a pin directly drives a register, with minimal routing

between the two, may require the delay to ensure zero hold time. However, a path

where a pin drives a register through long routing or through combinational logic

may not require the delay to achieve a zero hold time. The Quartus II software uses

this delay to ensure zero hold times when needed.

MultiVolt I/O Interface

The MAX V architecture supports the MultiVolt I/O interface feature, which allows

MAX V devices in all packages to interface with systems of different supply voltages.

The devices have one set of VCCpins for internal operation (V_CCINT), and up to four

sets for input buffers and I/O output driver buffers (V_CCIO), depending on the

number of I/O banks available in the devices where each set of VCCIOpins powers one

I/O bank. The 5M40Z, 5M80Z, 5M160Z, 5M240Z, and 5M570Z devices each have two

I/O banks while the 5M1270Z and 5M2210Z devices each have four I/O banks.

Connect VCCIOpins to either a 1.2-, 1.5-, 1.8-, 2.5-, or 3.3-V power supply, depending

on the output requirements. The output levels are compatible with systems of the

same voltage as the power supply (that is, when VCCIOpins are connected to a 1.5-V

power supply, the output levels are compatible with 1.5-V systems). When VCCIOpins

are connected to a 3.3-V power supply, the output high is 3.3 V and is compatible with

3.3-V or 5.0-V systems. Table 2–8 summarizes MAX V MultiVolt I/O support.

Table 2–8. MultiVolt I/O Support in MAX V Devices (Part 1 of 2) (Note 1)

Input Signal

1.5 V 1.8 V 2.5 V 3.3 V

Output Signal

5.0 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 5.0 V

VCCIO (V)

1.2 V

v

—

v

—

v

—

v

—

v

—

v

—

v

—

v

—

1.2

1.5

1.8

2.5

—

v

—

v (2) v (2)

v (3) v (3) v (3)

—

December 2010 Altera Corporation

MAX V Device Handbook

2–36

Chapter 2: MAX V Architecture

Document Revision History

Table 2–8. MultiVolt I/O Support in MAX V Devices (Part 2 of 2) (Note 1)

Input Signal

VCCIO (V)

Output Signal

5.0 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 5.0 V

1.2 V

1.5 V 1.8 V 2.5 V 3.3 V

—

v (4)

v

v (5) v (6) v (6) v (6) v (6)

v

v (7)

3.3

Notes to Table 2–8:

(1) To drive inputs higher than V_CCIObut less than 4.0 V including the overshoot, disable the I/O clamp diode. However, to drive 5.0-V signals to

the device, enable the I/O clamp diode to prevent V_Ifrom rising above 4.0 V. Use an external diode if the I/O pin does not support the clamp

diode.

(2) When V_CCIO= 1.8 V, a MAX V device can drive a 1.2-V or 1.5-V device with 1.8-V tolerant inputs.

(3) When V_CCIO= 2.5 V, a MAX V device can drive a 1.2-V, 1.5-V, or 1.8-V device with 2.5-V tolerant inputs.

(4) When V_CCIO= 3.3 V and a 2.5-V input signal feeds an input pin, the VCCIO supply current will be slightly larger than expected.

(5) MAX V devices can be 5.0-Vtolerant with the use of an external resistor and the internal I/Oclamp diode on the 5M1270Z and 5M2210Z devices.

Use an external clamp diode if the internal clamp diode is not available.

(6) When V_CCIO= 3.3 V, a MAX V device can drive a 1.2-V, 1.5-V, 1.8-V, or 2.5-V device with 3.3-V tolerant inputs.

(7) When V_CCIO= 3.3 V, a MAX V device can drive a device with 5.0-V TTL inputs but not 5.0-V CMOS inputs. For 5.0-V CMOS, open-drain setting

with internal I/O clamp diode (available only on 5M1270Z and 5M2210Z devices) and external resistor is required. Use an external clamp diode

if the internal clamp diode is not available.

Document Revision History

Table 2–9 lists the revision history for this chapter.

Table 2–9. Document Revision History

Date

Version

Changes

December 2010

1.0

Initial release.

MAX V Device Handbook

December 2010 Altera Corporation

3. DC and Switching Characteristics for

MAX V Devices

May 2011

MV51003-1.2

This chapter covers the electrical and switching characteristics for MAX^®V devices.

Electrical characteristics include operating conditions and power consumptions. This

chapter also describes the timing model and specifications.

You must consider the recommended DC and switching conditions described in this

chapter to maintain the highest possible performance and reliability of the MAX V

devices.

This chapter contains the following sections:

■

“Operating Conditions” on page 3–1

“Power Consumption” on page 3–10

“Timing Model and Specifications” on page 3–10

Operating Conditions

Table 3–1 through Table 3–15 on page 3–9 list information about absolute maximum

ratings, recommended operating conditions, DC electrical characteristics, and other

specifications for MAX V devices.

Absolute Maximum Ratings

Table 3–1 lists the absolute maximum ratings for the MAX V device family.

Table 3–1. Absolute Maximum Ratings for MAX V Devices (Note 1), (2)

Symbol

V_CCINT

Parameter

Internal supply voltage

I/O supply voltage

Conditions

Minimum

–0.5

Maximum

2.4

Unit

V

With respect to ground

V_CCIO

V_I

—

–0.5

4.6

V

DC input voltage

—

–0.5

4.6

V

I_OUT

T_STG

T_AMB

DC output current, per pin

Storage temperature

Ambient temperature

–25

25

mA

°C

No bias

–65

150

Under bias (3)

–65

135

TQFP and BGA packages

under bias

T_J

Junction temperature

—

135

°C

Notes to Table 3–1:

(1) For more information, refer to the Operating Requirements for Altera Devices Data Sheet.

(2) Conditions beyond those listed in Table 3–1 may cause permanent damage to a device. Additionally, device operation at the absolute maximum

ratings for extended periods of time may have adverse affects on the device.

(3) For more information about “under bias” conditions, refer to Table 3–2.

and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at

www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but

reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any

information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device

specifications before relying on any published information and before placing orders for products or services.

MAX V Device Handbook

May 2011

Subscribe

3–2

Chapter 3: DC and Switching Characteristics for MAX V Devices

Operating Conditions

Recommended Operating Conditions

Table 3–2 lists recommended operating conditions for the MAX V device family.

Table 3–2. Recommended Operating Conditions for MAX V Devices

Symbol

Parameter

Conditions

Minimum

Maximum

Unit

1.8-V supply voltage for internal logic and

in-system programming (ISP)

V_CCINT(1)

MAX V devices

1.71

1.89

V

Supply voltage for I/O buffers, 3.3-V

operation

—

3.00

2.375

1.71

3.60

2.625

1.89

V

Supply voltage for I/O buffers, 2.5-V

operation

Supply voltage for I/O buffers, 1.8-V

operation

V_CCIO(1)

Supply voltage for I/O buffers, 1.5-V

operation

1.425

1.14

1.575

1.26

Supply voltage for I/O buffers, 1.2-V

operation

V_I

Input voltage

(2), (3), (4)

—

–0.5

0

4.0

V_CCIO

85

V

V_O

Output voltage

V

Commercial range

Industrial range

Extended range (5)

0

°C

T_J

Operating junction temperature

–40

100

125

Notes to Table 3–2:

(1) MAX V device ISP and/or user flash memory (UFM) programming using JTAG or logic array is not guaranteed outside the recommended

operating conditions (for example, if brown-out occurs in the system during a potential write/program sequence to the UFM, Altera recommends

that you read back the UFM contents and verify it against the intended write data).

(2) The minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V for input currents less than 100 mA and periods

shorter than 20 ns.

(3) During transitions, the inputs may overshoot to the voltages shown below based on the input duty cycle. The DC case is equivalent to 100%

duty cycle. For more information about 5.0-V tolerance, refer to the Using MAX V Devices in Multi-Voltage Systems chapter.

V_IN

Max. Duty Cycle

4.0 V 100% (DC)

4.1 V 90%

4.2 V 50%

4.3 V 30%

4.4 V 17%

4.5 V 10%

(4) All pins, including the clock, I/O, and JTAG pins, may be driven before V_CCINTand V_CCIOare powered.

(5) For the extended temperature range of 100 to 125°C, MAX V UFM programming (erase/write) is only supported using the JTAG interface. UFM

programming using the logic array interface is not guaranteed in this range.

MAX V Device Handbook

May 2011 Altera Corporation

Chapter 3: DC and Switching Characteristics for MAX V Devices

3–3

Operating Conditions

Programming/Erasure Specifications

Table 3–3 lists the programming/erasure specifications for the MAX V device family.

Table 3–3. Programming/Erasure Specifications for MAX V Devices

Parameter

Erase and reprogram cycles

Note to Table 3–3:

Block

Minimum

Typical

—

Maximum

1000 (1)

100

Unit

UFM

Configuration flash memory (CFM)

—

Cycles

—

(1) This value applies to the commercial grade devices. For the industrial grade devices, the value is 100 cycles.

DC Electrical Characteristics

Table 3–4 lists DC electrical characteristics for the MAX V device family.

Table 3–4. DC Electrical Characteristics for MAX V Devices (Note 1) (Part 1 of 2)

Symbol

Parameter

Conditions

Minimum

Typical

Maximum

Unit

I_I

Input pin leakage current V_I= V_CCIOmax to 0 V (2)

–10

—

10

µA

Tri-stated I/O pin leakage

V_O= V_CCIOmax to 0 V (2)

current

I_OZ

–10

—

25

27

25

10

µA

5M40Z, 5M80Z, 5M160Z, and

5M240Z (Commercial grade)

(4), (5)

—

90

5M240Z (Commercial grade)

(6)

—

96

5M40Z, 5M80Z, 5M160Z, and

5M240Z (Industrial grade)

(5), (7)

V_CCINTsupply current

(standby) (3)

—

139

I_CCSTANDBY

5M240Z (Industrial grade) (6)

—

27

152

96

µA

5M570Z (Commercial grade)

(4)

5M570Z (Industrial grade) (7)

5M1270Z and 5M2210Z

V_CCIO= 3.3 V

—

27

2

152

—

µA

mA

mV

400

190

—

Hysteresis for Schmitt

trigger input (9)

V_SCHMITT(8)

V_CCIO= 2.5 V

—

V_CCINTsupply current

during power-up (10)

I_CCPOWERUP

MAX V devices

—

40

mA

V_CCIO= 3.3 V (11)

V_CCIO= 2.5 V (11)

5

—

25

40

k

10

25

45

80

Value of I/O pin pull-up

resistor during user

mode and ISP

R_PULLUP

V

_CCIO= 1.8 V (11)

V_CCIO= 1.5 V (11)

_CCIO= 1.2 V (11)

60

95

V

130

May 2011 Altera Corporation

MAX V Device Handbook

3–4

Chapter 3: DC and Switching Characteristics for MAX V Devices

Operating Conditions

Table 3–4. DC Electrical Characteristics for MAX V Devices (Note 1) (Part 2 of 2)

Symbol

Parameter

Conditions

Minimum

Typical

Maximum

Unit

I/O pin pull-up resistor

current when I/O is

unprogrammed

I_PULLUP

—

300

µA

Input capacitance for

user I/O pin

C_IO

—

8

pF

Input capacitance for

dual-purpose GCLK/user

I/O pin

C_GCLK

Notes to Table 3–4:

(1) Typical values are for T_A= 25°C, V_CCINT= 1.8 V and V_CCIO= 1.2, 1.5, 1.8, 2.5, or 3.3 V.

(2) This value is specified for normal device operation. The value may vary during power-up. This applies to all V_CCIOsettings (3.3, 2.5, 1.8, 1.5,

and 1.2 V).

(3) V_I= ground, no load, and no toggling inputs.

(4) Commercial temperature ranges from 0°C to 85°C with the maximum current at 85°C.

(5) Not applicable to the T144 package of the 5M240Z device.

(6) Only applicable to the T144 package of the 5M240Z device.

(7) Industrial temperature ranges from –40°C to 100°C with the maximum current at 100°C.

(8) This value applies to commercial and industrial range devices. For extended temperature range devices, the V_SCHMITTtypical value is 300 mV

for V_CCIO= 3.3 V and 120 mV for V_CCIO= 2.5 V.

(9) The TCKinput is susceptible to high pulse glitches when the input signal fall time is greater than 200 ns for all I/O standards.

(10) This is a peak current value with a maximum duration of t_CONFIGtime.

(11) Pin pull-up resistance values will lower if an external source drives the pin higher than V_CCIO

.

MAX V Device Handbook

May 2011 Altera Corporation

Chapter 3: DC and Switching Characteristics for MAX V Devices

3–5

Operating Conditions

Output Drive Characteristics

Figure 3–1 shows the typical drive strength characteristics of MAX V devices.

Figure 3–1. Output Drive Characteristics of MAX V Devices (Note 1)

MAX V Output Drive I_OHCharacteristics

(Maximum Drive Strength)

MAX V Output Drive I_OLCharacteristics

(Maximum Drive Strength)

60

50

40

30

20

10

0

70

60

50

40

30

20

10

0

3.3-V VCCIO

2.5-V VCCIO

1.8-V VCCIO

1.5-V VCCIO

1.2-V VCCIO (2)

1.5-V VCCIO

1.2-V VCCIO (2)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

Voltage (V)

MAX V Output Drive I_OLCharacteristics

(Minimum Drive Strength)

MAX V Output Drive I_OHCharacteristics

(Minimum Drive Strength)

30

25

20

15

10

5

35

3.3-V VCCIO

30

25

20

15

10

5

2.5-V VCCIO

1.8-V VCCIO

1.5-V VCCIO

1.8-V VCCIO

1.5-V VCCIO

0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

Voltage (V)

Notes to Figure 3–1:

(1) The DC output current per pin is subject to the absolute maximum rating of Table 3–1 on page 3–1.

(2) 1.2-V V_CCIOis only applicable to the maximum drive strength.

I/O Standard Specifications

Table 3–5 through Table 3–13 on page 3–8 list the I/O standard specifications for the

MAX V device family.

Table 3–5. 3.3-V LVTTL Specifications for MAX V Devices

Symbol

V_CCIO

Parameter

I/O supply voltage

Conditions

Minimum

3.0

Maximum

3.6

Unit

V

—

V_IH

High-level input voltage

Low-level input voltage

High-level output voltage

Low-level output voltage

—

1.7

4.0

V

V_IL

—

–0.5

2.4

0.8

V

V_OH

IOH = –4 mA (1)

IOL = 4 mA (1)

—

V

V_OL

—

0.45

V

Note to Table 3–5:

(1) This specification is supported across all the programmable drive strength settings available for this I/O standard, as shown in the

MAX V Device Architecture chapter.

May 2011 Altera Corporation

MAX V Device Handbook

3–6

Chapter 3: DC and Switching Characteristics for MAX V Devices

Operating Conditions

Table 3–6. 3.3-V LVCMOS Specifications for MAX V Devices

Symbol

V_CCIO

Parameter

I/O supply voltage

Conditions

Minimum

3.0

Maximum

3.6

Unit

V

—

V_IH

V_IL

High-level input voltage

Low-level input voltage

1.7

4.0

V

–0.5

0.8

V

_CCIO= 3.0,

IOH = –0.1 mA (1)

_CCIO= 3.0,

IOL = 0.1 mA (1)

V_OH

High-level output voltage

Low-level output voltage

V_CCIO– 0.2

—

V

V_OL

0.2

Note to Table 3–6:

(1) This specification is supported across all the programmable drive strength settings available for this I/O standard, as shown in the

MAX V Device Architecture chapter.

Table 3–7. 2.5-V I/O Specifications for MAX V Devices

Symbol

V_CCIO

Parameter

I/O supply voltage

Conditions

—

Minimum

2.375

1.7

Maximum

2.625

4.0

Unit

V

V_IH

V_IL

High-level input voltage

Low-level input voltage

—

V

—

–0.5

2.1

0.7

V

IOH = –0.1 mA (1)

IOH = –1 mA (1)

IOH = –2 mA (1)

IOL = 0.1 mA (1)

IOL = 1 mA (1)

IOL = 2 mA (1)

—

V

V_OH

High-level output voltage

Low-level output voltage

2.0

—

V

1.7

—

V

—

0.2

V

V_OL

—

0.4

V

—

0.7

V

Note to Table 3–7:

(1) This specification is supported across all the programmable drive strength settings available for this I/O standard, as shown in the

MAX V Device Architecture chapter.

Table 3–8. 1.8-V I/O Specifications for MAX V Devices

Symbol

V_CCIO

Parameter

I/O supply voltage

Conditions

Minimum

1.71

Maximum

1.89

Unit

V

—

V_IH

High-level input voltage

Low-level input voltage

High-level output voltage

Low-level output voltage

—

0.65 × V_CCIO

–0.3

2.25 (2)

0.35 × V_CCIO

—

V

V_IL

—

V

V_OH

IOH = –2 mA (1)

IOL = 2 mA (1)

V_CCIO– 0.45

—

V

V_OL

0.45

V

Notes to Table 3–8:

(1) This specification is supported across all the programmable drive strength settings available for this I/O standard, as shown in the

MAX V Device Architecture chapter.

(2) This maximum V_IHreflects the JEDEC specification. The MAX V input buffer can tolerate a V_IHmaximum of 4.0, as specified by the V_Iparameter

in Table 3–2 on page 3–2.

MAX V Device Handbook

May 2011 Altera Corporation

Chapter 3: DC and Switching Characteristics for MAX V Devices

3–7

Operating Conditions

Table 3–9. 1.5-V I/O Specifications for MAX V Devices

Symbol

V_CCIO

Parameter

I/O supply voltage

Conditions

Minimum

1.425

Maximum

1.575

Unit

V

—

V_IH

High-level input voltage

Low-level input voltage

High-level output voltage

Low-level output voltage

—

0.65 × V_CCIO

–0.3

V_CCIO+ 0.3 (2)

0.35 × V_CCIO

—

V

V_IL

—

V

V_OH

IOH = –2 mA (1)

IOL = 2 mA (1)

0.75 × V_CCIO

—

V

V_OL

0.25 × V_CCIO

V

Notes to Table 3–9:

(1) This specification is supported across all the programmable drive strength settings available for this I/O standard, as shown in the

MAX V Device Architecture chapter.

(2) This maximum V_IHreflects the JEDEC specification. The MAX V input buffer can tolerate a V_IHmaximum of 4.0, as specified by the V_Iparameter

in Table 3–2 on page 3–2.

Table 3–10. 1.2-V I/O Specifications for MAX V Devices

Symbol

V_CCIO

Parameter

I/O supply voltage

Conditions

Minimum

1.14

Maximum

1.26

Unit

V

—

V_IH

High-level input voltage

Low-level input voltage

High-level output voltage

Low-level output voltage

—

0.8 × V_CCIO

–0.3

V_CCIO+ 0.3

0.25 × V_CCIO

—

V

V_IL

—

V

V_OH

IOH = –2 mA (1)

IOL = 2 mA (1)

0.75 × V_CCIO

—

V

V_OL

0.25 × V_CCIO

V

Note to Table 3–10:

(1) This specification is supported across all the programmable drive strength settings available for this I/O standard, as shown in the

MAX V Device Architecture chapter.

Table 3–11. 3.3-V PCI Specifications for MAX V Devices (Note 1)

Symbol

V_CCIO

Parameter

I/O supply voltage

Conditions

Minimum

3.0

Typical

3.3

—

Maximum

3.6

Unit

—

V

V_IH

High-level input voltage

Low-level input voltage

High-level output voltage

Low-level output voltage

0.5 × V_CCIO

–0.5

V_CCIO+ 0.5

0.3 × V_CCIO

—

V_IL

—

V_OH

IOH = –500 µA

IOL = 1.5 mA

0.9 × V_CCIO

—

V_OL

—

0.1 × V_CCIO

Note to Table 3–11:

(1) 3.3-V PCI I/O standard is only supported in Bank 3 of the 5M1270Z and 5M2210Z devices.

Table 3–12. LVDS Specifications for MAX V Devices (Note 1)

Symbol

V_CCIO

Parameter

I/O supply voltage

Conditions

Minimum

2.375

247

Typical

2.5

Maximum

2.625

Unit

V

—

V_OD

V_OS

Differential output voltage swing

Output offset voltage

—

600

mV

V

1.125

1.25

1.375

Note to Table 3–12:

(1) Supports emulated LVDS output using a three-resistor network (LVDS_E_3R).

May 2011 Altera Corporation

MAX V Device Handbook

3–8

Chapter 3: DC and Switching Characteristics for MAX V Devices

Operating Conditions

Table 3–13. RSDS Specifications for MAX V Devices (Note 1)

Symbol

V_CCIO

Parameter

I/O supply voltage

Conditions

Minimum

2.375

247

Typical

2.5

Maximum

2.625

Unit

V

—

V_OD

V_OS

Differential output voltage swing

Output offset voltage

—

600

mV

V

1.125

1.25

1.375

Note to Table 3–13:

(1) Supports emulated RSDS output using a three-resistor network (RSDS_E_3R).

Bus Hold Specifications

Table 3–14 lists the bus hold specifications for the MAX V device family.

Table 3–14. Bus Hold Specifications for MAX V Devices

V_CCIOLevel

1.8 V

Parameter

Conditions

1.2 V

1.5 V

2.5 V

3.3 V

Unit

Min Max Min Max Min Max Min Max Min Max

Low sustaining

current

V_IN> V_IL(maximum) 10

V_IN< V_IH(minimum) –10

—

20

–20

—

30

–30

—

50

–50

—

70

–70

—

µA

High sustaining

current

Low overdrive

current

0 V < V_IN< V_CCIO

—

130

–130

160

–160

200

–200

300

–300

500

High overdrive

current

—

–500 µA

MAX V Device Handbook

May 2011 Altera Corporation

Chapter 3: DC and Switching Characteristics for MAX V Devices

3–9

Operating Conditions

Power-Up Timing

Table 3–15 lists the power-up timing characteristics for the MAX V device family.

Table 3–15. Power-Up Timing for MAX V Devices

Symbol

Parameter

Device

Temperature Range

Commercial and industrial

Extended

Min

—

Typ

—

Max

200

300

200

300

200

300

200

300

400

300

400

300

400

450

500

450

500

Unit

µs

5M40Z

Commercial and industrial

Extended

5M80Z

5M160Z

Commercial and industrial

Extended

Commercial and industrial

Extended

5M240Z (2)

5M240Z (3)

5M570Z

The amount of time from

when minimum V_CCINTis

reached until the device

enters user mode (1)

Commercial and industrial

Extended

t_CONFIG

Commercial and industrial

Extended

Commercial and industrial

Extended

5M1270Z (4)

5M1270Z (5)

5M2210Z

Commercial and industrial

Extended

Commercial and industrial

Extended

Notes to Table 3–15:

(1) For more information about power-on reset (POR) trigger voltage, refer to the Hot Socketing and Power-On Reset in MAX V Devices chapter.

(2) Not applicable to the T144 package of the 5M240Z device.

(3) Only applicable to the T144 package of the 5M240Z device.

(4) Not applicable to the F324 package of the 5M1270Z device.

(5) Only applicable to the F324 package of the 5M1270Z device.

May 2011 Altera Corporation

MAX V Device Handbook

3–10

Chapter 3: DC and Switching Characteristics for MAX V Devices

Power Consumption

You can use the Altera^®PowerPlay Early Power Estimator and PowerPlay Power

Analyzer to estimate the device power.

f For more information about these power analysis tools, refer to the PowerPlay Early

Power Estimator for Altera CPLDs User Guide and the PowerPlay Power Analysis chapter

in volume 3 of the Quartus II Handbook.

Timing Model and Specifications

MAX V devices timing can be analyzed with the Altera Quartus^®II software, a variety

of industry-standard EDA simulators and timing analyzers, or with the timing model

shown in Figure 3–2.

MAX V devices have predictable internal delays that allow you to determine the

worst-case timing of any design. The software provides timing simulation,

point-to-point delay prediction, and detailed timing analysis for device-wide

performance evaluation.

Figure 3–2. Timing Model for MAX V Devices

Output and Output Enable

Data Delay

t_R4

t_IODR

t_IOE

Data-In/LUT Chain

Output Routing

Delay

User

Flash

Memory

Logic Element

LUT Delay

Output

Delay

t_OD

t_XZ

t_ZX

t_C4

t_LUT

t_COMB

t_FASTIO

t_CO

t_SU

t_H

t_PRE

t_CLR

Input Routing

Delay

I/O Input Delay

t_IN

Register Control

Delay

I/O Pin

t_DL

t_C

From Adjacent LE

t_GLOB

INPUT

Combinational Path Delay

I/O Pin

Global Input Delay

To Adjacent LE

Register Delays

Data-Out

You can derive the timing characteristics of any signal path from the timing model

and parameters of a particular device. You can calculate external timing parameters,

which represent pin-to-pin timing delays, as the sum of the internal parameters.

f For more information, refer to AN629: Understanding Timing in Altera CPLDs.

MAX V Device Handbook

May 2011 Altera Corporation

Chapter 3: DC and Switching Characteristics for MAX V Devices

3–11

Timing Model and Specifications

Preliminary and Final Timing

This section describes the performance, internal, external, and UFM timing

specifications. All specifications are representative of the worst-case supply voltage

and junction temperature conditions.

Timing models can have either preliminary or final status. The Quartus II software

issues an informational message during the design compilation if the timing models

are preliminary. Table 3–16 lists the status of the MAX V device timing models.

Preliminary status means the timing model is subject to change. Initially, timing

numbers are created using simulation results, process data, and other known

parameters. These tests are used to make the preliminary numbers as close to the

actual timing parameters as possible.

Final timing numbers are based on actual device operation and testing. These

numbers reflect the actual performance of the device under the worst-case voltage

and junction temperature conditions.

Table 3–16. Timing Model Status for MAX V Devices

Device

5M40Z

Final

v

5M80Z

v

5M160Z

5M240Z

5M570Z

5M1270Z

5M2210Z

v

Performance

Table 3–17 lists the MAX V device performance for some common designs. All

performance values were obtained with the Quartus II software compilation of

megafunctions.

Table 3–17. Device Performance for MAX V Devices (Part 1 of 2)

Performance

Resources Used

5M40Z/ 5M80Z/ 5M160Z/

Resource

Used

Design Size and

Function

5M1270Z/ 5M2210Z

5M240Z/ 5M570Z

Unit

UFM

Blocks

Mode

LEs

C4

C5, I5

C4

C5, I5

16-bit counter (1)

64-bit counter (1)

16-to-1 multiplexer

32-to-1 multiplexer

16-bit XORfunction

—

16

64

11

24

5

0

184.1

83.2

17.4

12.5

9.0

118.3

80.5

20.4

25.3

16.1

247.5

154.8

8.0

201.1

125.8

9.3

MHz

ns

LE

9.0

11.4

8.2

ns

6.6

ns

16-bit decoder with

single address line

—

5

0

9.2

16.1

6.6

8.2

ns

May 2011 Altera Corporation

MAX V Device Handbook

3–12

Chapter 3: DC and Switching Characteristics for MAX V Devices

Timing Model and Specifications

Table 3–17. Device Performance for MAX V Devices (Part 2 of 2)

Resources Used

Performance

5M40Z/ 5M80Z/ 5M160Z/

5M1270Z/ 5M2210Z

Resource

Used

Design Size and

Function

5M240Z/ 5M570Z

Unit

UFM

Blocks

Mode

LEs

C4

C5, I5

C4

C5, I5

512 × 16

None

3

1

10.0

9.7

10.0

9.7

10.0

8.0

10.0

8.0

MHz

SPI (2)

37

UFM

Parallel

(3)

I²C (3)

512 × 8

73

1

(4)

MHz

kHz

512 × 16

142

100 (5)

Notes to Table 3–17:

(1) This design is a binary loadable up counter.

(2) This design is configured for read-only operation in Extended mode. Read and write ability increases the number of logic elements (LEs) used.

(3) This design is configured for read-only operation. Read and write ability increases the number of LEs used.

(4) This design is asynchronous.

(5) The I²C megafunction is verified in hardware up to 100-kHz serial clock line rate.

Internal Timing Parameters

Internal timing parameters are specified on a speed grade basis independent of device

density. Table 3–18 through Table 3–25 on page 3–19 list the MAX V device internal

timing microparameters for LEs, input/output elements (IOEs), UFM blocks, and

MultiTrack interconnects.

f For more information about each internal timing microparameters symbol, refer to

AN629: Understanding Timing in Altera CPLDs.

Table 3–18. LE Internal Timing Microparameters for MAX V Devices (Part 1 of 2)

5M40Z/ 5M80Z/ 5M160Z/

5M1270Z/ 5M2210Z

5M240Z/ 5M570Z

Symbol

Parameter

Unit

C4

C5, I5

Max

C4

C5, I5

Min

Max

Min

Max

Min

Max

LE combinational look-up

table (LUT) delay

t_LUT

—

1,215

—

2,247

—

742

—

914

ps

t_COMB

t_CLR

Combinational path delay

LE register clear delay

LE register preset delay

—

401

243

—

545

309

—

309

192

—

381

236

—

ps

t_PRE

—

LE register setup time

before clock

t_SU

t_H

260

0

—

321

0

—

271

0

—

333

0

—

ps

LE register hold time

after clock

LE register

clock-to-output delay

t_CO

—

380

—

494

—

305

—

376

MAX V Device Handbook

May 2011 Altera Corporation

Chapter 3: DC and Switching Characteristics for MAX V Devices

3–13

Timing Model and Specifications

Table 3–18. LE Internal Timing Microparameters for MAX V Devices (Part 2 of 2)

5M40Z/ 5M80Z/ 5M160Z/

5M240Z/ 5M570Z

5M1270Z/ 5M2210Z

C4 C5, I5

Symbol

Parameter

Unit

C4

C5, I5

Min

253

—

Max

—

Min

339

—

Max

Min

216

—

Max

—

Min

266

—

Max

Minimum clock high or

low time

t_CLKHL

t_C

—

ps

Register control delay

1,356

1,741

1,114

1,372

Table 3–19. IOE Internal Timing Microparameters for MAX V Devices

5M40Z/ 5M80Z/ 5M160Z/

5M240Z/ 5M570Z

5M1270Z/ 5M2210Z

C4 C5, I5

Symbol

Parameter

Unit

C4

C5, I5

Min

Max

Min

Max

Min

Max

Min

Max

Data output delay from

adjacent LE to I/O block

t_FASTIO

t_IN

—

170

—

428

—

207

—

254

ps

I/O input pad and buffer

delay

—

907

—

986

—

920

—

1,132

2,430

I/O input pad and buffer

t_GLOB(1) delay used as global

2,261

3,322

1,974

ps

signal pin

Internally generated

t_IOE

—

530

318

—

1,410

509

—

374

291

—

460

358

ps

output enable delay

t_DL

Input routing delay

Output delay buffer and

pad delay

t_OD(2)

1,319

1,543

1,383

1,702

Output buffer disable

delay

t_XZ(3)

t_ZX(4)

—

1,045

1,160

—

1,276

1,353

—

982

—

1,209

1,604

ps

Output buffer enable

delay

1,303

Notes to Table 3–19:

(1) Delay numbers for t_GLOBdiffer for each device density and speed grade. The delay numbers for t_GLOB, shown in Table 3–19, are based on a 5M240Z

device target.

(2) For more information about delay adders associated with different I/O standards, drive strengths, and slew rates, refer to Table 3–34 on page 3–24

and Table 3–35 on page 3–25.

(3) For more information about t_XZdelay adders associated with different I/O standards, drive strengths, and slew rates, refer to Table 3–22 on

page 3–15 and Table 3–23 on page 3–15.

(4) For more information about t_ZXdelay adders associated with different I/O standards, drive strengths, and slew rates, refer to Table 3–20 on

page 3–14 and Table 3–21 on page 3–14.

May 2011 Altera Corporation

MAX V Device Handbook

3–14

Chapter 3: DC and Switching Characteristics for MAX V Devices

Timing Model and Specifications

Table 3–20 through Table 3–23 list the adder delays for t_ZXand t_XZmicroparameters

when using an I/O standard other than 3.3-V LVTTL with 16 mA drive strength.

Table 3–20. t_ZXIOE Microparameter Adders for Fast Slew Rate for MAX V Devices

5M40Z/ 5M80Z/ 5M160Z/

5M1270Z/ 5M2210Z

5M240Z/ 5M570Z

Standard

Unit

C4

C5, I5

C4 C5, I5

Min

—

Max

0

Min

—

Max

0

Min

—

Max

0

Min

—

Max

0

16 mA

8 mA

4 mA

14 mA

7 mA

6 mA

3 mA

4 mA

2 mA

3 mA

20 mA

—

ps

3.3-V LVTTL

72

74

101

0

125

0

3.3-V LVCMOS

72

74

101

155

545

721

2012

1590

3269

2860

–18

155

125

191

671

888

126

196

608

681

1162

1245

1889

72

127

197

610

685

2.5-V LVTTL /

LVCMOS

1.8-V LVTTL /

LVCMOS

2477

1957

4024

3520

–22

1157

1244

1856

74

1.5-V LVCMOS

1.2-V LVCMOS

3.3-V PCI

LVDS

126

127

191

RSDS

—

127

191

Table 3–21. t_ZXIOE Microparameter Adders for Slow Slew Rate for MAX V Devices

5M40Z/ 5M80Z/ 5M160Z/

5M1270Z/ 5M2210Z

C4 C5, I5

5M240Z/ 5M570Z

C5, I5

Max

Standard

Unit

C4

Min

—

Max

5,951

6,534

5,951

6,534

9,110

9,830

21,800

23,020

39,120

40,670

69,505

6,534

Min

—

Min

—

Max

6,012

8,785

6,012

8,785

10,072

12,945

21,185

24,597

34,517

39,717

55,800

35

Min

—

Max

5,743

8,516

5,743

8,516

9,803

12,676

20,916

24,328

34,248

39,448

55,531

44

16 mA

8 mA

4 mA

14 mA

7 mA

6 mA

3 mA

4 mA

2 mA

3 mA

20 mA

6,063

6,662

ps

3.3-V LVTTL

6,063

3.3-V LVCMOS

6,662

9,237

2.5-V LVTTL /

LVCMOS

9,977

21,787

23,037

39,067

40,617

70,461

6,662

1.8-V LVTTL /

LVCMOS

1.5-V LVCMOS

1.2-V LVCMOS

3.3-V PCI

MAX V Device Handbook

May 2011 Altera Corporation

Chapter 3: DC and Switching Characteristics for MAX V Devices

3–15

Timing Model and Specifications

Table 3–22. t_XZIOE Microparameter Adders for Fast Slew Rate for MAX V Devices

5M40Z/ 5M80Z/ 5M160Z/

5M1270Z/ 5M2210Z

5M240Z/ 5M570Z

Standard

Unit

C4

C5, I5

C4 C5, I5

Min

—

Max

0

Min

—

Max

0

Min

—

Max

0

Min

—

Max

0

16 mA

8 mA

4 mA

14 mA

7 mA

6 mA

3 mA

4 mA

2 mA

3 mA

20 mA

—

ps

3.3-V LVTTL

–69

0

–69

0

–74

0

–91

0

3.3-V LVCMOS

–69

–7

–69

–10

–69

37

–74

–46

–82

–7

–91

–56

2.5-V LVTTL /

LVCMOS

–66

45

–101

–8

1.8-V LVTTL /

LVCMOS

34

25

119

339

464

817

80

147

418

571

1,006

99

166

190

300

–69

–7

155

179

283

–69

–10

1.5-V LVCMOS

1.2-V LVCMOS

3.3-V PCI

LVDS

–46

–56

RSDS

—

–7

Table 3–23. t_XZIOE Microparameter Adders for Slow Slew Rate for MAX V Devices

5M40Z/ 5M80Z/ 5M160Z/

5M1270Z/ 5M2210Z

5M240Z/ 5M570Z

Standard

Unit

C4

C5, I5

C4 C5, I5

Min

—

Max

171

112

171

112

213

166

441

496

765

903

1,159

112

Min

—

Max

174

116

174

116

213

166

438

494

755

897

Min

—

Max

73

Min

—

Max

–132

553

16 mA

8 mA

4 mA

14 mA

7 mA

6 mA

3 mA

4 mA

2 mA

3 mA

20 mA

ps

3.3-V LVTTL

758

73

–132

553

3.3-V LVCMOS

758

32

–173

509

2.5-V LVTTL /

LVCMOS

714

96

–109

758

1.8-V LVTTL /

LVCMOS

963

238

1,319

400

303

33

1.5-V LVCMOS

1,114

195

1.2-V LVCMOS

3.3-V PCI

1,130

116

373

May 2011 Altera Corporation

MAX V Device Handbook

3–16

Chapter 3: DC and Switching Characteristics for MAX V Devices

Timing Model and Specifications

1

The default slew rate setting for MAX V devices in the Quartus II design software is

“fast”.

Table 3–24. UFM Block Internal Timing Microparameters for MAX V Devices (Part 1 of 2)

5M40Z/ 5M80Z/ 5M160Z/

5M1270Z/ 5M2210Z

5M240Z/ 5M570Z

Symbol

Parameter

Unit

C4

C5, I5

C4 C5, I5

Min

Max

Min

Max

Min

Max

Min

Max

Address register clock

period

t_ACLK

100

—

100

—

100

—

100

—

ns

Address register shift

signal setup to address

register clock

t_ASU

20

—

20

—

20

—

20

—

Address register shift

signal hold to address

register clock

t_AH

ns

Address register data in

setup to address register

clock

t_ADS

Address register data in

hold from address

register clock

t_ADH

t_DCLK

t_DSS

20

100

60

—

20

100

60

—

20

100

60

—

20

100

60

—

ns

Data register clock period

Data register shift signal

setup to data register

clock

Data register shift signal

hold from data register

clock

t_DSH

20

—

20

—

20

—

20

—

ns

Data register data in

setup to data register

clock

t_DDS

Data register data in hold

from data register clock

t_DDH

t_DP

20

0

—

20

0

—

20

0

—

20

0

—

ns

Program signal to data

clock hold time

Maximum delay between

program rising edge to

UFM busysignal rising

edge

t_PB

—

960

—

960

—

960

—

960

ns

Minimum delay allowed

from UFM busysignal

going low to program

signal going low

t_BP

20

—

20

—

20

—

20

—

ns

µs

Maximum length of busy

pulse during a program

t_PPMX

100

MAX V Device Handbook

May 2011 Altera Corporation

Chapter 3: DC and Switching Characteristics for MAX V Devices

3–17

Timing Model and Specifications

Table 3–24. UFM Block Internal Timing Microparameters for MAX V Devices (Part 2 of 2)

5M40Z/ 5M80Z/ 5M160Z/

5M1270Z/ 5M2210Z

5M240Z/ 5M570Z

Symbol

Parameter

Unit

C4

C5, I5

C4 C5, I5

Min

Max

Min

Max

Min

Max

Min

Max

Minimum erasesignal

to address clock hold

time

t_AE

0

—

0

—

0

—

0

—

ns

Maximum delay between

the eraserising edge to

the UFM busysignal

rising edge

t_EB

—

20

960

—

20

960

—

20

960

—

20

960

—

Minimum delay allowed

from the UFM busy

signal going low to

t_BE

ns

erasesignal going low

Maximum length of busy

pulse during an erase

t_EPMX

—

500

5

—

500

5

—

500

5

—

500

5

ms

ns

Delay from data register

clock to data register

output

t_DCO

Delay from OSC_ENA

signal reaching UFM to

rising clock of OSC

leaving the UFM

t_OE

180

—

65

—

180

—

65

—

180

—

65

—

180

—

65

—

ns

Maximum read access

time

t_RA

Maximum delay between

the OSC_ENArising edge

to the erase/program

signal rising edge

t_OSCS

250

Minimum delay allowed

from the

erase/programsignal

going low to OSC_ENA

signal going low

t_OSCH

250

—

250

—

250

—

250

—

ns

May 2011 Altera Corporation

MAX V Device Handbook

3–18

Chapter 3: DC and Switching Characteristics for MAX V Devices

Timing Model and Specifications

Figure 3–3 through Figure 3–5 show the read, program, and erase waveforms for

UFM block timing parameters listed in Table 3–24.

Figure 3–3. UFM Read Waveform

ARShft

t_AH

9 Address Bits

t_ACLK

t_ASU

ARClk

ARDin

DRShft

DRClk

t_ADH

t_ADS

16 Data Bits

t_DSH

t_DCLK

t_DSS

t_DCO

DRDin

DRDout

OSC_ENA

Program

Erase

Busy

Figure 3–4. UFM Program Waveform

9 Address Bits

t_ACLK

ARShft

ARClk

t_AH

t_ADH

t_ASU

ARDin

DRShft

DRClk

DRDin

DRDout

t_ADS

16 Data Bits

t_DCLK

t_DSH

t_DSS

t_DDH

t_DDS

t_OSCH

t_OSCS

OSC_ENA

Program

t_PB

Erase

t_BP

Busy

t_PPMX

MAX V Device Handbook

May 2011 Altera Corporation

Chapter 3: DC and Switching Characteristics for MAX V Devices

3–19

Timing Model and Specifications

Figure 3–5. UFM Erase Waveform

9 Address Bits

ARShft

ARClk

t_ACLK

t_AH

t_ASU

t_ADH

ARDin

DRShft

DRClk

DRDin

DRDout

t_ADS

OSC_ENA

t_OSCS

t_OSCH

Program

Erase

t_EB

t_BE

Busy

t_EPMX

Table 3–25. Routing Delay Internal Timing Microparameters for MAX V Devices

5M40Z/ 5M80Z/ 5M160Z/

5M240Z/ 5M570Z

5M1270Z/ 5M2210Z

Routing

Unit

C4

C5, I5

C4

C5, I5

Min

—

Max

860

Min

—

Max

Min

—

Max

561

445

731

Min

—

Max

690

548

899

t_C4

1,973

1,479

2,947

ps

t_R4

—

655

—

t_LOCAL

—

1,143

—

External Timing Parameters

External timing parameters are specified by device density and speed grade. All

external I/O timing parameters shown are for the 3.3-V LVTTL I/O standard with the

maximum drive strength and fast slew rate. For external I/O timing using standards

other than LVTTL or for different drive strengths, use the I/O standard input and

output delay adders in Table 3–32 on page 3–23 through Table 3–36 on page 3–25.

f For more information about each external timing parameters symbol, refer to

AN629: Understanding Timing in Altera CPLDs.

May 2011 Altera Corporation

MAX V Device Handbook

3–20

Chapter 3: DC and Switching Characteristics for MAX V Devices

Timing Model and Specifications

Table 3–26 lists the external I/O timing parameters for the 5M40Z, 5M80Z, 5M160Z,

and 5M240Z devices.

Table 3–26. Global Clock External I/O Timing Parameters for the 5M40Z, 5M80Z, 5M160Z, and 5M240Z Devices

(Note 1), (2)

C4

C5, I5

Symbol

t_PD1

Parameter

Condition

Unit

Min

—

Max

7.9

5.8

—

Min

—

Max

14.0

8.5

—

Worst case pin-to-pin delay through one LUT

Best case pin-to-pin delay through one LUT

Global clock setup time

10 pF

—

ns

ps

t_PD2

t_SU

t_H

—

2.4

0

4.6

0

Global clock hold time

—

t_CO

t_CH

t_CL

Global clock to output delay

Global clock high time

10 pF

—

2.0

253

6.6

—

2.0

339

8.6

—

Global clock low time

—

Minimum global clock period for

16-bit counter

t_CNT

f_CNT

—

5.4

—

8.4

—

ns

Maximum global clock frequency for 16-bit

counter

184.1

118.3

MHz

Notes to Table 3–26:

(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global

clock input pin maximum frequency.

(2) Not applicable to the T144 package of the 5M240Z device.

Table 3–27 lists the external I/O timing parameters for the T144 package of the

5M240Z device.

Table 3–27. Global Clock External I/O Timing Parameters for the 5M240Z Device (Note 1), (2)

C4

C5, I5

Symbol

t_PD1

Parameter

Condition

Unit

Min

—

Max

9.5

5.7

—

Min

—

Max

17.7

8.5

—

Worst case pin-to-pin delay through one LUT

Best case pin-to-pin delay through one LUT

Global clock setup time

10 pF

—

ns

ps

t_PD2

t_SU

t_H

—

2.2

0

4.4

0

Global clock hold time

—

t_CO

t_CH

t_CL

Global clock to output delay

Global clock high time

10 pF

—

2.0

253

6.7

—

2.0

339

8.7

—

Global clock low time

—

Minimum global clock period for 16-bit

counter

t_CNT

f_CNT

—

5.4

—

8.4

—

ns

Maximum global clock frequency for 16-bit

counter

184.1

118.3

MHz

Notes to Table 3–27:

(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global

clock input pin maximum frequency.

(2) Only applicable to the T144 package of the 5M240Z device.

MAX V Device Handbook

May 2011 Altera Corporation

Chapter 3: DC and Switching Characteristics for MAX V Devices

3–21

Timing Model and Specifications

Table 3–28 lists the external I/O timing parameters for the 5M570Z device.

Table 3–28. Global Clock External I/O Timing Parameters for the 5M570Z Device (Note 1)

C4

C5, I5

Symbol

t_PD1

Parameter

Condition

Unit

Min

—

Max

9.5

5.7

—

Min

—

Max

17.7

8.5

—

Worst case pin-to-pin delay through one LUT

Best case pin-to-pin delay through one LUT

Global clock setup time

10 pF

—

ns

ps

t_PD2

t_SU

t_H

—

2.2

0

4.4

0

Global clock hold time

—

t_CO

t_CH

t_CL

Global clock to output delay

Global clock high time

10 pF

—

2.0

253

6.7

—

2.0

339

8.7

—

Global clock low time

—

Minimum global clock period for 16-bit

counter

t_CNT

f_CNT

—

5.4

—

8.4

—

ns

Maximum global clock frequency for 16-bit

counter

184.1

118.3

MHz

Note to Table 3–28:

(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global

clock input pin maximum frequency.

Table 3–29 lists the external I/O timing parameters for the 5M1270Z device.

Table 3–29. Global Clock External I/O Timing Parameters for the 5M1270Z Device (Note 1), (2)

C4

C5, I5

Symbol

t_PD1

Parameter

Condition

Unit

Min

—

Max

8.1

4.8

—

Min

—

Max

10.0

5.9

—

Worst case pin-to-pin delay through one LUT

Best case pin-to-pin delay through one LUT

Global clock setup time

10 pF

—

ns

ps

t_PD2

t_SU

t_H

—

1.5

0

1.9

0

Global clock hold time

—

t_CO

t_CH

t_CL

Global clock to output delay

Global clock high time

10 pF

—

2.0

216

5.9

—

2.0

266

7.3

—

Global clock low time

—

Minimum global clock period for 16-bit

counter

t_CNT

f_CNT

—

4.0

—

5.0

—

ns

Maximum global clock frequency for 16-bit

counter

247.5

201.1

MHz

Notes to Table 3–29:

(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global

clock input pin maximum frequency.

(2) Not applicable to the F324 package of the 5M1270Z device.

May 2011 Altera Corporation

MAX V Device Handbook

3–22

Chapter 3: DC and Switching Characteristics for MAX V Devices

Timing Model and Specifications

Table 3–30 lists the external I/O timing parameters for the F324 package of the

5M1270Z device.

Table 3–30. Global Clock External I/O Timing Parameters for the 5M1270Z Device (Note 1), (2)

C4

C5, I5

Symbol

t_PD1

Parameter

Condition

Unit

Min

—

Max

9.1

4.8

—

Min

—

Max

11.2

5.9

—

Worst case pin-to-pin delay through one LUT

Best case pin-to-pin delay through one LUT

Global clock setup time

10 pF

—

ns

ps

t_PD2

t_SU

t_H

—

1.5

0

1.9

0

Global clock hold time

—

t_CO

t_CH

t_CL

Global clock to output delay

Global clock high time

10 pF

—

2.0

216

6.0

—

2.0

266

7.4

—

Global clock low time

—

Minimum global clock period for 16-bit

counter

t_CNT

f_CNT

—

4.0

—

5.0

—

ns

Maximum global clock frequency for 16-bit

counter

247.5

201.1

MHz

Notes to Table 3–30:

(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global

clock input pin maximum frequency.

(2) Only applicable to the F324 package of the 5M1270Z device.

Table 3–31 lists the external I/O timing parameters for the 5M2210Z device.

Table 3–31. Global Clock External I/O Timing Parameters for the 5M2210Z Device (Note 1)

C4

C5, I5

Symbol

t_PD1

Parameter

Condition

Unit

Min

—

Max

9.1

4.8

—

Min

—

Max

11.2

5.9

—

Worst case pin-to-pin delay through one LUT

Best case pin-to-pin delay through one LUT

Global clock setup time

10 pF

—

ns

ps

t_PD2

t_SU

t_H

—

1.5

0

1.9

0

Global clock hold time

—

t_CO

t_CH

t_CL

Global clock to output delay

Global clock high time

10 pF

—

2.0

216

6.0

—

2.0

266

7.4

—

Global clock low time

—

Minimum global clock period for 16-bit

counter

t_CNT

f_CNT

—

4.0

—

5.0

—

ns

Maximum global clock frequency for 16-bit

counter

247.5

201.1

MHz

Note to Table 3–31:

(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global

clock input pin maximum frequency.

MAX V Device Handbook

May 2011 Altera Corporation

Chapter 3: DC and Switching Characteristics for MAX V Devices

3–23

Timing Model and Specifications

External Timing I/O Delay Adders

The I/O delay timing parameters for the I/O standard input and output adders and

the input delays are specified by speed grade, independent of device density.

Table 3–32 through Table 3–36 on page 3–25 list the adder delays associated with I/O

pins for all packages. If you select an I/O standard other than 3.3-V LVTTL, add the

input delay adder to the external t_SUtiming parameters listed in Table 3–26 on

page 3–20 through Table 3–31. If you select an I/O standard other than 3.3-V LVTTL

with 16 mA drive strength and fast slew rate, add the output delay adder to the

external t_COand t_PDlisted in Table 3–26 on page 3–20 through Table 3–31.

Table 3–32. External Timing Input Delay Adders for MAX V Devices

5M40Z/ 5M80Z/ 5M160Z/

5M240Z/ 5M570Z

5M1270Z/ 5M2210Z

C4 C5, I5

I/O Standard

Unit

C4

C5, I5

Min

Max

Min

Max

Min

Max

Min

Max

Without Schmitt

Trigger

—

0

—

0

—

0

—

0

ps

3.3-V LVTTL

With Schmitt

Trigger

—

387

0

—

442

0

—

480

0

—

591

0

Without Schmitt

Trigger

3.3-V LVCMOS

With Schmitt

Trigger

387

42

442

42

480

246

787

695

1,334

2,324

0

591

303

968

855

Without Schmitt

Trigger

2.5-V LVTTL /

LVCMOS

With Schmitt

Trigger

429

378

681

1,055

0

483

368

658

1.8-V LVTTL / Without Schmitt

LVCMOS

Trigger

Without Schmitt

Trigger

1.5-V LVCMOS

1,642

2,860

0

Without Schmitt

Trigger

1.2-V LVCMOS

3.3-V PCI

1,010

0

Without Schmitt

Trigger

Table 3–33. External Timing Input Delay t_GLOBAdders for GCLK Pins for MAX V Devices (Part 1 of 2)

5M40Z/ 5M80Z/ 5M160Z/

5M1270Z/ 5M2210Z

5M240Z/ 5M570Z

I/O Standard

Unit

C4

C5, I5

C4

C5, I5

Min

Max

Min

Max

Min

Max

Min

Max

Without Schmitt

Trigger

—

0

—

0

—

0

—

0

ps

3.3-V LVTTL

With Schmitt

Trigger

—

387

—

442

—

400

—

493

May 2011 Altera Corporation

MAX V Device Handbook

3–24

Chapter 3: DC and Switching Characteristics for MAX V Devices

Timing Model and Specifications

Table 3–33. External Timing Input Delay t_GLOBAdders for GCLK Pins for MAX V Devices (Part 2 of 2)

5M40Z/ 5M80Z/ 5M160Z/

5M1270Z/ 5M2210Z

5M240Z/ 5M570Z

I/O Standard

Unit

C4

C5, I5

C4

C5, I5

Min

Max

Min

Max

Min

Max

Min

Max

Without Schmitt

Trigger

—

0

—

0

—

0

—

0

ps

3.3-V LVCMOS

With Schmitt

Trigger

—

387

242

429

378

681

1,055

0

—

442

242

483

368

658

—

400

287

550

459

1,111

2,067

7

—

493

353

677

565

Without Schmitt

Trigger

2.5-V LVTTL /

LVCMOS

With Schmitt

Trigger

1.8-V LVTTL / Without Schmitt

LVCMOS

Trigger

Without Schmitt

Trigger

1.5-V LVCMOS

1,368

2,544

9

Without Schmitt

Trigger

1.2-V LVCMOS

3.3-V PCI

1,010

0

Without Schmitt

Trigger

Table 3–34. External Timing Output Delay and t_ODAdders for Fast Slew Rate for MAX V Devices

5M40Z/ 5M80Z/ 5M160Z/

5M1270Z/ 5M2210Z

C4 C5, I5

5M240Z/ 5M570Z

I/O Standard

Unit

C4

C5, I5

Min

—

Max

0

Min

—

Max

0

Min

—

Max

0

Min

—

Max

0

16 mA

8 mA

4 mA

14 mA

7 mA

6 mA

3 mA

4 mA

2 mA

3 mA

20 mA

—

ps

3.3-V LVTTL

39

58

84

104

0

3.3-V LVCMOS

39

58

84

104

195

309

909

122

196

624

686

1,188

1,279

1,911

39

129

188

624

694

158

251

738

850

1,376

1,517

2,206

4

2.5-V LVTTL / LVCMOS

1.8-V LVTTL / LVCMOS

1.5-V LVCMOS

1,046

1,694

1,867

2,715

5

1,184

1,280

1,883

58

1.2-V LVCMOS

3.3-V PCI

LVDS

122

129

158

195

RSDS

—

129

195

MAX V Device Handbook

May 2011 Altera Corporation

Chapter 3: DC and Switching Characteristics for MAX V Devices

3–25

Timing Model and Specifications

Table 3–35. External Timing Output Delay and t_ODAdders for Slow Slew Rate for MAX V Devices

5M40Z/ 5M80Z/ 5M160Z/

5M1270Z/ 5M2210Z

5M240Z/ 5M570Z

C5, I5

Max

I/O Standard

Unit

C4

C5, I5

Max

Min

—

Max

5,913

6,488

5,913

6,488

9,088

9,808

21,758

23,028

39,068

40,578

69,332

6,488

Min

—

Min

—

Max

6,612

7,313

6,612

7,313

10,021

10,881

21,134

22,399

34,499

36,281

55,796

339

Min

—

16 mA

8 mA

4 mA

14 mA

7 mA

6 mA

3 mA

4 mA

2 mA

3 mA

20 mA

6,043

6,645

6,043

6,645

9,222

9,962

21,782

23,032

39,032

40,542

70,257

6,645

6,293

6,994

6,293

6,994

9,702

10,562

20,815

22,080

34,180

35,962

55,477

418

ps

3.3-V LVTTL

3.3-V LVCMOS

2.5-V LVTTL / LVCMOS

1.8-V LVTTL / LVCMOS

1.5-V LVCMOS

1.2-V LVCMOS

3.3-V PCI

Table 3–36. IOE Programmable Delays for MAX V Devices

5M40Z/ 5M80Z/ 5M160Z/

5M1270Z/ 5M2210Z

C4 C5, I5

5M240Z/ 5M570Z

C5, I5

Max

Parameter

Unit

C4

Min

Max

Min

Max

Min

Max

Input Delay from Pin to Internal

Cells = 1

—

1,858

—

2,214

616

—

1,592

—

1,960

ps

Input Delay from Pin to Internal

Cells = 0

—

569

—

115

—

142

May 2011 Altera Corporation

MAX V Device Handbook

3–26

Chapter 3: DC and Switching Characteristics for MAX V Devices

Timing Model and Specifications

Maximum Input and Output Clock Rates

Table 3–37 and Table 3–38 list the maximum input and output clock rates for standard

I/O pins in MAX V devices.

Table 3–37. Maximum Input Clock Rate for I/Os for MAX V Devices

5M40Z/ 5M80Z/ 5M160Z/

5M240Z/ 5M570Z/5M1270Z/

I/O Standard

Unit

5M2210Z

C4, C5, I5

304

Without Schmitt Trigger

MHz

3.3-V LVTTL

With Schmitt Trigger

304

Without Schmitt Trigger

With Schmitt Trigger

304

3.3-V LVCMOS

2.5-V LVTTL

304

Without Schmitt Trigger

With Schmitt Trigger

304

Without Schmitt Trigger

With Schmitt Trigger

304

2.5-V LVCMOS

304

1.8-V LVTTL

1.8-V LVCMOS

1.5-V LVCMOS

1.2-V LVCMOS

3.3-V PCI

Without Schmitt Trigger

200

150

120

304

Table 3–38. Maximum Output Clock Rate for I/Os for MAX V Devices

5M40Z/ 5M80Z/ 5M160Z/

5M240Z/ 5M570Z/5M1270Z/

5M2210Z

I/O Standard

Unit

C4, C5, I5

304

3.3-V LVTTL

3.3-V LVCMOS

2.5-V LVTTL

2.5-V LVCMOS

1.8-V LVTTL

1.8-V LVCMOS

1.5-V LVCMOS

1.2-V LVCMOS

3.3-V PCI

MHz

304

200

150

120

304

LVDS

304

RSDS

200

MAX V Device Handbook

May 2011 Altera Corporation

Chapter 3: DC and Switching Characteristics for MAX V Devices

3–27

Timing Model and Specifications

LVDS and RSDS Output Timing Specifications

Table 3–39 lists the emulated LVDS output timing specifications for MAX V devices.

Table 3–39. Emulated LVDS Output Timing Specifications for MAX V Devices

5M40Z/ 5M80Z/ 5M160Z/

5M240Z/ 5M570Z/5M1270Z/

5M2210Z

Parameter

Mode

Unit

C4, C5, I5

Min

Max

304

55

10

9

8

7

6

5

4

3

2

1

—

45

—

Mbps

%

Data rate (1), (2)

t_DUTY

Total jitter (3)

t_RISE

0.2

UI

450

ps

t_FALL

ps

Notes to Table 3–39:

(1) The performance of the LVDS_E_3R transmitter system is limited by the lower of the two—the maximum data rate supported by LVDS_E_3R

I/O buffer or 2x (F_MAXof the ALTLVDS_TX instance). The actual performance of your LVDS_E_3R transmitter system must be attained through

the Quartus II timing analysis of the complete design.

(2) For the input clock pin to achieve 304 Mbps, use I/O standard with V_CCIOof 2.5 V and above.

(3) This specification is based on external clean clock source.

May 2011 Altera Corporation

MAX V Device Handbook

3–28

Chapter 3: DC and Switching Characteristics for MAX V Devices

Timing Model and Specifications

Table 3–40 lists the emulated RSDS output timing specifications for MAX V devices.

Table 3–40. Emulated RSDS Output Timing Specifications for MAX V Devices

5M40Z/ 5M80Z/ 5M160Z/

5M240Z/ 5M570Z/5M1270Z/

5M2210Z

Parameter

Mode

Unit

C4, C5, I5

Min

Max

200

55

10

9

8

7

6

5

4

3

2

1

—

45

—

Mbps

%

Data rate (1)

t_DUTY

Total jitter (2)

t_RISE

0.2

UI

450

ps

t_FALL

ps

Notes to Table 3–40:

(1) For the input clock pin to achieve 200 Mbps, use I/O standard with V_CCIOof 1.8 V and above.

(2) This specification is based on external clean clock source.

MAX V Device Handbook

May 2011 Altera Corporation

Chapter 3: DC and Switching Characteristics for MAX V Devices

3–29

Timing Model and Specifications

JTAG Timing Specifications

Figure 3–6 shows the timing waveform for the JTAG signals for the MAX V device

family.

Figure 3–6. JTAG Timing Waveform for MAX V Devices

TMS

TDI

t

JCP

t

JPH

JPSU

t

JCL

JCH

TCK

TDO

t

JPXZ

JPZX

JPCO

t

JSSU

JSH

Signal

to be

Captured

t

JSXZ

JSZX

JSCO

Signal

to be

Driven

Table 3–41 lists the JTAG timing parameters and values for the MAX V device family.

Table 3–41. JTAG Timing Parameters for MAX V Devices (Part 1 of 2)

Symbol

Parameter

TCKclock period for V_CCIO1= 3.3 V

TCKclock period for V_CCIO1= 2.5 V

TCKclock period for V_CCIO1= 1.8 V

TCKclock period for V_CCIO1= 1.5 V

TCKclock high time

Min

55.5

62.5

100

143

20

Max

—

15

—

25

Unit

ns

t_JCP(1)

t_JCH

t_JCL

TCK clock low time

20

t_JPSU

t_JPH

JTAG port setup time (2)

8

JTAG port hold time

10

t_JPCO

t_JPZX

t_JPXZ

t_JSSU

t_JSH

JTAG port clock to output (2)

JTAG port high impedance to valid output (2)

JTAG port valid output to high impedance (2)

Capture register setup time

—

8

Capture register hold time

10

t_JSCO

t_JSZX

Update register clock to output

Update register high impedance to valid output

—

May 2011 Altera Corporation

MAX V Device Handbook

3–30

Chapter 3: DC and Switching Characteristics for MAX V Devices

Document Revision History

Table 3–41. JTAG Timing Parameters for MAX V Devices (Part 2 of 2)

Symbol

Parameter

Min

Max

Unit

t_JSXZ

Notes to Table 3–41:

(1) Minimum clock period specified for 10 pF load on the TDOpin. Larger loads on TDOdegrades the maximum TCKfrequency.

Update register valid output to high impedance

—

25

ns

(2) This specification is shown for 3.3-V LVTTL/LVCMOS and 2.5-V LVTTL/LVCMOS operation of the JTAG pins. For 1.8-V LVTTL/LVCMOS and

1.5-V LVCMOS operation, the t_JPSUminimum is 6 ns and t_JPCO, t_JPZX, and t_JPXZare maximum values at 35 ns.

Document Revision History

Table 3–42 lists the revision history for this chapter.

Table 3–42. Document Revision History

Date

May 2011

Version

1.2

Changes

Updated Table 3–2, Table 3–15, Table 3–16, and Table 3–33.

Updated Table 3–37, Table 3–38, Table 3–39, and Table 3–40.

Initial release.

January 2011

1.1

December 2010

1.0

MAX V Device Handbook

May 2011 Altera Corporation


型号：	5M160ZM68A5N
厂家：	INTEL
描述：	Flash PLD, 14ns, 128-Cell, CMOS, PBGA68
文件：	总72页 (文件大小：1170K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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