541_技术文档

®

Intel Pentium 4 Processors

570/571, 560/561, 550/551,

∆

540/541, 530/531 and 520/521

Supporting Hyper-Threading

Technology

1

Datasheet

On 90 nm Process in 775-land LGA Package and

supporting Intel^®Extended Memory 64 Technology^Φ

May 2005

Document Number: 302351-004

Contents

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY

ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN

INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS

ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES

RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER

INTELLECTUAL PROPERTY RIGHT. INTEL PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE SUSTAINING

APPLICATIONS.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

®

The Intel Pentium 4 processor in the 775-land package on 90 nm process may contain design defects or errors known as errata which may cause

the product to deviate from published specifications. Current characterized errata are available on request.

∆

Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across

different processor families.

1

®

Hyper-Threading Technology requires a computer system with an Intel Pentium 4 processor supporting Hyper-Threading Technology and an HT

Technology enabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. See http:/

/www.intel.com/info/hyperthreading/ for more information including details on which processors support HT Technology.

®

ΦIntel Extended Memory 64 Technology (Intel EM64T) requires a computer system with a processor, chipset, BIOS, operating system, device

drivers and applications enabled for Intel EM64T. Processor will not operate (including 32-bit operation) without an Intel EM64T-enabled BIOS.

Performance will vary depending on your hardware and software configurations. See http://www.intel.com/info/em64t for more information including

details on which processors support EM64T or consult with your system vendor for more information.

Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system.

Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Intel, Pentium, Itanium, Intel Xeon, Intel NetBurst and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in

the United States and other countries.

*Other names and brands may be claimed as the property of others.

2

Datasheet

Contents

1

Introduction....................................................................................................................................11

1.1

Terminology........................................................................................................................12

1.1.1 Processor Packaging Terminology ........................................................................12

References .........................................................................................................................13

1.2

2

Electrical Specifications.................................................................................................................15

2.1

2.2

2.3

FSB and GTLREF...............................................................................................................15

Power and Ground Lands...................................................................................................15

Decoupling Guidelines........................................................................................................15

2.3.1 VCC Decoupling ....................................................................................................16

2.3.2 FSB GTL+ Decoupling...........................................................................................16

2.3.3 FSB Clock (BCLK[1:0]) and Processor Clocking ...................................................16

Voltage Identification ..........................................................................................................17

2.4.1 Phase Lock Loop (PLL) Power and Filter ..............................................................19

Reserved, Unused, FC and TESTHI Signals......................................................................20

FSB Signal Groups.............................................................................................................21

GTL+ Asynchronous Signals ..............................................................................................22

Test Access Port (TAP) Connection...................................................................................23

FSB Frequency Select Signals (BSEL[2:0]) .......................................................................23

2.4

2.5

2.6

2.7

2.8

2.9

2.10 Absolute Maximum and Minimum Ratings .........................................................................24

2.11 Processor DC Specifications ..............................................................................................24

2.12 VCC Overshoot Specification .............................................................................................33

2.12.1 Die Voltage Validation ...........................................................................................33

2.13 GTL+ FSB Specifications....................................................................................................34

3

Package Mechanical Specifications ..............................................................................................35

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

Package Mechanical Drawing ............................................................................................35

Processor Component Keep-Out Zones.............................................................................39

Package Loading Specifications.........................................................................................39

Package Handling Guidelines.............................................................................................39

Package Insertion Specifications........................................................................................40

Processor Mass Specification.............................................................................................40

Processor Materials............................................................................................................40

Processor Markings............................................................................................................40

Processor Land Coordinates ..............................................................................................41

4

5

Land Listing and Signal Descriptions ............................................................................................43

4.1

4.2

Processor Land Assignments.............................................................................................43

Alphabetical Signals Reference..........................................................................................66

Thermal Specifications and Design Considerations......................................................................75

5.1

5.2

Processor Thermal Specifications ......................................................................................75

5.1.1 Thermal Specifications ..........................................................................................75

5.1.2 Thermal Metrology.................................................................................................79

Processor Thermal Features ..............................................................................................79

5.2.1 Thermal Monitor.....................................................................................................79

5.2.2 Thermal Monitor 2..................................................................................................80

Datasheet

3

Contents

5.2.3 On-Demand Mode .................................................................................................81

5.2.4 PROCHOT# Signal................................................................................................82

5.2.5 THERMTRIP# Signal.............................................................................................82

5.2.6

T

and Fan Speed Reduction....................................................................82

CONTROL

5.2.7 Thermal Diode .......................................................................................................83

6

7

Features ........................................................................................................................................85

6.1

6.2

Power-On Configuration Options........................................................................................85

Clock Control and Low Power States .................................................................................85

6.2.1 Normal State..........................................................................................................86

6.2.2 HALT and Enhanced HALT Powerdown States ....................................................86

6.2.3 Stop-Grant State....................................................................................................87

6.2.4 Enhanced HALT Snoop or HALT Snoop State, Grant Snoop State......................88

Boxed Processor Specifications....................................................................................................89

7.1

Mechanical Specifications ..................................................................................................90

7.1.1 Boxed Processor Cooling Solution Dimensions ....................................................90

7.1.2 Boxed Processor Fan Heatsink Weight.................................................................91

7.1.3 Boxed Processor Retention Mechanism and Heatsink

Attach Clip Assembly.............................................................................................91

Electrical Requirements......................................................................................................91

7.2.1 Fan Heatsink Power Supply ..................................................................................91

Thermal Specifications .......................................................................................................93

7.3.1 Boxed Processor Cooling Requirements...............................................................93

7.3.2 Variable Speed Fan...............................................................................................95

7.2

7.3

4

Datasheet

Contents

Figures

2-1 Phase Lock Loop (PLL) Filter Requirements..............................................................................19

2-2 VCC Static and Transient Tolerance for 775_VR_CONFIG_04A...............................................28

2-3 VCC Static and Transient Tolerance for 775_VR_CONFIG_04B...............................................30

2-4 VCC Overshoot Example Waveform ..........................................................................................33

3-1 Processor Package Assembly Sketch........................................................................................35

3-2 Processor Package Drawing 1 ...................................................................................................36

3-3 Processor Package Drawing 2 ...................................................................................................37

3-4 Processor Package Drawing 3 ...................................................................................................38

3-5 Processor Top-Side Marking Example .......................................................................................40

®

3-6 Processor Top-Side Marking Example for Processors Supporting Intel EM64T......................41

3-7 Processor Land Coordinates (Top View)....................................................................................42

4-1 Landout Diagram (Top View – Left Side)....................................................................................44

4-2 Landout Diagram (Top View – Right Side) .................................................................................45

5-1 Thermal Profile for Processors with PRB = 1 .............................................................................77

5-2 Thermal Profile for Processors with PRB = 0 .............................................................................78

5-3 Case Temperature (TC) Measurement Location........................................................................79

5-4 Thermal Monitor 2 Frequency and Voltage Ordering .................................................................81

6-1 Processor Low Power State Machine.........................................................................................87

7-1 Mechanical Representation of the Boxed Processor..................................................................89

7-2 Space Requirements for the Boxed Processor (Side View) .......................................................90

7-3 Space Requirements for the Boxed Processor (Top View) ........................................................90

7-4 Space Requirements for the Boxed Processor (Overall View)...................................................91

7-5 Boxed Processor Fan Heatsink Power Cable Connector Description........................................92

7-6 Baseboard Power Header Placement Relative to Processor Socket .........................................93

7-7 Boxed Processor Fan Heatsink Airspace Keepout Requirements (Top View)...........................94

7-8 Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side View)..........................94

7-9 Boxed Processor Fan Heatsink Set Points.................................................................................95

Datasheet

5

Contents

Tables

1-1 References .................................................................................................................................13

2-1 Core Frequency to FSB Multiplier Configuration........................................................................16

2-2 Voltage Identification Definition ..................................................................................................18

2-3 FSB Signal Groups.....................................................................................................................21

2-4 Signal Characteristics.................................................................................................................22

2-5 Signal Reference Voltages.........................................................................................................22

2-6 BSEL[2:0] Frequency Table for BCLK[1:0].................................................................................23

2-7 Processor DC Absolute Maximum Ratings ................................................................................24

2-8 Voltage and Current Specifications ............................................................................................25

2-9 VCC Static and Transient Tolerance for 775_VR_CONFIG_04A Processors ...........................27

2-10VCC Static and Transient Tolerance for 775_VR_CONFIG_04B Processors ...........................29

2-11 GTL+ Asynchronous Signal Group DC Specifications ..............................................................31

2-12GTL+ Signal Group DC Specifications .......................................................................................31

2-13PWRGOOD and TAP Signal Group DC Specifications..............................................................32

2-14VTTPWRGD DC Specifications..................................................................................................32

2-15BSEL [2:0] and VID[5:0] DC Specifications................................................................................32

2-16BOOTSELECT DC Specifications..............................................................................................32

2-17VCC Overshoot Specifications ...................................................................................................33

2-18GTL+ Bus Voltage Definitions ....................................................................................................34

3-1 Processor Loading Specifications ..............................................................................................39

3-2 Package Handling Guidelines ....................................................................................................39

3-3 Processor Materials....................................................................................................................40

4-1 Alphabetical Land Assignments .................................................................................................46

4-2 Numerical Land Assignment.......................................................................................................56

4-3 Signal Description.......................................................................................................................66

5-1 Processor Thermal Specifications..............................................................................................76

5-2 Thermal Profile for Processors with PRB = 1 .............................................................................77

5-3 Thermal Profile for Processors with PRB = 0 .............................................................................78

5-4 Thermal Diode Parameters ........................................................................................................83

5-5 Thermal Diode Interface.............................................................................................................83

6-1 Power-On Configuration Option Signals.....................................................................................85

7-1 Fan Heatsink Power and Signal Specifications..........................................................................92

7-2 Fan Heatsink Power and Signal Specifications..........................................................................96

§

6

Datasheet

Contents

Revision History

Revision No.

Description

Date of Release

-001

-002

-003

•

Initial release

June 2004

•

Added specifications for processor number 550 with PRB = 0

Added support for Execute Disable Bit capability

Added Icc Enhanced Auto Halt specifications

Added support for Thermal Monitor 2

September 2004

November 2004

•

Added specifications for processor number 570 with PRB = 1

Added specifications for processor numbers 571, 561, 551, 541,

531, and 521.

•

Modified Table 2-3, “FSB Signal Groups“.

Added Note 5 to Table 2-18.

-004

May 2005

Updated Figure 3-5 Top SIde Marking Example and added

Figure 3-6.

•

Minor edits throughout for clarity.

§

Datasheet

7

Contents

8

Datasheet

Contents

®

Intel Pentium 4 Processors 570/571,

560/561, 550/551, 540/541, 530/531, and

520/521

• Available at 3.80 GHz, 3.60 GHz, 3.40 GHz,

3.20 GHz, 3 GHz, and 2.80 GHz

• 16-KB Level 1 data cache

• 1-MB Advanced Transfer Cache (on-die, full-

speed Level 2 (L2) cache) with 8-way associativity

and Error Correcting Code (ECC)

1

• Supports Hyper-Threading Technology

(HT Technology) for all frequencies with

800 MHz front side bus (FSB)

• 144 Streaming SIMD Extensions 2 (SSE2)

instructions

®

• Intel Pentium 4 processors 571, 561, 551, 541,

®

531, and 521 support Intel Extended Memory 64

• 13 Streaming SIMD Extensions 3 (SSE3)

instructions

Technology (EM64T)^Φ

• Supports Execute Disable Bit capability

• Enhanced floating point and multimedia unit for

enhanced video, audio, encryption, and 3D

performance

• Binary compatible with applications running on

previous members of the Intel microprocessor line

®

• Intel NetBurst microarchitecture

• Power Management capabilities

• System Management mode

• Multiple low-power states

• FSB frequency at 800 MHz

• Hyper-Pipelined Technology

• Advance Dynamic Execution

• Very deep out-of-order execution

• Enhanced branch prediction

• 8-way cache associativity provides improved

cache hit rate on load/store operations

• 775-land Package

• Optimized for 32-bit applications running on

advanced 32-bit operating systems

®

1

The Intel Pentium 4 processor family supporting Hyper-Threading Technology (HT Technology) delivers

Intel's advanced, powerful processors for desktop PCs and entry-level workstations that are based on the Intel

®

NetBurst microarchitecture. The Pentium 4 processor is designed to deliver performance across applications and

usages where end-users can truly appreciate and experience the performance. These applications include Internet

audio and streaming video, image processing, video content creation, speech, 3D, CAD, games, multimedia, and

®

multitasking user environments. Intel Extended Memory 64 Technology enables the Intel Pentium processor to

execute operating systems and applications written to take advange of the Intel EM64T^Φ.

§

Datasheet

9

Contents

10

Datasheet

Introduction

1 Introduction

®

The Intel Pentium 4 processor on 90 nm process in the 775-land package is a follow on to the

®

Pentium 4 processor in the 478-pin package with enhancements to the Intel NetBurst

microarchitecture. The Pentium 4 processor on 90 nm process in the 775-land package uses Flip-

Chip Land Grid Array (FC-LGA4) package technology, and plugs into a 775LGA socket. The

Pentium 4 processor in the 775-land package, like its predecessor, the Pentium 4 processor in the

478-pin package, is based on the same Intel 32-bit microarchitecture and maintains the tradition of

compatibility with IA-32 software.

Note: In this document the Pentium 4 processor on 90 nm process in the 775-land package is also referred

to as the processor.

The Pentium 4 processor on 90 nm process in the 775-land package supports Hyper-Threading

1

Technology . Hyper-Threading Technology allows a single, physical processor to function as two

logical processors. While some execution resources (such as caches, execution units, and buses)

are shared, each logical processor has its own architecture state with its own set of general-purpose

registers, control registers to provide increased system responsiveness in multitasking

environments, and headroom for next generation multithreaded applications. Intel recommends

enabling Hyper-Threading Technology with Microsoft Windows* XP Professional or

Windows* XP Home, and disabling Hyper-Threading Technology via the BIOS for all previous

versions of Windows operating systems. For more information on Hyper-Threading Technology,

see http://www.intel.com/info/hyperthreading. Refer to Section 6.1, for Hyper-Threading

Technology configuration details.

®

The Intel Pentium 4 processor 571, 561, 541, 531, and 521 support Intel Extended Memory 64

Φ

Technology (EM64T) as an enhancement to Intel’s IA-32 architecture. This enhancement enables

the processor to execute operating systems and applications written to take advantage of Intel

EM64T. With appropriate 64 bit supporting hardware and software, platforms based on an Intel

®

processor supporting Intel EM64T can enable use of extended virtual and physical memory.

Further details on the 64-bit extension architecture and programming model is provided in the

®

Intel Extended Memory 64 Technology Software Developer Guide at: http://developer.intel.com/

technology/64bitextensions/.

In addition to supporting all the existing Streaming SIMD Extensions 2 (SSE2), there are 13 new

instructions that further extend the capabilities of Intel processor technology. These new

instructions are called Streaming SIMD Extensions 3 (SSE3). These new instructions enhance the

performance of optimized applications for the digital home such as video, image processing, and

media compression technology. 3D graphics and other entertainment applications such as gaming

will have the opportunity to take advantage of these new instructions as platforms with the Pentium

4 processor in the 775-land package and SSE3 become available in the market place.

The processor’s Intel NetBurst microarchitecture FSB uses a split-transaction, deferred reply

protocol like the Pentium 4 processor. The Intel NetBurst microarchitecture FSB uses Source-

Synchronous Transfer (SST) of address and data to improve performance by transferring data four

times per bus clock (4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address

bus can deliver addresses two times per bus clock and is referred to as a "double-clocked" or 2X

address bus. Working together, the 4X data bus and 2X address bus provide a data bus bandwidth

of up to 6.4 GB/s.

Datasheet

11

Introduction

The Pentium 4 processor on 90 nm process in the LGA775-land package will also include the

®

Execute Disable Bit capability previously available in Intel Itanium processors. This feature

combined with a support operating system allows memory to be marked as executable or non-

executable. If code attempts to run in non-executable memory the processor raises an error to the

operating system. This feature can prevent some classes of viruses or worms that exploit buffer

®

overrun vulnerabilities and can thus help improve the overall security of the system. See the Intel

Architecture Software Developer's Manual for more detailed information.

Intel will enable support components for the processor including heatsink, heatsink retention

mechanism, and socket. Manufacturability is a high priority; hence, mechanical assembly may be

completed from the top of the baseboard and should not require any special tooling.

The processor includes an address bus powerdown capability that removes power from the address

and data pins when the FSB is not in use. This feature is always enabled on the processor.

1.1

Terminology

A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the active

state when driven to a low level. For example, when RESET# is low, a reset has been requested.

Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where

the name does not imply an active state but describes part of a binary sequence (such as address or

data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a

hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).

“FSB” refers to the interface between the processor and system core logic (a.k.a. the chipset

components). The FSB is a multiprocessing interface to processors, memory, and I/O.

1.1.1

Processor Packaging Terminology

Commonly used terms are explained here for clarification:

• Pentium 4 processor on 90 nm process in the 775-land package — Processor in the FC-

LGA4 package with a 1-MB L2 cache.

• Processor — For this document, the term processor is the generic form of the Pentium 4

processor in the 775-land package.

• Keep-out zone — The area on or near the processor that system design can not use.

• Intel 925X/915G/915P Express chipsets — Chipsets that supports DDR and DDR2 memory

technology for the Pentium 4 processor in the 775-land package.

• Processor core — Processor core die with integrated L2 cache.

• FC-LGA4 package — The Pentium 4 processor in the 775-land package is available in a Flip-

Chip Land Grid Array 4 package, consisting of a processor core mounted on a substrate with

an integrated heat spreader (IHS).

• LGA775 socket — The Pentium 4 processor in the 775-land package mates with the system

board through a surface mount, 775-land, LGA socket.

• Integrated heat spreader (IHS) —A component of the processor package used to enhance

the thermal performance of the package. Component thermal solutions interface with the

processor at the IHS surface.

12

Datasheet

Introduction

• Retention mechanism (RM)—Since the LGA775 socket does not include any mechanical

features for heatsink attach, a retention mechanism is required. Component thermal solutions

should attach to the processor via a retention mechanism that is independent of the socket.

• Storage conditions—Refers to a non-operational state. The processor may be installed in a

platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air.

Under these conditions, processor lands should not be connected to any supply voltages, have

any I/Os biased, or receive any clocks. Upon exposure to “free air” (i.e., unsealed packaging or

a device removed from packaging material) the processor must be handled in accordance with

moisture sensitivity labeling (MSL) as indicated on the packaging material.

• Functional operation—Refers to normal operating conditions in which all processor

specifications, including DC, AC, system bus, signal quality, mechanical and thermal, are

satisfied.

1.2

References

Material and concepts available in the following documents may be beneficial when reading this

document.

Table 1-1. References

Document Numbers/

Location

Document

http://developer.intel.com/

design/Pentium4/

Intel^®Pentium^®4 Processor on 90 nm Process Specification Update

specupdt/302352.htm

http://developer.intel.com/

design/Pentium4/guides/

302553.htm

Intel^®Pentium^®4 Processor on 90 nm Process in the 775-Land Package

Thermal Design Guidelines

http://developer.intel.com/

Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket design/Pentium4/guides/

302356.htm

Intel^®Architecture Software Developer's Manual

IA-32 Intel^®Architecture Software Developer's Manual Volume 1: Basic

Architecture

IA-32 Intel^®Architecture Software Developer's Manual Volume 2A: Instruction http://developer.intel.com/

Set Reference Manual A–M

design/pentium4/

manuals/index_new.htm

IA-32 Intel^®Architecture Software Developer's Manual Volume 2B: Instruction

Set Reference Manual, N–Z

IA-32 Intel^®Architecture Software Developer's Manual Volume 3: System

Programming Guide

http://developer.intel.com/

design/pentium4/

manuals/index_new.htm

IA-32 Intel^®Architecture and Intel® Extended Memory 64 Software

Developer's Manual Documentation Changes

§

Datasheet

13

Introduction

14

Datasheet

Electrical Specifications

2 Electrical Specifications

This chapter describes the electrical characteristics of the processor interfaces and signals. DC

electrical characteristics are provided.

2.1

FSB and GTLREF

Most processor FSB signals use Gunning Transceiver Logic (GTL+) signaling technology.

Platforms implement a termination voltage level for GTL+ signals defined as V . V must be

TT TT

provided via a separate voltage source and not be connected to V . This configuration allows for

CC

improved noise tolerance as processor frequency increases. Because of the speed improvements to

the data and address bus, signal integrity and platform design methods have become more critical

than with previous processor families.

The GTL+ inputs require a reference voltage (GTLREF) that is used by the receivers to determine

if a signal is a logical 0 or a logical 1. GTLREF must be generated on the system board (see

Table 2-18 for GTLREF specifications). Termination resistors are provided on the processor silicon

and are terminated to V . Intel chipsets will also provide on-die termination, thus eliminating the

TT

need to terminate the bus on the system board for most GTL+ signals.

Some GTL+ signals do not include on-die termination and must be terminated on the system board.

See Table 2-4 for details regarding these signals.

The GTL+ bus depends on incident wave switching. Therefore, timing calculations for GTL+

signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the

FSB, including trace lengths, is highly recommended when designing a system.

2.2

2.3

Power and Ground Lands

For clean on-chip power distribution, the Pentium 4 processor in the 775-land package has

226 V (power), 24 V and 273 V (ground) lands. All power lands must be connected to V ,

CC

TT

SS

CC

all V lands must be connected to V , while all V lands must be connected to a system ground

TT

SS

plane. The processor V lands must be supplied the voltage determined by the Voltage

CC

IDentification (VID) signals.

Decoupling Guidelines

Due to its large number of transistors and high internal clock speeds, the processor is capable of

generating large current swings between low and full power states. This may cause voltages on

power planes to sag below their minimum values if bulk decoupling is not adequate. Care must be

taken in the board design to ensure that the voltage provided to the processor remains within the

specifications listed in Table 2-8. Failure to do so can result in timing violations or reduced lifetime

of the component. For further information and design guidelines, refer to the Voltage Regulator

Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket.

Datasheet

15

Electrical Specifications

2.3.1

V_CCDecoupling

Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR)

and keep a low interconnect resistance from the regulator to the socket. Bulk decoupling for the

large current swings when the part is powering on, or entering/exiting low power states, must be

provided by the voltage regulator solution (VR). For more details on this topic, refer to the Voltage

Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket.

2.3.2

2.3.3

FSB GTL+ Decoupling

The Pentium 4 processor in the 775-land package integrates signal termination on the die as well as

incorporating high frequency decoupling capacitance on the processor package. Decoupling must

also be provided by the system baseboard for proper GTL+ bus operation.

FSB Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor.

As in previous generation processors, the Pentium 4 processor in the 775-land package core

frequency is a multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set

at its default ratio during manufacturing. No user intervention is necessary, and the processor will

automatically run at the speed indicated on the package.

The Pentium 4 processor in the 775-land package uses a differential clocking implementation. For

more information on the Pentium 4 processor in the 775-land package clocking, refer to the

CK410/CK410M Clock Synthesizer/Driver Specification.

Table 2-1. Core Frequency to FSB Multiplier Configuration

Multiplication of System Core

Frequency to FSB Frequency

Core Frequency (200 MHz

BCLK/800 MHz FSB)

Notes^{1, 2}

1/14

2.80 GHz

3 GHz

-

1/15

1/16

3.20 GHz

3.40 GHz

3.60 GHz

3.80 GHz

1/17

1/18

1/19

NOTES:

1.

2.

Individual processors operate only at or below the rated frequency.

Listed frequencies are not necessarily committed production frequencies.

16

Datasheet

Electrical Specifications

2.4

Voltage Identification

The VID specification for the Pentium 4 processor in the 775-land package is supported by the

Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket. The voltage set

by the VID signals is the reference VR output voltage to be delivered to the processor V pins. A

CC

minimum voltage is provided in Table 2-8 and changes with frequency. This allows processors

running at a higher frequency to have a relaxed minimum voltage specification. The specifications

have been set such that one voltage regulator can work with all supported frequencies.

Individual processor VID values may be calibrated during manufacturing such that two devices at

the same speed may have different VID settings.

The Pentium 4 processor in the 775-land package uses six voltage identification signals, VID[5:0],

to support automatic selection of power supply voltages. Table 2-2 specifies the voltage level

corresponding to the state of VID[5:0]. A ‘1’ in this table refers to a high voltage level and a ‘0’

refers to low voltage level. If the processor socket is empty (VID[5:0] = x11111), or the voltage

regulation circuit cannot supply the voltage that is requested, it must disable itself. See the Voltage

Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket for more details.

Power source characteristics must be guaranteed to be stable when the supply to the voltage

regulator is stable.

The LL_ID[1:0] lands are used by the platform to configure the proper loadline slope for the

processor. LL_ID[1:0] = 00 for the Pentium 4 processor in the 775-land package.

The VTT_SEL land is used by the platform to configure the proper V voltage level for the

TT

processor. VTT_SEL = 1 for the Pentium 4 processor in the 775-land package.

The GTLREF_SEL signal is used by the platform to select the appropriate chipset GTLREF level.

GTLREF_SEL = 0 for the Pentium 4 processor in the 775-land package.

LL_ID[1:0] and VTT_SEL are signals that are implemented on the processor package. That is,

they are either connected directly to V or are open lands.

SS

Datasheet

17

Electrical Specifications

Table 2-2.

Voltage Identification Definition

VID5

VID4

VID3

VID2

VID1

VID0

VID

VID5

VID4

VID3

VID2

VID1

VID0

VID

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0.8375

0.8500

0.8625

0.8750

0.8875

0.9000

0.9125

0.9250

0.9375

0.9500

0.9625

0.9750

0.9875

1.0000

1.0125

1.0250

1.0375

1.0500

1.0625

1.0750

1.0875

VR output off

1.1000

1.1125

1.1250

1.1375

1.1500

1.1625

1.1750

1.1875

1.2000

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1.2125

1.2250

1.2375

1.2500

1.2625

1.2750

1.2875

1.3000

1.3125

1.3250

1.3375

1.3500

1.3625

1.3750

1.3875

1.4000

1.4125

1.4250

1.4375

1.4500

1.4625

1.4750

1.4875

1.5000

1.5125

1.5250

1.5375

1.5500

1.5625

1.5750

1.5875

1.6000

18

Datasheet

Electrical Specifications

2.4.1

Phase Lock Loop (PLL) Power and Filter

V

and V

are power sources required by the PLL clock generators for the Pentium 4

CCIOPLL

CCA

processor in the 775-land package. Since these PLLs are analog, they require low noise power

supplies for minimum jitter. Jitter is detrimental to the system: it degrades external I/O timings as

well as internal core timings (i.e., maximum frequency). To prevent this degradation, these supplies

must be low pass filtered from V

.

TT

The AC low-pass requirements, with input at V are as follows:

TT

• < 0.2 dB gain in pass band

• < 0.5 dB attenuation in pass band < 1 Hz

• > 34 dB attenuation from 1 MHz to 66 MHz

• > 28 dB attenuation from 66 MHz to core frequency

The filter requirements are illustrated in Figure 2-1.

.

Figure 2-1. Phase Lock Loop (PLL) Filter Requirements

0.2 dB

0 dB

–0.5 dB

Forbidden

Zone

Forbidden

Zone

–28 dB

–34 dB

DC

1 Hz

Passband

fpeak

1 MHz

66 MHz

fcore

High

Frequency

Band

Filter_Spec

NOTES:

1. Diagram not to scale.

2. No specification exists for frequencies beyond fcore (core frequency).

3. fpeak, if existent, should be less than 0.05 MHz.

Datasheet

19

Electrical Specifications

2.5

Reserved, Unused, FC and TESTHI Signals

All RESERVED signals must remain unconnected. Connection of these signals to V , V , V

TT,

CC

SS

or to any other signal (including each other) can result in component malfunction or

incompatibility with future processors. See Chapter 4 for a land listing of the processor and the

location of all RESERVED signals.

For reliable operation, always connect unused inputs or bidirectional signals to an appropriate

signal level. In a system level design, on-die termination has been included on the Pentium 4

processor in the 775-land package to allow signals to be terminated within the processor silicon.

Most unused GTL+ inputs should be left as no connects, as GTL+ termination is provided on the

processor silicon. However, see Table 2-4 for details on GTL+ signals that do not include on-die

termination. Unused active high inputs should be connected through a resistor to ground (V ).

SS

Unused outputs can be left unconnected, however this may interfere with some test access port

(TAP) functions, complicate debug probing, and prevent boundary scan testing. A resistor must be

used when tying bidirectional signals to power or ground. When tying any signal to power or

ground, a resistor will also allow for system testability. For unused GTL+ input or I/O signals, use

pull-up resistors of the same value as the on-die termination resistors (R_TT). Refer to Table 2-18 for

more details.

TAP, GTL+ Asynchronous inputs, and GTL+ Asynchronous outputs do not include on-die

termination. Inputs and used outputs must be terminated on the system board. Unused outputs may

be terminated on the system board or left unconnected. Note that leaving unused outputs

unterminated may interfere with some TAP functions, complicate debug probing, and prevent

boundary scan testing.

FCx signals are signals that are available for compatibility with other processors.

The TESTHI signals must be tied to the processor V using a matched resistor, where a matched

TT

resistor has a resistance value within ±20% of the impedance of the board transmission line traces.

For example, if the trace impedance is 60 Ω, then a value between 48 Ω and 72 Ω is required.

The TESTHI signals may use individual pull-up resistors or be grouped together as detailed below.

A matched resistor must be used for each group:

• TESTHI[1:0]

• TESTHI[7:2]

• TESTHI8 – cannot be grouped with other TESTHI signals

• TESTHI9 – cannot be grouped with other TESTHI signals

• TESTHI10 – cannot be grouped with other TESTHI signals

• TESTHI11 – cannot be grouped with other TESTHI signals

• TESTHI12 – cannot be grouped with other TESTHI signals

• TESTHI13 – cannot be grouped with other TESTHI signals

20

Datasheet

Electrical Specifications

2.6

FSB Signal Groups

The FSB signals have been combined into groups by buffer type. GTL+ input signals have

differential input buffers, which use GTLREF as a reference level. In this document, the term

"GTL+ Input" refers to the GTL+ input group as well as the GTL+ I/O group when receiving.

Similarly, "GTL+ Output" refers to the GTL+ output group as well as the GTL+ I/O group when

driving.

With the implementation of a source synchronous data bus comes the need to specify two sets of

timing parameters. One set is for common clock signals which are dependent upon the rising edge

of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals

which are relative to their respective strobe lines (data and address) as well as the rising edge of

BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at

any time during the clock cycle. Table 2-3 identifies which signals are common clock, source

synchronous, and asynchronous.

Table 2-3. FSB Signal Groups

Signal Group

Type

Signals¹

Synchronous to

BCLK[1:0]

GTL+ Common Clock Input

GTL+ Common Clock I/O

BPRI#, DEFER#, RS[2:0]#, RSP#, TRDY#

Synchronous to

BCLK[1:0]

AP[1:0]#, ADS#, BINIT#, BNR#, BPM[5:0]#, BR0#, DBSY#,

DP[3:0]#, DRDY#, HIT#, HITM#, LOCK#, MCERR#

Signals

Associated Strobe

REQ[4:0]#, A[16:3]#³

A[35:17]#³

ADSTB0#

Synchronous to assoc.

strobe

ADSTB1#

GTL+ Source Synchronous I/O

D[15:0]#, DBI0#

D[31:16]#, DBI1#

D[47:32]#, DBI2#

D[63:48]#, DBI3#

DSTBP0#, DSTBN0#

DSTBP1#, DSTBN1#

DSTBP2#, DSTBN2#

DSTBP3#, DSTBN3#

Synchronous to

BCLK[1:0]

GTL+ Strobes

ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#

A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#,

STPCLK#, RESET#

GTL+ Asynchronous Input

GTL+ Asynchronous Output

GTL+ Asynchronous Input/Output

TAP Input

FERR#/PBE#, IERR#, THERMTRIP#

PROCHOT#

Synchronous to TCK

Clock

TCK, TDI, TMS, TRST#

TDO

TAP Output

FSB Clock

BCLK[1:0], ITP_CLK[1:0]²

VCC, VTT, VCCA, VCCIOPLL, VID[5:0], VSS, VSSA, GTLREF,

COMP[1:0], RESERVED, TESTHI[13:0], THERMDA,

THERMDC, VCC_SENSE, VSS_SENSE, BSEL[2:0],

SKTOCC#, DBR#², VTTPWRGD, BOOTSELECT, PWRGOOD,

VTT_OUT_LEFT, VTT_OUT_RIGHT, VTT_SEL, LL_ID[1:0],

FCx, VSS_MB_REGULATION, VCC_MB_REGULATION,

MSID[1:0]

Power/Other

Datasheet

21

Electrical Specifications

NOTES:

1. Refer to Section 4.2 for signal descriptions.

2. In processor systems where there is no debug port implemented on the system board, these signals are used

to support a debug port interposer. In systems with the debug port implemented on the system board, these

signals are no connects.

3. The value of these signals during the active-to-inactive edge of RESET# defines the processor configuration

options. See Section 6.1 for details.

Table 2-4. Signal Characteristics

Signals with R_TT

Signals with no R_TT

A20M#, BCLK[1:0], BPM[5:0]#, BR0#, BSEL[2:0],

COMP[1:0], FERR#/PBE#, IERR#, IGNNE#, INIT#,

LINT0/INTR, LINT1/NMI, PWRGOOD, RESET#,

SKTOCC#, SMI#, STPCLK#, TDO, TESTHI[13:0],

THERMDA, THERMDC, THERMTRIP#, VID[5:0],

VTTPWRGD, GTLREF, TCK, TDI, TRST#, TMS

A[35:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#,

BNR#, BOOTSELECT¹, BPRI#, D[63:0]#, DBI[3:0]#,

DBSY#, DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#,

DSTBP[3:0]#, HIT#, HITM#, LOCK#, MCERR#,

PROCHOT#, REQ[4:0]#, RS[2:0]#, RSP#, TRDY#

Open Drain Signals²

BSEL[2:0], VID[5:0], THERMTRIP#, FERR#/PBE#,

IERR#, BPM[5:0]#, BR0#, TDO, VTT_SEL, LL_ID[1:0],

MSID[1:0]

NOTES:

1.

2.

The BOOTSELECT signal has a 500-5000 Ω pull-up to V rather than on-die termination.

TT

Signals that do not have R_TT, nor are actively driven to their high-voltage level.

.

Table 2-5. Signal Reference Voltages

GTLREF

V_TT/2

BPM[5:0]#, LINT0/INTR, LINT1/NMI, RESET#, BINIT#,

BNR#, HIT#, HITM#, MCERR#, PROCHOT#, BR0#,

A[35:0]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BPRI#, D[63:0]#,

DBI[3:0]#, DBSY#, DEFER#, DP[3:0]#, DRDY#,

DSTBN[3:0]#, DSTBP[3:0]#, LOCK#, REQ[4:0]#, RS[2:0]#,

RSP#, TRDY#

BOOTSELECT, VTTPWRGD, A20M#,

IGNNE#, INIT#, PWRGOOD¹, SMI#,

STPCLK#, TCK¹, TDI¹, TMS¹, TRST#¹

NOTES:

1.

These signals also have hysteresis added to the reference voltage. See Table 2-13 for more information.

2.7

GTL+ Asynchronous Signals

Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS input

buffers. All of these signals follow the same DC requirements as GTL+ signals, however the

outputs are not actively driven high (during a logical 0 to 1 transition) by the processor. These

signals do not have setup or hold time specifications in relation to BCLK[1:0].

All of the GTL+ Asynchronous signals are required to be asserted/de-asserted for at least six

BCLKs for the processor to recognize the proper signal state. See Section 6.2 for additional timing

requirements for entering and leaving the low power states.

22

Datasheet

Electrical Specifications

2.8

2.9

Test Access Port (TAP) Connection

Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is

recommended that the Pentium 4 processor in the 775-land package be first in the TAP chain and

followed by any other components within the system. A translation buffer should be used to

connect to the rest of the chain unless one of the other components is capable of accepting an input

of the appropriate voltage level. Similar considerations must be made for TCK, TMS, TRST#, TDI,

and TDO. Two copies of each signal may be required, with each driving a different voltage level.

FSB Frequency Select Signals (BSEL[2:0])

The BSEL[2:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]).

Table 2-6 defines the possible combinations of the signals and the frequency associated with each

combination. The required frequency is determined by the processor, chipset, and clock

synthesizer. All agents must operate at the same frequency.

The Pentium 4 processor in the 775-land package currently operates at a 533 MHz or 800 MHz

FSB frequency (selected by a 133 MHz or 200 MHz BCLK[1:0] frequency). Individual processors

will only operate at their specified FSB frequency.

For more information about these signals, refer to Section 4.2.

Table 2-6. BSEL[2:0] Frequency Table for BCLK[1:0]

BSEL2

BSEL1

BSEL0

FSB Frequency

L

H

L

RESERVED

133 MHz

L

H

L

RESERVED

200 MHz

L

H

L

RESERVED

L

H

L

H

Datasheet

23

Electrical Specifications

2.10

Absolute Maximum and Minimum Ratings

Table 2-7 specifies absolute maximum and minimum ratings. Within functional operation limits,

functionality and long-term reliability can be expected.

At conditions outside functional operation condition limits, but within absolute maximum and

minimum ratings, neither functionality nor long-term reliability can be expected. If a device is

returned to conditions within functional operation limits after having been subjected to conditions

outside these limits, but within the absolute maximum and minimum ratings, the device may be

functional, but with its lifetime degraded depending on exposure to conditions exceeding the

functional operation condition limits.

At conditions exceeding absolute maximum and minimum ratings, neither functionality nor long-

term reliability can be expected. Moreover, if a device is subjected to these conditions for any

length of time then, when returned to conditions within the functional operating condition limits, it

will either not function, or its reliability will be severely degraded.

Although the processor contains protective circuitry to resist damage from static electric discharge,

precautions should always be taken to avoid high static voltages or electric fields.

Table 2-7. Processor DC Absolute Maximum Ratings

Symbol

V_CC

Parameter

Min

Max

Unit

Notes^{1, 2}

Core voltage with respect to

V_SS

–0.3

1.55

V

—

FSB termination voltage with

respect to V_SS

V_TT

–0.3

1.55

V

—

T_C

Processor case temperature

Processor storage temperature

See Section 5

–40

See Section 5

+85

°C

—

3, 4

T_STORAGE

NOTES:

1.

2.

3.

For functional operation, all processor electrical, signal quality, mechanical and thermal specifications must be satisfied.

Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor.

Storage temperature is applicable to storage conditions only. In this scenario, the processor must not receive a clock, and

no lands can be connected to a voltage bias. Storage within these limits will not affect the long-term reliability of the device.

For functional operation, refer to the processor case temperature specifications.

4.

This rating applies to the processor and does not include any tray or packaging.

2.11

Processor DC Specifications

The processor DC specifications in this section are defined at the processor core silicon and

not at the package lands unless noted otherwise. See Chapter 4 for the signal definitions and

signal assignments. Most of the signals on the processor FSB are in the GTL+ signal group. The

DC specifications for these signals are listed in Table 2-12.

Previously, legacy signals and Test Access Port (TAP) signals to the processor used low-voltage

CMOS buffer types. However, these interfaces now follow DC specifications similar to GTL+. The

DC specifications for these signal groups are listed in Table 2-11 and Table 2-13.

Table 2-8 through Table 2-15 list the DC specifications for the Pentium 4 processor in the 775-land

package and are valid only while meeting specifications for case temperature, clock frequency, and

input voltages. Care should be taken to read all notes associated with each parameter.

MSR_PLATFORM_BRV bit 18 is a Platform Requirement Bit (PRB) that indicates that the

processor has specific platform requirements.

24

Datasheet

Electrical Specifications

Table 2-8. Voltage and Current Specifications (Sheet 1 of 2)

Symbol

VID range

Parameter

Min

Typ

Max

Unit

Notes¹

2

VID

1.200

—

1.425

V

Processor Number

Core Frequency

V_CCfor 775_VR_CONFIG_04B

processors

Refer to Table 2-10 and

Figure 2-3

3, 4, 5, 6

570/571

560/561

550

3.80 GHZ (PRB = 1)

3.60 GHz (PRB = 1)

3.40 GHz (PRB = 1)

V_CC

V

V_CCfor 775_VR_CONFIG_04A

processors

550/551

540/541

530/531

520/521

3.40 GHz (PRB = 0)

3.20 GHz (PRB = 0)

3 GHz (PRB = 0)

Refer to Table 2-9 and

Figure 2-2

3, 4, 6, 7, 8

V_CC

2.80 GHz (PRB = 0)

I_CCfor processor with multiple

VID

570/571

560/561

550

3.80 GHZ (PRB = 1)

3.60 GHz (PRB = 1)

3.40 GHz (PRB = 1)

3.40 GHz (PRB = 0)

3.20 GHz (PRB = 0)

3 GHz (PRB = 0)

119

9

119

78

I_CC

—

A

550/551

540/541

530/531

520/521

2.80 GHz (PRB = 0)

I_CCStop-Grant

570/571

560/561

550

3.80 GHZ (PRB = 1)

3.60 GHz (PRB = 1)

3.40 GHz (PRB = 1)

3.40 GHz (PRB = 0)

3.20 GHz (PRB = 0)

3 GHz (PRB = 0)

56

40

I_SGNT

10, 11, 15

—

A

550/551

540/541

530/531

520/521

2.80 GHz (PRB = 0)

I_CCEnhanced Auto Halt

3.80 GHZ (PRB = 1)

3.60 GHz (PRB = 1)

3.40 GHz (PRB = 0)

3.20 GHz (PRB = 0)

3 GHz (PRB = 0)

570/571

560/561

550/551

540/541

530/531

520/521

37

31

40

I_{ENHANCED_AUTO_}

11, 15

—

A

HALT

2.80 GHz (PRB = 0)

12

I_TCC

I_CCTCC active

—

1.14

—

1.20

—

I_CC

1.26

580

3.5

A

V

13, 14

V_TT

FSB termination voltage (DC+AC specifications)

DC Current that may be drawn from VTT_OUT per pin

FSB termination current

VTT_OUT I_CC

I_TT

mA

A

15, 16

—

Datasheet

25

Electrical Specifications

Table 2-8. Voltage and Current Specifications (Sheet 2 of 2)

Symbol

I_{CC_VCCA}

Parameter

Min

Typ

Max

Unit

Notes¹

15

I_{CC FOR PLL LANDS}

I_{CC FOR I/O PLL LAND}

I_CCfor GTLREF

—

120

100

200

mA

µA

15

I_{CC_VCCIOPLL}

I_{CC_GTLREF}

NOTES:

1.

Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These specifications will be up-

dated with characterized data from silicon measurements at a later date.

2.

Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and can not be altered.

Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings

within the VID range. Note this differs from the VID employed by the processor during a power management event (Thermal Monitor 2 or En-

hanced HALT State).

3.

4.

These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is required. See Section 2.4

and Table 2-2 for more information.

The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the socket with a 100 MHz bandwidth os-

cilloscope, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the probe should be less

than 5 mm. Ensure external noise from the system is not coupled into the oscilloscope probe.

5.

6.

7.

8.

9.

Refer to Table 2-10 and Figure 2-3 for the minimum, typical, and maximum V allowed for a given current. The processor should not be sub-

CC

jected to any Vcc and Icc combination wherein V exceeds V

for a given current.

cc_max

CC

775_VR_CONFIG_04A and 775_VR_CONFIG_04B refer to voltage regulator configurations that are defined in the Voltage Regulator Down

(VRD) 10.1 Design Guide For Desktop LGA775 Socket.

Refer to Table 2-9 and Figure 2-2 for the minimum, typical, and maximum V allowed for a given current. The processor should not be subjected

CC

to any V and I combination wherein V exceeds V for a given current.

CC

CC_max

These frequencies will operate in a system designed for 775_VR_CONFIG_04B processors. The power and I will be incrementally higher in

CC

this configuration due to the improved loadline and resulting higher V

.

CC

I

is specified at V

.

cc_max

CC_max

10. The current specified is also for AutoHALT State.

11. Icc Stop-Grant and I Enhanced Auto Halt are specified at V

.

CC

CC_max

12. The maximum instantaneous current the processor will draw while the thermal control circuit is active as indicated by the assertion of PROCHOT#

is the same as the maximum Icc for the processor.

13.

V

must be provided via a separate voltage source and not be connected to V . This specification is measured at the land.

TT CC

14. Baseboard bandwidth is limited to 20 MHz.

15. These parameters are based on design characterization and are not tested.

16. This is maximum total current drawn from V plane by only the processor. This specification does not include the current coming from R

TT

(through the signal line). Refer to the Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket to determine the total I

drawn by the system.

26

Datasheet

Electrical Specifications

Table 2-9. V Static and Transient Tolerance for 775_VR_CONFIG_04A Processors

CC

Voltage Deviation from VID Setting (V)^{1, 2, 3, 4}

I_CC(A)

Maximum Voltage

Typical Voltage

Minimum Voltage

1.70 mΩ

1.75 mΩ

1.80 mΩ

0

5

0.000

-0.009

-0.017

-0.026

-0.034

-0.043

-0.051

-0.060

-0.068

-0.077

-0.085

-0.094

-0.102

-0.111

-0.119

-0.128

-0.133

-0.025

-0.034

-0.043

-0.051

-0.060

-0.069

-0.078

-0.086

-0.095

-0.104

-0.113

-0.121

-0.130

-0.139

-0.148

-0.156

-0.162

-0.050

-0.059

-0.068

-0.077

-0.086

-0.095

-0.104

-0.113

-0.122

-0.131

-0.140

-0.149

-0.158

-0.167

-0.176

-0.185

-0.190

10

15

20

25

30

35

40

45

50

55

60

65

70

75

78

NOTES:

1.

The loadline specification includes both static and transient limits except for overshoot allowed as shown in

Section 2.12.

2.

3.

This table is intended to aid in reading discrete points on Figure 2-2.

The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage

regulation feedback for voltage regulator circuits must be taken from processor V and V lands. Refer to

CC

SS

the Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket for socket loadline guide-

lines and VR implementation details.

4.

Adherence to this loadline specification for the processor is required to ensure reliable processor operation.

Datasheet

27

Electrical Specifications

Figure 2-2. V Static and Transient Tolerance for 775_VR_CONFIG_04A

CC

Icc [A]

0

10

20

30

40

50

60

70

VID - 0.000

VID - 0.025

VID - 0.050

VID - 0.075

VID - 0.100

VID - 0.125

VID - 0.150

VID - 0.175

VID - 0.200

Vcc Maximum

Vcc Typical

Vcc Minimum

NOTES:

1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2.12.

2. This loadline specification shows the deviation from the VID set point.

3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage regulation

feedback for voltage regulator circuits must be taken from processor V and V lands. Refer to the Voltage Regulator

CC

SS

Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket for socket loadline guidelines and VR implementation details.

4. Adherence to this loadline specification for the processor is required to ensure reliable processor operation.

28

Datasheet

Electrical Specifications

Table 2-10. V Static and Transient Tolerance for 775_VR_CONFIG_04B Processors

CC

Voltage Deviation from VID Setting (V)^{1, 2, 3, 4}

I_CC(A)

Maximum Voltage

Typical Voltage

Minimum Voltage

1.30 mΩ

1.35 mΩ

1.40 mΩ

0

5

0.000

-0.007

-0.013

-0.020

-0.026

-0.033

-0.039

-0.046

-0.052

-0.059

-0.065

-0.072

-0.078

-0.085

-0.091

-0.098

-0.104

-0.111

-0.117

-0.124

-0.130

-0.137

-0.143

-0.150

-0.155

-0.019

-0.026

-0.033

-0.039

-0.046

-0.053

-0.060

-0.066

-0.073

-0.080

-0.087

-0.093

-0.100

-0.107

-0.114

-0.120

-0.127

-0.134

-0.141

-0.147

-0.154

-0.161

-0.168

-0.174

-0.180

-0.038

-0.045

-0.052

-0.059

-0.066

-0.073

-0.080

-0.087

-0.094

-0.101

-0.108

-0.115

-0.122

-0.129

-0.136

-0.143

-0.150

-0.157

-0.164

-0.171

-0.178

-0.185

-0.192

-0.199

-0.205

10

15

20

25

30

35

40

45

50

55

60

65

70

75

80

85

90

95

100

105

110

115

119

NOTES:

1.

The loadline specification includes both static and transient limits except for overshoot allowed as shown in

Section 2.12.

2.

3.

This table is intended to aid in reading discrete points on Figure 2-2.

The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage

regulation feedback for voltage regulator circuits must be taken from processor V and V lands. Refer to

CC

SS

the Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket for socket loadline guide-

lines and VR implementation details.

4.

Adherence to this loadline specification for the processor is required to ensure reliable processor operation.

Datasheet

29

Electrical Specifications

Figure 2-3. V Static and Transient Tolerance for 775_VR_CONFIG_04B

CC

Icc [A]

0

10

20

30

40

50

60

70

80

90

100

110

120

VID - 0.000

VID - 0.019

VID - 0.038

VID - 0.057

VID - 0.076

VID - 0.095

VID - 0.114

VID - 0.133

VID - 0.152

VID - 0.171

VID - 0.190

VID - 0.209

VID - 0.228

Vcc Maximum

Vcc Typical

Vcc Minimum

NOTES:

1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2.12.

2. This loadline specification shows the deviation from the VID set point.

3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage regulation

feedback for voltage regulator circuits must be taken from processor V and V lands. Refer to the Voltage Regulator

CC

SS

Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket for socket loadline guidelines and VR implementation details.

4. Adherence to this loadline specification for the processor is required to ensure reliable processor operation.

30

Datasheet

Electrical Specifications

Table 2-11. GTL+ Asynchronous Signal Group DC Specifications

Symbol

Parameter

Min

Max

Unit Notes¹

2, 3

V_IL

V_IH

Input Low Voltage

Input High Voltage

Output High Voltage

0.0

V_TT/2 – (0.10 * V_TT

)

V

3, 4, 5, 6

V_TT/2 + (0.10 * V_TT

0.90*V_TT

)

V_TT

V

5, 6, 7

V_OH

V

V_TT/[(0.50*R_{TT_MIN}) +

8

I_OL

Output Low Current

—

A

R_{ON_MIN}

± 200

12

]

9

I_LI

I_LO

Input Leakage Current

Output Leakage Current

Buffer On Resistance

N/A

8

µA

10

µA

R_ON

Ω

-

NOTES:

1.

2.

3.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.

LINT0/INTR and LINT1/NMI use GTLREF as a reference voltage. For these two signals V = GTLREF + (0.10 * V ) and

V

IL

IH

TT

V = GTLREF – (0.10 * V ).

IL

TT

4.

5.

V

is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.

IH

and V may experience excursions above V . However, input signal drivers must comply with the signal quality spec-

OH

TT

ifications.

6.

7.

8.

The V referred to in these specifications refers to instantaneous V

All outputs are open drain.

The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test

load.

.

TT

9.

Leakage to V with land held at V .

SS TT

10. Leakage to V with land held at 300 mV.

TT

Table 2-12. GTL+ Signal Group DC Specifications

Symbol

Parameter

Min

Max

Unit Notes¹

2, 3

V_IL

V_IH

Input Low Voltage

Input High Voltage

Output High Voltage

0.0

GTLREF – (0.10 * V_TT

)

V

3, 4

GTLREF + (0.10 * V_TT

0.90*V_TT

)

V_TT

V

3

V_OH

V

V_TT/[(0.50*R_{TT_MIN}) +

I_OL

Output Low Current

N/A

A

-

R_{ON_MIN}

± 200

12

]

5

-

I_LI

I_LO

Input Leakage Current

Output Leakage Current

Buffer On Resistance

N/A

8

µA

Ω

R_ON

-

NOTES:

1.

2.

3.

4.

5.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.

The V referred to in these specifications is the instantaneous V

V

IL

.

TT

V

is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.

IH

Leakage to V with land held at V

.

SS

TT

Datasheet

31

Electrical Specifications

Table 2-13. PWRGOOD and TAP Signal Group DC Specifications

Symbol

Parameter

Min

Max

Unit Notes^{1, 2}

3

V_HYS

Input Hysteresis

200

350

mV

Input low to high

threshold voltage

4

V_T+

V_T-

0.5 * (V_TT+ V_{HYS_MIN)}

0.5 * (V_TT+ V_{HYS_MAX}

)

V

Input high to low

threshold voltage

4

0.5 * (V_TT– V_{HYS_MAX}

)

0.5 * (V_TT– V_{HYS_MIN}

)

V

4

V_OH

I_OL

Output High Voltage

Output Low Current

Input Leakage Current

Output Leakage Current

Buffer On Resistance

N/A

—

7

V_TT

45

V

5

mA

6

I_LI

± 200

12

µA

-

I_LO

µA

R_ON

NOTES:

Ω

-

1.

2.

3.

4.

5.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

All outputs are open drain.

V

represents the amount of hysteresis, nominally centered about 0.5 * V , for all TAP inputs.

HYS

TT

The V referred to in these specifications refers to instantaneous V

.

TT

The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test

load.

6.

Leakage to V with land held at V .

SS TT

Table 2-14. VTTPWRGD DC Specifications

Symbol

Parameter

Min

Typ

Max

Unit

Notes

V_IL

V_IH

Input Low Voltage

Input High Voltage

—

0.3

—

V

0.9

Table 2-15. BSEL [2:0] and VID[5:0] DC Specifications

Symbol

Parameter

Max

Unit

Notes^{1, 2}

R_ON(BSEL) Buffer On Resistance

R_ON(VID) Buffer On Resistance

60

Ω

—

60

8

I_OL

I_LO

Max Land Current

mA

µA

V

—

3

Output Leakage Current

Voltage Tolerance

200

V_TOL

V_TT(max)

—

NOTES:

1.

2.

3.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

These parameters are not tested and are based on design simulations.

Leakage to V with land held at 2.5 V.

SS

Table 2-16. BOOTSELECT DC Specifications

Symbol

Parameter

Min

Typ

Max

Unit

Notes

1

V_IL

V_IH

Input Low Voltage

Input High Voltage

—

0.24

—

V

0.96

—

NOTES:

1.

These parameters are not tested and are based on design simulations.

32

Datasheet

Electrical Specifications

2.12

V Overshoot Specification

CC

The Pentium 4 processor in the 775-land package can tolerate short transient overshoot events

where V exceeds the VID voltage when transitioning from a high to low current load condition.

CC

This overshoot cannot exceed VID + V_{OS_MAX}(V_{OS_MAX}is the maximum allowable overshoot

voltage). The time duration of the overshoot event must not exceed T_{OS_MAX}(T_{OS_MAX}is the

maximum allowable time duration above VID). These specifications apply to the processor die

voltage as measured across the VCC_SENSE and VSS_SENSE lands.

Table 2-17. V Overshoot Specifications

CC

Symbol

Parameter

Min

Typ

Max

Unit

Figure

Magnitude of V_CC

overshoot above VID

V_{OS_MAX}

—

0.050

V

2-4

Time duration of V_CC

overshoot above VID

T_{OS_MAX}

—

25

µs

2-4

Figure 2-4. V Overshoot Example Waveform

CC

Example Overshoot Waveform

V_OS

VID + 0.050

VID

T_OS

Time

T_OS: Overshoot time above VID

V_OS: Overshoot above VID

NOTES:

1. V_OSis measured overshoot voltage.

2. T_OSis measured time duration above VID.

2.12.1

Die Voltage Validation

Overshoot events from application testing on real processors must meet the specifications in

Table 2-17 when measured across the VCC_SENSE and VSS_SENSE lands. Overshoot events that

are < 10 ns in duration may be ignored. These measurements of processor die level overshoot

should be taken with a 100 MHz bandwidth limited oscilloscope. Refer to the Voltage Regulator

Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket for additional voltage regulator

validation details.

Datasheet

33

Electrical Specifications

2.13

GTL+ FSB Specifications

Termination resistors are not required for most GTL+ signals, as these are integrated into the

processor silicon.Valid high and low levels are determined by the input buffers which compare a

signal’s voltage with a reference voltage called GTLREF. Table 2-18 lists the GTLREF

specifications. The GTL+ reference voltage (GTLREF) should be generated on the system board

using high precision voltage divider circuits.

Table 2-18. GTL+ Bus Voltage Definitions

Symbol

Parameter

Min

Typ

Max

Units Notes¹

Bus Reference

Voltage

2, 3, 4, 5

GTLREF

(0.98 * 0.67) * V_TT0.67 * V_TT(1.02 * 0.67) * V_TT

V

On die pullup for

BOOTSELECT

signal

6

R_PULLUP

500

—

5000

Ω

Termination

Resistance

7

R_TT

54

60

66

61

Ω

8

COMP[1:0]

COMP Resistance

59.8

60.4

Ω

NOTES:

1.

2.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

The tolerances for this specification have been stated generically to enable the system designer to calculate the minimum

and maximum values across the range of V

.

TT

3.

4.

5.

GTLREF should be generated from V by a voltage divider of 1% resistors or 1% matched resistors.

TT

The V referred to in these specifications is the instantaneous V

The Intel 915G/915GV/915P and 910GL Express chipset platforms use a pull-up resistor of 100 Ω and a pull-down resistor

of 210 Ω. Contact your Intel representative for further details and documentation.

These pull-ups are to V .

TT

.

TT

®

6.

7.

8.

R_TTis the on-die termination resistance measured at V /2 of the GTL+ output driver.

TT

COMP resistance must be provided on the system board with 1% resistors. COMP[1:0] resistors are to V

.

SS

§

34

Datasheet

Package Mechanical Specifications

3 Package Mechanical

Specifications

The Pentium 4 processor in the 775-land package is packaged in a Flip-Chip Land Grid Array

(FC-LGA4) package that interfaces with the motherboard via an LGA775 socket. The package

consists of a processor core mounted on a substrate land-carrier. An integrated heat spreader (IHS)

is attached to the package substrate and core and serves as the mating surface for processor

component thermal solutions, such as a heatsink. Figure 3-1 shows a sketch of the processor

package components and how they are assembled together. Refer to the LGA775 Socket

Mechanical Design Guide for complete details on the LGA775 socket.

The package components shown in Figure 3-1 include the following:

• Integrated Heat Spreader (IHS)

• Thermal Interface Material (TIM)

• Processor core (die)

• Package substrate

• Capacitors

Figure 3-1. Processor Package Assembly Sketch

TIM

Core (die)

IHS

Substrate

Capacitors

LGA775 Socket

System Board

NOTE:

1. Socket and motherboard are included for reference and are not part of processor package.

3.1

Package Mechanical Drawing

The package mechanical drawings are shown in Figure 3-2 and Figure 3-4. The drawings include

dimensions necessary to design a thermal solution for the processor. These dimensions include:

• Package reference with tolerances (total height, length, width, etc.)

• IHS parallelism and tilt

• Land dimensions

• Top-side and back-side component keep-out dimensions

• Reference datums

All drawing dimensions are in mm [in].

Note: Guidelines on potential IHS flatness variation with socket load plate actuation and installation of

the cooling solution is available in the processor Thermal/Mechanical Design Guidelines.

Datasheet

35

Package Mechanical Specifications

Figure 3-2. Processor Package Drawing 1

36

Datasheet

Package Mechanical Specifications

Figure 3-3. Processor Package Drawing 2

Datasheet

37

Package Mechanical Specifications

Figure 3-4. Processor Package Drawing 3

38

Datasheet

Package Mechanical Specifications

3.2

Processor Component Keep-Out Zones

The processor may contain components on the substrate that define component keep-out zone

requirements. A thermal and mechanical solution design must not intrude into the required keep-

out zones. Decoupling capacitors are typically mounted to either the topside or land-side of the

package substrate. See Figure 3-2 and Figure 3-3 for keep-out zones.

The location and quantity of package capacitors may change due to manufacturing efficiencies but

will remain within the component keep-in.

3.3

Package Loading Specifications

Table 3-1 provides dynamic and static load specifications for the processor package. These

mechanical maximum load limits should not be exceeded during heatsink assembly, shipping

conditions, or standard use condition. Also, any mechanical system or component testing should

not exceed the maximum limits. The processor package substrate should not be used as a

mechanical reference or load-bearing surface for thermal and mechanical solution. The minimum

loading specification must be maintained by any thermal and mechanical solutions.

.

Table 3-1. Processor Loading Specifications

Parameter

Minimum

Maximum

Notes

1, 2, 3

Static

80 N [18 lbf]

—

311 N [70 lbf]

1, 3, 4

Dynamic

756 N [170 lbf]

NOTES:

1.

2.

These specifications apply to uniform compressive loading in a direction normal to the processor IHS.

This is the maximum force that can be applied by a heatsink retention clip. The clip must also provide the minimum specified

load on the processor package.

3.

4.

These specifications are based on limited testing for design characterization. Loading limits are for the package only and

does not include the limits of the processor socket.

Dynamic loading is defined as the sum of the load on the package from a 1 lb heatsink mass accelerating through a 11 ms

trapezoidal pulse of 50 g and the maximum static load.

3.4

Package Handling Guidelines

Table 3-2 includes a list of guidelines on package handling in terms of recommended maximum

loading on the processor IHS relative to a fixed substrate. These package handling loads may be

experienced during heatsink removal.

Table 3-2. Package Handling Guidelines

Parameter

Maximum Recommended

Notes

1, 4

Shear

Tensile

311 N [70 lbf]

111 N [25 lbf]

2, 4

3, 4

Torque

3.95 N-m [35 lbf-in]

NOTES:

1.

2.

3.

4.

A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface.

A tensile load is defined as a pulling load applied to the IHS in a direction normal to the IHS surface.

A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the IHS top surface.

These guidelines are based on limited testing for design characterization.

Datasheet

39

Package Mechanical Specifications

3.5

Package Insertion Specifications

The Pentium 4 processor in the 775-land package can be inserted into and removed from a

LGA775 socket 15 times. The socket should meet the LGA775 requirements detailed in the

LGA775 Socket Mechanical Design Guide.

3.6

3.7

Processor Mass Specification

The typical mass of the Pentium 4 processor in the 775-land package is 21.5 g [0.76 oz]. This mass

[weight] includes all the components that are included in the package.

Processor Materials

Table 3-3 lists some of the package components and associated materials.

Table 3-3. Processor Materials

Component

Material

Integrated Heat Spreader (IHS)

Substrate

Nickel Plated Copper

Fiber Reinforced Resin

Gold Plated Copper

Substrate Lands

3.8

Processor Markings

Figure 3-5 and Figure 3-6 show the topside markings on the processor. These diagrams aid in the

identification of the Pentium 4 processor in the 775-land package.

Figure 3-5. Processor Top-Side Marking Example

Frequency/L2Cache/Bus/

775_VR_CONFIG_04x

m

‘04

©

INTEL

®

Pentium 4

S-Spec/CountryofAssy

3.60GHz/1M/800/04B

SLxxx [COO]

FPO

[FPO]

UniqueUnit

Identifier

2-DMatrixMark

ATPO Serial#

ATPO

S/N

40

Datasheet

Package Mechanical Specifications

®

Figure 3-6. Processor Top-Side Marking Example for Processors Supporting Intel EM64T

ProcessorNumber/S-Spec/

CountryofAssy

m

‘04

©

INTEL

®

Pentium 4

Frequency/L2Cache/Bus/

775_VR_CONFIG_04x

571 SLxxx [COO]

3.80GHZ/1M/800/04B

[FPO]

FPO

UniqueUnit

Identifier

2-DMatrixMark

ATPO Serial#

ATPO

S/N

3.9

Processor Land Coordinates

Figure 3-7 shows the top view of the processor land coordinates. The coordinates are referred to

throughout the document to identify processor lands.

Datasheet

41

Package Mechanical Specifications

.

Figure 3-7. Processor Land Coordinates (Top View)

V_CC/ V_SS

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1

AN

AM

AL

AN

AM

AL

AK

AJ

AH

AG

AF

AE

AD

AC

AB

AA

Y

AK

AJ

AH

AG

AF

AE

AD

AC

AB

AA

Y

W

V

Socket 775

Quadrants

Address / Common

Clock / Async

V

U

T

Top View

R

P

N

M

L

P

N

M

L

K

J

K

J

H

G

F

H

G

F

E

D

C

B

A

E

D

C

B

A

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1

V_TT/ Clocks

Data

§

42

Datasheet

Land Listing and Signal Descriptions

4 Land Listing and Signal

Descriptions

This chapter provides the processor land assignment and signal descriptions.

4.1

Processor Land Assignments

This section contains the land listings for the Pentium 4 processor in the 775-land package. The

landout footprint is shown in Figure 4-1 and Figure 4-2. These figures represent the landout

arranged by land number and they show the physical location of each signal on the package land

array (top view). Table 4-1 is a listing of all processor lands ordered alphabetically by land (signal)

name. Table 4-2 is also a listing of all processor lands; the ordering is by land number.

Datasheet

43

Land Listing and Signal Descriptions

Figure 4-1. Landout Diagram (Top View – Left Side)

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

AN

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

AM

AL

AK

AJ

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

AH

AG

AF

AE

AD

AC

AB

AA

Y

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

W

V

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

U

T

R

VSS

P

N

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

M

VCC

L

K

J

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

DP3#

VSS

DP0#

DP2#

VCC

H

GTLREF

_SEL

BSEL1

DP1#

G

F

BSEL2 BSEL0 BCLK1 TESTHI4 TESTHI5 TESTHI3 TESTHI6 RESET# D47#

D44# DSTBN2# DSTBP2# D35#

D36#

D37#

VSS

D32#

VSS

D31#

D30#

D33#

VSS

RSVD

VSS

BCLK0 VTT_SEL TESTHI0 TESTHI2 TESTHI7 RSVD

VSS

D45#

D46#

D43#

D42#

VSS

D41#

VSS

D40#

DBI2#

D38#

D39#

VSS

E

D

VSS

VTT

VSS

VTT

VSS

VTT

VSS

VTT

RSVD

VSS

RSVD

D34#

RSVD

VTT

D48#

D49#

VCCIO

PLL

C

VTT

VSS

D58#

DBI3#

VSS

D54# DSTBP3#

VSS

D51#

D53#

B

A

VTT

30

VTT

29

VTT

28

VTT

27

VTT

26

VTT

25

VSS

24

VSSA

VCCA

23

D63#

D62#

22

D59#

VSS

21

VSS

RSVD

20

D60#

D61#

19

D57#

VSS

18

VSS

D56#

17

D55#

DSTBN3# VSS

16 15

44

Datasheet

Land Listing and Signal Descriptions

Figure 4-2. Landout Diagram (Top View – Right Side)

14

13

12

11

10

9

8

7

6

5

4

3

2

1

VSS_MB_

REGULATION REGULATION SENSE

VCC_MB_

VSS_

VCC_

SENSE

VCC

VSS

VCC

VSS

VCC

FC16

VSS

VID0

VSS

AN

VCC

VSS

VCC

VSS

VCC

FC12

VSS

VTTPWRGD

VID3

FC11

VID1

VSS

VID5

VID4

VSS

VID2

VSS

AM

AL

AK

AJ

PROCHOT# THERMDA

VCC

RSVD

A35#

VSS

ITP_CLK0

ITP_CLK1

VSS

THERMDC

BPM1#

VSS

VCC

A34#

A33#

A31#

A27#

VSS

BPM0#

RSVD

BPM3#

BPM4#

VSS

VCC

VSS

A32#

A30#

A28#

RSVD

VSS

AH

AG

AF

AE

AD

AC

AB

VCC

A29#

BPM5#

VSS

TRST#

TDO

VCC

VSS

SKTOCC#

VCC

RSVD

A22#

RSVD

TCK

ADSTB1#

A25#

A24#

BINIT#

VSS

BPM2#

DBR#

IERR#

TDI

VCC

VSS

RSVD

A26#

TMS

VCC

A17#

MCERR#

VSS

VTT_OUT_

RIGHT

VCC

VSS

A23#

VSS

A21#

A20#

VSS

LL_ID1

VSS

AA

Y

BOOT

SELECT

A19#

RSVD

VCC

VSS

A18#

VSS

A10#

VSS

A16#

A14#

A12#

A9#

VSS

A15#

A13#

A11#

TESTHI1 TESTHI12

MSID0

MSID1

VSS

W

V

VSS

AP1#

VSS

LL_ID0

AP0#

FC4

U

T

COMP1

FERR#/

PBE#

VCC

VSS

ADSTB0#

VSS

A8#

VSS

FC2

R

VCC

VSS

A4#

RSVD

VSS

INIT#

VSS

SMI#

TESTHI11

P

N

VSS

RSVD

IGNNE# PWRGOOD

THER-

VSS

VCC

VSS

REQ2#

A5#

A7#

STPCLK#

M

MTRIP#

VCC

VSS

A3#

A6#

VSS

TESTHI13

VSS

LINT1

LINT0

L

REQ3#

VSS

REQ0#

A20M#

K

VTT_OUT_

LEFT

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

REQ4#

VSS

REQ1#

VSS

RSVD

VSS

FC3

FC6

J

H

TESTHI10

RSP#

GTLREF

VSS

D29#

D28#

VSS

D27#

VSS

DSTBN1# DBI1# RSVD

D16#

D18#

D19#

VSS

BPRI#

D17#

VSS

DEFER#

VSS

RSVD

VSS

FC7

RS1#

RSVD

VSS

TESTHI9 TESTHI8

FC1

FC5

G

F

D24#

DSTBP1#

VSS

D23#

VSS

D21#

D22#

VSS

HITM#

HIT#

BR0#

TRDY#

VSS

D26#

D25#

RSVD

D20#

VSS

ADS#

E

D

C

RSVD

D15#

D12#

RSVD

DRDY#

VSS

D52#

VSS

D14#

D11#

VSS

RSVD

DSTBN0#

VSS

D3#

D1#

VSS

LOCK#

BNR#

VSS

D50#

14

RSVD

COMP0

13

D13#

VSS

12

VSS

D9#

11

D10# DSTBP0#

VSS

DBI0#

8

D6#

D7#

7

D5#

VSS

6

VSS

D4#

5

D0#

D2#

4

RS0#

RS2#

3

DBSY#

VSS

2

B

A

D8#

VSS

10

9

1

Datasheet

45

Land Listing and Signal Descriptions

Table 4-1. Alphabetical Land

Assignments

Table 4-1. Alphabetical Land

Assignments

Land Signal Buffer

Land Name

Land Signal Buffer

Land Name

Direction

#

Type

#

Type

A3#

A4#

L5

P6

M5

L4

Source Synch Input/Output

BCLK1

BINIT#

BNR#

BOOTSELECT

BPM0#

BPM1#

BPM2#

BPM3#

BPM4#

BPM5#

BPRI#

BR0#

BSEL0

BSEL1

BSEL2

COMP0

COMP1

D0#

G28

Clock

Input

AD3 Common Clock Input/Output

C2 Common Clock Input/Output

A5#

A6#

Y1

Power/Other

Input

A7#

M4

R4

T5

U6

T4

U5

U4

V5

V4

W5

AJ2 Common Clock Input/Output

AJ1 Common Clock Input/Output

AD2 Common Clock Input/Output

AG2 Common Clock Input/Output

AF2 Common Clock Input/Output

AG3 Common Clock Input/Output

A8#

A9#

A10#

A11#

A12#

A13#

A14#

A15#

A16#

A17#

A18#

A19#

A20#

A20M#

A21#

A22#

A23#

A24#

A25#

A26#

A27#

A28#

A29#

A30#

A31#

A32#

A33#

A34#

A35#

ADS#

ADSTB0#

ADSTB1#

AP0#

AP1#

BCLK0

G8 Common Clock

Input

F3 Common Clock Input/Output

G29

H30

G30

A13

T1

Power/Other

Output

Input

AB6 Source Synch Input/Output

W6

Y6

Y4

K3

Source Synch Input/Output

Input

B4

Source Synch Input/Output

Asynch GTL+

Input

D1#

C5

AA4 Source Synch Input/Output

AD6 Source Synch Input/Output

AA5 Source Synch Input/Output

AB5 Source Synch Input/Output

AC5 Source Synch Input/Output

AB4 Source Synch Input/Output

AF5 Source Synch Input/Output

AF4 Source Synch Input/Output

AG6 Source Synch Input/Output

AG4 Source Synch Input/Output

AG5 Source Synch Input/Output

AH4 Source Synch Input/Output

AH5 Source Synch Input/Output

AJ5 Source Synch Input/Output

AJ6 Source Synch Input/Output

D2 Common Clock Input/Output

D2#

A4

D3#

C6

D4#

A5

D5#

B6

D6#

B7

D7#

A7

D8#

A10 Source Synch Input/Output

A11 Source Synch Input/Output

B10 Source Synch Input/Output

C11 Source Synch Input/Output

D9#

D10#

D11#

D12#

D8

Source Synch Input/Output

D13#

B12 Source Synch Input/Output

C12 Source Synch Input/Output

D11 Source Synch Input/Output

D14#

D15#

D16#

G9

F8

F9

E9

D7

Source Synch Input/Output

D17#

R6

Source Synch Input/Output

D18#

AD5 Source Synch Input/Output

U2 Common Clock Input/Output

U3 Common Clock Input/Output

D19#

D20#

D21#

E10 Source Synch Input/Output

D10 Source Synch Input/Output

F28

Clock

Input

D22#

46

Datasheet

Land Listing and Signal Descriptions

Table 4-1. Alphabetical Land

Assignments

Table 4-1. Alphabetical Land

Assignments

Land Signal Buffer

Land Name

Land Signal Buffer

Direction

Land Name

Direction

#

Type

#

Type

D23#

D24#

D25#

D26#

D27#

D28#

D29#

D30#

D31#

D32#

D33#

D34#

D35#

D36#

D37#

D38#

D39#

D40#

D41#

D42#

D43#

D44#

D45#

D46#

D47#

D48#

D49#

D50#

D51#

D52#

D53#

D54#

D55#

D56#

D57#

D58#

D59#

D60#

D61#

D62#

F11

Source Synch Input/Output

D63#

DBI0#

B22 Source Synch Input/Output

A8 Source Synch Input/Output

F12 Source Synch Input/Output

D13 Source Synch Input/Output

E13 Source Synch Input/Output

G13 Source Synch Input/Output

F14 Source Synch Input/Output

G14 Source Synch Input/Output

F15 Source Synch Input/Output

G15 Source Synch Input/Output

G16 Source Synch Input/Output

E15 Source Synch Input/Output

E16 Source Synch Input/Output

G18 Source Synch Input/Output

G17 Source Synch Input/Output

F17 Source Synch Input/Output

F18 Source Synch Input/Output

E18 Source Synch Input/Output

E19 Source Synch Input/Output

F20 Source Synch Input/Output

E21 Source Synch Input/Output

F21 Source Synch Input/Output

G21 Source Synch Input/Output

E22 Source Synch Input/Output

D22 Source Synch Input/Output

G22 Source Synch Input/Output

D20 Source Synch Input/Output

D17 Source Synch Input/Output

A14 Source Synch Input/Output

C15 Source Synch Input/Output

C14 Source Synch Input/Output

B15 Source Synch Input/Output

C18 Source Synch Input/Output

B16 Source Synch Input/Output

A17 Source Synch Input/Output

B18 Source Synch Input/Output

C21 Source Synch Input/Output

B21 Source Synch Input/Output

B19 Source Synch Input/Output

A19 Source Synch Input/Output

A22 Source Synch Input/Output

DBI1#

G11 Source Synch Input/Output

D19 Source Synch Input/Output

C20 Source Synch Input/Output

DBI2#

DBI3#

DBR#

AC2

B2 Common Clock Input/Output

G7 Common Clock Input

Power/Other

Output

DBSY#

DEFER#

DP0#

J16 Common Clock Input/Output

H15 Common Clock Input/Output

H16 Common Clock Input/Output

J17 Common Clock Input/Output

C1 Common Clock Input/Output

DP1#

DP2#

DP3#

DRDY#

DSTBN0#

DSTBN1#

DSTBN2#

DSTBN3#

DSTBP0#

DSTBP1#

DSTBP2#

DSTBP3#

FC1

C8

Source Synch Input/Output

G12 Source Synch Input/Output

G20 Source Synch Input/Output

A16 Source Synch Input/Output

B9

Source Synch Input/Output

E12 Source Synch Input/Output

G19 Source Synch Input/Output

C17 Source Synch Input/Output

G2

R1

J2

Power/Other

Input

FC2

FC3

Input

FC4

T2

Input

FC5

F2 Common Clock

Input

FC6

H2

G5

Power/Other

Source Synch

Power/Other

Asynch GTL+

Power/Other

Input

FC7

Output

Input

FC11

AM5

AM7

AN7

R3

FC12

FC16

FERR#/PBE#

GTLREF

GTLREF_SEL

HIT#

H1

H29

Output

D4 Common Clock Input/Output

E4 Common Clock Input/Output

HITM#

IERR#

AB2 Asynch GTL+

Output

Input

IGNNE#

INIT#

N2

P3

Asynch GTL+

TAP

ITP_CLK0

AK3

Datasheet

47

Land Listing and Signal Descriptions

Table 4-1. Alphabetical Land

Assignments

Table 4-1. Alphabetical Land

Assignments

Land Signal Buffer

Land Name

Land Signal Buffer

Land Name

Direction

#

Type

#

Type

ITP_CLK1

LINT0

AJ3

K1

TAP

Input

RESERVED

RESET#

RS0#

Y3

D23

AK6

G6

Asynch GTL+

Power/Other

LINT1

L1

Input

LL_ID0

V2

Output

LL_ID1

AA2

G23 Common Clock

B3 Common Clock

F5 Common Clock

A3 Common Clock

H4 Common Clock

Input

Output

Input

Output

Input

LOCK#

C3 Common Clock Input/Output

AB3 Common Clock Input/Output

MCERR#

RS1#

MSID0

W1

V1

Power/Other

Output

RS2#

MSID1

RSP#

PROCHOT#

PWRGOOD

REQ0#

AL2

N1

Asynch GTL+ Input/Output

Power/Other Input

SKTOCC#

SMI#

AE8

P2

Power/Other

Asynch GTL+

TAP

K4

Source Synch Input/Output

STPCLK#

TCK

M3

REQ1#

J5

AE1

AD1

AF1

F26

W3

F25

G25

G27

G26

G24

F24

G3

REQ2#

M6

K6

TDI

TAP

REQ3#

TDO

TAP

REQ4#

J6

TESTHI0

TESTHI1

TESTHI2

TESTHI3

TESTHI4

TESTHI5

TESTHI6

TESTHI7

TESTHI8

TESTHI9

TESTHI10

TESTHI11

TESTHI12

TESTHI13

THERMDA

THERMDC

THERMTRIP#

TMS

Power/Other

Asynch GTL+

Power/Other

Asynch GTL+

TAP

RESERVED

A20

AC4

AE3

AE4

AE6

AH2

C9

D1

D14

D16

E23

E24

E5

G4

H5

P1

W2

L2

E6

AL1

AK1

M2

E7

F23

F29

F6

Output

Input

AC1

TRDY#

E3 Common Clock

G10

B13

J3

TRST#

AG1

AA8

AB8

TAP

VCC

Power/Other

VCC

N4

VCC

AC23 Power/Other

AC24 Power/Other

AC25 Power/Other

N5

VCC

P5

VCC

48

Datasheet

Land Listing and Signal Descriptions

Table 4-1. Alphabetical Land

Assignments

Table 4-1. Alphabetical Land

Assignments

Land Signal Buffer

Land Name

Land Signal Buffer

Direction

Land Name

Direction

#

Type

#

Type

VCC

AC26 Power/Other

AC27 Power/Other

AC28 Power/Other

AC29 Power/Other

AC30 Power/Other

VCC

AG19 Power/Other

AG21 Power/Other

AG22 Power/Other

AG25 Power/Other

AG26 Power/Other

AG27 Power/Other

AG28 Power/Other

AG29 Power/Other

AG30 Power/Other

AC8

Power/Other

AD23 Power/Other

AD24 Power/Other

AD25 Power/Other

AD26 Power/Other

AD27 Power/Other

AD28 Power/Other

AD29 Power/Other

AD30 Power/Other

AG8

AG9

Power/Other

AH11 Power/Other

AH12 Power/Other

AH14 Power/Other

AH15 Power/Other

AH18 Power/Other

AH19 Power/Other

AH21 Power/Other

AH22 Power/Other

AH25 Power/Other

AH26 Power/Other

AH27 Power/Other

AH28 Power/Other

AH29 Power/Other

AH30 Power/Other

AD8

Power/Other

AE11 Power/Other

AE12 Power/Other

AE14 Power/Other

AE15 Power/Other

AE18 Power/Other

AE19 Power/Other

AE21 Power/Other

AE22 Power/Other

AE23 Power/Other

AE9

Power/Other

AF11 Power/Other

AF12 Power/Other

AF14 Power/Other

AF15 Power/Other

AF18 Power/Other

AF19 Power/Other

AF21 Power/Other

AF22 Power/Other

AH8

AH9

Power/Other

AJ11

AJ12

AJ14

AJ15

AJ18

AJ19

AJ21

AJ22

AJ25

AJ26

AJ8

AF8

AF9

Power/Other

AG11 Power/Other

AG12 Power/Other

AG14 Power/Other

AG15 Power/Other

AG18 Power/Other

AJ9

AK11 Power/Other

Datasheet

49

Land Listing and Signal Descriptions

Table 4-1. Alphabetical Land

Assignments

Table 4-1. Alphabetical Land

Assignments

Land Signal Buffer

Land Name

Land Signal Buffer

Land Name

Direction

#

Type

#

Type

VCC

AK12 Power/Other

AK14 Power/Other

AK15 Power/Other

AK18 Power/Other

AK19 Power/Other

AK21 Power/Other

AK22 Power/Other

AK25 Power/Other

AK26 Power/Other

VCC

AN12 Power/Other

AN14 Power/Other

AN15 Power/Other

AN18 Power/Other

AN19 Power/Other

AN21 Power/Other

AN22 Power/Other

AN25 Power/Other

AN26 Power/Other

AN29 Power/Other

AN30 Power/Other

AK8

AK9

AL11

Power/Other

AN8

AN9

J10

J11

J12

J13

J14

J15

J18

J19

J20

J21

J22

J23

J24

J25

J26

J27

J28

J29

J30

J8

Power/Other

AL12 Power/Other

AL14 Power/Other

AL15 Power/Other

AL18 Power/Other

AL19 Power/Other

AL21 Power/Other

AL22 Power/Other

AL25 Power/Other

AL26 Power/Other

AL29 Power/Other

AL30 Power/Other

AL8

AL9

Power/Other

AM11 Power/Other

AM12 Power/Other

AM14 Power/Other

AM15 Power/Other

AM18 Power/Other

AM19 Power/Other

AM21 Power/Other

AM22 Power/Other

AM25 Power/Other

AM26 Power/Other

AM29 Power/Other

AM30 Power/Other

J9

K23

K24

K25

K26

K27

K28

AM8

AM9

Power/Other

AN11 Power/Other

50

Datasheet

Land Listing and Signal Descriptions

Table 4-1. Alphabetical Land

Assignments

Table 4-1. Alphabetical Land

Assignments

Land Signal Buffer

Land Name

Land Signal Buffer

Direction

Land Name

Direction

#

Type

#

Type

VCC

K29

K30

K8

Power/Other

VCC

U30

U8

Power/Other

V8

L8

W23

W24

W25

W26

W27

W28

W29

W30

W8

M23

M24

M25

M26

M27

M28

M29

M30

M8

Y23

Y24

Y25

Y26

Y27

Y28

Y29

Y30

Y8

N23

N24

N25

N26

N27

N28

N29

N30

N8

VCC_MB_

REGULATION

AN5

Power/Other

Output

P8

VCC_SENSE

VCCA

VCCIOPLL

VID0

AN3

A23

C23

AM2

AL5

AM3

AL6

AK4

AL4

A12

A15

A18

A2

Power/Other

R8

T23

T24

T25

T26

T27

T28

T29

T30

T8

Output

VID1

VID2

VID3

VID4

VID5

VSS

U23

U24

U25

U26

U27

U28

U29

VSS

A21

A24

A6

VSS

A9

VSS

AA23 Power/Other

Datasheet

51

Land Listing and Signal Descriptions

Table 4-1. Alphabetical Land

Assignments

Table 4-1. Alphabetical Land

Assignments

Land Signal Buffer

Land Name

Land Signal Buffer

Land Name

Direction

#

Type

#

Type

VSS

AA24 Power/Other

AA25 Power/Other

AA26 Power/Other

AA27 Power/Other

AA28 Power/Other

AA29 Power/Other

VSS

AF10 Power/Other

AF13 Power/Other

AF16 Power/Other

AF17 Power/Other

AF20 Power/Other

AF23 Power/Other

AF24 Power/Other

AF25 Power/Other

AF26 Power/Other

AF27 Power/Other

AF28 Power/Other

AF29 Power/Other

AA3

Power/Other

AA30 Power/Other

AA6

AA7

AB1

Power/Other

AB23 Power/Other

AB24 Power/Other

AB25 Power/Other

AB26 Power/Other

AB27 Power/Other

AB28 Power/Other

AB29 Power/Other

AB30 Power/Other

AF3

Power/Other

AF30 Power/Other

AF6

AF7

Power/Other

AG10 Power/Other

AG13 Power/Other

AG16 Power/Other

AG17 Power/Other

AG20 Power/Other

AG23 Power/Other

AG24 Power/Other

AB7

AC3

AC6

AC7

AD4

AD7

Power/Other

AG7

AH1

Power/Other

AE10 Power/Other

AE13 Power/Other

AE16 Power/Other

AE17 Power/Other

AH10 Power/Other

AH13 Power/Other

AH16 Power/Other

AH17 Power/Other

AH20 Power/Other

AH23 Power/Other

AH24 Power/Other

AE2

Power/Other

AE20 Power/Other

AE24 Power/Other

AE25 Power/Other

AE26 Power/Other

AE27 Power/Other

AE28 Power/Other

AE29 Power/Other

AE30 Power/Other

AH3

AH6

Power/Other

AH7

AJ10

AJ13

AJ16

AJ17

AJ20

AE5

AE7

Power/Other

52

Datasheet

Land Listing and Signal Descriptions

Table 4-1. Alphabetical Land

Assignments

Table 4-1. Alphabetical Land

Assignments

Land Signal Buffer

Land Name

Land Signal Buffer

Direction

Land Name

Direction

#

Type

#

Type

VSS

AJ23 Power/Other

AJ24 Power/Other

AJ27 Power/Other

AJ28 Power/Other

AJ29 Power/Other

AJ30 Power/Other

VSS

AM24 Power/Other

AM27 Power/Other

AM28 Power/Other

AM4

AN1

Power/Other

AN10 Power/Other

AN13 Power/Other

AN16 Power/Other

AN17 Power/Other

AJ4

AJ7

Power/Other

AK10 Power/Other

AK13 Power/Other

AK16 Power/Other

AK17 Power/Other

AN2

Power/Other

AN20 Power/Other

AN23 Power/Other

AN24 Power/Other

AN27 Power/Other

AN28 Power/Other

AK2

Power/Other

AK20 Power/Other

AK23 Power/Other

AK24 Power/Other

AK27 Power/Other

AK28 Power/Other

AK29 Power/Other

AK30 Power/Other

B1

B11

B14

B17

B20

B24

B5

Power/Other

AK5

AK7

Power/Other

AL10 Power/Other

AL13 Power/Other

AL16 Power/Other

AL17 Power/Other

AL20 Power/Other

AL23 Power/Other

AL24 Power/Other

AL27 Power/Other

AL28 Power/Other

B8

C10

C13

C16

C19

C22

C24

C4

C7

AL3

AL7

AM1

Power/Other

D12

D15

D18

D21

D24

D3

AM10 Power/Other

AM13 Power/Other

AM16 Power/Other

AM17 Power/Other

AM20 Power/Other

AM23 Power/Other

D5

D6

D9

Datasheet

53

Land Listing and Signal Descriptions

Table 4-1. Alphabetical Land

Assignments

Table 4-1. Alphabetical Land

Assignments

Land Signal Buffer

Land Name

Land Signal Buffer

Land Name

Direction

#

Type

#

Type

VSS

E11

E14

E17

E2

Power/Other

VSS

H9

J4

Power/Other

J7

K2

E20

E25

E26

E27

E28

E29

E8

K5

K7

L23

L24

L25

L26

L27

L28

L29

L3

F10

F13

F16

F19

F22

F4

L30

L6

L7

F7

M1

M7

N3

G1

H10

H11

H12

H13

H14

H17

H18

H19

H20

H21

H22

H23

H24

H25

H26

H27

H28

H3

N6

N7

P23

P24

P25

P26

P27

P28

P29

P30

P4

P7

R2

R23

R24

R25

R26

R27

R28

R29

H6

H7

H8

54

Datasheet

Land Listing and Signal Descriptions

Table 4-1. Alphabetical Land

Assignments

Table 4-1. Alphabetical Land

Assignments

Land Signal Buffer

Land Name

Land Signal Buffer

Direction

Land Name

Direction

#

Type

#

Type

VSS

R30

R5

Power/Other

VTT

C26

C27

C28

C29

C30

D25

D26

D27

D28

D29

D30

J1

Power/Other

VTT

R7

VTT

T3

T6

VTT

T7

VTT

U1

VTT

U7

VTT

V23

V24

V25

V26

V27

V28

V29

V3

VTT

VTT_OUT_LEFT

VTT_OUT_RIGHT

VTT_SEL

VTTPWRGD

Output

Input

AA1

F27

AM6

V30

V6

V7

W4

W7

Y2

Y5

Y7

VSS_MB_

AN6

Power/Other

Output

REGULATION

VSS_SENSE

VSSA

VTT

AN4

B23

A25

A26

A27

A28

A29

A30

B25

B26

B27

B28

B29

B30

C25

Power/Other

VTT

Datasheet

55

Land Listing and Signal Descriptions

Table 4-2. Numerical Land Assignment

Land

#

Signal Buffer

Type

Land

#

Signal Buffer

Type

Land Name

Direction

Land Name

Direction

A2

A3

VSS

RS2#

D2#

Power/Other

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

C1

RESERVED

VSS

Common Clock

Input

Power/Other

A4

Source Synch Input/Output

Power/Other

D53#

D55#

VSS

Source Synch Input/Output

Power/Other

A5

D4#

A6

VSS

A7

D7#

Source Synch Input/Output

Power/Other

D57#

D60#

VSS

Source Synch Input/Output

Power/Other

A8

DBI0#

VSS

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

B1

D8#

Source Synch Input/Output

Power/Other

D59#

D63#

VSSA

VSS

Source Synch Input/Output

Power/Other

D9#

VSS

COMP0

D50#

VSS

Power/Other

Input

Power/Other

Source Synch Input/Output

Power/Other

VTT

Power/Other

VTT

Power/Other

DSTBN3#

D56#

VSS

Source Synch Input/Output

Power/Other

VTT

Power/Other

VTT

Power/Other

VTT

Power/Other

D61#

RESERVED

VSS

Source Synch Input/Output

VTT

Power/Other

DRDY#

BNR#

LOCK#

VSS

Common Clock Input/Output

Power/Other

C2

D62#

VCCA

VSS

Source Synch Input/Output

Power/Other

C3

C4

Power/Other

C5

D1#

Source Synch Input/Output

Power/Other

VTT

Power/Other

C6

D3#

VTT

Power/Other

C7

VSS

VTT

Power/Other

C8

DSTBN0#

RESERVED

VSS

Source Synch Input/Output

VTT

Power/Other

C9

VTT

Power/Other

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

Power/Other

VTT

Power/Other

D11#

Source Synch Input/Output

Power/Other

VSS

Power/Other

D14#

VSS

B2

DBSY#

RS0#

D0#

Common Clock Input/Output

B3

Common Clock

Input

D52#

D51#

VSS

Source Synch Input/Output

Power/Other

B4

Source Synch Input/Output

Power/Other

B5

VSS

B6

D5#

Source Synch Input/Output

Power/Other

DSTBP3#

D54#

VSS

Source Synch Input/Output

Power/Other

B7

D6#

B8

VSS

B9

DSTBP0#

D10#

VSS

Source Synch Input/Output

Power/Other

DBI3#

D58#

VSS

Source Synch Input/Output

Power/Other

B10

B11

B12

D13#

Source Synch Input/Output

VCCIOPLL

Power/Other

56

Datasheet

Land Listing and Signal Descriptions

Table 4-2. Numerical Land Assignment

Land

#

Signal Buffer

Type

Land

#

Signal Buffer

Type

Land Name

Direction

Land Name

Direction

C24

C25

C26

C27

C28

C29

C30

D1

VSS

VTT

Power/Other

E6

E7

RESERVED

VSS

VTT

E8

Power/Other

VTT

E9

D19#

Source Synch Input/Output

Power/Other

VTT

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

E21

E22

E23

E24

E25

E26

E27

E28

E29

F2

D21#

VTT

VSS

VTT

DSTBP1#

D26#

Source Synch Input/Output

Power/Other

RESERVED

ADS#

VSS

D2

Common Clock Input/Output

Power/Other

VSS

D3

D33#

Source Synch Input/Output

Power/Other

D4

HIT#

Common Clock Input/Output

Power/Other

D34#

D5

VSS

D6

VSS

Power/Other

D39#

Source Synch Input/Output

Power/Other

D7

D20#

D12#

VSS

Source Synch Input/Output

Power/Other

D40#

D8

VSS

D9

D42#

Source Synch Input/Output

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

E2

D22#

D15#

VSS

Source Synch Input/Output

Power/Other

D45#

RESERVED

VSS

D25#

RESERVED

VSS

Source Synch Input/Output

Power/Other

VSS

Power/Other

VSS

RESERVED

D49#

VSS

Source Synch Input/Output

Power/Other

VSS

FC5

Common Clock

Input

DBI2#

D48#

VSS

Source Synch Input/Output

Power/Other

F3

BR0#

VSS

Common Clock Input/Output

Power/Other

F4

F5

RS1#

RESERVED

VSS

Common Clock

Input

D46#

RESERVED

VSS

Source Synch Input/Output

F6

F7

Power/Other

F8

D17#

Source Synch Input/Output

Power/Other

VTT

F9

D18#

VTT

F10

F11

F12

F13

F14

F15

F16

F17

F18

VSS

VTT

D23#

Source Synch Input/Output

Power/Other

VTT

D24#

VTT

VSS

VTT

D28#

Source Synch Input/Output

Power/Other

VSS

D30#

E3

TRDY#

HITM#

RESERVED

Common Clock

Input

VSS

E4

Common Clock Input/Output

D37#

Source Synch Input/Output

E5

D38#

Datasheet

57

Land Listing and Signal Descriptions

Table 4-2. Numerical Land Assignment

Land

#

Signal Buffer

Type

Land

#

Signal Buffer

Type

Land Name

Direction

Land Name

Direction

F19

F20

F21

F22

F23

F24

F25

F26

F28

F29

G1

VSS

D41#

Power/Other

H2

H3

FC6

VSS

Power/Other

Common Clock

Power/Other

Input

Source Synch Input/Output

Power/Other

D43#

H4

RSP#

TESTHI10

VSS

Input

VSS

H5

RESERVED

TESTHI7

TESTHI2

TESTHI0

BCLK0

RESERVED

VSS

H6

Power/Other

Clock

Input

H7

VSS

H8

VSS

H9

VSS

H10

H11

H12

H13

H14

H15

H16

H17

H18

H19

H20

H21

H22

H23

H24

H25

H26

H27

H28

H29

H30

J1

VSS

Power/Other

Source Synch

VSS

G2

FC1

Input

VSS

G3

TESTHI8

TESTHI9

FC7

VSS

G4

Input

DP1#

DP2#

VSS

Common Clock Input/Output

Power/Other

G5

Output

G6

RESERVED

DEFER#

BPRI#

G7

Common Clock

Input

VSS

Power/Other

G8

VSS

Power/Other

G9

D16#

Source Synch Input/Output

VSS

Power/Other

G10

G11

G12

G13

G14

G15

G16

G17

G18

G19

G20

G21

G22

G23

G24

G25

G26

G27

G28

G29

G30

H1

RESERVED

DBI1#

VSS

Power/Other

Source Synch Input/Output

VSS

Power/Other

DSTBN1#

D27#

VSS

Power/Other

VSS

Power/Other

D29#

VSS

Power/Other

D31#

VSS

Power/Other

D32#

VSS

Power/Other

D36#

VSS

Power/Other

D35#

GTLREF_SEL

BSEL1

VTT_OUT_LEFT

FC3

Power/Other

Output

Input

DSTBP2#

DSTBN2#

D44#

J2

D47#

J3

RESERVED

VSS

RESET#

TESTHI6

TESTHI3

TESTHI5

TESTHI4

BCLK1

BSEL0

BSEL2

GTLREF

Common Clock

Power/Other

Clock

Input

Output

Input

J4

Power/Other

J5

REQ1#

REQ4#

VSS

Source Synch Input/Output

Power/Other

J6

J7

J8

VCC

Power/Other

J9

VCC

Power/Other

J10

J11

J12

VCC

Power/Other

VCC

Power/Other

VCC

Power/Other

58

Datasheet

Land Listing and Signal Descriptions

Table 4-2. Numerical Land Assignment

Land

#

Signal Buffer

Type

Land

#

Signal Buffer

Type

Land Name

Direction

Land Name

Direction

J13

J14

J15

J16

J17

J18

J19

J20

J21

J22

J23

J24

J25

J26

J27

J28

J29

J30

K1

VCC

DP0#

DP3#

VCC

LINT0

VSS

Power/Other

L8

L23

L24

L25

L26

L27

L28

L29

L30

M1

VCC

VSS

Power/Other

Asynch GTL+

VSS

Common Clock Input/Output

Power/Other

VSS

Power/Other

VSS

Power/Other

VSS

Power/Other

VSS

Power/Other

VSS

Power/Other

M2

THERMTRIP#

STPCLK#

A7#

Output

Input

Power/Other

M3

Power/Other

M4

Source Synch Input/Output

Power/Other

M5

A5#

Power/Other

M6

REQ2#

VSS

Power/Other

M7

Power/Other

M8

VCC

Power/Other

M23

M24

M25

M26

M27

M28

M29

M30

N1

VCC

Power/Other

Asynch GTL+

Power/Other

Asynch GTL+

Input

VCC

Power/Other

K2

VCC

Power/Other

K3

A20M#

REQ0#

VSS

VCC

Power/Other

K4

Source Synch Input/Output

Power/Other

VCC

Power/Other

K5

VCC

Power/Other

K6

REQ3#

VSS

Source Synch Input/Output

Power/Other

VCC

Power/Other

K7

VCC

Power/Other

K8

VCC

LINT1

TESTHI13

VSS

Power/Other

PWRGOOD

IGNNE#

VSS

Power/Other

Asynch GTL+

Power/Other

Input

K23

K24

K25

K26

K27

K28

K29

K30

L1

Power/Other

N2

Power/Other

N3

Power/Other

N4

RESERVED

VSS

Power/Other

N5

Power/Other

N6

Power/Other

N7

VSS

Power/Other

N8

VCC

Power/Other

N23

N24

N25

N26

N27

N28

N29

N30

VCC

Asynch GTL+

Power/Other

Input

VCC

L2

VCC

L3

VCC

L4

A6#

Source Synch Input/Output

Power/Other

VCC

L5

A3#

VCC

L6

VSS

VCC

L7

VSS

Power/Other

VCC

Datasheet

59

Land Listing and Signal Descriptions

Table 4-2. Numerical Land Assignment

Land

#

Signal Buffer

Type

Land

#

Signal Buffer

Type

Land Name

Direction

Land Name

Direction

P1

P2

TESTHI11

SMI#

INIT#

VSS

Power/Other

Asynch GTL+

Power/Other

Input

T24

T25

T26

T27

T28

T29

T30

U1

VCC

VSS

Power/Other

P3

P4

P5

RESERVED

A4#

P6

Source Synch Input/Output

Power/Other

P7

VSS

P8

VCC

Power/Other

P23

P24

P25

P26

P27

P28

P29

P30

R1

VSS

Power/Other

U2

AP0#

AP1#

A13#

A12#

A10#

VSS

Common Clock Input/Output

Source Synch Input/Output

Power/Other

VSS

Power/Other

U3

VSS

Power/Other

U4

VSS

Power/Other

U5

VSS

Power/Other

U6

VSS

Power/Other

U7

VSS

Power/Other

U8

VCC

MSID1

LL_ID0

VSS

Power/Other

VSS

Power/Other

U23

U24

U25

U26

U27

U28

U29

U30

V1

Power/Other

FC2

Power/Other

Asynch GTL+

Input

Power/Other

R2

VSS

Power/Other

R3

FERR#/PBE#

A8#

Output

Power/Other

R4

Source Synch Input/Output

Power/Other

R5

VSS

Power/Other

R6

ADSTB0#

VSS

Source Synch Input/Output

Power/Other

R7

Power/Other

R8

VCC

Power/Other

Output

R23

R24

R25

R26

R27

R28

R29

R30

T1

VSS

Power/Other

V2

VSS

Power/Other

V3

VSS

Power/Other

V4

A15#

A14#

VSS

Source Synch Input/Output

Power/Other

VSS

Power/Other

V5

VSS

Power/Other

V6

VSS

Power/Other

V7

VSS

Power/Other

VSS

Power/Other

V8

VCC

VSS

Power/Other

VSS

Power/Other

V23

V24

V25

V26

V27

V28

V29

V30

W1

W2

Power/Other

COMP1

FC4

Power/Other

Input

VSS

Power/Other

T2

VSS

Power/Other

T3

VSS

Power/Other

T4

A11#

A9#

Source Synch Input/Output

Power/Other

VSS

Power/Other

T5

VSS

Power/Other

T6

VSS

Power/Other

T7

VSS

Power/Other

VSS

Power/Other

T8

VCC

Power/Other

MSID0

TESTHI12

Power/Other

Output

Input

T23

VCC

Power/Other

60

Datasheet

Land Listing and Signal Descriptions

Table 4-2. Numerical Land Assignment

Land

#

Signal Buffer

Type

Land

#

Signal Buffer

Type

Land Name

Direction

Land Name

Direction

W3

W4

TESTHI1

VSS

Power/Other

Input

AA27

AA28

AA29

AA30

AB1

VSS

Power/Other

Asynch GTL+

W5

A16#

A18#

VSS

Source Synch Input/Output

Power/Other

VSS

W6

VSS

W7

VSS

W8

VCC

Power/Other

AB2

IERR#

MCERR#

A26#

A24#

A17#

VSS

Output

W23

W24

W25

W26

W27

W28

W29

W30

Y1

VCC

Power/Other

AB3

Common Clock Input/Output

Source Synch Input/Output

Power/Other

VCC

Power/Other

AB4

VCC

Power/Other

AB5

VCC

Power/Other

AB6

VCC

Power/Other

AB7

VCC

Power/Other

AB8

VCC

Power/Other

VCC

Power/Other

AB23

AB24

AB25

AB26

AB27

AB28

AB29

AB30

AC1

VSS

Power/Other

VCC

Power/Other

VSS

Power/Other

BOOTSELECT

VSS

Power/Other

Input

VSS

Power/Other

Y2

VSS

Power/Other

Y3

RESERVED

A20#

VSS

Power/Other

Y4

Source Synch Input/Output

Power/Other

VSS

Power/Other

Y5

VSS

Power/Other

Y6

A19#

VSS

Source Synch Input/Output

Power/Other

VSS

Power/Other

Y7

TMS

TAP

Input

Y8

VCC

Power/Other

AC2

DBR#

VSS

Power/Other

Output

Y23

Y24

Y25

Y26

Y27

Y28

Y29

Y30

AA2

AA3

AA4

AA5

AA6

AA7

AA8

AA23

AA24

AA25

AA26

VCC

Power/Other

AC3

VCC

Power/Other

AC4

RESERVED

A25#

VSS

VCC

Power/Other

AC5

Source Synch Input/Output

Power/Other

VCC

Power/Other

AC6

VCC

Power/Other

AC7

VSS

Power/Other

VCC

Power/Other

AC8

VCC

Power/Other

VCC

Power/Other

AC23

AC24

AC25

AC26

AC27

AC28

AC29

AC30

AD1

VCC

Power/Other

VCC

Power/Other

VCC

Power/Other

LL_ID1

VSS

Power/Other

Output

VCC

Power/Other

VCC

Power/Other

A21#

A23#

VSS

Source Synch Input/Output

Power/Other

VCC

Power/Other

VCC

Power/Other

VCC

Power/Other

VSS

Power/Other

VCC

Power/Other

VCC

Power/Other

TDI

TAP

Input

VSS

Power/Other

AD2

BPM2#

BINIT#

VSS

Common Clock Input/Output

Power/Other

VSS

Power/Other

AD3

VSS

Power/Other

AD4

VSS

Power/Other

AD5

ADSTB1#

Source Synch Input/Output

Datasheet

61

Land Listing and Signal Descriptions

Table 4-2. Numerical Land Assignment

Land

#

Signal Buffer

Type

Land

#

Signal Buffer

Type

Land Name

Direction

Land Name

Direction

AD6

AD7

A22#

VSS

Source Synch Input/Output

Power/Other

AF1

AF2

TDO

BPM4#

A28#

A27#

VSS

TAP

Output

Common Clock Input/Output

Source Synch Input/Output

Power/Other

AD8

VCC

Power/Other

AF4

AD23

AD24

AD25

AD26

AD27

AD28

AD29

AD30

AE1

VCC

Power/Other

AF5

VCC

Power/Other

AF6

VCC

Power/Other

AF7

VSS

Power/Other

VCC

Power/Other

AF8

VCC

VSS

Power/Other

VCC

Power/Other

AF9

Power/Other

VCC

Power/Other

AF10

AF11

AF12

AF13

AF14

AF15

AF16

AF17

AF18

AF19

AF20

AF21

AF22

AF23

AF24

AF25

AF26

AF27

AF28

AF29

AF3

Power/Other

VCC

Power/Other

VCC

VSS

Power/Other

VCC

Power/Other

TCK

TAP

Input

Power/Other

AE2

VSS

Power/Other

VCC

VSS

Power/Other

AE3

RESERVED

VSS

Power/Other

AE4

Power/Other

AE5

Power/Other

VSS

Power/Other

AE6

RESERVED

VSS

VCC

VSS

Power/Other

AE7

Power/Other

AE8

SKTOCC#

VCC

Output

Power/Other

AE9

VCC

VSS

Power/Other

AE10

AE11

AE12

AE13

AE14

AE15

AE16

AE17

AE18

AE19

AE20

AE21

AE22

AE23

AE24

AE25

AE26

AE27

AE28

AE29

AE30

VSS

Power/Other

VCC

Power/Other

VCC

VSS

Power/Other

VSS

Power/Other

VCC

VSS

Power/Other

VCC

VSS

Power/Other

VSS

Power/Other

VSS

Power/Other

VCC

VSS

Power/Other

VCC

AF30

AG1

AG2

AG3

AG4

AG5

AG6

AG7

AG8

AG9

AG10

AG11

VSS

Power/Other

VSS

TRST#

BPM3#

BPM5#

A30#

A31#

A29#

VSS

TAP

Input

VCC

Common Clock Input/Output

Source Synch Input/Output

Power/Other

VCC

VSS

VCC

VSS

Power/Other

VSS

Power/Other

VSS

Power/Other

VSS

VCC

Power/Other

62

Datasheet

Land Listing and Signal Descriptions

Table 4-2. Numerical Land Assignment

Land

#

Signal Buffer

Type

Land

#

Signal Buffer

Type

Land Name

Direction

Land Name

Direction

AG12

AG13

AG14

AG15

AG16

AG17

AG18

AG19

AG20

AG21

AG22

AG23

AG24

AG25

AG26

AG27

AG28

AG29

AG30

AH1

VCC

VSS

Power/Other

AH23

AH24

AH25

AH26

AH27

AH28

AH29

AH30

AJ1

VSS

Power/Other

VCC

VSS

VCC

VSS

VCC

VSS

VCC

BPM1#

BPM0#

ITP_CLK1

VSS

Common Clock Input/Output

VCC

VSS

AJ2

AJ3

TAP

Input

AJ4

Power/Other

VSS

AJ5

A34#

A35#

VSS

Source Synch Input/Output

Power/Other

VCC

VSS

AJ6

AJ7

AJ8

VCC

AJ9

VCC

AJ10

AJ11

AJ12

AJ13

AJ14

AJ15

AJ16

AJ17

AJ18

AJ19

AJ20

AJ21

AJ22

AJ23

AJ24

AJ25

AJ26

AJ27

AJ28

AJ29

AJ30

AK1

VSS

VCC

AH2

RESERVED

VSS

AH3

Power/Other

VCC

AH4

A32#

A33#

VSS

Source Synch Input/Output

Power/Other

VCC

AH5

VSS

AH6

VSS

AH7

VSS

Power/Other

VCC

AH8

VCC

VSS

Power/Other

VCC

AH9

Power/Other

VSS

AH10

AH11

AH12

AH13

AH14

AH15

AH16

AH17

AH18

AH19

AH20

AH21

AH22

Power/Other

VCC

VSS

Power/Other

VCC

Power/Other

VSS

Power/Other

VSS

VCC

VSS

Power/Other

VCC

Power/Other

VCC

Power/Other

VSS

Power/Other

VSS

VCC

VSS

Power/Other

VSS

Power/Other

VSS

Power/Other

THERMDC

VSS

VCC

Power/Other

AK2

Power/Other

AK3

ITP_CLK0

TAP

Input

Datasheet

63

Land Listing and Signal Descriptions

Table 4-2. Numerical Land Assignment

Land

#

Signal Buffer

Type

Land

#

Signal Buffer

Type

Land Name

Direction

Land Name

Direction

AK4

AK5

VID4

VSS

Power/Other

Output

AL15

AL16

AL17

AL18

AL19

AL20

AL21

AL22

AL23

AL24

AL25

AL26

AL27

AL28

AL29

AL30

AM1

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VID0

VID2

VSS

FC11

FC12

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

Power/Other

AK6

RESERVED

VSS

AK7

Power/Other

AK8

VCC

AK9

VCC

AK10

AK11

AK12

AK13

AK14

AK15

AK16

AK17

AK18

AK19

AK20

AK21

AK22

AK23

AK24

AK25

AK26

AK27

AK28

AK29

AK30

AL1

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

AM2

Output

VCC

AM3

VSS

AM4

VSS

AM5

Output

VCC

AM7

VCC

AM8

VSS

AM9

VSS

AM10

AM11

AM12

AM13

AM14

AM15

AM16

AM17

AM18

AM19

AM20

AM21

AM22

AM23

AM24

AM25

AM26

VSS

THERMDA

PROCHOT#

VSS

AL2

Asynch GTL+ Input/Output

Power/Other

AL3

AL4

VID5

VID1

VID3

VSS

Power/Other

Output

AL5

AL6

AL7

AL8

VCC

AL9

VCC

AL10

AL11

AL12

AL13

AL14

VSS

VCC

VSS

VCC

64

Datasheet

Land Listing and Signal Descriptions

Table 4-2. Numerical Land Assignment

Land

#

Signal Buffer

Type

Land

#

Signal Buffer

Type

Land Name

Direction

Land Name

Direction

AM27

AM28

AM29

AM30

AN1

VSS

Power/Other

AN16

AN17

AN18

AN19

AN20

AN21

AN22

AN23

AN24

AN25

AN26

AN27

AN28

AN29

AN30

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

Power/Other

VCC

VSS

AN2

VSS

AN3

VCC_SENSE

VSS_SENSE

Output

AN4

VCC_MB_

REGULATION

AN5

AN6

Power/Other

Output

VSS_MB_

REGULATION

Output

AN7

AN8

FC16

VCC

VSS

VCC

VSS

VCC

Power/Other

AN9

AN10

AN11

AN12

AN13

AN14

AN15

Datasheet

65

Land Listing and Signal Descriptions

4.2

Alphabetical Signals Reference

Table 4-3. Signal Description (Sheet 1 of 8)

Name

Type

Description

A[35:3]# (Address) define a 2³⁶-byte physical memory address space. In sub-

phase 1 of the address phase, these signals transmit the address of a

transaction. In sub-phase 2, these signals transmit transaction type information.

These signals must connect the appropriate pins/lands of all agents on the

processor FSB. A[35:3]# are protected by parity signals AP[1:0]#. A[35:3]# are

source synchronous signals and are latched into the receiving buffers by

ADSTB[1:0]#.

Input/

Output

A[35:3]#

On the active-to-inactive transition of RESET#, the processor samples a subset

of the A[35:3]# signals to determine power-on configuration. See Section 6.1 for

more details.

If A20M# (Address-20 Mask) is asserted, the processor masks physical

address bit 20 (A20#) before looking up a line in any internal cache and before

driving a read/write transaction on the bus. Asserting A20M# emulates the 8086

processor's address wrap-around at the 1-MB boundary. Assertion of A20M# is

only supported in real mode.

A20M#

ADS#

Input

A20M# is an asynchronous signal. However, to ensure recognition of this signal

following an Input/Output write instruction, it must be valid along with the

TRDY# assertion of the corresponding Input/Output Write bus transaction.

ADS# (Address Strobe) is asserted to indicate the validity of the transaction

address on the A[35:3]# and REQ[4:0]# signals. All bus agents observe the

ADS# activation to begin parity checking, protocol checking, address decode,

internal snoop, or deferred reply ID match operations associated with the new

transaction.

Input/

Output

Address strobes are used to latch A[35:3]# and REQ[4:0]# on their rising and

falling edges. Strobes are associated with signals as shown below.

Signals

Associated Strobe

Input/

Output

ADSTB[1:0]#

REQ[4:0]#, A[16:3]#

A[35:17]#

ADSTB0#

ADSTB1#

AP[1:0]# (Address Parity) are driven by the request initiator along with ADS#,

A[35:3]#, and the transaction type on the REQ[4:0]#. A correct parity signal is

high if an even number of covered signals are low and low if an odd number of

covered signals are low. This allows parity to be high when all the covered

signals are high. AP[1:0]# should connect the appropriate pins/lands of all

processor FSB agents. The following table defines the coverage model of these

signals.

Input/

Output

AP[1:0]#

Request Signals

Subphase 1

Subphase 2

A[35:24]#

A[23:3]#

AP0#

AP1#

AP0#

REQ[4:0]#

The differential pair BCLK (Bus Clock) determines the FSB frequency. All

processor FSB agents must receive these signals to drive their outputs and

latch their inputs.

BCLK[1:0]

Input

All external timing parameters are specified with respect to the rising edge of

BCLK0 crossing V_CROSS

.

66

Datasheet

Land Listing and Signal Descriptions

Table 4-3. Signal Description (Sheet 2 of 8)

Name

Type

Description

BINIT# (Bus Initialization) may be observed and driven by all processor FSB

agents and if used, must connect the appropriate pins/lands of all such agents.

If the BINIT# driver is enabled during power-on configuration, BINIT# is

asserted to signal any bus condition that prevents reliable future operation.

If BINIT# observation is enabled during power-on configuration, and BINIT# is

sampled asserted, symmetric agents reset their bus LOCK# activity and bus

request arbitration state machines. The bus agents do not reset their IOQ and

transaction tracking state machines upon observation of BINIT# activation.

Once the BINIT# assertion has been observed, the bus agents will re-arbitrate

for the FSB and attempt completion of their bus queue and IOQ entries.

Input/

Output

BINIT#

If BINIT# observation is disabled during power-on configuration, a central agent

may handle an assertion of BINIT# as appropriate to the error handling

architecture of the system.

BNR# (Block Next Request) is used to assert a bus stall by any bus agent

unable to accept new bus transactions. During a bus stall, the current bus

owner cannot issue any new transactions.

Input/

Output

BNR#

This input is required to determine whether the processor is installed in a

platform that supports the Pentium 4 processor in the 775-land package. The

processor will not operate if this signal is low. This input has a weak internal

BOOTSELECT

Input

pull-up to V_CC

.

BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor

signals. They are outputs from the processor which indicate the status of

breakpoints and programmable counters used for monitoring processor

performance. BPM[5:0]# should connect the appropriate pins/lands of all

processor FSB agents.

BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. PRDY#

is a processor output used by debug tools to determine processor debug

readiness.

Input/

Output

BPM[5:0]#

BPM5# provides PREQ# (Probe Request) functionality for the TAP port.

PREQ# is used by debug tools to request debug operation of the processor.

These signals do not have on-die termination. Refer to Section 2.5 for

termination requirements.

BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor

FSB. It must connect the appropriate pins/lands of all processor FSB agents.

Observing BPRI# active (as asserted by the priority agent) causes all other

agents to stop issuing new requests, unless such requests are part of an

ongoing locked operation. The priority agent keeps BPRI# asserted until all of

its requests are completed, then releases the bus by de-asserting BPRI#.

BPRI#

BR0#

Input

BR0# drives the BREQ0# signal in the system and is used by the processor to

request the bus. During power-on configuration this signal is sampled to

determine the agent ID = 0.

Input/

Output

This signal does not have on-die termination and must be terminated.

The BCLK[1:0] frequency select signals BSEL[2:0] are used to select the

processor input clock frequency. Table 2-6 defines the possible combinations of

the signals and the frequency associated with each combination. The required

frequency is determined by the processor, chipset and clock synthesizer. All

agents must operate at the same frequency. For more information about these

signals, including termination recommendations refer to Section 2.9.

BSEL[2:0]

COMP[1:0]

Output

Analog

COMP[1:0] must be terminated to V_SSon the system board using precision

resistors.

Datasheet

67

Land Listing and Signal Descriptions

Table 4-3. Signal Description (Sheet 3 of 8)

Name

Type

Description

D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path

between the processor FSB agents, and must connect the appropriate pins/

lands on all such agents. The data driver asserts DRDY# to indicate a valid data

transfer.

D[63:0]# are quad-pumped signals and will, thus, be driven four times in a

common clock period. D[63:0]# are latched off the falling edge of both

DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a

pair of one DSTBP# and one DSTBN#. The following table shows the grouping

of data signals to data strobes and DBI#.

Quad-Pumped Signal Groups

DSTBN#/

Input/

Output

D[63:0]#

Data Group

DBI#

DSTBP#

D[15:0]#

D[31:16]#

D[47:32]#

D[63:48]#

0

1

2

3

0

1

2

3

Furthermore, the DBI# signals determine the polarity of the data signals. Each

group of 16 data signals corresponds to one DBI# signal. When the DBI# signal

is active, the corresponding data group is inverted and therefore sampled active

high.

DBI[3:0]# (Data Bus Inversion) are source synchronous and indicate the

polarity of the D[63:0]# signals.The DBI[3:0]# signals are activated when the

data on the data bus is inverted. If more than half the data bits, within a 16-bit

group, would have been asserted electrically low, the bus agent may invert the

data bus signals for that particular sub-phase for that 16-bit group.

DBI[3:0] Assignment To Data Bus

Input/

Output

DBI[3:0]#

Bus Signal

Data Bus Signals

DBI3#

DBI2#

DBI1#

DBI0#

D[63:48]#

D[47:32]#

D[31:16]#

D[15:0]#

DBR# (Debug Reset) is used only in processor systems where no debug port is

implemented on the system board. DBR# is used by a debug port interposer so

DBR#

Output that an in-target probe can drive system reset. If a debug port is implemented in

the system, DBR# is a no connect in the system. DBR# is not a processor

signal.

DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on

Input/ the processor FSB to indicate that the data bus is in use. The data bus is

Output released after DBSY# is de-asserted. This signal must connect the appropriate

pins/lands on all processor FSB agents.

DBSY#

DEFER# is asserted by an agent to indicate that a transaction cannot be

guaranteed in-order completion. Assertion of DEFER# is normally the

responsibility of the addressed memory or input/output agent. This signal must

connect the appropriate pins/lands of all processor FSB agents.

DEFER#

DP[3:0]#

Input

DP[3:0]# (Data parity) provide parity protection for the D[63:0]# signals. They

are driven by the agent responsible for driving D[63:0]#, and must connect the

appropriate pins/lands of all processor FSB agents.

Input/

Output

68

Datasheet

Land Listing and Signal Descriptions

Table 4-3. Signal Description (Sheet 4 of 8)

Name

Type

Description

DRDY# (Data Ready) is asserted by the data driver on each data transfer,

Input/ indicating valid data on the data bus. In a multi-common clock data transfer,

Output DRDY# may be de-asserted to insert idle clocks. This signal must connect the

appropriate pins/lands of all processor FSB agents.

DRDY#

DSTBN[3:0]# are the data strobes used to latch in D[63:0]#.

Signals

Associated Strobe

D[15:0]#, DBI0#

D[31:16]#, DBI1#

D[47:32]#, DBI2#

D[63:48]#, DBI3#

DSTBN0#

DSTBN1#

DSTBN2#

DSTBN3#

Input/

Output

DSTBN[3:0]#

DSTBP[3:0]# are the data strobes used to latch in D[63:0]#.

Signals

Associated Strobe

D[15:0]#, DBI0#

D[31:16]#, DBI1#

D[47:32]#, DBI2#

D[63:48]#, DBI3#

DSTBP0#

DSTBP1#

DSTBP2#

DSTBP3#

Input/

Output

DSTBP[3:0]#

FCx

Other FC signals are signals that are available for compatibility with other processors.

FERR#/PBE# (floating point error/pending break event) is a multiplexed signal

and its meaning is qualified by STPCLK#. When STPCLK# is not asserted,

FERR#/PBE# indicates a floating-point error and will be asserted when the

processor detects an unmasked floating-point error. When STPCLK# is not

asserted, FERR#/PBE# is similar to the ERROR# signal on the Intel 387

coprocessor, and is included for compatibility with systems using MS-DOS*-

type floating-point error reporting. When STPCLK# is asserted, an assertion of

FERR#/PBE# indicates that the processor has a pending break event waiting

FERR#/PBE#

Output

for service. The assertion of FERR#/PBE# indicates that the processor should

be returned to the Normal state. For additional information on the pending break

event functionality, including the identification of support of the feature and

enable/disable information, refer to volume 3 of the Intel Architecture Software

Developer's Manual and the Intel Processor Identification and the CPUID

Instruction application note.

GTLREF determines the signal reference level for GTL+ input signals. GTLREF

Input

GTLREF

is used by the GTL+ receivers to determine if a signal is a logical 0 or logical 1.

GTLREF_SEL

Output GTLREF_SEL is used to select the appropriate chipset GTLREF voltage.

Input/

Output

HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation

results. Any FSB agent may assert both HIT# and HITM# together to indicate

that it requires a snoop stall, which can be continued by reasserting HIT# and

HITM# together.

HIT#

HITM#

Input/

Output

IERR# (Internal Error) is asserted by a processor as the result of an internal

error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction

on the processor FSB. This transaction may optionally be converted to an

external error signal (e.g., NMI) by system core logic. The processor will keep

IERR# asserted until the assertion of RESET#.

IERR#

Output

This signal does not have on-die termination. Refer to Section 2.5 for

termination requirements.

Datasheet

69

Land Listing and Signal Descriptions

Table 4-3. Signal Description (Sheet 5 of 8)

Name

Type

Description

IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a

numeric error and continue to execute noncontrol floating-point instructions. If

IGNNE# is de-asserted, the processor generates an exception on a noncontrol

floating-point instruction if a previous floating-point instruction caused an error.

IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.

IGNNE#

Input

IGNNE# is an asynchronous signal. However, to ensure recognition of this

signal following an Input/Output write instruction, it must be valid along with the

TRDY# assertion of the corresponding Input/Output Write bus transaction.

INIT# (Initialization), when asserted, resets integer registers inside the

processor without affecting its internal caches or floating-point registers. The

processor then begins execution at the power-on Reset vector configured

during power-on configuration. The processor continues to handle snoop

requests during INIT# assertion. INIT# is an asynchronous signal and must

connect the appropriate pins/lands of all processor FSB agents.

INIT#

Input

If INIT# is sampled active on the active to inactive transition of RESET#, then

the processor executes its Built-in Self-Test (BIST).

ITP_CLK[1:0] are copies of BCLK that are used only in processor systems

where no debug port is implemented on the system board. ITP_CLK[1:0] are

used as BCLK[1:0] references for a debug port implemented on an interposer. If

a debug port is implemented in the system, ITP_CLK[1:0] are no connects in

the system. These are not processor signals.

ITP_CLK[1:0]

LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins/lands of all

APIC Bus agents. When the APIC is disabled, the LINT0 signal becomes INTR,

a maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable

interrupt. INTR and NMI are backward compatible with the signals of those

names on the Pentium processor. Both signals are asynchronous.

LINT[1:0]

Input

Both of these signals must be software configured via BIOS programming of the

APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the

APIC is enabled by default after Reset, operation of these signals as LINT[1:0]

is the default configuration.

The LL_ID[1:0] signals are used to select the correct loadline slope for the

LL_ID[1:0]

LOCK#

Output processor. LL_ID[1:0] = 00 for the Pentium 4 processor in the 775-land

package.

LOCK# indicates to the system that a transaction must occur atomically. This

signal must connect the appropriate pins/lands of all processor FSB agents. For

a locked sequence of transactions, LOCK# is asserted from the beginning of

the first transaction to the end of the last transaction.

Input/

Output

When the priority agent asserts BPRI# to arbitrate for ownership of the

processor FSB, it will wait until it observes LOCK# de-asserted. This enables

symmetric agents to retain ownership of the processor FSB throughout the bus

locked operation and ensure the atomicity of lock.

MCERR# (Machine Check Error) is asserted to indicate an unrecoverable error

without a bus protocol violation. It may be driven by all processor FSB agents.

MCERR# assertion conditions are configurable at a system level. Assertion

options are defined by the following options:

•

Enabled or disabled.

Input/

Output

MCERR#

MSID[1:0]

Asserted, if configured, for internal errors along with IERR#.

Asserted, if configured, by the request initiator of a bus transaction after it

observes an error.

•

Asserted by any bus agent when it observes an error in a bus transaction.

For more details regarding machine check architecture, refer to the IA-32

Software Developer’s Manual, Volume 3: System Programming Guide.

MSID[1:0] are provided to indicate the market segment for the processor and

may be used for future processor compatibility or for keying.

Output

70

Datasheet

Land Listing and Signal Descriptions

Table 4-3. Signal Description (Sheet 6 of 8)

Name

Type

Description

As an output, PROCHOT# (Processor Hot) will go active when the processor

temperature monitoring sensor detects that the processor has reached its

maximum safe operating temperature. This indicates that the processor

Thermal Control Circuit (TCC) has been activated, if enabled. As an input,

assertion of PROCHOT# by the system will activate the TCC, if enabled. The

TCC will remain active until the system de-asserts PROCHOT#. See

Section 5.2.4 for more details.

Input/

Output

PROCHOT#

PWRGOOD (Power Good) is a processor input. The processor requires this

signal to be a clean indication that the clocks and power supplies are stable and

within their specifications. ‘Clean’ implies that the signal will remain low

(capable of sinking leakage current), without glitches, from the time that the

power supplies are turned on until they come within specification. The signal

must then transition monotonically to a high state. PWRGOOD can be driven

inactive at any time, but clocks and power must again be stable before a

subsequent rising edge of PWRGOOD. The PWRGOOD signal must be

supplied to the processor; it is used to protect internal circuits against voltage

sequencing issues. It should be driven high throughout boundary scan

operation.

PWRGOOD

Input

REQ[4:0]# (Request Command) must connect the appropriate pins/lands of all

processor FSB agents. They are asserted by the current bus owner to define

the currently active transaction type. These signals are source synchronous to

ADSTB0#. Refer to the AP[1:0]# signal description for a details on parity

checking of these signals.

Input/

Output

REQ[4:0]#

Asserting the RESET# signal resets the processor to a known state and

invalidates its internal caches without writing back any of their contents. For a

power-on Reset, RESET# must stay active for at least one millisecond after

V

_CCand BCLK have reached their proper specifications. On observing active

RESET#, all FSB agents will de-assert their outputs within two clocks. RESET#

must not be kept asserted for more than 10 ms while PWRGOOD is asserted.

RESET#

Input

A number of bus signals are sampled at the active-to-inactive transition of

RESET# for power-on configuration. These configuration options are described

in the Section 6.1.

This signal does not have on-die termination and must be terminated on the

system board.

RS[2:0]# (Response Status) are driven by the response agent (the agent

responsible for completion of the current transaction), and must connect the

appropriate pins/lands of all processor FSB agents.

RS[2:0]#

RSP#

Input

RSP# (Response Parity) is driven by the response agent (the agent responsible

for completion of the current transaction) during assertion of RS[2:0]#, the

signals for which RSP# provides parity protection. It must connect to the

appropriate pins/lands of all processor FSB agents.

A correct parity signal is high if an even number of covered signals are low and

low if an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is

also high, since this indicates it is not being driven by any agent guaranteeing

correct parity.

SKTOCC# (Socket Occupied) will be pulled to ground by the processor. System

board designers may use this signal to determine if the processor is present.

SKTOCC#

SMI#

Output

Input

SMI# (System Management Interrupt) is asserted asynchronously by system

logic. On accepting a System Management Interrupt, the processor saves the

current state and enter System Management Mode (SMM). An SMI

Acknowledge transaction is issued, and the processor begins program

execution from the SMM handler.

If SMI# is asserted during the de-assertion of RESET#, the processor will tri-

state its outputs.

Datasheet

71

Land Listing and Signal Descriptions

Table 4-3. Signal Description (Sheet 7 of 8)

Name

Type

Description

STPCLK# (Stop Clock), when asserted, causes the processor to enter a low

power Stop-Grant state. The processor issues a Stop-Grant Acknowledge

transaction, and stops providing internal clock signals to all processor core units

except the FSB and APIC units. The processor continues to snoop bus

transactions and service interrupts while in Stop-Grant state. When STPCLK# is

de-asserted, the processor restarts its internal clock to all units and resumes

execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK#

is an asynchronous input.

STPCLK#

Input

TCK (Test Clock) provides the clock input for the processor Test Bus (also

known as the Test Access Port).

TCK

TDI

Input

TDI (Test Data In) transfers serial test data into the processor. TDI provides the

serial input needed for JTAG specification support.

TDO (Test Data Out) transfers serial test data out of the processor. TDO

provides the serial output needed for JTAG specification support.

TDO

Output

TESTHI[13:0] must be connected to the processor’s appropriate power source

(refer to VTT_OUT_LEFT and VTT_OUT_RIGHT signal description) through a

resistor for proper processor operation. See Section 2.5 for more details.

TESTHI[13:0]

Input

THERMDA

THERMDC

Other Thermal Diode Anode. See Section 5.2.7.

Other Thermal Diode Cathode. See Section 5.2.7.

In the event of a catastrophic cooling failure, the processor will automatically

shut down when the silicon has reached a temperature approximately 20 °C

above the maximum T_C. Assertion of THERMTRIP# (Thermal Trip) indicates the

processor junction temperature has reached a level beyond where permanent

silicon damage may occur. Upon assertion of THERMTRIP#, the processor will

shut off its internal clocks (thus, halting program execution) in an attempt to

reduce the processor junction temperature. To protect the processor, its core

Output voltage (V_CC) must be removed following the assertion of THERMTRIP#.

Driving of the THERMTRIP# signal is enabled within 10 µs of the assertion of

PWRGOOD and is disabled on de-assertion of PWRGOOD. Once activated,

THERMTRIP# remains latched until PWRGOOD is de-asserted. While the de-

assertion of the PWRGOOD signal will de-assert THERMTRIP#, if the

processor’s junction temperature remains at or above the trip level,

THERMTRIP# will again be asserted within 10 µs of the assertion of

PWRGOOD.

THERMTRIP#

TMS (Test Mode Select) is a JTAG specification support signal used by debug

TMS

Input

tools.

TRDY# (Target Ready) is asserted by the target to indicate that it is ready to

TRDY#

Input

receive a write or implicit writeback data transfer. TRDY# must connect the

appropriate pins/lands of all FSB agents.

TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be

driven low during power on Reset.

TRST#

VCC

Input

VCC are the power pins for the processor. The voltage supplied to these pins is

determined by the VID[5:0] pins.

VCCA

Input

VCCA provides isolated power for the internal processor core PLLs.

VCCIOPLL provides isolated power for internal processor FSB PLLs.

VCC_SENSE is an isolated low impedance connection to processor core power

VCCIOPLL

VCC_SENSE

Output (V_CC). It can be used to sense or measure voltage near the silicon with little

noise.

This land is provided as a voltage regulator feedback sense point for V_CC. It is

connected internally in the processor package to the sense point land U27 as

described in the Voltage Regulator-Down (VRD) 10.1 Design Guide for Desktop

VCC_MB_

REGULATION

Output

Socket 775.

72

Datasheet

Land Listing and Signal Descriptions

Table 4-3. Signal Description (Sheet 8 of 8)

Name

Type

Description

VID[5:0] (Voltage ID) signals are used to support automatic selection of power

supply voltages (V_CC). These are open drain signals that are driven by the

processor and must be pulled up on the motherboard. Refer to the Voltage

Regulator-Down (VRD) 10.1 Design Guide for Desktop Socket 775 for more

information. The voltage supply for these signals must be valid before the VR

can supply V_CCto the processor. Conversely, the VR output must be disabled

until the voltage supply for the VID signals becomes valid. The VID signals are

needed to support the processor voltage specification variations. See Table 2-2

for definitions of these signals. The VR must supply the voltage that is

requested by the signals, or disable itself.

VID[5:0]

Output

VSS are the ground pins for the processor and should be connected to the

system ground plane.

VSS

Input

VSSA

VSSA is the isolated ground for internal PLLs.

VSS_SENSE is an isolated low impedance connection to processor core V_SS. It

can be used to sense or measure ground near the silicon with little noise.

VSS_SENSE

Output

This land is provided as a voltage regulator feedback sense point for V_SS. It is

connected internally in the processor package to the sense point land V27 as

described in the Voltage Regulator-Down (VRD) 10.1 Design Guide for Desktop

Socket 775.

VSS_MB_

REGULATION

Output

VTT

Miscellaneous voltage supply.

The VTT_OUT_LEFT and VTT_OUT_RIGHT signals are included to provide a

voltage supply for some signals that require termination to V_TTon the

motherboard.

For future processor compatibility some signals are required to be pulled up to

VTT_OUT_LEFT or VTT_OUT_RIGHT. Refer to the following table for the

signals that should be pulled up to VTT_OUT_LEFT and VTT_OUT_RIGHT.

VTT_OUT_LEFT

VTT_OUT_RIGHT

Output

Pull-up Signal

Signals to be Pulled Up

VTT_PWRGOOD, VID[5:0], GTLREF, TMS, TDI,

TDO, BPM[5:0], other VRD components

VTT_OUT_RIGHT

RESET#, BR0#, PWRGOOD, TESTHI1, TESTHI8,

TESTHI9, TESTHI10, TESTHI11, TESTHI12

VTT_OUT_LEFT

The VTT_SEL signal is used to select the correct V_TTvoltage level for the

processor.

VTT_SEL

Output

Input

The processor requires this input to determine that the V_TTvoltages are stable

and within specification.

VTTPWRGD

§

Datasheet

73

Land Listing and Signal Descriptions

74

Datasheet

Thermal Specifications and Design Considerations

5 Thermal Specifications and

Design Considerations

5.1

Processor Thermal Specifications

The Pentium 4 processor in the 775-land package requires a thermal solution to maintain

temperatures within operating limits as set forth in Section 5.1.1. Any attempt to operate the

processor outside these operating limits may result in permanent damage to the processor and

potentially other components within the system. As processor technology changes, thermal

management becomes increasingly crucial when building computer systems. Maintaining the

proper thermal environment is key to reliable, long-term system operation.

A complete thermal solution includes both component and system level thermal management

features. Component level thermal solutions can include active or passive heatsinks attached to the

processor Integrated Heat Spreader (IHS). Typical system level thermal solutions may consist of

system fans combined with ducting and venting.

®

For more information on designing a component level thermal solution, refer to the Intel

®

Pentium 4 Processor on 90 nm Process in the 775-Land Package Thermal Design Guidelines.

Note: The boxed processor will ship with a component thermal solution. Refer to Chapter 7 for details on

the boxed processor.

5.1.1

Thermal Specifications

To allow for the optimal operation and long-term reliability of Intel processor-based systems, the

system/processor thermal solution should be designed such that the processor remains within the

minimum and maximum case temperature (T ) specifications when operating at or below the

C

Thermal Design Power (TDP) value listed per frequency in Table 5-1. Thermal solutions not

designed to provide this level of thermal capability may affect the long-term reliability of the

processor and system. For more details on thermal solution design, refer to the appropriate

processor thermal design guidelines.

The Pentium 4 processor in the 775-land package introduces a new methodology for managing

processor temperatures which is intended to support acoustic noise reduction through fan speed

control. Selection of the appropriate fan speed will be based on the temperature reported by the

processor’s thermal diode. If the diode temperature is greater than or equal to T

, the

CONTROL

processor case temperature must remain at or below the temperature as specified by the thermal

profile. If the diode temperature is less than T then the case temperature is permitted to

CONTROL

exceed the thermal profile, but the diode temperature must remain at or below T

. Systems

CONTROL

that implement fan speed control must be designed to take these conditions into account. Systems

that do not alter the fan speed only need to guarantee the case temperature meets the thermal profile

specifications.

To determine a processor's case temperature specification based on the thermal profile, it is

necessary to accurately measure processor power dissipation.

Datasheet

75

Thermal Specifications and Design Considerations

The case temperature is defined at the geometric top center of the processor IHS. Analysis indicates

that real applications are unlikely to cause the processor to consume maximum power dissipation for

sustained periods of time. Intel recommends that complete thermal solution designs target the

Thermal Design Power (TDP) indicated in Table 5-1 instead of the maximum processor power

consumption. The Thermal Monitor feature is intended to help protect the processor in the unlikely

event that an application exceeds the TDP recommendation for a sustained period of time. For more

details on the usage of this feature, refer to Section 5.2. In all cases, the Thermal Monitor feature

must be enabled for the processor to remain within specification.

Table 5-1. Processor Thermal Specifications

Processor

Number

Core Frequency

(GHz)

Thermal Design Minimum T_C

Maximum T_C(°C)

Notes

Power (W)

(°C)

1, 2

520/521

530/531

540/541

550/551

550

2.80 (PRB = 0)

3 (PRB = 0)

84

5

See Table 5-3 and Figure 5-2

See Table 5-2 and Figure 5-1

3.20 (PRB = 0)

3.40 (PRB = 0)

3.40 (PRB = 1)

3.60 (PRB = 1)

3.80 (PRB = 1)

84

115

560/561

570/571

NOTES:

1.

Thermal Design Power (TDP) should be used for processor thermal solution design targets. The TDP is not the maximum pow-

er that the processor can dissipate.

2.

This table shows the maximum TDP for a given frequency range. Individual processors may have a lower TDP. Therefore, the

maximum T will vary depending on the TDP of the individual processor. Refer to thermal profile figure and associated table

C

for the allowed combinations of power and T .

C

76

Datasheet

Thermal Specifications and Design Considerations

Table 5-2. Thermal Profile for Processors with PRB = 1

Power

(W)

Maximum T_C

(°C)

Power

(W)

Maximum T_C

(°C)

Power

(W)

Maximum T_C

(°C)

Power

(W)

Maximum T_C

(°C)

0

44.0

44.5

45.0

45.5

46.0

46.5

47.0

47.5

48.0

48.5

49.0

49.5

50.0

50.5

51.0

30

32

34

36

38

40

42

44

46

48

50

52

54

56

58

51.5

52.0

52.5

53.0

53.5

54.0

54.5

55.0

55.5

56.0

56.5

57.0

57.5

58.0

58.5

60

62

64

66

68

70

72

74

76

78

80

82

84

86

88

59.0

59.5

60.0

60.5

61.0

61.5

62.0

62.5

63.0

63.5

64.0

64.5

65.0

65.5

66.0

90

92

66.5

67.0

67.5

68.0

68.5

69.0

69.5

70.0

70.5

71.0

71.5

72.0

72.5

72.8

2

4

94

6

96

8

98

10

12

14

16

18

20

22

24

26

28

100

102

104

106

108

110

112

114

115

Figure 5-1. Thermal Profile for Processors with PRB = 1

75.0

70.0

65.0

60.0

55.0

50.0

45.0

40.0

y = 0.25x + 44

0

10

20

30

40

50

60

70

80

90

100

110

Power (W)

Datasheet

77

Thermal Specifications and Design Considerations

Table 5-3. Thermal Profile for Processors with PRB = 0

Power

(W)

Maximum Tc

(°C)

Power

(W)

Maximum Tc

(°C)

Power

(W)

Maximum Tc

(°C)

0

44.2

44.8

45.3

45.9

46.4

47.0

47.6

48.1

48.7

49.2

49.8

50.4

50.9

51.5

52.0

30

32

34

36

38

40

42

44

46

48

50

52

54

56

58

52.6

53.2

53.7

54.3

54.8

55.4

56.0

56.5

57.1

57.6

58.2

58.8

59.3

59.9

60.4

60

62

64

66

68

70

72

74

76

78

80

82

84

61.0

61.6

62.1

62.7

63.2

63.8

64.4

64.9

65.5

66.0

66.6

67.2

67.7

2

4

6

8

10

12

14

16

18

20

22

24

26

28

Figure 5-2. Thermal Profile for Processors with PRB = 0

70.0

65.0

60.0

55.0

50.0

45.0

40.0

y = 0.28x + 44.2

0

10

20

30

40

50

60

70

80

Power (W)

78

Datasheet

Thermal Specifications and Design Considerations

5.1.2

Thermal Metrology

The maximum and minimum case temperatures (T ) are specified in Table 5-1. These temperature

C

specifications are meant to help ensure proper operation of the processor. Figure 5-3 illustrates

where Intel recommends T thermal measurements should be made. For detailed guidelines on

C

®

temperature measurement methodology, refer to the Intel Pentium 4 Processor on 90 nm

Process in the 775-Land Package Thermal Design Guidelines.

Figure 5-3. Case Temperature (T ) Measurement Location

C

Measure T_Cat this point

(geometric center of the package)

37.5 mm

5.2

Processor Thermal Features

5.2.1

Thermal Monitor

The Thermal Monitor feature helps control the processor temperature by activating the TCC when

the processor silicon reaches its maximum operating temperature. The TCC reduces processor

power consumption as needed by modulating (starting and stopping) the internal processor core

clocks. The Thermal Monitor feature must be enabled for the processor to be operating

within specifications. The temperature at which Thermal Monitor activates the thermal control

circuit is not user configurable and is not software visible. Bus traffic is snooped in the normal

manner, and interrupt requests are latched (and serviced during the time that the clocks are on)

while the TCC is active.

When the Thermal Monitor feature is enabled, and a high temperature situation exists (i.e., TCC is

active), the clocks will be modulated by alternately turning the clocks off and on at a duty cycle

specific to the processor (typically 30–50%). Clocks often will not be off for more than

3.0 microseconds when the TCC is active. Cycle times are processor speed dependent and will

decrease as processor core frequencies increase. A small amount of hysteresis has been included to

prevent rapid active/inactive transitions of the TCC when the processor temperature is near its

maximum operating temperature. Once the temperature has dropped below the maximum

operating temperature, and the hysteresis timer has expired, the TCC goes inactive and clock

modulation ceases.

Datasheet

79

Thermal Specifications and Design Considerations

With a properly designed and characterized thermal solution, it is anticipated that the TCC would

only be activated for very short periods of time when running the most power intensive

applications. The processor performance impact due to these brief periods of TCC activation is

expected to be so minor that it would be immeasurable. An under-designed thermal solution that is

not able to prevent excessive activation of the TCC in the anticipated ambient environment may

cause a noticeable performance loss, and in some cases may result in a T_Cthat exceeds the

specified maximum temperature and may affect the long-term reliability of the processor. In

addition, a thermal solution that is significantly under-designed may not be capable of cooling the

®

processor even when the TCC is active continuously. Refer to the Intel Pentium 4 Processor on

90 nm Process in the 775-Land Package Thermal Design Guidelines for information on designing

a thermal solution.

The duty cycle for the TCC, when activated by the Thermal Monitor, is factory configured and

cannot be modified. The Thermal Monitor does not require any additional hardware, software

drivers, or interrupt handling routines.

5.2.2

Thermal Monitor 2

The Pentium 4 processor in the 775-land package also supports a power management capability

known as Thermal Monitor 2. This mechanism provides an efficient mechanism for limiting the

processor temperature by reducing power consumption within the processor.

When Thermal Monitor 2 is enabled, and a high temperature situation is detected, the enhanced

Thermal Control Circuit (TCC) will be activated. This enhanced TCC causes the processor to

adjust its operating frequency (bus multiplier) and input voltage (VID). This combination of

reduced frequency and VID results in a decrease in processor power consumption.

A processor enabled for Thermal Monitor 2 includes two operating points, each consisting of a

specific operating frequency and voltage. The first point represents the normal operating conditions

for the processor.

The second point consists of both a lower operating frequency and voltage. When the enhanced

TCC is activated, the processor automatically transitions to the new frequency. This transition

occurs very rapidly (on the order of 5 µs). During the frequency transition, the processor is unable

to service any bus requests, and consequently, all bus traffic is blocked. Edge-triggered interrupts

will be latched and kept pending until the processor resumes operation at the new frequency.

Once the new operating frequency is engaged, the processor will transition to the new core

operating voltage by issuing a new VID code to the voltage regulator. The voltage regulator must

support VID transitions in order to support Thermal Monitor 2. During the voltage change, it will

be necessary to transition through multiple VID codes to reach the target operating voltage. Each

step will be one VID table entry (i.e., 12.5 mV steps). The processor continues to execute

instructions during the voltage transition. Operation at this lower voltage reduces both the dynamic

and leakage power consumption of the processor, providing a reduction in power consumption at a

minimum performance impact.

Once the processor has sufficiently cooled, and a minimum activation time has expired, the

operating frequency and voltage transition back to the normal system operating point. Transition of

the VID code will occur first, to insure proper operation once the processor reaches its normal

operating frequency. Refer to Figure 5-4 for an illustration of this ordering.

80

Datasheet

Thermal Specifications and Design Considerations

Figure 5-4. Thermal Monitor 2 Frequency and Voltage Ordering

T_TM2

Temperature

Frequency

f_MAX

f_TM2

VID

VID_TM2

VID

PROCHOT#

Time

The PROCHOT# signal is asserted when a high temperature situation is detected, regardless of

whether or not Thermal Monitor or Thermal Monitor 2 is enabled.

It should be noted that the Thermal Monitor 2 TCC can not be activated via the on demand mode.

The Thermal Monitor TCC, however, can be activated through the use of the on demand mode.

5.2.3

On-Demand Mode

The Pentium 4 processor in the 775-land package provides an auxiliary mechanism that allows

system software to force the processor to reduce its power consumption. This mechanism is

referred to as "On-Demand" mode and is distinct from the Thermal Monitor feature. On-Demand

mode is intended as a means to reduce system level power consumption. Systems using the

Pentium 4 processor in the 775-land package must not rely on software usage of this mechanism to

limit the processor temperature.

If bit 4 of the ACPI P_CNT Control Register (located in the processor IA32_THERM_CONTROL

MSR) is written to a '1', the processor will immediately reduce its power consumption via

modulation (starting and stopping) of the internal core clock, independent of the processor

temperature. When using On-Demand mode, the duty cycle of the clock modulation is

programmable via bits 3:1 of the same ACPI P_CNT Control Register. In On-Demand mode, the

duty cycle can be programmed from 12.5% on/ 87.5% off, to 87.5% on/12.5% off in 12.5%

increments. On-Demand mode may be used in conjunction with the Thermal Monitor. If the system

tries to enable On-Demand mode at the same time the TCC is engaged, the factory configured duty

cycle of the TCC will override the duty cycle selected by the On-Demand mode.

Datasheet

81

Thermal Specifications and Design Considerations

5.2.4

PROCHOT# Signal

An external signal, PROCHOT# (processor hot), is asserted when the processor die temperature

has reached its maximum operating temperature. If the Thermal Monitor is enabled (note that the

Thermal Monitor must be enabled for the processor to be operating within specification), the TCC

will be active when PROCHOT# is asserted. The processor can be configured to generate an

interrupt upon the assertion or de-assertion of PROCHOT#. Refer to the Intel Architecture

Software Developer's Manuals for specific register and programming details.

The Pentium 4 processor in the 775-land package implements a bi-directional PROCHOT#

capability to allow system designs to protect various components from over-temperature situations.

The PROCHOT# signal is bi-directional in that it can either signal when the processor has reached

its maximum operating temperature or be driven from an external source to activate the TCC. The

ability to activate the TCC via PROCHOT# can provide a means for thermal protection of system

components.

One application is the thermal protection of voltage regulators (VR). System designers can create a

circuit to monitor the VR temperature and activate the TCC when the temperature limit of the VR

is reached. By asserting PROCHOT# (pulled-low) and activating the TCC, the VR can cool down

as a result of reduced processor power consumption. Bi-directional PROCHOT# can allow VR

thermal designs to target maximum sustained current instead of maximum current. Systems should

still provide proper cooling for the VR, and rely on bi-directional PROCHOT# only as a backup in

case of system cooling failure. The system thermal design should allow the power delivery

circuitry to operate within its temperature specification even while the processor is operating at its

Thermal Design Power. With a properly designed and characterized thermal solution, it is

anticipated that bi-directional PROCHOT# would only be asserted for very short periods of time

when running the most power intensive applications. An under-designed thermal solution that is

not able to prevent excessive assertion of PROCHOT# in the anticipated ambient environment may

cause a noticeable performance loss. Refer to the Voltage Regulator-Down (VRD) 10.1 Design

Guide for Desktop Socket 775 for details on implementing the bi-directional PROCHOT# feature.

5.2.5

5.2.6

THERMTRIP# Signal

Regardless of whether or not the Thermal Monitor feature is enabled, in the event of a catastrophic

cooling failure, the processor will automatically shut down when the silicon has reached an

elevated temperature (refer to the THERMTRIP# definition in Table 4-3). At this point, the FSB

signal THERMTRIP# will go active and stay active as described in Table 4-3. THERMTRIP#

activation is independent of processor activity and does not generate any bus cycles.

T_CONTROLand Fan Speed Reduction

T

is a temperature specification based on a temperature reading from the thermal diode.

CONTROL

The value for T

will be calibrated in manufacturing and configured for each processor.

CONTROL

When T

is above T

, then T must be at or below T

as defined by the thermal

diode

CONTROL

C

C-MAX

profile in Table 5-2 and Figure 5-1; otherwise, the processor temperature can be maintained at

(or lower) as measured by the thermal diode.

T

CONTROL

The purpose of this feature is to support acoustic optimization through fan speed control. Contact

your Intel representative for further details and documentation.

82

Datasheet

Thermal Specifications and Design Considerations

5.2.7

Thermal Diode

The processor incorporates an on-die thermal diode. A thermal sensor located on the system board

may monitor the die temperature of the processor for thermal management/long term die

temperature change purposes. Table 5-4 and Table 5-5 provide the diode parameter and interface

specifications. This thermal diode is separate from the Thermal Monitor’s thermal sensor and

cannot be used to predict the behavior of the Thermal Monitor.

Table 5-4. Thermal Diode Parameters

Symbol

I_FW

Parameter

Forward Bias Current

Min

Typ

Max

Unit

Notes

1

11

187

µA

2, 3, 4, 5

2, 3, 6

n

R_T

Diode Ideality Factor

Series Resistance

1.0083

3.242

1.011

3.33

1.023

3.594

Ω

NOTES:

1.

2.

3.

4.

Intel does not support or recommend operation of the thermal diode under reverse bias.

Characterized at 75 °C.

Not 100% tested. Specified by design characterization.

The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode equation:

I_FW= I_S* (e ^{qV /nkT}–1)

D

where I_S= saturation current, q = electronic charge, V_D= voltage across the diode, k = Boltzmann

Constant, and T = absolute temperature (Kelvin).

5.

6.

Devices found to have an ideality factor of 1.0183 to 1.023 will create a temperature error approximately 2 C° higher than

the actual temperature. To minimize any potential acoustic impact of this temperature error, T

2 C° on these parts.

will be increased by

CONTROL

The series resistance, R , is provided to allow for a more accurate measurement of the thermal diode temperature. R , as

T

defined, includes the pins of the processor but does not include any socket resistance or board trace resistance between

the socket and the external remote diode thermal sensor. RT can be used by remote diode thermal sensors with automatic

series resistance cancellation to calibrate out this error term. Another application is that a temperature offset can be manu-

ally calculated and programmed into an offset register in the remote diode thermal sensors as exemplified by the equation:

T_error= [R_T* (N-1) * I_FWmin] / [nk/q * ln N]

where T_error= sensor temperature error, N = sensor current ratio, k = Boltzmann Constant, q = electronic

charge.

Table 5-5. Thermal Diode Interface

Signal Name

Land Number

Signal Description

THERMDA

THERMDC

AL1

AK1

diode anode

diode cathode

§

Datasheet

83

Thermal Specifications and Design Considerations

84

Datasheet

Features

6 Features

6.1

Power-On Configuration Options

Several configuration options can be configured by hardware. The Pentium 4 processor in the 775-

land package samples the hardware configuration at reset, on the active-to-inactive transition of

RESET#. For specifications on these options, refer to Table 6-1.

The sampled information configures the processor for subsequent operation. These configuration

options cannot be changed except by another reset. All resets reconfigure the processor; for reset

purposes, the processor does not distinguish between a "warm" reset and a "power-on" reset.

Frequency determination functionality will exist on engineering sample processors which means

that samples can run at varied frequencies. Production material will have the bus to core ratio

locked and can only be operated at the rated frequency.

Table 6-1. Power-On Configuration Option Signals

Configuration Option

Signal^{1, 2}

Output tristate

SMI#

Execute BIST

INIT#

In Order Queue pipelining (set IOQ depth to 1)

Disable MCERR# observation

Disable BINIT# observation

APIC Cluster ID (0-3)

A7#

A9#

A10#

A[12:11]#

Disable bus parking

A15#

Disable Hyper-Threading Technology

Symmetric agent arbitration ID

RESERVED

A31#

BR0#

A[6:3]#, A8#, A[14:13]#, A[16:30]#, A[32:35]#

NOTES:

1.

2.

Asserting this signal during RESET# will select the corresponding option.

Address signals not identified in this table as configuration options should not be asserted during RESET#.

6.2

Clock Control and Low Power States

The processor allows the use of AutoHALT and Stop-Grant states to reduce power consumption by

stopping the clock to internal sections of the processor, depending on each particular state. See

Figure 6-1 for a visual representation of the processor low power states.

The processor adds support for the Enhanced HALT powerdown state. Refer to Figure 6-1 and the

following sections.

Not all processors are capable of supporting the Enhanced HALT state. Refer to the Specification

Update to determine which processor stepping and frequencies will support the Enhanced HALT

state.

Datasheet

85

Features

6.2.1

Normal State

This is the normal operating state for the processor.

6.2.2

HALT and Enhanced HALT Powerdown States

The Prescott processor supports the HALT or Enhanced HALT powerdown state. The Enhanced

HALT powerdown state is configured and enabled via the BIOS.

The Enhanced HALT state is a lower power state as compared to the Stop Grant State.

If Enhanced HALT is not enabled, the default powerdown state entered will be HALT. Refer to the

sections below for details about the HALT and Enhanced HALT states.

6.2.2.1

HALT Powerdown State

HALT is a low power state entered when all the logical processors have executed the HALT or

MWAIT instructions. When one of the logical processors executes the HALT instruction, that

logical processor is halted, however, the other processor continues normal operation. The processor

will transition to the Normal state upon the occurrence of SMI#, BINIT#, INIT#, or LINT[1:0]

(NMI, INTR). RESET# will cause the processor to immediately initialize itself.

The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or

the HALT Power Down state. See the Intel Architecture Software Developer's Manual, Volume III:

System Programmer's Guide for more information.

The system can generate a STPCLK# while the processor is in the HALT Power Down state. When

the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state.

While in HALT Power Down state, the processor will process bus snoops.

6.2.2.2

Enhanced HALT Powerdown State

Enhanced HALT is a low power state entered when all logical processors have executed the HALT

or MWAIT instructions and Enhanced HALT has been enabled via the BIOS. When one of the

logical processors executes the HALT instruction, that logical processor is halted; however, the

other processor continues normal operation.

The processor will automatically transition to a lower frequency and voltage operating point before

entering the Enhanced HALT state. Note that the processor FSB frequency is not altered; only the

internal core frequency is changed. When entering the low power state, the processor will first

switch to the lower bus ratio and then transition to the lower VID.

While in Enhanced HALT state, the processor will process bus snoops.

The processor exits the Enhanced HALT state when a break event occurs. When the processor exits

the Enhanced HALT state, it will first transition the VID to the original value and then change the

bus ratio back to the original value.

86

Datasheet

Features

Figure 6-1. Processor Low Power State Machine

HALT or MWAIT Instruction and

HALT Bus Cycle Generated

Enhanced HALT or HALT State

Normal State

Normal execution

INIT#, BINIT#, INTR, NMI, SMI#,

RESET#, FSB interrupts

BCLK running

Snoops and interrupts allowed

Snoop

Event

Occurs

Snoop

Event

Serviced

STPCLK#

Asserted

STPCLK#

De-asserted

HALT Snoop State

BCLK running

Service snoops to caches

Snoop Event Occurs

Snoop Event Serviced

Stop-Grant State

Grant Snoop State

BCLK running

Snoops and interrupts allowed

Service snoops to caches

6.2.3

Stop-Grant State

When the STPCLK# signal is asserted, the Stop-Grant state of the processor is entered 20 bus

clocks after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle.

Since the GTL+ signals receive power from the FSB, these signals should not be driven (allowing

the level to return to V_TT) for minimum power drawn by the termination resistors in this state. In

addition, all other input signals on the FSB should be driven to the inactive state.

BINIT# will not be serviced while the processor is in Stop-Grant state. The event will be latched

and can be serviced by software upon exit from the Stop Grant state.

RESET# will cause the processor to immediately initialize itself, but the processor will stay in

Stop-Grant state. A transition back to the Normal state will occur with the de-assertion of the

STPCLK# signal.

A transition to the HALT/Grant Snoop state will occur when the processor detects a snoop on the

FSB (see Section 6.2.3).

While in the Stop-Grant State, SMI#, INIT#, BINIT# and LINT[1:0] will be latched by the

processor, and only serviced when the processor returns to the Normal State. Only one occurrence

of each event will be recognized upon return to the Normal state.

While in Stop-Grant state, the processor will process a FSB snoop.

Datasheet

87

Features

6.2.4

Enhanced HALT Snoop or HALT Snoop State, Grant Snoop

State

The Enhanced HALT Snoop State is used in conjunction with the new Enhanced HALT state. If

Enhanced HALT state is not enabled in the BIOS, the default Snoop State entered will be the

HALT Snoop State. Refer to the sections below for details on HALT Snoop State, Grant Snoop

State and Enhanced HALT Snoop State.

6.2.4.1

6.2.4.2

HALT Snoop State, Grant Snoop State

The processor will respond to snoop transactions on the FSB while in Stop-Grant state or in HALT

Power Down state. During a snoop transaction, the processor enters the HALT:Grant Snoop state.

The processor will stay in this state until the snoop on the FSB has been serviced (whether by the

processor or another agent on the FSB). After the snoop is serviced, the processor will return to the

Stop-Grant state or HALT Power Down state, as appropriate.

Enhanced HALT Snoop State

The Enhanced HALT Snoop State is the default Snoop State when the Enhanced HALT state is

enabled via the BIOS. The processor will remain in the lower bus ratio and VID operating point of

the Enhanced HALT state.

While in the Enhanced HALT Snoop State, snoops are handled the same way as in the HALT

Snoop State. After the snoop is serviced the processor will return to the Enhanced HALT Power

Down state.

§

88

Datasheet

Boxed Processor Specifications

7 Boxed Processor Specifications

The Pentium 4 processor on 90 nm process in the 775-land package will also be offered as a boxed

Intel processor. Boxed Intel processors are intended for system integrators who build systems from

baseboards and standard components. The boxed Pentium 4 processor in the 775-land package will

be supplied with a cooling solution. This chapter documents baseboard and system requirements

for the cooling solution that will be supplied with the boxed Pentium 4 processor in the 775-land

package. This chapter is particularly important for OEMs that manufacture baseboards for system

integrators. Unless otherwise noted, all figures in this chapter are dimensioned in millimeters and

inches [in brackets]. Figure 7-1 shows a mechanical representation of a boxed Pentium 4 processor

in the 775-land package.

Note: Drawings in this section reflect only the specifications on the boxed Intel processor product. These

dimensions should not be used as a generic keep-out zone for all cooling solutions. It is the system

designers’ responsibility to consider their proprietary cooling solution when designing to the

®

required keep-out zone on their system platforms and chassis. Refer to the Intel Pentium 4

Processor on 90 nm Process in the 775-Land Package Thermal Design Guidelines for further

guidance. Contact your local Intel Sales Representative for this document.

Figure 7-1. Mechanical Representation of the Boxed Processor

NOTE: The airflow of the fan heatsink is into the center and out of the sides of the fan heatsink.

Datasheet

89

Boxed Processor Specifications

7.1

Mechanical Specifications

7.1.1

Boxed Processor Cooling Solution Dimensions

This section documents the mechanical specifications of the boxed Pentium 4 processor on 90 nm

process in the 775-land package. The boxed processor will be shipped with an unattached fan

heatsink. Figure 7-1 shows a mechanical representation of the boxed Pentium 4 processor in the

775-land package.

Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling. The

physical space requirements and dimensions for the boxed processor with assembled fan heatsink

are shown in Figure 7-2 (side view), and Figure 7-3 (top view). The airspace requirements for the

boxed processor fan heatsink must also be incorporated into new baseboard and system designs.

Airspace requirements are shown in Figure 7-7 and Figure 7-8. Note that some figures have

centerlines shown (marked with alphabetic designations) to clarify relative dimensioning.

Figure 7-2. Space Requirements for the Boxed Processor (Side View)

3.74

[95.0]

3.2

[81.3]

0.98

0.39

[25.0]

[10.0]

Figure 7-3. Space Requirements for the Boxed Processor (Top View)

3.74

[95.0]

3.74

[95.0]

NOTES:

1. Diagram does not show the attached hardware for the clip design and is provided only as a mechanical

representation.

90

Datasheet

Boxed Processor Specifications

Figure 7-4. Space Requirements for the Boxed Processor (Overall View)

7.1.2

7.1.3

Boxed Processor Fan Heatsink Weight

The boxed processor fan heatsink will not weigh more than 450 grams. See Chapter 5 and the

®

Intel Pentium 4 Processor on 90 nm Process in the 775-Land Package Thermal Design

Guidelines for details on the processor weight and heatsink requirements.

Boxed Processor Retention Mechanism and Heatsink

Attach Clip Assembly

The boxed processor thermal solution requires a heatsink attach clip assembly, to secure the

processor and fan heatsink in the baseboard socket. The boxed processor will ship with the heatsink

attach clip assembly.

7.2

Electrical Requirements

7.2.1

Fan Heatsink Power Supply

The boxed processor's fan heatsink requires a +12 V power supply. A fan power cable will be

shipped with the boxed processor to draw power from a power header on the baseboard. The power

cable connector and pinout are shown in Figure 7-5. Baseboards must provide a matched power

header to support the boxed processor. Table 7-1 contains specifications for the input and output

signals at the fan heatsink connector.

Datasheet

91

Boxed Processor Specifications

The fan heatsink outputs a SENSE signal that is an open-collector output that pulses at a rate of

2 pulses per fan revolution. A baseboard pull-up resistor provides V to match the system board-

OH

mounted fan speed monitor requirements, if applicable. Use of the SENSE signal is optional. If the

SENSE signal is not used, pin 3 of the connector should be tied to GND.

The fan heatsink receives a PWM signal from the motherboard from the 4th pin of the connector

labeled as CONTROL.

The boxed processor's fan heatsink requires a constant +12 V supplied to pin 2 and does not

support variable voltage control or 3-pin PWM control.

The power header on the baseboard must be positioned to allow the fan heatsink power cable to

reach it. The power header identification and location should be documented in the platform

documentation, or on the system board itself. Figure 7-6 shows the location of the fan power

connector relative to the processor socket. The baseboard power header should be positioned

within 110 mm [4.33 inches] from the center of the processor socket.

Figure 7-5. Boxed Processor Fan Heatsink Power Cable Connector Description

Signal

Straight square pin, 4-pin terminal housing with

polarizing ribs and friction locking ramp.

1

2

3

4

GND

+12 V

0.100" pitch, 0.025" square pin width.

SENSE

CONTROL

Match with straight pin, friction lock header on

mainboard.

3 4

1 2

Boxed_Proc_PwrCable

Table 7-1. Fan Heatsink Power and Signal Specifications

Description

Min

Typ

Max

Unit

Notes

+12 V: 12 volt fan power supply

10.2

12

13.8

V

-

IC:

Peak Fan current draw

Fan start-up current draw

Fan start-up current draw maximum duration

1.1

—

1.5

2.2

1.0

A

—

-

—

Second

pulses per fan

revolution

1

SENSE: SENSE frequency

—

2

—

2, 3

CONTROL

21

25

28

kHz

NOTES:

1.

2.

3.

Baseboard should pull this pin up to 5V with a resistor.

Open drain type, pulse width modulated.

Fan will have pull-up resistor to 4.75 V maximum of 5.25 V.

92

Datasheet

Boxed Processor Specifications

Figure 7-6. Baseboard Power Header Placement Relative to Processor Socket

R4.33

[110]

B

C

7.3

Thermal Specifications

This section describes the cooling requirements of the fan heatsink solution used by the boxed

processor.

7.3.1

Boxed Processor Cooling Requirements

The boxed processor may be directly cooled with a fan heatsink. However, meeting the processor's

temperature specification is also a function of the thermal design of the entire system, and

ultimately the responsibility of the system integrator. The processor temperature specification is in

Chapter 5. The boxed processor fan heatsink is able to keep the processor temperature within the

specifications (see Table 5-1) in chassis that provide good thermal management. For the boxed

processor fan heatsink to operate properly, it is critical that the airflow provided to the fan heatsink

is unimpeded. Airflow of the fan heatsink is into the center and out of the sides of the fan heatsink.

Airspace is required around the fan to ensure that the airflow through the fan heatsink is not

blocked. Blocking the airflow to the fan heatsink reduces the cooling efficiency and decreases fan

life. Figure 7-7 and Figure 7-8 illustrate an acceptable airspace clearance for the fan heatsink. The

air temperature entering the fan should be kept below 38 ºC. Again, meeting the processor's

temperature specification is the responsibility of the system integrator.

Datasheet

93

Boxed Processor Specifications

Figure 7-7. Boxed Processor Fan Heatsink Airspace Keepout Requirements (Top View)

Figure 7-8. Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side View)

94

Datasheet

Boxed Processor Specifications

7.3.2

Variable Speed Fan

If the boxed processor fan heatsink 4-pin connector is connected to a 3-pin motherboard header it

will operate as follows:

The boxed processor fan will operate at different speeds over a short range of internal chassis

temperatures. This allows the processor fan to operate at a lower speed and noise level, while

internal chassis temperatures are low. If internal chassis temperature increases beyond a lower

set point, the fan speed will rise linearly with the internal temperature until the higher set point

is reached. At that point, the fan speed is at its maximum. As fan speed increases, so does fan

noise levels. Systems should be designed to provide adequate air around the boxed processor

fan heatsink that remains cooler then lower set point. These set points, represented in

Figure 7-9 and Table 7-2, can vary by a few degrees from fan heatsink to fan heatsink. The

internal chassis temperature should be kept below 38 ºC. Meeting the processor's temperature

specification (see Chapter 5) is the responsibility of the system integrator.

The motherboard must supply a constant +12 V to the processor's power header to ensure proper

operation of the variable speed fan for the boxed processor. Refer to Table 7-1 for the specific

requirements.

Figure 7-9. Boxed Processor Fan Heatsink Set Points

Higher Set Point

Highest Noise Level

Increasing Fan

Speed & Noise

Lower Set Point

Lowest Noise Level

X

Y

Z

Internal Chassis Temperature (Degrees C)

Datasheet

95

Boxed Processor Specifications

Table 7-2. Fan Heatsink Power and Signal Specifications

Boxed Processor Fan

Heatsink Set Point (ºC)

Boxed Processor Fan Speed

Notes

When the internal chassis temperature is below or equal to this set point,

the fan operates at its lowest speed. Recommended maximum internal

chassis temperature for nominal operating environment.

1

X ≤ 30

When the internal chassis temperature is at this point, the fan operates

between its lowest and highest speeds. Recommended maximum

internal chassis temperature for worst-case operating environment.

Y = 34

-

When the internal chassis temperature is above or equal to this set point,

the fan operates at its highest speed.

Z ≥ 38

NOTES:

1.

Set point variance is approximately ± 1 °C from fan heatsink to fan heatsink.

If the boxed processor fan heatsink 4-pin connector is connected to a 4-pin motherboard header and

the motherboard is designed with a fan speed controller with PWM output (CONTROL see

Table 7-1) and remote thermal diode measurement capability the boxed processor will operate as

follows:

As processor power has increased the required thermal solutions have generated increasingly more

noise. Intel has added an option to the boxed processor that allows system integrators to have a

quieter system in the most common usage.

The 4th wire PWM solution provides better control over chassis acoustics. This is achieved by

more accurate measurement of processor die temperature through the processor's temperature

diode (T

). Fan RPM is modulated through the use of an ASIC located on the motherboard that

diode

sends out a PWM control signal to the 4th pin of the connector labeled as CONTROL. The fan

speed is based on actual processor temperature instead of internal ambient chassis temperatures.

If the new 4-pin active fan heat sink solution is connected to an older 3-pin baseboard processor fan

header, it will default back to a thermistor controlled mode, allowing compatibility with existing 3-

pin baseboard designs. Under thermistor controlled mode, the fan RPM is automatically varied

based on the Tinlet temperature measured by a thermistor located at the fan inlet.

For more details on specific motherboard requirements for 4-wire based fan speed control see the

®

Intel Pentium 4 Processor on 90 nm Process in the 775-Land Package Thermal Design Guide.

§

96

Datasheet


型号：	541
厂家：	INTEL
描述：	Pentium 4 Processors Supporting Hyper-Threading Technology 奔腾4处理器，支持超线程技术
文件：	总96页 (文件大小：1585K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

541 [INTEL]

相关型号：

541-0001-0-01

541-0004-8-01

541-0869-035

541-100KJTR-ND

541-1074

541-1074-ND

541-1075

541-1075-ND

541-1076

541-1076-ND

541-1203

541-1203-ND