450NX [INTEL]
Intel 450NX PCIset; 英特尔450NX PCIset
| 型号： | 450NX |
| 厂家： | 
INTEL |
| 描述： | Intel 450NX PCIset |
| 文件： | 总248页 (文件大小：2110K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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in l
e
Intel® 450NX PCIset
82454NX PCI Expander Bridge (PXB)
82453NX Data Path Multiplexor (MUX)
82452NX RAS/CAS Generator (RCG)
82451NX Memory & I/O Controller (MIOC)
Order Number: 243771-004
June 1998
© Intel Corporation 1998
Information in this document is provided in connection with Intel products. No license, express or
implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except
as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatso-
ever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products
including liability or warranties relating to fitness for a particular purpose, merchantability, or infringe-
ment of any patent, copyright or other intellectual property right. Intel products are not intended for use
in medical, life saving, or life sustaining applications. Intel may make changes to specifications and prod-
uct descriptions at any time, without notice.
The Intel® 450NX PCIset may contain design defects or errors known as errata which may cause the prod-
uct to deviate from the published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing
your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel
literature, may be obtained by calling 1-800-548-4725 or by visiting Intel’s website at
http://www.intel.com
Copyright © Intel Corporation 1998.
* Third-party brands and names are the property of their respective owners.
CONTENTS
Chapter 1
Introduction ......................................................................................................................................... 1-1
1.1
1.2
1.3
1.4
Overview ..................................................................................................................................................... 1-1
®
Intel 450NX PCIset Components .............................................................................................................. 1-2
®
Intel 450NX PCIset Feature Summary ...................................................................................................... 1-3
Packaging & Power ..................................................................................................................................... 1-4
Chapter 2
Signal Descriptions ............................................................................................................................ 2-1
2.1
2.2
Conventions ................................................................................................................................................ 2-1
Summary ..................................................................................................................................................... 2-2
2.2.1
Signal Summary, By Component .................................................................................................. 2-2
2.2.1.1
2.2.1.2
2.2.1.3
2.2.1.4
MIOC Signal List .......................................................................................................... 2-3
PXB Signal List ............................................................................................................ 2-4
RCG Signal List ........................................................................................................... 2-5
MUX Signal List ........................................................................................................... 2-5
2.3
2.4
System Interface ......................................................................................................................................... 2-6
2.3.1
2.3.2
System / MIOC Interface ............................................................................................................... 2-6
Third-Party Agent / MIOC Interface .............................................................................................. 2-8
PCI Interface ............................................................................................................................................... 2-8
2.4.1
2.4.2
2.4.3
2.4.4
Primary Bus .................................................................................................................................. 2-8
64-bit Access Support ................................................................................................................. 2-10
Internal vs. External Arbitration ................................................................................................... 2-10
PIIX4E Interface .......................................................................................................................... 2-11
2.5
Memory Subsystem Interface .................................................................................................................... 2-12
2.5.1
2.5.2
External Interface ........................................................................................................................ 2-12
Internal Interface ......................................................................................................................... 2-14
2.5.2.1
2.5.2.2
2.5.2.3
RCG / DRAM Interface .............................................................................................. 2-14
DRAM / MUX Interface .............................................................................................. 2-15
RCG / MUX Interface ................................................................................................. 2-15
2.6
2.7
Expander Interface .................................................................................................................................... 2-15
Common Support Signals ......................................................................................................................... 2-17
2.7.1
2.7.2
JTAG Interface ............................................................................................................................ 2-17
Reference Signals ....................................................................................................................... 2-17
2.8
Component-Specific Support Signals ........................................................................................................ 2-18
2.8.1
2.8.2
2.8.3
2.8.4
MIOC ........................................................................................................................................... 2-18
PXB ............................................................................................................................................ 2-19
RCG ............................................................................................................................................ 2-19
MUX ............................................................................................................................................ 2-19
Chapter 3
Register Descriptions ......................................................................................................................... 3-1
3.1
3.2
Access Restrictions ..................................................................................................................................... 3-1
I/O Mapped Registers ................................................................................................................................. 3-1
3.2.1
CONFIG_ADDRESS: Configuration Address Register ............................................................... 3-1
Intel® 450NX PCIset
-i-
CONTENTS
3.2.2
CONFIG_DATA: Configuration Data Register .............................................................................. 3-2
3.3
MIOC Configuration Space .......................................................................................................................... 3-3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.3.6
3.3.7
3.3.8
3.3.9
BUFSIZ: Buffer Sizes ................................................................................................................... 3-4
BUSNO[1:0]: Lowest PCI Bus Number, per PXB ......................................................................... 3-5
CHKCON: Check Connection ....................................................................................................... 3-5
CLASS: Class Code Register ....................................................................................................... 3-6
CONFIG: Software-Defined Configuration Register ..................................................................... 3-6
CVCR: Configuration Values Captured on Reset ......................................................................... 3-8
CVDR: Configuration Values Driven On Reset ............................................................................ 3-9
DBC[15:0]: DRAM Bank Configuration Registers ......................................................................... 3-9
DEVMAP: System Bus PCI Device Map .................................................................................... 3-10
3.3.10 DID: Device Identification Register ............................................................................................. 3-11
3.3.11 ECCCMD: ECC Command Register .......................................................................................... 3-11
3.3.12 ECCMSK: ECC Mask Register ................................................................................................... 3-12
3.3.13 ERRCMD: Error Command Register .......................................................................................... 3-12
3.3.14 ERRSTS: Error Status Register ................................................................................................. 3-13
3.3.15 GAPEN: Gap Enables ................................................................................................................ 3-14
3.3.16 HDR: Header Type Register ....................................................................................................... 3-15
3.3.17 HEL[1:0] Host Bus Error Log ...................................................................................................... 3-15
3.3.18 HXGB: High Expansion Gap Base ............................................................................................. 3-16
3.3.19 HXGT: High Expansion Gap Top ............................................................................................... 3-16
3.3.20 IOABASE: I/O APIC Base Address ............................................................................................ 3-16
3.3.21 IOAR: I/O APIC Ranges ............................................................................................................. 3-17
3.3.22 IOR: I/O Ranges ......................................................................................................................... 3-17
3.3.23 ISA: ISA Space ........................................................................................................................... 3-18
3.3.24 LXGB: Low Expansion Gap Base ............................................................................................... 3-18
3.3.25 LXGT: Low Expansion Gap Top ................................................................................................. 3-18
3.3.26 MAR[6:0]: Memory Attribute Region Registers ........................................................................... 3-19
3.3.27 MEA[1:0] Memory Error Effective Address ................................................................................. 3-20
3.3.28 MEL[1:0] Memory Error Log ....................................................................................................... 3-20
3.3.29 MMBASE: Memory-Mapped PCI Base ...................................................................................... 3-21
3.3.30 MMR[3:0]: Memory-Mapped PCI Ranges .................................................................................. 3-21
3.3.31 PMD[1:0]: Performance Monitoring Data Register ..................................................................... 3-21
3.3.32 PME[1:0]: Performance Monitoring Event Selection .................................................................. 3-22
3.3.33 PMR[1:0]: Performance Monitoring Response ........................................................................... 3-23
3.3.34 RC: Reset Control Register ........................................................................................................ 3-24
3.3.35 RCGP: RCGs Present ................................................................................................................ 3-25
3.3.36 REFRESH: DRAM Refresh Control Register ............................................................................. 3-25
3.3.37 RID: Revision Identification Register .......................................................................................... 3-25
3.3.38
ROUTE[1:0]: Route Field Seed ................................................................................................. 3-26
3.3.39 SMRAM: SMM RAM Control Register ........................................................................................ 3-26
3.3.40 SUBA[1:0]: Bus A Subordinate Bus Number, per PXB .............................................................. 3-27
3.3.41 SUBB[1:0]: Bus B Subordinate Bus Number, per PXB .............................................................. 3-28
3.3.42 TCAP[0:3]: Target Capacity, per PXB/PCI Port .......................................................................... 3-28
3.3.43 TOM: Top of Memory ................................................................................................................. 3-29
3.3.44 VID: Vendor Identification Register ............................................................................................ 3-29
3.4
PXB Configuration Space .......................................................................................................................... 3-29
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
3.4.7
BUFSIZ: Buffer Sizes ................................................................................................................. 3-31
CLASS: Class Code Register ..................................................................................................... 3-31
CLS: Cache Line Size ................................................................................................................ 3-32
CONFIG: Configuration Register ................................................................................................ 3-32
DID: Device Identification Register ............................................................................................. 3-33
ERRCMD: Error Command Register .......................................................................................... 3-34
ERRSTS: Error Status Register ................................................................................................. 3-35
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Intel® 450NX PCIset
CONTENTS
3.4.8
3.4.9
GAPEN: Gap Enables ................................................................................................................ 3-36
HDR: Header Type Register ...................................................................................................... 3-36
3.4.10 HXGB: High Expansion Gap Base ............................................................................................. 3-36
3.4.11 HXGT: High Expansion Gap Top ............................................................................................... 3-36
3.4.12 IOABASE: I/O APIC Base Address ............................................................................................ 3-37
3.4.13 ISA: ISA Space .......................................................................................................................... 3-37
3.4.14 LXGB: Low Expansion Gap Base .............................................................................................. 3-37
3.4.15 LXGT: Low Expansion Gap Top ................................................................................................ 3-37
3.4.16 MAR[6:0]: Memory Attribute Region Registers .......................................................................... 3-38
3.4.17 MLT: Master Latency Timer Register ......................................................................................... 3-38
3.4.18 MMBASE: Memory-Mapped PCI Base ..................................................................................... 3-38
3.4.19 MMT: Memory-Mapped PCI Top ............................................................................................... 3-39
3.4.20 MTT: Multi-Transaction Timer Register ..................................................................................... 3-39
3.4.21 PCICMD: PCI Command Register ............................................................................................. 3-39
3.4.22 PCISTS: PCI Status Register .................................................................................................... 3-40
3.4.23 PMD[1:0]: Performance Monitoring Data Register ..................................................................... 3-41
3.4.24 PME[1:0]: Performance Monitoring Event Selection .................................................................. 3-42
3.4.25 PMR[1:0]: Performance Monitoring Response .......................................................................... 3-43
3.4.26 RID: Revision Identification Register ......................................................................................... 3-44
3.4.27 RC: Reset Control Register ....................................................................................................... 3-44
3.4.28 ROUTE: Route Field Seed ......................................................................................................... 3-45
3.4.29 SMRAM: SMM RAM Control Register ....................................................................................... 3-45
3.4.30 TCAP: Target Capacity .............................................................................................................. 3-46
3.4.31 TMODE: Timer Mode ................................................................................................................. 3-46
3.4.32 TOM: Top of Memory ................................................................................................................. 3-47
3.4.33 VID: Vendor Identification Register ............................................................................................ 3-47
Chapter 4
System Address Maps ....................................................................................................................... 4-1
4.1
Memory Address Map ................................................................................................................................. 4-1
4.1.1
4.1.2
Memory-Mapped I/O Spaces ........................................................................................................ 4-4
SMM RAM Support ....................................................................................................................... 4-4
4.2
4.3
I/O Space .................................................................................................................................................... 4-5
PCI Configuration Space ............................................................................................................................. 4-6
Chapter 5
Interfaces ............................................................................................................................................. 5-1
5.1
5.2
5.3
System Bus ................................................................................................................................................. 5-1
PCI Bus ....................................................................................................................................................... 5-1
Expander Bus .............................................................................................................................................. 5-1
5.3.1
Expander Electrical Signal and Clock Distribution ........................................................................ 5-2
5.4
5.5
Third-Party Agents ...................................................................................................................................... 5-2
Connectors .................................................................................................................................................. 5-3
Chapter 6
Memory Subsystem ............................................................................................................................ 6-1
6.1
Overview ..................................................................................................................................................... 6-1
6.1.1
6.1.2
Physical Organization ................................................................................................................... 6-1
Configuration Rules and Limitations ............................................................................................. 6-3
6.1.2.1
6.1.2.2
6.1.2.3
Interleaving .................................................................................................................. 6-3
Address Bit Permuting Rules and Limitations ............................................................. 6-4
Card to Card (C2C) Interleaving Rules and limitations ................................................ 6-4
6.1.3
Address Bit Permuting .................................................................................................................. 6-5
Intel® 450NX PCIset
-iii-
CONTENTS
6.1.4
6.1.5
Card to Card (C2C) Interleaving .................................................................................................... 6-5
Memory Initialization ...................................................................................................................... 6-6
Chapter 7
Transaction Summary ......................................................................................................................... 7-1
7.1 Host To/From Memory Transactions ........................................................................................................... 7-1
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.1.6
7.1.7
7.1.8
Reads and Writes .......................................................................................................................... 7-1
Cache Coherency Cycles .............................................................................................................. 7-1
Interrupt Acknowledge Cycles ....................................................................................................... 7-1
Locked Cycles ............................................................................................................................... 7-1
Branch Trace Cycles ..................................................................................................................... 7-2
Special Cycles ............................................................................................................................... 7-2
System Management Mode Accesses .......................................................................................... 7-3
Third-Party Intervention ................................................................................................................. 7-3
7.2
Outbound Transactions ................................................................................................................................ 7-4
7.2.1
7.2.2
7.2.3
7.2.4
Supported Outbound Accesses ..................................................................................................... 7-4
Outbound Locked Transactions ..................................................................................................... 7-4
Outbound Write Combining ........................................................................................................... 7-4
Third-Party Intervention on Outbounds ......................................................................................... 7-4
7.3
7.4
Inbound Transactions .................................................................................................................................. 7-5
7.3.1
7.3.2
Inbound LOCKs ............................................................................................................................. 7-5
South Bridge Accesses ................................................................................................................. 7-5
Configuration Accesses ............................................................................................................................... 7-6
Chapter 8
Arbitration, Buffers & Concurrency ................................................................................................... 8-1
8.1
8.2
PCI Arbitration Scheme ............................................................................................................................... 8-1
Host Arbitration Scheme .............................................................................................................................. 8-1
8.2.1
Third Party Arbitration .................................................................................................................... 8-2
8.3
South Bridge Support ................................................................................................................................... 8-2
8.3.1
8.3.2
8.3.3
I/O Bridge Configuration Example. ................................................................................................ 8-2
PHOLD#/PHLDA# Protocol ........................................................................................................... 8-3
WSC# Protocol .............................................................................................................................. 8-3
Chapter 9
Data Integrity & Error Handling .......................................................................................................... 9-1
9.1
DRAM Integrity ............................................................................................................................................. 9-1
9.1.1
9.1.2
9.1.3
9.1.4
9.1.5
ECC Generation ............................................................................................................................ 9-1
ECC Checking and Correction ...................................................................................................... 9-1
ECC Error Reporting ..................................................................................................................... 9-1
Memory Scrubbing ........................................................................................................................ 9-2
Debug/Diagnostic Support ............................................................................................................. 9-2
9.2
System Bus Integrity .................................................................................................................................... 9-2
9.2.1 System Bus Control & Data Integrity ............................................................................................. 9-3
9.3
9.4
PCI Integrity ................................................................................................................................................. 9-3
Expander Bus .............................................................................................................................................. 9-3
Chapter 10
System Initialization .......................................................................................................................... 10-1
10.1 Post Reset Initialization .............................................................................................................................. 10-1
10.1.1 Reset Configuration Using CVDR/CVCR .................................................................................... 10-1
10.1.1.1 Configuration Protocol ................................................................................................ 10-1
10.1.1.2 Special Considerations for Third-Party Agents .......................................................... 10-2
-iv-
Intel® 450NX PCIset
CONTENTS
Chapter 11
Clocking and Reset .......................................................................................................................... 11-1
11.1 Clocking ..................................................................................................................................................... 11-1
11.2 System Reset ............................................................................................................................................ 11-2
®
11.2.1 Intel 450NX PCIset Reset Structure ......................................................................................... 11-2
11.2.2 Output States During Reset ........................................................................................................ 11-5
11.2.2.1 MIOC Reset State ..................................................................................................... 11-6
11.2.2.2 PXB Reset State ........................................................................................................ 11-8
11.2.2.3 RCG Reset State ....................................................................................................... 11-9
11.2.2.4 MUX Reset State ....................................................................................................... 11-9
Chapter 12
Electrical Characteristics ................................................................................................................. 12-1
12.1 Signal Specifications ................................................................................................................................. 12-1
12.1.1 Unused Pins ................................................................................................................................ 12-1
12.1.2 Signal Groups ............................................................................................................................. 12-1
12.1.3 The Power Good Signal: PWRGD .............................................................................................. 12-3
12.1.4 LDSTB# Usage ........................................................................................................................... 12-5
12.1.5 VCCA Pins .................................................................................................................................. 12-5
12.2 Maximum Ratings ...................................................................................................................................... 12-6
12.3 DC Specifications ...................................................................................................................................... 12-7
12.4 AC Specifications .................................................................................................................................... 12-11
12.5 Source Synchronous Data Transfers ...................................................................................................... 12-20
12.6 I/O Signal Simulations: Ensuring I/O Timings ......................................................................................... 12-21
12.7 Signal Quality Specifications ................................................................................................................... 12-21
®
12.7.1 Intel 450NX PCIset Ringback Specification ............................................................................ 12-21
®
12.7.2 Intel 450NX PCIset Undershoot Specification ........................................................................ 12-24
12.7.3 Skew Requirements .................................................................................................................. 12-24
®
12.8 Intel 450NX PCIset Thermal Specifications .......................................................................................... 12-25
12.8.1 Thermal Solution Performance ................................................................................................. 12-25
12.9 Mechanical Specifications ....................................................................................................................... 12-26
12.9.1 Pin Lists Sorted by Pin Number: ............................................................................................... 12-26
12.9.2 Pin Lists Sorted by Signal ......................................................................................................... 12-72
12.9.3 Package information ............................................................................................................... 12-118
12.9.3.1 324 BGA Package Information .............................................................................. 12-118
12.9.3.2 540 PBGA Package Information ............................................................................ 12-120
Intel® 450NX PCIset
-v-
CONTENTS
-vi-
Intel® 450NX PCIset
Introduction
1
1.1 Overview
®
The Intel 450NX PCIset provides an integrated Host-to-PCI bridge and memory controller
optimized for multiprocessor systems and standard high-volume (SHV) servers based on the
®
Pentium II Xeon™ processor variant of the P6 family. The Intel 450NX PCIset consists of four
components: 82454NX PCI Expander Bridge (PXB), 82451NX Memory and I/O Bridge
Controller (MIOC), 82452NX RAS/CAS Generator (RCG), and 82453NX Data Path
Multiplexor (MUX). Figure 1-1 illustrates a typical SHV server system based on the Intel
450NX PCIset. The system bus interface supports up to 4 Pentium II Xeon processors at 100
MHz. An additional bus mastering agent such as a cluster bridge can be supported at reduced
frequencies. Two dedicated PCI Expander Bridges (PXBs) can be connected via the Expander
L2
L2
L2
L2
Cache
Cache
Cache
Cache
Pentium II
Pentium II
Pentium II
Pentium® II
Xeon
processor
Xeon
processor
Xeon
processor
Xeon™
processor
Optional
Cluster
Bridge
System Bus
AGTL+ 100 MHz
MD[71:0]
MIOC
Memory
Subsystem
1 or 2 cards
MUXs
third-party
controls
Memory
and I/O
Controller
MA[13:0]
Control
Expander
Buses
X1
X0
PXB #1
PXB #0
BMIDE HDDs
PCI
Expander
Bridge
PCI
Expander
Bridge
USB
USB
PIIX4E
South Bridge
1B
1A
0B
0A
IDE CD-ROM
PCI
Slots
ISA slots
I/O
APIC
XCVR
KBC
8042
SIO
BIOS
Flash
EPROM
4 PCI Buses
32-bit, 33 MHz, 3.3v or 5v
Can link pairs into 64-bit bus
®
Figure 1-1: Simplified Intel 450NX PCIset System Block Diagram
Intel® 450NX PCIset
1-1
1. Introduction
Bus. Each PXB provides two independent 32-bit, 33 MHz PCI buses, with an option to link the
two buses into a single 64-bit, 33 MHz bus. The Intel 450NX PCIset memory subsystem
supports one or two memory cards. Each card is comprised of an RCG, a DRAM array, and
two MUXs. The MIOC issues requests to the RCG components on each card to generate RAS#,
CAS#, and WE# outputs to the DRAMs. The MUX components provide the datapath for the
DRAM arrays. Up to 8 GB of memory in various configurations are supported.
Other capabilities of the Intel 450NX PCIset include:
®
•
•
Full Pentium II Xeon™ processor bus interface (36-bit address, 64-bit data) at 100 MHz.
Support for two dedicated PCI expander bridges (PXBs) attached behind the system bus so
as not to add additional electrical load to the system bus.
•
Support for both internal and external system bus and I/O bus arbitration.
Supporting Devices
The Intel 450NX PCIset is designed to support the PIIX4E south bridge. The PIIX4E is a highly
integrated mulit-functional component that supports the following capabilities:
•
•
•
•
•
PCI Rev 2.1-compliant PCI-to-ISA Bridge with support for 33-MHz PCI operations
Enhanced DMA controller
8259 Compatible Programmable Interrupt Controller
System Timer functions
Integrated IDE controller with Ultra DMA/33 support
1.2 Intel® 450NX PCIset Components
MIOC Memory and I/O Bridge Controller
The MIOC accepts access requests from the system bus and directs those accesses to
memory or one of the PCI buses. The MIOC also accepts inbound requests from the
PCI buses. The MIOC provides the data port and buffering for data transferred
between the system bus, PXBs and memory. In addition, the MIOC generates the
appropriate controls to the RCG and MUX components to control data transfer to and
from the memory.
PXB
PCI Expander Bridge
The PXB provides the interface to two independent 32-bit, 33 MHz Rev 2.1-compliant
PCI buses. The PXB is both a master and target on each PCI bus.
RCG RAS/CAS Generator
The RCG is responsible for accepting memory requests from the MIOC and
converting these into the specific signals and timings required by the DRAM. Each
RCG controls up to four banks of memory.
MUX Data Path Multiplexor
The MUX provides the multiplexing and staging required to support memory
interleaving between the DRAMs and the MIOC. Each MUX provides the data path
for one-half of a Qword for each of four interleaves.
1-2
Intel® 450NX PCIset
®
1.3 Intel 450NX PCIset Feature Summary
1.3 Intel® 450NX PCIset Feature Summary
System Bus Support
®
•
•
•
Fully supports the Pentium II Xeon™ processor bus protocol at bus frequencies up to
100 MHz.
Functionally and electrically compatible with the original and Pentium II P6 family
processor buses.
Fully supports 4-way multiprocessing, with performance scaling to 3.5x that of a uni-
processor system.
•
•
•
•
Full 36-bit address decode and drive capability.
Full 64-bit data bus (32-bit data bus mode is not supported).
Parity protection on address and control signals, ECC protection on data signals.
8-deep in-order queue; 24-deep memory request queue; 2-deep outbound read-request
queue per PCI bus; 6-deep outbound write-posting queue per PCI bus.
•
•
•
AGTL+ bus driver technology.
®
Intel 450NX PCIset adds only one load to the system bus.
Intel 450GX PCIset-compatible third-party request/grant and control signals, allowing
cluster bridges to be placed on the system bus.
DRAM Interface Support
•
Memory technologies supported are 16- and 64-Mbit, 60nsec and 50nsec 3.3v EDO DRAM
devices.
•
•
Supports from 32 MB to 8 GB of memory, in 64 MB increments after the initial 32 MB.
Supports 4-way interleaved operation, with 2-way interleave supported in the first bank
of card 0 to permit entry-level systems with minimal memory.
•
•
Supports memory address bit permuting (ABP) to obtain alternate row selection bits.
Supports card-to-card interleaving to further distribute memory accesses across multiple
banks of memory.
•
•
•
Staggered CAS-before-RAS refresh.
ECC with single-bit error correction and scrub-on-error in the memory.
Extensive Host-to-Memory and PCI-to-Memory write data buffering.
I/O Bridge Support
•
Up to four independent 32-bit PCI ports (using two PXBs)
–
–
each supports up to 10 electrical loads (connectors count as loads).
each provides internal arbitration for up to 6 masters plus a south bridge on the
compatibility PCI bus, or external arbitration.
•
Synchronous operation to the system bus clock using a 3:1 system bus/PCI bus gearing
ratio.
–
–
3:1 ratio supports a 100 MHz system bus and 33.33 MHz PCI bus.
3:1 ratio supports a 90 MHz system bus and 30 MHz PCI bus (or lower, depending on
effect of 6th load).
•
•
•
•
Parity protection on all PCI signals.
Inbound read prefetches of up to 4 cache lines.
Outbound write assembly of full/partial line writes.
Data streaming support from PCI to DRAM.
Intel® 450NX PCIset
1-3
1. Introduction
System Management Features
•
Provides controlled access to the Intel Architecture System Management Mode (SMM)
memory space (SM RAM).
Test & Tuning Features
•
•
Signal interconnectivity testing via boundary scan.
Access to internal control and status registers via JTAG TAP port.
I2C access is not provided in the PCIset; however, error indicators are reported to pins
which can be monitored and sampled using I2C capabilities if provided elsewhere in the
system.
•
System bus, memory and I/O performance counters with programmable events.
Reliability/Availability/Serviceability (RAS) Features
•
ECC coverage of system data bus and memory; parity coverage of system bus controls,
PCI bus, and Expander bus.
•
•
ECC bits can be corrupted via selective masking for diagnostics.
Fault recording of the first two ECC errors. Each includes error type and syndrome.
Memory ECC error logs include the effective address, allowing identification of the failing
location. Error logs are not affected by reset, allowing recovery software to examine the
logs.
1.4 Packaging & Power
®
•
Table 1-1 indicates the signal count, package and power for each component in the Intel
450NX PCIset. In a common high-end configuration, using two memory cards (each with
one RCG and two MUX components), two PXBs and 3.3 V supplies, the Intel 450NX
PCIset would contribute approximately 47 watts.
Table 1-1: Signals, Pins, Packaging and Power
1
Chip
MIOC
PXB
Signals
348
Package
Footprint Power
2
PLGA-540
42.5 mm
42.5 mm
27.0 mm
27.0 mm
13.2 W
7.8 W
2.5 W
3.3 W
2
177
PLGA-540
RCG
173
BGA-324
BGA-324
MUX
Notes:
207
1. Assumes 3.3 V supplies.
2. Requires heat sink.
1-4
Intel® 450NX PCIset
Signal Descriptions
2
®
This chapter provides a detailed description of all signals used in any component in the Intel
450NX PCIset.
2.1 Conventions
The terms assertion and deassertion are used extensively when describing signals, to avoid
confusion when working with a mix of active-high and active-low signals. The term assert, or
assertion, indicates that the signal is active, independent of whether the active level is
represented by a high or low voltage. The term deassert, or deassertion, indicates that the signal
is inactive.
The “#” symbol at the end of a signal name indicates that the active, or asserted state occurs
when the signal is at a low voltage level. When “#” is not present after the signal name the
signal is asserted when at the high voltage level.
When discussing data values used inside the chip set, the logical value is used; i.e., a data
value described as "1101b" would appear as "1101b" on an active-high bus, and as "0010b" on
an active-low bus. When discussing the assertion of a value on the actual pin, the physical
value is used; i.e., asserting an active-low signal produces a "0" value on the pin.
The following notations are used to describe the signal type:
I
Input pin
O
Output pin
I/O
OD
Bidirectional (input/output) pin
Open drain output pin (other than AGTL+ signals)
The signal description also includes the type of buffer used for the particular signal:
AGTL+
PCI
Open drain AGTL+ interface.
PCI-compliant 3.3 V/5 V-tolerant interface
Low-voltage (3.3 V) TTL-compatible signals.
2.5 V CMOS signals.
LVTTL
2.5V
Analog
Typically a voltage reference or specialty power supply.
Intel® 450NX PCIset
2-1
2. Signal Descriptions
Some signals or groups of signals have multiple versions. These signal groups may represent
distinct but similar ports or interfaces, or may represent identical copies of the signal used to
reduce loading effects. The following conventions are used:
RR(A,B,C)XX
expands to: RRAXX, RRBXX, and RRCXX
expands to: RRAXX, RRBXX, RRCXX, and RRDXX
expands to: RRAXX, RRBXX, and RRCXX
RR(A,...,D)XX
RRpXX, where p=A,B,C
Typically, upper case groups (e.g., “(A,B,C)”) represent functionally similar but logically
distinct signals; each signal provides an independent control, and may or may not be asserted
at the same time as the other signals in the grouping. In contrast, lower case groups (e.g.,
“(a,b,c)”) typically represent identical duplicates of a common signal provided to reduce
loading.
2.2 Summary
®
Figure 2-1 illustrates the partitioning of interfaces across the components in the Intel 450NX
PCIset. The remainder of this section lists the signals and signal counts in each interface by
component. The signal functions are described in subsequent sections.
®
Pentium II Xeon
processor bus
™
System Interface
Memory
Interface
(External)
MIOC
MUXs
Expander
Interface (2)
DRAM
Array
memory
cards
1
0
Memory Interface (Internal)
PXB #1
PXB #0
1B
1A
0B
0A
PCI Interfaces (2)
PCI Interfaces (2)
PCI Bus #0A is the Compatibility Bus
Figure 2-1: Interface Summary: Partitioning
2.2.1
Signal Summary, By Component
The following tables provide summary lists of all signals in each component, sorted
alphabetically within interface type. The signals are described in a later section.
2-2
Intel® 450NX PCIset
2.2 Summary
2.2.1.1
MIOC Signal List
System Interface
A[35:3]#
134
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
DEP[7:0]#
DRDY#
HIT#
AGTL+ I/O
AGTL+ I/O
AGTL+ I
ADS#
AERR#
AP[1:0]#
HITM#
AGTL+ I
2.5V
AGTL+ I
BERR#
INIT#
OD
BINIT#
LOCK#
REQ[4:0]#
BNR#
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
BP[1:0]#
LVTTL I/OD RP#
BPRI#
AGTL+ I/O
AGTL+ O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
RS[2:0]#
BREQ[0]#
D[63:0]#
RSP#
TRDY#
DBSY#
DEFER#
Third-Party Agent Interface
IOGNT#
4
LVTTL I
TPCTL[1:0]
LVTTL I
IOREQ#
LVTTL O
Memory Subsystem / External Interface
119
BANK[2:0]#
CARD[1:0]#
CMND[1:0]#
CSTB#
AGTL+ O
AGTL+ O
AGTL+ O
AGTL+ O
AGTL+ I/O
AGTL+ O
AGTL+ O
AGTL+ I/O
AGTL+ I/O
DVALID(a,b)#
MA[13:0]#
MD[71:0]#
MRESET#
PHIT(a,b)#
ROW#
AGTL+ O
AGTL+ O
AGTL+ I/O
AGTL+ O
AGTL+ I
AGTL+ O
AGTL+ I
AGTL+ I
AGTL+ O
DCMPLT(a,b)#
DOFF[1:0]#
DSEL[1:0]#
DSTBN[3:0]#
DSTBP[3:0]#
RCMPLT(a,b)#
RHIT(a,b)#
WDEVT#
Expander Interface (two per MIOC: 0,1)
2 x 33
X(0,1)ADS#
X(0,1)BE[1:0]#
X(0,1)BLK#
X(0,1)CLK
AGTL+ I/O
AGTL+ I/O
AGTL+ O
X(0,1)HSTBP#
X(0,1)PAR#
AGTL+ O
AGTL+ I/O
AGTL+ O
AGTL+ O
AGTL+ I
AGTL+ I
AGTL+ I
AGTL+ I
X(0,1)RST#
CMOS
CMOS
CMOS
O
O
I
X(0,1)RSTB#
X(0,1)RSTFB#
X(0,1)XRTS#
X(0,1)XSTBN#
X(0,1)XSTBP#
X(0,1)CLKB
X(0,1)CLKFB
X(0,1)D[15:0]#
X(0,1)HRTS#
X(0,1)HSTBN#
Common Support Signals
CRES[1:0]
AGTL+ I/O
AGTL+ O
AGTL+ O
16
Analog
2.5V
I
TMS
2.5V
I
I
I
I
TCK
I
TRST#
VCCA (3)
VREF (6)
2.5V
TDI
2.5V
I
Analog
Analog
TDO
2.5V
OD
Intel® 450NX PCIset
2-3
2. Signal Descriptions
Component-Specific Support Signals
CRESET# LVTTL O
LVTTL I/OD PWRGDB
9
PWRGD
LVTTL I
ERR[1:0]#
LVTTL O
AGTL+ I/O
LVTTL O
HCLKIN
2.5V
I
RESET#
INTREQ#
LVTTL O
SMIACT#
TOTAL SIGNALS
348
2.2.1.2
PXB Signal List
PCI Bus Interface (2 per PXB: A,B)
2 x 61
I/O
I/O
I
P(A,B)AD[31:0]
P(A,B)C/BE[3:0]#
P(A,B)CLKFB
P(A,B)CLK
PCI
PCI
I/O
I/O
P(A,B)PAR
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
P(A,B)PERR#
P(A,B)REQ[5:0]#
P(A,B)RST#
LVTTL I
LVTTL O
O
P(A,B)DEVSEL#
P(A,B)FRAME#
P(A,B)GNT[5:0]#
P(A,B)IRDY#
PCI
PCI
PCI
PCI
PCI
I/O
P(A,B)SERR#
P(A,B)STOP#
P(A,B)TRDY#
P(A,B)XARB#
OD
I/O
I/O
I
I/O
O
I/O
I/O
P(A,B)LOCK#
PCI Bus Interface / Non-Duplicated (one set per PXB)
6
O
ACK64#
PCI
PCI
PCI
I/O
PHLDA#
REQ64#
WSC#
PCI
PCI
PCI
MODE64#
PHOLD#
I
I
I/O
O
Expander Interface (one per PXB)
30
XADS#
AGTL+ I/O
AGTL+ I/O
AGTL+ I
XHSTBP#
XIB
AGTL+ I
XBE[1:0]#
AGTL+ O
AGTL+ I/O
AGTL+ I
XBLK#
XPAR#
XCLK
CMOS
I
XRST#
XD[15:0]#
AGTL+ I/O
AGTL+ I
AGTL+ I
XXRTS#
XXSTBN#
XXSTBP#
AGTL+ O
AGTL+ O
AGTL+ O
XHRTS#
XHSTBN#
Common Support Signals
12
CRES[1:0]
TCK
Analog
2.5V
I
TMS
2.5V
I
I
I
I
I
TRST#
VCCA (3)
VREF (2)
2.5V
TDI
2.5V
I
Analog
Analog
TDO
2.5V
OD
Component-Specific Support Signals
8
INTRQ(A,B)#
PCI
OD
PIIXOK#
LVTTL I
LVTTL I
P(A,B)MON[1:0]#
TOTAL SIGNALS
LVTTL I/OD PWRGD
177
2-4
Intel® 450NX PCIset
2.2 Summary
2.2.1.3
RCG Signal List
Memory Subsystem / External Interface
27
BANK[2:0]#
CARD#
AGTL+
I
MRESET#
PHIT#
AGTL+ I
AGTL+ I
AGTL+ I
AGTL+ I
AGTL+ I/O
AGTL+ I
AGTL+ O
AGTL+ O
AGTL+ O
AGTL+ I
CMND[1:0]#
CSTB#
RCMPLT#
RHIT#
GRCMPLT#
MA[13:0]#
ROW#
Memory Subsystem / Internal Interface
123
10
ADDR(A,B,C,D)[13:0]
AVWP#
LVTTL O
AGTL+ O
LRD#
AGTL+ O
RAS(A,B,C,D)(a,b,c,d)[1:0]# LVTTL O
WDME#
CAS(A,B,C,D)(a,b,c,d)[1:0]# LVTTL O
AGTL+ O
LVTTL O
LDSTB#
AGTL+ O
WE(A,B,C,D)(a,b)#
Common Support Signals
CRES[1:0]
TCK
Analog
2.5V
I
TMS
2.5 V
I
I
I
I
I
TRST#
VCCA
VREF (2)
2.5 V
TDI
2.5V
I
Analog
Analog
TDO
2.5V
OD
Component-Specific Support Signals
4
BANKID#
LVTTL I
LVTTL I
DR50T#
HCLKIN
LVTTL I
2.5 V
DR50H#
I
TOTAL SIGNALS
173
2.2.1.4
MUX Signal List
Memory Subsystem / External Interface
48
DCMPLT#
DOFF[1:0]#
DSEL#
AGTL+ I/O
AGTL+ I
DVALID#
AGTL+ I
GDCMPLT#
MD[35:0]#
MRESET#
WDEVT#
AGTL+ I/O
AGTL+ I/O
AGTL+ I
AGTL+ I
DSTBP[1:0]#
DSTBN[1:0]#
AGTL+ I/O
AGTL+ I/O
AGTL+ I
Memory Subsystem / Internal Interface
148
AVWP#
AGTL+ I
AGTL+ I
AGTL+ I
LVTTL I/O
Q1D[35:0]
Q2D[35:0]
Q3D[35:0]
WDME#
LVTTL I/O
LVTTL I/O
LVTTL I/O
AGTL+ I
LDSTB#
LRD#
Q0D[35:0]
Common Support Signals
10
CRES[1:0]
TCK
Analog
2.5 V
2.5 V
2.5 V
I
TMS
2.5 V
I
I
I
I
I
TRST#
VCCA
VREF (2)
2.5 V
TDI
I
Analog
Analog
TDO
OD
Component-Specific Support Signals
1
HCLKIN
2.5 V
I
TOTAL SIGNALS
207
Intel® 450NX PCIset
2-5
2. Signal Descriptions
2.3 System Interface
®
The MIOC provides the Intel 450NX PCIset’s sole connection to the system bus. This section
describes the Intel 450NX PCIset-specific uses of these signals.
2.3.1
System / MIOC Interface
A[35:3]#
Address Bus
AGTL+ I/O
A[35:3]# connect to the system address bus. During processor cycles the
A[35:3]# are inputs. The MIOC drives A[35:3]# during snoop cycles on behalf
of PCI initiators. The address bus is inverted on the system bus.
ADS#
Address Strobe
AGTL+ I/O
The system bus owner asserts ADS# to indicate the first of two cycles of a
request phase.
AERR#
Address Parity Error
AGTL+ I/O
AERR# is asserted by any agent that detects an address parity error.
AP[1:0]#
Address Parity
AGTL+ I/O
Parity protection on the address bus. AP#[1] covers A#[35:24], and AP#[0]
covers A#[23:3]. They are valid on both cycles of the request.
BERR#
BINIT#
Bus Error
AGTL+ I/O
This signal is asserted by any agent that observes an unrecoverable bus
protocol violation.
Bus Initialization
AGTL+ I/O
BINIT# is asserted to re-initialize the bus state machines. The MIOC will
terminate any ongoing PCI transaction and reset its inbound and outbound
queues. No configuration registers or error logging registers are affected.
BNR#
Block Next Request
AGTL+ I/O
Used to block the current request bus owner from issuing a new request.
BP[1:0]#
Performance Monitoring
LVTTL I/OD
In normal operation, the MIOC can be configured to drive performance
monitoring data out of either of these pins, similar in function to the BP pins
provided on the processors.
BPRI#
Priority Agent Bus Request
AGTL+ O
The MIOC is the only Priority Agent on the system bus. It asserts this signal
to obtain ownership of the address bus. BPRI# has priority over symmetric
bus requests.
BREQ[0]#
Symmetric Agent Bus Request
AGTL+ O
This signal is asserted by the MIOC when RESET# is asserted, to select the
boot processor. It is deasserted 2 host clocks after RESET# is deasserted.
2-6
Intel® 450NX PCIset
2.3 System Interface
D[63:0]#
DBSY#
Data
AGTL+ I/O
These signals are connected to the system data bus. The data signals are
inverted on the system bus.
Data Bus Busy
AGTL+ I/O
Used by the data bus owner to hold the data bus for transfers requiring more
than one cycle.
DEP[7:0]#
DEFER#
Data Bus ECC/Parity
These signals provide parity or ECC for the D#[63:0] signals. The MIOC only
provides ECC.
AGTL+ I/O
Defer
AGTL+ I/O
DEFER# is driven by the addressed agent to indicate that the transaction
cannot be guaranteed to be globally observed.
DRDY#
HIT#
Data Ready
AGTL+ I/O
AGTL+ I
Asserted for each cycle that valid data is transferred.
Hit
The MIOC never asserts HIT#; it has no cache, and never snoop stalls.
HITM#
INIT#
Hit Modified
AGTL+ I
The MIOC never asserts HITM#; it has no cache, and never snoop stalls.
Soft Reset
2.5V OD
INIT# may be asserted to request a soft reset of the processors. During a
system hard reset, the INIT# signal may be optionally asserted to cause the
processors to initiate their BIST. The INIT# signal is not asserted during
power-good reset.
LOCK#
Lock
AGTL+ I
All system bus cycles sampled with the assertion of LOCK# and ADS#, until
the negation of LOCK#, must be atomic; i.e., no PCI activity to DRAM is
allowed and the locked cycle must be translated to PCI if targeted for the PCI
bus.
REQ[4:0]#
Request Command
AGTL+ I/O
Asserted during both clocks of a request phase. In the first clock, the signals
define the transaction type to a level which is sufficient to begin a snoop
request. In the second clock, the signals carry additional information to define
the complete transaction type.
RP#
Request Parity
AGTL+ I/O
Even parity protection on ADS# and REQ[4:0]#. It is valid on both cycles of
the request.
RS[2:0]#
Response Signals
AGTL+ I/O
Indicate response type as shown below:
000 Idle state
001 Retry
010 Deferred
011 reserved
100 Hard failure
101 No Data
110 Implicit writeback
111 Normal Data
Intel® 450NX PCIset
2-7
2. Signal Descriptions
RSP#
Response Parity Signal
Parity protection on RS[2:0]#.
AGTL+ I/O
AGTL+ I/O
TRDY#
Target Ready
Indicates that the target of the system transaction is able to enter the data
transfer phase.
2.3.2
Third-Party Agent / MIOC Interface
The following signals provide support for an additional non-processor, third-party agent
(TPA) on the system bus. Such agents may need priority access to the system bus itself, or may
®
need to intervene in transactions between the processors and the Intel 450NX PCIset.
IOGNT#
I/O Grant
LVTTL I
The IOGNT# signal has two modes: Internal Arbitration Mode and External
Arbitration Mode, selected by a bit in the MIOC’s CONFIG register. In
Internal Arbitration Mode IOGNT# is an input from another bridge device
which is requesting ownership of the BPRI# signal. In external arbitration
mode, this bridge requests BPRI# ownership from an external bridge arbiter.
IOGNT# should be asserted by the external arbiter when this MIOC has been
granted ownership of the BPRI# signal.
IOREQ#
I/O Request
LVTTL O
The IOREQ# signal has two modes: Internal Arbitration Mode and External
Arbitration Mode, selected by a bit in the MIOC’s CONFIG register. In
Internal Arbitration Mode IOREQ# is the grant to another bridge device that
is making a request for ownership of the BPRI# signal. In external arbitration
mode this signal is asserted to request ownership of the BPRI# signal.
TPCTL[1:0]
Third Party Control
LVTTL I
®
These signals allow an agent participating in transactions between the Intel
450NX PCIset and another bus agent as a “third-party” to control the
responses generated by the Intel 450NX PCIset.
00
Accept
The MIOC will accept the request and provide the
normal response.
01
10
11
reserved
Retry
Defer
–
The MIOC will generate a RETRY response.
The MIOC will generate a DEFERRED response.
2.4 PCI Interface
2.4.1
Primary Bus
There are two primary PCI buses per PXB, identified as the “a” bus and the “b” bus groups.
Each signal name includes a “p”, indicating the PCI bus port; p = A or B.
2-8
Intel® 450NX PCIset
2.4 PCI Interface
PpAD[31:0]
PCI Address/Data
PCI I/O
PCI Address and Data signals are multiplexed on this bus. The physical byte
address is output during the address phase and the data follows in the
subsequent data phase(s).
PpC/BE[3:0]# Command/Byte Enable
PCI I/O
PCI Bus Command and Byte Enable signals are multiplexed on the same pins.
During the address phase of a transaction, C/BE[3:0]# define the bus
command. During the data phase C/BE[3:0]# are used as byte enables.
PpCLK
PCI Clock
LVTTL O
This signal is an output with a derived frequency equal to 1/3 of the system
bus frequency.
PpCLKFB
PCI Clock Feedback
LVTTL I
This signal is connected to the output of a low skew PCI clock buffer tree. It is
used to synchronize the PCI clock driven from PpCLK to the clock used for
the internal PCI logic.
PpDEVSEL# Device Select
PCI I/ O
DEVSEL# is driven by the device that has decoded its address as the target of
the current access.
PpFRAME#
Frame
PCI I/O
The PXB asserts FRAME# to indicate the start of a bus transaction. While
FRAME# is asserted, data transfers continue. When FRAME# is negated, the
transaction is in the final data phase. FRAME# is an input when the PXB acts
as a PCI target.
PpIRDY#
PpPAR
Initiator Ready
PCI I/O
This signal is asserted by a master to indicate its ability to complete the
current data transfer. IRDY# is an output when the PXB acts as a PCI initiator
and an input when the PXB acts as a PCI target.
Parity
PCI I/O
PAR is driven by the PXB when it acts as a PCI initiator during address and
data phases for a write cycle, and during the address phase for a read cycle.
PAR is driven by the PXB when it acts as a PCI target during each data phase
of a PCI memory read cycle. Even parity is generated across AD[31:0] and
C/BE[3:0]#.
PpRST#
PCI Reset
PCI O
PCI Bus Reset forces the PCI interfaces of each device to a known state. The
PXB generates a minimum 1 ms pulse on RST#.
PpPERR#
PCI Parity Error
PCI I/O
Pulsed by an agent receiving data with bad parity one clock after PAR is
asserted. The PXB will generate PERR# active if it detects a parity error on
the PCI bus and the PERR# Enable bit in the PCICMD register is set.
PpLOCK#
Lock
PCI I/O
LOCK# indicates an exclusive bus operation and may require multiple
transactions to complete. It is possible for different agents to use the PCI Bus
while a single initiator retains ownership of the LOCK# signal.
Intel® 450NX PCIset
2-9
2. Signal Descriptions
PpTRDY#
Target Ready
PCI I/O
The assertion of TRDY# indicates the target agent's ability to complete the
current data phase of the transaction. TRDY# is an input when the PXB acts as
a PCI master and an output when the PXB acts as a PCI target.
PpSERR#
PpSTOP#
System Error
PCI OD
The PXB asserts this signal to indicate an error condition.
Stop
PCI I/O
STOP# is used for disconnect, retry, and abort sequences on the PCI Bus. It is
an input when the PXB acts as a PCI initiator and an output when the PXB
acts as a PCI target.
2.4.2
64-bit Access Support
These signals are used only in 64-bit bus mode. There is one set per PXB.
ACK64#
64-bit Access Acknowledge
PCI I/O
This signal is driven by the accessed target to indicate its willingness to
transfer 64-bit data. When the PXB is the bus target, this signal is an output.
If asserted, the PXB will transfer 64-bit data; otherwise, the PXB will transfer
32-bit data. When the PXB is the bus master, this signal is an input.
MODE64#
64-bit Bus Mode
PCI I
A strapping pin that selects whether the pair of 32-bit PCI buses are used as
two independent 32-bit buses, or linked together as a single 64-bit bus. If
asserted, the buses are used as a single 64-bit bus: the 32-bit data bus of the
PCI “B” port becomes the high Dword of the 64-bit bus. An internal pull-up
insures that the pin appears deasserted if left unconnected.
REQ64#
64-bit Access Request
PCI I/O
This signal is driven by the bus master to indicate it’s desire to transfer 64-bit
data. When the PXB is the bus master, this signal is an output. The PXB will
assert this signal if it can transfer 64-bit data. When the PXB is the bus target,
this signal is an input.
The following 64-bit extension signals are mapped from the existing “B” port signals:
AD[63:32] from PBAD[31:0]
C/BE[7:4] from PBC/BE[3:0]
PAR64
from PBPAR
All other controls and status signals in 64-bit operation are taken from the Bus “A” signal set.
Unused pins on the “B” side should be tied inactive.
2.4.3
Internal vs. External Arbitration
Each PXB supports both internal arbitration and external arbitration, independently for each
PCI bus. While in internal arbitration mode, six pairs of request/grant signals are used to
support up to six PCI masters on the bus (plus the PXB itself, and the PIIX4E south bridge on
2-10
Intel® 450NX PCIset
2.4 PCI Interface
the compatibility PCI bus). While in external arbitration mode, only one pair (#0) are used,
and have different meanings.
Each signal name includes a “p”, indicating the PCI bus port; p = A or B.
PpXARB#
External Arbitration Mode
PCI I
A strapping pin, sampled at the trailing edge of reset. If asserted, the PCI bus
is controlled using an external arbiter. If deasserted, the PCI bus is controlled
using the PXB’s internal arbiter. An internal pull-up insures that the pin
appears deasserted if left unconnected.
Internal Arbitration Mode (per PCI bus, p=A,B)
PpREQ[5:0]# PCI Bus Request
PCI I
Six independent PCI bus request signals used by the internal PCI arbiter for
PCI initiator arbitration. Unused signals should be strapped inactive.
PpGNT[5:0]# PCI Grant
PCI O
Six independent PCI bus grant signals used by the internal PCI arbiter for PCI
initiator arbitration.
External Arbitration Mode (per PCI bus, p=A,B)
When operating in external arbitration mode, REQ[5:1]# and GNT[5:1]# signals are not used.
The REQ[0]# signal is redefined as HGNT#, and the GNT[0]# signal is redefined as HREQ#.
PpHREQ#
Host Request
PCI O
Generated by the PXB to the external PCI arbiter to request control of the PCI
bus to perform a Host-PCI access.
PpHGNT#
Host Grant
PCI I
Generated by the external PCI arbiter to grant the PCI bus to the PXB to
perform a Host-PCI transfer.
2.4.4
PIIX4E Interface
The compatibility PCI bus (PCI Bus 0A) supports a PIIX4E south bridge, and requires several
additional handshake signals, provided by the PXB. They are active only for Bus 0A.
NOTE
These signals, and the associated PHOLDA# and WSC# protocols, cannot be used with the PXB in
external arbiter mode.
PHOLD#
PHLDA#
PCI Hold
PCI I
This signal is the PIIX4E’s request for the PCI bus.
PCI Hold Acknowledge
PCI O
This signal is driven by the PXB to grant PCI bus ownership to the PIIX4E.
Intel® 450NX PCIset
2-11
2. Signal Descriptions
WSC#
Write Snoop Complete
PCI O
This signal is asserted active to indicate completion of snoop activity on the
system bus on the behalf of the last PCI-DRAM write transaction, and that it
is safe to send the APIC interrupt message.
2.5 Memory Subsystem Interface
The memory subsystem is comprised of the DRAM arrays and the associated RCGs and
MUXs. There is the external interface (between the MIOC and the memory subsystem), and
the internal interface (between the various parts of the memory subsystem.)
2.5.1
External Interface
BANK[2:0]#
Bank Selects
AGTL+ MIOC→ RCG
These signals indicate which memory bank will service this access.
BANK[2:0]# are connected to all RCGs on both memory cards.
CARD[1:0]#
Card Selects
AGTL+ MIOC→ RCG
These signals indicate which memory card will service this access. Valid
®
patterns in the Intel 450NX PCIset are 01b=card0 and 10b=card1, allowing
CARD[0]# to be connected only to card 0 and CARD[1]# to be connected only
to card 1. Each CARD signal is connected to all RCGs on the given memory
card.
CMND[1:0]#
CSTB#
Access Command
AGTL+ MIOC→ RCG
These signals encode the command of the current operation. CMND[1:0]# are
connected to all RCGs on both memory cards.
Command Strobe
AGTL+ MIOC→ RCG
This strobe, when activated, indicates the initiation of an access. This signal is
connected to all RCGs on both memory cards.
MA[13:0]#
Memory Address bus
AGTL+ MIOC→ RCG
These signals define the address of the location to be accessed in the DRAM.,
and are driven on two successive clock cycles to provide up to 28 bits of
effective memory address. The signals are connected to all RCGs on both
memory cards.
ROW#
Row Selects
AGTL+ MIOC→ RCG
These signals indicate which row in the selected memory bank will service
this access. These signals are connected to all RCGs on both memory cards.
GRCMPLT#
Global RCMPLT#
AGTL+, I/O, all RCGs
A “global” version of the RCMPLT(a,b)# signals, asserted coincident with
RCMPLT#, and by the same agent. Whereas each RCMPLT# signal connects
the RCGs on one card with the MIOC, the GRCMPLT# signal connects the
2-12
Intel® 450NX PCIset
2.5 Memory Subsystem Interface
RCGs across both cards while excluding the MIOC. This allows all RCGs to
monitor each request completion without placing undue loading on the
RCMPLT# signals.
MRESET#
Memory Subsystem Reset
AGTL+ MIOC→ RCG/MUX
This signal represents a hard reset of the memory subsystem. It is asserted
following PWRGD or upon the MIOC issuing a processor RESET due to
software invocation.
RCMPLTa#
RCMPLTb#
Request Complete
AGTL+ RCG→ MIOC
This signal, which is driven by the currently active RCG, indicates the
completion of a request into the memory array. Typically the “a” signal
connects the MIOC and all RCGs on Card #0, while the “b” signal connects
the MIOC and all RCGs on Card #1.
PHIT(a,b)#
RHIT(a,b)#
Page and Row Hit Status
AGTL+ RCG→ MIOC
These signals indicate what resource, if any, delayed the initiation of a read.
Typically the “a” signal connects the MIOC and all RCGs on Card #0, while
the “b” signal connects the MIOC and all RCGs on Card #1.
DSTBP[3:0]#
DSTBN[3:0]# Data Strobes
AGTL+ MUX↔ MIOC
This set of four signal-pairs are strobes which qualify the data transferred
between the MUX and MIOC. Each strobe pair qualifies 18 bits (two bytes
and two check bits), as follows:
DSTB[0]# qualifies MD[17:00]#.
DSTB[1]# qualifies MD[35:18]#.
DSTB[2]# qualifies MD[53:36]#.
DSTB[3]# qualifies MD[71:54]#.
In a 4:1 interleaved system, with 2 MUXs per card, DSTB[1:0]# strobes the
low MUX and DSTB[3:2]# strobes the high MUX. In a 2:1 interleaved system,
with only a single MUX per card, DSTB[1:0]# strobes the MUX, and
DSTB[3:2]# is not used.
MD[71:36]#
MD[35:00]#
Memory Data
AGTL+ MUX↔ MIOC
These signals are connected to the external datapath of the MUXs. Each MUX
provides 36 bits of the 72-bit datapath to the MIOC.
DCMPLTa#
DCMPLTb#
AGTL+ MUX→ MIOC/MUX
Data Transfer Complete
MIOC→M U X s
This signal is driven by the source of the data transfer: the MIOC for writes,
and the MUX for reads. DCMPLT# active indicates that the data transfer is
complete. Typically the “a” signal connects the MIOC and all MUXs on Card
#0, while the “b” signal connects the MIOC and all MUXs on Card #1.
DOFF[1:0]#
Data Offset
AGTL+ MIOC→ MUX
These two bits, when qualified by the DVALID# signal, define the initial
Qword access order for the data transfer. The result is that the critical chunk
is accessed first and the remaining chunks are accessed in Intel “Toggle”
order.
Intel® 450NX PCIset
2-13
2. Signal Descriptions
DSEL#
Data Card Select
AGTL+ MIOC→ MUX
This signal, when qualified by the DVALID# signal, selects which card the
memory transfer is coming from or destined towards. Each memory card uses
a single DSEL# input, sent to each MUX on the card. The MIOC provides two
DSEL# outputs (DSEL[1:0]#), one sent to each card.
DVALIDa#
DVALIDb#
Data Transfer Complete
AGTL+ MIOC→ MUX
This signal indicates that the DSEL[1:0]#, DOFF[1:0]#, and WDEVT# signals
are valid. Typically the “a” signal connects the MIOC and all MUXs on Card
#0, while the “b” signal connects the MIOC and all MUXs on Card #1.
GDCMPLT#
Global DCMPLT#
AGTL+, I/O, all MUXs
A “global” version of the DCMPLT(a,b)# signals, asserted coincident with
DCMPLT#, and by the same agent. Whereas each DCMPLT# signal connects
the MUXs on one card with the MIOC, the GDCMPLT# signal connects the
MUXs across both cards while excluding the MIOC. This allows all MUXs to
monitor each data completion without placing undue loading on the
DCMPLT# signals.
WDEVT#
Write Data Event
AGTL+ MIOC→ MUX
This signal, when qualified by the DVALID# signal, indicates the type of data
transfer command. If asserted, the command represents a write data transfer.
If deasserted, the command represents a read data transfer.
2.5.2
Internal Interface
2.5.2.1
RCG / DRAM Interface
Each RCG provides four sets of signals to drive four banks in the DRAM array. In each of the
following signal names, the "ß" indicates a set of signals per bank. Each RCG controls four
banks; therefore ß = A, B, C or D.
CASß(a,b,c,d)[1:0]#
Column Address Strobes
LVTTL RCG→ DRAM
These signals are used to latch the column address into the DRAMs. The “a”,
“b”, “c” and “d” versions are duplicates for load reduction.
ADDRß[13:0] DRAM Address
LVTTL RCG→ DRAM
ADDR is used to provide the multiplexed row and column address to DRAM.
RASß(a,b,c,d)[1:0]#
Row Address Strobe
LVTTL RCG→ DRAM
The RAS signals are used to latch the row address into the DRAMs. Each
signal is used to select one DRAM row. The 1:0 signals indicate which row
within the bank. The “a”, “b”, “c” and “d” versions are duplicates for load
reduction.
WEß(a,b)#
Write Enable Signal
LVTTL RCG→ DRAM
WE# is asserted during writes to main memory. The “a” and “b” versions are
duplicates for load reduction.
2-14
Intel® 450NX PCIset
2.6 Expander Interface
2.5.2.2
DRAM / MUX Interface
Q0D[35:0]
Q1D[35:0]
Q2D[35:0]
Q3D[35:0]
Memory Data, Interleave 0
LVTTL DRAM↔ MUX
These signals are connected to the output of the DRAMs. This is one-half of a
Quad-word and is connected to interleave zero.
Memory Data, Interleave 1
These signals are connected to the output of the DRAMs. This is one-half of a
Quad-word and is connected to interleave one.
LVTTL DRAM↔ MUX
Memory Data, Interleave 2
These signals are connected to the output of the DRAMs. This is one-half of a
Quad-word and is connected to interleave two.
LVTTL DRAM↔ MUX
Memory Data, Interleave 3
LVTTL DRAM↔ MUX
These signals are connected to the output of the DRAMs. This is one-half of a
Quad-word and is connected to interleave three.
2.5.2.3
RCG / MUX Interface
AVWP#
LDSTB#
LRD#
Advance MUX Write Path Pointers
This signal is activated by an RCG after performing a memory write.
AGTL+ RCG→ MUX
Load Data Strobe
AGTL+ RCG→ MUX
This signal controls when read data is latched from the DRAM data bus.
Load Read Data
AGTL+ RCG→ MUX
This signal indicates when read data is ready to load from the DRAMs.
WDME#
Write Data to Memory Enable
AGTL+ RCG→ MUX
This signal enables the MUXes to drive write data to the DRAMs.
2.6 Expander Interface
The MIOC component has two Expander interfaces, one for each of the two PXBs supported
®
by Intel 450NX PCIset. These two high speed, low latency interfaces are identified as the X0
bus and the X1 bus groups.
Each signal name includes a “p”, indicating the Expander port. On the MIOC, p = 0 or 1,
designating one of the two interfaces. On the PXB, p is not used.
XpADS#
Address / Data Strobe.
AGTL+ MIOC↔ PXB
Bidirectional signal asserted by the sending agent during data transmission.
XpBE[1:0]#
Byte Enables.
AGTL+ MIOC↔ PXB
Bidirectional signals indicating valid bytes during the data phases of a
transmission.
Intel® 450NX PCIset
2-15
2. Signal Descriptions
XpD[15:0]#
Datapath
AGTL+ MIOC↔ PXB
This bidirectional datapath is used to transfer addresses and data between the
MIOC and the PCI Expander.
XpHRTS#
Host Request to Send.
AGTL+ MIOC→ PXB
Request to use the bidirectional Expander bus sent from MIOC to PXB,
synchronous to HCLKIN.
XpHSTBP#
XpHSTBN#
Host Strobes
AGTL+ MIOC→ PXB
This pair of opposite-phase strobes are used by the PXB to latch and
synchronize incoming data.
XpPAR#
Bus Parity.
AGTL+ MIOC↔ PXB
Bidirectional signal indicating even parity across XD[15:0] and XBE[1:0].
XpXRTS#
Expander Request to Send.
AGTL+ PXB→ MIOC
Request to use the bidirectional Expander bus sent from PXB to MIOC,
synchronous to HCLKIN.
XpXSTBP#
XpXSTBN#
Expander Strobes
AGTL+ PXB→ MIOC
This pair of opposite-phase strobes are used by the MIOC to latch and
synchronize incoming data.
Support Signals
XpBLK
Block Counters.
AGTL+ MIOC→ PXB
This signal is asserted when the Performance Counter Master Enable bit in
the MIOC’s CONFIG register is set, and is used to affect a nearly
simultaneous stop/start of the performance counters across both the MIOC
and all PXBs.
XpCLK
Host Clock.
CMOS MIOC→ PXB
This is the primary clock source provided to the PXB, analogous to HCLKIN
for the MIOC, RCG and MUX. Inside the PXB, it is divided by 3 to produce a
PCI clock output at 33.33 MHz from an HCLKIN of 100 MHz.
XpCLKB
Host Clock, 2nd Version.
CMOS MIOC→ ext
This is a duplicate of the XpCLK signal, to be used in maintaining PLL
synchronization in the MIOC. See XpCLKFB below.
XpCLKFB
Host Clock, Feedback.
CMOS ext→ MIOC
This signal is a length-matched copy of the XpCLK signal sent to the PXB,
used to maintain PLL synchronization in the MIOC. The XpCLKB signal is
length-matched to the XpCLK’s path to the PXB, then returned to the MIOC
as the XpCLKFB input.
XpIB
Driving Inbound.
AGTL+ PXB→ ext
This active-high signal is asserted when the PXB is driving data over the
Expander bus. This pin is not connected to the MIOC.
XpRST#
PXB Reset.
AGTL+ MIOC→ PXB
This signal issues a hard reset of the PXB, including the dependent PCI buses.
2-16
Intel® 450NX PCIset
2.7 Common Support Signals
XpRSTB#
PXB Reset, 2nd Version.
AGTL+ MIOC→ ext
This is a duplicate of the XpRST# signal, to be used in maintaining PLL
synchronization in the MIOC. See XpRSTFB# below.
XpRSTFB#
PXB Reset, Feedback.
AGTL+ ext→ MIOC
The XpRSTB# signal is length-matched to the XpRST#’s path to the PXB,
then returned to the MIOC as the XpRSTFB# input.
2.7 Common Support Signals
2.7.1
JTAG Interface
®
All four components in the Intel 450NX PCIset have a JTAG Test Access Port (TAP) to allow
access to internal registers and perform boundary scan. Each interface is identical.
TCK
Test Clock
2.5V I
Test Clock is used to clock state information and data into and out of the
device during boundary scan.
TDI
Test Data Input
2.5V I
Test Input is used to serially shift data and instructions into the TAP.
TDO
TMS
TRST#
Test Output
Test Output is used to shift data out of the device.
2.5V OD
2.5V I
Test Mode Select
Test Mode Select is used to control the state of the TAP controller.
Test Reset
2.5V I
Test Reset is used to reset the TAP controller logic.
2.7.2
Reference Signals
All four components have the following support signals to provide voltage references or
compensation for the AGTL+ interfaces or the PLL circuitry.
CRES[1:0]
VCCA (n)
I/O Buffer Compensation Resistor Terminals
Analog I
For correct component operation an external 768 ohm resistor must be
connected between CRES1 and CRES0. This resistor should have a
minimum precision of 1%.
PLL Analog Voltage
Analog I
This pin is an independent power supply for a PLL. In normal operation, this
pin provides power to the PLL, and requires special decoupling (refer to
Electrical Characteristics).
Intel® 450NX PCIset
2-17
2. Signal Descriptions
VREF (n)
AGTL+ Reference Voltage
Analog I
This is the reference voltage derived from the termination voltage to the pull-
up resistors. The MIOC has 6 VREF pins, while the PXB, RCG and MUX each
have 2 VREF pins.
2.8 Component-Specific Support Signals
2.8.1
MIOC
CRESET#
Clock Selection Reset.
LVTTL O
This is a delayed version of the RESET# signal provided to the processors.
This signal is asserted asynchronously along with RESET#, but is deasserted
two system bus clocks following the deassertion of RESET#.
ERR[1:0]#
Error Code
LVTTL I/OD
These pins reflect irrecoverable errors detectable by the Intel 450NX PCIset.
ERR Error Type Associated Error s Flags
00 No error
01 PCIset Internal Error
10 Multi-Bit Memory Error Multi-Bit Memory ECC error
Expander Bus Parity
11 System Bus Error
Address Parity, Request Parity, Protocol
Violation, BERR, Multi-Bit Host ECC error
HCLKIN
INTREQ#
PWRGD
Host Clock In
2.5V I
This pin receives a buffered system clock. This is a single trace from the clock
synthesizer to minimize clock skew.
Interrupt Request
LVTTL O
This pin is asserted by the MIOC when an internal event occurs and sets a
status flag, and that flag has been configured to request an interrupt.
Power Good
LVTTL I
This pin should be connected to a 3.3 V version of the system’s power good
indicator, and should be asserted only after all power supplies and clocks
have reached their stable references and been stable for at least 1 msec.
PWRGDB
RESET#
Buffered Power Good
A buffered (but not synchronized) version of the PWRGD input, which is
used to drive the PWRGD input on each PXB in the system.
LVTTL O
Reset
AGTL+ I/O
In normal operation, this signal is an output. The MIOC will reset the system
bus either on power-up or when programmed through the Reset Control
register.
2-18
Intel® 450NX PCIset
2.8 Component-Specific Support Signals
SMIACT#
SMI Active.
LVTTL O
This signal provides a visible indicator that the system has entered System
Management Mode.
2.8.2
PXB
INTRQ(A,B)# Interrupt Requests
PCI OD
These pins are asserted by the PXB when an internal event occurs and sets a
status flag, and that flag has been configured to request an interrupt. There is
one pin for each side (A,B) of the PXB. The signals may be connected to the
standard PCI bus interrupt request lines.
PAMON[1:0]#
PBMON[1:0]# Performance Monitors
LVTTL I/OD
These pins track the two performance monitoring counters associated with
each PCI bus (a,b) in the PXB. PMON[0] tracks the PMD[0] counter while
PMON[1] tracks the PMD[1] counter.
PIIXOK#
PWRGD
PIIX Reset Complete.
This signal is tied to the PIIX’s CPURST output, and is used to detect when
the PIIX completes its reset functions.
LVTTL I
Power Good
LVTTL I
This input should be driven from the MIOC's PWRGDB output.
2.8.3
RCG
BANKID#
Bank Identifier
LVTTL I
This strapping pin should be tied high (deasserted), or have an external
pullup.
DR50H#
50ns DRAM “Here”.
LVTTL I
This strapping pin selects between 60ns and 50ns DRAM timings for this
RCG.
Deasserted: 60ns timings will be used.
Asserted:
50ns timings will be used.
DR50T#
HCLKIN
50ns DRAM “There”.
This strapping pin should match the DR50H# strapping pin described above.
LVTTL I
Host Clock In
2.5V I
This pin receives a buffered system clock.
2.8.4
MUX
HCLKIN
Host Clock In
2.5V I
This pin receives a buffered system clock.
Intel® 450NX PCIset
2-19
2. Signal Descriptions
2-20
Intel® 450NX PCIset
Register Descriptions
3
®
The Intel 450NX PCIset internal registers (both I/O Mapped and Configuration registers) are
accessible by the processor. Each MIOC, and each PCI bus in each PXB has an independent
configuration space. This chapter provides detailed descriptions of each register.
3.1 Access Restrictions
Register Attributes
Read Only
Writes to this register have no effect.
Read/Write
Data may be read from and written to this register. Selected bits in the
register may be designated as "read-only"; such bits are not affected by data
writes to the register.
Read/Clear
Sticky
Data may be read from the register. A data write operates strictly as a clear:
Data in this register remains valid and unchanged, during and following any
reset except the power-good reset.
3.2 I/O Mapped Registers
®
The Intel 450NX PCIset contains two registers that reside in the processor I/O address space:
the Configuration Address (CONFIG_ADDRESS) Register and the Configuration Data
(CONFIG_DATA) Register. The Configuration Address Register enables/disables the
configuration space and determines what portion of configuration space is visible through the
Configuration Data window.
3.2.1
CONFIG_ADDRESS: Configuration Address Register
I/O Address:
Default Value:
CF8h [Dword]
00000000h
Size:
32 bits
Attribute: Read/Write
The CONFIG_ADDRESS register contains the Bus Number, Device Number, Function
Number, and Register Number for which a subsequent configuration access is intended.
Intel® 450NX PCIset
3-1
3. Register Descriptions
Bits
Description
31
Configuration Enable (CFGE).
When this bit is set to 1 accesses to PCI configuration space are enabled. If this bit is
reset to 0 accesses to PCI configuration space are disabled.
30:24 reserved (0)
23:16 Bus Number.
The Bus Number field selects which PCI bus should receive the configuration cycle.
The system bus and the compatibility PCI bus (PCI Bus 0A) are both accessed using
Bus Number 0; which bus is accessed depends on the Device Number.
15:11 Device Number.
This field selects one agent on the PCI bus selected by the Bus Number. On Bus
Number 0, Device Numbers 0-15 are on the compatibility PCI bus (PCI Bus 0A), while
Device Numbers 16-31 refer to devices on the system bus, including the Intel 450NX
PCIset itself and any Third Party Agents which use this configuration mechanism.
No.
Device
No.
Device
No.
Device
No.
Device
10h MIOC
14h PXB 1, Bus a 18h reserved
15h PXB 1, Bus b 19h reserved
1Ch Third Party Agent
1Dh Third Party Agent
1Eh Third Party Agent
1Fh n/a
11h reserved
12h PXB 0, Bus a 16h reserved
13h PXB 0, Bus b 17h reserved
1Ah reserved
1Bh reserved
10:8
7:2
Function Number.
The 450NX PCIset devices are not multi-function devices, and therefore this field
should always be "0" when accessing them.
Register Number.
This field selects one register within a particular Bus, Device, and Function as
specified by the other fields in the Configuration Address Register.
1:0
reserved (0)
3.2.2
CONFIG_DATA: Configuration Data Register
I/O Address:
Default Value:
CFCh
00000000h
Size:
32 bits
Attribute: Read/Write
The portion of configuration space that is referenced by CONFIG_DATA is determined by the
contents of CONFIG_ADDRESS.
Bits
Description
31:0
Configuration Data Window (CDW).
If bit 31 of CONFIG_ADDRESS is 1 any I/O reference that falls in the CONFIG_DATA
I/O space will be mapped to configuration space using the contents of
CONFIG_ADDRESS.
3-2
Intel® 450NX PCIset
3.3 MIOC Configuration Space
3.3 MIOC Configuration Space
1
Table 3-1: MIOC Configuration Space
DID
VID
00h
04h
08h
0Ch
10h
14h
18h
1Ch
DBC 01
DBC 03
DBC 05
DBC 07
DBC 09
DBC 11
DBC 13
DBC 15
DBC 00
DBC 02
DBC 04
DBC 06
DBC 08
DBC 10
DBC 12
DBC 14
80h
84h
88h
8Ch
90h
94h
98h
9Ch
A0h
A4h
A8h
ACh
B0h
B4h
CLASS
HDR
RID
RCGP
Reserved
REFRESH
MEA1 MEA0
24h
28h
2Ch
30h
MEL1
HEL1
MEL0
HEL0
34h
38h
ECCMSK ECCCMD B8h
BCh
3Ch
CHKCON
RC
CONFIG
ERRSTS
40h
ROUTE0
TCAP0
TCAP1
TCAP2
TCAP3
SUBA0
SUBB1
C0h
C4h
ERRCMD
44h
BUFSIZ
48h
ROUTE1
C8h
CVCR
CVDR
4Ch
CCh
TOM
50h
54h
BUSNO1
SUBB0
BUSNO0 D0h
SUBA1 D4h
D8h
LXGT
LXGB
DEVMAP
HXGB
HXGT
MAR0
MAR4
58h
PMD0
PMR0
PMD1
PMR1
PME0
5Ch
PMD0
PMD1
DCh
E0h
E4h
E8h
ECh
F0h
F4h
F8h
FCh
MAR2
MAR6
MAR1
MAR5
GAPEN 60h
MAR3
64h
68h
6Ch
70h
74h
78h
7Ch
IOAR
IOABASE
PME1
SMRAM
MMBASE
MMR0
MMR1
MMR3
IOR
MMR2
ISA
1. The first 64 bytes are predefined in the PCI Specification. All other locations are defined specifically for the
component of interest.
Intel® 450NX PCIset
3-3
3. Register Descriptions
Table 3-1 illustrates the MIOC’s Configuration Space Map. Many of these registers affect both
host-initiated transactions and PCI-initiated transactions, and are therefore duplicated in both
the MIOC and PXB Configuration Spaces. It is software’s responsibility to ensure that both
sets of registers are programmed consistently to achieve correct operation.
3.3.1
BUFSIZ: Buffer Sizes
Address Offset: 48-4Ah
Default Value: 304310h
Size:
24 bits
Attribute: Read Only
Bits
Description
23:18 Inbound Write Transaction Capacity.
Total number of inbound write transactions, per Expander Port, that can be accepted
by the MIOC.
Value=12.
17:12 Inbound Read Transaction Capacity.
Total number of inbound read transactions, per Expander Port, that can be accepted
by the MIOC.
Value=4.
11:6
5:0
Inbound Write Data Buffer Capacity.
Total number of data buffers, per Expander Port, available in the MIOC for use by
inbound write transactions, in increments of 32 bytes.
Value=12.
Inbound Read Data Buffer Capacity.
Total number of data buffers, per Expander Port, available in the MIOC for use by
inbound read transactions, in increments of 32 bytes.
Value=16.
3-4
Intel® 450NX PCIset
3.3 MIOC Configuration Space
3.3.2
BUSNO[1:0]: Lowest PCI Bus Number, per PXB
Address Offset: D0h, D3h
Default Value: 00h each
Size:
8 bits each
Attribute: Read/Write
The MIOC supports two Expander Ports; each can support one PXB. PXB #0 is connected to
Expander Port #0, and PXB #1 is connected to Expander Port #1. Each PXB supports one or
two PCI buses, connected to PCI Ports “A” and “B”. The PCI bus connected to Port #0A must
be the compatibility PCI bus from which a system boots.
Three registers (BUSNO, SUBA and SUBB) define the bus hierarchy for each PXB.
BUSNO[0]
SUBA[0]
SUBB[0]
Holds the PCI-bus-number of the bus connected to PXB #0 Bus #A. This must
be set to 0.
Holds the PCI-bus-number of the highest subordinate bus under PXB #0 Bus
#A. The PCI bus number for PXB #0 Bus #B is SUBA[0]+1.
Holds the PCI-bus-number of the highest subordinate bus under PXB #0 Bus
#B. This also represents the highest PCI-bus-number accessible from PXB #0.
BUSNO[1]
SUBA[1]
Holds the PCI-bus-number of the bus connected to PXB #1 Bus #A.
Holds the PCI-bus-number of the highest subordinate bus under PXB #1 Bus
#A. The PCI bus number for PXB #1 Bus #b is SUBA[1]+1.
SUBB[1]
Holds the PCI-bus-number of the highest subordinate bus under PXB #1 Bus
#B. This also represents the highest PCI-bus-number accessible from PXB #1
(and therefore the Intel 450NX PCIset). If PXB#1 is not in use, program this
register to 0.
If PXB i is operating in 64-bit bus mode, SUBB[i] must equal SUBA[i].
Bits
Description
7:0
PCI Bus Number.
NOTE
Inactive PXBs should be disabled by writing the corresponding Reset Expander Port bit in the RC
register and resetting the corresponding "Device present" bit in the DEVMAP register.
3.3.3
CHKCON: Check Connection
Address Offset: 43h
Default Value: 10h
Size:
8 bits
Attribute: Read/Write
Bits
Description
7:6
reserved
Intel® 450NX PCIset
3-5
3. Register Descriptions
5
4
Live Port #1 Flag.
If set, the port is "live".
Default=0.
Live Port #0 Flag.
If set, the port is "live."
Default=1.
3:2
1
reserved
Test Port #1 Enable.
Setting this enable triggers the check connection protocol for port 1.
Default=0.
0
Test Port #0 Enable.
Setting this enable triggers the check connection protocol for port 0.
Default=0.
NOTE
Setting both Test Port #1 Enable and Test Port #0 Enable simultaneously is prohibited, and will have
unpredictable results, up to and including system hangs requiring a full system reset. Inactive PXBs
should be disabled by writing the corresponding Reset Expander Port bit in the RC register. Transactions
sent to inactive PXBs can result in system hangs.
3.3.4
CLASS: Class Code Register
Address Offset: 09 - 0Bh
Default Value: 060000h
Size:
24 bits
Attribute: Read Only
Bits
Description
23:16 Base Class
For the MIOC, this field is hardwired to 06h.
15:8
7:0
Sub-Class
For the MIOC, this field is hardwired to 00h.
Register-Level Programming Interface
For the MIOC this field is hardwired to 00h.
3.3.5
CONFIG: Software-Defined Configuration Register
Address Offset: 40-41h
Default Value: 1000h
Size:
16 bits
Attribute: Read/Write
Bits
Description
15:13 reserved (0)
3-6
Intel® 450NX PCIset
3.3 MIOC Configuration Space
12
11
Outbound Fairness Disable.
When this bit is clear, Host-PCI writes and reads that receive a retry by the MIOC
follow a fairness algorithm to guarantee that retried transactions receive first priority
before new transactions. If set, Host-PCI writes and reads are serviced in the order
first observed without regard to retry history. Default=1.
Performance Counter Master Enable (PCME).
This bit provides a mechanism to (nearly) simultaneously freeze or start the
performance counters across both the MIOC and PXBs.
If this bit is cleared the MIOC’s and PXB’s performance counters will not increment
If set the MIOC’s and PXB’s performance counters resume normal operation.
Default = 0.
10
9
reserved (0)
Third Party Support Disable
If set, performance optimizations are enabled that may result in coherency violations
in the presence of a third party agent. This bit should be clear for systems with TPAs.
Default = 0.
8
External Arbiter Enable.
If set, access to the system bus is controlled by an external arbiter. If cleared, the
MIOC’s internal arbiter is used. Default=0.
7
6
WC Write Post During I/O Bridge Access Enable (UWPE).
This bit should be cleared for normal operation. Default=0.
Outbound I/O Write Posting Enable.
If set, Host-PCI I/O writes will be posted. If cleared, Host-PCI I/O writes will not be
posted. In normal operation, this enable should be set. Default=0.
5
4
Read-Around-Write Enable (RAWE).
If RAWE is set, it enables the read-around-write capability for the MIOC and memory
subsystem. If cleared, read accesses will not advance past any previously posted
writes. In normal operation, this enable should be set. Default=0.
ISA Expansion Aliasing Enable.
If set, every I/O access with an address in the range x100-x3FFh, x500-x7FFh, x900-
xBFF and xD00-xFFFh is internally aliased to the range 0100-03FFh before any other
address range checking is performed. This bit only affects routing, the unmasked
address is passed to the PCI bus. Default=0.
3
2
reserved (0)
Card to Card Interleave Enable.
If set, Host or PCI accesses to memory are distributed to both memory cards on a
cache line granularity. This provides a performance enhancement for systems which
utilize two memory cards. When this bit is clear, C2C interleaving is disabled. Default
= 0.
Intel® 450NX PCIset
3-7
3. Register Descriptions
1:0
Memory Address Bit Permuting.
The MIOC supports cache-line permuting across banks. This field controls the type of
permuting used, as follows:
00b No permuting.
01b 2-way Permuting.
10b 4-way Permuting.
11b reserved
Default=0.
3.3.6
CVCR: Configuration Values Captured on Reset
Address Offset: 4E-4Fh
Default Value: 0000h
Size:
16 bits
Attribute: Read-Only
This register captures the configuration values driven on A#[15:0] at the trailing edge of
RESET#. This allows an external device to override the default values provided by the MIOC
via its CVDR register.
Bits
Description
15:13 reserved (0)
12:11 APIC Cluster ID.
Captured from A#[12:11]. Represents the APIC Cluster identifier.
10
9
Enable BINIT# Input.
Captured from A#[10]. If set, the MIOC will observe the assertion of the BINIT# input.
Further details on BINIT# processing may be found in the ERRCMD register.
Enable BERR# Input.
Captured from A#[9]. If set, the MIOC will observe the assertion of the BERR# input.
Further details on BERR# processing may be found in the ERRCMD register.
8
Enable AERR# Input.
Captured from A#[8]. If set, the MIOC will observe the assertion of the AERR# input.
Further details on AERR# processing may be found in the ERRCMD register. If this
enable is asserted, then the BINIT# Driver Enable in the ERRCMD register must also
be asserted.
7
6
In-Order Queue Depth 1.
Captured from A#[7]. If set, the MIOC will limit its In-Order Queue Depth to 1 (no
pipelining support), instead of the usual 8.
1M Power-on Reset Vector.
Captured from A#[6]. This bit has no meaning for the MIOC. If set, all Pentium II
®
Xeon™ processors on the system bus will use the 1MB-1 (000FFFFFh) reset vector,
instead of their usual 4 GB-1 (FFFFFFFFh) vector.
5
Enable FRC Mode.
Captured from A#[5]. This bit has no meaning for the MIOC. If set, all Pentium II
Xeon processors on the system bus will enter FRC-enabled mode.
4:0
reserved (0)
3-8
Intel® 450NX PCIset
3.3 MIOC Configuration Space
3.3.7
CVDR: Configuration Values Driven On Reset
Address Offset: 4C-4Dh
Default Value:
0000h
Size:
16 bits
Attribute: Read/Write, Sticky
During RESET# assertion, and for one host clock past the trailing edge of RESET#, the MIOC
drives the contents of this register onto the A[15:0]# pins.
Bits
Description
15:13 reserved (0)
12:11 APIC Cluster ID.
This two-bit field representing the APIC Cluster identifier is driven to A#[12:11]
during RESET#. Note that there are no pins to input the cluster ID; software must
explicitly load the value into this register. Default=0.
10
9
reserved (0)
Enable BERR# Input.
If set, A#[9] will be asserted during RESET#, and all system bus agents will enable
BERR# observation. Default=0.
8
7
Enable AERR# Input.
If set, A#[8] will be asserted during RESET#, and all system bus agents will enable
AERR# observation. Default=0.
In-Order Queue Depth 1.
If set, A#[7] will be asserted during RESET#, and all Pentium II Xeon™ processors
®
on the system bus will limit their In-Order Queue Depth to 1 (no pipelining support),
instead of their usual 8. Default=0.
6
1M Power-on Reset Vector.
If set, A#[6] will be asserted during RESET#, and all Pentium II Xeon processors on
the system bus will use the 1MB-1 (000FFFFFh) reset vector, instead of their usual
4 GB-1 (FFFFFFFFh) vector. Default=0.
5
Enable FRC Mode.
If set, A#[5] will be asserted during RESET#, and all Pentium II Xeon processors on
the system bus will enter FRC enabled mode. Default=0.
4:0
reserved (0)
3.3.8
DBC[15:0]: DRAM Bank Configuration Registers
Address Offset: 80-9Fh
Default Value:
A200h each
Size:
16 bits each
Attribute: Read/Write
The Intel 450NX PCIset memory subsystem supports at most two RCGs (one RCG and four
banks per card) for a maximum of 8 GB of memory. This corresponds to DBC[0:3] on the first
card and DBC[8:11] on the second card.
Intel® 450NX PCIset
3-9
3. Register Descriptions
Unused DBC registers should be configured as inactive, with the Bank Present bit cleared and
the TOB field set to that of the previous bank, indicating that the amount of memory in that
bank is zero.
Bits
Description
15
4:1 Interleave.
If set, bank is a 4:1 interleave. If cleared, bank is a 2:1 interleave.
Default=1.
14
13
Single Row.
This bit is set if the bank contains only a single row. If cleared, the bank contains two
rows; both rows must be configured identically. Default=0.
Bank Present.
This bit is set to indicate that this memory bank is present, and refresh cycles should
be issued to the bank. This bit must be cleared if this bank is not physically present.
Default=1.
12:10 reserved (0)
9:0 Top of Bank (TOB).
This field contains the effective address of the top of memory in this bank and all lower
banks, and is used to determine which bank is selected. Each TOB field specifies the
amount of memory, in 32 MB chunks, contained in this bank and all lower banks.
Unpopulated banks must have their TOB set equal to that of the previous bank
indicating that the amount of memory in that bank is zero.
Default = 200h, each.
3.3.9
DEVMAP: System Bus PCI Device Map
Address Offset: D6-D7h
Default Value: 0005h
Size:
16 bits
Attribute: Read/Write, Read Only
This register indicates which PCI devices on the system bus have active configuration spaces.
At reset, DEVMAP is initialized with all devices not present except the MIOC and the
compatibility PCI bus.
Bits
15
Description
reserved (0)
14:0
PCI Bus #0, Device [30:16] Present.
Each bit corresponds to a device on PCI Bus #0 (numbers 16-30). If set, the device is
present in the system and is expected to respond to configuration cycles directed to it.
Bit 0 is hardwired "on", and is read-only.
Default=0005h (MIOC, PCI #0A present)
3-10
Intel® 450NX PCIset
3.3 MIOC Configuration Space
3.3.10 DID: Device Identification Register
Address Offset: 02 - 03h
Size:
16 bits
Default Value:
84CAh
Attributes: Read Only
Bits
Description
15:0
Device Identification Number.
The value 84CAh indicates the Intel 450NX PCIset MIOC.
®
3.3.11 ECCCMD: ECC Command Register
Address Offset: B8h
Default Value:
00h
Size:
8 bits
Attribute: Read/Write
This register controls the Intel 450NX PCIset responses to ECC errors on data retrieved from
the memory subsystem or received from the system bus.
Bits
Description
7
6
reserved (0)
System Bus, Report Multi-Bit Errors (HRM).
If set, the Intel 450NX PCIset will log multiple-bit ECC errors on data received from
®
the system bus in the appropriate HEL register. If the BERR# driver is enabled,
BERR# will also be asserted. Default=0.
5
4
3
System Bus, Report Single-Bit Errors (HRS).
If set, on detection of a single-bit ECC error on data received from the system bus the
Intel 450NX PCIset will log the error in the appropriate HEL register, and assert the
INTREQ# signal. Default=0.
System Bus, Correct Single-Bit Errors (HCS).
If set, on detection of a single-bit ECC error on data received from the system bus the
Intel 450NX PCIset will correct the data and generate a new ECC code before writing
the data into memory. Default=0.
Memory, Scrub Single-Bit Errors (MSS).
If set, on detection of a single-bit ECC error on data read from the memory array the
Intel 450NX PCIset will perform a scrub operation to correct the location in the
memory. The MCS bit in this register must be set for this feature to be effective.
Default=0.
2
Memory, Report Multi-Bit Errors (MRM).
If set, on detection of a multiple-bit ECC error on data read from the memory array
the Intel 450NX PCIset will log the error in the appropriate MEL and MEA registers. If
the BERR# driver is enabled, BERR# will also be asserted. Default=0.
Intel® 450NX PCIset
3-11
3. Register Descriptions
1
0
Memory, Report Single-Bit Errors (MRS).
If set, on detection of a single-bit ECC error on data read from the memory array the
Intel 450NX PCIset will log the error in the appropriate MEL and MEA registers, and
assert the INTREQ# signal. Default=0.
Memory, Correct Single-Bit Errors (MCS).
If set, on detection of a single-bit ECC error on data read from the memory array the
Intel 450NX PCIset will correct the data and generate a new ECC code before
returning the data to the requestor. Default=0.
3.3.12 ECCMSK: ECC Mask Register
Address Offset: B9h
Default Value: 00h
Size:
8 bits
Attribute: Read/Write
This register is used to test the ECC error detection logic in the memory subsystem. The
register is written with a masking function which is applied on subsequent writes to memory.
All subsequent writes into memory will store a masked version of the computed ECC.
Subsequent reads of the memory locations written while masked will return an invalid ECC
code. To disable testing, the mask value is left at 0h (default).
Bits
Description
7:0
ECC Generation Mask.
Each bit of the computed ECC is XOR’ed with the corresponding bit in this mask field
before it is stored in the memory array.
3.3.13 ERRCMD: Error Command Register
Address Offset: 46h
Default Value: 00h
Size:
8 bits
Attribute: Read/Write
This register controls the MIOC responses to various system and data errors.
Bits
7:6
5
Description
reserved (0)
BERR#-to-BINIT# Enable.
If set, on observation or assertion of BERR#, (and Enable BERR# Input is set) the MIOC
will also assert BINIT#.
Default=0.
4
Fast System Bus Time-out.
This bit controls the duration of a watchdog timer which is started at the end of the
system bus response phase. If this bit is set, the timer expires in 256 host cycles. If
17
cleared, the timer expires in 2 cycles.
Default=0.
3-12
Intel® 450NX PCIset
3.3 MIOC Configuration Space
3
2
1
0
BINIT# on System Bus Time-outs.
If this bit is set, and the BINIT# Driver Enable is set, the MIOC will assert BINIT# on a
system bus access time-out. Default=0.
AERR# Driver Enable.
If set, parity errors on the system bus address and request signals are reported by
asserting AERR#. Default=0.
BERR# Driver Enable.
If set, BERR# will be asserted for uncorrectable ECC errors on memory reads or data
arriving from the system data bus. Default=0.
BINIT# Driver Enable.
If set, BINIT# will be asserted upon detecting protocol violations on the system bus.
This enable should only be cleared for system boot. In normal operation, this enable
must be set. Default=0.
3.3.14 ERRSTS: Error Status Register
Address Offset: 44-45h
Default Value:
0000h
Size:
16 bits
Attribute: Read/Write Clear, Sticky
This register records error conditions detected in the address or controls of the system bus, or
in the MIOC itself. Recording of these error conditions is controlled via the ERRCMD register.
ERRSTS is sticky through reset, and bits will remain set until explicitly cleared by software
writing a 1 to the bit.
Bits
Description
15:13 reserved (0)
12
11
Received Hard Fail Response on System Bus.
This flag is set when the MIOC detects a Hard Fail response on the system bus. If the
BINIT# Driver Enable in the ERRCMD register is set, BINIT# is also asserted.
Expander Bus #1 Protocol Violation Flag.
This flag is set when the Expander Bus #1 interface receives unexpected data that the
MIOC is not prepared to service. If the BINIT# Driver Enable is set in the ERRCMD
register, BINIT# is also asserted.
10
Expander Bus #0 Protocol Violation Flag.
This flag is set when the Expander Bus #0 interface receives unexpected data that the
MIOC is not prepared to service. If the BINIT# Driver Enable is set in the ERRCMD
register, BINIT# is also asserted.
9
8
Performance Monitor #1 Event Flag.
This flag is set when the Performance Monitor #1 requests that an interrupt request be
asserted. While this bit is set, the INTREQ# line will be asserted.
Performance Monitor #0 Event Flag.
This flag is set when the Performance Monitor #0 requests that an interrupt request be
asserted. While this bit is set, the INTREQ# line will be asserted.
Intel® 450NX PCIset
3-13
3. Register Descriptions
7
6
reserved (0)
System Bus Time-out Flag.
This flag is set when the watchdog timer monitoring accesses on the system bus times
out. See the BINIT#-on-System-Bus-Time-outs Enable and the BINIT# Driver Enable in the
ERRCMD register.
5
4
Expander Bus 1 Parity Error Flag.
This flag is set when Expander Bus #1 reports a parity error on data inbound from the
PXB. This condition is a catastrophic fail and will also assert BINIT#.
Expander Bus 0 Parity Error Flag.
This flag is set when Expander Bus #0 reports a parity error on data inbound from the
PXB. This condition is a catastrophic fail and will also assert BINIT#.
3
2
BERR# Error Flag.
This flag is set when BERR# is detected asserted on the system bus.
Address Parity Error.
This flag is set upon detecting the assertion of AP#, indicating a parity error on the
system address signals. If the AERR# Driver Enable is set in the ERRCMD register,
AERR# is asserted. If the BINIT# Driver Enable is set in the ERRCMD register, BINIT#
is asserted.
1
0
Response Parity Error Flag.
This flag is set upon detecting the assertion of RP#, indicating a parity error on the
system bus response signals. If the BINIT# Driver Enable is set in the ERRCMD
register, BINIT# is also asserted.
Request Parity Error.
This flag is set upon detecting the assertion of RP#, indicating an error on ADS or
request signals. If the AERR# Driver Enable is set in the ERRCMD register, AERR# is
asserted. If the BINIT# Driver Enable is set in the ERRCMD register, BINIT# is asserted.
3.3.15 GAPEN: Gap Enables
Address Offset: 60h
Size:
8 bits
Default Value:
0Eh
Description
reserved (0)
ISA Space Enable.
Attribute: Read/Write
Bits
7
6
When set, the ISA Space address range is enabled. Memory-mapped accesses that fall
within this address range are forwarded to the compatibility PCI bus. If this bit is
cleared, accesses to this address range are handled normally. Default=0.
5
High Expansion Gap Enable.
When set, the High Expansion Gap (HXG) is enabled. Default=0.
3-14
Intel® 450NX PCIset
3.3 MIOC Configuration Space
4
3
Low Expansion Gap Enable.
When set, the Low Expansion Gap (LXG) is enabled. Default=0.
High BIOS Space Enable.
If set, a 2 MByte space is opened at location (4 GB - 2 MB), and accesses into this
address range will be directed to the compatibility PCI bus instead of memory.
Default=1.
2
High Graphics Adapter Space Enable.
If set, a 64 KB space is opened in the upper half of the Graphics Adapter portion of the
Low Compatibility Region (address range B_0000h-BFFFFh), and accesses into this
address range will be directed to the compatibility PCI bus instead of memory.
Default=1.
1
0
Low Graphics Adapter Space Enable.
If set, a 64 KB space is opened in the lower half of the Graphics Adapter portion of the
Low Compatibility Region (address range A_0000h-AFFFFh), and accesses into this
address will be directed to the compatibility PCI bus instead of memory. Default=1.
reserved (0)
3.3.16 HDR: Header Type Register
Address Offset: 0Eh
Size:
8 bits
Default Value:
00h
Attribute: Read Only
This register identifies the header layout of the configuration space. Writes to this register
have no effect.
Bits
Description
7
Multi-function Device.
The MIOC is not a multi-function device, and this bit is hardwired to 0.
6:0
Configuration Layout.
This field is hardwired to 00h, which represents the default PCI configuration layout.
3.3.17 HEL[1:0] Host Bus Error Log
Address Offset: B4-B7h
Size:
16 bits each
Default Value:
0000h each
Attribute: Read/Write, Sticky
These registers are loaded on the first and second ECC errors detected on data received from
the system bus. HEL[0] logs the first error, and HEL[1] logs the second. The registers hold
their data until reloaded due to a new error condition, or until they are explicitly cleared by
software or a power-good reset.
Intel® 450NX PCIset
3-15
3. Register Descriptions
Bits
Description
15:8
Syndrome.
Holds the calculated syndrome that identifies the specific bit in error.
7:2
1
reserved (0)
Multiple-Bit Error Logged (MBE).
This flag is set if the logged error was a multiple-bit (uncorrectable) error.
0
Single-Bit Error Logged (SBE).
This flag is set if the logged error was a single-bit (correctable) error.
3.3.18 HXGB: High Expansion Gap Base
Address Offset: 58-5Ah
Size:
24 bits
Default Value:
000000h
Attribute: Read/Write
Bits
Description
23:0
Gap Base Address.
This field specifies the A[43:20] portion of the gap’s base address, in 1 MB increments.
The A[19:0] portions of the gap’s base address are zero.
3.3.19 HXGT: High Expansion Gap Top
Address Offset: 5C-5Eh
Size:
24 bits
Default Value:
000000h
Attribute: Read/Write
Bits
Description
23:0
Gap Top Address.
This field specifies the A[43:20] portion of the gap’s highest address, in 1 MB
increments. The A[19:0] portion of the gap’s top address is FFFFFh.
3.3.20 IOABASE: I/O APIC Base Address
Address Offset: 68-69h
Default Value: 0FECh
Size:
16 bits
Attribute: Read/Write
Bits
15:12 reserved (0)
11:0 I/O APIC Base Address.
Description
This field specifies the A[31:20] portion of the I/O APIC Space’s base address, in 1 MB
increments. The A[43:32] and A[19:0] portions of the address are zero.
3-16
Intel® 450NX PCIset
3.3 MIOC Configuration Space
3.3.21 IOAR: I/O APIC Ranges
Address Offset: 6A-6Bh
Size:
16 bits
Default Value:
0000h
Attribute: Read/Write
Each of the three fields in the IOAR register specifies the highest APIC number (0-15) that
should be directed to that PCI bus, for buses 0A, 0B and 1A. All higher APIC ID are directed
to PCI Bus 1B.
Bits
Description
15:12 reserved (0)
11:8
7:4
PCI Bus #1A Highest APIC ID (BUS1A).
This field represents the highest APIC ID that should be directed to PCI Bus #1A.
PCI Bus #0B Highest APIC ID (BUS0B).
This field represents the highest APIC ID that should be directed to PCI Bus #0B.
3:0
PCI Bus #0A Highest APIC ID (BUS0A).
This field represents the highest APIC ID that should be directed to PCI Bus #0A.
3.3.22 IOR: I/O Ranges
Address Offset: 7E-7Fh
Size:
16 bits
Default Value:
0FFFh
Attribute: Read/Write
The IOR register defines the I/O range addresses for each PCI bus. These are specified in
sixteen 4 KB segments. The starting (base) address for PCI Bus #0A is 0h.
Bits
Description
15:12 reserved (0)
11:8
7:4
PCI Bus #1A Upper Address (BUS1A).
This field represents the A[15:12] portion of the highest I/O address that should be
directed to PCI Bus #1A. The A[11:0] portion of this address is FFFh.
PCI Bus #0B Upper Address (BUS0B).
This field represents the A[15:12] portion of the highest I/O address that should be
directed to PCI Bus #0B. The A[11:0] portion of this address is FFFh.
3:0
PCI Bus #0A Upper Address (BUS0A).
This field represents the A[15:12] portion of the highest I/O address that should be
directed to PCI Bus #0A. The A[11:0] portion of this address is FFFh.
If PXB x is operating in 64-bit bus mode, BUSxB must equal BUSxA.
Intel® 450NX PCIset
3-17
3. Register Descriptions
3.3.23 ISA: ISA Space
Address Offset: 7Ch
Size:
8 bits
Default Value:
00h
Attribute: Read/Write
This register defines the ISA Space address range. If enabled, memory-mapped accesses into
this address range will be forwarded to the compatibility PCI bus. This space is defined to
support ISA cards incapable of using the full 32-bit PCI address.
Bits
7:6
Description
reserved (0)
5:4
ISA Space Size.
This field specifies the size of the gap. Legal sizes are:
00b: 1 MB
01b: 2 MB
10b: 4 MB
11b: 8 MB
3:0
ISA Space Base Address.
This 4-bit field specifies the A[23:20] portion of the gap’s base address. The A[43:24]
and A[19:0] portions of the gap’s base address are zero.
3.3.24 LXGB: Low Expansion Gap Base
Address Offset: 54-55h
Default Value: 0000h
Size:
16 bits
Attribute: Read/Write
Bits
15:12 reserved (0)
11:0 Gap Base Address.
Description
This field specifies the A[31:20] portion of the gap’s base address, in 1 MB increments.
The A[43:32] and A[19:0] portions of the gap’s base address are zero.
3.3.25 LXGT: Low Expansion Gap Top
Address Offset: 56-57h
Default Value: 0000h
Size:
16 bits
Attribute: Read/Write
Bits
15:12 reserved (0)
11:0 Gap Top Address.
Description
This field specifies the A[31:20] portion of the gap’s highest address, in 1 MB
increments. The A[43:32] portion of the gap’s top address is zero, while the A[19:0]
portion of the gap’s top address is FFFFFh.
3-18
Intel® 450NX PCIset
3.3 MIOC Configuration Space
3.3.26 MAR[6:0]: Memory Attribute Region Registers
Address Offset: 61-67h
Default Value:
03h for MAR[0]
00h for all others
Size:
8 bits each
Attribute: Read/Write
Seven Memory Attribute Region (MAR) registers are used to program memory attributes of
various sizes in the 640 Kbyte-1 MByte address range. Each MAR register controls two
segments, typically 16 Kbyte in size. Each of these segments has an identical 4-bit field which
specifies the memory attributes for the segment, and apply to both host-initiated accesses and
PCI-initiated accesses to the segment.
Bits
7:6
5
Description
reserved (0)
Segment 1, Write Enable (WE).
When cleared, host-initiated write accesses are directed to the compatibility PCI bus.
When set, write accesses are handled normally according to the outbound access
disposition.
4
Segment 1, Read Enable (RE).
When cleared, host-initiated read accesses are directed to the compatibility PCI bus.
When set, read accesses are handled normally according to the
outbound access disposition.
3:2
1
reserved (0)
Segment 0, Write Enable (WE).
Identical to segment 1 WE, above.
0
Segment 0, Read Enable (RE).
Identical to segment 1 RE, above.
Table 3-2 summarizes the possible outcomes of the various Read Enable (RE) and Write
Enable (WE) combinations:
Table 3-2: MAR-controlled Access Disposition
Outbound
Write Read
PCI 0a PCI 0a
Outbound locked
Write Read
PCI 0a PCI 0a
Inbound
Write
WE,
RE
Read
00
unclaimed
unclaimed
unclaimed
1
2
01
10
11
PCI 0a
Memory
PCI 0a
PCI 0a
PCI 0a
Memory
1
1
2
Memory
Memory
PCI 0a
PCI 0a
Memory
unclaimed
1
1
1
2
2
Memory
Memory
Memory
Memory
Memory
1. Normally, the access will be directed to the DRAM. However, if this MAR region is overlapped by
an enabled expansion gap, the access will instead be left unclaimed on the system bus. A third-
party agent may then claim the access.
2. Normally, the access will be directed to the DRAM. However, if this MAR region is overlapped by
an enabled expansion gap, the access will instead be directed up to the system bus. A third-party
agent may then claim the access.
Intel® 450NX PCIset
3-19
3. Register Descriptions
3.3.27 MEA[1:0] Memory Error Effective Address
Address Offset: A8-A9h
Default Value: 00h each
Size:
8 bits each
Attribute: Read/Write, Sticky
These registers contain the effective address information needed to identify the specific
DIMM that produced the error.
Bits
Description
7
Card.
Holds the card number (0,1) where the suspect DIMM resides.
6:4
3
Bank.
Identifies the bank within the card (0..7) where the suspect DIMM resides.
Row.
Identifies the row within the bank (for double row DIMMs).
2
reserved (0)
1:0
Effective Address [4:3].
These two bits of the effective address indicate the "starting" Qword in the critical
order access. When combined with the chunk number of the error, as logged in the
MEL registers, this identifies the specific DIMM where the error occurred.
3.3.28 MEL[1:0] Memory Error Log
Address Offset: B0-B3h
Size:
16 bits each
Default Value:
0000h each
Attribute: Read/Write, Sticky
These registers are loaded on the first and second ECC errors detected on data retrieved from
the memory. MEL[0] logs the first error, and MEL[1] logs the second.
Bits
Description
15:8
Syndrome.
Holds the calculated syndrome that identifies the specific bit in error.
7:4
3:2
reserved (0)
Chunk Number.
Specifies which of the four possible chunks in the critical chunk ordered transfer the
error occurred in, from zero to three.
1
0
Multiple-Bit Error Logged (MBE).
This flag is set if the logged error was a multiple-bit (uncorrectable) error.
Single-Bit Error Logged (SBE).
This flag is set if the logged error was a single-bit (correctable) error.
3-20
Intel® 450NX PCIset
3.3 MIOC Configuration Space
3.3.29 MMBASE: Memory-Mapped PCI Base
Address Offset: 70-71h
Default Value:
0002h
Size:
16 bits
Attribute: Read/Write
The MMBASE register defines the starting address of the Memory-Mapped PCI Space, and
each MMR register defines the highest address to be directed to a PCI bus.
If PXB 0 is operating in 64-bit bus mode, MMR[0] must equal MMBASE.
If PXB 1 is operating in 64-bit bus mode, MMR[3] must equal MMR[2].
Bits Description
15:12 reserved (0)
11:0
PCI Space Base Address.
This field specifies the A[31:20] portion of the PCI space’s base address, in 1MB
increments. The A[43:32] and A[19:0] portions of the address are zero.
3.3.30 MMR[3:0]: Memory-Mapped PCI Ranges
Address Offset: 74-7Bh
Default Value:
0001h each
Size:
16 bits each
Attribute: Read/Write
These registers define the high addresses for addresses to be directed to the PCI space.
Bits Description
15:12 reserved (0)
11:0 PCI Space Top Address.
This field specifies the A[31:20] portion of the PCI space’s highest address, in 1 MB
increments. The A[43:32] portion of this address is zero, while the A[19:0] portion of
this address is FFFFFh.
3.3.31 PMD[1:0]: Performance Monitoring Data Register
Address Offset: D8-DCh, E0-E4h
Default Value:
0000000000h each
Size:
40 bits each
Attribute: Read/Write
Two performance monitoring counters are provided in the MIOC. The PMD registers hold the
performance monitoring count values. Each counter can be configured to reload the data
when it, or the other counter overflows.
Event selection is controlled by the PME registers, and the action performed on event
detection is controlled by the PMR registers. An additional Performance Counter Master Enable
(PCME) in the MIOC’s CONFIG register allows (nearly) simultaneous stopping/starting of all
counters in the MIOC and each PXB. The counters cannot be read or written coherently while
the counters are running.
Intel® 450NX PCIset
3-21
3. Register Descriptions
Bits
Description
Count Value.
39:0
3.3.32 PME[1:0]: Performance Monitoring Event Selection
Address Offset: E8-E9h, EA-EBh
Default Value: 0000h each
Size:
16 bits each
Attribute: Read/Write
Bits
15
Description
reserved (0)
Count Data Cycles
14
1: Count the request length of the selected transaction.
0: Count the selected event
13
reserved (0)
12:10 Initiating Agent Selection.
This field qualifies the tracking of bus transactions by limiting event detection to those
transactions issued by specific agents.
000 Symmetric Agent 0 (DID=0/000) 100 Any symmetric agent (DID=0/xxx)
001 Symmetric Agent 1 (DID=0/001) 101 Third party agent (DID=1/other)
®
010 Symmetric Agent 2 (DID=0/010) 110 Intel 450NX PCIset agent (DID=1/001)
011 Symmetric Agent 3 (DID=0/011) 111 Any agent
9:8
Transaction Destination Selection.
This field qualifies the tracking of bus transactions by limiting event detection to those
transactions directed to a specific resource.
1
00
01
Any
Main Memory
10
11
Not Third Party or Memory
Third party
1. The usual destination in this category is a PCI Target. Also included are Internal CFC/CF8
accesses, Branch trace messages, Interrupt acknowledge, and some special transactions.
7:6
5:0
Data Length Selection.
This field qualifies the tracking of bus transactions by limiting event detection to those
transactions of a specific length.
00 Any
01 Lines
10 Part-lines or partials
11 reserved
Event Selection.
This field specifies the basic system bus transaction, system bus signal assertion, or
memory event to be monitored.
Individual Bus Transactions
00 0000 Deferred Reply
00 0001 reserved
00 0010 reserved
00 0011 reserved
00 0100 I/O Read
00 0101 I/O Write
00 1000 reserved
00 1001 reserved
00 1010 Memory Read Invalidate
00 1011 reserved
00 1100 Memory Read Code
00 1101 Memory Writeback
3-22
Intel® 450NX PCIset
3.3 MIOC Configuration Space
00 0110 reserved
00 0111 reserved
00 1110 Memory Read
00 1111 Memory Write
Generic (Grouped) Bus Transactions
010 000 Any bus transaction
010 001 Any memory transaction
010 010 Any memory read
010 100 Any I/O transaction
010 101 Any I/O or memory transactions
010 110 Any I/O or memory read
010 111 Any I/O or memory write
010 011 Any memory write
Bus Signal Assertions
1,2
1,2
011 000 HIT
011 001 HITM
011 100 BNR
1,2
2
011 101 BPRI
1,2
2
011 010 RETRY
011 011 DEFER
011 110 LOCK
1,2
011 111 reserved
Memory Hits/Misses
100 000 Bank was idle
100 001 Waited for Row precharge
1,2
1,2
100 010 Waited for address lines
100 011 Hit open page
1,2
1,2
All other encodings are reserved.
Notes:
1. Counting data cycles is undefined for this selection.
2. The Agent, Destination and Length fields cannot be applied to this selection,
and should be programmed to "any".
3.3.33 PMR[1:0]: Performance Monitoring Response
Address Offset: DDh, E5h
Default Value:
00h each
Size:
8 bits each
Attribute: Read/Write
The PMR register specifies how the event selected by the corresponding PME register affects
the associated PMD register, the BP[1:0] pins, and the INTREQ# pin. Events defined by
PME[0] can be driven out BP0 and events defined by PME[1] can be driven out BP1.
Bits
Description
7:6
Interrupt Assertion
Defines how selected event affects INTREQ# assertion. Whenever INTREQ# is
asserted, a flag for this counter is set in the Error Status (ERRSTS) register, so that
software can determine the cause of the interrupt. This flag is reset by writing the
ERRSTS register.
0
1
2
3
Selected event does not assert INTREQ#
reserved
Assert INTREQ# pin when event occurs
Assert INTREQ# pin when counter overflows
5:4
Performance Monitoring pin assertion
Defines how the selected event affects the Performance Monitoring pin for this
counter.
0
1
2
3
Selected event does not assert this counters PM pin
reserved
Assert this counter’s PM pin when event occurs
Assert this counter’s PM pin when counter overflows
Intel® 450NX PCIset
3-23
3. Register Descriptions
3:2
Count Mode
Selects when the counter is updated for the detected event.
0
1
2
3
Stop counting.
Count each cycle selected event occurs.
Count on each rising edge of the selected event.
Trigger. Start counting on the first rising edge of the selected
event, and continue counting each clock cycle.
1:0
Reload Mode
Reload has priority over increment. If a reload event and a count event happen
simultaneously, the count event has no effect.
0
1
2
3
Never Reload
Reload when this counter overflows.
Reload when the other counter overflows.
Reload unless the other counter increments.
3.3.34 RC: Reset Control Register
Address Offset: 42h
Size:
8 bits
Default Value:
00h
Attribute: Read/Write
The RC initiates processor reset cycles and initiates Built-in Self Test (BIST) for the
processors.
Bits
7:6
5
Description
reserved (0)
Reset Expander Port #1.
While this bit is set, the X1RST# signal is asserted. When this bit is cleared, the
X1RST# pin will be deasserted, unless other assertion criteria are still in effect (e.g.,
system hard reset).
Default=0.
4
3
Reset Expander Port #0.
While this bit is set, the X0RST# signal is asserted. When this bit is cleared, the
X0RST# will be deasserted, unless other assertion criteria are still in effect (e.g.,
system hard reset). Default=0.
Processor BIST Enable (BISTE).
This bit modifies the action of the RCPU and SHRE bits, below. If this bit is set, a
subsequent invocation of system hard reset causes the INIT# signal to be asserted
coincident with the deassertion of RESET#; this combination will invoke the Built-In
Self Test (BIST) feature of the processors. Default=0.
2
Reset Processor (RCPU).
The transition of this bit from 0 to 1 causes the MIOC to initiate a hard or soft reset.
Selection of hard or soft reset, and processor BIST, are controlled by the BISTE and
SHRE enables, which must be set up prior to the 0-to-1 transition on the RCPU bit.
Default=0.
3-24
Intel® 450NX PCIset
3.3 MIOC Configuration Space
1
0
System Hard Reset Enable (SHRE).
®
This bit modifies the action of the RCPU bit, above. If set, the Intel 450NX PCIset
will initiate a system hard reset upon a subsequent 0-to-1 transition of the RCPU bit. If
this bit is cleared, the Intel 450NX PCIset will initiate a soft reset upon a subsequent 0-
to-1 transition of the RCPU bit. Default=0.
reserved (0)
3.3.35 RCGP: RCGs Present
Address Offset: A3h
Size:
8 bits
Default Value:
00h
Attribute: Read/Write
The Intel 450NX PCIset memory subsystem supports at most two RCGs (one per card). This
corresponds to RCG #0 and RCG #2, bits 0 and 2 in the RCGP register.
Bits
7:4
Description
reserved (0)
3:0
RCGs Present [3:0].
If bit i is set, then RCG[i] was detected as present in the system following power-on
reset. If cleared, then RCG[i] is not present. Default= <hardware generated>.
3.3.36 REFRESH: DRAM Refresh Control Register
Address Offset: A4-A5h
Default Value:
0411h
Size:
16 bits
Attribute: Read/Write
Bits
15:11 reserved (0)
10:0 Refresh Count.
Description
Specifies the number of system bus cycles between refresh cycles. Typically, the value
is chosen to provide a refresh at least every 15.625 usec.
@ 100.0 MHz: 61Ah = 15.620 usec
@ 90.0 MHz: 57Eh = 15.622 usec
Maximum value is 20.48 usec at 100 MHz.
Default=411h
3.3.37 RID: Revision Identification Register
Address Offset: 08h
Default Value:
00h
Size:
8 bits
Attribute: Read Only
Intel® 450NX PCIset
3-25
3. Register Descriptions
Bits
Description
7:0
Revision Identification Number.
This is an 8-bit value that indicates the revision identification number for the MIOC
3.3.38 ROUTE[1:0]: Route Field Seed
Address Offset: C3h, CBh
Size:
8 bits
Default Value:
40h
Attribute: Read/Write
Bits
Description
7:4
Outbound-to-B Route Seed.
This field represents the “seed” value used to create the routing field for outbound
packets to the PXB’s B-port.
Default: 0100b
3:0
Outbound-to-A Route Seed.
This field represents the “seed” value used to create the routing field for outbound
packets to the PXB’s A-port.
Default: 0000b
3.3.39 SMRAM: SMM RAM Control Register
Address Offset: 6C-6Fh
Size:
32 bits
Default Value:
00000Ah
Attribute: Read/Write
Bits
Description
31
SMRAM Enable (SMRAME).
If set, the SMRAM functions are enabled. Host-initiated accesses to the SMM space
can be selectively directed to memory or PCI, as defined below and in Table 3-3. If
SMRAME is cleared, SMRAM functions are disabled. Default=0.
30:27 reserved (0)
26
SMM Space Open (D_OPEN).
If set, all accesses (code fetches or data references) to SMM space are passed to
memory, regardless of whether the SMMEM# signal is asserted. D_OPEN may be set
or cleared by software. D_OPEN will also be automatically cleared, and will become
read-only, when the D_LCK enable is set. Default=0.
25
SMM Space Closed (D_CODE).
This bit should not be set unless D_OPEN=0. If D_CODE is set, only code fetches to
SMM space may be passed to the DRAM, depending on the SMMEM# signal. Data
accesses to SMM space will not be passed to the DRAM, regardless of the SMMEM#
signal. Default=0.
3-26
Intel® 450NX PCIset
3.3 MIOC Configuration Space
24
SMM Space Locked (D_LCK).
When software writes a 1 to this bit, the hardware will clear the D_OPEN bit, and
both D_LCK and D_OPEN then become read only. No application software, except
the SMI handler, should violate or change the contents of SMM memory. Default=0.
23:20 SMM Space Size.
This field specifies the size of the SMM RAM space, in 64 KB increments.
0h
64 KB
4h 320 KB
5h 384 KB
6h 448 KB
7h 512 KB
8h 576 KB
9h 640 KB
Ah 704 KB
Bh 768 KB
Ch 832 KB
Dh 896 KB
Eh 960 KB
Fh 1 MB
1h 128 KB
2h 192 KB
3h 256 KB
Default: 0h (64 KB).
19:16 reserved (0)
15:0
SMM Space Base Address.
This field specifies the A[31:16] portion of the SMM RAM space base address
(A[15:0]=0000h). The space may be relocated anywhere below the 4 GB boundary
and the Top of Memory (TOM); however, the base address must be aligned on the
next highest power-of-2 natural boundary given the chosen size. Incorrect alignment
results in indeterminate operation. Default: 000Ah.
Table 3-3: SMRAM Space Cycles
Code
Fetch
Data
Reference
Usage
1
1
0
1
X
0
X
0
X
X
X
0
Normal
Normal
SMM RAM space is not supported.
PCI 0a
PCI 0A
Normal SMM usage. Accesses to the SMM
RAM space from processors in SMM will
access the DRAM. Accesses by processors
not in SMM will be diverted to the
compatibility PCI bus.
1
0
0
X
1
DRAM
DRAM
1
1
0
0
1
1
X
X
0
1
PCI 0A
DRAM
PCI 0A
PCI 0A
A modification of the normal SMM usage, in
which only code fetches are accepted from
processors in SMM mode.
X
1
1
1
1
0
X
0
X
X
Illegal Combination
DRAM Full access by any agent to SMM RAM
space.
DRAM
1. SMRAM functions are disabled.
3.3.40 SUBA[1:0]: Bus A Subordinate Bus Number, per PXB
Address Offset: D1h, D4h
Default Value: 00h each
Size:
8 bits each
Attribute: Read/Write
See the description of BUSNO.
Intel® 450NX PCIset
3-27
3. Register Descriptions
3.3.41 SUBB[1:0]: Bus B Subordinate Bus Number, per PXB
Address Offset: D2h, D5h
Default Value: 00h each
Size:
8 bits each
Attribute: Read/Write
See the description of BUSNO.
3.3.42 TCAP[0:3]: Target Capacity, per PXB/PCI Port
Address Offset: C0-C2h, C4-C6h
Size:
24 bits each
C8-CAh, CC-CEh
Default Value:
041082 each
Attribute: Read/Write
Each of these registers is programmed by software with the maximum number of transactions
and data bytes that the receiving PXB/PCI port can accept for outbound transactions.
Register
Controls outbound transactions to ... if in ...
dual 32-bit Bus Mode
PXB #0 / PCI Bus A
PXB #0 / PCI Bus B
PXB #1 / PCI Bus A
PXB #1/ PCI Bus B
64-bit Bus Mode
PXB #0
TCAP[0]
TCAP[1]
TCAP[2]
TCAP[3]
N/A
PXB #0
N/A
NOTE
Setting a value below the listed minimum-allowed value will have unpredictable results, up to and
including potential deadlocks requiring a hard reset of the PCIset.
Bits
Description
23:18 Outbound Write Transaction Capacity.
This field specifies the total number of outbound write transactions, per PXB/PCI
port, that can be forwarded and queued by the PXB.
MIOC maximum: 12
Minimum allowed: 1, 2 or 3
Default= 1
- If no outbound locks are supported, then the minimum is 1.
- If ordinary outbound locks are supported, then the minimum is 2.
- If outbound split locks are supported, then the minimum is 3.
17:12 Outbound Read Transaction Capacity.
This field specifies the total number of outbound read transactions, per PXB/PCI port,
that can be forwarded and queued in the PXB.
MIOC maximum: 2
Minimum allowed: 1
Default= 1
11:6 Outbound Write Data Buffer Capacity.
This field specifies the total number of data buffers, per PXB/PCI port, available in
the PXB for use by outbound write transactions, in increments of 32 bytes.
MIOC maximum: 12
Minimum allowed: 2
Default= 2
3-28
Intel® 450NX PCIset
3.4 PXB Configuration Space
5:0
Outbound Read Data Buffer Capacity.
This field specifies the total number of data buffers, per PXB/PCI port, available in
the PXB for use by outbound read transactions, in increments of 32 bytes.
MIOC maximum: 16
Minimum allowed: 2
Default= 2
3.3.43 TOM: Top of Memory
Address Offset: 50-52h
Size:
24 bits
Default Value:
000FFFh
Attribute: Read/Write
Bits
Description
23:0
Memory Address Ceiling.
Represents bits A[43:20] of the highest physical address to be directed toward this
node’s DRAM. The lower A[19:0] bits of this address are FFFFFh.
Default=000FFFh (4 GB-1).
3.3.44 VID: Vendor Identification Register
Address Offset: 00 - 01h
Size:
16 bits
Default Value:
8086h
Attributes: Read Only
Bits
Description
15:0
Vendor Identification Number.
This is a 16-bit value assigned to Intel. Intel VID = 8086h.
3.4 PXB Configuration Space
Each PXB supports two independent PCI buses (Bus “A” and Bus “B”), which can be
configured independently. Each PCI bus therefore has its own configuration space. Both
configuration spaces are identical. When operating the PXB in 64-bit Bus Mode, only the A-
side configuration space is used. The B-side configuration space is not accessible while in 64-
bit mode.
Table 3-4 illustrates the PXB/PCI Bus Configuration Space Map.
Intel® 450NX PCIset
3-29
3. Register Descriptions
1
Table 3-4: PXB Configuration Space
DID
PCISTS
CLASS
HDR
VID
00h
04h
08h
0Ch
10h
14h
18h
1Ch
80h
84h
PCICMD
RID
CLS
88h
MLT
8Ch
90h
94h
98h
9Ch
A0h
24h
28h
2Ch
30h
34h
38h
3Ch
40h
A4h
A8h
ACh
B0h
B4h
B8h
BCh
MTT
CONFIG
ROUTE
TCAP
C0h
RC
ERRCMD
ERRSTS 44h
TMODE C4h
C8h
BUFSIZ
TOM
48h
4Ch
50h
CCh
D0h
LXGT
LXGB
54h
58h
D4h
HXGB
HXGT
MAR0
MAR4
PMD0
PMR0
PMD1
PMR1
PME0
D8h
5Ch
PMD0
PMD1
DCh
E0h
E4h
E8h
ECh
F0h
F4h
F8h
FCh
MAR2
MAR6
MAR1
MAR5
GAPEN 60h
MAR3
64h
68h
6Ch
70h
74h
78h
7Ch
IOABASE
PME1
SMRAM
MMBASE
MMT
ISA
1. The first 64 bytes are predefined in the PCI Specification. All other locations are defined specifically for the
component of interest.
3-30
Intel® 450NX PCIset
3.4 PXB Configuration Space
3.4.1
BUFSIZ: Buffer Sizes
Address Offset: 48-4Ah
Size:
24 bits
Default Value:
302308h (64-bit bus mode)Attribute: Read Only
182184h (32-bit bus mode)
This register contains the hardwired information defining the maximum number of outbound
transactions and data bytes that this PXB/PCI port can accept.
Bits
Description
23:18 Outbound Write Transaction Capacity.
This field specifies the total number of outbound write transactions that can be
accepted and queued in this PXB/PCI port.
Value=
6
(32-bit bus mode)
12 (64-bit bus mode)
17:12 Outbound Read Transaction Capacity.
This field specifies the total number of outbound read transactions that can be
accepted and queued in this PXB/PCI port.
Value=
2
2
(32-bit bus mode)
(64-bit bus mode)
11:6
5:0
Outbound Write Data Buffer Capacity.
This field specifies the total number of data buffers available in this PXB/PCI port for
use by outbound write transactions, in increments of 32 bytes.
Value= 6 (x 32 bytes) (32-bit bus mode)
12 (x 32 bytes) (64-bit bus mode)
Outbound Read Data Buffer Capacity.
This field specifies the total number of data buffers available in this PXB/PCI port for
use by outbound read transactions, in increments of 32 bytes.
Value= 4 (x 32 bytes) (32-bit bus mode)
8 (x 32 bytes) (64-bit bus mode)
3.4.2
CLASS: Class Code Register
Address Offset: 09 - 0Bh
Size:
24 bits
Default Value:
060000h
Attribute: Read Only
Bits Description
23:16 Base Class
For the PXB, this field is hardwired to 06h.
15:8
7:0
Sub-Class
For the PXB, this field is hardwired to 00h.
Register-Level Programming Interface
For the PXB, this field is hardwired to 00h.
Intel® 450NX PCIset
3-31
3. Register Descriptions
3.4.3
CLS: Cache Line Size
Address Offset: 0Ch
Size:
8 bits
Default Value:
08h
Attribute: Read/Write
Bits
Description
7:0
Cache Line Size
®
This field specifies the cache line size, in 32-bit Dword units. The Intel 450NX PCIset
supports only one value: 8 Dwords (32 bytes). Default=08h.
3.4.4
CONFIG: Configuration Register
Address Offset: 40-41h
Default Value: 2310h
Size:
16 bits
Attribute: Read/Write, Read-Only
Bits
15
Description
reserved (0)
PCI Bus Lock Enable.
14
This mode works only if internal bus arbitration is selected. When set, the internal
arbiter detects when the lock is established and inhibits a PCI bus grant to all agents
except the agent that established the lock.
Default=0.
13
WSC# Assertion Enable.
If cleared, the WSC# signal will always remain asserted. While asserted, writes
continue to be accepted from the PIIX even with writes outstanding. This option is
provided to allow improved performance in systems with ISA masters that desire to
write to main memory.
Default=1.
12
11
10
PCI-TPA Prefetch Line Enable (PLE).
If set, inbound line accesses (e.g., MRM and MRL accesses) to third-party space are
treated as prefetchable. Default=0.
PCI-TPA Prefetch Word Enable (PWE).
If set, inbound sub-line accesses (e.g., MR accesses) to third-party space are treated as
prefetchable. Default=0.
Block Requests.
This enable is provided for debug, diagnostic and error recovery purposes. If set, the
internal arbiter ignores all further REQ[0:5]# assertions by any of the six PCI agents,
and will deassert any current PCI agent’s GNT# in order to prevent further inbound
transactions from a parking agent. This enable has no effect if the PXB is configured to use
external arbitration. Default=0.
9
I/O Address Mask Enable.
If set, on outbound I/O accesses the PXB will force A[31:16] to zero before placing the
address on the PCI bus. Default=1.
3-32
Intel® 450NX PCIset
3.4 PXB Configuration Space
8
7
Outbound Write Around Retried/Partial Read Enable.
If set, the PXB allows outbound writes to pass retried or partially completed (i.e.,
®
disconnected) outbound reads. This enable must be set for Pentium II Xeon™
®
processor/Intel 450NX PCIset systems. Default=1.
Burst Write Combining Enable (BWCE).
If set, back-to-back sequentially addressed outbound writes may be combined in the
outbound write buffers before placement on the PCI bus. When the BWCE is cleared,
all outbound write combining is disabled, and each host transaction results in a
corresponding transaction on the PCI bus. Default=0.
6
Re-streaming Buffer Enable.
If set, the data returned and buffered for a Delayed Inbound Read may be re-accessed
following a disconnect. If cleared, following a disconnect, the buffer is invalidated,
and a subsequent read to the next location will initiate a new read. Default=0
(Disabled).
5:4
Read Prefetch Size.
This field configures the number of Dwords that will be prefetched on Memory Read
Multiple commands. Legal values are:
00 16 Dwords (2 x 32 bytes)
01 32 Dwords (4 x 32 bytes)
10 64 Dwords (8 x 32 bytes)
11 reserved
The normal selection is 32 Dwords The 64 Dword selection provides highest
performance when the PXB is in 64-bit bus mode. Default=01 (32 Dwords).
3
2
1
External Arbiter Enable.
This is a read-only bit that selects internal or external arbitration for the PCI bus. The
bit reflects the state of the P(A,B)XARB# strapping pin for this bus (A or B).
Default=[P(A,B)XARB pin].
64-bit Bus Enable.
This is a read-only bit that selects whether the PXB operates as two 32-bit PCI buses or
a single 64-bit PCI bus. The bit reflects the state of the MODE64# strapping pin.
Default=[MODE64# pin].
Host/PCI Bus Gearing Ratio.
This is a read-only bit that selects the system clock to PCI clock gearing ratio. The bit
reflects the state of the GEAR4# strapping pin. This bit should be cleared (i.e.,
GEAR4# is high, or deasserted), resulting in a system clock/ PCI clock gearing ratio
of 3:1.
Default=[GEAR4# pin].
0
reserved
3.4.5
DID: Device Identification Register
Address Offset: 02 - 03h
Default Value:
84CBh
Size:
16 bits
Attributes: Read Only
Intel® 450NX PCIset
3-33
3. Register Descriptions
Bits
Description
15:0
Device Identification Number.
The value 84CBh indicates the Intel 450NX PCIset PXB.
®
3.4.6
ERRCMD: Error Command Register
Address Offset: 46h
Default Value: 00h
Size:
8 bits
Attribute: Read/Write
This register provides extended control over the assertion of SERR# beyond the basic controls
specified in the PCI-standard PCICMD register.
Bits
Description
7
6
reserved
Assert SERR# on Observed Parity Error.
If set, the PXB asserts SERR# if PERR# is observed asserted, and the PXB was not the
asserting agent.
5
Assert SERR# on Received Data with Parity Error.
If set, the PXB asserts SERR# upon receiving PCI data with a parity error. This occurs
regardless of whether PXB asserts it's PERR# pin.
4
3
Assert SERR# on Address Parity Error.
If set, the PXB asserts SERR# on detecting a PCI address parity error.
Assert PERR# on Data Parity Error.
If set, and the PERRE bit is set in the PCICMD register, the PXB asserts PERR# upon
receiving PCI data with parity errors.
2
Assert SERR# On Inbound Delayed Read Time-out.
Each inbound read request that is accepted and serviced as a delayed read will start a
15
watchdog timer (2 cycles). If this enable is set, the PXB will assert SERR# if the data
has been returned and the timer expires before the requesting master initiates its
repeat request. Default=0.
1
0
Assert SERR# on Expander Bus Parity Error.
If set, the PXB asserts SERR# upon detecting a parity error on packets arriving from
the Expander bus. (Note that SERR# will be asserted on both PCI buses).
Return Hard Fail Upon Generating Master Abort.
If set, the PXB will return a Hard Fail response through the MIOC to the system bus
after generating a master abort time-out for an outbound transaction placed on the
PCI bus. If cleared, the PXB will return a normal response (with data of all 1’s for a
read). In either case, an error flag is set in the PCISTS register. Default=0.
3-34
Intel® 450NX PCIset
3.4 PXB Configuration Space
3.4.7
ERRSTS: Error Status Register
Address Offset: 44h
Default Value:
00h
Size:
8 bits
Attribute: Read/Write Clear, Sticky
This register records error conditions detected from the PCI bus (not already covered in
PCISTS), from the Expander bus, and performance monitoring events. Bits remain set until
explicitly cleared by software writing a 1 to the bit.
Bits
Description
7
6
reserved(0)
Parity Error observed on PCI Data.
This flag is set if the PXB detects the PERR# input asserted, and the PXB was not the
asserting agent. This flag may be configured to assert SERR# or PERR# in the
ERRCMD register.
5
4
3
Parity Error on Received PCI Data.
This flag is set if the PXB detects a parity error on data being read from the PCI bus.
This flag may be configured to assert SERR# or PERR# in the ERRCMD register.
Parity Error on PCI Address.
This flag is set if the PXB detects a parity error on the PCI address. This flag may be
configured to assert SERR# in the ERRCMD register.
Inbound Delayed Read Time-out Flag.
Each inbound read request that is accepted and serviced as a delayed read will initiate
15
a watchdog timer (2 cycles). If the data has been returned and the timer expires
before the requesting master initiates its repeat request, this flag will be set. This flag
may be configured to assert SERR# or PERR# in the ERRCMD register.
2
1
0
Expander Bus Parity Error Flag.
This flag is set when Expander bus reports a parity error on packets received from the
MIOC. This flag is set in both PCI configuration spaces. This flag may be configured
to assert SERR# or PERR# in the ERRCMD register.
Performance Monitor #1 Event Flag.
This flag is set when the Performance Monitor #1 requests that an interrupt request be
asserted. The PME and PMR registers describe the conditions that can cause this to
occur. While this bit is set, the INT(A,B)RQ# line will be asserted.
Performance Monitor #0 Event Flag.
This flag is set when the Performance Monitor #0 requests that an interrupt request be
asserted. The PME and PMR registers describe the conditions that can cause this to
occur. While this bit is set, the INT(A,B)RQ# line will be asserted.
Intel® 450NX PCIset
3-35
3. Register Descriptions
3.4.8
GAPEN: Gap Enables
Address Offset: 60h
Default Value: 0Eh
Size:
8 bits
Attribute: Read/Write
This register controls the enabling of the two programmable memory gaps, and several fixed-
size/fixed-location spaces. This register applies to both host-initiated transactions and PCI-
initiated inbound transactions, and is therefore duplicated in both the MIOC and PXB
Configuration Spaces. Software must ensure that both sets are programmed identically to
achieve correct functioning. See the MIOC Configuration Space for a detailed description.
3.4.9
HDR: Header Type Register
Address Offset: 0Eh
Size:
8 bits
Default Value:
00h
Attribute: Read Only
Bits
Description
7
Multi-function Device.
Selects whether this is a multi-function device, that may have alternative
configuration layouts. This bit is hardwired to 0.
6:0
Configuration Layout.
This field identifies the format of the 10h through 3Fh space. This field is hardwired
to 00h, which represents the default PCI configuration layout.
3.4.10 HXGB: High Expansion Gap Base
Address Offset: 58-5Ah
Default Value: 000000h
Size:
24 bits
Attribute: Read/Write
This register defines the starting address of the High Expansion Gap (HXG). This register
applies to both host-initiated transactions and PCI-initiated inbound transactions, and is
therefore duplicated in both the MIOC and PXB Configuration Spaces. Software must ensure
that both sets are programmed identically to achieve correct functioning. See the MIOC
Configuration Space for a detailed description.
3.4.11 HXGT: High Expansion Gap Top
Address Offset: 5C-5Eh
Default Value: 000000h
Size:
24 bits
Attribute: Read/Write
This register defines the highest address of the High Expansion Gap (HXG), above. HXGT
applies to both host-initiated transactions and PCI-initiated inbound transactions, and is
therefore duplicated in both the MIOC and PXB Configuration Spaces. Software must ensure
that both sets are programmed identically to achieve correct functioning. See the MIOC
Configuration Space for a detailed description.
3-36
Intel® 450NX PCIset
3.4 PXB Configuration Space
3.4.12 IOABASE: I/O APIC Base Address
Address Offset: 68-69h
Default Value: 0FECh
Size:
16 bits
Attribute: Read/Write
This register defines the base address of the 1MB I/O APIC Space address range. IOABASE
applies to both host-initiated transactions and PCI-initiated inbound transactions, and is
therefore duplicated in both the MIOC and PXB Configuration Spaces. Software must ensure
that both sets are programmed identically to achieve correct functioning. See the MIOC
Configuration Space for a detailed description.
3.4.13 ISA: ISA Space
Address Offset: 7Ch
Default Value:
00h
Size:
8 bits
Attribute: Read/Write
This register defines the ISA Space address range. The register applies to both host-initiated
transactions and PCI-initiated inbound transactions, and is therefore duplicated in both the
MIOC and PXB Configuration Spaces. Software must ensure that both sets are programmed
identically to achieve correct functioning. See the MIOC Configuration Space for a detailed
description.
3.4.14 LXGB: Low Expansion Gap Base
Address Offset: 54-55h
Default Value:
0000h
Size:
16 bits
Attribute: Read/Write
This register defines the starting address of the Low Expansion Gap (LXG). LXGB register
applies to both host-initiated transactions and PCI-initiated inbound transactions, and is
therefore duplicated in both the MIOC and PXB Configuration Spaces. Software must ensure
that both sets are programmed identically to achieve correct functioning. See the MIOC
Configuration Space for a detailed description.
3.4.15 LXGT: Low Expansion Gap Top
Address Offset: 56-57h
Default Value:
0000h
Size:
16 bits
Attribute: Read/Write
LXGT defines the highest address of the Low Expansion Gap (LXG), above. This register
applies to both host-initiated transactions and PCI-initiated inbound transactions, and is
therefore duplicated in both the MIOC and PXB Configuration Spaces. Software must ensure
that both sets are programmed identically to achieve correct functioning. See the MIOC
Configuration Space for a detailed description.
Intel® 450NX PCIset
3-37
3. Register Descriptions
3.4.16 MAR[6:0]: Memory Attribute Region Registers
Address Offset: 61-67h
Default Value: 03h for MAR[0]
00h for all others
Size:
8 bits each
Attribute: Read/Write
The Intel 450NX PCIset allows programmable memory attributes on 14 memory segments of
various sizes in the 640 Kbyte to 1 MByte address range. Seven Memory Attribute Region
(MAR) registers are used to support these features. These registers apply to both host-initiated
transactions and PCI-initiated transactions, and are therefore duplicated in both the MIOC
and PXB Configuration Spaces. Software must ensure that both sets are programmed
identically to achieve correct functioning. See the MIOC Configuration Space for a detailed
description.
3.4.17 MLT: Master Latency Timer Register
Address Offset: 0Dh
Default Value: 00h
Size:
8 bits
Attribute: Read/Write
MLT is an 8-bit register that controls the amount of time (measured in PCI clocks) the Intel
450NX PCIset, as a bus master, can burst data on the PCI Bus. The Count Value is an 8 bit
quantity; however, MLT[2:0] are reserved and assumed to be 0 when determining the Count
Value. The number of clocks programmed in the MLT represents the guaranteed time slice
allotted to the Intel 450NX PCIset, after which it must complete the current data transfer phase
and then surrender the bus as soon as its bus grant is removed.
Bits
Description
7:3
Master Latency Timer Count Value.
Counter value in 8 PCI clock units.
2:0
reserved (0)
3.4.18 MMBASE: Memory-Mapped PCI Base
Address Offset: 70-71h
Default Value: 0002h
Size:
16 bits
Attribute: Read/Write
The MMBASE register specifies the starting address of this memory-mapped PCI range, and is
identical to the MMBASE register in the MIOC. The MMT register specifies the highest
address that will be directed to PCI Bus #1B, and corresponds identically to the MMR[3]
register in the MIOC. The MMBASE register must be programmed identically to the MMBASE
register in the MIOC to achieve correct functioning. See the MIOC Configuration Space for a
detailed description.
3-38
Intel® 450NX PCIset
3.4 PXB Configuration Space
3.4.19 MMT: Memory-Mapped PCI Top
Address Offset: 7A-7Bh
Default Value:
0001h
Size:
16 bits
Attribute: Read/Write
This register defines the highest address of the memory-mapped PCI space. See the MMBASE
register above for a detailed description. The MMT register must be programmed identically
to MMR[3] in the MIOC to achieve correct functioning.
3.4.20 MTT: Multi-Transaction Timer Register
Address Offset: 43h
Default Value:
00h
Size:
8 bits
Attribute: Read/Write
This register controls the amount of time that the PCI bus arbiter allows a PCI initiator to
perform multiple back-to-back transactions on the PCI bus.
Bits
Description
7:3
MTT Count Value.
Specifies the guaranteed time slice (in 8-PCI-clock increments) allotted to the current
agent, after which the PXB will grant the bus as soon as other PCI masters request the
bus. A value of 0 disables this function. Default=0.
2:0
reserved (0)
3.4.21 PCICMD: PCI Command Register
Address Offset: 04 - 05h
Default Value:
0016h
Size:
16 bits
Attribute: Read/Write, Read-Only
This is a PCI specification required register with a fixed format.
Bits Description
15:10 reserved (0)
9
Fast Back-to-Back.
Fast back-to-back cycles are not implemented by the PXB, and this bit is hardwired to
0.
8
SERR# Enable (SERRE).
If this bit is set, the PXB’s SERR# signal driver is enabled and SERR# is asserted for
all relevant bits set in the ERRSTS and PCISTS as controlled by the corresponding
bits of the ERRCMD register. If SERRE is set and the PXB’s PCI parity error reporting
is enabled by the PERRE bit, then the PXB will assert SERR# on address parity
errors. Default=0.
Intel® 450NX PCIset
3-39
3. Register Descriptions
7
Address/Data Stepping.
The PXB does not support address/data stepping, and this bit is hardwired to 0.
6
Parity Error Response (PERRE).
If PERRE is set, the PXB will report parity errors on data received by asserting the
PERR# signal. Address parity errors are not reported using PERR#, but instead
through the SERR# signal, and only if both PERRE and SERRE are set. If PERRE is
cleared, then PCI parity errors are not reported by the PXB. Default=0.
5
4
reserved (0)
Memory Write and Invalidate Enable.
Selects whether the PXB, as a PCI master, can generate Memory Write and Invalidate
cycles. Default=1.
3
2
1
0
Special Cycle Enable.
The PXB will ignore all special cycles generated on the PCI bus, and this bit is
hardwired to 0.
Bus Master Enable.
The PXB does not permit disabling of its bus master capability, and this bit is
hardwired to 1.
Memory Access Enable.
The PXB does not permit disabling access to main memory, and this bit is hardwired
to 1.
I/O Access Enable.
The PXB does not respond to PCI I/O cycles, and this bit is hardwired to 0.
3.4.22 PCISTS: PCI Status Register
Address Offset: 06 - 07h
Size:
16 bits
Default Value:
0280h
Attribute: Read/Write Clear, Sticky
This is a PCI specification required register, with a fixed format.
Bits
Description
15
Parity Error (PE).
This bit is set when the PXB detects a parity error in data or address on the PCI bus.
This bit remains set until explicitly cleared by software writing a 1 to this bit.
Default=0.
14
Signaled System Error (SSE).
This bit is set when the PXB asserts the SERR# signal. This bit remains set until
explicitly cleared by software writing a 1 to this bit.
Default=0.
3-40
Intel® 450NX PCIset
3.4 PXB Configuration Space
13
Received Master Abort (RMA).
This bit is set when the PXB, as bus master, terminates its transaction (except for
Special Cycles) with a master abort. This bit remains set until explicitly cleared by
software writing a 1 to this bit.
Default=0.
12
Received Target Abort (RTA).
This bit is set when the PXB, as bus master, receives a target abort for its transaction.
This bit remains set until explicitly cleared by software writing a 1 to this bit.
Default=0.
11
Signaled Target Abort (STA).
This bit is set when the PXB, as bus target, terminates a transaction with target abort.
This bit remains set until explicitly cleared by software writing a 1 to this bit.
Default=0.
10:9
DEVSEL# Timing (DEVT).
This 2-bit field encodes the timing of the DEVSEL# signal when the PXB responds as a
target, and represents the slowest time that the PXB asserts DEVSEL# for any bus
command except Configuration Reads or Writes. This field is hardwired to the value
01b (medium).
8
Data Parity Error (DPE).
This bit is set when all of the following conditions are met:
1. The PXB asserted PERR# or sampled PERR# asserted.
2. The PXB was the initiator for the operation in which the error occurred.
3. The PERRE bit in the PCICMD register is set.
This bit remains set until explicitly cleared by software writing a 1 to this bit.
Default=0.
7
6
Fast Back-to-Back (FB2B).
The PXB supports fast back-to-back transactions, and this bit is hardwired to 1.
UDF Supported.
The PXB does not support User Definable Features (UDF), and this bit is hardwired to
0.
5
66 MHz Capable.
The PXB is not capable of running at 66 MHz, and this bit is hardwired to 0.
4:0
reserved (0)
3.4.23 PMD[1:0]: Performance Monitoring Data Register
Address Offset: D8-DCh, E0-E4h
Default Value:
000000000000h each
Size:
40 bits each
Attribute: Read/Write
Two performance monitoring counters, with associated event selection and control registers,
are provided for each PCI bus in the PXB. The PMD registers hold the performance
monitoring count values. Event selection is controlled by the PME registers, and the action
performed on event detection is controlled by the PMR registers.
Intel® 450NX PCIset
3-41
3. Register Descriptions
Bits
Description
Count Value.
39:0
3.4.24 PME[1:0]: Performance Monitoring Event Selection
Address Offset: E8 - EBh
Default Value: 0000h each
Size:
16 bits each
Attribute: Read/Write
Bits
15
Description
reserved (0)
Count Data Cycles
14
1: Count the data cycles associated with the selected transactions.
0: Count the selected event
13:10 Initiating Agent Selection.
This field qualifies the tracking of bus transactions by limiting event detection to those
transactions issued by specific agents.
0000 Agent 0 1000 reserved
0001 Agent 1 1001 reserved
0010 Agent 2 1010 reserved
0011 Agent 3 1011 reserved
0100 Agent 4 1100 reserved
0101 Agent 5 1101 south bridge
®
0110 reserved 1110 Intel 450NX PCIset agent (i.e., outbound)
0111 reserved 1111 Any agent
Note: This field is applicable only if the PCI bus is operated in internal arbiter mode.
If the bus is operated using an external arbiter, this field must be set to Any Agent to
trigger any events.
9:8
7:6
Transaction Destination Selection.
This field qualifies the tracking of bus transactions by limiting event detection to those
transactions directed to a specific resource.
00 Any
10 PCI Target
01 Main Memory 11 Third party
reserved
3-42
Intel® 450NX PCIset
3.4 PXB Configuration Space
5:0
Event Selection.
This field specifies the basic PCI bus transaction or PCI bus signal to be monitored.
Individual Bus Transactions
00 0000 reserved
00 0001 reserved
00 0010 I/O Read
00 0011 I/O Write
00 0100 reserved
00 0101 reserved
00 0110 Memory Read
00 0111 Memory Write
00 1000 reserved
00 1001 reserved
00 1010 reserved
00 1011 reserved
00 1100 Memory Read Multiple
00 1101 Dual Address Cycle
00 1110 Memory Read Line
00 1111 Memory Write & Invalidate
Generic (Grouped) Bus Transactions
010 000 Any bus transaction
010 001 Any memory transaction
010 010 Any memory read
010 100 Any I/O transaction
010 101 Any I/O or memory transactions
010 110 Any I/O read or memory read
010 111 Any I/O read or memory write
010 011 Any memory write
Bus Signal Assertions
011 000 reserved
011 001 reserved
011 100 reserved
011 101 reserved
011 110 LOCK
011 111 ACK64
1
011 010 RETRY
011 011 reserved
All other encodings are reserved.
Note:
1. Counting data cycles is undefined for this selection.
3.4.25 PMR[1:0]: Performance Monitoring Response
Address Offset: DDh, E5h
Default Value:
0000h each
Size:
8 bits each
Attribute: Read/Write
There are two PMR registers for each PCI bus, one for each PMD counter. Each PMR register
specifies how the event selected by the corresponding PME register affects the associated
PMD register, P(A,B)MON# pins, and the INT(A,B)RQ# pins.
Bits
Description
7:6
Interrupt Assertion
Defines how selected event affects INTRQ# assertion. Whenever INTRQ# is asserted,
a flag for this counter is set in the Error Status Register, so that software can determine
the cause of the interrupt. This flag is reset by writing the Error Status Register.
0
1
2
3
Selected event does not assert INTRQ #
reserved
Assert INTRQ# pin when event occurs
Assert INTRQ# pin when counter overflows
5:4
Performance Monitoring pin assertion
Defines how the selected event affects the PMON# pin for this counter.
0
1
PMON# pin is tristated. Selected event has no effect.
reserved
Intel® 450NX PCIset
3-43
3. Register Descriptions
2
3
Assert this counter’s PMON# pin when event occurs
Assert this counter’s PMON# pin when counter overflows
3:2
1:0
Count Mode
Selects when the counter is updated for the detected event.
0
1
2
3
Stop counting.
Count each cycle selected event is active.
Count on each rising edge of the selected event.
Trigger. Start counting on the first rising edge of the selected event, and
continue counting each clock cycle.
Reload Mode
Reload has priority over increment. That is, if a reload event and a count event
happen simultaneously, the count event has no effect.
0
1
2
3
Never reload
Reload when this counter overflows.
Reload when the other counter overflows.
Reload unless the other counter increments.
3.4.26 RID: Revision Identification Register
Address Offset: 08h
Size:
8 bits
Default Value:
00h
Attribute: Read Only
Bits
Description
7:0
Revision Identification Number.
This is an 8-bit value that indicates the revision identification number for the PXB.
These bits are read only and writes to this register have no effect.
3.4.27 RC: Reset Control Register
Address Offset: 47h
Size:
8 bits
Default Value:
01h
Attribute: Read/Write/Sticky
The RC register controls the response of the PXB to XRST#.
Bits
7:1
0
Description
reserved (0)
Reset PCI clocks on XRST#
Clearing this bit enables PCICLKA and PCICLKB to run undisturbed through reset.
When set, PCI clock phase will be reset whenever XRST# is asserted.
When clear, System Hard Resets, PXB Resets, Soft Resets, BINIT Resets will not
disturb PCICLKA and PCICLKB. This bit is defined to be sticky so that it can only be
modified by PWRGD or configuration write. Default=1.
3-44
Intel® 450NX PCIset
3.4 PXB Configuration Space
3.4.28 ROUTE: Route Field Seed
Address Offset: C3h
Size:
8 bits
Default Value:
73h (A-side space)
62h (B-side space)
Attribute: Read/Write
Bits
Description
7:4
Inbound-to-Host-Bus Route Seed.
This field represents the "seed" value used to create the routing field for packets
inbound to the system bus (i.e., third-party).
Default:
0111b
0110b
(A-side configuration space)
(B-side configuration space)
3:0
Inbound-to-Memory Route Seed.
This field represents the "seed" value used to create the routing field for packets
inbound to memory.
Default:
0011b
0010b
(A-side configuration space)
(B-side configuration space)
3.4.29 SMRAM: SMM RAM Control Register
Address Offset: 6C-6Fh
Default Value:
00000Ah
Size:
32 bits
Attribute: Read/Write
This register defines the System Management Mode RAM address range, and enables the
control access into that range. Fields of this register which exist in the MIOC SMRAM register
must be programmed to the same values.
Bits
Description
31
SMRAM Enable (SMRAME).
If set, the SMRAM space is protected from inbound PCI bus access. If clear, this
register has no effect on inbound memory accesses.
Default=0.
30:24 reserved (0)
23:20 SMM Space Size.
This field specifies the size of the SMM RAM space, in 64 KB increments.
0h
64 KB
4h 320 KB
5h 384 KB
6h 448 KB
7h 512 KB
8h 576 KB
9h 640 KB
Ah 704 KB
Bh 768 KB
Ch 832 KB
Dh 896 KB
Eh 960 KB
Fh 1 MB
1h 128 KB
2h 192 KB
3h 256 KB
Default: 0h (64 KB).
19:16 reserved (0)
15:0 SMM Space Base Address.
This field specifies the A[31:16] portion of the SMM RAM space base address
(A[15:0]=0000h). The space may be relocated anywhere below the 4 GB boundary
Intel® 450NX PCIset
3-45
3. Register Descriptions
and the Top of Memory (TOM); however, the base address must be aligned on the
next highest power-of-2 natural boundary given the chosen size. Incorrect alignment
results in indeterminate operation.
Default: 000Ah (representing a base address of A0000h)
3.4.30 TCAP: Target Capacity
Address Offset: C0-C2h
Default Value: 041082h
Size:
24 bits
Attribute: Read/Write
This register is programmed with the maximum number of transactions and data bytes that
the receiving MIOC can accept from this PXB/PCI port for inbound transactions. The MIOC
space has a set of four similar TCAP registers, one per PXB/PCI bus, that is programmed with
the transaction and data limits for outbound transactions.
If the PXB is in 32-bit bus mode, divide the MIOC BUFSIZ limits in half. If the PXB is in 64-bit
bus mode, the full MIOC BUFSIZ limits can be used, except in either case, the PXB’s
maximum values (shown below) cannot be exceeded.
Bits
Description
23:18 Inbound Write Transaction Capacity.
This field specifies the total number of inbound write transactions that can be
forwarded and enqueued in the MIOC from this PXB/PCI port.
32-bit Bus PXB maximum: 6
64-bit Bus PXB maximum: 12
Minimum allowed: 1
Minimum allowed: 1
Default= 1
Default= 1
17:12 Inbound Read Transaction Capacity.
This field specifies the total number of inbound read transactions that can be
forwarded and enqueued in the MIOC from this PXB/PCI port.
32-bit Bus PXB maximum: 2
64-bit Bus PXB maximum: 2
Minimum allowed: 1
Minimum allowed: 1
Default= 1
Default= 1
11:6
5:0
Inbound Write Data Buffer Capacity.
This field specifies the total number of data buffers available in the MIOC for use by
inbound write transactions from this PXB/PCI port, in increments of 32 bytes.
32-bit Bus PXB maximum: 6
64-bit Bus PXB maximum: 12
Minimum allowed: 2
Minimum allowed: 2
Default= 2
Default= 2
Inbound Read Data Buffer Capacity.
This field specifies the total number of data buffers available in the MIOC for use by
inbound read transactions from this PXB/PCI port, in increments of 32 bytes.
32-bit Bus PXB maximum: 8
64-bit Bus PXB maximum: 16
Minimum allowed: 2
Minimum allowed: 2
Default= 2
Default= 2
3.4.31 TMODE: Timer Mode
Address Offset: C4h
Size:
8 bits
Default Value:
00h
Attribute: Read/Write
3-46
Intel® 450NX PCIset
3.4 PXB Configuration Space
This register allows nominally fixed-duration timers to be adjusted to shorter values for test
purposes.
Bits
7:2
Description
reserved (0)
1:0
Delayed Read Request Expiration Counter.
This counter is strictly for test purposes. Changing it from the default value is a
violation of the PCI specification.
15
00
01
10
11
normal mode (2 clocks)
128 clocks
64 clocks
16 clocks
3.4.32 TOM: Top of Memory
Address Offset: 50-52h
Size:
24 bits
Default Value:
000FFFh
Attribute: Read/Write
This register specifies the highest physical address that could be directed to the memory. This
register applies to both host-initiated transactions and PCI-initiated inbound transactions, and
is therefore duplicated in both the MIOC and PXB Configuration Spaces. Software must
ensure that both sets are programmed identically to achieve correct functioning. See the
MIOC Configuration Space for a detailed description.
3.4.33 VID: Vendor Identification Register
Address Offset: 00 - 01h
Size:
16 bits
Default Value:
8086h
Attributes: Read Only
Bits
Description
15:0
Vendor Identification Number.
This is a 16-bit value assigned to Intel. Intel VID = 8086h.
Intel® 450NX PCIset
3-47
3. Register Descriptions
3-48
Intel® 450NX PCIset
System Address Maps
4
4.1 Memory Address Map
®
®
A Pentium II Xeon™ processor system based on the Intel 450NX PCIset supports up to
64 GBytes of addressable memory space. Within this memory address range the Intel 450NX
PCIset has two structured compatibility regions, two expansion gaps, and two general
purpose memory-mapped I/O spaces, as illustrated in Figure 4-1. The two compatibility
regions are the 1 MB Low Compatibility Region at the bottom of the address space, and the
20 MB High Compatibility Region just below the 4 GB boundary. The two expansion gaps
allow holes to be opened in the address space, where accesses can be directed to the PCI buses
or to a third-party agent, instead of to memory. The two I/O spaces allow control over which
addresses are forwarded to each of the four PCI buses supported by the Intel 450NX PCIset.
Spaces and Gaps
The Intel 450NX PCIset memory address map is based on spaces and gaps.
A space is an address range where the access is directed to a specific destination, usually (but
not always) a PCI bus. Any DRAM behind the space is not reclaimed, unless it is also covered
by a gap (described below). The Intel 450NX PCIset supports a variety of spaces with fixed or
configurable address ranges and individual enables.
A gap is a memory-mapped address range where the access is specifically not directed to
DRAM. The DRAM behind the gap is reclaimed; that is, the effective address presented to the
memory has the gaps subtracted from it, presenting a contiguous address space to the
memory. The gap does not control where the access is directed. Accesses may be directed
through an overlapping space, or left unclaimed on the system bus for a third-party agent to
claim. In typical maps, large spaces will be contained within gaps, to reclaim the DRAM that
would otherwise be wasted. The Intel 450NX PCIset supports two configurable gaps.
Low Compatibility Region
The Low Compatibility Region spans the first 1 MB address range (0h to F_FFFFh). This
region is divided into five subregions, some of which are further subdivided.
•
•
The 640 KB DOS Region is split into a 512 KB DOS area (memory only) and a 128 KB ISA
Window, which can be mapped to either main memory or the PCI memory.
The 128 KB Graphics Adapter Memory is normally mapped to a video device on the PCI
bus, typically a VGA controller. This region is also the default location of the
configuration SMM RAM space.
Intel® 450NX PCIset
4-1
4. System Address Maps
F_FFFF_FFFF
64 GB
20 MB Total
High BIOS
2 MB
FFE0_0000
14 MB
Top of
Memory
Local APIC
Reserved
1 MB
1 MB
1 MB
1 MB
FEF0_0000
FEE0_0000
1_0000_0000
4 GB
High
Compatibility
Region
I/O APIC
FEC0_0000
Local PCI Bus 1b
Local PCI Bus 1a
Local PCI Bus 0b
Local PCI Bus 0a
High
Expansion
Gap
100_0000
16 MB
Low
Expansion
Low ISA Space
Gap
10_0000
1 MB
Low
System BIOS
64K
64K
F_0000
E_0000
Compatibility
Ext System BIOS
96KB
32KB
ISA
Region
Channel I/O
0
C_8000
8_0000
ISA Expansion
128K
128K
Video BIOS
C_0000
A_0000
Graphics Adapter
Memory
128KB
512KB
ISA Window
DOS Area
Areas are not
drawn to scale.
640K
DOS Region
0
Figure 4-1: System Memory Address Space
•
•
The 128 KB ISA Expansion Region is divided into eight 16 KB blocks that can be
independently configured for read/write accessibility. Typically, these blocks are
mapped through the PCI bridge to ISA space. Memory that is disabled is not remapped.
Traditionally, the lower 32 KB contains the video BIOS located on a video card, and the
upper 96 KB is made available to expand memory windows in 16 KB blocks depending on
the requirements of other channel devices in the corresponding ISA space.
The 64 KB Extended System BIOS Region is divided into four 16 KB blocks and may be
mapped either to memory or the compatibility PCI bus. Typically, this area is used for
RAM or ROM. Selecting appropriate read/write attributes for this region allows the BIOS
to be “shadowed” into RAM.
4-2
Intel® 450NX PCIset
4.1 Memory Address Map
Top Of
Memory
➌
High
Gap
PCI space
➋
➌
wasted
Low
Gap
ISA space
➋
➊
➊
Host Bus Address
Physical Memory
Figure 4-2: Gaps, Spaces and Reclaiming Physical Memory
•
The 64 KB System BIOS Region is treated as a single block and is normally mapped to the
compatibility PCI bus. Selecting appropriate read/write attributes for this region allows
the BIOS to be “shadowed” into RAM. After power-on reset, the Intel 450NX PCIset has
®
this area configured to direct accesses to PCI memory, allowing fetches from the boot
ROM during system initialization.
High Compatibility Region
The High Compatibility Region spans 20 MB immediately below the 4 GB address boundary
(address range FEC0_0000h to FFFF_FFFFh). This region supports four fixed spaces with
predefined functions for compatibility with PC-based systems.
•
The 2 MB High BIOS Space is where the processor begins execution after reset. Following
power-on, the Intel 450NX PCIset has this space enabled; accesses will be directed to the
®
compatibility PCI bus. If an ISA bridge is also used, this area is then aliased by the ISA
bridge to the top of the ISA address range (14-16 MB). If this space is disabled, accesses
will be directed to memory (unless superceded by an expansion gap.)
®
•
The 1 MB Local APIC Space is reserved for use by the processor. In Pentium II Xeon™
processors, this contains the default local APIC space (which can be remapped to the I/O
APIC space, below). Accesses to this region will not be claimed by the Intel 450NX PCIset.
No resources should be mapped to this region.
•
•
The 1 MB Reserved Space is defined for future use. No resources should be mapped to this
region.
The 1 MB I/O APIC Configuration Space provides an area where I/O APIC units in the
system can be mapped, and the I/O APICs within the processors can be remapped for
consistency of access. At least one I/O APIC must be included in an Intel 450NX PCIset-
based system. The I/O APIC space may be relocated anywhere in the 4 GB boundary.
Intel® 450NX PCIset
4-3
4. System Address Maps
Top of Memory and Expansion Gaps
A “Top of Memory” pointer identifies the highest memory-mapped address that can be
serviced by this node. Accesses to addresses above this pointer will not be directed to local
memory or the PCI buses, but will be allowed to sit unclaimed on the system bus. A third-
party agent on the system bus may claim such accesses, either servicing them with its own
local resources or forwarding them to other nodes for service (i.e., a cluster bridge). Any
access that remains unclaimed will eventually timeout in the Intel 450NX PCIset; on timeout
the access is claimed by the Intel 450NX PCIset and terminated.
Below the Top of Memory, there are two programmable expansion gaps: the Low Expansion
Gap and the High Expansion Gap. Each gap, if enabled, opens a “hole” in the physical address
space, where accesses will not be directed to memory. Instead, these accesses may be directed
to one of the PCI buses, or will be allowed to sit unclaimed on the system bus where they may
be claimed by a third-party agent, as above.
Both expansion gaps are defined using base and top addresses, on 1MB boundaries. The Low
Expansion Gap must be located above the Low Compatibility Region, and below the High
Expansion Gap, the 4 GB boundary, and the Top of Memory. The High Expansion Gap must
be located above the enabled Low Expansion Gap, above 1MB, and below the Top of Memory.
At power-on, both gaps are disabled.
4.1.1
Memory-Mapped I/O Spaces
®
The Intel 450NX PCIset provides two programmable I/O spaces: the Low ISA Space and the
PCI Space. Both spaces allow accesses to be directed to a PCI bus. Any region defined as
memory-mapped I/O must have a UC (UnCacheable) memory type, set in the Pentium II
Xeon processor’s MTTR registers.
Low ISA Space
The Low ISA Space is provided to support older ISA devices which cannot be relocated above
the 16 MB address limit of older systems. Accesses to this space will be directed down to the
compatibility PCI bus (0A). The Low ISA Space can start on any 1 MB boundary below 16 MB,
and can be of size 1, 2, 4 or 8 MB.
PCI Space
The PCI Space consists of four contiguous address ranges, allowing accesses to be directed to
each of the four PCI buses supported by the Intel 450NX PCIset. Each address range
corresponds to a PCI bus, and is configurable on 1 MB boundaries.
4.1.2
SMM RAM Support
Intel Architecture processors include a System Management Mode (SMM) that defines a
protected region of memory called SM RAM. The Intel 450NX PCIset allows an SM RAM
region to be defined and enabled. When enabled, memory reads and writes to addresses that
fall within the SM RAM address range are protected accesses. If the configuration enables
permit access, and the requesting agent asserts SMMEM# (priveleged access), the MIOC will
4-4
Intel® 450NX PCIset
4.2 I/O Space
direct the access to DRAM. Otherwise, the access will be forwarded to the compatibility PCI
bus. If SMM is not enabled in the Intel 450NX PCIset, accesses are treated normally.
4.2 I/O Space
®
The Intel 450NX PCIset allows I/O accesses to be mapped to resources supported on any of
the four PCI buses. The 64KB I/O address range is partitioned into sixteen 4 KB segments
which may be partitioned amongst the four PCI buses, as shown in Figure 4-3. Host-initiated
accesses that fall within a bus’ I/O range are directed to that bus. Segment 0 always defaults to
the compatibility PCI bus.
The Intel 450NX PCIset’s I/O Range Register defines the mapping of I/O segments to each
PCI bus. This is illustrated in Figure 4-3. Accesses that fall within an I/O address range and
forwarded to the selected PCI bus, but not claimed by a device on that bus, will time-out and
be terminated by the Intel 450NX PCIset.
Segment Configuration
I/O Space Mapping to PCI Buses
ISA Alias Mode
Disabled
ISA Alias Mode
FFFF
F000
FFFF
Enabled
Segment
15
I/O
Space
Bus 1B
xFFF
xFFF
xD00
xC00
xD00
xC00
IOR.BUS1A
(top)
I/O
Space
Bus 1A
x900
x800
x900
x800
IOR.BUS0B
(top)
x500
x400
x500
x400
4000
3000
I/O
Space
Bus 0B
Segment
3
x100
x000
x100
x000
Segment
2
2000
1000
0000
IOR.BUS0A
(top)
Segment
1
Segment 0
I/O
Space
Bus 0A
03FF
Segment
0
0100
0000
0000
Figure 4-3: I/O Space Address Mapping
The Intel 450NX PCIset optionally supports ISA expansion aliasing, as shown in Figure 4-3.
When ISA expansion aliasing is supported, the ranges designated as I/O Expansion are
internally aliased to the 0100h-03FFh range in Segment 0 before the normal I/O address
range checking is performed. This aliasing is only for purposes of routing to the correct PCI
bus. The address that appears on the PCI bus is unaltered. ISA expansion aliasing is enabled
or disabled through the ISA Aliasing Enable bit in the MIOC’s CONFIG register.
Intel® 450NX PCIset
4-5
4. System Address Maps
Restricted-Access Addresses
By default, all Host-PCI I/O writes will be posted. However, in traditional Intel-architecture
systems, there are certain I/O addresses to which posting is not desirable, due to ordering
side effects. Table 4-1 lists the I/O addresses for which I/O write posting will not be
supported, regardless of the posting enable in the MIOC’s CONFIG register. These accesses
will be deferred instead.
Table 4-1: Non-Postable I/O Addresses
Address
0020h-0021h
0060h-0064h
0070h
Function
8259A Interrupt Controller, Master, Interrupt Masks
Keyboard controller: com/status and data
NMI# Mask
0092h
A20 Gate
00A0h-00A1h
00F0h
8259A Interrupt Controller, Slave, Interrupt Masks
IGNNE#, IRQ13
0CF8h, 0CFCh PCI configuration space access
4.3 PCI Configuration Space
®
The Intel 450NX PCIset provides a PCI-compatible configuration space for the MIOC, and
two in the PXB—one for each PCI bus. I/O reads and writes issued on the system bus are
normally claimed by the MIOC and forwarded through the PXBs as I/O reads and writes on
the PCI bus. However, I/O accesses to the 0CF8h and 0CFCh addresses are defined as special
configuration accesses for I/O devices.
Each configuration space is selected using a Bus Number and a Device Number within that
bus. PCI buses are numbered in ascending order within hierarchical buses. PCI Bus #0
represents both the compatibility PCI bus as well as the devices in the Intel 450NX PCIset and
any third party agents attached to the system bus.
The MIOC and each PCI bus within each PXB in the system is assigned a unique Device
Number on Bus #0, as shown in Table 4-2. The PXBs are numbered based on the Expander
bus port used.
1 2
Table 4-2: Device Numbers for Bus Number 0
Device
Number
Device
Number
Device
Device
10h
11h
12h
13h
MIOC
18h
19h
1Ah
1Bh
reserved
3
PXB 0, Bus a
PXB 0, Bus b
4-6
Intel® 450NX PCIset
4.3 PCI Configuration Space
1 2
Table 4-2: Device Numbers for Bus Number 0 (Continued)
Device
Number
Device
Number
Device
Device
14h
15h
16h
17h
PXB 1, Bus a
PXB 1, Bus b
1Ch
1Dh
1Eh
1Fh
Third Party Agent
Third Party Agent
Third Party Agent
4
n/a
1. Device numbers 0-15 represent devices actually on the compatibility PCI bus.
2. Shaded columns are defined for future PCIset compatibility.
3. This is the compatibility PCI bus.
4. Bus #0/Device # 31 is used (along with a Function Number of all 1’s and a
Register Number of all 0’s) to generate a PCI Special Cycle. Therefore Bus
#0/Device #31 is never mapped to a device.
Intel® 450NX PCIset
4-7
4. System Address Maps
4-8
Intel® 450NX PCIset
Interfaces
5
5.1 System Bus
®
®
The host interface of the Intel 450NX PCIset is targeted toward Pentium II Xeon™
processor-based multiprocessor systems, and is specifically optimized for four processors
sharing a common bus with bus clock frequencies of 100 MHz. The MIOC provides the
system bus address, control and data interfaces for the Intel 450NX PCIset, and represents a
single electrical load on the system bus.
The Intel 450NX PCIset recognizes and supports a large subset of the transaction types that
are defined for the P6 family processor’s bus interface. However, each of these transaction
types have a multitude of response types, some of which are not supported by this controller.
The responses that are supported by the MIOC are: Normal without Data, Normal with Data,
Retry, Implicit Write Back, Deferred Response. Refer to the chapter on Transactions for more
details on the transaction types supported by the Intel 450NX PCIset.
5.2 PCI Bus
Each PXB provides two independent 32-bit, 33 MHz Rev. 2.1-compliant PCI interfaces which
support 5 volt or 3 volt PCI devices. Each bus will support up to 10 electrical loads, where the
PXB and the PIIX4E south bridge each represent one load, and each connector/device pair
represents two loads. The internal bus arbiter supports six PCI bus masters in addition to the
PXB itself and the south bridge on the compatibility bus. The compatibility bus is always bus
#0A (PXB #0, Bus A).
The PCI buses are operated synchronously with the system bus, using the system bus clock as
®
the master clock. A system bus/PCI bus clock ratio of 3:1 supports the Intel Pentium II
Xeon™ processor at 100 MHz with 33.3 MHz PCI bus, or a degraded 90 MHz system bus with
a 30 MHz PCI bus (or lower, depending on the effect of the 6th load on the system bus).
A configuration option allows the two 32-bit PCI buses (A and B) on a single PXB to be
operated in combination as a single 64-bit PCI bus. Bus A data represents the low Dword,
while bus B data represents the high Dword.
5.3 Expander Bus
The Expander Interface provides a bidirectional path for data and control between the PXB
and MIOC components. The Expander bus consists of a 16 bit wide data bus which carries
command, address, data, and transaction information. There are two additional bits that carry
Intel® 450NX PCIset
5-1
5. Interfaces
Byte enable information for data fields. All 18 of these bits are protected by an even parity
signal. Two synchronous arbitration signals (one in each direction) are used for each
Expander bus.
5.3.1
Expander Electrical Signal and Clock Distribution
The Expander bus is designed to allow multiple high bandwidth I/O ports to be added to the
®
Intel 450NX PCIset with minimal impact on signal pin count. The Expander bus also
provides flexibility in server system topology by allowing the I/O subsystem to be located
away from the main PCIset. This flexibility is achieved with a signaling scheme that uses a
combination of synchronous and source synchronous clocking. This is illustrated in Figure 5-
1.
Expander Bus
HRTS#
MIOC
PXB
XRTS#
XADS#
XBE[1:0]
XD[15:0]
XPAR
HSTBP#
HSTBN#
Strobe
Synch
XSTBP#
XSTBN#
Strobe
Synch
XRSTFB#
XRSTB#
XRST#
(L1)
(L2)
PXB
RST
XCLK
(L3)
(L4)
R
PLL
FB
XCLKB
XCLKFB
HCLKIN
R
PLL
FB
Required length matching: L1=L2=L3=L4
Core CLK
Figure 5-1: Expander Bus Clock Distribution
5.4 Third-Party Agents
®
®
In addition to the processors and the Intel 450NX PCIset, the Pentium II Xeon™ processor
bus allows for additional bus masters, generically referred to as third-party agents (TPA).
These agents may be symmetric agents, in which case they must participate in the bus
arbitration algorithm used by the processors. They may also be priority agents, in which case
they must negotiate with the Intel 450NX PCIset for control of the system bus.
5-2
Intel® 450NX PCIset
5.5 Connectors
The Intel 450NX PCIset supports the same request/grant and third-party control signals
originally provided by the Intel 450GX PCIset. Theses signals are used to exchange priority
ownership of the bus between the TPA and the Intel 450NX PCIset. The Intel 450NX PCIset
makes no assumptions about the relative priorities between the Intel 450NX PCIset and the
TPA, and will grant priority ownership at the next natural transaction boundary. The Intel
450NX PCIset also makes no assumptions about the frequency of TPA requests or the
duration of TPA bus ownership; it is the responsibility of the TPA to ensure that its use of the
system bus is commensurate with its intended purpose and expected system performance.
5.5 Connectors
Connectors are permitted only for the memory cards and between the MIOC and PXBs.
Between MIOC and PXB, some degree of “stretch” distance is possible, with specific distance
dependent on the design and medium chosen. Connectors are specifically not permitted
between the MIOC and the system bus.
Intel® 450NX PCIset
5-3
5. Interfaces
5-4
Intel® 450NX PCIset
Memory Subsystem
6
6.1 Overview
®
The Intel 450NX PCIset’s memory subsystem consists of one or two memory cards. Each
card is comprised of one RCG component, a DRAM array, and two MUX components. Table
6-1 summarizes the Intel 450NX PCIset’s general memory characteristics.
Table 6-1: General Memory Characteristics
DRAM type
Extended Data Out (EDO)
Memory modules
72-bit, single and double high DIMMs
DRAM technologies 16 Mbit and 64 Mbit
50 and 60 nsec
3.3 V
Interleaves
4:1, 2:1 (in bank 0, of card 0)
Memory size
2:1 interleave: 32 MB
4:1 interleave: 64 MB to 8 GB, in 64 MB increments
6.1.1
Physical Organization
®
The Intel 450NX PCIset supports up to 8 banks of memory, configured across one or two
memory cards. Each bank can support up to 1 GB using 64 Mbit double-high DIMMs to
provide a total of 8 GB of memory in 8 banks. Each bank can support one or two rows of 2 or 4
interleaves. Each row represents a set of memory devices simultaneously selected by a RAS#
signal. Each interleave generates 72 bits (64 data, 8 ECC) of data per row using one DIMM.
Four interleaves provide a total of 256 bits of data (32 bytes) which is one cache line for the
®
Pentium II Xeon™ processor. Data from multiple interleaves are combined by the MUXs to
exchange 72 bits of data with the MIOC at an effective rate of one cache line every 30ns
(effective rate: 1.067 GB/s) for a 4-way interleaved memory. Figure 6-1 illustrates this
configuration.
The RCG and MUX Components
The RCGs generate the signals to control accesses to the main memory DRAMs. The RCG
initiates no activity until it receives a command from the MIOC. The maximum number of
RCGs per Intel 450NX PCIset system is two. Each RCG controls up to four banks of DRAM.
Each bank of memory may consist of one (for single-sided DIMMs) or two (for double-sided
or double-high DIMMs) rows. Internally, each RCG component contains four RAS/CAS
control units (RCCUs), each dedicated to one bank of DRAM. This is illustrated in Figure 6-2.
Each MUX component has four 36-bit data I/O connections to DRAM (one 18-bit path for
each of four possible interleaved quad-words) and one 36-bit data I/O connection to the MD
Intel® 450NX PCIset
6-1
6. Memory Subsystem
Pentium® II Xeon™ processor system bus
addr[35:0], data[71:0] & ctrls
MD[71:0]
memory cards
2x36
MUXs
Memory
Control
MIOC
72
Interface
36
36
rows
bank
Card 1
to PCI via
Expander bridge
Card 0
Figure 6-1: Memory Configuration Using 2 Cards
To/From MIOC
Memory Array
RASA[a:d][1:0]#, CASA[a:d][1:0]#, WEA[a:b]#
ADDRA[13:0]
Bank A
RASB[a:d][1:0]#, CASB[a:d][1:0]#, WEB[a:b]#
ADDRB[13:0]
Bank B
RCG
#0
RASC[a:d][1:0]#, CASC[a:d][1:0]#, WEC[a:b]#
ADDRC[13:0]
Bank C
Bank D
RASD[a:d][1:0]#, CASD[a:d][1:0]#, WED[a:b]#
ADDRD[13:0]
AVWP#
LDSTB#
LRD#
WDME#
MUXs (2)
To/From Other RCGs
DOFF[1:0]#
DSEL#
DVALID[a:b]#
WDEVT#
DCMPLT[a:b]#
DSTBP[3:0]#
DSTBN[3:0]#
GDCMPLT#
To/From Other MUXs
From MIOC
To/From MIOC
Figure 6-2: Example Showing RCG/MUX Control Signals
6-2
Intel® 450NX PCIset
6.1 Overview
bus. There are two MUX components per board to provide a 72-bit data path from each of
four possible interleaved quad-words to the MD bus. This is illustrated in Figure 6-3.
Memory
Card
MUX
MUX
MD[71:0]
DSTBP[3:0]#,
DSTBN[3:0]#
To MIOC
To other memory card
Figure 6-3: Memory Card Datapath
6.1.2
Configuration Rules and Limitations
Memory array configurations are governed by the following rules:
•
•
•
•
Either one or two cards can be populated in a working system.
Any number of memory rows, on either card, can be populated in a working system.
Memory banks can be populated in any order on either card.
Cards designed to support 4:1 interleaving will also support 2:1 interleaves (in the first
bank only).
•
•
Within any given row, the populated interleaves must have DIMMs of uniform size.
Memory sizes (16 MB vs. 64 MB) may be mixed within a memory card, but must be the
same within a bank.
•
Memory speeds (60ns or faster) may be mixed, but all four banks within an RCG operate
at the same speed, and must therefore be configured to the slowest DIMM in the set.
6.1.2.1
Interleaving
The Intel 450NX PCIset supports 4:1 interleaving across all banks, and 2:1 interleaving in the
first bank of card #0 only. The Intel 450NX PCIset does not support non-interleaved
configurations. Interleave configuration register programming must be consistent across the
entire memory system. For example, if one bank is configured as 4:1 then the entire memory
sub-system must be 4:1 and the associated memory bank configuration registers must be
programmed as 4:1.
To support a 4:1 interleave requires two MUXs. Supporting a 2:1 interleave requires only one
MUX. A two-MUX design will also support 2:1 interleaves. An entry-level card (i.e., 2:1
Intel® 450NX PCIset
6-3
6. Memory Subsystem
interleave) that may be expanded beyond the first bank must therefore be designed using two
MUXs.
Table 6-2 gives a summary of the characteristics of memory configurations supported by the
Intel 450NX PCIset for 4-way interleaved memory cards.
Table 6-2: Minimum and Maximum Memory Size Per Card
Memory Size for
Addressing
4-way Interleave
DRAM
Technology&
Config.
Max
(Double-
high
DIMM
Size
Size
Min
Max
Mode
row/col (DIMMs) (DIMMs)
DIMMs)
16M
64M
2M x 8
4M x 4
2M x 72 Asymmetric
11 10
64 MB
256 MB
512 MB
512 MB
1 GB
4M x72 Symmetric
Asymmetric
11 11
12 10
128 MB
8M x 8
8M x 72 Asymmetric
12 11
256 MB
512 MB
1 GB
2 GB
2 GB
4 GB
16M x 4 16M x 72 Symmetric
Asymmetric
12 12
13 11
6.1.2.2
Address Bit Permuting Rules and Limitations
The Intel 450NX PCIset supports permuting of cache lines across two or four populated
banks. For a complete description of the operation of Address Bit Permuting (ABP) see Section
6.1.3.
The following rules and limitations are required for ABP to operate properly.
•
•
•
All banks must be in 4:1 interleave mode.
There must be a power of two number of banks populated.
All banks within an ABP group (2 banks in 2 bank permuting and 4 banks in 4 bank
permuting) must be the same size.
•
•
All populated rows must be adjacent and start at bank 0.
Both cards in a system must be configured to allow equivilent ABP settings (i.e., Card 0
and Card 1 must both be configured according to the above rules for the current setting of
the ABP enable.)
6.1.2.3
Card to Card (C2C) Interleaving Rules and limitations
Card to Card Interleaving is described in detail in Section 6.1.4. All of the ABP rules defined
above apply to C2C interleaving, plus the following rules:
•
The memory cards must be identically populated with memory DIMMs of the same size
and type.
•
The DBC registers must be programmed in the alternate C2C order as defined in the C2C
functional description in Section 6.1.4.
6-4
Intel® 450NX PCIset
6.1 Overview
6.1.3
Address Bit Permuting
Address Bit Permuting works by increasing the likelihood that requests spaced closely
together in time access different banks of memory which will already be closed and
precharged.
This is achieved by distributing the addresses, on a cache line size granularity, across either
two or four banks of memory. The lowest order address bits which define a cache line are
used as the bank selects into the memory array so that all requests to a zero based cache line
are directed at bank 0. This is illustrated in Figure 6-4.
Request address accesses bank:
4 Bank Permuting
0h, 80h, 100h, ....
Bank 0
Bank 1
Bank 2
Bank 3
20h, A0h, 120h, ...
40h, C0h, 140h, ...
60h, E0h, 160h, ...
Request address accesses bank:
Bank 0
Bank 1
2 Bank Permuting
0h, 40h, 80h, ....
20h, 60h, A0h, ...
Figure 6-4: Effect of Address Bit Permuting on Bank Access Order
6.1.4
Card to Card (C2C) Interleaving
The purpose of the C2C feature is to further distribute memory accesses across multiple banks
of memory as done with the ABP modes. This mode is supported in addition to the standard
ABP modes so that maximum distribution of memory accesses and hence, maximum
sustained bandwidth can be acheived.
The distribution of accesses to each memory card with C2C enabled is by cache line with all
even cache lines sent to Card 0 and all odd cache lines sent to Card 1. The feature can be
enabled, if all of the restricions are met, by setting bit 2 of the MIOC CONFIG register.
With C2C enabled the DRAM Bank Configuration Registers become mapped to the physical
memory differently than with C2C disabled (default mode). Figure 6-5 shows both the C2C
disabled and enabled modes mapping of DRAM Bank Configuration Registers to physical
bank location.
With C2C enabled and 2 bank ABP enabled Banks 0, 1, 2 and 3 must all be the same size and
type and Banks 4, 5, 6 and 7 (if present) must be the same size and type.
With C2C enabled and 4 bank ABP enabled Banks 0 through 7 must all be the same size and
type.
Intel® 450NX PCIset
6-5
6. Memory Subsystem
With C2C enabled and no ABP enabled each pair of consecutive banks must be of the same
size and type. For example Banks 0 and 1 must be the same size and type and Banks 2 and 3
must be the same size and type but need not match Banks 0 and 1.
C2C Disabled Bank Register Ordering
Bank 0
Bank 1
Bank 2
Bank 3
Bank 8
Bank 9
Bank 10
Bank 11
Memory Card 0
Memory Card 1
C2C Enabled Bank Register Ordering
Bank 0
Bank 2
Bank 4
Bank 6
Bank 1
Bank 3
Bank 5
Bank 7
Memory Card 0
Memory Card 1
Figure 6-5: DRAM Bank Configuration Register Programming with C2C
Disabled and Enabled
6.1.5
Memory Initialization
The MIOC provides an MRESET# output, which is asserted on power-good reset, system
hard reset, and a BINIT reset. The MRESET# signal is sent to all RCGs and MUXs in the
memory subsystem. When asserted, each RCG and MUX clears their transaction queues, data
buffers and transaction state. Any transactions that may have been in-progress or pending in
the memory subsystem are lost. Note that this may corrupt the contents of the DRAMs, and
could leave the DRAMs themselves in an intermediate state, unable to accept a new
transaction. Following MRESET# deassertion, the MIOC will re-initialize the memory
subsystem by issuing eight CAS#-before-RAS# refreshes per bank (this does not affect the
data held in the memory).
6-6
Intel® 450NX PCIset
Transaction Summary
7
®
This chapter describes the transactions supported by the Intel 450NX PCIset.
7.1 Host To/From Memory Transactions
7.1.1
Reads and Writes
The Read transactions supported by the Intel 450NX PCIset are: Partial Reads, Part-line Reads,
Cache Line Reads, Memory Read and Invalidate (length > 0), Memory Read and Invalidate (length =
0), Memory Read (length = 0).
The Write transactions supported by the Intel 450NX PCIset are: Partial Writes, Part-line Writes,
Cache Line Writes.
7.1.2
7.1.3
Cache Coherency Cycles
The MIOC implements an implicit writeback response during system bus read and write
transactions when a system bus agent asserts HITM# during the snoop phase. In the read case
the MIOC snarfs the writeback data and updates the DRAM. The write case has two data
transfers: the requesting agent’s data followed by the snooping agent’s writeback data.
Interrupt Acknowledge Cycles
A processor agent issues an Interrupt Acknowledge cycle in response to an interrupt from an
8259-compatible interrupt controller. The Interrupt Acknowledge cycle is similar to a partial
read transaction, except that the address bus does not contain a valid address. The interrupt
acknowledge request issued by the processor is deferred by the MIOC and forwarded to PXB
#0, which performs a PCI Interrupt Acknowledge cycle on PCI bus #0A (the compatibility PCI
bus).
7.1.4
Locked Cycles
The system bus specification provides a means of performing a bus lock. Any Host-PCI locked
transaction will initiate a PCI locked sequence. The processor implements the bus lock
Intel® 450NX PCIset
7-1
7. Transaction Summary
mechanism which means that no change of bus ownership can occur from the time the agent
has established the locked sequence (i.e., asserts LOCK# signal on the first transaction and
data is returned) until it is completed. The DRAM is locked from the PCI perspective until the
host locked transaction is completed.
7.1.5
7.1.6
Branch Trace Cycles
An agent issues a Branch Trace Cycle for taken branches if execution tracing is enabled. The
address Aa[35:3]# is reserved and can be driven to any value. D[63:32]# carries the linear
address of the instruction causing the branch and D[31:0]# carries the target linear address.
The MIOC will respond and retire this transaction but will not latch the value on the data lines
or provide any additional support for this type of cycle.
Special Cycles
Special cycles are used to indicate to the system some internal processor conditions. The first
address phase Aa[35:3]# is undefined and can be driven to any value. The second address
phase, Ab[15:8]# defines the type of Special Cycle issued by the processor. Table 7-1 below
specifies the cycle type and definition as well as the action taken by the MIOC when the
corresponding cycles are identified.
Table 7-1: MIOC Actions on Special Cycles
Ab[15:8]
Cycle Type
Action Taken
0000 0000 NOP
This transaction has no side-effects.
0000 0001 Shutdown
This cycle is claimed by the MIOC. No corresponding cycle
is delivered to the PCI bus. The MIOC asserts INIT# back to
the agent for a minimum of 4 clocks.
0000 0010 Flush
0000 0011 Halt
The MIOC claims this cycle and retires it.
This cycle is claimed by the MIOC, forwarded to the
compatability PCI bus as a Special Halt Cycle, and retired
on the system bus after it is terminated on the PCI bus via a
master abort mechanism.
0000 0100 Sync
The MIOC claims this cycle and retires it.
The MIOC claims this cycle and retires it.
0000 0101 Flush
Acknowledge
0000 0110 Stop Clock
This cycle is claimed by the MIOC and propagated to the
Acknowledge PCI bus as a Special Stop Grant Cycle. It is completed on the
system bus after it is terminated on the PCI bus via a master
abort mechanism.
0000 0111 SMI
The MIOC’s SMIACT# signal will be asserted upon
Acknowledge detecting an SMI Acknowledge cycle with SMMEM#
asserted, and will remain asserted until detecting a
subsequent SMI Acknowledge cycle with SMMEM#
deasserted.
all others Reserved
7-2
Intel® 450NX PCIset
7.1 Host To/From Memory Transactions
7.1.7
System Management Mode Accesses
The Intel 450NX PCIset uses an SMRAM configuration register to enable, define and control
access to the SMM RAM space. The SMM RAM space defaults to location A000h, with a size
of 64 KB, but may be relocated and grown in increments of 64 KB. A master enable (SMRAME)
and three access-control enables (Open, Closed, Locked) determine how accesses to the space
are to be serviced. Table 7-2 summarizes how accesses to the SMM RAM space are serviced.
Table 7-2: SMRAM Space Cycles
Code
Fetch
Data
Reference
Usage
1
1
0
1
X
0
X
0
X
X
X
0
Normal
Normal
SMM RAM space is not supported.
PCI 0a
PCI 0a
Normal SMM usage. Accesses to the SMM
RAM space from processors in SMM will
access the DRAM. Accesses by processors
not in SMM will be diverted to the
compatibility PCI bus.
1
0
0
X
1
DRAM
DRAM
1
1
0
0
1
1
X
X
0
1
PCI 0a
DRAM
PCI 0a
PCI 0a
A modification of the normal SMM usage, in
which only code fetches are accepted from
processors in SMM mode.
1
1
X
0
X
DRAM
DRAM
Full access by any agent to SMM RAM
space. Typically used by the BIOS to
initialize SMM RAM space.
1. SMRAM functions are disabled. The access is serviced like any other. The address is checked
against the other space and gap definitions to determine its disposition -- to PCI, to memory, or to
the system bus for a third party agent to claim.
7.1.8
Third-Party Intervention
The Intel 450NX PCIset supports the same third-party control sideband controls that were
defined in Intel 450GX PCIset. These controls allow an external agent on the system bus to
affect the way in which the MIOC responds to a system bus request to memory. This external
agent is referred to as a “third-party” to the transaction. When a third-party agent intervenes
in the normal transaction flow, both the MIOC and the third-party share responsibility for
generating the appropriate response; however, the MIOC is always the “owner” of the
transaction, and hence must be the responding bus agent.
The third-party controls how the MIOC responds by asserting a code on the sideband
TPCTL[1:0] signals during the snoop phase. The MIOC samples these signals in the last cycle
of the snoop phase. Table 7-3 indicates the actions possible using the TPCTL[1:0] signals.
Intel® 450NX PCIset
7-3
7. Transaction Summary
Table 7-3: TPCTL[1:0] Operations
Action
TPCTL
[1:0]
00
Accept. The MIOC accepts the request, and provides the normal response.
The third-party agent is not involved in the transaction.
®
01
10
Hard Fail. Not supported by the Intel 450NX PCIset.
Retry. The MIOC will generate a retry response. The access will be retried by
the requesting agent.
11
Defer. The MIOC will issue a defer response, and the third-party agent will
complete the transaction at a later time using a deferred reply.
7.2 Outbound Transactions
7.2.1
7.2.2
7.2.3
Supported Outbound Accesses
The PXB translates valid system bus commands into PCI bus requests. For all Host-PCI
transactions the PXB is a non-caching agent since the Intel 450NX PCIset does not support
cacheability on PCI. However, the PXB must respond appropriately to the system bus
commands that are cache oriented.
Outbound Locked Transactions
The Intel 450NX PCIset supports memory-mapped outbound locked operations. I/O-
mapped outbound locked transactions are not supported. Further, a locked transaction
cannot be initiated with a zero-length read. These restrictions are consistent with the
transactions supported by the processor.
Outbound Write Combining
The Intel 450NX PCIset provides its own write combining for Host-PCI write transactions. If
enabled, and multiple Host-PCI writes target sequential locations in the PCI space, the data is
combined and sent to the PCI bus as a single write burst. This holds true for all memory
attributes, not just WC. There is no corresponding write-combining for the Host-DRAM
path.
7.2.4
Third-Party Intervention on Outbounds
The use of the third-party control signals (TPCTL) is not supported for outbound transactions
(Host-PCI). Assertion of the TPCTL signals during an outbound transaction will have
7-4
Intel® 450NX PCIset
7.3 Inbound Transactions
indeterminate results. Assertion of DEFER# during an outbound transaction will also have
indeterminate results.
7.3 Inbound Transactions
®
For all inbound transactions, the Intel 450NX MIOC will use an Agent ID of ‘1001b (9). This
is the same agent ID used by the Intel 450GX PCIset, which the Intel 450NX PCIset replaces.
Note that memory-mapped accesses across PCI buses (i.e., peer-to-peer transfers) are not
supported. Also, inbound I/O transactions are not supported, either to other PCI buses or to
the system bus.
7.3.1
Inbound LOCKs
Inbound (PCI-to-system bus) LOCKs are not supported in the Intel 450NX PCIset. Use of
inbound locks on the Intel 450NX PCIset may result in unanticipated behavior. The Intel
450NX PCISet is NOT compatible with devices on the compatibility PCI bus which are
capable of initiating inbound bus- or resource-locks. Deadlock may occur between outbound
locked transactions, south bridge-initiated Secure Sideband Requests (PHOLD#), and LOCK#
assertion by the offending device. Devices capable of asserting LOCK# to access memory
should not be used on the compatibility PCI bus.
7.3.2
South Bridge Accesses
The PXB’s Bus ‘a’ has sideband signals to support the PIIX4E south bridge for ISA expansion.
The PXB does not support an EISA bridge.
WSC# Handshake
When the PIIX4E south bridge issues an interrupt for an ISA master, it must first check that
any writes posted from ISA to memory have been observed before the interrupt is issued.
This action is necessary to guarantee that an ISA write followed by an ISA interrupt is
observed in that same order by a processor on the system bus.
Whenever the compatibility bus PXB receives a write from the south bridge, it will deassert
the WSC# (Write Snoop complete) signal. WSC# will remain de-asserted until the write
Completion for that write has returned. When the Completion returns, WSC# is again
asserted. While WSC# is de-asserted the PXB must retry any additional writes from the south
bridge.
The PXB will only support the WSC# Handshake when the internal arbiter is used. When
operating in external arbiter mode, the PXB will always hold WSC# asserted. The WSC#
mode may be disabled by a bit in the PXB’s CONFIG register. If disabled, WSC# stays
asserted and inbound writes from the south bridge are accepted.
Intel® 450NX PCIset
7-5
7. Transaction Summary
Distributed DMA
Distributed DMA across the PCI bus is not supported by the Intel 450NX PCIset. This
function is incompatible with the passive release mechanism portion of the PHOLD#/PHLDA#
protocol used to grant PCI bus access to south bridges.
Accesses Prohibited to Third-Party Agent
The Intel 450NX PCIset only supports inbound south bridge accesses to memory. Inbound
accesses from a south bridge using the PHOLD#/PHLDA# protocol, directed to a third-party
agent on the system bus, are not supported. Such accesses, involving interactions with
unknown and unpredictable agents, could violate the rules governing the PHOLD#/PHLDA#
protocol, potentially leading to deadlocks.
7.4 Configuration Accesses
The PCI specification defines two mechanisms to access configuration space, Mechanism #1
®
and Mechanism #2. The Intel 450NX PCIset supports only Mechanism #1.
Mechanism #1 defines two I/O-space locations: an address register (CONFIG_ADDRESS) at
location
, and a data register (CONFIG_DATA) at location
0CF8h
. The Intel 450NX
0CFCh
PCIset provides a PCI-compatible configuration space for the MIOC, and one for each PCI bus
in the PXB.
•
If the MIOC detects the I/O request is a configuration access to its own configuration
space, it will service that request entirely within the MIOC. Reads result in data being
returned to the system bus.
•
If the MIOC detects the I/O request is a configuration access to a PXB configuration space,
it will forward the request to the appropriate PXB for servicing. The request is not
forwarded to a PCI bus. Reads will result in data being returned by the PXB through the
MIOC to the system bus.
•
•
If the MIOC detects the I/O request is a configuration access to a third-party agent on the
system bus, it will leave the access unclaimed on the system bus. The third-party agent
may claim the access, with reads resulting in data being returned by the third-party agent
to the system bus.
Otherwise, the access is forwarded on to the PXB to be placed on the PCI bus as a
Configuration Read or Configuration Write cycle.
Reads will result in data being
returned through the PXB and MIOC back to the system bus, just as in normal Outbound
Read operations.
7-6
Intel® 450NX PCIset
Arbitration, Buffers & Concurrency
8
8.1 PCI Arbitration Scheme
The PCI Specification Rev 2.1 requires that the arbiter implement a fairness algorithm to avoid
deadlocks and that it assert only a single GNT# signal on any rising clock. The arbitration
algorithm is fundamentally not part of the PCI Specification.
The PXB contains an internal PCI arbiter. This arbiter can be disabled either when the PXB
operates with I/O bridges which include this function, or when a customized PCI arbiter
solution is required. The Internal PCI Arbiter has the following features:
•
•
•
•
•
•
•
•
•
Support for 6 PCI masters, Host and I/O Bridge
2 Level Round Robin
Bus Lock Implementation
Bus Parking on last agent using the bus
4-PCI clock grant (FRAME#) time-out
Multi Transaction Timer (MTT) mechanism
PCI arbitration is independent from the system bus arbitration
PIIX4E- compatible protocol (EISA bridges are not supported)
PCI Protocol Requirements
8.2 Host Arbitration Scheme
The system bus arbitration protocol supports two classes of bus agents: symmetric agents and
priority agents. The processors arbitrate for the system bus as symmetric agents using their
own signaling. Symmetric agents implement fair, distributed arbitration using a round-robin
algorithm. The MIOC, as an I/O agent, uses a priority agent arbitration protocol to obtain the
ownership of the system bus. Priority agents use the BPRI# signal to immediately obtain bus
ownership.
Besides two classes of arbitration agents (symmetric and priority agents), each bus agent has
two mechanisms available that act as arbitration modifiers: the bus lock (LOCK#) and the
request stall (BNR#).
Intel® 450NX PCIset
8-1
8. Arbitration, Buffers & Concurrency
8.2.1
Third Party Arbitration
The Intel 450NX PCIset requests the system bus with BPRI#. If multiple bridges or a third
party agent is on the system bus, an arbitration method is required to establish bus ownership
among multiple requesting bridges (which bridge can drive BPRI#). This arbitration is
®
transparent to the Pentium II Xeon™ processors or other symmetric bus agents. Only one
bridge is allowed to drive BPRI# at a time.
8.3 South Bridge Support
®
The Intel 450NX PCIset is designed to work with the PIIX4E south bridge which connects the
PCI bus to ISA bus and I/O APIC components. Note that the protocols described here apply
only when the Intel 450NX PCIset is used in internal arbiter mode — use of the PIIX4E in
external arbiter configurations is not supported.
The Intel 450NX PCIset does not guarantee ISA access latencies of < 2.5 usec. ISA devices
which require these latencies to be met (GAT mode timing) are not supported.
8.3.1
I/O Bridge Configuration Example.
The basic I/O bridge configuration supported by the Intel 450NX PCIset is shown in Figure 8-
1. The figure shows the sideband signals that connect the PXB to the PIIX4E, I/O APIC
components and the external arbiter. Note that PHOLD#/PHLDA# are connected between
PXB and the PIIX4E, and WSC# output from PXB is connected to the APICACK2# input of the
stand-alone I/O APIC component. If the configuration does not have I/O APIC component,
then WSC# pin is left unconnected.
REQ#[0:5]
PHLDA#
GNT#[0:5]
EXTARB
WSC#
NC
PHOLD#
PXB
PCI bus
APICREQ#
APICACK#
APICREQ#
APICACK#
PHOLD#
PHLDA#
APICACK2#
PIIX4E
I/O APIC
Figure 8-1: ISA Bridge with the I/O APIC (Internal Arbiter)
8-2
Intel® 450NX PCIset
8.3 South Bridge Support
8.3.2
PHOLD#/PHLDA# Protocol
The PIIX4E uses only two signals to obtain the ownership of the PCI bus. The PIIX4E will
assert PHOLD# to indicate that an ISA master is requesting to run a cycle (DREQ active) or an
integrated PCI-IDE bus-mastering device is requesting the PCI bus.
DREQ#
DGNT#
<PCI req
from PIIX>
active
bus
release
passive
bus
release
passive
bus
release
PHOLD#
PHLDA#
<Host-PCI
writes
disabled>
<other
PCI
trans>
Figure 8-2: PHOLD#/PHLDA# Protocol Showing Active
and Passive Bus Release
8.3.3
WSC# Protocol
The WSC# (Write Snoop Complete) is a status signal output from the Intel 450NX PCIset PXB.
The WSC# assertion indicates that all necessary snoops for a previously posted PCI-DRAM
write have been completed on the system bus.
The WSC# signal is primarily used by the I/O APIC device connected to the ISA bridge. The
I/O APIC uses this signal to maintain data coherency and ordering of transactions in the
system.
NOTE
The WSC# Handshake only applies if the PXB is in internal arbiter mode.
Intel® 450NX PCIset
8-3
8. Arbitration, Buffers & Concurrency
PCLK
FRAME#
C/BE#
AD(31:0)#
IRDY#
DEVSEL#
STOP#
TRDY#
WSC#
PHOLDA#
Figure 8-3: WSC# Signal Functionality
8-4
Intel® 450NX PCIset
Data Integrity & Error Handling
9
This chapter describes the data integrity support and general error detection and reporting
®
mechanisms used in the Intel 450NX PCIset.
9.1 DRAM Integrity
®
Both the system data bus and the Intel 450NX PCIset’s memory subsystem use a common
Error Correcting Code which provides SEC/DED/NED coverage. The ECC used is capable of
correcting single-bit errors and detecting 100% of double-bit errors over one code word.
9.1.1
9.1.2
9.1.3
ECC Generation
When enabled, the DRAM ECC mechanism allows automatic generation of an 8-bit
protection code for the 64-bit (Qword) of data during DRAM write operations. Note that
when ECC is intended to be enabled, the whole DRAM array must be first initialized by doing
writes before the DRAM read operations can be performed. This will establish the correlation
between 64-bit data and associated 8-bit ECC code which does not exist after power-on. This
function is not provided by hardware.
ECC Checking and Correction
During DRAM read operations, a full Qword of data (8 bytes) is always transferred from the
DRAM to the MIOC regardless of the size of the originally requested data. Both 64-bit data
and 8-bit ECC code are transferred simultaneously from the DRAM to the MIOC. The ECC
checking logic in the MIOC uses the received 72 bit Data + ECC to generate the check
syndrome. If a single-bit error is detected the ECC logic corrects the identified incorrect data
bit.
ECC Error Reporting
When ECC checking is enabled, single-bit and multiple-bit errors detected by the ECC logic
are logged in the MIOC. The first two errors detected on reads-from-memory are logged, as
are the first two errors detected on data received from the system bus.
For memory errors, the error type (single-bit or multi-bit), syndrome, chunk and effective
address are logged. The first two memory errors (single-bit or multi-bit) will be logged in the
Intel® 450NX PCIset
9-1
9. Data Integrity & Error Handling
MEL and MEA registers. For bus errors, the error type, syndrome and chunk are logged. The
first two system bus errors (single-bit or multi-bit) will be logged in the HEL registers.
All ECC error logging registers are sticky through reset, allowing software to determine the
source of an error after restoring the system to functioning mode. The logging registers hold
their values until explicitly cleared by software.
Error Signaling Mechanism
Single-bit correctable errors are not critical from the point-of-view of presenting the correct
value of data to the system. The DRAM (if the cause of error is a DRAM array) will still
contain faulty data which will cause the repetition of error detection and recovery for the
subsequent accesses to the same location.
Multi-bit uncorrectable errors are fatal system errors and will cause the MIOC to assert the
BERR# signal if enabled in the ERRCMD register. The uncorrected data is forwarded to its
destination. For the first two multi-bit uncorrectable errors, the MIOC will log in the MEA
register the row number where the error occurred. This information can be used later to point
to a faulty DRAM DIMM.
The MEA/MEL registers log only the first two errors. After the first two errors have been
logged, the MEA/MEL registers will not be updated. However, normal error detection still
continues, the ERR[1:0]# and BERR# signals are still asserted as appropriate, and scrubbing
of the memory still continues.
9.1.4
9.1.5
Memory Scrubbing
The Intel 450NX PCIset provides a “scrub-on-error” (demand scrubbing) mechanism, wherein
corrected data for single-bit errors will be automatically written back into the memory
subsystem by the MIOC. Note that this is not the same as “walk-through” scrubbing, in
which every memory location is systematically accessed, checked and corrected on a regular
basis. The scrub-on-error mechanism will scrub only those locations accessed during normal
operation and thus complements the software controlled “walk-through” scrubbing.
Debug/Diagnostic Support
The MIOC supports in-system testing of ECC functions. An ECC Mask Register (ECCMSK)
can be programmed with a masking function. Subsequent writes into memory will store a
masked version of the computed ECC. Subsequent reads of the memory locations written
while masked will return an invalid ECC code. If the mask register is left at 0h (the default),
the normal computed ECC is written to memory.
9.2 System Bus Integrity
A variety of system bus error detection features are provided by the MIOC. Particularly, the
system data bus is checked for ECC errors on Host-DRAM and Host-PCI writes.
9-2
Intel® 450NX PCIset
9.3 PCI Integrity
Additionally, the MIOC supports parity checking on the system address and
request/response signals.
9.2.1
System Bus Control & Data Integrity
The MIOC detects errors on the system data bus by checking the ECC provided with data and
the parity flag provided with control signals. In turn, the MIOC will generate new ECC with
data and parity with control signals so that bus errors can be detected by receiving clients.
The request control signals ADS# and REQ#[4:0] are covered with the Request Parity signal
RP#, which is computed as even parity. This ensures that it is deasserted when all covered
signals are deasserted.
The address signals A#[35:3] are covered by the Address Parity signal AP#[1:0], which is also
configured for even parity. This ensures that each is deasserted when all covered signals are
deasserted. AP#[1] covers A#[35:24] and AP#[0] covers A#[23:3].
Response signals RS#[2:0] are protected by RSP#. RSP# is computed as even parity. This
ensures that it is deasserted when all covered signals are deasserted.
9.3 PCI Integrity
The PCI bus provides a single even-parity bit (PAR) that covers the AD[31:0] and C/BE#[3:0]
lines. The agent that drives the AD[31:0] lines is responsible for driving PAR. Any undefined
signals must still be driven to a valid logic level and included in the parity calculation.
Parity generation is not optional on the PCI bus; however, parity error detection and reporting
is optional. The PXB will always detect an address parity error, even if it is not the selected
target. The PXB will detect data parity errors if it is either the master or the target of a
transaction, and will optionally report them to the system.
Address parity errors are reported using the SERR# signal. Data parity errors are reported
using the PERR# signal. The ERRCMD (Error Command) register provides the capability to
configure the PXB to propagate PERR# signaled error conditions onto the SERR# signal.
9.4 Expander Bus
Each Expander bus has a parity bit covering all data and control signals for each clock cycle.
Parity is generated at the expander bus interface by the sender, and checked at the expander
bus interface in the receiver. Detected parity errors are reported at the receiving component
— outbound packets report parity errors in the PXB, while inbound packets report parity
errors in the MIOC.
Intel® 450NX PCIset
9-3
9. Data Integrity & Error Handling
9-4
Intel® 450NX PCIset
System Initialization
10
10.1 Post Reset Initialization
10.1.1 Reset Configuration Using CVDR/CVCR
All system bus devices must sample the following configuration options at reset:
•
•
•
•
•
•
•
•
•
Address/request/response parity checking: Enabled or Disabled
AERR# detection enable
BERR# detection enable
BINIT# detection enable
FRC mode: Enabled or Disabled
Power-on reset vector: 1M or 4G
In-Order Queue depth: 1 or 8
APIC cluster ID: 0, 1, 2, or 3
Symmetric agent arbitration ID: 0, 1, 2, 3
The MIOC provides both the Symmetric Arbitration ID parameter and other parameters.
(Refer to the CVDR register description.)
10.1.1.1
Configuration Protocol
®
A Pentium II Xeon™ processor-based system is initialized and configured in the following
manner.
®
1. The system is powered. The power-supply provides resets for the Intel 450NX PCIset
through the PWRGD signal. The MIOC and PXBs assert their resets while the PWRGD
signal is not asserted. PCI reset is driven to tristate the PCI buses in order to prevent PCI
output buffers from short circuiting when the PCI power rails are not within the specified
tolerances.
2. All Intel 450NX PCIset components are initialized, with their internal registers defaulting
to the power-on values.
3. The MIOC will drive the appropriate system bus data lines with the initial configuration
values that defaulted in the Configuration Values Driven on Reset (CVDR) register.
4. On the rising edge of RESET#, the MIOC will continue driving the appropriate system
bus lines with the configuration values. These values are driven at least one clock after the
rising edge of RESET#.
Intel® 450NX PCIset
10-1
10. System Initialization
5. All system bus devices will capture the system configuration parameters from the
appropriate system bus lines on the rising edge of RESET#. The MIOC captures these
values in its Configuration Values Captured on Reset (CVCR) register. (This allows an
external device to over-ride the MIOC default parameters.)
6. All system bus devices are now ready for further programming. The MIOC will respond
to BIOS code fetches.
7. If a change in the system bus system configuration is desired, the MIOC’s CVDR register
can be programmed with the desired values.
8. After the CVDR register is programmed, the MIOC must be programmed to do a hard
reset, through the Reset Control (RC) register.
9. When the MIOC performs a hard reset, all system bus devices are again reset. This reset
repeats steps 2-8, except that the CVDR register is not effected by the reset. This register is
only re-initialized by the PWRGD signal.
10.1.1.2
Special Considerations for Third-Party Agents
One of the settings available in the CVDR/CVCR registers allows the Bus In-Order Queue
Depth to be set to 1, instead of the usual 8. When IOQ Depth=1, there is a case where a Third-
Party Agent can starve the system bus.
Therefore, any system containing a TPA must either:
•
require that the TPA back-off its BPRI# arbitration requests sufficiently to allow the
symmetric agents access to the bus, or
•
not use IOQ depth=1.
10-2
Intel® 450NX PCIset
Clocking and Reset
11
This chapter describes the generation, distribution and interaction between the various clocks
®
in an Intel 450NX PCIset-based system, as well as the various reset functionality supported
by the Intel 450NX PCIset.
11.1 Clocking
®
The Pentium II Xeon™ processor uses a clock ratio scheme where the system bus clock
frequency is multiplied to produce the processor’s core frequency. The MIOC supports a
®
system bus frequency optimized for 100 MHz. The Intel 450NX PCIset should be used at a
bus frequency which provides the required clock frequency for the PCI interfaces. The
external clock generator is responsible for generating the system clock. The Intel 450NX
PCIset’s core clock is equal to the system bus clock rate. The Intel 450NX PCIset is responsible
for driving the signals which the processor uses to determine the core to bus clock ratio.
The MIOC receives an output of a clock generator on the HCLKIN pin, as illustrated in Figure
11-1. The MIOC uses the HCLKIN signal to drive the host and memory interfaces and the core.
This clock is doubled for the MD bus and the Expander buses.
External Low Skew
Clock Driver
System Bus CLK
Y1
Y2
Y3
Yn
HCLKIN
MIOC
Figure 11-1: Host Clock Generation and Distribution
PCI clock distribution is illustrated in Figure 11-2. The PXB provides a PCI bus clock that is
generated by dividing the internal host clock frequency by three. The PCI clock is output
through the PCLK pin. Externally this PCI clock drives a low skew clock driver which in turn
supplies multiple copies of the PCI clock to the PCI bus. One of the outputs of the external
clock driver is fed back into the PXB. A PLL in the PXB forces the external PCI clock to phase
lock to the internal PCI clock tree.
Intel® 450NX PCIset
11-1
11. Clocking and Reset
VCC
Pull-up/Pull-down
Detect
External Low Skew
Clock Driver
PCLK
Host CLK/ 3
A
Y1
Y2
Y3
Yn
PCLKFB
PXB
Figure 11-2:
PCI Clock Generation and Distribution
11.2 System Reset
®
Five varieties of reset functions are supported by the Intel 450NX PCIset.
–
A Power-Good Reset is triggered by an externally generated signal which indicates that
the power supplies and clocks are stable. This reset clears all configuration and
transaction state in the Intel 450NX PCIset, as well as asserting resets to the
processors, PCI buses, and PIIX, if present.
–
A System Hard Reset is a software-initiated reset that performs nearly the same
functions as the power-good reset. The key difference is that the system hard reset
does not clear "sticky" error flags in the Intel 450NX PCIset, thus allowing an error
handler to determine the cause of a failure that resulted in reset. Also, hard reset may
optionally trigger the processor’s Built-In Self-Test (BIST).
–
–
–
A Soft Reset is another software-initiated reset which affects only the processors. This
reset may also be generated by certain I/O activities.
A BINIT Reset results from a catastrophic transaction error on the system bus. The
memory and the MIOC’s configuration space are untouched.
A PXB Reset is a software-initiated reset that affects only a single PXB and its
dependent PCI buses. This reset may be used in high-availability systems, where it is
desirable to allow the processors and one PXB to continue operation in the event of
failure of a single PXB.
11.2.1 Intel® 450NX PCIset Reset Structure
Figure 11-3 shows the recommended reset structure for an Intel 450NX PCIset-based system
including the PIIX4E south bridge. Note that the primary system power-good signal is
provided to the MIOC, which then distributes a variety of reset signals to the rest of the
system.
11-2
Intel® 450NX PCIset
11.2 System Reset
Processor
Processor
82C42
...
A20M#, INTR,
NMI#, IGNE#
A20M#,IGNE#,
INTR,NMI#
frequency
select
logic
System
Bus
CRESET#
RESET#
BINIT#
Power
Good
PWRGD
MRESET#
PWRGDB
MIOC
RCG Mux
RCG Mux
Memory
Card #0
Memory
Card #1
PIIXOK#
PIIXOK#
CPURST
PWRGD
PXB #1
PXB #0
®
Figure 11-3: Recommended RESET Distribution for Intel 450NX
PCIset-Based Systems Including a PIIX4E South Bridge
Power Good
The reference system shown here assumes a single "power good" signal that indicates clean
power supplies and clocks to the MIOC and both PXBs. For routing convenience and drive
capability, the MIOC provides a buffered version of its PWRGD input (PWRGDB), which
should be connected to the PWRGD inputs of each PXB. Refer to the Electrical Characteristics
for additional PWRGD requirements.
RESET#
The RESET# signal is directed to the processors. Assertion of this signal puts all processors in
a known state, and invalidates their L1 and L2 caches. When this signal is deasserted, the
processor begins to execute from address 00_FFFF_FFF0h. The Boot ROM must respond to
this address range regardless of where it physically resides in the system.
CRESET#
The CRESET# signal tracks RESET#, but is held asserted two clocks longer than RESET#. It
is provided to allow an external frequency selection mux to drive the system-bus-to-core-clock
ratio onto pins LINT[1:0], IGNNE#, and A20M# of the system bus during RESET#.
Intel® 450NX PCIset
11-3
11. Clocking and Reset
MRESET#
The MRESET# signal is sent to all RCGs and MUXs in the memory subsystem. When
asserted, each RCG and MUX clears their transaction state and data buffers. Any transactions
that may have been in-progress or pending in the memory subsystem are lost. Upon
MRESET# deassertion, the MIOC will re-initialize the memory subsystem by issuing 8 CAS-
before-RAS refreshes per bank (this does not affect the data held in the memory).
Bus CLK
2ms req’d
PWRGD
1ms
Core & Exp.
Clocks
2ms
Internal
Reset#
MRESET#
RESET#
CRESET#
2 Hclk
2ms
tristate
BNR#
X(0,1)RST#
Expander Buses
Core Clock
held in reset
ready
resynch
1ms
PCI CLK
relock (1ms)
PWRGDB
1ms
Internal
Reset#
P(A,B)RST#
= PIIX4E PWROK
1ms req’d
RSTDRV
1ms
CPURST
= PXB PIIXOK#
2ms
Figure 11-4: Power-Good Reset
11-4
Intel® 450NX PCIset
11.2 System Reset
Soft Reset
A Soft Reset is a reset directed to the processors on the system bus which does not affect the
configuration or transaction state of the Intel 450NX PCIset or the dependent PCI buses. To
support this function, the system design must externally combine the MIOC’s INIT# output
with the I/O port 92h and keyboard controller soft reset sources as shown in Figure 11-5.
Vcc
KBC RESET#
I/O Port 92 Reset
INIT# (to processors)
MIOC INIT#
74F07
Figure 11-5: Soft Reset
PXB Reset
A PXB Reset is a software-initiated reset that affects only a single PXB and its dependent PCI
buses. Figure 11-4 illustrates a software-initiated PXB Reset.
Reset Without Disturbing PCI Clocks
PCICLKA and PCICLKB must be re-phased whenever any type of reset is asserted if the Intel
450NX PCIset is to be deterministic relative to that reset. The behavior of these clocks cannot
be guaranteed during this re-phasing. A bit in the PXB RC register can be cleared by a
configuration write to defeat the PCI clock re-phasing, so that PCICLKA and PCICLKB remain
well behaved through resets.
11.2.2 Output States During Reset
The following tables shows the signal states of the Intel 450NX PCIset components during a
Power-Good Reset or System Hard Reset. Inputs are denoted by “-”.
Intel® 450NX PCIset
11-5
11. Clocking and Reset
CF8/CFC Write to RC to
assert System Hard Reset
CF8/CFC Write to RC to
deassert System Hard Reset
ADS#
BNR#
➋
2ms
2ms
X(0,1)RST#
67 Hclk
resynch
Expander Buses
PCI CLK
held in reset
ready
relock (1ms)
64 Hclk
Internal
Reset#
P(A,B)RST#
= PIIX4E PWROK
RSTDRV
1ms
CPURST
= PXB PIIXOK#
2ms
Figure 11-6: Software-Initiated PXB Reset
11.2.2.1
MIOC Reset State
Host Interface
A[35:3]#
ADS#
1
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
DEP[7:0]#
DRDY#
HIT#
Tristate
Tristate
-
AERR#
AP[1:0]#
BERR#
HITM#
INIT#
-
3
Tristate
-
Tristate
Tristate
Tristate
Tristate
BINIT#
LOCK#
REQ[4:0]#
RP#
BNR#
BP[1:0]#
BPRI#
RS[2:0]#
RSP#
2
BREQ[0]#
D[63:0]#
DBSY#
Asserted
Tristate
Tristate
Tristate
TRDY#
Tristate
DEFER#
11-6
Intel® 450NX PCIset
11.2 System Reset
Third-Party Agent Interface
IOGNT#
-
TPCTL[1:0]
-
IOREQ#
Tristate
Memory Subsystem / External Interface
BANK[2:0]#
CARD[1:0]#
CMND[1:0]#
CSTB#
Deasserted DVALID(a,b)#
Deasserted MA[13:0]#
Deasserted MD[71:0]#
Deasserted MRESET#
Deasserted
Deasserted
Tristate
Asserted
DCMPLT(a,b)#
DOFF[1:0]#
DSEL[1:0]#
DSTBN[3:0]#
DSTBP[3:0]#
Tristate
PHIT(a,b)#
-
Deasserted ROW#
Deasserted RCMPLT(a,b)#
Deasserted
-
-
Tristate
Tristate
RHIT(a,b)#
WDEVT#
Deasserted
Expander Interface (two per MIOC: 0,1)
X(0,1)ADS#
X(0,1)BE[1:0]#
X(0,1)BLK#
X(0,1)CLK
Tristate
Tristate
X(0,1)HSTBP#
X(0,1)PAR#
Toggling
Tristate
Asserted
Asserted
-
-
-
-
Deasserted X(0,1)RST#
Toggling
Toggling
-
Tristate
Toggling
Toggling
X(0,1)RSTB#
X(0,1)RSTFB#
X(0,1)XRTS#
X(0,1)XSTBN#
X(0,1)XSTBP#
X(0,1)CLKB
X(0,1)CLKFB
X(0,1)D[15:0]#
X(0,1)HRTS#
X(0,1)HSTBN#
Common Support Signals
CRES[1:0]
Strapped
TMS
-
TCK
-
TRST#
VCCA (3)
VREF (6)
-
TDI
-
Reference
Reference
TDO
OD
Component-Specific Support Signals
4
CRESET#
ERR[1:0]#
HCLKIN
Asserted
Tristate
PWRGD
PWRGDB
RESET#
-
4
De/asserted
Asserted
Toggling
INTREQ#
Deasserted SMIACT#
Deasserted
Notes:
1.
The Pentium® II Xeon™ processor allows for configuring a variety of processor and bus variables during the reset sequence.
During RESET# assertion, and for one clock past the trailing edge of RESET#, the Intel 450NX PCIset MIOC will drive the
contents of its CVDR register onto A[15:3]#. All system bus devices (including the MIOC) are required to sample these address
lines using the trailing edge of reset, and modify their internal configuration accordingly. Note the initial value of CVDR may be
changed by the boot processor, and the reset process re-engaged. This allows the processors and buses to power-up in a “safe”
state, yet allow re-configuration based on specific system constraints.
2.
3.
4.
BREQ0# must stay asserted (low) for a minimum of 2 system clocks after the rising edge of RESET#. The MIOC then releases
(tristates) the BREQ0# signal.
INIT# is not asserted during power-up. It may be optionally asserted during system hard reset through the RC register to cause
the processors to initiate BIST.
The PWRGDB output is asserted if the PWRGD input is asserted (i.e., a power-good reset). For a system hard reset, the
PWRGDB output is deasserted.
Intel® 450NX PCIset
11-7
11. Clocking and Reset
11.2.2.2
PXB Reset State
PCI Bus Interface (2 per PXB: A,B)
P(A,B)AD[31:0]
P(A,B)C/BE[3:0]#
P(A,B)CLKFB
P(A,B)CLK
Tristate
Tristate
-
P(A,B)PAR
Tristate
Tristate
- (see note)
Asserted
Open
P(A,B)PERR#
P(A,B)REQ[5:0]#
P(A,B)RST#
Toggling
Tristate
Tristate
Tristate
Tristate
Tristate
P(A,B)DEVSEL#
P(A,B)FRAME#
P(A,B)GNT[5:0]#
P(A,B)IRDY#
P(A,B)SERR#
P(A,B)STOP#
P(A,B)TRDY#
P(A,B)XARB#
Tristate
Tristate
Strapped
P(A,B)LOCK#
PCI Bus Interface / Non-Duplicated (one set per PXB)
ACK64#
Tristate
Strapped
-
PHLDA#
REQ64#
WSC#
Tristate
Asserted
Tristate
MODE64#
PHOLD#
Expander Interface (one per PXB)
XADS#
Tristate
XHSTBP#
XIB
-
XBE[1:0]#
Tristate
Deasserted
Tristate
XBLK#
-
XPAR#
XCLK
Toggling
Tristate
XRST#
Asserted
Deasserted
Deasserted
Deasserted
XD[15:0]#
XXRTS#
XXSTBN#
XXSTBP#
XHRTS#
-
-
XHSTBN#
Common Support Signals
CRES[1:0]
TCK
Strapped
TMS
-
-
TRST#
VCCA (3)
VREF (2)
-
TDI
-
Reference
Reference
TDO
OD
Component-Specific Support Signals
INTRQ(A,B)#
LONGXB#
Deasserted PIIXOK#
-
-
Strapped
Tristate
PWRGD
P(A,B)MON[1:0]#
Note:
The P(A,B)REQ[5:0]# signals are inputs to the PXB. During reset, these inputs are ignored. However,
these signals become "live" immediately following reset desassertion. All unconnected REQ# inputs
should be strapped deasserted. All connected REQ# inputs should have weak pullups.
11-8
Intel® 450NX PCIset
11.2 System Reset
11.2.2.3
RCG Reset State
Memory Subsystem / External Interface
BANK[2:0]#
CARD#
-
-
-
-
MRESET#
PHIT#
-
Deasserted
Deasserted
Deasserted
-
CMND[1:0]#
CSTB#
RCMPLT#
RHIT#
GRCMPLT#
MA[13:0]#
Deasserted ROW#
-
Memory Subsystem / Internal Interface
ADDR(A,B,C,D)[13:0]
LRD#
Deasserted
Deasserted
Deasserted
Deasserted
Deasserted
Deasserted
Deasserted
Deasserted
AVWP#
RAS(A,B,C,D)(a,b,c,d)[1:0]#
WDME#
CAS(A,B,C,D)(a,b,c,d)[1:0]#
LDSTB#
WE(A,B,C,D)(a,b)#
Common Support Signals
CRES[1:0]
TCK
-
TMS
-
-
TRST#
VCCA
VREF (2)
-
TDI
-
Reference
Reference
TDO
Tristate
Component-Specific Support Signals
BANKID#
DR50H#
DR50T#
HCLKIN
Strapped
Strapped
Strapped
Toggling
11.2.2.4
MUX Reset State
Memory Subsystem / External Interface
DCMPLT#
DOFF[1:0]#
DSEL#
Deasserted DVALID#
-
-
GDCMPLT#
MD[35:0]#
MRESET#
WDEVT#
Deasserted
-
Tristate
DSTBP[1:0]#
DSTBN[1:0]#
Tristate
Tristate
-
-
Memory Subsystem / Internal Interface
AVWP#
Q1D[35:0]
Q2D[35:0]
Q3D[35:0]
WDME#
Tristate
Tristate
Tristate
-
-
-
-
LDSTB#
LRD#
Q0D[35:0]
Tristate
Common Support Signals
CRES[1:0]
TCK
Strapped
TMS
-
-
TRST#
VCCA
VREF (2)
-
TDI
-
Reference
Reference
TDO
Tristate
Component-Specific Support Signals
HCLKIN
Toggling
Intel® 450NX PCIset
11-9
11. Clocking and Reset
11-10
Intel® 450NX PCIset
Electrical Characteristics
12
12.1 Signal Specifications
12.1.1 Unused Pins
For reliable operation, always connect unused inputs to an appropriate signal level. Unused
AGTL+ inputs should be connected to V . Unused active low 3.3 V-tolerant inputs should be
TT
connected to 3.3 V. Unused active high inputs should be connected to ground (V ). When
SS
tying bidirectional signals to power or ground, a resistor must be used. When tying any signal
to power or ground, a resistor will also allow for fully testing the processor and PCIset after
board assembly. It is suggested that ~10KΩ resistors be used for pull-ups and ~1KΩ resistors
be used as pull-downs.
12.1.2 Signal Groups
In order to simplify the following discussion, signals have been combined into groups of like
characteristics (see below). Refer to Chapter 2 for a description of the signals and their
functions.
Table 12-1: Signal Groups MIOC
Pin Group
Signals
Notes
AGTL+ Input
LOCK#, PHIT(a,b)#, RCMPLT(a,b)#, RHIT(a,b)#,
X(0,1)RSTFB#, X(0,1)XRTS#, X(0,1)XSTBN#,
X(0,1)XSTBP#, HIT#, HITM#
AGTL+ Output
AGTL+ I/O
BR[0]#, BANK[2:0]#, BREQ[0]#, CARD[1:0]#,
CMND[1:0]#, CSTB#, DOFF[1:0]#, DSEL[1:0]#,
DVALID(a,b)#, MA[13:0]#, MRESET#, ROW#,
X(0,1)BLK#, X(0,1)HRTS#, X(0,1)HSTBN#,
X(0,1)HSTBP#, X(0,1)RST#, X(0,1)RSTB#, WDEVT#
A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#,
BNR#, BPRI#, D[63:0]#, DBSY#, DCMPLT(a,b)#, DE-
FER#, DEP[7:0]#, DRDY#, DSTBN[3:0]#, DST-
BP[3:0]#, MD[71:0]#, REQ[4:0]#, RESET#, RP#,
RS[2:0]#, RSP#, TRDY#, X(0,1)ADS#, X(0,1)BE[1:0]#,
X(0,1)D[15:0]#, X(0,1)PAR#
CMOS 14 mA 2.5 V Open Drain Output
(3.3 V Tolerant)
INIT#, TDO
CMOS Input 3.3 V
IOGNT#, TPCTL[1:0], PWRGD,
Intel® 450NX PCIset
12-1
12. Electrical Characteristics
Table 12-1: Signal Groups MIOC (Continued)
CMOS Input 2.5 V (3.3 V Tolerant)
HCLKIN, X(0,1)CLKFB, TMS, TDI, TCK, TRST#
BP[1:0]#, ERR[1:0]#
1
CMOS I/O 14mA 2.5 V Open Drain
Output (3.3 V Tolerant)
CMOS Output 10mA 3.3 V
CRESET#, INTREQ#, IOREQ#, SMIACT#,
PWRGDB, X(0,1)CLK, X(0,1)CLKB
Analog signals
Note:
CRES[1:0], VCCA[2:0], VREF[5:0]
1. HCLKIN is equivalent to the Processor BCLK
Table 12-2: Signal Groups PXB
Pin Group
Signals
Notes
AGTL+ Input
AGTL+ Output
AGTL+ I/O
XBLK#, XHRTS#, XHSTBN#, XHSTBP#, XRST#
XIB, XXRTS#, XXSTBN#, XXSTBP#
XADS#, XBE[1:0], XD[15:0]#, XPAR#
CMOS Input 2.5 V (3.3 V Tolerant) XCLK, TMS, TDI, TCK, TRST#
CMOS Input 3.3 V
P(A,B)CLKFB, PIIXOK#, PWRGD
CMOS Output 10mA, 3.3 V
P(A,B)CLK
TDO
CMOS 14mA 2.5 V Open Drain
Output (3.3 V Tolerant)
CMOS I/O 14mA, 3.3 V
Open Drain Output
P(A,B)MON[1:0]#
Analog Signals
CRES[1:0], VCCA[2:0], VREF[1:0]
PCI Signals (Non-Duplicated)
ACK64#, MODE64#, PHOLD#, PHLDA#, REQ64#,
WSC#
PCI Signals
INTRQ(A,B)#, P(A,B)AD[31:0], P(A,B)C/BE#[3:0],
P(A,B)DEVSEL#, P(A,B)FRAME#, P(A,B)GNT[5:0]#,
P(A,B)IRDY#, P(A,B)LOCK#, P(A,B)PAR,
P(A,B)PERR#, P(A,B)REQ(5:0)#, P(A,B)RST#,
P(A,B)SERR#, P(A,B)STOP#, P(A,B)TRDY#,
P(A,B)XARB#
Table 12-3: Signal Groups MUX
Pin Group
Signals
Notes
AGTL+ Input
AVWP#, DOFF[1:0]#, DSEL#, DVALID#, LD-
STB#, LRD#, WDEVT#, WDME#, MRESET#
AGTL+ I/O
DCMPLT#, DSTBP[1:0]#, DSTBN[1:0]#, GDCM-
PLT#, MD[35:0]#
CMOS Input 2.5 V (3.3 V Tolerant)
HCLKIN, TMS, TDI, TCK, TRST#
TDO
CMOS 14mA, 2.5 V Open Drain
Output (3.3 V Tolerant)
CMOS I/O 10mA, 3.3 V
Analog Signals
Q0D[35:0], Q1D[35:0], Q2D[35:0], Q3D[35:0]
CRES[1:0], VCCA, VREF[1:0]
12-2
Intel® 450NX PCIset
12.1 Signal Specifications
Table 12-4: Signal Groups RCG
Pin Group
Signals
Notes
AGTL+ Input
BANK[2:0]#, CARD#, CMND[1:0]#, CSTB#, MA[13:0]#,
MRESET#, ROW#
AGTL+ Output
AVWP#, LDSTB#, LRD#, PHIT#, RCMPLT#, RHIT#,
WDME#
AGTL+ I/O
GRCMPLT#
CMOS Input 3.3 V
BANKID#, DR50H#, DR50T#
CMOS Input 2.5 V (3.3 V Tolerant) HCLKIN, TMS, TDI, TCK, TRST#
CMOS 14mA, 2.5 V Open Drain
Output (3.3 V Tolerant)
TDO
CMOS Output 10mA, 3.3 V
ADDR(A,B,C,D)[13:0]#, WE(A,B,C,D)(a,b)#,
CAS(A,B,C,D)(a,b,c,d)[1:0]#,
RAS(A,B,C,D)(a,b,c,d)[1:0]#
Analog Signals
CRES[1:0], VCCA, VREF[1:0]
12.1.3 The Power Good Signal: PWRGD
PWRGD is a 3.3 V-tolerant input to the PCI Bridge and memory controller components. It is
expected that this signal will be a clean indication that the clocks and the 3.3 V, VCC_PCI
supplies are within their specifications. ‘Clean’ implies that PWRGD will remain low, (capable
of sinking leakage current) without glitches, from the time that the power supplies are turned
on until they become valid. The signal will then have a single low to high transition to a high
(3. V) state with a minimum of 100ns slew rate. Figure 12-1 illustrates the relationship of
PWRGD to HCLKIN and system reset signals.
Intel® 450NX PCIset
12-3
12. Electrical Characteristics
3.3V
VCC_PCI
HCLKIN
P W R G D
<=100ns
RESET#
CRESET#
Figure 12-1: PWRGD Relationship
®
®
The PWRGD inputs to the Intel 450NX PCIset and to the Pentium II Xeon™ processor(s)
should be driven with an “AND” of ‘Power-Good’ signals from the 5 V, 3.3 V and V
CCcoreP
supplies. The output of this logic should be a 3.3 V level and should have a pull-down resistor
at the output to cover the period when this logic is not receiving power.
12-4
Intel® 450NX PCIset
12.1 Signal Specifications
12.1.4 LDSTB# Usage
xxQData
LDSTB#
Latch
D
Q
EN
Enabled
DFlop
To Core
DFlop
D
D
Q
LRD#
HCLKIN
Q
EN
Figure 12-2: LDSTB# Usage
LDSTB# opens a flow-through latch to enable fine tuning of the read data timing. By adjusting
the trace length of the LDSTB# signal it is possible to match the CAS# or RAS# timings
(whichever is last) for optimal timing margin on DRAM read cycles.
12.1.5 VCCA Pins
The VCCA inputs provide the analog supply voltage used by the internal PLLs. To ensure
PLL stability, a filter circuit must be used from the board VCC. Figure 12-3 shows a
recommended circuit. It is important to note that a separate filter for each VCCA pin is
necessary to avoid feeding noise from one analog circuit to another.
10 Ohm 1%
VCCA
VCC
10uF
Figure 12-3: VCCA filter
Intel® 450NX PCIset
12-5
12. Electrical Characteristics
12.2 Maximum Ratings
®
Table 12-5 contains stress ratings for the Intel 450NX PCIset. Functional operation at the
absolute maximum and minimum ratings is neither implied nor guaranteed. The Intel 450NX
PCIset should not receive a clock while subjected to these conditions. Functional operating
conditions are given in the AC and DC tables. Extended exposure to the maximum ratings
may affect device reliability. Furthermore, although the Intel 450NX PCIset contains
protective circuitry to resist damage from static discharge, care should always be taken to
avoid high static voltages or electric fields.
Table 12-5: Absolute Maximum Ratings
Symbol
Parameter
Min
Max
4.3
Unit
Notes
V
3.3 V Supply Voltage with respect to -0.5
V
CC3
V
SS
V
V
V
T
AGTL+ Buffer DC Input Voltage
with respect to V
-0.5
-0.5
V + 0.5
V
1
IN
tt
SS
(not to exceed 3.0)
3.3 V Tolerant DC Input Voltage
with respect to V
V
+ 0.9
CC3
V
2
3
IN3
IN5
SS
(not to exceed 4.3)
+ 0.5
5 V Tolerant DC Input Voltage with -0.5
respect to V
V
V
CC-PCI
SS
oC
Storage Temperature
-65
150
STOR
Notes:
1. Parameter applies to the AGTL+ signal groups only.
2. Parameter applies to 3.3 V-tolerant and JTAG signal groups only.
3. Parameter applies to 5 V-tolerant signal groups and PCI signals only. V
PCI Bus.
is the voltage level on the
CC-PCI
11nSec
(min)
Overvoltage Waveform
Voltage Source
Impedance
+ 11V
R
=
55 Ohms
11V, p-to-p
(minimum)
3.3V Supply
0V
4
nSec
4
nSec
(max)
(max)
Input
Buffer
62.5nSec
(16Mhz)
R
5.25V
V
10.75V, p-to-p
(minimum)
Undervoltage Waveform
Voltage Source
Impedance
-5.5V
R= 25 Ohms
Figure 12-4: Maximum AC Waveforms for 5 V Signaling (PCI Signals)
12-6
Intel® 450NX PCIset
12.3 DC Specifications
11nSec
(min)
Overvoltage Waveform
Voltage Source
Impedance
+7.1V
R
=
29 Ohms
7.1V, p-to-p
(minimum)
3.3V Supply
0V
4
nSec
4
nSec
(max)
(max)
Input
Buffer
62.5nSec
(16Mhz)
R
+3.6V
V
7.1V, p-to-p
(minimum)
Undervoltage Waveform
Voltage Source Impedance
R= 28 Ohms
-3.5V
Figure 12-5: Maximum AC Waveforms for 3.3 V Signaling (PCI Signals)
12.3 DC Specifications
®
Table 12-6 through Table 12-10 list the DC specifications associated with the Intel 450NX
PCIset. Care should be taken to read any notes associated with each parameter listed.
®
Table 12-6: Intel 450NX PCIset Power Parameters
Symbol
Parameter
Device V
Mi
n
Typ
Max
Unit
Notes
V
3.13
3.0
3.3
3.46
3.6
5.5
2
V
1
CC3
CC
V
V
(3.3)
(5)
PCI V for 3.3 V PCI Operation
3.3
5.0
V
2, 4
2, 4, 5
3
CC-PCI
CC-PCI
CC-PCI
CC
PCI V for 5.0 V PCI Operation
4.5
V
CC
I
Clamping Diode Leakage Current
Operating Case Temperature
mA
o
T
0
85
C
C
Notes:
1. 3.3 V +/-5%.
®
2. The Intel 450NX PCIset PXB will support either a 5 V or 3.3 V PCI Bus.
3. At 33 MHz.
4. From PCI Specification Rev 2.1.
5. Pin List VCC (A-N).
Intel® 450NX PCIset
12-7
12. Electrical Characteristics
®
Table 12-7: Intel 450NX PCIset Power Specifications
Symbol
Parameter
Max
7.8
Unit
Notes
P
Max Power Dissipation
PXB
MIOC
W
1, 2, 5
MAX
CC3
SS
13.2
3.3
W
W
W
A
1, 2, 5
1, 2, 5
1, 5
MUX
RCG
2.5
I
I
Max Power Supply Current PXB
2.2
1, 4
MIOC
3.3
A
A
A
A
1, 4
1, 4
1
MUX
RCG
0.87
0.7
Max Power Supply Current PXB
3.3
1, 3
MIOC
MUX
RCG
18.1
2.5
A
A
A
1, 3
1, 3
1, 3
0.8
Notes:
1. Frequency = 100 MHz.
2. This specification is a combination of core power (Icc ), and power dissipated in the AGTL+ outputs and
3
I/O.
3. Iss is the maximum supply current consumption when all AGTL+ signals are low.
4. The Icc Specification does not include the AGTL+ output current to GND.
Table 12-8 lists the nominal specifications for the AGTL+ termination voltage (V ) and the
TT
AGTL+ reference voltage (V ).
REF
Table 12-8: Intel® 450NX PCIset AGTL+ Bus DC Specifications
Symbol
Parameter
Min
Typ
Max
Uni
Notes
t
V
Bus Termination Voltage
1.5
V
1
TT
V
Input Reference Voltage 2/3 V -2% 2/3 V
2/3 V +2%
V
2, 3
REF
TT
TT
TT
Notes:
1. +/-9% during maximum di/dt and +/- 3% steady state, as measured at component V pins.
TT
2. Where VTT tolerance can range from - 9% to +9%, as noted above.
3.
V
should be created from V by a voltage divider of 1% resistors.
REF TT
Some of the signals on the MIOC, PXB, MUX and RCG are in the AGTL+ signal group. These
signals are specified to be terminated to 1.5V. The DC specifications for these signals are
shown in Table 12-9.
12-8
Intel® 450NX PCIset
12.3 DC Specifications
®
Table 12-9: Intel 450NX PCIset DC Specifications (AGTL+ Signal Groups)
o
Vcc = 3.3 V (5%, T
= 0 to 85 C)
3
CASE
Symbol
Parameter
Min
-0.3
Max
Unit
Notes
V
Input Low Voltage
V
-0.2
V
1
IL
REF
V
V
V
Input High Voltage
Output Low Voltage
Output High Voltage
Output High Current
Output Low Current
Input Leakage Current
Reference Voltage Current
Output Leakage Current
Input Capacitance
V
+0.2 2.185
REF
V
1
2
3
IH
0.6
--
V
OL
OH
1.2
2
V
I
I
I
I
I
20
55
mA
mA
uA
uA
uA
pF
pF
pF
OH
38
2
4
5
6
7
7
7
OL
LI
+/- 15
+/- 15
+/- 15
10
REF
LO
C
C
C
IN
O
Output Capacitance
I/O Capacitance
10
10
I/O
Notes:
®
1.
V
worst case. Noise on V
should be accounted for. Refer to the Pentium Pro Family Developer’s
REF
REF
Manual for more information on V
.
REF
2. Parameter measured into a 25 Ω resistor to V (1.5 V).
TT
3. A high level is maintained by the external pull-up resistors. AGTL+ is an open drain bus. Refer to the
®
Pentium Pro Family Developer’s Manual for information on V
TT.
4. (0 < V < Vcc )
IN
3
5. Total current for all V
pins.
REF
6. (0 < V
< Vcc )
OUT
3
7. Total of I/O buffer and package parasitics.
®
Table 12-10: Intel 450NX PCIset DC Specifications (Non AGTL+ Groups)
o
Vcc = 3.3 V (5%, T
= 0 to 85 C)
3
CASE
Notes/Test
Conditions
Symbol
Pin Group
All
Parameter
Min
Max
10
Unit
pF
C
C
C
C
C
Input Capacitance
Output Capacitance
I/O Capacitance
1
IN
All
10
10
10
8
pF
pF
pF
pF
mA
O
All
I/O
CLK
TCK
OL-14
HCLKIN
TCK
HCLKIN Input Capacitance
TCK Input Capacitance
I
CMOS 2.5 V Output Low Current
OD 14mA
14.0
10.0
I
CMOS 10mA Output Low Current
CMOS 10mA Output Low Voltage
mA
V
2
OL-10
V
0.45
OL
Intel® 450NX PCIset
12-9
12. Electrical Characteristics
®
Table 12-10: Intel 450NX PCIset DC Specifications (Non AGTL+ Groups) (Continued)
o
Vcc = 3.3 V (5%, T
= 0 to 85 C)
3
CASE
Notes/Test
Conditions
Symbol
Pin Group
Parameter
Min
Max
Unit
V
CMOS 2.5 V Output Low Voltage
OD 14mA
0.45
V
11
OL
V
V
CMOS 10mA Output High Voltage
2.4
V
9
OH
OH
CMOS 2.5 V Output High Voltage
OD 14mA
--
8, 11
I
I
CMOS 10mA Output Leakage Current
CMOS Input Input Leakage Current
CMOS Input Input Low Voltage
CMOS Input Input High Voltage
+/-10
+/-10
0.8
uA
uA
V
3
LO
LI
4, 5
V
V
V
-0.5
2.0
IL
IH
IL
3.6
V
CMOS 2.5 V Input Low Voltage
Input
-0.5
0.7
V
11
11
V
CMOS 2.5 V Input High Voltage
Input
1.7
3.6
V
IH
V
V
PCI
PCI
Input Low Voltage
Input High Voltage
- 0.5
2.0
0.8
V
V
6
IL-PCI
IH-PCI
V
6, 7
CC-PCI
+0.5
V
V
PCI
PCI
PCI
PCI
PCI
Output Low Voltage
Output High Voltage
Output Low Current
Input Leakage Current
Output Leakage Current
0.55
V
6
6
6
6
6
OL-PCI
OH-PCI
OL-PCI
LI-PCI
2.4
6.0
V
I
I
I
mA
uA
uA
+/-70
+/-10
LO-PCI
Notes:
1. Except HCLK, TCK
2.
V
= 0.4V
OL
3. (0 < V
< Vcc )
OUT
3
4. (0 < V < Vcc )
IN
3
5. -100uA for pins with 50K pullups, +100uA for pins with 50K pulldowns.
6. 5 V-tolerant 3.3V I/O buffer.
7.
V
= PCI Bus Voltage.
CC-PCI
8. Determined by 2.5 V connected through a 150 ohm resistor.
9. Measured with 10ma load.
10. Specifications for PCI are from PCI Specification Rev 2.1.
11. 3.3 V-tolerant 2.5 V Input or Output buffer.
12-10
Intel® 450NX PCIset
12.4 AC Specifications
12.4 AC Specifications
T3
T5 = CLK Rise Time
T3 = CLK High Time
T4 = CLK Low Time
T1 = CLK Period
T5
1.7V
1.25V
0.7V
T6
T4
T1
Figure 12-6: CLK Waveform
®
Table 12-11: Intel 450NX PCIset Clock Specifications
o
Vcc = 3.3 V (5%, T
= 0 to 85 C)
Min
3
CASE
Symbol
Parameter
Max
Unit
Notes
Host Interface:
Bus Frequency
CLK Period
90
10
100
MHz
ns
T1
11.11
1
T2
CLK Period Stability
CLK High Time
CLK Low Time
CLK Rise Time
CLK Fall Time
TCK Frequency
TCK Hightime
TCK Lowtime
TCK rise time
+/-100
ps
1
1
1
1
1
T3
3
ns
T4
3
ns
T5
0.5
0.5
1.5
ns
T6
1.5
ns
T9
16.67
MHz
ns
T72
T73
T74
T75
25
25
ns
5
5
ns
TCK fall time
ns
Note:
®
1. These specifications apply to all clock inputs for all four Intel 450NX PCIset components.
Intel® 450NX PCIset
12-11
12. Electrical Characteristics
®
Table 12-12: Intel 450NX PCIset MIOC AC Specifications
o
Vcc = 3. 3V (5%, T
= 0 to 85 C)
3
CASE
Setup
Min
Hold
Min
Delay
Min
Delay
Max
Symbol
Parameter
Unit
Notes
Host Interface:
T10A
A[35:3]#, ADS#,
AERR#, AP[1:0]#,
BERR#, BINIT#,
BNR#, BPRI#,
1.58
0.63
-0.15
2.65
ns
8
D[63:0]#, DBSY#,
DEFER#, DEP[7:0]#,
DRDY#, REQ[4:0]#,
RP#, RS[2:0]#, RSP#,
TRDY#
T17
BP[1:0]
BR0#
2.0
0.5
1.0
5.0
ns
ns
ns
10
8
T11
-0.15
2.65
T13A
HIT#, HITM#,
LOCK#
1.58
0.63
T12
INIT#
1.0
0.0
5.0
3.5
ns
9
3
Third-Party Agent
Interface:
T14
T15
T16
IOREQ#
ns
ns
ns
IOGNT#
TPCTL[1:0]
2.0
2.0
0.5
0.5
Memory
Interface:
T11
BANK[2:0]#,
CARD[1:0]#,
-0.15
2.65
ns
8
CMND[1:0]#,
CSTB#, DOFF[1:0],
DSEL[1:0]#,
DVALID(a,b)#,
MA[13:0]#, ROW#,
WDEVT#
T11
T10
T13
MRESET#
-0.15
-0.15
2.65
2.65
ns
ns
ns
7, 8
8
DCMPLT(a,b)#
1.88
1.88
0.63
0.63
PHIT(a,b)#, RCM-
PLT(a,b)#,
RHIT(a,b)#
MD(71:0)#, DST-
BP(3:0)#, DST-
BN(3:0)#
11
11
11
12-12
Intel® 450NX PCIset
12.4 AC Specifications
®
Table 12-12: Intel 450NX PCIset MIOC AC Specifications (Continued)
o
Vcc = 3. 3V (5%, T
= 0 to 85 C)
3
CASE
Setup
Min
Hold
Min
Delay
Min
Delay
Max
Symbol
Parameter
Unit
Notes
Expander Interface
(two per
MIOC:0,1)
T21
T23
T11
X(0,1)RST#,
X(0,1)RSTB#
-0.1
3.25
2.65
ns
7, 8
X(0,1)RSTFB#,
X(0,1)XRTS#
1.88
0.63
ns
ns
X(0,1)HRTS#
Other
-0.15
8
T39
T25
T70
CRESET#
ERR[1:0]#
1.0
1.0
0.0
4.1
5.0
3.5
ns
ns
ns
3
2.0
4.0
0.5
1.0
10
3
INTREQ#, SMI-
ACT#
T71
T70
T21
PWRGD
PWRGDB
RESET#
ns
ns
ns
1, 6
0.0
3.5
3, 5, 13
7, 8, 12
-0.1
3.25
Testability
Signals:
T26
T27
T27
T28
T29
TRST#
ns
ns
ns
ns
ns
4, 6
2
TMS
5.0
5.0
14.0
14.0
TDI
2
TDO
1.0
10.0
25.0
2, 3
2, 3
TDO on/off delay
Notes:
1. The power supply must wait until all voltages are stable for at least 1ms, and then assert the PWRGD
signal.
2. 3.3 V-tolerant signals. Inputs are referenced to TCK rising, outputs are referenced to TCK falling.
3. Min and Max timings are measured with 0pF load.
4. TRST# requires a pulse width of 40 ns.
5. This output is asynchronous.
6. This input is asynchronous.
7. Asynchronous assertion with synchronous deassertion.
8. Min and Max timings are measured with 0pf and 25 Ohms to Vtt.
9. Min and Max timings are measured with 0pf and 150 Ohms to 2.5 V.
10. Min and Max timings are measured with 0pf and 230 Ohm to 3.3 V.
11. See Table 12-16 for source synchronous timings.
12. Minimum pulse width 1.0ms.
13. PWRGDB is the buffered output of PWRGD, and has no relation to HCLKIN.
Intel® 450NX PCIset
12-13
12. Electrical Characteristics
®
Table 12-13: Intel 450NX PCIset PXB AC Specifications
o
Vcc = 3.3 V (5%, T
= 0 to 85 C)
3
CASE
Symbol
Parameter
Setup
Min
Hold
Min
Delay
Min
Delay
Max
Unit
Notes
PCI Interface
T30
P(A,B)AD[31:0],
7.0
0.0
2.0
11.0
ns
1, 3
P(A,B)C/BE[3:0]#,
P(A,B)TRDY#,
P(A,B)STOP#,
P(A,B)LOCK#,
P(A,B)DEVSEL#,
P(A,B)PAR,
P(A,B)IRDY#,
P(A,B)FRAME#,
P(A,B)PERR#,
P(A,B)XARB#
T31
T32
T34
P(A,B)REQ[5:0]#
P(A,B)GNT[5:0]#
12.0
0.0
ns
ns
ns
1, 3
1, 3
1, 3
2.0
2.0
12.0
11.0
INTRQ(A,B)#,
P(A,B)RST#,
P(A,B)SERR#,
T33
T35
T36
T37
T38
ACK64#
PHOLD#
PHLDA#
REQ64#
WSC#
7.0
7.0
0.0
0.0
2.0
11.0
ns
ns
ns
ns
ns
1, 3
1
2.0
2.0
2.0
12.0
11.0
12.0
1, 3
1, 3
1, 3
7.0
0.0
Expander Interface
(one per PXB)
T40
T11
T13
XRST#
2.8
0.0
ns
ns
ns
6
8
XXRTS#
-0.15
1.0
2.65
6.0
XHRTS#
1.88
0.63
OTHER
T47
T46
P(A,B)MON[1:0]#
PIIXOK#
4.0
7.0
0.5
0.0
ns
ns
4
1
Testability Signals:
T26
T27
T27
T28
T29
TRST#
ns
ns
ns
ns
ns
5, 7
2
TMS
5.0
5.0
14.0
14.0
TDI
2
TDO
1.0
10.0
25.0
2, 4
2, 4
TDO on/off delay
12-14
Intel® 450NX PCIset
12.4 AC Specifications
Notes:
1. 5 V-tolerant.
2. 3.3 V-tolerant signals. Inputs are referenced to TCK rising, outputs are referenced to TCK falling.
3. Min timings are measured with 0pF load, Max timings are measured with 50pF load.
4. Min and Max timings are measured with 0pF load.
5. TRST# requires a pulse width of 40 ns.
6. This signal has an asynchronous assertion and a synchronous deassertion.
7. This input is asynchronous.
PCI Bus Signal Waveforms: All PCI Bus signals are referenced to the PCLK Rising edge. For
more information on the PCI Bus signals and waveforms, please refer to the PCI Specification.
®
Table 12-14: Intel 450NX PCIset RCG AC Specifications
o
Vcc = 3.3 V (5%, T
= 0 to 85 C)
3
CASE
Symbol
Parameter
Setup
Hold
Min
Delay
Min
Delay
Max
Unit
Notes
Min
MemorySubsystem/External
Interface
T50
BANK[2:0]#, CARD#,
CMND[1:0]#, CSTB#,
MA[13:0]#, ROW#
2.80
2.80
0.0
ns
T51
T52
GRCMPLT#
0.0
-0.15
-0.15
2.65
2.65
ns
ns
6
PHIT#, RCMPLT#, RHIT#
6
Memory Subsystem/Internal
Interface
T52
AVWP#, LRD#, WDME#, LD-
STB#
-0.15
2.65
ns
6
T53
T54
T53
T53
CAS(A,B,C,D)(a,b,c,d)[1:0]#
0.0
1.0
0.0
0.0
3.5
5.5
3.5
3.5
ns
ns
ns
ns
3
3
3
3
ADDR(A,B,C,D)[13:0]#
RAS(A,B,C,D)(a,b,c,d)[1:0]#
WE(A,B,C,D)(a,b)#
Other
T50
T26
T27
T27
T28
T29
MRESET#
TRST#
2.8
0.0
ns
ns
ns
ns
ns
ns
5
4, 7
2
TMS
5.0
5.0
14.0
14.0
TDI
2
TDO
1.0
10.0
25.0
2, 3
2, 3
TDO on/off delay
Notes:
1. The power supply must wait until all voltages are stable for at least 1ms, and then assert the PWRGD
signal.
2. 3.3- tolerant signals. Inputs are referenced to TCK rising, outputs are referenced to TCK falling.
3. Min and Max timings are measured with 0pF load.
4. TRST# requires a pulse width of 40 ns.
5. Max delay timing requirement from MIOC to RCGs and MUXs is two clock cycles. Asynchronous
assertion and synchronous deassertion.
6. Min and Max timings are measured with 0pF and 25Ω to Vtt (1.5 V).
7. This input is asynchronous.
Intel® 450NX PCIset
12-15
12. Electrical Characteristics
®
Table 12-15: Intel 450NX PCIset MUX AC Specifications
o
Vcc = 3.3 V (5%, T
= 0 to 85 C)
3
CASE
Symbol
Parameter
Setup
Min
Hold
Min
Delay
Min
Delay
Max
Unit
Notes
Memory Subsystem/
External Interface
T60
T61
DCMPLT#
2.8
2.8
0.0
-0.15
-0.15
2.65
2.65
ns
6
DOFF[1:0]#, DSEL#,
DVALID#, WDEVT#
0.0
ns
8
T60
T67
GDCMPLT#
LDSTB#
2.8
3.0
0.0
1.0
ns
ns
6
Memory Subsystem/
Internal Interface
T62
T62
T68
AVWP#, WDME#
LRD#
3.5
3.5
1.0
0.0
0.0
4.0
ns
ns
ns
Q0D[35:0], Q1D[35:0],
Q2D[35:0], Q3D[35:0]
0.0
3.5
2, 4
5
Other
T69
MRESET#
Testability Signals:
TRST#
2.8
5.0
0.0
ns
T26
T27
T28
T29
ns
ns
ns
ns
3, 7
1
TMS, TDI
TDO
14.0
1.0
10.0
25.0
1, 2
1, 2
TDO on/off delay
Notes:
1. 3.3 V-tolerant signals. Inputs are referenced to TCK rising, outputs are referenced to TCK falling.
2. Min and Max timings are measured with 0pF load.
3. TRST# requires a pulse width of 40 ns.
4. Input timings are referenced from LDSTB# rising edge. Output timings are referenced from HCLKIN.
5. Max delay timing requirement from MIOC to RCGs and MUXs is two clock cycles. Asynchronous
assertion and synchronous deassertion.
6. Min and Max timings are measured with 0pF and 25Ω to Vtt (1.5 V).
7. This input is asynchronous.
8. DOFF[1:0]#, DSEL#, WDEVT# max delay timing requirement from MIOC to MUX is two clock cycles.
12-16
Intel® 450NX PCIset
12.4 AC Specifications
HCLKIN
T63
min
T63
max
T64
min
DSTBP#
X(0,1)HSTBP#
X(0,1)XSTBP#
T64
max
T65
min
T65
max
T66
min
T66
max
DSTBN#
X(0,1)HSTBN#
X(0,1)XSTBN#
Figure 12-7: Source Synchronous Strobe Timing
Table 12-16: 100 MHz Source Synchronous Timing
Symbol
Parameter
Delay
Min
Delay
Max
Skew
Unit
ns
Notes
T63
DSTBP(3:0)#, X(0,1)HSTBP#,
X(0,1)XSTBP#
Falling Edge
2.35
7.35
2.35
7.35
5.15
1, 2, 4
T64
T65
T66
DSTBP(3:0)#, X(0,1)HSTBP#,
X(0,1)XSTBP#
Rising Edge
10.15
5.15
ns
ns
ns
1, 3, 4
1, 2, 4
1, 3, 4
DSTBN(3:0)#, X(0,1)HSTBN#,
X(0,1)XSTBN#
Rising Edge
DSTBN(3:0)#, X(0,1)HSTBN#,
X(0,1)XSTBN#,
10.15
Falling Edge
Intel® 450NX PCIset
12-17
12. Electrical Characteristics
Notes:
1. Relative to HCLKIN Rising edge.
2. Strobe timings are generated from an internal clock which is a multiple of HCLKIN. This enables the
strobes to track system timings staying centered within the data window. Numbers given are for 100 MHz
operation. Timings for other frequencies can be calculated by Strobe_Min_Time = [-0.15 +
(1/Bus_Freq)1/ 4] ns and Strobe_Max_Time = [2.65 + (1/Bus_Freq)1 /4] ns.
3. Strobe timings are generated from an internal clock which is a multiple of HCLKIN. This enables the
strobes to track system timings staying centered within the data window. Numbers given are for 100 MHz
operation. Timings for other frequencies can be calculated by Strobe_Min_Time = [-0.15 +
(1/Bus_Freq)3/4] ns and Strobe_Max_Time = [2.65 + (1/Bus_Freq)3/4] ns.
4. Min and Max timings are measured with 0pF and 25Ω to Vtt (1.5 V).
Table 12-17: Source Synchronous Signal to Strobe Timings (at source)
Symbol
Parameter
Setup
Min
Setup
Max
Hold
Min
Hold
Max
Notes
1-5
T80
MD(71:0)#,
2.0
2.75
X(0,1)D[15:0]#,
X(0,1)ADS#,
X(0,1)BE[1:0]#,
X(0,1)BLK#,
X(0,1)PAR#
T81
MD(71:0)#,
2.0
2.75
1-5
X(0,1)D[15:0]#,
X(0,1)ADS#,
X(0,1)BE[1:0]#,
X(0,1)BLK#,
X(0,1)PAR#
Notes:
1. MD(71:0)# strobes are single-ended, and the falling edge of the strobe is used to capture data;
Expander strobes are differential.
2. Values are guaranteed by design.
3. Setup Max and Hold Max are specified at frequency= 100 MHz.
4. Timings for other frequencies can be calculated as follows: T80 Setup_Max = [(1/Bus_Freq)1/4 + .250]
ns, T81 Hold_Max = [(1/Bus_Freq)1/4 + .250 ] ns, where .250ns represents the error margin around
strobe placement.
5. Data delay times relative to HCLK for any bus frequency can be calculated as follows... For First Data:
Data_Min_Time = [-0.15 ]ns and Data_Max_Time = [2.65 ]ns; For Second Data: Data_Min_Time = [-0.15
+ (1/Bus Freq)/2 ]ns and Data_Max_Time = [2.65 + (1/Bus Freq)/2 ]ns.
12-18
Intel® 450NX PCIset
12.4 AC Specifications
DSTBx#
XHSTBx#
XXSTBx#
MD(71:0)#
XD(15:0)#
XBE[1:0]#
XPAR#
T80
T81
T81
XADS#
XBLK#
Figure 12-8: Source Synchronous Signal to Strobe Timings (at source)
Table 12-18: 100 MHz Source Synchronous Timing (at destination)
Symbol
Parameter
Setup
Min
Hold
Min
Unit
ns
Notes
1,4
T20
DSTBN(3:0)#,
DSTBP(3:0)#
X(0,1)XSTBN#
X(0,1)XSTBP#
7.0
T24
T22
MD(71:0)#
1.5
1.5
1.0
ns
ns
2
3
X(0,1)D[15:0]#,
X(0,1)ADS#,
X(0,1)BE[1:0]#,
X(0,1)BLK#,
1.75
X(0,1)D[15:0]#,
X(0,1)PAR#
Notes:
1. Setup in relation to “capture” HCLKIN.
2. With respect to the DSTBs.
3. With respect to the HSTBs.
4. Applies to Expander bus source synchronous signals. For synchronous signals (RTS#) the maximum
clock skew between MIOC and PXB plus the flight time must not exceed 4.97nS.
Intel® 450NX PCIset
12-19
12. Electrical Characteristics
1P Launched Here 1P Sampled Here
1P Capture Range
T20
H C L K
Data
1P
1N
2P
2N
3P
3N
O D D
E V E N
O D D
STRB
Figure 12-9: Source Synchronous Data Transfer
12.5 Source Synchronous Data Transfers
A Source Synchronous packet has a two clock period delivery time, and is divided into
positive and negative phases of even and odd cycles. During this two clock window, packets
are launched synchronously and sampled synchronously. Signals launched with a positive
phase “even” clock are sampled on a positive phase of next “even” clock. Between launch and
sample, signals are captured with source synchronous strobes.
HCLKIN
1.25V
Ts
Th
V
VALID
Ts =Setup Time
Th Hold Time
=
V
=1.0V for AGTL+
1.5V for 3.3V-tolerant CMOS
1.25V for 2.5V CMOS
Figure 12-10: Setup and Hold Timings
12-20
Intel® 450NX PCIset
12.6 I/O Signal Simulations: Ensuring I/O Timings
HCLKIN
TxMAX
TxMIN
V
Valid
Tx = Valid Delay
Figure 12-11: Valid Delay Timing
12.6 I/O Signal Simulations: Ensuring I/O Timings
®
It is highly recommended that system designers run extensive simulations on their Pentium
®
II Xeon™ processor/Intel 450NX PCIset-based designs. These simulations should include
the memory subsystem design as well. Please refer to the Pentium Pro Family Developer’s
®
Manual for more information.
12.7 Signal Quality Specifications
®
Signals driven by any component on the Pentium II Xeon™ processor bus must meet signal
quality specifications to guarantee that the components read data properly, and to ensure that
incoming signals do not affect the long term reliability of the components. There are three
signal quality parameters defined: Overshoot/Undershoot, Ringback, and Settling Limit,
which are discussed in the next sections.
12.7.1 Intel® 450NX PCIset Ringback Specification
This section discusses the ringback specification for the parameters in the AGTL+ signal
®
groups on the Intel 450NX PCIset.
Case A requires less time than Case B from the V
crossing until the ringback into the
REF
“overdrive” region. The longer time from V
crossing until the ringback into the
REF
“overdrive” region required in Case B allows the ringback to be closer to V
period.
for a defined
REF
Intel® 450NX PCIset
12-21
12. Electrical Characteristics
Table 12-19: Intel® 450NX PCIset AGTL+ Signal Groups Ringback Tolerance: Case A
Parameter
Min
100
Unit
mV
ns
Figure
12 & 13
12 & 13
Notes
1
α Overshoot
2.25
-100
1
1
τ
Minimum Time at High or Low
mV
12 & 13
ρ
Amplitude of Ringback
N/A
100
ns
12 & 13
12 & 13
1
1
δ Duration of Squarewave Ringback
mV
φ
Final Settling Voltage
Note:
®
1. Specified for an edge rate of 0.8-1.3 V/ns. See the Pentium Pro Family Developer’s Manual for the
definition of these terms. See Figure 12-12 and Figure 12-13 for the generic waveforms. All values are
determined by design/characterization.
®
Table 12-20: Intel 450NX PCIset AGTL+ Signal Groups Ringback Tolerance: Case B
Parameter
Min
100
Unit
mV
ns
Figure
12 & 13
12
Notes
1
α Overshoot
2.7
3.7
-0
1
1
1
τ
Minimum Time at High or Low
ns
13
τ
Minimum Time at Low
mV
12 & 13
ρ
Amplitude of Ringback
2
ns
12 & 13
12 & 13
1
1
δ Duration of Squarewave Ringback
Final Settling Voltage
100
mV
φ
Note:
®
1. Specified for an edge rate of 0.8-1.3 V/ns. See the Pentium Pro Family Developer’s Manual for the
definition of these terms. See the figures below for the generic waveforms. All values are determined by
design/characterization.
12-22
Intel® 450NX PCIset
12.7 Signal Quality Specifications
1.25V Clk Ref.
τ
10ps rise/fall edges
α
+0.2
REF
V
φ
V
REF
ρ
-0.2
V
REF
δ
Clock
Vstart
Tsu +0.05ns
TIME
Figure 12-12: Standard Input Lo-to-Hi Waveform for Characterizing Receiver Ringback Tolerance
Tsu +0.05ns
Vstart
1.25V Clk Ref.
δ
REF
V
+0.2
ρ
REF
V
φ
REF
V
-0.2
α
10ps rise/fall edges
Clock
τ
TIME
Figure 12-13: Standard Input Hi-to-Lo Waveform for Characterizing Receiver Ringback Tolerance
Intel® 450NX PCIset
12-23
12. Electrical Characteristics
12.7.2 Intel® 450NX PCIset Undershoot Specification
The undershoot specification for the Intel 450NX PCIset components (and Pentium II Xeon
processor) is as follows:
The Pentium II Xeon processor bus signals AERR#, BERR#, BINIT#, BNR#, HIT#, and HITM#
(only) are capable of sinking an 85mA current pulse at a 2.4% average time duty cycle. This is
equivalent to -1.7V applied to a 20Ω source in series with the device pin for 5.38 ns at
100 MHz with a utilization of 5%.
This test covers the AC operating conditions only
0.5ns (max)
+1.7 V
3.4V, p-to-p (max)
R
DUT
Voltage source
waveform
V
Undershoot Test Waveform
-1.7 V
Voltage Source Impedance
R = 20 ohms
7.5 ns (max)
Average duty cycle of 2.4%.
Figure 12-14: Undershoot Test Setup
12.7.3 Skew Requirements
The skew requirement for XpRST# versus XpRSTFB#, and XpCLK versus XpCLKFB is +/-
125ps.
The electrical length (delay) from the XpCLK# signal pin on the MIOC to the clock input of the
PXB must match the delay to the XpCLKFB# pin on the MIOC by that amount. The same is
true with XpRST# and XpRSTFB#.
12-24
Intel® 450NX PCIset
®
12.8 Intel 450NX PCIset Thermal Specifications
12.8 Intel® 450NX PCIset Thermal Specifications
12.8.1 Thermal Solution Performance
The system’s thermal solution must adequately control the package temperatures below the
maximum and above the minimum specified. The performance of any thermal solution is
defined as the thermal resistance between the package and the ambient air around the part
(package to ambient). The lower the thermal resistance between the package and the ambient
air, the more efficient the thermal solution is. The required θ package to ambient is dependent
upon the maximum allowed package temperature (T
), the local ambient temperature
Package
(TLA), and the package power (P
).
Package
Package to ambient = (T
– T )/P
LA Package
Package
TLA is a function of the system design. Table 12-21 and Table 12-22 provide the resulting
®
thermal solution performance required for an Intel 450NX PCIset at different ambient air
temperatures around the parts.
Table 12-21: Example Thermal Solution Performance for MIOC at Package Power of 13.2 Watts
Local Ambient Temperature (TLA)
35° C
40° C
45° C
°
θ Package to ambient C ⁄ (Watt)
3.79
3.41
3.03
Table 12-22: Example Thermal Solution Performance for PXB at Package Power of 7.8 Watts
Local Ambient Temperature (TLA)
35° C
40° C
45° C
θ Package to ambient °C ⁄ (Watt)
6.41
5.76
5.13
The θ package to ambient value is made up of two primary components: the thermal
resistance between the package and heatsink (θ package to heatsink) and the thermal
resistance between the heatsink and the ambient air around the part (θ heatsink to air). A
critical but controllable factor to decrease the value of θ package to heatsink is management of
the thermal interface between the package and heatsink. The other controllable factor
(θ heatsink to air) is determined by the design of the heatsink and airflow around the heatsink.
Intel® 450NX PCIset
12-25
12. Electrical Characteristics
12.9 Mechanical Specifications
12.9.1 Pin Lists Sorted by Pin Number:
Table 12-23: MIOC Pin List Sorted by Pin
Pin #
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
B01
GND
GND
GND
DBSY#
A07#
GND
A13#
VTT
Power
Power
Power
AGTL+
AGTL+
Power
AGTL+
Power
AGTL+
Power
Power
AGTL+
AGTL+
Power
AGTL+
Power
Analog
AGTL+
Power
AGTL+
AGTL+
Power
Power
AGTL+
Power
AGTL+
Power
AGTL+
AGTL+
Power
Power
Power
Power
I/O
I/O
55ma
55ma
I/O
I/O
55ma
55ma
A20#
GND
GND
A29#
A34#
GND
D01#
GND
CRES1
D12#
GND
D19#
D22#
GND
GND
D32#
VTT
I/O
I/O
55ma
55ma
55ma
I/O
I
I/O
I/O
I/O
55ma
55ma
I/O
I/O
55ma
55ma
D38#
GND
D46#
D49#
VCC
VCC
VCC
GND
I/O
I/O
55ma
55ma
12-26
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-23: MIOC Pin List Sorted by Pin (Continued)
Pin #
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
C01
C02
C03
C04
C05
C06
C07
GND
RS0#
A03#
GND
A10#
A14#
VTT
Power
I/O
I/O
AGTL+
AGTL+
Power
55ma
55ma
I/O
I/O
AGTL+
AGTL+
Power
55ma
55ma
A21#
A24#
A27#
A30#
A35#
DRDY#
D02#
D06#
D09#
D13#
D17#
D20#
D23#
D27#
D29#
D33#
VTT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
Power
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
D39#
D43#
GND
D50#
D54#
VCC
VCC
GND
BNR#
RS1#
A04#
A08#
A11#
A15#
I/O
I/O
AGTL+
AGTL+
Power
55ma
55ma
I/O
I/O
AGTL+
AGTL+
Power
55ma
55ma
Power
Power
I/O
I/O
I/O
I/O
I/O
I/O
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
55ma
55ma
55ma
55ma
55ma
55ma
Intel® 450NX PCIset
12-27
12. Electrical Characteristics
Table 12-23: MIOC Pin List Sorted by Pin (Continued)
Pin #
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
C08
C09
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
A18#
A22#
VCC
CRES0
A31#
VCC
VCC
D03#
VTT
I/O
I/O
AGTL+
AGTL+
Power
Analog
AGTL+
Power
Power
AGTL+
Power
Power
AGTL+
Power
Power
AGTL+
Power
55ma
55ma
I
I/O
55ma
55ma
55ma
55ma
I/O
I/O
I/O
VTT
D14#
VCC
VCC
D24#
VCC
N/C
D34#
D36#
D40#
D44#
D47#
D51#
D55#
D57#
VCC
BPRI#
TRDY#
VTT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
Power
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
I/O
I/O
AGTL+
AGTL+
Power
55ma
55ma
A05#
VTT
I/O
AGTL+
Power
55ma
A12#
A16#
GND
A23#
A25#
A28#
A32#
BERR#
I/O
I/O
AGTL+
AGTL+
Power
55ma
55ma
I/O
I/O
I/O
I/O
I/O
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
55ma
55ma
55ma
55ma
55ma
12-28
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-23: MIOC Pin List Sorted by Pin (Continued)
Pin #
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
E01
E02
E03
E04
E05
E06
E07
E08
E09
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
D00#
D04#
D07#
D10#
D15#
D18#
D21#
D25#
D28#
D30#
D35#
GND
D41#
D45#
VTT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
Power
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
I/O
I/O
AGTL+
AGTL+
Power
55ma
55ma
D52#
VTT
I/O
AGTL+
Power
55ma
D58#
D60#
REQ0#
RSP#
RS2#
A06#
A09#
VCC
A17#
A19#
GND
A26#
VTT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
Power
55ma
55ma
55ma
55ma
55ma
55ma
55ma
I/O
I/O
AGTL+
AGTL+
Power
55ma
55ma
I/O
I/O
AGTL+
Power
55ma
55ma
A33#
GND
GND
D05#
D08#
D11#
D16#
GND
AGTL+
Power
Power
I/O
I/O
I/O
I/O
AGTL+
AGTL+
AGTL+
AGTL+
Power
55ma
55ma
55ma
55ma
Intel® 450NX PCIset
12-29
12. Electrical Characteristics
Table 12-23: MIOC Pin List Sorted by Pin (Continued)
Pin #
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
E20
E21
E22
E23
E24
E25
E26
E27
E28
E29
E30
E31
E32
F01
F02
F03
F04
F05
F28
F29
F30
F31
F32
G01
G02
G03
G04
G05
G28
G29
G30
G31
G32
H01
H02
H03
H04
H05
GND
D26#
Power
I/O
I/O
AGTL+
Power
55ma
55ma
VTT
D31#
AGTL+
Power
GND
D37#
I/O
I/O
AGTL+
AGTL+
Power
55ma
55ma
D42#
VCC
D48#
I/O
I/O
I/O
I/O
I/O
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
Power
55ma
55ma
55ma
55ma
55ma
D53#
D56#
D59#
D61#
GND
REQ4#
LOCK#
REQ1#
VCC
I/O
I
AGTL+
AGTL+
AGTL+
Power
55ma
55ma
I/O
VCC
Power
D62#
I/O
I/O
I/O
AGTL+
AGTL+
AGTL+
Power
55ma
55ma
55ma
D63#
DEP7#
GND
GND
HIT#
Power
I
AGTL+
Power
VTT
REQ2#
DEFER#
DEP6#
DEP5#
VTT
I/O
I/O
I/O
I/O
AGTL+
AGTL+
AGTL+
AGTL+
Power
55ma
55ma
55ma
55ma
DEP4#
DEP3#
AP0#
HITM#
VTT
I/O
I/O
I/O
I
AGTL+
AGTL+
AGTL+
AGTL+
Power
55ma
55ma
55ma
REQ3#
GND
I/O
AGTL+
Power
55ma
12-30
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-23: MIOC Pin List Sorted by Pin (Continued)
Pin #
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
H28
H29
H30
H31
H32
J01
GND
Power
LVTTL
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
Power
LVTTL
AGTL+
OD
CRESET#
DEP2#
DEP1#
DEP0#
AP1#
O
10ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
I/O
I/O
I/O
I/O
O
J02
BR0#
J03
ADS#
RP#
I/O
I/O
J04
J05
GND
J28
X0CLKFB
BINIT#
BP0#
I
J29
I/O
I/O
I/O
55ma
14ma
14ma
J30
J31
BP1#
OD
J32
GND
Power
OD
K01
K02
K03
K04
K05
K28
K29
K30
K31
K32
L01
L02
L03
L04
L05
L28
L29
L30
L31
L32
M01
M02
M03
ERR0#
ERR1#
VCC
I/O
I/O
14ma
14ma
OD
Power
Analog
AGTL+
Power
VREF
I
AERR#
VCC
I/O
55ma
N/C
VCCA0
VCCA1
VCCA2
GND
Power
Power
Power
Power
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Power
LVTTL
Power
LVTTL
Power
OD
TRST#
TCK
I
I
INTREQ#
TMS
O
I
10ma
X0CLK
X0CLKB
VCC
O
O
10ma
10ma
PWRGD
GND
I
TPCTL0
VCC
I
TDO
O
14ma
Intel® 450NX PCIset
12-31
12. Electrical Characteristics
Table 12-23: MIOC Pin List Sorted by Pin (Continued)
Pin #
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
M04
M05
M28
M29
M30
M31
M32
N01
N02
N03
N04
N05
N28
N29
N30
N31
N32
P01
P02
P03
P04
P05
P28
P29
P30
P31
P32
R01
R02
R03
R04
R05
R28
R29
R30
R31
R32
T01
TDI
I
LVTTL
Power
Power
AGTL+
LVTTL
LVTTL
AGTL+
Power
LVTTL
Power
LVTTL
LVTTL
LVTTL
2.5V
GND
GND
RESET#
X1CLK
X1CLKB
X0RSTFB#
VCC
I/O
O
55ma
10ma
10ma
O
I
TPCTL1
VTT
I
IOREQ#
IOGNT#
X1CLKFB
INIT#
O
I
10ma
I
OD
O
I
14ma
55ma
X0RSTB#
VREF
AGTL+
Analog
Power
Power
AGTL+
AGTL+
AGTL+
Power
LVTTL
AGTL+
AGTL+
AGTL+
Power
Power
AGTL+
AGTL+
Power
Power
2.5V
VCC
VCC
MD00#
MD01#
MD02#
VCC
I/O
I/O
I/O
55ma
55ma
55ma
PWRGDB
X0RST#
X0BE1#
X0BE0#
VCC
O
10ma
55ma
55ma
55ma
O
I/O
I/O
GND
MD03#
MD04#
VCC
I/O
I/O
55ma
55ma
VCC
HCLKIN
GND
I
Power
AGTL+
AGTL+
AGTL+
AGTL+
X0ADS#
X0PAR#
X0BLK#
MD05#
I/O
I/O
O
55ma
55ma
55ma
55ma
I/O
12-32
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-23: MIOC Pin List Sorted by Pin (Continued)
Pin #
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
T02
MD06#
MD07#
MD08#
VCC
I/O
I/O
I/O
AGTL+
AGTL+
AGTL+
Power
55ma
55ma
55ma
T03
T04
T05
T28
GND
Power
T29
X0D03#
X0D02#
X0D01#
X0D00#
DSTBP0#
DSTBN0#
MD09#
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
Power
55ma
55ma
55ma
55ma
55ma
55ma
55ma
T30
T31
T32
U01
U02
U03
U04
U05
U28
U29
U30
U31
U32
V01
V02
V03
V04
V05
V28
V29
V30
V31
V32
W01
W02
W03
W04
W05
W28
W29
W30
W31
GND
Power
N/C
X0D04#
VREF
I/O
I
AGTL+
Analog
AGTL+
Power
55ma
55ma
X0D05#
GND
I/O
VCC
Power
MD10#
MD11#
GND
I/O
I/O
AGTL+
AGTL+
Power
55ma
55ma
GND
Power
VCC
Power
VCC
Power
X0XSTBN#
X0XSTBP#
GND
I
I
AGTL+
AGTL+
Power
MD12#
MD13#
MD14#
MD15#
GND
I/O
I/O
I/O
I/O
AGTL+
AGTL+
AGTL+
AGTL+
Power
55ma
55ma
55ma
55ma
VCC
Power
X0XRTS#
X0HRTS#
X0HSTBN#
I
AGTL+
AGTL+
AGTL+
O
O
55ma
55ma
Intel® 450NX PCIset
12-33
12. Electrical Characteristics
Table 12-23: MIOC Pin List Sorted by Pin (Continued)
Pin #
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
W32
X0HSTBP#
VCC
O
AGTL+
Power
55ma
Y01
Y02
MD16#
VTT
I/O
AGTL+
Power
55ma
Y03
Y04
MD17#
MD18#
GND
I/O
I/O
AGTL+
AGTL+
Power
55ma
55ma
Y05
Y28
Y29
X0D07#
VTT
I/O
I/O
AGTL+
Power
55ma
55ma
Y30
Y31
X0D06#
VCC
AGTL+
Power
Y32
AA01
AA02
AA03
AA04
AA05
AA28
AA29
AA30
AA31
AA32
AB01
AB02
AB03
AB04
AB05
AB28
AB29
AB30
AB31
AB32
AC01
AC02
AC03
AC04
AC05
AC28
AC29
MD19#
MD20#
MD21#
MD22#
GND
I/O
I/O
I/O
I/O
AGTL+
AGTL+
AGTL+
AGTL+
Power
55ma
55ma
55ma
55ma
GND
Power
X0D11#
X0D10#
X0D09#
X0D08#
GND
I/O
I/O
I/O
I/O
AGTL+
AGTL+
AGTL+
AGTL+
Power
55ma
55ma
55ma
55ma
MD23#
VCC
I/O
AGTL+
Power
55ma
MD24#
MD25#
X0D14#
X0D13#
VCC
I/O
I/O
I/O
I/O
AGTL+
AGTL+
AGTL+
AGTL+
Power
55ma
55ma
55ma
55ma
X0D12#
GND
I/O
AGTL+
Power
55ma
GND
Power
MD26#
VREF
I/O
I
AGTL+
Analog
AGTL+
Power
55ma
55ma
DSTBP1#
GND
I/O
GND
Power
X1RST#
O
AGTL+
55ma
12-34
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-23: MIOC Pin List Sorted by Pin (Continued)
Pin #
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
AC30
AC31
AC32
AD01
AD02
AD03
AD04
AD05
AD28
AD29
AD30
AD31
AD32
AE01
AE02
AE03
AE04
AE05
AE28
AE29
AE30
AE31
AE32
AF01
AF02
AF03
AF04
AF05
AF28
AF29
AF30
AF31
AF32
AG01
AG02
AG03
AG04
AG05
VCC
Power
X0D15#
VCC
I/O
AGTL+
Power
55ma
DSTBN1#
MD27#
MD28#
MD29#
GND
I/O
I/O
I/O
I/O
AGTL+
AGTL+
AGTL+
AGTL+
Power
55ma
55ma
55ma
55ma
GND
Power
X1BE1#
X1BE0#
X1RSTB#
X1ADS#
GND
I/O
I/O
O
AGTL+
AGTL+
AGTL+
AGTL+
Power
55ma
55ma
55ma
55ma
I/O
MD30#
VTT
I/O
AGTL+
Power
55ma
MD31#
MD32#
X1BLK#
X1D1#
VTT
I/O
I/O
O
AGTL+
AGTL+
AGTL+
AGTL+
Power
55ma
55ma
55ma
55ma
I/O
X1D00#
GND
I/O
I/O
AGTL+
Power
55ma
55ma
GND
Power
MD33#
VTT
AGTL+
Power
MD34#
MD35#
VCC
I/O
I/O
AGTL+
AGTL+
Power
55ma
55ma
X1D03#
VTT
I/O
I/O
AGTL+
Power
55ma
55ma
X1D02#
GND
AGTL+
Power
MD36#
MD37#
MD38#
MD39#
VCC
I/O
I/O
I/O
I/O
AGTL+
AGTL+
AGTL+
AGTL+
Power
55ma
55ma
55ma
55ma
Intel® 450NX PCIset
12-35
12. Electrical Characteristics
Table 12-23: MIOC Pin List Sorted by Pin (Continued)
Pin #
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
AG28
AG29
AG30
AG31
AG32
AH01
AH02
AH03
AH04
AH05
AH06
AH07
AH08
AH09
AH10
AH11
AH12
AH13
AH14
AH15
AH16
AH17
AH18
AH19
AH20
AH21
AH22
AH23
AH24
AH25
AH26
AH27
AH28
AH29
AH30
AH31
AH32
AJ01
VCC
Power
VREF
I
Analog
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
Power
X1D05#
X1D04#
X1RSTFB#
MD40#
MD41#
MD42#
MD43#
MD44#
VCC
I/O
I/O
I
55ma
55ma
I/O
I/O
I/O
I/O
I/O
55ma
55ma
55ma
55ma
55ma
MD57#
MD62#
DSTBN3#
VCC
I/O
I/O
I/O
AGTL+
AGTL+
AGTL+
Power
55ma
55ma
55ma
VCC
Power
DOFF0#
GND
O
AGTL+
Power
55ma
GND
Power
DCMPLTB#
ROW#
VCC
I/O
O
AGTL+
AGTL+
Power
55ma
55ma
BANK1#
GND
O
AGTL+
Power
55ma
GND
Power
MA07#
VTT
O
O
AGTL+
Power
55ma
55ma
MA12#
GND
AGTL+
Power
GND
Power
X1D14#
VCC
I/O
AGTL+
Power
55ma
X1HSTBN#
X1HSTBP#
X1XSTBN#
X1XSTBP#
GND
O
O
I
AGTL+
AGTL+
AGTL+
AGTL+
Power
55ma
55ma
I
DSTBP2#
I/O
AGTL+
55ma
12-36
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-23: MIOC Pin List Sorted by Pin (Continued)
Pin #
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
AJ02
AJ03
AJ04
AJ05
AJ06
AJ07
AJ08
AJ09
AJ10
AJ11
AJ12
AJ13
AJ14
AJ15
AJ16
AJ17
AJ18
AJ19
AJ20
AJ21
AJ22
AJ23
AJ24
AJ25
AJ26
AJ27
AJ28
AJ29
AJ30
AJ31
AJ32
AK01
AK02
AK03
AK04
AK05
AK06
AK07
DSTBN2#
VTT
I/O
AGTL+
Power
55ma
MD45#
VTT
I/O
AGTL+
Power
55ma
MD54#
MD58#
GND
I/O
I/O
AGTL+
AGTL+
Power
55ma
55ma
MD63#
MD67#
MD71#
CMND1#
DSEL0#
WDEVT#
RCMPLTB#
DCMPLTA#
BANK0#
CARD1#
GND
I/O
I/O
I/O
O
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
Power
55ma
55ma
55ma
55ma
55ma
55ma
O
O
I
I/O
O
55ma
55ma
55ma
O
MA02#
MA06#
MA09#
MA11#
GND
O
O
O
O
AGTL+
AGTL+
AGTL+
AGTL+
Power
55ma
55ma
55ma
55ma
GND
Power
GND
Power
X1D13#
VTT
I/O
I/O
AGTL+
Power
55ma
55ma
X1D06#
VTT
AGTL+
Power
X1XRTS#
X1HRTS#
VCC
I
AGTL+
AGTL+
Power
O
55ma
MD46#
MD47#
MD48#
MD49#
MD55#
MD59#
I/O
I/O
I/O
I/O
I/O
I/O
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
55ma
55ma
55ma
55ma
55ma
55ma
Intel® 450NX PCIset
12-37
12. Electrical Characteristics
Table 12-23: MIOC Pin List Sorted by Pin (Continued)
Pin #
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
AK08
AK09
AK10
AK11
AK12
AK13
AK14
AK15
AK16
AK17
AK18
AK19
AK20
AK21
AK22
AK23
AK24
AK25
AK26
AK27
AK28
AK29
AK30
AK31
AK32
AL01
AL02
AL03
AL04
AL05
AL06
AL07
AL08
AL09
AL10
AL11
AL12
AL13
DSTBP3#
MD64#
MD68#
VCC
I/O
I/O
I/O
AGTL+
AGTL+
AGTL+
Power
Power
AGTL+
Power
AGTL+
Power
Power
Power
Power
Power
AGTL+
Power
Power
Power
Power
AGTL+
Power
AGTL+
AGTL+
AGTL+
AGTL+
Power
Power
Power
AGTL+
AGTL+
Power
AGTL+
AGTL+
Power
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
55ma
55ma
55ma
VCC
PHITA#
VCC
I
DVALIDA#
VTT
O
55ma
VTT
VCC
VCC
VCC
MA5#
VCC
O
55ma
55ma
VCC
GND
GND
X1D15#
GND
I/O
X1D10#
X1D09#
X1D08#
X1D07#
GND
I/O
I/O
I/O
I/O
55ma
55ma
55ma
55ma
VCC
VCC
MD50#
MD51#
GND
I/O
I/O
55ma
55ma
MD56#
MD60#
VTT
I/O
I/O
55ma
55ma
MD65#
MD69#
CMND0#
RHITA#
MRESET#
I/O
I/O
O
55ma
55ma
55ma
I
O
55ma
12-38
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-23: MIOC Pin List Sorted by Pin (Continued)
Pin #
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
AL14
AL15
AL16
AL17
AL18
AL19
AL20
AL21
AL22
AL23
AL24
AL25
AL26
AL27
AL28
AL29
AL30
AL31
AL32
AM01
AM02
AM03
AM04
AM05
AM06
AM07
AM08
AM09
AM10
AM11
AM12
AM13
AM14
AM15
AM16
AM17
AM18
AM19
DSEL1#
VREF
O
AGTL+
Analog
AGTL+
AGTL+
AGTL+
LVTTL
AGTL+
AGTL+
AGTL+
AGTL+
Power
Power
Power
Power
Power
AGTL+
AGTL+
Power
Power
Power
Power
Power
AGTL+
AGTL+
Power
AGTL+
Power
AGTL+
AGTL+
Power
AGTL+
AGTL+
Power
AGTL+
Power
AGTL+
AGTL+
Power
55ma
I
DVALIDB#
PHITB#
CARD0#
SMIACT#
MA01#
MA04#
MA08#
MA10#
VCC
O
I
55ma
55ma
55ma
10ma
55ma
55ma
55ma
55ma
O
O
O
O
O
O
VTT
VTT
GND
GND
X1D12#
X1D11#
GND
I/O
I/O
55ma
55ma
GND
VCC
VCC
VCC
MD52#
MD53#
GND
I/O
I/O
55ma
55ma
MD61#
VTT
I/O
55ma
MD66#
MD70#
GND
I/O
I/O
55ma
55ma
CSTB#
DOFF1#
GND
O
O
55ma
55ma
RCMPLTA#
GND
I
RHITB#
BANK2#
GND
I
O
55ma
Intel® 450NX PCIset
12-39
12. Electrical Characteristics
Table 12-23: MIOC Pin List Sorted by Pin (Continued)
Pin #
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
AM20
AM21
AM22
AM23
AM24
AM25
AM26
AM27
AM28
AM29
AM30
AM31
AM32
MA00#
MA03#
GND
O
AGTL+
AGTL+
Power
Power
AGTL+
Power
Power
Power
Power
AGTL+
Power
Power
Power
55ma
55ma
O
GND
MA13#
VTT
O
55ma
55ma
VTT
GND
GND
X1PAR#
GND
I/O
GND
GND
Table 12-24: PXB Pinlist Sorted by Pin
PIN#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
N/C
N/C
VCC
Power
Power
Power
Power
Power
Power
Power
Power
VCC
VCC
VCC
VCC
VCC
VCC
VCC
N/C
VREF
N/C
I
Analog
VCC
Power
AGTL+
Power
AGTL+
Power
AGTL+
Power
AGTL+
Power
XD[10]#
VCC
I/O
55ma
55ma
XHSTBN#
VCC
I
XD[04]#
VCC
I/O
I
XBLK#
VCC
12-40
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-24: PXB Pinlist Sorted by Pin (Continued)
PIN#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
N/C
VREF
N/C
I
Analog
VCC
Power
Power
Power
Power
VCCA0
VCC
VCC
N/C
N/C
N/C
N/C
VCC
Power
Power
Power
VCC
VCC
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
XD[15]#
XD[11]#
XD[08]#
N/C
I/O
I/O
I/O
AGTL+
AGTL+
AGTL+
55ma
55ma
55ma
XHRTS#
XD[05]#
XD[02]#
XPAR#
XBE[01]#
N/C
I
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
I/O
I/O
I/O
I/O
55ma
55ma
55ma
55ma
N/C
N/C
N/C
N/C
VCC
Power
Intel® 450NX PCIset
12-41
12. Electrical Characteristics
Table 12-24: PXB Pinlist Sorted by Pin (Continued)
PIN#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
B29
B30
B31
B32
C01
C02
C03
C04
C05
C06
C07
C08
C09
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
D01
D02
VCC
Power
Power
Power
VCC
VCC
N/C
N/C
N/C
N/C
N/C
N/C
GND
GND
GND
N/C
Power
Power
Power
GND
N/C
Power
Power
GND
N/C
GND
XD[12]#
GND
XHSTBP#
GND
XXSTBN#
GND
XADS#
GND
N/C
Power
AGTL+
Power
AGTL+
Power
AGTL+
Power
AGTL+
Power
I/O
I
55ma
O
55ma
55ma
I/O
GND
XCLK
GND
VCCA1
N/C
Power
LVTTL
Power
Power
I
N/C
N/C
N/C
N/C
N/C
GND
Power
12-42
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-24: PXB Pinlist Sorted by Pin (Continued)
PIN#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
E01
E02
E03
E04
E05
E06
E07
E08
N/C
VTT
Power
N/C
N/C
N/C
N/C
CRES1
N/C
I
Analog
N/C
N/C
N/C
N/C
XD[13]#
XD[09]#
XD[06]#
XXRTS#
N/C
I/O
I/O
I/O
O
AGTL+
AGTL+
AGTL+
AGTL+
55ma
55ma
55ma
55ma
XD[03]#
XD[00]#
XRST#
N/C
I/O
I/O
I
AGTL+
AGTL+
AGTL+
55ma
55ma
N/C
N/C
N/C
VCC
Power
Power
LVTTL
VTT
PWRGD
N/C
I
GND
N/C
Power
N/C
N/C
N/C
N/C
N/C
VTT
Power
Power
N/C
VTT
Intel® 450NX PCIset
12-43
12. Electrical Characteristics
Table 12-24: PXB Pinlist Sorted by Pin (Continued)
PIN#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
E09
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
E27
E28
E29
E30
E31
E32
F01
F02
F03
F04
F05
F28
F29
F30
F31
F32
G01
G02
G03
G04
CRES0
VTT
I
Analog
Power
N/C
VTT
Power
AGTL+
Power
AGTL+
Power
AGTL+
Power
AGTL+
Power
AGTL+
Power
AGTL+
Power
XIB
O
55ma
55ma
55ma
55ma
55ma
55ma
VTT
XD[14]#
VTT
I/O
I/O
O
XD[07]#
VTT
XXSTBP#
VTT
XD[01]#
VTT
I/O
I/O
XBE[00]#
VTT
N/C
VTT
Power
Power
VCCA2
N/C
N/C
N/C
N/C
N/C
GND
N/C
Power
Power
VCC
N/C
GND
GND
PIIXOK#
N/C
Power
Power
LVTTL
I
N/C
N/C
N/C
N/C
N/C
N/C
12-44
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-24: PXB Pinlist Sorted by Pin (Continued)
PIN#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
G05
G28
G29
G30
G31
G32
H01
H02
H03
H04
H05
H28
H29
H30
H31
H32
J01
N/C
N/C
N/C
VCC
VCC
N/C
VCC
N/C
GND
N/C
VCC
N/C
N/C
GND
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
PBCLKFB
N/C
PACLKFB
GND
N/C
VCC
N/C
GND
GND
N/C
VCC
N/C
GND
GND
GND
Power
Power
Power
Power
Power
Power
J02
J03
J04
J05
J28
J29
J30
I
I
LVTTL
J31
J32
LVTTL
Power
K01
K02
K03
K04
K05
K28
K29
K30
K31
K32
L01
L02
Power
Power
Power
Power
Power
Power
Power
Intel® 450NX PCIset
12-45
12. Electrical Characteristics
Table 12-24: PXB Pinlist Sorted by Pin (Continued)
PIN#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
L03
L04
L05
L28
L29
L30
L31
L32
M01
M02
M03
M04
M05
M28
M29
M30
M31
M32
N01
N02
N03
N04
N05
N28
N29
N30
N31
N32
P01
P02
P03
P04
P05
P28
P29
P30
P31
P32
GND
GND
GND
N/C
N/C
PBCLK
N/C
PACLK
VCC
N/C
GND
TCK
Power
Power
Power
O
LVTTL
10ma
10ma
O
LVTTL
Power
Power
2.5V
I
VCC
VCC
N/C
GND
N/C
VCC
TDI
Power
Power
Power
Power
2.5V
I
TDO
VCC
TMS
TRST#
N/C
N/C
N/C
N/C
N/C
VCC
N/C
GND
N/C
VCC
GND
N/C
VCC
N/C
GND
O
OD
14ma
Power
2.5V
I
I
2.5V
Power
Power
Power
Power
Power
Power
12-46
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-24: PXB Pinlist Sorted by Pin (Continued)
PIN#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
R01
R02
R03
R04
R05
R28
R29
R30
R31
R32
T01
T02
T03
T04
T05
T28
T29
T30
T31
T32
U01
U02
U03
U04
U05
U28
U29
U30
U31
U32
V01
V02
V03
V04
V05
V28
V29
V30
VCC
N/C
GND
N/C
VCC
GND
N/C
VCC
N/C
GND
VCC
N/C
GND
N/C
VCC
GND
N/C
VCC
N/C
GND
N/C
N/C
N/C
N/C
N/C
N/C
N/C
VCC
N/C
GND
GND
N/C
VCC5A
N/C
GND
VCC
N/C
VCC5N
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
I
Power (PCI)
Power
Power
Power (PCI)
Intel® 450NX PCIset
12-47
12. Electrical Characteristics
Table 12-24: PXB Pinlist Sorted by Pin (Continued)
PIN#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
V31
N/C
V32
GND
Power
PCI
W01
W02
W03
W04
W05
W28
W29
W30
W31
W32
Y01
PBAD[31]
PBAD[30]
PBAD[29]
PBAD[28]
GND
I/O
I/O
I/O
I/O
PCI
PCI
PCI
Power
Power
PCI
VCC
PAAD[28]
PAAD[29]
PAAD[30]
PAAD[31]
VCC
I/O
I/O
I/O
I/O
PCI
PCI
PCI
Power
PCI
Y02
PBAD[27]
GND
I/O
I/O
Y03
Power
PCI
Y04
PBAD[26]
VCC
Y05
Power
Power
PCI
Y28
VCC
Y29
PAAD[26]
GND
I/O
I/O
Y30
Power
PCI
Y31
PAAD[27]
VCC
Y32
Power
PCI
AA1
AA2
AA3
AA4
AA5
AA28
AA29
AA30
AA31
AA32
AB01
AB02
AB03
AB04
AB05
AB28
PBAD[25]
PBAD[24]
PBAD[23]
PBAD[22]
PBAD[21]
PAAD[21]
PAAD[22]
PAAD[23]
PAAD[24]
PAAD[25]
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
Power
PCI
PBAD[20]
VCC5B
I/O
I/O
Power (PCI)
PCI
PBAD[19]
GND
Power
Power
GND
12-48
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-24: PXB Pinlist Sorted by Pin (Continued)
PIN#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
AB29
AB30
AB31
AB32
AC01
AC02
AC03
AC04
AC05
AC28
AC29
AC30
AC31
AC32
AD01
AD02
AD03
AD04
AD05
AD28
AD29
AD30
AD31
AD32
AE01
AE02
AE03
AE04
AE05
AE28
AE29
AE30
AE31
AE32
AF01
AF02
AF03
AF04
PAAD[19]
VCC5M
I/O
PCI
Power (PCI)
PCI
PAAD[20]
GND
I/O
Power
PCI
PBAD[18]
PBAD[17]
PBAD[16]
PBAD[15]
PBAD[14]
PAAD[14]
PAAD[15]
PAAD[16]
PAAD[17]
PAAD[18]
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
Power
PCI
PBAD[13]
GND
I/O
I/O
Power
PCI
PBAD[12]
VCC
Power
Power
PCI
VCC
PAAD[12]
GND
I/O
I/O
Power
PCI
PAAD[13]
VCC
Power
PCI
PBAD[11]
PBAD[10]
PBAD[09]
PBAD[08]
PBAD[07]
PAAD[07]
PAAD[08]
PAAD[09]
PAAD[10]
PAAD[11]
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
Power
PCI
PBAD[06]
VCC5C
I/O
I/O
Power (PCI)
PCI
PBAD[05]
Intel® 450NX PCIset
12-49
12. Electrical Characteristics
Table 12-24: PXB Pinlist Sorted by Pin (Continued)
PIN#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
AF05
AF28
AF29
AF30
AF31
AF32
AG01
AG02
AG03
AG04
AG05
AG28
AG29
AG30
AG31
AG32
AH01
AH02
AH03
AH04
AH05
AH06
AH07
AH08
AH09
AH10
AH11
AH12
AH13
AH14
AH15
AH16
AH17
AH18
AH19
AH20
AH21
AH22
GND
Power
Power
PCI
GND
PAAD[05]
VCC5L
I/O
I/O
Power (PCI)
PCI
PAAD[06]
GND
Power
PCI
PBAD[04]
PBAD[03]
PBAD[02]
PBAD[01]
PBAD[00]
PAAD[00]
PAAD[01]
PAAD[02]
PAAD[03]
PAAD[04]
N/C
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
N/C
VCC5D
VCC
Power (PCI)
Power
N/C
N/C
GND
Power
LVTTL
Power
PCI
PBMON[01]#
VCC
I/O
O
10ma
PBGNT[02]#
GND
Power
PCI
PBREQ[01]#
VCC
I
Power
PCI
PBDEVSEL#
GND
I/O
I/O
I/O
I/O
I
Power
PCI
PBCBE[00]#
VCC
Power
PCI
PACBE[00]#
GND
Power
PCI
PADEVSEL#
VCC
Power
PCI
PAREQ[01]#
12-50
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-24: PXB Pinlist Sorted by Pin (Continued)
PIN#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
AH23
AH24
AH25
AH26
AH27
AH28
AH29
AH30
AH31
AH32
AJ01
AJ02
AJ03
AJ04
AJ05
AJ06
AJ07
AJ08
AJ09
AJ10
AJ11
AJ12
AJ13
AJ14
AJ15
AJ16
AJ17
AJ18
AJ19
AJ20
AJ21
AJ22
AJ23
AJ24
AJ25
AJ26
AJ27
AJ28
GND
Power
PCI
PAGNT[02]#
VCC
O
Power
LVTTL
Power
PAMON[01]#
GND
I/O
10ma
N/C
VCC
Power
VCC5K
Power (PCI)
N/C
N/C
N/C
N/C
N/C
VCC
Power
PCI
N/C
N/C
PBXARB#
N/C
I
PBRST#
PBGNT[03]#
PBGNT[00]#
PBREQ[02]#
PBCBE[03]#
PBTRDY#
PBLOCK#
PBCBE[01]#
REQ64#
PACBE[01]#
PALOCK#
PATRDY#
PACBE[03]#
PAREQ[02]#
PAGNT[00]#
PAGNT[03]#
PARST#
MODE64#
PAXARB#
N/C
O
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
O
O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
O
O
O
I
I
Intel® 450NX PCIset
12-51
12. Electrical Characteristics
Table 12-24: PXB Pinlist Sorted by Pin (Continued)
PIN#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
AJ29
VCC
Power
AJ30
N/C
AJ31
N/C
AJ32
N/C
AK01
AK02
AK03
AK04
AK05
AK06
AK07
AK08
AK09
AK10
AK11
AK12
AK13
AK14
AK15
AK16
AK17
AK18
AK19
AK20
AK21
AK22
AK23
AK24
AK25
AK26
AK27
AK28
AK29
AK30
AK31
AK32
AL01
AL02
N/C
GND
Power
N/C
VCC5E
N/C
Power (PCI)
N/C
VCC
Power
N/C
GND
Power
PCI
PBGNT[04]#
VCC5F
PBREQ[03]#
GND
O
Power (PCI)
PCI
I
Power
PCI
PBIRDY#
VCC5G
PBPAR
GND
I/O
I/O
I/O
I/O
I
Power (PCI)
PCI
Power
PCI
PAPAR
VCC5H
PAIRDY#
GND
Power (PCI)
PCI
Power
PCI
PAREQ[03]#
VCC5I
PAGNT[04]#
GND
Power (PCI)
PCI
O
Power
PCI
PHOLD#
VCC
I
Power
N/C
VCC5J
N/C
Power (PCI)
Power
GND
N/C
N/C
N/C
12-52
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-24: PXB Pinlist Sorted by Pin (Continued)
PIN#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
AL03
AL04
AL05
AL06
AL07
AL08
AL09
AL10
AL11
AL12
AL13
AL14
AL15
AL16
AL17
AL18
AL19
AL20
AL21
AL22
AL23
AL24
AL25
AL26
AL27
AL28
AL29
AL30
AL31
AL32
AM01
AM02
AM03
AM04
AM05
AM06
AM07
AM08
N/C
N/C
N/C
N/C
INTRQB#
N/C
OD
PCI
PBMON[00]#
PBGNT[05]#
PBGNT[01]#
PBREQ[04]#
PBREQ[00]#
PBFRAME#
PBSTOP#
PBSERR#
ACK64#
PASERR#
PASTOP#
PAFRAME#
PAREQ[00]#
PAREQ[04]#
PAGNT[01]#
PAGNT[05]#
PAMON[00]#
PHLDA#
INTRQA#
N/C
I/O
O
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
O
I
I
I/O
I/O
OD
I/O
OD
I/O
I/O
I
I
O
O
I/O
O
OD
N/C
N/C
N/C
N/C
N/C
N/C
GND
Power
Power
Power
GND
GND
N/C
GND
Power
N/C
Intel® 450NX PCIset
12-53
12. Electrical Characteristics
Table 12-24: PXB Pinlist Sorted by Pin (Continued)
PIN#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
AM09
AM10
AM11
AM12
AM13
AM14
AM15
AM16
AM17
AM18
AM19
AM20
AM21
AM22
AM23
AM24
AM25
AM26
AM27
AM28
AM29
AM30
AM31
AM32
VCC
Power
N/C
GND
Power
PCI
PBREQ[05]#
VCC
I
Power
PCI
PBCBE[02]#
GND
I/O
I/O
I/O
I/O
I
Power
PCI
PBPERR#
VCC
Power
PCI
PAPERR#
GND
Power
PCI
PACBE[02]#
VCC
Power
PCI
PAREQ[05]#
GND
Power
N/C
VCC
Power
PCI
WSC#
GND
O
Power
Power
Power
Power
GND
GND
GND
N/C
GND
Power
Table 12-25: MUX Pin List Sorted by Pin
Pin#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
GND
Power
LVTTL
LVTTL
LVTTL
LVTTL
Power
LVTTL
Power
LVTTL
OD
Q2D23
Q1D22
Q3D21
Q3D20
GND
I/O
I/O
I/O
I/O
10ma
10ma
10ma
10ma
Q3D19
VCC
I/O
10ma
Q3D18
TDO
I/O
O
10ma
14ma
VCC
Power
12-54
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-25: MUX Pin List Sorted by Pin (Continued)
Pin#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
A12
A13
A14
A15
A16
A17
A18
A19
A20
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
C01
C02
C03
C04
C05
C06
C07
C08
C09
Q3D17
VCC
I/O
LVTTL
Power
LVTTL
Power
LVTTL
LVTTL
LVTTL
LVTTL
Power
LVTTL
Power
LVTTL
Power
LVTTL
Power
LVTTL
Power
LVTTL
Power
Power
LVTTL
Power
LVTTL
Power
LVTTL
Power
LVTTL
Power
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
10ma
Q1D16
GND
I/O
10ma
Q1D15
Q3D14
Q3D13
Q1D13
GND
I/O
I/O
I/O
I/O
10ma
10ma
10ma
10ma
Q1D25
GND
I/O
I/O
I/O
I/O
I/O
10ma
10ma
10ma
10ma
10ma
Q1D23
VCC
Q2D21
GND
Q2D19
VCC
Q2D18
GND
GND
Q2D17
VCC
I/O
I/O
I/O
I/O
10ma
10ma
10ma
10ma
Q0D16
GND
Q2D14
VCC
Q0D13
GND
Q2D11
Q3D25
Q0D25
Q0D24
Q0D23
Q0D22
Q1D21
Q1D20
Q1D19
Q1D18
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
Intel® 450NX PCIset
12-55
12. Electrical Characteristics
Table 12-25: MUX Pin List Sorted by Pin (Continued)
Pin#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
E01
E02
E03
E04
E05
E06
E07
TDI
I
I
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Power
LVTTL
Power
LVTTL
Power
LVTTL
Power
LVTTL
Power
Power
LVTTL
Power
LVTTL
Power
LVTTL
Power
LVTTL
Power
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
TCK
Q1D17
Q3D16
Q3D15
Q1D14
Q2D13
Q3D12
Q0D12
Q1D11
Q1D10
Q3D26
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
Q3D24
GND
I/O
I/O
I/O
I/O
10ma
10ma
10ma
10ma
Q3D22
VCC
Q2D20
GND
Q0D18
VCC
VCC
Q0D17
GND
I/O
I/O
I/O
I/O
10ma
10ma
10ma
10ma
Q0D15
VCC
Q2D12
GND
Q0D11
VCC
Q3D09
Q1D27
Q2D26
Q2D25
Q2D24
Q3D23
Q2D22
Q0D21
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
12-56
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-25: MUX Pin List Sorted by Pin (Continued)
Pin#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
E08
E09
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
F01
F02
F03
F04
F05
F06
F14
F15
F16
F17
F18
F19
F20
G01
G02
G03
G04
G05
G06
G16
G17
G18
G19
G20
H01
Q0D20
Q0D19
TMS
I/O
I/O
I
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Power
LVTTL
Power
LVTTL
Power
Power
Power
LVTTL
Power
LVTTL
Power
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Power
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Power
10ma
10ma
TRST#
Q2D16
Q2D15
Q0D14
Q1D12
Q3D11
Q3D10
Q0D10
Q2D09
Q3D08
Q0D28
GND
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
Q1D26
VCC
I/O
I/O
10ma
10ma
Q1D24
VCC
VCC
VCC
Q2D10
VCC
I/O
I/O
10ma
10ma
Q1D09
GND
Q1D08
Q2D28
Q1D28
Q3D27
Q0D27
Q0D26
VCC
I/O
I/O
I/O
I/O
I/O
I/O
10ma
10ma
10ma
10ma
10ma
10ma
Q0D09
Q2D08
Q0D08
Q1D07
Q2D07
VCC
I/O
I/O
I/O
I/O
I/O
10ma
10ma
10ma
10ma
10ma
Intel® 450NX PCIset
12-57
12. Electrical Characteristics
Table 12-25: MUX Pin List Sorted by Pin (Continued)
Pin#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
H02
H03
H04
H05
H16
H17
H18
H19
H20
J01
VCC
Power
LVTTL
Power
LVTTL
LVTTL
Power
LVTTL
Power
Power
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Power
Power
Power
Power
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Power
LVTTL
Power
LVTTL
Power
Power
Power
Power
LVTTL
Power
LVTTL
Power
LVTTL
LVTTL
Q0D29
GND
I/O
10ma
Q2D27
Q3D07
GND
I/O
I/O
10ma
10ma
Q0D07
VCC
I/O
10ma
VCC
Q0D30
Q3D29
Q2D29
Q1D29
Q3D28
GND
I/O
I/O
I/O
I/O
I/O
10ma
10ma
10ma
10ma
10ma
J02
J03
J04
J05
J09
J10
GND
J11
GND
J12
GND
J16
Q3D06
Q3D05
Q0D06
Q1D06
Q2D06
Q3D30
GND
I/O
I/O
I/O
I/O
I/O
I/O
10ma
10ma
10ma
10ma
10ma
10ma
J17
J18
J19
J20
K01
K02
K03
K04
K05
K09
K10
K11
K12
K16
K17
K18
K19
K20
L01
Q2D30
VCC
I/O
I/O
10ma
10ma
Q1D30
GND
GND
GND
GND
Q0D05
VCC
I/O
I/O
10ma
10ma
Q1D05
GND
Q2D05
Q2D31
I/O
I/O
10ma
10ma
12-58
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-25: MUX Pin List Sorted by Pin (Continued)
Pin#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
L02
GND
Power
LVTTL
Power
LVTTL
Power
Power
Power
Power
LVTTL
Power
LVTTL
Power
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Power
Power
Power
Power
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Power
Power
LVTTL
Power
LVTTL
LVTTL
Power
LVTTL
Power
Power
LVTTL
L03
Q1D31
VCC
I/O
I/O
10ma
10ma
L04
L05
Q0D31
GND
L09
L10
GND
L11
GND
L12
GND
L16
Q1D04
VCC
I/O
I/O
10ma
10ma
L17
L18
Q2D04
GND
L19
L20
Q3D04
Q2D32
Q1D32
Q0D32
Q3D31
Q3D32
GND
I/O
I/O
I/O
I/O
I/O
I/O
10ma
10ma
10ma
10ma
10ma
10ma
M01
M02
M03
M04
M05
M09
M10
M11
M12
M16
M17
M18
M19
M20
N01
N02
N03
N04
N05
N16
N17
N18
N19
N20
P01
GND
GND
GND
Q3D02
Q1D03
Q2D03
Q3D03
Q0D04
VCC
I/O
I/O
I/O
I/O
I/O
10ma
10ma
10ma
10ma
10ma
VCC
Q0D33
GND
I/O
10ma
Q3D33
Q3D01
GND
I/O
I/O
10ma
10ma
Q0D03
VCC
I/O
I/O
10ma
10ma
VCC
Q2D33
Intel® 450NX PCIset
12-59
12. Electrical Characteristics
Table 12-25: MUX Pin List Sorted by Pin (Continued)
Pin#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
P02
P03
P04
P05
P15
P16
P17
P18
P19
P20
R01
R02
R03
R04
R05
R06
R07
R15
R16
R17
R18
R19
R20
T01
T02
T03
T04
T05
T06
T07
T08
T09
T10
T11
T12
T13
T14
T15
Q1D33
Q0D34
Q1D34
Q3D34
VCC
I/O
I/O
I/O
I/O
LVTTL
LVTTL
LVTTL
LVTTL
Power
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Power
Power
LVTTL
Power
AGTL+
Power
Power
Power
AGTL+
Power
LVTTL
Power
Power
LVTTL
LVTTL
LVTTL
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
10ma
10ma
10ma
10ma
Q1D00
Q1D01
Q0D02
Q1D02
Q2D02
GND
I/O
I/O
I/O
I/O
I/O
10ma
10ma
10ma
10ma
10ma
GND
Q0D35
VCC
I/O
I/O
10ma
55ma
MD31#
VCC
VCC
VCC
MD00#
VCC
I/O
I/O
55ma
10ma
Q2D00
GND
GND
Q2D34
Q1D35
Q3D35
MD32#
MD29#
DSTBP1#
MD23#
MD19#
N/C
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
10ma
10ma
10ma
55ma
55ma
55ma
55ma
55ma
VCCA
WDME#
CRES0
MD15#
MD09#
MD07#
Power
I
AGTL+
Analog
AGTL+
AGTL+
AGTL+
55ma
I
I/O
I/O
I/O
55ma
55ma
55ma
12-60
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-25: MUX Pin List Sorted by Pin (Continued)
Pin#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
T16
T17
T18
T19
T20
U01
U02
U03
U04
U05
U06
U07
U08
U09
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
V01
V02
V03
V04
V05
V06
V07
V08
V09
V10
V11
V12
V13
MD05#
MD01#
Q0D00
Q3D00
Q2D01
Q2D35
VCC
I/O
I/O
I/O
I/O
I/O
I/O
AGTL+
AGTL+
LVTTL
LVTTL
LVTTL
LVTTL
Power
AGTL+
Power
Power
Power
AGTL+
Power
Power
Power
Power
Power
Power
AGTL+
Power
Power
Power
AGTL+
Power
LVTTL
55ma
55ma
10ma
10ma
10ma
10ma
MD33#
GND
I/O
55ma
VTT
VCC
MD21#
GND
I/O
55ma
VTT
VCC
VCC
VTT
GND
MD13#
VCC
I/O
55ma
VTT
GND
MD02#
VCC
I/O
I/O
55ma
10ma
Q0D01
N/C
MD34#
MD30#
MD27#
VREF
I/O
AGTL+
AGTL+
AGTL+
Analog
AGTL+
AGTL+
AGTL+
AGTL+
2.5V
55ma
55ma
55ma
I/O
I/O
I
MD24#
MD20#
DOFF1#
DOFF0#
HCLKIN
DVALID#
LRD#
I/O
55ma
55ma
55ma
55ma
I/O
I
I
I
I
I
I
AGTL+
AGTL+
Analog
55ma
55ma
CRES1
Intel® 450NX PCIset
12-61
12. Electrical Characteristics
Table 12-25: MUX Pin List Sorted by Pin (Continued)
Pin#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
V14
V15
V16
V17
V18
V19
V20
W01
W02
W03
W04
W05
W06
W07
W08
W09
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
Y01
MD16#
MD10#
VREF
I/O
I/O
I
AGTL+
AGTL+
Analog
AGTL+
AGTL+
AGTL+
55ma
55ma
MD08#
MD06#
MD03#
N/C
I/O
I/O
I/O
55ma
55ma
55ma
MD35#
GND
I/O
AGTL+
Power
Power
Power
AGTL+
Power
Power
Power
AGTL+
Power
Power
AGTL+
Power
Power
Power
AGTL+
Power
Power
Power
AGTL+
Power
AGTL+
AGTL+
AGTL+
AGTL+
Power
AGTL+
AGTL+
AGTL+
Power
AGTL+
55ma
VTT
VCC
MD25#
GND
I/O
55ma
VTT
VCC
DSEL#
GND
I
55ma
55ma
GND
GDCMPLT#
VCC
I/O
VTT
GND
MD11#
VCC
I/O
55ma
VTT
GND
MD04#
GND
I/O
55ma
Y02
MD28#
DSTBN1#
MD26#
MD22#
GND
I/O
I/O
I/O
I/O
55ma
55ma
55ma
55ma
Y03
Y04
Y05
Y06
Y07
MD18#
LDSTB#
MRESET#
VCC
I/O
55ma
55ma
55ma
Y08
I
I
Y09
Y10
Y11
WDEVT#
I
55ma
12-62
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-25: MUX Pin List Sorted by Pin (Continued)
Pin#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
AVWP#
DCMPLT#
MD17#
GND
I
AGTL+
AGTL+
AGTL+
Power
55ma
55ma
55ma
I/O
I/O
MD14#
MD12#
DSTBP0#
DSTBN0#
GND
I/O
I/O
I/O
I/O
AGTL+
AGTL+
AGTL+
AGTL+
Power
55ma
55ma
55ma
55ma
Table 12-26: RCG Pin List Sorted by Pin
Pin#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
B01
B02
B03
B04
B05
B06
GND
Power
LVTTL
LVTTL
LVTTL
LVTTL
Power
LVTTL
Power
LVTTL
LVTTL
LVTTL
LVTTL
Power
LVTTL
Power
LVTTL
LVTTL
LVTTL
LVTTL
Power
LVTTL
Power
LVTTL
Power
LVTTL
Power
RASCA0#
CASCA0#
RASCB0#
CASCB1#
GND
O
10ma
10ma
10ma
10ma
O
O
O
WECA#
VCC
O
10ma
WECB#
ADDRD13
ADDRD08
ADDRD03
VCC
O
O
O
O
10ma
10ma
10ma
10ma
ADDRD01
GND
O
10ma
RASDD1#
RASDD0#
CASDC0#
CASDA1#
GND
O
O
O
O
10ma
10ma
10ma
10ma
RASCA1#
GND
O
O
O
10ma
10ma
10ma
RASCB1#
VCC
CASCC0#
GND
Intel® 450NX PCIset
12-63
12. Electrical Characteristics
Table 12-26: RCG Pin List Sorted by Pin (Continued)
Pin#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
B07
B08
B09
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
C01
C02
C03
C04
C05
C06
C07
C08
C09
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
D01
D02
D03
D04
CASCD1#
VCC
O
LVTTL
Power
LVTTL
Power
Power
LVTTL
Power
LVTTL
Power
LVTTL
Power
LVTTL
Power
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
10ma
CASCC1#
GND
O
10ma
GND
ADDRD04
VCC
O
O
O
O
10ma
10ma
10ma
10ma
RASDC1#
GND
RASDC0#
VCC
CASDD1#
GND
CASDC1#
ADDRC05
ADDRC03
ADDRC00
RASCC1#
RASCC0#
RASCD0#
CASCB0#
CASCD0#
N/C
O
O
O
O
O
O
O
O
O
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
ADDRD12
ADDRD09
ADDRD05
ADDRD02
ADDRD00
RASDA0#
RASDB0#
WEDA#
CASDB0#
CASDD0#
WEDB#
O
O
O
O
O
O
O
O
O
O
O
O
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Power
LVTTL
Power
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
ADDRC08
VCC
ADDRC02
GND
O
10ma
12-64
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-26: RCG Pin List Sorted by Pin (Continued)
Pin#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
E01
E02
E03
E04
E05
E06
E07
E08
E09
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
F01
F02
RASCD1#
VCC
O
LVTTL
Power
LVTTL
Power
10ma
CASCA1#
GND
O
10ma
N/C
VCC
Power
Power
LVTTL
Power
LVTTL
Power
LVTTL
Power
LVTTL
Power
VCC
ADDRD06
GND
O
O
O
O
10ma
10ma
10ma
10ma
RASDB1#
VCC
CASDA0#
GND
CASDB1#
VCC
N/C
ADDRC10
ADDRC07
ADDRC04
ADDRC01
N/C
O
O
O
O
LVTTL
LVTTL
LVTTL
LVTTL
10ma
10ma
10ma
10ma
N/C
N/C
N/C
N/C
ADDRD11
ADDRD10
ADDRD07
RASDA1#
N/C
O
O
O
O
LVTTL
LVTTL
LVTTL
LVTTL
10ma
10ma
10ma
10ma
N/C
N/C
N/C
N/C
N/C
ADDRB12
ADDRC13
GND
O
O
LVTTL
LVTTL
Power
10ma
10ma
Intel® 450NX PCIset
12-65
12. Electrical Characteristics
Table 12-26: RCG Pin List Sorted by Pin (Continued)
Pin#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
F03
F04
F05
F06
F14
F15
F16
F17
F18
F19
F20
G01
G02
G03
G04
G05
G06
G16
G17
G18
G19
G20
H01
H02
H03
H04
H05
H16
H17
H18
H19
H20
J01
ADDRC06
VCC
LVTTL
LVTTL
10ma
10ma
O
N/C
VCC
Power
Power
Power
VCC
VCC
N/C
VCC
Power
LVTTL
Power
LVTTL
ADDRB13
GND
O
O
10ma
10ma
ADDRB09
N/C
ADDRC12
ADDRC11
ADDRC09
N/C
O
O
O
LVTTL
LVTTL
LVTTL
10ma
10ma
10ma
VCC
Power
N/C
ADDRB11
ADDRB10
ADDRB06
ADDRB05
VCC
O
O
O
O
LVTTL
LVTTL
LVTTL
LVTTL
Power
Power
LVTTL
Power
LVTTL
LVTTL
Power
LVTTL
Power
Power
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Power
10ma
10ma
10ma
10ma
VCC
CASAC0#
GND
O
10ma
CASAA1#
ADDRB08
GND
O
O
10ma
10ma
ADDRB07
VCC
O
10ma
VCC
WEAA#
CASAB1#
CASAD1#
WEAB#
CASAC1#
GND
O
O
O
O
O
10ma
10ma
10ma
10ma
10ma
J02
J03
J04
J05
J09
12-66
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-26: RCG Pin List Sorted by Pin (Continued)
Pin#
J10
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
GND
Power
Power
Power
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Power
LVTTL
Power
LVTTL
Power
Power
Power
Power
LVTTL
Power
LVTTL
Power
LVTTL
LVTTL
Power
LVTTL
Power
LVTTL
Power
Power
Power
Power
LVTTL
Power
LVTTL
Power
LVTTL
LVTTL
LVTTL
J11
GND
J12
GND
J16
ADDRB04
ADDRB03
ADDRB02
ADDRB01
ADDRB00
CASAA0#
GND
O
10ma
10ma
10ma
10ma
10ma
10ma
J17
O
O
O
O
O
J18
J19
J20
K01
K02
K03
K04
K05
K09
K10
K11
K12
K16
K17
K18
K19
K20
L01
L02
L03
L04
L05
L09
L10
L11
L12
L16
L17
L18
L19
L20
M01
M02
CASAB0#
VCC
O
O
10ma
10ma
CASAD0#
GND
GND
GND
GND
RASBB1#
VCC
O
O
10ma
10ma
RASBC1#
GND
RASBD1#
RASAA0#
GND
O
O
10ma
10ma
RASAC0#
VCC
O
O
10ma
10ma
RASAD0#
GND
GND
GND
GND
RASBA1#
VCC
O
O
10ma
10ma
RASBA0#
GND
RASBC0#
RASAB0#
RASAA1#
O
O
O
10ma
10ma
10ma
Intel® 450NX PCIset
12-67
12. Electrical Characteristics
Table 12-26: RCG Pin List Sorted by Pin (Continued)
Pin#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
M03
M04
M05
M09
M10
M11
M12
M16
M17
M18
M19
M20
N01
N02
N03
N04
N05
N16
N17
N18
N19
N20
P01
RASAB1#
RASAC1#
RASAD1#
GND
O
LVTTL
LVTTL
LVTTL
Power
Power
Power
Power
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Power
Power
LVTTL
Power
LVTTL
10ma
10ma
10ma
O
O
GND
GND
GND
CASBA0#
CASBB1#
RASBB0#
CASBB0#
RASBD0#
VCC
O
O
O
O
O
10ma
10ma
10ma
10ma
10ma
VCC
ADDRA01
GND
O
O
10ma
10ma
ADDRA00
N/C
GND
Power
LVTTL
Power
Power
LVTTL
LVTTL
LVTTL
LVTTL
CASBA1#
VCC
O
10ma
VCC
ADDRA03
ADDRA02
ADDRA05
ADDRA04
N/C
O
O
O
O
10ma
10ma
10ma
10ma
P02
P03
P04
P05
P15
VCC
Power
P16
N/C
P17
WEBA#
CASBC0#
CASBD0#
WEBB#
GND
O
O
O
O
LVTTL
LVTTL
LVTTL
LVTTL
Power
Power
LVTTL
Power
10ma
10ma
10ma
10ma
P18
P19
P20
R01
R02
R03
R04
R05
GND
ADDRA06
VCC
O
10ma
N/C
12-68
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-26: RCG Pin List Sorted by Pin (Continued)
Pin#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
R06
R07
R15
R16
R17
R18
R19
R20
T01
T02
T03
T04
T05
T06
T07
T08
T09
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
U01
U02
U03
U04
U05
U06
U07
U08
U09
U10
VCC
Power
Power
Power
VCC
VCC
N/C
VCC
Power
LVTTL
Power
Power
LVTTL
LVTTL
LVTTL
LVTTL
CASBD1#
GND
O
10ma
GND
ADDRA08
ADDRA07
ADDRA10
ADDRA09
N/C
O
O
O
O
10ma
10ma
10ma
10ma
N/C
MA05#
MA02#
N/C
I
I
LVTTL
LVTTL
10ma
10ma
VCCA
CMND1#
BANK0#
N/C
Power
I
I
AGTL+
AGTL+
WDME#
LRD#
O
O
AGTL+
AGTL+
55ma
55ma
N/C
VCC
Power
LVTTL
LVTTL
LVTTL
LVTTL
Power
BANKID#
DR50T#
CASBC1#
ADDRA11
VCC
I
Requires external pull-up
I
O
O
10ma
10ma
N/C
GND
Power
Power
Power
LVTTL
Power
Power
Power
VTT
VCC
MA06#
GND
I
10ma
VTT
VCC
Intel® 450NX PCIset
12-69
12. Electrical Characteristics
Table 12-26: RCG Pin List Sorted by Pin (Continued)
Pin#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
V01
V02
V03
V04
V05
V06
V07
V08
V09
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
W01
W02
W03
W04
W05
W06
W07
W08
VCC
Power
Power
Power
AGTL+
Power
Power
Power
LVTTL
Power
Power
LVTTL
LVTTL
Analog
Analog
Analog
AGTL+
AGTL+
AGTL+
AGTL+
2.5V
VTT
GND
RHIT#
VCC
O
55ma
VTT
GND
DR50H#
VCC
I
VCC
ADDRA13
ADDRA12
CRES1
CRES0
VREF
MA09#
MA07#
MA03#
MA00#
HCLKIN
CSTB#
BANK1#
RCMPLT#
PHIT#
AVWP#
VREF
TRST#
TCK
O
O
I
10ma
10ma
I
I
I
I
I
I
I
I
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
Analog
LVTTL
LVTTL
OD
I
O
O
O
I
55ma
55ma
55ma
I
I
TDO
O
I
14ma
TDI
LVTTL
N/C
GND
Power
Power
Power
AGTL+
Power
Power
Power
VTT
VCC
MA10#
GND
I
VTT
VCC
12-70
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-26: RCG Pin List Sorted by Pin (Continued)
Pin#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
W09
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
Y01
Y02
Y03
Y04
Y05
Y06
Y07
Y08
Y09
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
MA01#
GND
I
I
AGTL+
Power
Power
AGTL+
Power
Power
Power
GND
BANK2#
VCC
VTT
GND
N/C
VCC
Power
Power
Power
VTT
GND
N/C
GND
Power
N/C
MA13#
MA12#
MA11#
GND
I
I
I
AGTL+
AGTL+
AGTL+
Power
MA08#
MA04#
MRESET#
VCC
I
I
I
AGTL+
AGTL+
AGTL+
Power
ROW#
CMND0#
CARD#
GRCMPLT#
GND
I
I
I
AGTL+
AGTL+
AGTL+
AGTL+
Power
I/O
55ma
55ma
LDSTB#
N/C
O
AGTL+
TMS
I
LVTTL
Power
N/C
GND
Intel® 450NX PCIset
12-71
12. Electrical Characteristics
12.9.2 Pin Lists Sorted by Signal
Table 12-27: MIOC Pin List Sorted by Signal
Pin#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
B04
C04
D04
E04
A05
C05
E05
B06
C06
D06
A07
B07
C07
D07
E07
C08
E08
A09
B09
C09
D09
B10
D10
E10
B11
D11
A12
B12
C12
D12
E12
A13
B13
J03
A03#
A04#
A05#
A06#
A07#
A08#
A09#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
A32#
A33#
A34#
A35#
ADS#
AERR#
AP0#
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
K05
H01
12-72
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-27: MIOC Pin List Sorted by Signal (Continued)
Pin#
J01
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
AP1#
I/O
O
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
OD
55ma
55ma
55ma
55ma
55ma
55ma
55ma
14ma
14ma
55ma
55ma
55ma
55ma
55ma
55ma
AJ17
AH18
AM18
D13
J29
BANK0#
BANK1#
BANK2#
BERR#
BINIT#
BNR#
BP0#
O
O
I/O
I/O
I/O
I/O
I/O
I/O
O
C02
J30
J31
BP1#
OD
D01
J02
BPRI#
BR0#
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
Analog
Analog
LVTTL
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AL18
AJ18
AL11
AJ12
C11
A17
H29
AM12
D14
A15
B15
CARD0#
CARD1#
CMND0#
CMND1#
CRES0
CRES1
CRESET#
CSTB#
D00#
O
O
O
O
I
I
O
10ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D01#
D02#
C15
D15
E15
D03#
D04#
D05#
B16
D06#
D16
E16
D07#
D08#
B17
D09#
D17
E17
D10#
D11#
A18
B18
D12#
D13#
C18
D18
E18
D14#
D15#
D16#
B19
D17#
D19
D18#
Intel® 450NX PCIset
12-73
12. Electrical Characteristics
Table 12-27: MIOC Pin List Sorted by Signal (Continued)
Pin#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
A20
B20
D20
A21
B21
C21
D21
E21
B22
D22
B23
D23
E23
A24
B24
C24
D24
C25
E25
A26
B26
C26
D26
E26
B27
C27
D27
A28
C28
E28
A29
B29
C29
D29
E29
B30
C30
E30
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
12-74
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-27: MIOC Pin List Sorted by Signal (Continued)
Pin#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
C31
D57#
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
OD
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
14ma
14ma
D31
D58#
E31
D59#
D32
D60#
E32
D61#
F29
D62#
F30
D63#
A04
DBSY#
AJ16
AH15
G05
DCMPLTA#
DCMPLTB#
DEFER#
DEP0#
H32
H31
H30
G32
DEP1#
DEP2#
DEP3#
G31
DEP4#
G29
DEP5#
G28
DEP6#
F31
DEP7#
AH12
AM13
B14
DOFF0#
DOFF1#
DRDY#
DSEL0#
DSEL1#
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
DVALIDA#
DVALIDB#
ERR0#
O
I/O
O
AJ13
AL14
U02
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
AD01
AJ02
AH09
U01
AC04
AJ01
AK08
AK15
AL16
K01
O
I/O
I/O
K02
ERR1#
OD
A01
GND
Power
A02
GND
Power
Intel® 450NX PCIset
12-75
12. Electrical Characteristics
Table 12-27: MIOC Pin List Sorted by Signal (Continued)
Pin#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
A03
A06
A10
A11
A14
A16
A19
A22
A23
A27
B01
B02
B05
B28
C01
D08
D25
E09
E13
E14
E19
E20
E24
F01
F32
G01
H05
H28
J05
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
J32
L01
L32
M05
M28
R01
R29
T28
U04
12-76
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-27: MIOC Pin List Sorted by Signal (Continued)
Pin#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
U05
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
U32
V04
V05
V32
W05
Y28
AA05
AA28
AB01
AB32
AC01
AC05
AC28
AD05
AD28
AE01
AE32
AF01
AF32
AH13
AH14
AH19
AH20
AH24
AH25
AH32
AJ08
AJ19
AJ24
AJ25
AJ26
AK24
AK25
AK27
AK32
AL05
AL27
Intel® 450NX PCIset
12-77
12. Electrical Characteristics
Table 12-27: MIOC Pin List Sorted by Signal (Continued)
Pin#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
AL28
AL31
AL32
AM06
AM11
AM14
AM16
AM19
AM22
AM23
AM27
AM28
AM30
AM31
AM32
R28
GND
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
2.5V
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
HCLKIN
HIT#
I
I
G02
AGTL+
AGTL+
2.5V
H02
HITM#
INIT#
N29
OD
O
I
14ma
10ma
L04
INTREQ#
IOGNT#
IOREQ#
LOCK#
MA00#
MA01#
MA02#
MA03#
MA04#
MA05#
MA06#
MA07#
MA08#
MA09#
MA10#
MA11#
MA12#
MA13#
MD00#
LVTTL
LVTTL
LVTTL
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
N05
N04
O
I
10ma
F03
AM20
AL20
AJ20
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I/O
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
AM21
AL21
AK21
AJ21
AH21
AL22
AJ22
AL23
AJ23
AH23
AM24
P02
12-78
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-27: MIOC Pin List Sorted by Signal (Continued)
Pin#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
P03
MD01#
MD02#
MD03#
MD04#
MD05#
MD06#
MD07#
MD08#
MD09#
MD10#
MD11#
MD12#
MD13#
MD14#
MD15#
MD16#
MD17#
MD18#
MD19#
MD20#
MD21#
MD22#
MD23#
MD24#
MD25#
MD26#
MD27#
MD28#
MD29#
MD30#
MD31#
MD32#
MD33#
MD34#
MD35#
MD36#
MD37#
MD38#
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
P04
R02
R03
T01
T02
T03
T04
U03
V02
V03
W01
W02
W03
W04
Y02
Y04
Y05
AA01
AA02
AA03
AA04
AB02
AB04
AB05
AC02
AD02
AD03
AD04
AE02
AE04
AE05
AF02
AF04
AF05
AG01
AG02
AG03
Intel® 450NX PCIset
12-79
12. Electrical Characteristics
Table 12-27: MIOC Pin List Sorted by Signal (Continued)
Pin#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
AG04
AH01
AH02
AH03
AH04
AH05
AJ04
MD39#
MD40#
MD41#
MD42#
MD43#
MD44#
MD45#
MD46#
MD47#
MD48#
MD49#
MD50#
MD51#
MD52#
MD53#
MD54#
MD55#
MD56#
MD57#
MD58#
MD59#
MD60#
MD61#
MD62#
MD63#
MD64#
MD65#
MD66#
MD67#
MD68#
MD69#
MD70#
MD71#
MRESET#
N/C
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
AK02
AK03
AK04
AK05
AL03
AL04
AM04
AM05
AJ06
AK06
AL06
AH07
AJ07
AK07
AL07
AM07
AH08
AJ09
AK09
AL09
AM09
AJ10
AK10
AL10
AM10
AJ11
AL13
C23
K29
N/C
U28
N/C
AC32
VCC
Power
12-80
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-27: MIOC Pin List Sorted by Signal (Continued)
Pin#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
AK13
AL17
L31
PHITA#
PHITB#
PWRGD
PWRGDB
RCMPLTA#
RCMPLTB#
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
RESET#
RHITA#
RHITB#
ROW#
RP#
I
I
I
AGTL+
AGTL+
LVTTL
LVTTL
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
LVTTL
LVTTL
LVTTL
OD
P28
O
10ma
AM15
AJ15
E01
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I
55ma
55ma
55ma
55ma
55ma
55ma
F04
G04
H04
F02
M29
AL12
AM17
AH16
J04
I
O
55ma
55ma
55ma
55ma
55ma
55ma
10ma
I/O
I/O
I/O
I/O
I/O
O
B03
RS0#
C03
E03
RS1#
RS2#
E02
RSP#
AL19
L03
SMIACT#
TCK
I
M04
M03
L05
TDI
I
TDO
O
14ma
55ma
TMS
I
LVTTL
LVTTL
LVTTL
AGTL+
LVTTL
Power
M01
N02
D02
L02
TPCTL0
TPCTL1
TRDY#
TRST#
VCC
I
I
I/O
I
A30
A31
A32
B31
VCC
Power
VCC
Power
VCC
Power
B32
VCC
Power
C10
C13
C14
C19
VCC
Power
VCC
Power
VCC
Power
VCC
Power
Intel® 450NX PCIset
12-81
12. Electrical Characteristics
Table 12-27: MIOC Pin List Sorted by Signal (Continued)
Pin#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
C20
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
C22
C32
E06
E27
F05
F28
K03
K28
L30
M02
N01
N32
P01
P05
P32
R04
R05
T05
V01
V28
V29
W28
Y01
Y32
AB03
AB30
AC30
AF28
AG05
AG28
AH06
AH10
AH11
AH17
AH27
AK01
AK11
12-82
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-27: MIOC Pin List Sorted by Signal (Continued)
Pin#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
AK12
AK14
AK18
AK19
AK20
AK22
AK23
AL01
AL02
AL24
AM01
AM02
AM03
K30
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCA0
VCCA1
VCCA2
VREF
VREF
VREF
VREF
VREF
VREF
VTT
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Analog
Analog
Analog
Analog
Analog
Analog
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
K31
K32
K04
I
I
I
I
I
I
N31
U30
AC03
AG29
AL15
A08
A25
VTT
B08
VTT
B25
VTT
C16
VTT
C17
VTT
D03
VTT
D05
VTT
D28
VTT
D30
VTT
E11
VTT
E22
VTT
G03
VTT
G30
VTT
H03
VTT
N03
VTT
Intel® 450NX PCIset
12-83
12. Electrical Characteristics
Table 12-27: MIOC Pin List Sorted by Signal (Continued)
Pin#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
Y03
VTT
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
LVTTL
LVTTL
LVTTL
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
Y30
VTT
AE03
AE30
AF03
AF30
AH22
AJ03
AJ05
AJ28
AJ30
AK16
AK17
AL08
AL25
AL26
AM08
AM25
AM26
AJ14
R30
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
WDEVT#
X0ADS#
X0BE0#
X0BE1#
X0BLK#
X0CLK
X0CLKB
X0CLKFB
X0D00#
X0D01#
X0D02#
X0D03#
X0D04#
X0D05#
X0D06#
X0D07#
X0D08#
X0D09#
X0D10#
O
55ma
55ma
55ma
55ma
55ma
10ma
10ma
I/O
I/O
I/O
O
P31
P30
R32
L28
O
L29
O
J28
I
T32
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
T31
T30
T29
U29
U31
Y31
Y29
AA32
AA31
AA30
12-84
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-27: MIOC Pin List Sorted by Signal (Continued)
Pin#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
AA29
AB31
AB29
AB28
AC31
W30
X0D11#
X0D12#
X0D13#
X0D14#
X0D15#
X0HRTS#
X0HSTBN#
X0HSTBP#
X0PAR#
X0RST#
X0RSTB#
X0RSTFB#
X0XRTS#
X0XSTBN#
X0XSTBP#
X1ADS#
X1BE0#
I/O
I/O
I/O
I/O
I/O
O
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
LVTTL
LVTTL
LVTTL
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
W31
O
W32
O
R31
I/O
O
P29
N30
O
M32
I
W29
I
V30
I
V31
I
AD32
AD30
AD29
AE28
M30
I/O
I/O
I/O
O
55ma
55ma
55ma
55ma
10ma
10ma
X1BE1#
X1BLK#
X1CLK
O
M31
X1CLKB
X1CLKFB
X1D00#
X1D01#
X1D02#
X1D03#
X1D04#
X1D05#
X1D06#
X1D07#
X1D08#
X1D09#
X1D10#
X1D11#
X1D12#
X1D13#
X1D14#
X1D15#
O
N28
I
AE31
AE29
AF31
AF29
AG31
AG30
AJ29
AK31
AK30
AK29
AK28
AL30
AL29
AJ27
AH26
AK26
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
Intel® 450NX PCIset
12-85
12. Electrical Characteristics
Table 12-27: MIOC Pin List Sorted by Signal (Continued)
Pin#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
AJ32
X1HRTS#
X1HSTBN#
X1HSTBP#
X1PAR#
O
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
55ma
55ma
55ma
55ma
55ma
55ma
AH28
AH29
AM29
AC29
AD31
AG32
AJ31
O
O
I/O
O
O
I
X1RST#
X1RSTB#
X1RSTFB#
X1XRTS#
X1XSTBN#
X1XSTBP#
I
AH30
AH31
I
I
Table 12-28: PXB Pin List Sorted by Signal
PIN#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
AL17
E09
ACK64#
CRES0
CRES1
INTRQA#
INTRQB#
MODE64#
N/C
I/O
PCI
I
Analog
Analog
PCI
D09
AL27
AL7
AJ26
A01
A02
A11
A13
A23
A25
A30
A31
A32
B01
I
OD
OD
I
PCI
PCI
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
B05
N/C
B06
N/C
B07
N/C
B08
N/C
B09
N/C
B10
N/C
B11
N/C
B12
N/C
B13
N/C
12-86
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-28: PXB Pin List Sorted by Signal (Continued)
I/O Driver Type Driver Strength Internal Pullup/Pulldown
PIN#
Signal
B17
B23
B24
B25
B26
B27
B32
C01
C02
C03
C04
C05
C09
C11
C13
C23
C28
C29
C30
C31
C32
D01
D03
D05
D06
D07
D08
D10
D11
D12
D13
D14
D19
D23
D24
D25
D26
D30
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
Intel® 450NX PCIset
12-87
12. Electrical Characteristics
Table 12-28: PXB Pin List Sorted by Signal (Continued)
I/O Driver Type Driver Strength Internal Pullup/Pulldown
PIN#
Signal
D32
E01
E02
E03
E04
E05
E07
E11
E25
E28
E29
E30
E31
E32
F02
F04
F30
F32
G01
G02
G03
G04
G05
G28
G29
G32
H02
H04
H28
H29
H31
H32
J01
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
J02
J03
J04
J05
J28
12-88
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-28: PXB Pin List Sorted by Signal (Continued)
I/O Driver Type Driver Strength Internal Pullup/Pulldown
PIN#
J29
Signal
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
J31
K02
K04
K31
L28
L29
L31
M02
M31
N28
N29
N30
N31
N32
P02
P04
P29
P31
R02
R04
R29
R31
T02
T04
T29
T31
U01
U02
U03
U04
U05
U28
U29
U31
V02
V04
V29
Intel® 450NX PCIset
12-89
12. Electrical Characteristics
Table 12-28: PXB Pin List Sorted by Signal (Continued)
I/O Driver Type Driver Strength Internal Pullup/Pulldown
PIN#
Signal
V31
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
AH01
AH02
AH05
AH06
AH28
AH31
AH32
AJ01
AJ02
AJ03
AJ05
AJ06
AJ08
AJ28
AJ30
AJ31
AJ32
AK01
AK03
AK05
AK06
AK08
AK28
AK30
AK32
AL01
AL02
AL03
AL04
AL05
AL06
AL08
AL28
AL29
AL30
AL31
AL32
12-90
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-28: PXB Pin List Sorted by Signal (Continued)
PIN#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
AM01
AM02
AM06
AM08
AM10
AM24
AM31
K29
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
M29
N/C
F31
N/C
AG28
AG29
AG30
AG31
AG32
AF29
AF31
AE28
AE29
AE30
AE31
AE32
AD29
AD31
AC28
AC29
AC30
AC31
AC32
AB29
AB31
AA28
AA29
AA30
AA31
AA32
Y29
PAAD[00]
PAAD[01]
PAAD[02]
PAAD[03]
PAAD[04]
PAAD[05]
PAAD[06]
PAAD[07]
PAAD[08]
PAAD[09]
PAAD[10]
PAAD[11]
PAAD[12]
PAAD[13]
PAAD[14]
PAAD[15]
PAAD[16]
PAAD[17]
PAAD[18]
PAAD[19]
PAAD[20]
PAAD[21]
PAAD[22]
PAAD[23]
PAAD[24]
PAAD[25]
PAAD[26]
PAAD[27]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
Y31
Intel® 450NX PCIset
12-91
12. Electrical Characteristics
Table 12-28: PXB Pin List Sorted by Signal (Continued)
PIN#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
W29
PAAD[28]
PAAD[29]
PAAD[30]
PAAD[31]
PACBE[0]#
PACBE[1]#
PACBE[2]#
PACBE[3]#
PACLK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
LVTTL
LVTTL
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
LVTTL
LVTTL
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
W30
W31
W32
AH18
AJ18
AM20
AJ21
L32
10ma
J32
PACLKFB
I
AH20
AL20
AJ23
AL23
AH24
AJ24
AK24
AL24
AK20
AJ19
AL25
AH26
AK18
AM18
AL21
AH22
AJ22
AK22
AL22
AM22
AJ25
PADEVSEL# I/O
PAFRAME#
PAGNT[0]#
PAGNT[1]#
PAGNT[2]#
PAGNT[3]#
PAGNT[4]#
PAGNT[5]#
PAIRDY#
I/O
O
O
O
O
O
O
I/O
I/O
PALOCK#
PAMON[0]# I/O
PAMON[1]# I/O
10ma
10ma
PAPAR
I/O
I/O
I
PAPERR#
PAREQ[0]#
PAREQ[1]#
PAREQ[2]#
PAREQ[3]#
PAREQ[4]#
PAREQ[5]#
PARST#
I
I
I
I
I
O
AL18
AL19
AJ20
AJ27
AG05
AG04
AG03
PASERR#
PASTOP#
PATRDY#
PAXARB#
PBAD[00]
PBAD[01]
PBAD[02]
OD
I/O
I/O
I
I/O
I/O
I/O
12-92
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-28: PXB Pin List Sorted by Signal (Continued)
PIN#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
AG02
AG01
AF04
AF02
AE05
AE04
AE03
AE02
AE01
AD04
AD02
AC05
AC04
AC03
AC02
AC01
AB04
AB02
AA05
AA04
AA03
AA02
AA01
Y04
PBAD[03]
PBAD[04]
PBAD[05]
PBAD[06]
PBAD[07]
PBAD[08]
PBAD[09]
PBAD[10]
PBAD[11]
PBAD[12]
PBAD[13]
PBAD[14]
PBAD[15]
PBAD[16]
PBAD[17]
PBAD[18]
PBAD[19]
PBAD[20]
PBAD[21]
PBAD[22]
PBAD[23]
PBAD[24]
PBAD[25]
PBAD[26]
PBAD[27]
PBAD[28]
PBAD[29]
PBAD[30]
PBAD[31]
PBCBE[0]#
PBCBE[1]#
PBCBE[2]#
PBCBE[3]#
PBCLK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
LVTTL
LVTTL
PCI
PCI
PCI
Y02
W04
W03
W02
W01
AH16
AJ16
AM14
AJ13
L30
10ma
J30
PBCLKFB
PBDEVSEL#
PBFRAME#
PBGNT[0]#
I
AH14
AL14
AJ11
I/O
I/O
O
Intel® 450NX PCIset
12-93
12. Electrical Characteristics
Table 12-28: PXB Pin List Sorted by Signal (Continued)
PIN#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
AL11
AH10
AJ10
AK10
AL10
AK14
AJ15
AL09
AH08
AK16
AM16
AL13
AH12
AJ12
AK12
AL12
AM12
AJ09
AL16
AL15
AJ14
AJ07
AL26
AK26
F29
PBGNT[1]#
PBGNT[2]#
PBGNT[3]#
PBGNT[4]#
PBGNT[5]#
PBIRDY#
PBLOCK#
PBMON[0]#
PBMON[1]#
PBPAR
O
PCI
O
PCI
O
PCI
O
PCI
O
PCI
I/O
PCI
I/O
PCI
I/O
PCI
I/O
PCI
I/O
PCI
PBPERR#
PBREQ[0]#
PBREQ[1]#
PBREQ[2]#
PBREQ[3]#
PBREQ[4]#
PBREQ[5]#
PBRST#
PBSERR#
PBSTOP#
PBTRDY#
PBXARB#
PHLDA#
PHOLD#
PIIXOK#
PWRGD
REQ64#
TCK
I/O
PCI
I
PCI
I
PCI
I
PCI
I
PCI
I
PCI
I
PCI
O
PCI
OD
PCI
I/O
PCI
I/O
PCI
I
PCI
O
PCI
I
PCI
I
LVTTL
LVTTL
PCI
D29
I
AJ17
M04
I/O
I
2.5V
2.5V
OD
N01
TDI
I
N02
TDO
O
I
14ma
N04
TMS
2.5V
2.5V
Power
Power
Power
Power
Power
Power
N05
TRST#
I
A03
VCC
A04
VCC
A05
VCC
A06
VCC
A07
VCC
A08
VCC
12-94
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-28: PXB Pin List Sorted by Signal (Continued)
PIN#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
A09
A10
A14
A16
A18
A20
A22
A26
A28
A29
B02
B03
B04
B28
B29
B30
B31
D27
F03
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
G30
G31
H01
H05
K03
K30
M01
M05
M28
M32
N03
P01
P30
R01
R30
T01
T30
U030
Y1
Intel® 450NX PCIset
12-95
12. Electrical Characteristics
Table 12-28: PXB Pin List Sorted by Signal (Continued)
PIN#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
Y05
VCC
Power
Y28
VCC
Power
Y32
VCC
Power
AD01
AD05
AD28
AD32
AH04
AH09
AH13
AH17
AH21
AH25
AH29
AJ04
VCC
Power
VCC
Power
VCC
Power
VCC
Power
VCC
Power
VCC
Power
VCC
Power
VCC
Power
VCC
Power
VCC
Power
VCC
Power
VCC
Power
AJ29
VCC
Power
AK07
AK27
AM09
AM13
AM17
AM21
AM25
P05
VCC
Power
VCC
Power
VCC
Power
VCC
Power
VCC
Power
VCC
Power
VCC
Power
VCC
Power
R05
VCC
Power
T05
VCC
Power
V28
VCC
Power
W28
VCC
Power
V03
VCC5A
VCC5B
VCC5C
VCC5D
VCC5E
VCC5F
VCC5G
VCC5H
VCC5I
VCC5J
Power (PCI)
Power (PCI)
Power (PCI)
Power (PCI)
Power (PCI)
Power (PCI)
Power (PCI)
Power (PCI)
Power (PCI)
Power (PCI)
AB03
AF03
AH03
AK04
AK11
AK15
AK19
AK23
AK29
12-96
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-28: PXB Pin List Sorted by Signal (Continued)
PIN#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
AH30
AF30
AB30
V30
A27
C27
E27
A12
A24
C06
C07
C08
C10
C12
C14
C16
C18
C20
C22
C24
C26
D02
D31
F01
VCC5K
VCC5L
VCC5M
VCC5N
VCCA0
VCCA1
VCCA2
VREF
VREF
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Power (PCI)
Power (PCI)
Power (PCI)
Power (PCI)
Power
Power
Power
I
I
Analog
Analog
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
F05
Power
F28
Power
H03
H30
K01
K05
K28
K32
L01
L02
L03
L04
L05
M03
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Intel® 450NX PCIset
12-97
12. Electrical Characteristics
Table 12-28: PXB Pin List Sorted by Signal (Continued)
PIN#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
M30
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
P03
P32
R03
R32
T03
T32
U32
V01
V32
Y03
Y30
AB01
AB05
AB28
AB32
AD03
AD30
AF01
AF05
AF28
AF32
AH07
AH11
AH15
AH19
AH23
AH27
AK02
AK09
AK13
AK17
AK21
AK25
AK31
AM03
AM04
AM05
12-98
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-28: PXB Pin List Sorted by Signal (Continued)
PIN#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
AM07
AM11
AM15
AM19
AM23
AM27
AM28
AM29
AM30
AM32
P28
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VTT
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
PCI
R28
T28
V05
W05
D04
D28
VTT
E06
VTT
E08
VTT
E10
VTT
E12
VTT
E14
VTT
E16
VTT
E18
VTT
E20
VTT
E22
VTT
E24
VTT
E26
VTT
AM26
C21
WSC#
XADS#
XBE[0]#
XBE[1]#
XBLK#
XCLK
XD[00]#
XD[01]#
XD[02]#
XD[03]#
O
I/O
I/O
I/O
I
AGTL+
AGTL+
AGTL+
AGTL+
LVTTL
AGTL+
AGTL+
AGTL+
AGTL+
55ma
55ma
55ma
E23
B22
A21
C25
I
D21
I/O
I/O
I/O
I/O
55ma
55ma
55ma
55ma
E21
B20
D20
Intel® 450NX PCIset
12-99
12. Electrical Characteristics
Table 12-28: PXB Pin List Sorted by Signal (Continued)
PIN#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
A19
B19
D17
E17
B16
D16
A15
B15
C15
D15
E15
B14
B18
A17
C17
E13
B21
D22
D18
C19
E19
XD[04]#
XD[05]#
XD[06]#
XD[07]#
XD[08]#
XD[09]#
XD[10]#
XD[11]#
XD[12]#
XD[13]#
XD[14]#
XD[15]#
XHRTS#
XHSTBN#
XHSTBP#
XIB
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
I
I
O
55ma
55ma
XPAR#
I/O
I
XRST#
XXRTS#
XXSTBN#
XXSTBP#
O
55ma
55ma
55ma
O
O
Table 12-29: MUX Pin List Sorted by Signal
PIN#
Signal
I/O
Driver Type
Driver Strength
Input Pullup/Pulldown
Y12
T12
V13
Y13
V09
V08
W09
Y19
Y03
Y18
T06
V11
T09
AVWP#
CRES0
I
I
I
AGTL+
Analog
Analog
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
CRES1
DCMPLT#
DOFF0#
DOFF1#
DSEL#
I/O
I
55ma
I
I
DSTBN0#
DSTBN1#
DSTBP0#
DSTBP1#
DVALID#
N/C
I/O
I/O
I/O
I/O
I
55ma
55ma
55ma
55ma
12-100
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-29: MUX Pin List Sorted by Signal (Continued)
PIN#
Signal
I/O
Driver Type
Driver Strength
Input Pullup/Pulldown
W12
A01
A06
A15
A20
B02
B06
B10
B11
B15
B19
F02
F19
H04
H17
J09
GDCMPLT#
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
I/O
AGTL+
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
55ma
J10
J11
J12
N04
N17
R01
R02
R19
R20
W06
W10
W11
W15
W19
Y01
Y06
Y15
Y20
D04
D08
D13
D17
Intel® 450NX PCIset
12-101
12. Electrical Characteristics
Table 12-29: MUX Pin List Sorted by Signal (Continued)
PIN#
Signal
I/O
Driver Type
Driver Strength
Input Pullup/Pulldown
K02
K09
K10
K11
K12
K19
L02
L09
L10
L11
L12
L19
M09
M10
M11
M12
U04
U08
U13
U17
W02
V10
Y08
V12
R16
T17
U18
V19
W20
T16
V18
T15
V17
T14
V15
W16
Y17
U14
GND
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
2.5V
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
HCLKIN
LDSTB#
LRD#
MD00#
MD01#
MD02#
MD03#
MD04#
MD05#
MD06#
MD07#
MD08#
MD09#
MD10#
MD11#
MD12#
MD13#
I
O
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
55ma
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
12-102
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-29: MUX Pin List Sorted by Signal (Continued)
PIN#
Signal
I/O
Driver Type
Driver Strength
Input Pullup/Pulldown
Y16
T13
V14
Y14
Y07
T08
V07
U07
Y05
T07
V06
W05
Y04
V04
Y02
T05
V03
R05
T04
U03
V02
W01
Y09
Y10
V20
V01
T18
U20
P18
N18
M20
K16
J18
MD14#
MD15#
MD16#
MD17#
MD18#
MD19#
MD20#
MD21#
MD22#
MD23#
MD24#
MD25#
MD26#
MD27#
MD28#
MD29#
MD30#
MD31#
MD32#
MD33#
MD34#
MD35#
MRESET#
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
Power
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
55ma
N/C
N/C
Q0D00
Q0D01
Q0D02
Q0D03
Q0D04
Q0D05
Q0D06
Q0D07
Q0D08
Q0D09
Q0D10
Q0D11
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
H18
G18
G16
E18
D18
Intel® 450NX PCIset
12-103
12. Electrical Characteristics
Table 12-29: MUX Pin List Sorted by Signal (Continued)
PIN#
Signal
I/O
Driver Type
Driver Strength
Input Pullup/Pulldown
C18
B18
E14
D14
B14
D12
D09
E09
E08
E07
C05
C04
C03
C02
G05
G04
F01
H03
J01
Q0D12
Q0D13
Q0D14
Q0D15
Q0D16
Q0D17
Q0D18
Q0D19
Q0D20
Q0D21
Q0D22
Q0D23
Q0D24
Q0D25
Q0D26
Q0D27
Q0D28
Q0D29
Q0D30
Q0D31
Q0D32
Q0D33
Q0D34
Q0D35
Q1D00
Q1D01
Q1D02
Q1D03
Q1D04
Q1D05
Q1D06
Q1D07
Q1D08
Q1D09
Q1D10
Q1D11
Q1D12
Q1D13
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
L05
M03
N03
P03
R03
P16
P17
P19
M17
L16
K18
J19
G19
F20
F18
C20
C19
E15
A19
12-104
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-29: MUX Pin List Sorted by Signal (Continued)
PIN#
Signal
I/O
Driver Type
Driver Strength
Input Pullup/Pulldown
C15
A16
A14
C12
C09
C08
C07
C06
A03
B03
F05
B01
F03
E01
G02
J04
Q1D14
Q1D15
Q1D16
Q1D17
Q1D18
Q1D19
Q1D20
Q1D21
Q1D22
Q1D23
Q1D24
Q1D25
Q1D26
Q1D27
Q1D28
Q1D29
Q1D30
Q1D31
Q1D32
Q1D33
Q1D34
Q1D35
Q2D00
Q2D01
Q2D02
Q2D03
Q2D04
Q2D05
Q2D06
Q2D07
Q2D08
Q2D09
Q2D10
Q2D11
Q2D12
Q2D13
Q2D14
Q2D15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
K05
L03
M02
P02
P04
T02
R18
T20
P20
M18
L18
K20
J20
G20
G17
E19
F16
B20
D16
C16
B16
E13
Intel® 450NX PCIset
12-105
12. Electrical Characteristics
Table 12-29: MUX Pin List Sorted by Signal (Continued)
PIN#
Signal
I/O
Driver Type
Driver Strength
Input Pullup/Pulldown
E12
B12
B09
B07
D07
B05
E06
A02
E04
E03
E02
H05
G01
J03
Q2D16
Q2D17
Q2D18
Q2D19
Q2D20
Q2D21
Q2D22
Q2D23
Q2D24
Q2D25
Q2D26
Q2D27
Q2D28
Q2D29
Q2D30
Q2D31
Q2D32
Q2D33
Q2D34
Q2D35
Q3D00
Q3D01
Q3D02
Q3D03
Q3D04
Q3D05
Q3D06
Q3D07
Q3D08
Q3D09
Q3D10
Q3D11
Q3D12
Q3D13
Q3D14
Q3D15
Q3D16
Q3D17
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
K03
L01
M01
P01
T01
U01
T19
N16
M16
M19
L20
J17
J16
H16
E20
D20
E17
E16
C17
A18
A17
C14
C13
A12
12-106
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-29: MUX Pin List Sorted by Signal (Continued)
PIN#
Signal
I/O
Driver Type
Driver Strength
Input Pullup/Pulldown
A09
A07
A05
A04
D05
E05
D03
C01
D01
G03
J05
Q3D18
Q3D19
Q3D20
Q3D21
Q3D22
Q3D23
Q3D24
Q3D25
Q3D26
Q3D27
Q3D28
Q3D29
Q3D30
Q3D31
Q3D32
Q3D33
Q3D34
Q3D35
TCK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
OD
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
J02
K01
M04
M05
N05
P05
T03
C11
C10
A10
E10
E11
A08
A11
A13
B04
B08
B13
B17
F04
F06
F14
F15
F17
G06
H01
H02
TDI
I
TDO
O
14ma
TMS
I
LVTTL
LVTTL
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
TRST#
VCC
I
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Intel® 450NX PCIset
12-107
12. Electrical Characteristics
Table 12-29: MUX Pin List Sorted by Signal (Continued)
PIN#
Signal
I/O
Driver Type
Driver Strength
Input Pullup/Pulldown
H19
H20
N19
N20
P15
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCA
VREF
VREF
VTT
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Analog
Analog
Power
Power
Power
R04
R06
R07
R15
R17
W08
W13
W17
D02
D06
D10
D11
D15
D19
K04
K17
L04
L17
N01
N02
U02
U06
U10
U11
U15
U19
W04
T10
V05
V16
W07
W14
W18
I
I
VTT
VTT
12-108
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-29: MUX Pin List Sorted by Signal (Continued)
PIN#
Signal
I/O
Driver Type
Driver Strength
Input Pullup/Pulldown
U05
U09
U12
U16
W03
Y11
T11
VTT
Power
Power
Power
Power
Power
AGTL+
AGTL+
VTT
VTT
VTT
VTT
WDEVT#
WDME#
I
I
Table 12-30: RCG Pin List Sorted by Signal
Pin#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
N05
N03
P02
P01
P04
P03
R03
T02
T01
T04
T03
U01
V02
V01
J20
ADDRA00
ADDRA01
ADDRA02
ADDRA03
ADDRA04
ADDRA05
ADDRA06
ADDRA07
ADDRA08
ADDRA09
ADDRA10
ADDRA11
ADDRA12
ADDRA13
ADDRB00
ADDRB01
ADDRB02
ADDRB03
ADDRB04
ADDRB05
ADDRB06
ADDRB07
ADDRB08
ADDRB09
ADDRB10
ADDRB11
ADDRB12
ADDRB13
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
J19
J18
J17
J16
G20
G19
H18
H16
F20
G18
G17
E20
F18
Intel® 450NX PCIset
12-109
12. Electrical Characteristics
Table 12-30: RCG Pin List Sorted by Signal (Continued)
Pin#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
C03
E04
D03
C02
E03
C01
F03
E02
D01
G04
E01
G03
G02
F01
C14
A14
C13
A12
B12
C12
D12
E12
A11
C11
E11
E10
C10
A10
V15
T12
V12
W12
T18
Y13
K01
H05
K03
J02
ADDRC00
ADDRC01
ADDRC02
ADDRC03
ADDRC04
ADDRC05
ADDRC06
ADDRC07
ADDRC08
ADDRC09
ADDRC10
ADDRC11
ADDRC12
ADDRC13
ADDRD00
ADDRD01
ADDRD02
ADDRD03
ADDRD04
ADDRD05
ADDRD06
ADDRD07
ADDRD08
ADDRD09
ADDRD10
ADDRD11
ADDRD12
ADDRD13
AVWP#
O
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
AGTL+
AGTL+
AGTL+
AGTL+
LVTTL
AGTL+
LVTTL
LVTTL
LVTTL
LVTTL
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
55ma
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
BANK0#
BANK1#
I
BANK2#
I
BANKID#
CARD#
I
Requires external pull-up
I
CASAA0#
CASAA1#
CASAB0#
CASAB1#
O
O
O
O
10ma
10ma
10ma
10ma
12-110
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-30: RCG Pin List Sorted by Signal (Continued)
Pin#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
H03
J05
CASAC0#
CASAC1#
CASAD0#
CASAD1#
CASBA0#
CASBA1#
CASBB0#
CASBB1#
CASBC0#
CASBC1#
CASBD0#
CASBD1#
CASCA0#
CASCA1#
CASCB0#
CASCB1#
CASCC0#
CASCC1#
CASCD0#
CASCD1#
CASDA0#
CASDA1#
CASDB0#
CASDB1#
CASDC0#
CASDC1#
CASDD0#
CASDD1#
CMND0#
CMND1#
CRES0
O
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
AGTL+
AGTL+
Analog
Analog
AGTL+
LVTTL
LVTTL
Power
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
0
K05
J03
M16
N18
M19
M17
P18
T20
P19
R18
A03
D07
C07
A05
B05
B09
C08
B07
D16
A19
C18
D18
A18
B20
C19
B18
Y12
T11
V04
V03
V11
U18
T19
A01
A06
A15
I
I
I
CRES1
I
CSTB#
I
DR50H#
DR50T#
I
I
GND
GND
Power
GND
Power
Intel® 450NX PCIset
12-111
12. Electrical Characteristics
Table 12-30: RCG Pin List Sorted by Signal (Continued)
Pin#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
A20
B02
B06
B10
B11
B15
B19
F02
F19
H04
H17
J09
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
J10
J11
J12
N04
N17
R01
R02
R19
R20
W06
W10
W11
W15
W19
Y01
Y06
Y15
Y20
D04
D08
D13
D17
K02
K09
K10
K11
12-112
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-30: RCG Pin List Sorted by Signal (Continued)
Pin#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
K12
K19
L02
L09
L10
L11
L12
L19
M09
M10
M11
M12
U04
U08
U13
U17
W02
Y14
V10
Y16
T15
V09
W09
T08
V08
Y08
T07
U07
V07
Y07
V06
W05
Y05
Y04
Y03
Y09
T17
P16
GND
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
AGTL+
2.5V
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GRCMPLT#
HCLKIN
LDSTB#
LRD#
I/O
55ma
I
O
O
I
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
Power
55ma
55ma
MA00#
MA01#
MA02#
MA03#
MA04#
MA05#
MA06#
MA07#
MA08#
MA09#
MA10#
MA11#
MA12#
MA13#
MRESET#
VCC
I
I
I
I
I
I
I
I
I
I
I
I
I
I
N/C
Intel® 450NX PCIset
12-113
12. Electrical Characteristics
Table 12-30: RCG Pin List Sorted by Signal (Continued)
Pin#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
R05
R16
T05
T06
T09
T13
T16
E05
E06
E07
E08
E09
E14
E15
E16
F05
F16
G05
G16
N16
P05
Y10
C09
D09
D20
E17
E18
E19
G01
W1
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
VCC
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
PHIT#
RASAA0#
Power
W16
W20
Y02
U03
Y17
Y19
V14
L01
O
AGTL+
LVTTL
55ma
10ma
O
12-114
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-30: RCG Pin List Sorted by Signal (Continued)
Pin#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
M02
M01
M03
L03
M04
L05
M05
L18
L16
M18
K16
L20
K18
M20
K20
A02
B01
A04
B03
C05
C04
C06
D05
C15
E13
C16
D14
B16
B14
A17
A16
V13
U14
Y11
V18
V20
V19
Y18
RASAA1#
RASAB0#
RASAB1#
RASAC0#
RASAC1#
RASAD0#
RASAD1#
RASBA0#
RASBA1#
RASBB0#
RASBB1#
RASBC0#
RASBC1#
RASBD0#
RASBD1#
RASCA0#
RASCA1#
RASCB0#
RASCB1#
RASCC0#
RASCC1#
RASCD0#
RASCD1#
RASDA0#
RASDA1#
RASDB0#
RASDB1#
RASDC0#
RASDC1#
RASDD0#
RASDD1#
RCMPLT#
RHIT#
O
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
AGTL+
AGTL+
AGTL+
LVTTL
LVTTL
OD
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
55ma
55ma
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
ROW#
TCK
I
TDI
I
TDO
O
I
14ma
TMS
LVTTL
Intel® 450NX PCIset
12-115
12. Electrical Characteristics
Table 12-30: RCG Pin List Sorted by Signal (Continued)
Pin#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
V17
D11
D15
D19
K04
K17
L04
L17
N01
N02
U02
U06
U10
U11
U15
U19
U20
W04
A08
A13
B04
B08
B13
B17
F04
TRST#
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
I
LVTTL
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
F06
F14
F15
F17
G06
H01
H02
H19
H20
N19
N20
P15
R04
12-116
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-30: RCG Pin List Sorted by Signal (Continued)
Pin#
Signal
I/O
Driver Type
Driver Strength
Internal Pullup/Pulldown
R06
R07
R15
R17
W08
W13
W17
D02
D06
D10
T10
V05
V16
W07
W14
W18
U05
U09
U12
U16
W03
T14
J01
VCC
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Analog
Analog
Power
Power
Power
Power
Power
Power
Power
Power
AGTL+
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCA
VREF
VREF
VTT
I
I
VTT
VTT
VTT
VTT
VTT
VTT
VTT
WDME#
WEAA#
WEAB#
WEBA#
WEBB#
WECA#
WECB#
WEDA#
WEDB#
O
O
O
O
O
O
O
O
O
55ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
10ma
J04
P17
P20
A07
A09
C17
C20
Intel® 450NX PCIset
12-117
12. Electrical Characteristics
12.9.3 Package information
12.9.3.1
324 BGA Package Information
NOTE:
Measurements in millimeters
Figure 12-15: 324 BGA Dimension Top View
12-118
Intel® 450NX PCIset
12.9 Mechanical Specifications
Figure 12-16: 324 BGA Dimensions Bottom View
Intel® 450NX PCIset
12-119
12. Electrical Characteristics
12.9.3.2
540 PBGA Package Information
12-120
Intel® 450NX PCIset
12.9 Mechanical Specifications
Table 12-31: 540 PBGA dimensions
Package Dimensions
Packages
540 LD
Symbol
Min
Max
A
A
3.59
0.40
4.10
0.70
1
2
A
0.95
1.10
b
0.60
2.00
42.30
-
0.90
c
2.30
D
D
42.70
27.70
1
E
42.30
-
42.70
27.70
E
e
1
1.27
540
N
S
1.56 REF
1
NOTE: Measurement in millimeters
Intel® 450NX PCIset
12-121
12. Electrical Characteristics
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Bottom View
Figure 12-17: 540 PBGA Pin Grid
12-122
Intel® 450NX PCIset
UNITED STATES, Intel Corporation
2200 Mission College Blvd., P.O. Box 58119, Santa Clara, CA 95052-8119
Tel: +1 408 765-8080
JAPAN, Intel Japan K.K.
5-6 Tokodai, Tsukuba-shi, Ibaraki-ken 300-26
Tel: + 81-29847-8522
FRANCE, Intel Corporation S.A.R.L.
1, Quai de Grenelle, 75015 Paris
Tel: +33 1-45717171
UNITED KINGDOM, Intel Corporation (U.K.) Ltd.
Pipers Way, Swindon, Wiltshire, England SN3 1RJ
Tel: +44 1-793-641440
GERMANY, Intel GmbH
Dornacher Strasse 1
85622 Feldkirchen/ Muenchen
Tel: +49 89/99143-0
HONG KONG, Intel Semiconductor Ltd.
32/F Two Pacific Place, 88 Queensway, Central
Tel: +852 2844-4555
CANADA, Intel Semiconductor of Canada, Ltd.
190 Attwell Drive, Suite 500
Rexdale, Ontario M9W 6H8
Tel: +416 675-2438
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