325119-001_技术文档

Intel® Xeon® Processor E7-

8800/4800/2800 Product Families

Datasheet Volume 1 of 2

April 2011

Reference Number: 325119-001

®

L

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED,

BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS

PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER,

AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING

LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY

PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving,

life sustaining, critical control or safety systems, or in nuclear facility applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

The Intel® Xeon® Processor E7-8800/4800/2800 Product Families may contain design defects or errors known as errata, which

may cause the product to deviate from published specifications. Current characterized errata are available upon request.

Throughout this document, Intel® Xeon® Processor E7-8800/4800/2800 Product Families will be referred to as the Intel® Xeon®

E7-8800/4800/2800 Product Families Processor when used in referring to a singular processor.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel

reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future

changes to them. The information here is subject to change without notice. Do not finalize a design with this information.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained

by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com/design/literature.htm

64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device

®

drivers and applications enabled for Intel 64 architecture. Performance will vary depending on your hardware and software

configurations. Consult with your system vendor for more information. For more information, visit

http://www.intel.com/info/em64t.

Intel® AES-NI requires a computer system with an AES-NI enabled processor, as well as non-Intel software to execute the

instructions in the correct sequence. AES-NI is available on select Intel® processors. For availability, consult your reseller or

system manufacturer. For more information, see http://software.intel.com/en-us/articles/intel-advanced-encryption-standard-

instructions-aes-ni/

Enhanced Intel SpeedStep Technology: See the Processor Spec Finder at http://ark.intel.com or contact your Intel representative

for more information.

Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting

operating system. Check with your PC manufacturer to determine whether your system delivers this functionality. For more

information, visit http://www.intel.com/technology/xdbit/index.htm

Intel® Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor

(VMM) and for some uses, certain computer system software enabled for it. Functionality, performance or other benefits will vary

depending on hardware and software configurations and may require a BIOS update. Software applications may not be compatible

with all operating systems. Please check with your application vendor.

Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family,

not across different processor families. Go to: http://www.intel.com/products/processor_number

Intel® Turbo Boost Technology requires a PC with a processor with Intel® Turbo Boost Technology capability. Intel Turbo Boost

Technology performance varies depending on hardware, software and system configuration. Consult your PC manufacturer on

whether your system delivers Intel Turbo Boost Technology. For more information, visit

http://www.intel.com/technology/turboboost

Intel, Intel Xeon, the Intel logo and Intel SpeedStep are trademarks or registered trademarks of Intel Corporation in the United

States and other countries.

2

I C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I C bus/protocol and was developed

2

by Intel. Implementations of the I C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and

North American Philips Corporation.

*Other names and brands may be claimed as the property of others.

2

Datasheet Volume 1 of 2

Contents

1

Introduction..............................................................................................................9

1.1

1.2

1.3

1.4

Terminology .......................................................................................................9

References ....................................................................................................... 11

State of Data.................................................................................................... 11

Statement of Volatility ....................................................................................... 11

2

Electrical Specifications........................................................................................... 13

2.1

2.2

2.3

2.4

2.5

Processor Maximum Ratings ............................................................................... 13

Socket Voltage Identification............................................................................... 14

Signal Groups................................................................................................... 19

Processor DC Specifications ................................................................................ 21

Intel^®QPI and Intel^®Scalable Memory Interconnect (Intel^®SMI)

Interface Differential Signaling............................................................................ 26

2.5.1 Intel QPI Signaling Specifications ............................................................. 27

2.5.2 Intel QPI Electrical Specifications.............................................................. 30

2.5.3 Intel SMI Signaling Specifications ............................................................. 34

2.5.4 Intel SMI Transmitter and Receiver Specifications....................................... 34

Platform Environmental Control Interface (PECI) DC Specifications........................... 40

2.6.1 DC Characteristics.................................................................................. 41

2.6.2 Input Device Hysteresis .......................................................................... 41

DC Specifications .............................................................................................. 42

AC Specifications............................................................................................... 43

Processor AC Timing Waveforms ......................................................................... 49

2.6

2.7

2.8

2.9

2.10 Flexible Motherboard Guidelines .......................................................................... 55

2.11 Reserved (RSVD) or Unused Signals .................................................................... 55

2.12 Test Access Port Connection ............................................................................... 55

2.13 Mixing Processors.............................................................................................. 55

2.14 Processor SPD Interface..................................................................................... 55

3

Processor Package Mechanical Specifications.......................................................... 57

3.1

Package Mechanical Specifications....................................................................... 57

3.1.1 Package Mechanical Drawing.................................................................... 58

3.1.2 Processor Component Keep-Out Zones...................................................... 61

3.1.3 Package Loading Specifications ................................................................ 61

3.1.4 Package Handling Guidelines.................................................................... 61

3.1.5 Package Insertion Specifications............................................................... 61

3.1.6 Processor Mass Specification.................................................................... 62

3.1.7 Processor Materials................................................................................. 62

3.1.8 Processor Markings................................................................................. 62

3.1.9 Processor Land Coordinates..................................................................... 63

4

Pin Listing ............................................................................................................... 65

4.1

Processor Package Bottom Land Assignments........................................................ 65

4.1.1 Processor Pin List, Sorted by Socket Name ................................................ 65

4.1.2 Processor Pin List, Sorted by Land Number ................................................ 85

5

6

Signal Definitions .................................................................................................. 105

Thermal Specifications .......................................................................................... 111

6.1

6.2

Package Thermal Specifications......................................................................... 111

6.1.1 Thermal Specifications .......................................................................... 111

6.1.2 Thermal Metrology ............................................................................... 117

Processor Thermal Features.............................................................................. 118

6.2.1 Thermal Monitor Features...................................................................... 118

6.2.2 Intel^®Thermal Monitor 1 ...................................................................... 118

Datasheet Volume 1 of 2

3

6.2.3 Intel Thermal Monitor 2.........................................................................118

6.2.4 On-Demand Mode.................................................................................119

6.2.5 PROCHOT_N Signal...............................................................................120

6.2.6 FORCE_PR_N Signal..............................................................................120

6.2.7 THERMTRIP_N Signal ............................................................................121

6.2.8 THERMALERT_N Signal..........................................................................121

Platform Environment Control Interface (PECI) ....................................................121

6.3.1 PECI Client Capabilities..........................................................................122

6.3.2 Client Command Suite...........................................................................123

6.3.3 Multi-Domain Commands.......................................................................138

6.3.4 Client Responses ..................................................................................138

6.3.5 Originator Responses ............................................................................139

6.3.6 Temperature Data ................................................................................140

6.3.7 Client Management...............................................................................141

6.3

7

Features ................................................................................................................145

7.1

7.2

Introduction....................................................................................................145

Clock Control and Low Power States...................................................................146

7.2.1 Processor C-State Power Specifications....................................................146

Sideband Access to Processor Information ROM via SMBus....................................146

7.3.1 Processor Information ROM....................................................................146

7.3.2 Scratch EEPROM...................................................................................148

7.3.3 PIROM and Scratch EEPROM Supported SMBus Transactions.......................149

SMBus Memory Component Addressing...............................................................149

Managing Data in the PIROM.............................................................................150

7.5.1 Header................................................................................................150

7.5.2 Processor Data.....................................................................................154

7.5.3 Processor Core Data..............................................................................156

7.5.4 Processor Uncore Data ..........................................................................159

7.5.5 Package Data.......................................................................................164

7.5.6 Part Number Data.................................................................................165

7.5.7 Thermal Reference Data ........................................................................168

7.5.8 Feature Data........................................................................................169

7.5.9 Other Data ..........................................................................................171

7.5.10 Checksums ..........................................................................................172

7.3

7.4

7.5

8

Debug Tools Specifications ....................................................................................173

8.1

Logic Analyzer Interface ...................................................................................173

8.1.1 Mechanical Considerations .....................................................................173

8.1.2 Electrical Considerations........................................................................173

4

Datasheet Volume 1 of 2

Figures

2-1

VCC Static and Transient Tolerance ..................................................................... 24

Vcache Static and Transient Tolerance ................................................................. 25

Overshoot Example Waveform ............................................................................ 26

Active ODT for a Differential Link Example............................................................ 26

Validation Topology for Testing Specifications of the Reference Clock ....................... 27

Differential Waveform Measurement Points........................................................... 27

Setup for Validating Standalone Tx Voltage and Timing Parameters.......................... 28

Setup for Validating Tx + Worst-Case Interconnect Specifications ............................ 29

Required Receiver Input Eye (Differential) Showing Minimum Voltage Specs ............. 39

2-2

2-3

2-4

2-5

2-6

2-7

2-8

2-9

2-10 Input Device Hysteresis ..................................................................................... 42

2-11 RESET_N SEtup/Hold Time for Deterministic RESET_N Deassertion .......................... 45

2-12 THERMTRIP_N Power Down Sequence.................................................................. 45

2-13 VID Step Times................................................................................................. 46

2-14 SMBus Timing Waveform.................................................................................... 47

2-15 SMBus Valid Delay Timing Waveform ................................................................... 47

2-16 FLASHROM Timing Waveform.............................................................................. 48

2-17 TAP Valid Delay Timing Waveform ....................................................................... 48

2-18 Test Reset (TRST_N), Force_PR_N, RESET_N and PROCHOT_N Pulse Width

Waveform ........................................................................................................ 49

2-19 Intel QPI System Interface Electrical Test Setup for Validating

Standalone TX Voltage and Timing Parameters...................................................... 49

2-20 Intel QPI System Interface Electrical Test Setup for Validating

TX + Worst-Case Interconnect Specifications ........................................................ 50

2-21 Differential Clock Waveform................................................................................ 50

2-22 Differential Clock Crosspoint Specification............................................................. 51

2-23 System Common Clock Valid Delay Timing Waveform ............................................ 51

2-24 Differential Measurement Point for Ringback ......................................................... 51

2-25 Differential Measurement Points for Rise and Fall time............................................ 52

2-26 Single-Ended Measurement Points for Absolute Cross Point and Swing...................... 52

2-27 Single-Ended Measurement Points for Delta Cross Point.......................................... 52

2-28 Voltage Sequence Timing Requirements ............................................................... 53

2-29 VID Step Times and Vcc Waveforms .................................................................... 54

3-1

3-2

3-3

3-4

3-5

6-1

6-2

6-3

6-4

6-5

6-6

6-7

6-8

6-9

Processor Package Assembly Sketch .................................................................... 57

Processor Package Drawing (Sheet 1 of 2)............................................................ 59

Processor Package Drawing (Sheet 2 of 2)............................................................ 60

Processor Top-Side Markings .............................................................................. 62

Processor Land Coordinates and Quadrants, Top View ............................................ 63

130W TDP Processor Thermal Profile.................................................................. 113

105W TDP Processor Thermal Profile.................................................................. 114

95W TDP Processor Thermal Profile.................................................................... 116

Case Temperature (TCASE) Measurement Location .............................................. 117

Intel® Thermal Monitor 2 Frequency and Voltage Ordering ................................... 119

Ping()............................................................................................................ 123

Ping() Example ............................................................................................... 123

GetDIB()........................................................................................................ 124

Device Info Field Definition............................................................................... 124

6-10 Revision Number Definition............................................................................... 125

6-11 GetTemp() ..................................................................................................... 125

6-12 GetTemp() Example......................................................................................... 126

6-13 PCI Configuration Address ................................................................................ 126

6-14 PCIConfigRd()................................................................................................. 127

Datasheet Volume 1 of 2

5

6-15 PCIConfigWr().................................................................................................128

6-16 Thermal Status Word .......................................................................................131

6-17 Thermal Data Configuration Register ..................................................................132

6-18 ACPI T-state Throttling Control Read / Write Definition .........................................133

6-19 MbxSend() Command Data Format ....................................................................134

6-20 MbxSend()......................................................................................................135

6-21 MbxGet()........................................................................................................136

6-22 Temperature Sensor Data Format ......................................................................140

6-23 PECI Power-up Timeline....................................................................................142

7-1

Logical Schematic of Intel^®Xeon^®Processor E7-8800/4800/2800

Product Families Package..................................................................................145

Tables

1-1

References........................................................................................................11

Processor Absolute Maximum Ratings...................................................................13

Voltage Identification Definition ...........................................................................15

Signal Groups ...................................................................................................20

Signals with RTT................................................................................................21

Voltage and Current Specifications.......................................................................21

Processor Vcc Static and Transient Tolerance.........................................................23

Processor VccCache Static and Transient Tolerance ................................................24

VCC and Vcache overshoot Specification ...............................................................25

System Clock Specifications ................................................................................27

2-1

2-2

2-3

2-4

2-5

2-6

2-7

2-8

2-9

2-10 Link Speed Independent Specifications .................................................................29

2-11 Clock Frequency Table........................................................................................30

2-12 Parameter Values for Intel® QPI Phy1 Channel at 1/4 RefClk Frequency ...................31

2-13 Parameter Values for Intel QPI Channel at 4.8 GT/s................................................32

2-14 Parameter Values for Intel QPI at 6.4 GT/s............................................................33

2-15 Parameter Values for Intel SMI at 6.4 GT/s and lower.............................................35

2-16 PLL Specification for TX and RX ...........................................................................36

2-17 Transmitter Voltage Swing..................................................................................37

2-18 Transmitter De-emphasis (Swing Setting 110: Large).............................................37

2-19 Transmitter De-emphasis (Swing Setting 100: Medium)..........................................37

2-20 Transmitter De-emphasis (Swing Setting 010: Small).............................................37

2-21 Summary of Differential Transmitter Output Specifications ......................................38

2-22 Summary of Differential Receiver Input Specifications.............................................39

2-23 PECI DC Electrical Limits.....................................................................................41

2-24 TAP, Strap Pins, Error, Powerup, RESET, Thermal, VID Signal Group DC

Specifications....................................................................................................42

2-25 Miscellaneous DC Specifications...........................................................................43

2-26 System Reference Clock AC Specifications.............................................................43

2-27 Miscellaneous GTL AC Specifications.....................................................................44

2-28 VID Signal Group AC Specifications ......................................................................45

2-29 SMBus and SPDBus Signal Group AC Timing Specifications......................................46

2-30 FLASHROM Signal Group AC Timing Specifications..................................................47

2-31 TAP Signal Group AC Timing Specifications............................................................48

3-1

3-2

3-3

3-4

4-1

Processor Loading Specifications..........................................................................61

Package Handling Guidelines...............................................................................61

Processor Materials ............................................................................................62

Mark Content ....................................................................................................62

Pin List, Sorted by Socket Name ..........................................................................65

6

Datasheet Volume 1 of 2

4-2

5-1

6-1

6-2

6-3

6-4

6-5

6-6

6-7

6-8

6-9

Pin List, Sorted by land Number .......................................................................... 85

Signal Definitions ............................................................................................ 105

Processor Thermal Specifications....................................................................... 112

130W TDP Processor Thermal Profile Table ......................................................... 113

105W TDP Processor Thermal Profile Table ......................................................... 115

95W TDP Processor Thermal Profile Table ........................................................... 116

Summary of Processor-specific PECI Commands.................................................. 122

GetTemp() Response Definition......................................................................... 126

PCIConfigRd() Response Definition .................................................................... 127

PCIConfigWr() Response Definition .................................................................... 129

Mailbox Command Summary ............................................................................ 129

6-10 Counter Definition ........................................................................................... 131

6-11 ACPI T-state Duty Cycle Definition..................................................................... 132

6-12 MbxSend() Response Definition......................................................................... 135

6-13 MbxGet() Response Definition........................................................................... 136

6-14 Domain ID Definition ....................................................................................... 138

6-15 Multi-Domain Command Code Reference ............................................................ 138

6-16 Completion Code Pass/Fail Mask........................................................................ 139

6-17 Device Specific Completion Code (CC) Definition.................................................. 139

6-18 Originator Response Guidelines......................................................................... 140

6-19 Error Codes and Descriptions ............................................................................ 141

6-20 PECI Client Response During Power-Up (During ‘Data Not Ready’) ......................... 141

6-21 Power Impact of PECI Commands vs. C-states .................................................... 143

6-22 PECI Client Response During S1........................................................................ 143

7-1

7-2

7-3

7-4

7-5

Processor C-State Power Specifications .............................................................. 146

Read Byte SMBus Packet.................................................................................. 149

Write Byte SMBus Packet ................................................................................. 149

Memory Device SMBus Addressing..................................................................... 150

128-Byte ROM Checksum Values....................................................................... 172

Datasheet Volume 1 of 2

7

Revision History

Document

Number

Revision

Number

Description

Date

April 2011

325119

001

•

Public release

§

8

Datasheet Volume 1 of 2

Introduction

1 Introduction

The Intel^®Xeon^®Processor E7-8800/4800/2800 Product Families are a next-

generation Intel^®Xeon^®multi-core MP family processor. The processor uses Intel^®

QuickPath Interconnect (Intel^®QPI) technology, implementing up to four high-speed

serial point-to-point links. It is optimized for MP configurations targeted at enterprise

and technical computing applications, delivering server-class RAS and performance.

Intel Xeon Processor E7-8800/4800/2800 Product Families are multi-core processors,

based on 32-nm process technology. The processors feature Intel QuickPath

Interconnect point-to-point links capable of up to 6.4 GT/s, up to 30 MB of shared

cache, and an integrated memory controller. The processors support all the existing

Streaming SIMD Extensions 2 (SSE2), Streaming SIMD Extensions 3 (SSE3) and

Streaming SIMD Extensions 4 (SSE4). The processors support several Advanced

Technologies: Execute Disable Bit, Intel^®64 technology, Enhanced Intel SpeedStep^®

technology, Intel^®Virtualization technology (Intel^®VT), and Simultaneous Multi-

Threading.

®

Feature

Cache Sizes

Intel Xeon Processor E7-8800/4800/2800 Product Families

Instruction Cache (L1) = 32 KB/core (I) and16 KB/core (D)

Data Cache (L2) = 256 KB/core

Last Level Cache (L3) = 30 MB shared among cores

Data Transfer Rate

Multi-Core Support

Up to four full-width Intel QuickPath Interconnect links, up to 6.4 GT/s in

each direction

Up to 10 cores per processor

Multiple Processor Support Dependent on SKU, and supporting silicon. Minimum of two CPUs.

Package

1567-land FCLGA

1.1

Terminology

A ‘_N’ after a signal name refers to an active low signal, indicating that a signal is in the

asserted state when driven to a low level. For example, when RESET_N is low (that is,

when RESET_N is asserted), a reset has been requested. Conversely, when TCK is high

(that is, when TCK is asserted), a test clock request has occurred.

• Enhanced Intel SpeedStep technology — Enhanced Intel SpeedStep technology

allows the O/S to reduce power consumption when performance is not needed.

• Eye Definitions — The eye at any point along the data channel is defined to be the

creation of overlapping of a large number of UI of the data signal and timing width

measured with regards to the edges of a separate clock signal at any other point.

Each differential signal pair by combining the D+ and D- signals produces a signal

eye. A _DN and _DP after a signal name refers to a differential pair.

• FCLGA-1567 — The Intel Xeon Processor E7-8800/4800/2800 Product Families

are available in a Flip-Chip Land Grid Array (FC-LGA) package, consisting of 10

processor cores mounted on a pinned substrate with an integrated heat spreader

(IHS).

• Functional Operation — Refers to the normal operating conditions in which all

processor specifications, including DC, AC, system bus, signal quality, mechanical,

and thermal, are satisfied.

Datasheet Volume 1 of 2

9

Introduction

• Integrated Heat Spreader (IHS) — A component of the processor package used

to enhance the thermal performance of the package. Component thermal solutions

interface with the processor at the IHS surface.

• Intel^®QuickPath Interconnect (Intel^®QPI) — Intel QuickPath Interconnect is

a cache-coherent, links-based interconnect specification for Intel^®processor,

chipset, and I/O bridge components.

• Jitter — Any timing variation of a transition edge or edges from the defined UI.

• MP — Multi-processor system consisting of more than two processors.

• OEM — Original Equipment Manufacturer.

• Processor Information ROM (PIROM) — A memory device located on the

processor and accessible via the System Management Bus (SMBus) which contains

information regarding the processor’s features. This device is shared with the

Scratch EEPROM, is programmed during manufacturing, and is write-protected.

— Scratch EEPROM (Electrically Erasable, Programmable Read-Only

Memory) — A memory device located on the processor and addressable via

the SMBus which can be used by the OEM to store information useful for

system management.

• SMBus — System Management Bus. A two-wire interface through which simple

system and power management related devices can communicate with the rest of

the system. It is based on the principals of the operation of the I²C* two-wire serial

bus developed by Phillips Semiconductor. SMBus is a subset of the I²C bus/protocol

developed by Intel. Implementations of the I²C bus/protocol or the SMBus bus/

protocol may require licensing from various entities, including, but not restricted to,

Philips Electronics N.V. and North American Philips Corporation.

• Storage Conditions — Refers to a non-operational state. The processor may be

installed in a platform, in a tray, or loose. Processors may be sealed in packaging or

exposed to free air. Under these conditions, processor pins should not be connected

to any supply voltages, have any I/Os biased, or receive any clocks.

• Intel^®Xeon^®Processor E7-8800/4800/2800 Product Families — The entire

product, including processor core, die, substrate and integrated heat spreader

(IHS).

• Unit Interval (UI) — Intel QPI signaling convention is binary and unidirectional.

In this binary signaling, one bit is sent for every edge of the forwarded clock,

whether it be a rising edge or a falling edge. If a number of edges are collected at

instances t₁, t₂, t_n,...., t_kthen the UI at instance “n” is defined as:

UI _n= t _n- t

n - 1

10

Introduction

1.2

References

Material and concepts available in the following documents may be beneficial when

reading this document:

Table 1-1.

References

Document

Location

325120

Notes

®

Intel Xeon Processor E7-8800/4800/2800 Product Families

Datasheet Volume 2 of 2

1

®

AP-485, Intel Processor Identification and the CPUID Instruction

241618

1

®

Intel 64 and IA-32 Architecture Software Developer's Manual

Volume 1: Basic Architecture

253665

253666

253667

253668

253669

Volume 2A: Instruction Set Reference, A-M

Volume 2B: Instruction Set Reference, N-Z

Volume 3A: System Programming Guide, Part 1

Volume 3B: Systems Programming Guide, Part 2

®

Intel 64 and IA-32 Architectures Optimization Reference Manual

248966

1

®

Intel Virtualization Technology Specification for Directed I/O

D51397-001

Architecture Specification

Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-

Down (EVRD) 11.1 Design Guidelines

321736

1

Notes:

1.

Document is available publicly at http://developer.intel.com.

1.3

1.4

State of Data

The data contained within this document is production data.

Statement of Volatility

No Intel® Xeon® E7-8800/4800/2800 Product Families processors retain any end user

data when powered down and/or when the parts are physically removed from the

socket.

§

Datasheet Volume 1 of 2

11

Introduction

12

Electrical Specifications

2 Electrical Specifications

The Intel Xeon Processor E7-8800/4800/2800 Product Families package pin electrical

specification is outlined in this section. The Intel Xeon E7-8800/4800/2800 Product

Families processor interfaces to other components of the platform via connections

established at Intel^®QuickPath Interconnect (Intel^®QPI), Intel^®Scalable Memory

Interconnect (Intel^®SMI), system management interfaces, power, reset, clock and

debug signals. The electrical characteristics of all such signals, categorized per the I/O

type, are documented in this section.

2.1

Processor Maximum Ratings

Table 2-1 specifies absolute maximum and minimum ratings. Within operational

maximum and minimum limits, functionality and long-term reliability can be expected.

Processor maximum ratings outlined in Table 2-1 are applicable for all Intel Xeon E7-

8800/4800/2800 Product Families processor SKUs.

At conditions outside operational maximum ratings, but within absolute maximum and

minimum ratings, neither functionality nor long-term reliability can be expected. If a

device is returned to conditions within operational maximum and minimum ratings

after having been subjected to conditions outside these limits, but within the absolute

maximum and minimum ratings, the device may be functional, but with its lifetime

degraded depending on exposure to conditions exceeding the functional operation

condition limits.

At conditions exceeding absolute maximum and minimum ratings, neither functionality

nor long-term reliability can be expected. Moreover, if a device is subjected to these

conditions for any length of time, then when returned to conditions within the

functional operating condition limits, it will either not function, or its reliability will be

severely degraded.

Although the processor contains protective circuitry to resist damage from static

electric discharge, precautions should always be taken to avoid high static voltages or

electric fields.

Table 2-1.

Processor Absolute Maximum Ratings (Sheet 1 of 2)

Notes

1, 2

Symbol

Vcc

Parameter

Min

Max

Unit

Processor core supply voltage with

respect to VSS

–0.3

1.42

V

Processor cache voltage with respect

to VSS

–0.3

3.135

1.55

1.89

1.55

3.465

V

CACHE

REG

Processor Analog Supply Voltage with

respect to VSS

Processor Intel QPI I/O Supply

Voltage with respect to VSS

IOC

Processor I/O Supply Voltage for SMI

with respect to VSS

IOF

Processor 3.3V Supply Voltage with

respect to VSS

CC33

Datasheet Volume 1 of 2

13

Electrical Specifications

Table 2-1.

Processor Absolute Maximum Ratings (Sheet 2 of 2)

Notes

Symbol

Parameter

Min

Max

Unit

1, 2

V(ISENSE)

Analog input voltage with respect to

Vss for sensing current consumption

-0.25

1.15

V

T

Processor case temperature

See Chapter 6

–40

See Chapter 6

85

CASE

Processor storage temperature

°C

3, 4

STORAGE

Notes:

1.

For functional operation, all processor electrical, signal quality, mechanical, and thermal specifications must

be satisfied.

2.

3.

Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor.

Storage temperature is applicable to storage conditions only. In this scenario, the processor must not

receive a clock, and no pins can be connected to a voltage bias. Storage within these limits will not affect

the long-term reliability of the device. For functional operation, please refer to the processor case

temperature specifications.

4.

This rating applies to the processor and does not include any packaging or trays.

2.2

Socket Voltage Identification

The VID[7:0], CVID[7:1], and VIO_VID[4:1] pins identify encoding that determine the

voltage to be supplied by the VR to the socket Vcore, Vcache and VIO (the core, cache

& system interface voltages for the Intel Xeon Processor E7-8800/4800/2800 Product

Families processor) voltage regulators. The CoreVID and CacheVID specifications for

the Intel Xeon Processor E7-8800/4800/2800 Product Families processors are defined

by VR 11.1. VIO_VID specifications for the Intel Xeon Processor E7-8800/4800/2800

Product Families processors are defined by VR 11.0.

For CoreVID and CacheVID, individual processor VID values may be calibrated during

manufacturing such that two devices at the same core speed may have different

default VID settings. Furthermore, any Intel Xeon Processor E7-8800/4800/2800

Product Families processor can drive different VID settings during normal operation. For

VIO_VID, all processors of a given stepping will have the same values.

The Voltage Identification (VID) specification for the Intel Xeon Processor E7-8800/

4800/2800 Product Families processor is defined by the Voltage Regulator Module

(VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.1 Design Guidelines. The

voltage set by the VID signals is the reference VR output voltage to be delivered to the

processor Vcc pins. VID signals are CMOS push/pull drivers. Please refer to Table 2-24

for the DC specifications for these signals. A voltage range is provided in Table 2-5 and

changes with frequency. The specifications have been set such that one voltage

regulator can operate with all supported frequencies.

The Intel Xeon Processor E7-8800/4800/2800 Product Families processor uses eight

voltage identification signals, VID[7:0], to support automatic selection of power supply

voltages. Table 2-2 specifies the voltage level corresponding to the state of VID[7:0]. A

‘1’ in this table refers to a high voltage level and a ‘0’ refers to a low voltage level. If

the processor socket is empty (SKTOCC# high), or the voltage regulation circuit cannot

supply the voltage that is requested, the voltage regulator must disable itself. See the

Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.1

Design Guidelines for further details.

The Intel Xeon Processor E7-8800/4800/2800 Product Families processor provides the

ability to operate while transitioning to an adjacent VID and its associated processor

core voltage (Vcc). This will represent a DC shift in the load line. It should be noted that

a low-to-high or high-to-low voltage state change may result in as many VID

transitions as necessary to reach the target core voltage. Transitions above the

14

Datasheet Volume 1 of 2

Electrical Specifications

maximum specified VID are not permitted. Table 2-5 includes VID step sizes and DC

shift ranges. Minimum and maximum voltages must be maintained as shown in

Table 2-6.

The VRM or EVRD utilized must be capable of regulating its output to the value defined

by the new VID. DC specifications for dynamic VID transitions are included in Table 2-5

and Table 2-6, while AC specifications are included in Table 2-28. Refer to the Voltage

Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.1 Design

Guidelines for further details.

The VIO_VID[4:1] pins identify encoding that determine the voltage to be supplied by

the VR 11.1 to the socket Vio voltage regulators. In all cases, when reading from

Table 2-2, assume VID7=0, VID6=1, VID5=0, and VID0=0. Note that all Intel Xeon

Processor E7-8800/4800/2800 Product Families processor SKUs will have the same

setting.

Power source characteristics must be guaranteed to be stable whenever the supply to

the voltage regulator is stable.

Table 2-2.

Voltage Identification Definition (Sheet 1 of 5)

VID7

VID6

VID5

VID4

VID3

VID2

VID1

VID0

V

CC_MAX

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

OFF

1.60000

1.59375

1.58750

1.58125

1.57500

1.56875

1.56250

1.55625

1.55000

1.54375

1.53750

1.53125

1.52500

1.51875

1.51250

1.50625

1.50000

1.49375

1.48750

1.48125

1.47500

1.46875

1.46250

1.45625

1.45000

Datasheet Volume 1 of 2

15

Electrical Specifications

Table 2-2.

Voltage Identification Definition (Sheet 2 of 5)

VID7

VID6

VID5

VID4

VID3

VID2

VID1

VID0

V

CC_MAX

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1.44375

1.43750

1.43125

1.42500

1.41875

1.41250

1.40625

1.40000

1.39375

1.38750

1.38125

1.37500

1.36875

1.36250

1.35625

1.35000

1.34375

1.33750

1.33125

1.32500

1.31875

1.31250

1.30625

1.30000

1.29375

1.28750

1.28125

1.27500

1.26875

1.26250

1.25625

1.25000

1.24375

1.23750

1.23125

1.22500

1.21875

1.21250

1.20625

1.20000

1.19375

1.18750

16

Datasheet Volume 1 of 2

Electrical Specifications

Table 2-2.

Voltage Identification Definition (Sheet 3 of 5)

VID7

VID6

VID5

VID4

VID3

VID2

VID1

VID0

V

CC_MAX

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1.18125

1.17500

1.16875

1.16250

1.15625

1.15000

1.14375

1.13750

1.13125

1.12500

1.11875

1.11250

1.10625

1.10000

1.09375

1.08750

1.08125

1.07500

1.06875

1.06250

1.05625

1.05000

1.04375

1.03750

1.03125

1.02500

1.01875

1.01250

1.00625

1.00000

0.99375

0.98750

0.98125

0.97500

0.96875

0.96250

0.95625

0.95000

0.94375

0.93750

0.93125

0.92500

Datasheet Volume 1 of 2

17

Electrical Specifications

Table 2-2.

Voltage Identification Definition (Sheet 4 of 5)

VID7

VID6

VID5

VID4

VID3

VID2

VID1

VID0

V

CC_MAX

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0.91875

0.91250

0.90625

0.90000

0.89375

0.88750

0.88125

0.87500

0.86875

0.86250

0.85625

0.85000

0.84375

0.83750

0.83125

0.82500

0.81875

0.81250

0.80625

0.80000

0.79375

0.78750

0.78125

0.77500

0.76875

0.76250

0.75625

0.75000

0.74375

0.73750

0.73125

0.72500

0.71875

0.71250

0.70625

0.70000

0.69375

0.68750

0.68125

0.67500

0.66875

0.66250

18

Datasheet Volume 1 of 2

Electrical Specifications

Table 2-2.

Voltage Identification Definition (Sheet 5 of 5)

VID7

VID6

VID5

VID4

VID3

VID2

VID1

VID0

V

CC_MAX

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.65625

0.65000

0.64375

0.63750

0.63125

0.62500

0.61875

0.61250

0.60625

0.60000

0.59375

0.58750

0.58125

0.57500

0.56875

0.56250

0.55625

0.55000

0.54375

0.53750

0.53125

0.52500

0.51875

0.51250

0.50625

0.50000

OFF

Notes:

1.

2.

3.

When the “11111111” VID pattern is observed, or when the SKTOCC# pin is deasserted, the voltage

regulator output should be disabled.

Shading denotes the expected VID range of the Intel Xeon Processor E7-8800/4800/2800 Product Families

processor.

The VID range includes VID transitions that may be initiated by thermal events, Extended HALT state

transitions, higher C-States or Enhanced Intel® SpeedStep technology transitions. The Extended HALT

state must be enabled for the processor to remain within its specifications

Once the VRM/EVRD is operating after power-up, if either the Output Enable signal is de-asserted or a

specific VID off code is received, the VRM/EVRD must turn off its output (the output should go to high

impedance) within 500 ms and latch off until power is cycled. Refer to Voltage Regulator Module (VRM) and

Enterprise Voltage Regulator-Down (EVRD) 11.1 Design Guidelines.

4.

2.3

Signal Groups

The signals are grouped by buffer type and similar characteristics, as listed in

Table 2-3. The buffer type indicates which signaling technology and specifications apply

to the signals. All the differential signals have On Die Termination (ODT) resistors.

There are some signals that do not have ODT and need to be terminated on the board.

The signals which have ODT are listed in Table 2-4.

Datasheet Volume 1 of 2

19

Electrical Specifications

Table 2-3.

Signal Groups (Sheet 1 of 2)

1

Signal Group

Type

Signals

System Reference Clock

Differential

Differential Pair, HSTL

SYSCLK_DP, SYSCLK_DN, SYSCLK_LAI_N,

SYSCLK_LAI

Intel® QPI Interface Signal Groups

Differential

SCiD 2 Input

QPI[3:0]_DRX_D[n/p][19:0],

QPI[3:0]_CLKRX_D[p/n]

SCiD 2 Output

QPI[3:0]_DTX_D[n/p][19:0],

QPI[3:0]_CLKTX_D[p/n]

Intel® SMI Signals

Differential

Inputs

Output

Input

FBD0NBICLK[A/B][P/N]0

FBD1NBICLK[C/D][P/N]0

Differential

TAP

FBD0SBOCLK[A/B][P/N]0

FBD1SBOCLK[C/D][P/N]0

FBD0NBI[A/B][P/N][13:0]

FBD1NBI[C/D][P/N][13:0]

Output

FBD0SBO[A/B][P/N][10:0], FBD1SBO[C/D][P/

N][10:0]

Single ended

GTL

TCK, TDI,TMS, TRST_N

TDO

GTL-Open Drain

PECI

Single ended

SMBus

CMOS

PECI

Single ended

SPD Bus

CMOS

SMBCLK, SMBDAT, SM_WP

SPDCLK, SPDDAT

Single ended

Strap Pins

CMOS I/OD

Single ended

GTL

BOOTMODE[1:0]

SKTID[2:0]

CMOS

Flash ROM Port

Single ended

GTL - OD

FLASHROM_CFG[2:0], FLASHROM_DATI

FLASHROM_CS[3:0]_N, FLASHROM_CLK,

FLASHROM_DATO, FLASHROM_WP_N

ERROR Bus

Single ended

GTL Input, GTL Open Drain

Output

ERROR[0]_N, ERROR[1]_N

Power Up, RESETs

Single ended

CMOS Input

GTL Input

PWRGOOD, VIOPWRGOOD,

RUNBIST, RESET_N

Thermal

Single ended

GTL Input

Force_PR_N

GTL

MEM_Throttle[1]_N,MEM_Throttle[0]_N

PROCHOT_N, THERMTRIP_N

Thermalert_N

GTL-Open Drain

CMOS - Open Drain

20

Datasheet Volume 1 of 2

Electrical Specifications

Table 2-3.

Signal Groups (Sheet 2 of 2)

1

Signal Group

VID

Type

Signals

Single ended

CMOS Output

Open/Ground

VID[7:0], CVID[7:1]

VIO_VID[4:1]

Voltage, and Voltage Regulator

Differential

Power

ISENSE_DN, ISENSE_DP

Single ended

Vcc, VREG, VCACHE, VCACHESENSE,

VCC33,VCORESENSE, VIO, PSI_CACHE_N,PSI_N,

VSSCACHESENSE,VSSCORESENSE,

Debug

Single ended

GTL I/O-OD

MBP[7:0]_N, PRDY_N,PREQ_N

Notes:

1.

See Chapter 5 for signal descriptions.

Table 2-4.

Signals with R_TT

Signals with RTT

•

QPI[3:0]R[P/N]Dat[19:0], QPI[5:4]R[P/N]CLK0, QPI[3:0]T[P/N]Dat[19:0],

QPI[5:4]T[P/N]CLK0

FBD0NBICLK[A/B][P/N]0, FBD1NBICLK[C/D][P/N]0, FBD0SBOCLK[A/B][P/N]0,

FBD1SBOCLK[C/D][P/N]0, FBD0NBI[A/B][P/N][12:0], FBD1NBI[C/D][P/

N][12:0], FBD0SBO[A/B][P/N][9:0], FBD1SBO[C/D][P/N][9:0].

2.4

Processor DC Specifications

Voltage and current specifications are detailed in Table 2-5. For platform planning refer

to Table 2-6, which provides Vcc static and transient tolerances.

Differential SYSCLK specifications are found in Table 2-26. Control Sideband and Test

Access Port (TAP) are listed in Table 2-24.

Table 2-5 through Table 2-24 list the DC specifications for the processor and are valid

only while meeting specifications for case temperature (T_CASEas specified in Chapter 6,

“Thermal Specifications”), clock frequency, and input voltages. Care should be taken to

read all notes associated with each parameter.

Table 2-5.

Voltage and Current Specifications (Sheet 1 of 2)

Voltage

Symbol

Parameter

Min

Typ

Max

Unit

V

Notes 1

4,5

Plane

VID

VCore VID range

for processor core

Launch - FMB

Vcc Load Line

VCache VID range

Vcc for cache

N/A

0.60

1.35

Vcc

V

4,5,6

CC

See Table 2-6

V

Vcc LL

CVID

0.8

mΩ

V

0.7

1.35

4,5

V

See Table 2-7

1.4

V

4,5,7

CACHE

LL

V

Load Line

mΩ

CACHE

Vcc VID step size during a

transition

VID_STEP

N/A

± ±6.25

mV

Datasheet Volume 1 of 2

21

Electrical Specifications

Table 2-5.

Voltage and Current Specifications (Sheet 2 of 2)

Voltage

Plane

Symbol

Parameter

Min

Typ

Max

Unit

Notes 1

V

Total allowable DC load line

shift from VID steps

LLType +/

-15mV

VID_SHIFT

N/A

mV

VIO_VID

Processor I/O supply voltage

1.053

3.135

1.0875

1.8

1.1

1,3

1,2

V

PLL supply voltage (DC + AC

specification)

REG

N/A

V

Vcc33

Package component voltage

IccMax for Vcc33

3.3

3.465

75

Icc_Max

Vcc33

mA

I

for Intel Xeon Processor

CC

CC_MAX

Vcc

Vcache

120

75

18.1

1.5

E7-8800/4800/2800 Product

Families processor 130W

TDP with multiple VID

A

V

IO

V

REG

Launch - FMB

I

for Intel Xeon Processor

CC

Vcc

Vcache

115

70

17.6

1.5

E7-8800/4800/2800 Product

Families processor 105W

TDP with multiple VID

V

IO

V

REG

Launch - FMB

I

for Intel Xeon Processor

CC

Vcc

Vcache

115

70

17.6

1.5

E7-8800/4800/2800 Product

Families processor 95W TDP

with multiple VID

V

IO

V

REG

Launch - FMB

I

Thermal Design Current

(TDC)

CC_TDC

Vcc

Vcache

110

55

16.0

1.3

Intel Xeon Processor E7-

8800/4800/2800 Product

Families processor 130W

TDP

V

A

IO

V

REG

Launch - FMB

Thermal Design Current

(TDC)

Intel Xeon Processor E7-

8800/4800/2800 Product

Families processor 105W

TDP

Vcc

Vcache

90

50

16.0

1.3

V

A

IO

V

REG

Launch - FMB

Thermal Design Current

(TDC)

Intel Xeon Processor E7-

8800/4800/2800 Product

Families processor 95W TDP

Vcc

Vcache

85

50

15.5

1.3

V

IO

V

REG

Launch - FMB

PSI TDC

Thermal Design Current

Launch - FMB

130W

105W

95W

22

25

21

A

PSI_CACHE

TDC

Thermal Design Current

Launch - FMB

130W

105W

95W

45

Notes:

1.

2.

3.

4.

DC for a power supply is defined as any variation less than 1 MHz.

±1% tolerance

±1% ripple, ±2% total as measured at VR remote sense point

Unless otherwise noted, all specifications in this table apply to all processors. These specifications are

based on pre-silicon characterization and will be updated as further data becomes available.

Individual processor VID values may be calibrated during manufacturing such that two devices at the same

speed may have different settings.

5.

6.

The V voltage specification requirements are measured across vias on the platform for the VCORESENSE

CC

and VSSCORESENSE pins close to the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum

22

Datasheet Volume 1 of 2

Electrical Specifications

probe capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the probe

should be less than 5 mm. Ensure external noise from the system is not coupled in the scope probe.

The V voltage specification requirements are measured across vias on the platform for the

7.

CACHE

VCACHESENSE and VSSCACHESENSE pins close to the socket with a 100 MHz bandwidth oscilloscope, 1.5

pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on

the probe should be less than 5 mm. Ensure external noise from the system is not coupled in the scope

probe.

Table 2-6.

Processor Vcc Static and Transient Tolerance

I

(A)

Vcc

(V)

Vcc

(V)

Vcc (V)

_Min

Notes

CC

_Max

_Typ

0

VID - 0.000

VID - 0.004

VID - 0.008

VID - 0.012

VID - 0.016

VID - 0.020

VID - 0.024

VID - 0.028

VID - 0.032

VID - 0.036

VID - 0.040

VID - 0.044

VID - 0.048

VID - 0.052

VID - 0.056

VID - 0.060

VID - 0.064

VID - 0.068

VID - 0.072

VID - 0.076

VID - 0.080

VID - 0.084

VID - 0.088

VID - 0.092

VID - 0.096

VID - 0.100

VID - 0.104

VID - 0.108

VID - 0.112

VID - 0.116

VID - 0.120

VID - 0.015

VID - 0.019

VID - 0.023

VID - 0.027

VID - 0.031

VID - 0.035

VID - 0.039

VID - 0.043

VID - 0.047

VID - 0.051

VID - 0.055

VID - 0.059

VID - 0.063

VID - 0.067

VID - 0.071

VID - 0.075

VID - 0.079

VID - 0.083

VID - 0.087

VID - 0.091

VID - 0.095

VID - 0.099

VID - 0.103

VID - 0.107

VID - 0.111

VID - 0.115

VID - 0.119

VID - 0.123

VID - 0.127

VID - 0.131

VID - 0.135

VID - 0.030

VID - 0.034

VID - 0.038

VID - 0.042

VID - 0.046

VID - 0.050

VID - 0.054

VID - 0.058

VID - 0.062

VID - 0.066

VID - 0.070

VID - 0.074

VID - 0.078

VID - 0.082

VID - 0.086

VID - 0.090

VID - 0.094

VID - 0.098

VID - 0.102

VID - 0.106

VID - 0.110

VID - 0.114

VID - 0.118

VID - 0.122

VID - 0.126

VID - 0.130

VID - 0.134

VID - 0.138

VID - 0.142

VID - 0.146

VID - 0.150

-

5

10

15

20

25

30

35

40

45

50

55

60

65

70

75

80

85

90

95

100

105

110

115

120

125

130

135

140

145

150

Notes:

1.

The Vcc

and Vcc

loadlines represent static and transient limits. Please see Table 2-8 and

_MIN

_MAX

Figure 2-3 for Vcc overshoot specifications.

2.

The loadlines specify voltage limits at the die. Die Vcc voltage is available at the Vcoresense and

Vsscoresense lands and should be measured there. Voltage regulation feedback for voltage regulator

circuits must be taken from the processor VCORESENSE and VSSCORESENSE lands. Voltage regulation

feedback for voltage regulator circuits must also be taken from processor VCCCORESENSE and

VSSCORESENSE lands. Refer to the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator

Down (EVRD) 11.1 Design Guidelines for socket load line guidelines and VR implementation

Datasheet Volume 1 of 2

23

Electrical Specifications

Figure 2-1. VCC Static and Transient Tolerance

Load (A)

0

10 20 30 40 50 60 70 80 90 100 110 120 130 140 150

0.00

-0.01

-0.02

-0.03

-0.04

-0.05

-0.06

-0.07

-0.08

-0.09

-0.10

-0.11

-0.12

-0.13

-0.14

-0.15

0.8 mOhm Load Line

Vcc max

Vcc min

Vcc typ

Table 2-7.

Processor VccCache Static and Transient Tolerance

I

(A)

Vcc

(V)

Vcc

(V)

Vcc (V)

_Min

Notes

CC

_Max

_Typ

0

VID - 0.000

VID - 0.007

VID - 0.014

VID - 0.021

VID - 0.028

VID - 0.035

VID - 0.042

VID - 0.049

VID - 0.056

VID - 0.063

VID - 0.070

VID - 0.077

VID - 0.084

VID - 0.091

VID - 0.098

VID - 0.105

VID - 0.112

VID - 0.015

VID - 0.022

VID - 0.029

VID - 0.036

VID - 0.043

VID - 0.050

VID - 0.057

VID - 0.064

VID - 0.071

VID - 0.078

VID - 0.085

VID - 0.092

VID - 0.099

VID - 0.106

VID - 0.113

VID - 0.120

VID - 0.127

VID - 0.030

VID - 0.037

VID - 0.044

VID - 0.051

VID - 0.058

VID - 0.065

VID - 0.072

VID - 0.079

VID - 0.086

VID - 0.093

VID - 0.100

VID - 0.107

VID - 0.114

VID - 0.121

VID - 0.128

VID - 0.135

VID - 0.142

5

10

15

20

25

30

35

40

45

50

55

60

65

70

75

80

Notes:

1.

The Vcc

and Vcc

loadlines represent static and transient limits. Please see Table 2-8 and

_MAX

_MIN

Figure 2-3 for Vcc overshoot specifications.

24

Datasheet Volume 1 of 2

Electrical Specifications

2.

The loadlines specify voltage limits at the die. Die VccCache voltage is available at the Vcachesense and

Vsscachesense lands and should be measured there. Voltage regulation feedback for voltage regulator

circuits must also be taken from the processor VCACHESENSE and VSSCACHESENSE lands. Refer to the

Voltage Regulator Module (VRM) and Enterprise Voltage Regulator Down (EVRD) 11.1 Design Guidelines for

socket load line guidelines and VR implementation.

Figure 2-2. Vcache Static and Transient Tolerance

Load (A)

0

5

10 15 20 25 30 35 40 45 50 55 60 65 70 75

0.00

-0.01

-0.02

-0.03

-0.04

-0.05

-0.06

-0.07

-0.08

-0.09

-0.10

-0.11

-0.12

-0.13

-0.14

-0.15

1.4 mOhm Load Line

Vcc max

Vcc min

Vcc typ

Table 2-8.

V_CCand Vcache overshoot Specification

Symbol

Parameter

Min

Max

Units

Figure

Notes

Magnitude of Vcc Overshoot above

VID

V

T

0.05

V

2-3

OS_MAX

Time duration of V Overshoot

CC

25

μs

2-3

OS_MAX

above VID

The Intel Xeon Processor E7-8800/4800/2800 Product Families processor can tolerate

short transient overshoot events where supplied voltage exceeds the VID/CVID voltage

when transitioning from a high-to-low current load condition. This overshoot cannot

exceed VID/CVID + V_{OS_MAX}. (V_{OS_MAX}is the maximum allowable overshoot above

VID/CVID). These specifications apply to the processor die voltages, as measured with

respect to VSSCORESENSE, and VSSCACHESENSE.

Datasheet Volume 1 of 2

25

Electrical Specifications

Figure 2-3. Overshoot Example Waveform

V_OS

VID + 0.050

VID - 0.000

T_OS

0

5

10

15

20

25

Time [us]

T_OS: Overshoot time above VID

V_OS: Overshoot voltage above VID

2.5

Intel^®QPI and Intel^®Scalable Memory

Interconnect (Intel^®SMI) Interface Differential

Signaling

The Intel Xeon Processor E7-8800/4800/2800 Product Families processor Intel QPI and

Intel^®Scalable Memory Interconnect (Intel^®SMI) signals use differential links. The

termination voltage level for the Intel Xeon Processor E7-8800/4800/2800 Product

Families processor for uni-directional serial differential links, each link consisting of a

pair of opposite-polarity (D+, D-) signals is V_SS.

Termination resistors are provided on the processor silicon and are terminated to V_SS.

Intel chipsets also provide on-die termination (ODT), thus eliminating the need to

terminate the links on the system board for the Intel QPI and Intel SMI signals.

Figure 2-4 illustrates the active ODT. Signal listings are included in Table 2-3 and

Table 2-4.

See Chapter 5 for the pin signal definitions. All of the signals on the processor Intel QPI

and Intel SMI signals are in the differential signal group.

Figure 2-4. Active ODT for a Differential Link Example

T_X

R_X

Signal

R_TT

26

Datasheet Volume 1 of 2

Electrical Specifications

2.5.1

Intel QPI Signaling Specifications

Intel QPI electrical specifications call out specifications that are common across all

platforms and specifications that target Intel QPI within Enterprise MP class server

systems.

2.5.1.1

Intel QPI Reference Clocking Specifications

Reference clock requirements required by the PLL as measured at the package pin.

Table 2-9 provides a list of system clock specifications.

Figure 2-5. Validation Topology for Testing Specifications of the Reference Clock

Figure 2-6. Differential Waveform Measurement Points

Table 2-9.

System Clock Specifications (Sheet 1 of 2)

Symbol

Parameter

Min

Nom

Max

Unit

MHz

Notes

f

System clock frequency

133.33

Refclk

ER

Rise and fall slope

parameter

1.0

4.0

V/nsec

Refclk-diffRise,

Refclk-diffFall

V

Single ended maximum

voltage with overshoot

1150

mV

Refclk-max

Refclk-min

Cross

Single ended minimum

voltage with overshoot

-350

250

Absolute crossing point

limits between Refclk+ and

Refclk- waveforms

550

140

See

Figure 2-6

V

Peak-peak variation in

crossing points

See

Figure 2-6

Cross_delta

High of the differential

150

mV

Refclk_diff-ih

voltage (V

+ - V

-)

Refclk

above zero

Datasheet Volume 1 of 2

27

Electrical Specifications

Table 2-9.

System Clock Specifications (Sheet 2 of 2)

Symbol

Parameter

Min

Nom

Max

Unit

mV

Notes

V

Low of the differential

-150

Refclk_diff-il

voltage (V

+ - V

-)

Refclk

above zero

T

Duty cycle of reference

clock.

40

50

60

%

Refclk-Dutycycle

Accumulated rms jitter over

n UI of a given PLL model

output in response to the

jittery reference clock

input. The PLL output is

generated by convolving

the measured reference

clock phase jitter with a

given PLL transfer function.

Here n=12.

0.5

psec

1

Refclk-jitter-rms-onepll

TRefclk-diff-jit

TRefclk-C2C-jit

Phase Drift between clocks

at two connected ports

500

100

psec

Short term difference in the

period of any two adjacent

clock cycles

At via

Note:

1.

The given PLL parameters are: Underdamping (z) = 0.8 and natural frequency = fn = 7.86E6 Hz; w = 2 *

n

fn. N_minUI = 12 for Intel QPI Phy 1 channel.

2.5.1.2

Link Speed Independent Specifications

Link speed independent specifications call out the transmitter and receiver parameters

required at all link speeds. The transmitter specifications are for stand-alone, individual

transmitters (Tx). The validation setup for Tx is called out in Figure 2-7.

Figure 2-7. Setup for Validating Standalone Tx Voltage and Timing Parameters

Ideal Loads

Silicon TX

Tx Package

SI Tx pin terminations are set to optimum values

(targeted around 50 ohms single-ended)

The parameters for the receiver (Rx) couple the transmitter with the worst-case

interconnect. The validation setup for Rx is called out in Figure 2-8.

28

Datasheet Volume 1 of 2

Electrical Specifications

Figure 2-8. Setup for Validating Tx + Worst-Case Interconnect Specifications

W o rs t-C a s e In te rc o n n e c t

Id e a l

L o a d s

S ilic o n

T x b it

(D a ta )

T x

P a c k a g e

Id e a l

L o a d s

S ilic o n

T x b it

(C lo c k )

L o s s le s s In te rc o n n e c t P h a s e

M a tc h e d to D a ta B it In te rc o n n e c t

Specifications for link speed independent specifications are called out in Table 2-10.

Table 2-10. Link Speed Independent Specifications (Sheet 1 of 2)

Symbol

UIavg

Parameter

Min

Nom

Max

Unit

Notes

Average UI size at “G” GT/ 0.999 *

s (Where G = 4.8, 6.4,

and so on)

1000/G 1.001 *

nominal

psec

% of

nominal

T

+/- 100mV@crossing

25 psec

-6

0.25 UI

6

rise-fall-pin-20-80

ΔZ

RL

Defined as:

TX_LOW_CM_DC

(max(Z

) -

Z

TX_LOW_CM_DC

min(Z

Z

)) /

TX_LOW_CM_DC

expressed

TX_LOW_CM_DC

in %, over full range of Tx

single ended voltage

Defined as:

-6

0

6

% of

Z

RX_LOW_CM_DC

(max(Z

) -

)) /

TX_LOW_CM_DC

min(Z

Z

TX_LOW_CM_DC

expressed

TX_LOW_CM_DC

in %, over full range of Tx

single ended voltage

Return Loss of Receiver

See note

1

RX

Package measured at any

data or clock signal inputs

N

Z

# of UI over which the

eye mask voltage and

timing spec needs to be

validated

1,000,000

40k

MIN-UI-Validation

Single ended DC

Ω

2

RX_HIGH_CM_DC

impedance to GND for

either D+ or D- of any

data bit at Tx

Z

V

Link Detection Resistor

500

2000

1.5

Ω

TX_LINK_DETECT

Link Detection Resistor

Pull-up Voltage

V

TX_LINK_DETECT

V

Voltage difference

between D+ and D- when

lanes are either in

Electrical Idle or

0.1 * V

V

DIFF_IDLE

Rx-

diff-pp-pin

V

TX_LINK_DETECT

Datasheet Volume 1 of 2

29

Electrical Specifications

Table 2-10. Link Speed Independent Specifications (Sheet 2 of 2)

Symbol

Parameter

Min

Nom

Max

Unit

Notes

T

Skew between first to last

data termination meeting

RX_LOW_CM_DC

128

1.5

20K

32

UI

μs

UI

DATA_TERM_SKEW

Z

T

Time taken by inband

reset detector to sense

Inband Reset

INBAND_RESET_

SENSE

Tclk

Time taken by clock

detector to observe clock

stability

_DET

T

Time taken by clock

frequency detector to

decide slow vs.

Reference Clock

Cycles

CLK_FREQ_DET

operational clock after

stable clock

T

Phase variability between

reference Clk (at Tx input)

and Tx output.

500

psec

UI

Refclk-Tx-Variability

Refclk-Rx-Variability

D+/D-RX-Skew

Phase variability between 1000

reference Clk (at Rx

input) and Rx output.

L

Phase skew between D+

and D- lines for any data

bit at Rx

0.03

BER

Bit Error Rate per lane

1.0E-14

VIO

Events

mV

V

Lane

valid for 4.8 and 6.4 GT/s

Voh_bscan

Vol_bscan

Vih_bcan

Vil_bscan

Output high during

boundary scan

VIO-100

Output low during

boundary scan

0

100

Input high during

boundary scan

0.86 * VIO

Output low during

boundary scan

0.40 * VIO

V

Notes:

1.

Return loss specifications for receiver package are not provided. However, maintaining a well impedance

matched and low loss receiver package is crucial for a successful silicon operation, including maintaining as

low as possible on-die capacitance.

2.

Used during initialization. It is the state of “OFF” condition for the receiver when only the minimum

termination is connected

2.5.2

Intel QPI Electrical Specifications

The applicability of this section applies to Intel QPI within a links-based Enterprise MP

class server platform. This section contains information for slow boot up speed (1/4

frequency of the reference clock), 4.8 GT/s, and 6.4 GT/s.

The transfer rates available for the Intel Xeon Processor E7-8800/4800/2800 Product

Families processor are shown in Table 2-11.

Table 2-11. Clock Frequency Table

Intel QPI System Interface

Forwarded Clock Frequency

Intel QPI System Interface

Data Transfer Rate

1

33.33 MHz

2.40 GHz

3.20 GHz

66.66 MT/s

4.8 GT/s

6.4 GT/s

30

Datasheet Volume 1 of 2

Electrical Specifications

Notes:

1. This speed is the 1/4 RefClk Frequency.

2.5.2.1

Requirements at 1/4 RefClk Signaling Rate

The signaling rate is defined as 1/4 the rate of the System Reference Clock. For

example, a 133 MHz System Reference Clock would have a forwarded clock frequency

of 33.33 MHz and the signaling rate would be 66.66 MT/s.

Table 2-12. Parameter Values for Intel® QPI Phy1 Channel at 1/4 RefClk Frequency

Symbol

Parameter

Min

Nom

Max

Unit

Notes

mV

1

V

Z

Transmitter differential swing

800

1500

Tx-diff-pp-pin

Ω

DC resistance of Tx terminations

at half the single ended swing

37

47

TX_LOW_CM_DC

(which is usually 0.25*V

Tx-diff-pp-

) bias point

Ω

DC resistance of Rx terminations

at half the single ended swing

Z

37

47

RX_LOW_CM_DC

(which is usually 0.25*V

Tx-diff-pp-

) bias point

5

2

Transmitter output DC common

mode, defined as average of V

Fraction of

V

0.23

0.27

V

Tx-cm-dc-pin

D+

Tx-diff-pp-pin

and V

D-

Transmitter output AC common

mode, defined as ((V + V )/2 -

Fraction of

-

0.0375

0.0025

0.0075

V

Tx-cm-ac-pin

D+

D-

Tx-diff-pp-pin

0.0375

V

)

Tx-cm-dc-pin

UI

1

3

TX

Average of absolute UI-UI jitter

-0.002

-0.007

duty-pin

Absolute value of UI-UI jitter

measured at Tx output pins with

1E-7 probability.

jitUI-UI-1E-7-pin

mV

Voltage eye opening at the end of

Tx+ channel for any data or clock

channel measured with a

cumulative probability of 1E-9

(UI).

V

150

0.9

V

1

Rx-diff-pp-pin

Tx-diff-pp-pin

T

Timing eye opening at the end of

Tx+ channel for any data or clock

channel measured with a

cumulative probability of 1E-9

(UI).

UI

Rx-diff-pp-pin

T

Delay of any data lane relative to

the clock lane, as measured at the

end of Tx+ channel. This

0.48

0.52

Rx-data-clk-skew-pin

parameter is a collective sum of

effects of data clock mismatches

in Tx and on the medium

connecting Tx and Rx.

VRx-CLK

Forward CLK Rx input voltage

sensitivity (differential pp)

150

400

mV

V

DC common mode ranges at the

Rx input for any data or clock

channel

75

Rx-cm-dc-pin

Rx-cm-ac-pin

V

AC common mode ranges at the

Rx input for any data or clock

channel, defined as:

-50

50

mV

2

((V

+ V /2 - V

)

RX-cm-dc-pin

D+

D-

Datasheet Volume 1 of 2

31

Electrical Specifications

Notes:

1.

2.

The UI size is dependent upon the reference clock frequency

1300mVpp swing is recommended when CPU to CPU length is within 2” of PDG max trace length. Note that

default value is 1100mVpp.

3.

Measure AC CM noise at the TX and decimate to its spectral components. For all spectral components above

3.2GHz, apply the attenuation of the channel at the appropriate frequency. If the resultant AC CM at the

receiver is met after taking out the appropriate spectral component and it meets the RX AC CM spec then

we can allow the transmitter AC CM noise to pass.

4.

DC CM can be relaxed to 0.20 min and 0.30 max Vdiffp-p swing if RX has wide DC common mode range.

2.5.2.2

Requirements for 4.8 GT/s and 6.4 GT/s

Electrical specifications for Tx and Rx for 4.8 GT/s are captured in Table 2-13 and for

6.4 GT/s are captured in Table 2-14.

Table 2-13. Parameter Values for Intel QPI Channel at 4.8 GT/s (Sheet 1 of 2)

Symbol

Parameter

Min

800

Nom

Max

1500

Unit

Notes

V

Z

Transmitter differential swing

mV

1

Tx-diff-pp-pin

DC resistance of Tx terminations

at half the single ended swing

37

47

Ω

TX_LOW_CM_DC

(which is usually 0.25*V

Tx-diff-pp-

) bias point

Z

V

DC resistance of Rx terminations

at half the single ended swing

37

47

Ω

RX_LOW_CM_DC

Tx-cm-dc-pin

(which is usually 0.25*V

Tx-diff-pp-

) bias point

Transmitter output DC common

mode, defined as average of V

0.23

0.27

Fraction of

V

D+

Tx-diff-pp-

and V

D-

V

Transmitter output AC common

mode, defined as ((V + V )/2

-

0.0375

Fraction of

Tx-diff-pp-

UI

2

3

Tx-cm-ac-pin

0.0375

V

D+

D-

- V

)

Tx-cm-dc-pin

TX

Average of UI-UI jitter.

-0.025

-0.065

0.03

0.07

duty-pin

UI-UI jitter measured at Tx

output pins with 1E-7 probability.

UI

jitUI-UI-1E-7-pin

TX

UI-UI jitter measured at Tx

output pins with 1E-9 probability.

-0.07

0

0.076

0.15

jitUI-UI-1E-9-pin

p-p accumulated jitter out of

transmitter over 0 <= n <= N UI

where N=12, measured with 1E-7

probability.

clk-acc-jit-N_UI-1E-7

TX

p-p accumulated jitter out of

transmitter over 0 <= n <= N UI

where N=12, measured with 1E-9

probability.

0

0.17

UI

clk-acc-jit-N_UI-1E-9

Tx-data-clk-skew-pin

T

Delay of any data lane relative to

clock lane, as measured at Tx

output

-0.5

0.5

UI

V

Voltage eye opening at the end of 225

Tx+ channel for any data or clock

channel measured with a

cumulative probability of 1E-9

(UI).

1200

mV

Rx-diff-pp-pin

T

Timing eye opening at the end of

Tx+ channel for any data or clock

channel measured with a

cumulative probability of 1E-9

(UI)

0.63

1

UI

Rx-diff-pp-pin

32

Datasheet Volume 1 of 2

Electrical Specifications

Table 2-13. Parameter Values for Intel QPI Channel at 4.8 GT/s (Sheet 2 of 2)

Symbol

Parameter

Min

-1

Nom

Max

Unit

Notes

T

Delay of any data lane relative to

the clock lane, as measured at

the end of Tx+ channel. This

parameter is a collective sum of

effects of data clock mismatches

in Tx and on the medium

3

UI

Rx-data-clk-skew-pin

connecting Tx and Rx.

VRx-CLK

Forward CLK Rx input voltage

sensitivity (differential pp)

180

350

mV

V

DC common mode ranges at the

Rx input for any data or clock

channel

125

-50

Rx-cm-dc-pin

Rx-cm-ac-pin

AC common mode ranges at the

Rx input for any data or clock

channel, defined as:

50

mV

2

((V

+ V /2 - V

)

RX-cm-dc-pin

D+

D-

Notes:

1.

1300mVpp swing is recommended when CPU to CPU length is within 2” of PDG max trace length. Note that

default value is 1100mVpp.

Measure AC CM noise at the TX and decimate to its spectral components. For all spectral components above

3.2GHz, apply the attenuation of the channel at the appropriate frequency. If the resultant AC CM at the

receiver is met after taking out the appropriate spectral components meets the RX AC CM spec then we can

allow the transmitter AC CM noise to pass.

2.

3.

Measured with victim lane running clock pattern, neighboring aggressor lanes running DC pattern and far

aggressor lanes running PRBS pattern.

Table 2-14. Parameter Values for Intel QPI at 6.4 GT/s (Sheet 1 of 2)

Symbol

Parameter

Min

800

Nom

Max

1500

Unit

Notes

V

Z

Transmitter differential swing

mV

1

Tx-diff-pp-pin

DC resistance of Tx terminations

at half the single ended swing

38

47

Ω

TX_LOW_CM_DC

RX_LOW_CM_DC

(which is usually 0.25*V

Tx-diff-pp-

) bias point

Z

DC resistance of Rx terminations

at half the single ended swing

38

47

Ω

(which is usually 0.25*V

Tx-diff-pp-

) bias point

V

Transmitter output DC common

mode, defined as average of V

0.23

0.27

Fraction of

Tx-diff-pp-pin

4

2

Tx-cm-dc-pin

V

D+

and V

D-

Transmitter output AC common

mode, defined as ((V + V )/2 -

-0.065

0.065

Fraction of

Tx-cm-ac-pin

V

D+

D-

Tx-diff-pp-pin

V

)

Tx-cm-dc-pin

TX

Average of absolute UI-UI jitter

-

0.0325

0.12

UI

duty-pin

0.0325

UI-UI jitter measured at Tx output -0.12

pins with 1E-7 probability.

3

jitUI-UI-1E-7-pin

jitUI-UI-1E-9-pin

clk-acc-jit-N_UI-1E-7

UI-UI jitter measured at Tx output -0.137

pins with 1E-9 probability.

0.137

0.2

p-p accumulated jitter out of

transmitter over 0 <= n <= N UI

where N=12, measured with 1E-7

probability.

0

TX

p-p accumulated jitter out of

transmitter over 0 <= n <= N UI

where N=12, measured with 1E-9

probability.

0.23

UI

clk-acc-jit-N_UI-1E-9

Datasheet Volume 1 of 2

33

Electrical Specifications

Table 2-14. Parameter Values for Intel QPI at 6.4 GT/s (Sheet 2 of 2)

Symbol

Parameter

Min

-0.5

Nom

Max

0.5

Unit

Notes

T

Delay of any data lane relative to

clock lane, as measured at Tx

output

UI

Tx-data-clk-skew-pin

V

Voltage eye opening at the end of 155

Tx+ channel for any data or clock

channel measured with a

cumulative probability of 1E-9

(UI).

1200

mV

2

Rx-diff-pp-pin

T

Timing eye opening at the end of

Tx+ channel for any data or clock

channel measured with a

0.61

1

3

UI

Rx-diff-pp-pin

cumulative probability of 1E-9 (UI)

Delay of any data lane relative to

the clock lane, as measured at the

end of Tx+ channel. This

-1

Rx-data-clk-skew-pin

parameter is a collective sum of

effects of data clock mismatches

in Tx and on the medium

connecting Tx and Rx.

VRx-CLK

Forward CLK Rx input voltage

sensitivity (differential pp)

150

350

mV

V

DC common mode ranges at the

Rx input for any data or clock

channel

90

Rx-cm-dc-pin

Rx-cm-ac-pin

AC common mode ranges at the

Rx input for any data or clock

channel, defined as:

-50

50

mV

((V

+ V /2 - V

)

RX-cm-dc-pin

D+

D-

Notes:

1.

1300 mVpp swing is recommended when CPU to CPU length is within 2” of PDG max trace length. Note that

default value is 1100mVpp.

2.

Measure AC CM noise at the TX and decimate to its spectral components. For all spectral components above

3.2 GHz, apply the attenuation of the channel at the appropriate frequency. If the resultant AC CM at the

receiver is met after taking out the appropriate spectral components meets the RX AC CM spec then we can

allow the transmitter AC CM noise to pass.

3.

4.

Measured with victim lane running clock pattern, neighboring aggressor lanes running DC pattern and far

aggressor lanes running PRBS pattern.

DC CM can be relaxed to 0.20 and 0.30 Vdiffp-p swing if RX has wide DC common mode range.

2.5.3

2.5.4

Intel SMI Signaling Specifications

This section defines the high-speed differential point-to-point signaling link for Intel

SMI. The link consists of a transmitter and a receiver and the interconnect in between

them. The specifications described in this section covers 6.4 Gb/s operation.

Reference Intel SMI high-speed differential PTP link is at 1.5 V.

Intel SMI Transmitter and Receiver Specifications

All TX-RX links are DC-coupled and the TX and RX pins adhere to the return loss

specifications for continuous transmission operation.

34

Datasheet Volume 1 of 2

Electrical Specifications

Table 2-15. Parameter Values for Intel SMI at 6.4 GT/s and lower (Sheet 1 of 2)

Symbol

Parameter

Min

800

Nom

Max

1200

Unit

Notes

V

Z

Transmitter differential swing

mV

Tx-diff-pp-pin

DC resistance of Tx terminations

at half the single ended swing

37

47

Ω

TX_LOW_CM_DC

RX_LOW_CM_DC

(which is usually 0.25*V

Tx-diff-pp-

) bias point

Z

DC resistance of Rx terminations

at half the single ended swing

37

47

Ω

(which is usually 0.25*V

Tx-diff-pp-

) bias point

VTx-diff-pp-CLK-pin Transmitter differential swing

using a CLK like pattern

0.9*mi

n(VTx-

diff-pp

pin)

max(VTxdi mV

ff-pp-pin)

1

V

Transmitter output DC common

mode, defined as average of V

0.20

-0.20

-

0.30

Fraction of

Tx-diff-pp-pin

3

Tx-cm-dc-pin

Tx-cm-ac-pin

V

D+

and V

D-

V

Transmitter output AC common

mode, defined as ((V + V )/2 -

0.20

Fraction of

V

D+

D-

Tx-diff-pp-pin

V

)

Tx-cm-dc-pin

TX

This is computed as absolute

0.0325

UI

duty-UI-pin

difference between average value 0.0325

of all UI with that of average of

odd UI, which in magnitude would

equal absolute difference between

average of all UI and average of all

even UI.

Rj value of 1-UI jitter, using setup

of Figure 2-7. With X-talk off, but

on-die system like noise present.

This extraction is to be done after

software correction of DCD

0

0.008

2

TX1UI-Rj-NoXtalk-pin

pp Dj value of 1-UI jitter With X-

talk off, but on-die system like

noise present.

-0.01

0

0.01

UI

2

TX1UI-Dj-NoXtalk--pin

TXN-UI-Rj-NoXtalkpin

Rj value of N-UI jitter. With X-talk

off, but on-die system like noise

present. Here 1 < N < 9.This

extraction is to be done after

software correction of DCD

0.012

pp Dj value of N-UI jitter. With X- -0.04

talk off, but on-die system like

noise present. Here 1 < N < 9.Dj

here indicated Djdd of dual-dirac

fitting, after software correction of

DCD

0.04

0.2

UI

2

TXN-UI-Dj-NoXtalkpin

T

Delay of any data lane relative to

clock lane, as measured at Tx

output

-0.5

0.5

3.5

UI

Tx-data-clk-skew-pin

Delay of any data lane relative to

the clock lane, as measured at the

end of Tx+ channel. This

-1

Rx-data-clk-skew-pin

parameter is a collective sum of

effects of data clock mismatches

in Tx and on the medium

connecting Tx and Rx.

VRx-CLK

Forward CLK Rx input voltage

sensitivity (differential pp)

150

100

mV

Any data lane Rx input voltage

(differential pp) measured at

BER=1E-9

VRx-Vmargin

Datasheet Volume 1 of 2

35

Electrical Specifications

Table 2-15. Parameter Values for Intel SMI at 6.4 GT/s and lower (Sheet 2 of 2)

Symbol

Parameter

Min

0.8

Nom

Max

Unit

Notes

Timing width for any data lane

using repetitive patterns (check

validation conditions) and clean

forwarded CLK, measured at

BER=1E-9

UI

TRx-Tmargin

Δ

Magnitude of degradation of

timing width for any data lane

using repetitive patterns with DCD

injection in forwarded CLK

measured at BER=1E-9, compared

to TRx-Tmargin. The magnitude of

DCD is specified under validation

conditions.

0.02

TRx-Tmargin-DCD-CLK

TRx-Tmargin-Rj-CLK

TRx-Tmargin-DCD-Rj-

Magnitude of degradation of

timing width for any data lane

using repetitive patterns with only

Rj injection in forwarded CLK

measured at BER=1E-9, compared

to TRx-Tmargin. The magnitude of

Rj is specified under validation

conditions.

0.11

0.12

UI

Magnitude of degradation of

timing width for any data lane

using repetitive patterns with DCD

and Rj injection in forwarded CLK

measured at BER=1E-9, compared

to TRx-Tmargin. The magnitude of

DCD and Rj is specified under

validation conditions.

CLK

V

DC common mode ranges at the

Rx input for any data or clock

channel, defined as average of

VD+ and VD-.

125

-50

350

50

mV

Rx-cm-dc-pin

Rx-cm-ac-pin

AC common mode ranges at the

Rx input for any data or clock

channel, defined as:

((V

+ V /2 - V

)

RX-cm-dc-pin

D+

D-

Notes:

1.

This is the swing specification for the forwarded CLK output. Note that this specification will also have to be

suitably de-embedded for package/PCB loss to translate the value to the pad, since there is a significant

variation between traces in a setup.

2.

While the X-talk is off, on-die noise similar to that occurring with all the transmitter and receiver lanes

toggling will still need to be present. When a socket is not present in the transmitter measurement setup,

in many cases the contribution of the cross-talk is not significant or can be estimated within tolerable error

even with all the transmitter lanes sending patterns. Therefore for all Tx measurements, use of a socket

should be avoided. The contribution of cross-talk may be significant and should be done using the same

setup at Tx and compared against the expectations of full link signaling. Note that there may be cases

when one of Dj and Rj specs is met and another violated in which case the signaling analysis should be run

to determine link feasibility.

3.

DC CM can be relaxed to 0.20 and 0.30 Vdiffp-p swing if RX has wide DC common mode range.

2.5.4.1

Summary of Transmitter Amplitude Specifications

Table 2-16. PLL Specification for TX and RX

Symbol

Parameter

Min

Max

16

Units

Notes

F

-3dB bandwidth

Jitter Peaking

4

MHz

dB

PLL-BW_TX-RX

JitPk

3

TX-RX

36

Datasheet Volume 1 of 2

Electrical Specifications

Table 2-17. Transmitter Voltage Swing

Voltage Swing

Setting

Mean

TX-diffp-p-min

Mean

TX-diffp-p-max

Units

V

110 (L)

100 (M)

010 (S)

850

700

600

1200

1000

850

mV

Table 2-18. Transmitter De-emphasis (Swing Setting 110: Large)

De-emphasis Range

Measured Values After Inverse Equalization

Normalized

swing delta

(max)

De-emphasis

Setting

V

Minimum

Swing

Maximum

Swing

TX-DE-ratio-

min

TX-DE-ratio-

max

Units

10.1 dB

8.5 dB

7.2 dB

6.0 dB

5.0 dB

9.3

7.8

6.6

5.5

4.5

11.0

9.3

7.8

6.6

5.5

680

685

700

1315

1305

1300

1285

mV

0.450

0.400

0.390

0.300

0.290

Table 2-19. Transmitter De-emphasis (Swing Setting 100: Medium)

De-emphasis Range

Measured Values After Inverse Equalization

Normalized

swing delta

(max)

De-emphasis

Setting

V

Minimum

Swing

Maximum

Swing

TX-DE-ratio-

min

TX-DE-ratio-

max

Units

8.5 dB

7.2 dB

6.0 dB

5.0 dB

4.1 dB

3.3 dB

7.8

6.6

5.5

4.5

3.7

2.9

9.3

7.8

6.6

5.5

4.5

3.7

555

570

1100

1095

1090

mV

0.420

0.410

0.320

0.315

0.295

0.270

Table 2-20. Transmitter De-emphasis (Swing Setting 010: Small)

De-emphasis Range

Measured Values After Inverse Equalization

Normalized

swing delta

(max)

De-emphasis

Setting

V

Minimum

Swing

Maximum

Swing

TX-DE-ratio-

min

TX-DE-ratio-

max

Units

6.0 dB

5.0 dB

4.1 dB

3.3 dB

2.5 dB

1.8 dB

5.5

4.5

3.7

2.9

2.1

1.5

6.6

5.5

4.5

3.7

2.9

2.1

485

930

mV

0.345

0.335

0.320

0.295

0.290

0.285

Datasheet Volume 1 of 2

37

Electrical Specifications

2.5.4.2

Summary of Transmitter Output Specifications

Table 2-21. Summary of Differential Transmitter Output Specifications

Symbol

Parameter

Min

Max

Units

Comments

V

Ratio of V

TX-DIFFp-p (DC)

to measured

23

27

%

TX-CM-Ratio

TX-CM

V

Ratio of V

measured V

to

7.5

%

TX-CM-AC-Ratio

TX-SE

TX-CM-ACp-p

TX-DIFFp-p (DC)

Single-ended voltage

(w.r.t. VSS) on D+/D-

-75

750

mV

1, 2

T

Transmitter total jitter

0.25

0.15

TX_TJ

Transmitter dual-dirac

deterministic jitter

UI

TX_DJ

T

Transmitter pulse width

shrinkage (data)

0.05

0.018

30

TX_PWS

Transmitter pulse width

shrinkage (forwarded clock)

UI

TX_CLK_PWS

ER

,

Differential TX output edge

rates

10

V/ns

Differential voltage levels at ±100 mV

Measured as: Note 1

TX-RISE

TX-FALL

RL

Differential return loss

8

6

dB

Ω

Measured relative to 50 ohms over

0.1 GHz to 3.2 GHz.

TX-DIFF

RL

Common mode return loss

Measured relative to 50 ohms over

0.1 GHz to 3.2 GHz.

TX-CM

R

Transmitter termination

resistance

37.4

47.6

TX

L

Lane-to-lane skew at TX

100

ps

TX-SKEW

+ 2 UI

L

TX clock-to-data skew

-0.2

-1.5

0.2

1.5

ns

Forwarded clock delay - data delay

TX-SKEW-CLK-DAT

L

Total system clock-to-data

skew

TOT-SKEW-CLK-DAT

T

Maximum TX Drift

Bit Error Ratio

240

ps

3

TX-DRIFT

-12

10

BER

Notes:

1.

2.

3.

Specified at the package pins into a timing and voltage compliance test load.

The maximum value is specified to be at least (V / 4) + V + (V / 2)

TX-CM-ACp-p

Measured from the reference clock edge to the center of the output eye. This specification must be met across specified

voltage and temperature ranges for a single component. Drift rate of change is significantly below the tracking capability of

the receiver.

TX-DIFFp-p L

TX-CM L

2.5.4.3

Intel® SMI Differential Receiver Input Specifications

The receiver definition starts from the input pin of the receiver end package and

therefore includes the package and the receiver end device.

2.5.4.3.1

Receiver Input Compliance Eye Specification

Following the specification of the transmitter, the receiver is specified in terms of the

minimum input eye height that must be maintained at the input to the receiver, and

under which the receiver must function at the specified data rates. In addition to eye

height, there are timing specifications that must also be met for both the data lanes

and the forwarded clock.

The receiver eye is referenced to V_SSand all input terminations at the receiver must be

referenced to V_SS. This input eye must be maintained for the entire duration of the RX

test pattern. An appropriate average transmitter UI must be used as the interval for

38

Datasheet Volume 1 of 2

Electrical Specifications

measuring the eye diagram. The eye diagram is created using all edges of the RX test

pattern. The eye diagrams shall be measured by observing a continuous pattern at the

pin of the device. Note that the persistent eye diagram is used for determining

conformance to voltage level specifications only.

Figure 2-9. Required Receiver Input Eye (Differential) Showing Minimum Voltage Specs

V_RX-DIFF= 0mV

(D+ D- Crossing Point)

V_{RX-DIFp-p-MIN}

2.5.4.4

2.5.4.5

Receiver Input Timing

The figure of merit for receiver input timing is the RX eye width, represented by the

symbol T_RX-Eye-Min. The receiver eye width is measured with respect to a delayed

version of the transmitted forwarded clock, as described in Section 2.5.4.5.

Summary of Receiver Input Specifications

Table 2-22. Summary of Differential Receiver Input Specifications (Sheet 1 of 2)

Symbol

Parameter

Min

Max

Units

Comments

= 2*|V - V

V

Differential peak-to-peak

input voltage

115

1200

mV

V

|

RX-D-

RX-DIFFp-p

RX-D+

Measured as: Note 1; see also Note 2

V

Single-ended voltage (w.r.t. VSS)

on D+/D-

-200

85

750

4.0

mV

3

RX-SE

Single-pulse peak

differential input voltage

3, 4

RX-DIFF-PULSE

V

Amplitude ratio between

adjacent symbols,

3, 5

RX-DIFF-ADJ-RATIO

V

<= 1100 mV

RX-DIFFp-p

T

Minimum RX Eye Width

0.50

UI

3, 6, 7

RX-Eye-MIN

RX-DJ-DD

Max RX eye closure due to dual-

dirac deterministic jitter

0.40

310

3, 6, 8, 9

T

Single-pulse width at zero-voltage

crossing

0.55

0.2

120

1

UI

3, 4

RX-PW-ZC

RX-PW-ML

Single-pulse width at minimum-

level crossing

V

Common mode of the input voltage

mV

V

= DC

of |V

+ V

|/2

RX-D-

RX-CM-MinEH

RX-CM

(avg)

RX-D+

(V

= V

)

RX-DIFFp-p

RX-DIFFp-p-min

Ratio of V

increase to max

V

>= V

+

RX-DIFFp-p-min

RX-CM-EH-Ratio

RX-DIFFp-p

DC common mode increase (V

RX-

* (V

- 310 mV)

RX-CM

RX-CM-EH-Ratio

> V

)

DIFFp-p

RX-DIFFp-p-min

Datasheet Volume 1 of 2

39

Electrical Specifications

Table 2-22. Summary of Differential Receiver Input Specifications (Sheet 2 of 2)

Symbol

Parameter

Min

Max

Units

Comments

V

Common mode of the input voltage

(Absolute max)

375

mV

V

DC

of |V

+ V

|/2

RX-D-

RX-CM-ABS

RX-CM =

(avg)

RX-D+

AC peak-to-peak common mode of

input voltage

270

45

mV

=

RX-CM-ACp-p

RX-CM-AC

Max |V

Min |V

Measured as: Note 1

+ V

|/2–

RX-D+

RX-D-

|/2

RX-D-

RX-D+

V

Ratio of V

to minimum

%

11

RX-CM-AC-EH-Ratio

RX-CM-ACp-p

RX-DIFFp-p

V

RL

Differential return loss

9

6

dB

Measured over 0.1GHz to 3.2 GHz.

See also Note 12

R

RX termination resistance

37.4

0.0

47.6

1.0

Ohm

ns

RX

T

RX skew between clock and data

Forwarded clock delay - data delay

14

RX-SKEW-CLK-DATA

Minimum RX Drift Tolerance

Fast reset entry detect time

Bit Error Ratio

600

ps

UI

RX-DRIFT

240

FR-ENTRY -DETECT

-12

10

BER

Notes:

1.

2.

3.

4.

Specified at the package pins into a timing and voltage compliant test setup.

The V pin specification reflects a target eye height at the pad equal to 70 mV.

RX-DIFFp-p

Specified at the package pins into a timing and voltage compliance test setup.

The single-pulse mask provides sufficient symbol energy for reliable RX reception. Each symbol must comply with both the

single-pulse mask and the cumulative eye mask.

The relative amplitude ratio limit between adjacent symbols prevents excessive inter-symbol interference in the Rx. Each

symbol must comply with the peak amplitude ratio with regard to both the preceding and subsequent symbols.

This number does not include the effects of SSC or reference clock jitter.

5.

6.

7.

8.

9.

The T

pin specification reflects a target eye width at the pad equal to 0.45 UI.

RX-Eye-MIN

pin specification reflects a target max deterministic jitter at the pad equal to 0.45 UI.

RX-DJ-DD

Defined as the dual-dirac deterministic jitter at the receiver input.

10. Allows for 15 mV DC offset between transmit and receive devices.

11. The received differential signal must satisfy both this ratio as well as the absolute maximum AC peak-to-peak common mode

specification. For example, if V

is 200 mV, the maximum AC peak-to-peak common mode is the lesser of

RX-CM-ACp-p

RX-DIFFp-p

(200 mV * 0.45 = 90 mV) and V

.

12. One of the components that contribute to the deterioration of the return loss is the ESD structure which needs to be carefully

designed.

13. The termination small signal resistance; tolerance over the entire signaling voltage range shall not exceed ± 5 Ω.

14. Measured from the reference clock edge to the center of the input eye. This specification must be met across specified voltage

and temperature ranges for a single component. Drift rate of change is significantly below the tracking capability of the

receiver.

2.6

Platform Environmental Control Interface (PECI)

DC Specifications

PECI is an Intel proprietary interface that provides a communication channel between

Intel processors and chipset components to external thermal monitoring devices. The

Intel Xeon Processor E7-8800/4800/2800 Product Families processor contains a Digital

Thermal Sensor (DTS) that reports a relative die temperature as an offset from T_CC

40

Datasheet Volume 1 of 2

Electrical Specifications

activation temperature. Temperature sensors located throughout the die are

implemented as analog-to-digital converters calibrated at the factory. PECI provides an

interface for external devices to read processor die and DRAM temperatures, perform

processor manageability functions, and manage processor interface tuning and

diagnostics.

2.6.1

DC Characteristics

The PECI interface operates at a nominal voltage set by V_IOC. The set of DC electrical

specifications shown in Table 2-23 is used with devices normally operating from a V_IOC

interface supply. V_IOCnominal levels will vary between processor families. All PECI

devices will operate at the V_IOClevel determined by the processor installed in the

system. For specific nominal V_IOClevels, refer to Table 2-23.

Table 2-23. PECI DC Electrical Limits

Notes

1

Symbol

Definition and Conditions

Min

Max

+ 0.15

IOC

Units

V

Input Voltage Range

Hysteresis

-0.150

V

in

V

0.1 * V

IOC

hysteresis

V

Negative-edge threshold voltage

Positive-edge threshold voltage

Low level output sink

0.275 * V

0.50 * V

IoC

2

n

IOC

0.55 * V

0.5

0.725 * V

1.0

2

p

IOC

I

mA

µA

sink

(V = 0.25 * V

)

OL

IOC

High impedance state leakage to

3

V

I

N/A

50

IOC

leak+

(V

= V

)

OL

leak

High impedance leakage to GND

(V = V

3

I

N/A

25

10

µA

pF

leak-

)

OH

leak

C

Bus capacitance per node

4,5

bus

Signal noise immunity above

300 MHz

V

0.1 * V

N/A

V

p-p

noise

IOC

Note:

1.

2.

V

supplies the PECI interface. PECI behavior does not affect V

min/max specifications.

IOC

It is expected that the PECI driver will take in to account, the variance in the receiver input thresholds and

consequently, be able to drive its output within safe limits (-0.15V to 0.275*V for the low level and

IOC

0.725*V

to V

+0.15 for the high level).

IOC

3.

4.

The leakage specification applies to powered devices on the PECI bus.

One node is counted for each client and one node for the system host. Extended trace lengths might appear

as additional nodes.

5.

Excessive capacitive loading on the PECI line may slow down the signal rise/fall times and consequently

limit the maximum bit rate at which the interface can operate.

2.6.2

Input Device Hysteresis

The input buffers in both client and host models must use a Schmitt-triggered input

design for improved noise immunity. Use Figure 2-10 as a guide for input buffer design.

Datasheet Volume 1 of 2

41

Electrical Specifications

Figure 2-10. Input Device Hysteresis

V_IO

Maximum V_P

PECI High Range

Minimum V_P

Maximum V_N

Minimum

Hysteresis Signal Range

Valid Input

Minimum V_N

PECI Ground

PECI Low Range

2.7

DC Specifications

Table 2-24. TAP, Strap Pins, Error, Powerup, RESET, Thermal, VID Signal Group DC

Specifications

Notes

1

Symbol

Parameter

Min

Typ

Max

0.54 V

IOF

Units

V

Input Low Voltage

Input High Voltage

-0.1

V

2,3

IL

*

V

0.86

V

IOF

2

IH

*

V

* R / (R +

ON

sys_term

2,5

IOC

ON

V

Output Low Voltage

V

OL

R

)

V

Output High Voltage

V

2

OH

IOC

Rtt

On Die Pull Up Termination

42.5

0.5

50

57.5

2.9

Ohm

T

time from SYSCLK pin

3

4

CO

T

ns

ps

CO

till signal valid at output

Control Sideband Input

signals with respect to

SYSCLK

Setup

Time

900

Control Sideband Input

signals with respect to

SYSCLK

4

Hold

Time

ps

POC/

Reset

Setup

Time

Power-On Configuration

Setup Time

2

SYSCLK

POC/

Reset

Hold

Power-On Configuration

Hold Time

108

8

SYSCLK

Time

Control Sideband Buffer on

Resistance

R

18

Ohm

ON

I

Input Leakage Current

± 200

μA

6

LI

Notes:

1.

2.

3.

4.

5.

6.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

The V referred to in these specifications refers to instantaneous V

IO

IO.

Based on a test load of 50Ω to V

IOC.

Specified for synchronous signals.

R

is the termination on the system, not part of the processor.

SYS_TERM

®

Intel Trusted Execution Technology for Servers Input Leakage Current Maximum is ±50 uA.

42

Datasheet Volume 1 of 2

Electrical Specifications

Table 2-25. Miscellaneous DC Specifications

Notes

1

Parameter

Min

Typ

Max

Units

SKTID[2:0]

Input Low Voltage

Input High Voltage

Leakage limit low

Leakage limit high

Leakage limit low

Leakage limit high

<0.54 V_IOC

V

3

>0.7 V_CC

V

2

3

2

3

5

uA

mA

uA

4.2

2.6

5

THERMALERT

Notes:

1.

2.

3.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

Recommended strapping high is 1K - 10K Ω.

Recommended strapping low is <100 Ω.

2.8

AC Specifications

The processor timings specified in this section are defined at the processor pads.

Therefore, proper simulation of the signals is the only means to verify proper timing

and signal quality.

Table 2-26 through Table 2-28 list the AC specifications associated with the processor.

See Chapter 5 for signal definitions.

The timings specified in this section should be used in conjunction with the processor

signal integrity models provided by Intel. Intel QPI, SMI and sideband layout guidelines

are also available in the appropriate platform design guidelines.

Note:

Care should be taken to read all notes associated with a particular timing parameter.

Table 2-26. System Reference Clock AC Specifications (Sheet 1 of 2)

Symbol

(SSC-off)

Parameter

Min

Nom

Max

Unit

Figure

Notes

System Reference Clock

frequency

f

133.29

133.33

133.37

MHz

REFCLK

System Reference Clock

frequency

f

(SSC-on)

132.62

175

133.33

133.37

700

MHz

ps

REFCLK

T

Rise time, fall time.

1, 2

Rise, Fall

%

period

3

T

Duty cycle of reference clock.

40

50

60

Refclk-Dutycycle

ER

,

Differential Rising and falling

edge rates

3, 4

Refclk-diff-Rise

1

4

V/ns

ER

Refclk-diff-Fall

C CK

I-

Clock Input Capacitance

Differential Input Low Voltage

Differential Input High Voltage

Absolute Crossing Point

0.2

1.0

pF

V

VL

-0.15

3

VH

0.15

0.25

V

3

V

0.35

0.55

V

1, 5, 6

5, 7

cross

0.25 +

0.55 +

V

(rel)

Relative Crossing Point

0.5*(VH

-

0.5*(VH

-

avg

cross

avg

0.700)

-

0.700)

0.14

V

Delta

V

variation

cross

-

V

1, 5, 8

1, 9

cross

V

(Absolute

max

Overshoot)

Single-ended maximum voltage

-

1.15

Datasheet Volume 1 of 2

43

Electrical Specifications

Table 2-26. System Reference Clock AC Specifications (Sheet 2 of 2)

Symbol

(Absolute

Parameter

Min

Nom

Max

Unit

Figure

Notes

V

1, 10

min

Single-ended minimum voltage

-0.3

-

V

Undershoot)

Differential ringback voltage

threshold

3, 11

VRB-Diff

-100

500

100

mV

ps

T

Allowed time before ringback

Stable

Notes:

1.

2.

3.

4.

Measurement taken from single ended waveform.

Rise and Fall times are measured single ended between 245 mV and 455 mV of the clock swing.

Measurement taken from differential waveform.

Measured from -150 mV to +150 mV on the differential waveform (derived from REFCLK+ minus REFLCLK). The signal must

be monotic through the measurement region for rise and fall time. The 300 mV measurement window is centred on the

differential zero crossing. See Figure 2-25

5.

6.

7.

Measured at crossing point where the instantaneous voltage value of the rising edge REFCLK+ equals the falling edge

REFCLK-. See Figure 2-26.

Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all

crossing points for this measurement. See Figure 2-26.

VHavg is the statistical average of the VH measured by the oscilloscope. The purpose of defining relative crossing point

voltages is to prevent a 250 mV Vcross with a 850 mV VH. Also this prevents the case of a 550 mV Vcross with a 660 mV VH.

See Figure 2-21.

8.

9.

Defined as the total variation of all crossing voltages of Rising REFCLK+ and falling REFCLK-. This is the maximum allowed

variance in Vcross for any particular system. See Figure 2-27.

Defined as the maximum instantaneous voltage including overshoot. See Figure 2-26.

10. Defined as the minimum instantaneous voltage including overshoot. See Figure 2-26.

11. TStable is the time the differential clock must maintain a minimum ±150 mV differential voltage after rising/falling edges

before it is allowed to droop back into the VRB ±100 mV range. See Figure 2-22.

Table 2-27. Miscellaneous GTL AC Specifications

Notes

1, 2

T# Parameter

Min

Max

Unit

Figure

Asynchronous GTL input pulse width

8

SYSCLKs

V/ns

ERROR[0]_N, ERROR[1]_N, THERMTRIP_N,

PROCHOT_N Output Edge Rate

0.7

2.3

16

1, 3

ERROR[0]_N pulse width

16

b-clocks

V/ns

MEM_THROTTLE0_N, MEM_THROTTLE1_N, Intel

TXT, RUNBIST, Input Edge Rate

0.5

FORCE_PR_N pulse width

PROCHOT_N pulse width

PWRGOOD rise time

500

µs

2-18

20

ns

PWRGOOD, RESET_N, FORCE_PR_N, ERROR[0]_N,

ERROR[1]_N, SKTDIS_N Input Edge Rates

0.1

V/ns

2, 3, 4

5

RESET_N hold time w.r.t SYSCLK/SYSCLK_N

RESET_N pulse width while PWRGOOD is active

SYSCLK stable to PWRGOOD assertion

0.5

ns

ms

2-11

2-12

1

10

SYSCLK

ms

THERMTRIP_N assertion until Vcc, and VCCCACHE

removal

500

Vcc stable to PWRGOOD assertion

0.05

1

ms

ns

V

stable to PWRGOOD assertion

REG

V

stable to VIOPWRGOOD assertion

1

500

20

IO

VIOPWRGOOD de-assertion to V outside

io

100

specification

VIOPWRGOOD rise time

ns

PWRGOOD assertion to RESET_N de-assertion

34

ms

44

Datasheet Volume 1 of 2

Electrical Specifications

Notes:

1.

2.

3.

These values are based on driving a 50Ω transmission line into a 50Ω±pullup.

Deterministic reset.

Inspection range is VIL Max to VIH Min. When a signal ledge presents between VIL and VIH region,

measure the first edge rate from VIL (or VIH) to the first inflection point, then measure the second edge

rate from the second inflection point to VIH (or VIL) and divide the sum of the two edge rates by two, to

generate the final edge rate number.

4.

5.

Error signals are 0.1 V/ns if non-monotonic, and 0.05 V/ns if monotonic.

For production platforms, reset determinism is not required.

Table 2-28. VID Signal Group AC Specifications

Notes

1, 2

T # Parameter

Min

Max

Unit

Figure

VID Step Time

-

µs

2-29

VID Down Transition to Valid V

(min)

2-28,2-29

CCP

VID Up Transition to Valid V

(min)

CCP

VID Down Transition to Valid V

VID Up Transition to Valid V

(max)

CCP

(max)

CCP

Notes:

1.

See Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.1 Design

Guidelines for addition information.

2.

Platform support for VID transitions is required for the processor to operate within specifications.

Figure 2-11. RESET_N SEtup/Hold Time for Deterministic RESET_N Deassertion

SYSCLK_N

SYSCLK

Tsetup

Thold

V

IH

V

IL

RESET_N

Note: Deterministic RESET_N is defined for RESET_N deassertion only (coming out of RESET_N)

Figure 2-12. THERMTRIP_N Power Down Sequence

T_A

THERMTRIP_N

V_CC,V_CACHE

T_A= THERMTRIP_N assertion until V_CCand V_CACHEremoval

Datasheet Volume 1 of 2

45

Electrical Specifications

Figure 2-13. VID Step Times

n

n-1

m

m+1

VID

...

Tc

V_CC(max)

Ta

Tb

Td

V_CC(min)

Ta = VID Down to Valid V_CC(max)

Tb = VID Down to Valid V_CC(min)

Tc

= VID Up to Valid V_CC(max)

Td = VID Up to Valid V_CC(min)

Table 2-29. SMBus and SPDBus Signal Group AC Timing Specifications

Notes

1, 2

Symbol

Parameter

Min

Max

Unit

Figure

Transmitter and Receiver Timings

F

SMBCLK Frequency

SMBCLK Period

10

4

100

kHz

µs

ns

V

SMB

TCK

t

SMBCLK High Time

SMBCLK Low Time

SMBus Rise Time

SMBus Fall Time

2-14

2-15

2-14

LOW

HIGH

R

4.7

1

3

0.3

4.5

3

F

T

SMBus Output Valid Delay

SMBus Input Setup Time

SMBus Input Hold Time

SMBus Vil

0.1

250

AA

t

SU;DAT

HD;DAT

0

Vil, SMBus

Vih, SMBus

Vol, SMBus

-0.3

Vcc33 x 0.3

Vcc33 + 0.5

0.4

SMBus Vih

Vcc33 x 0.7

V

SMBus Vol Vcc >2.5

SMBus Vol Vcc <= 2.5

V

0.2

V

t

Bus Free Time between

Stop and Start Condition

4.7

4.0

4.7

4.0

µs

2-14

4, 5

BUF

Hold Time after Repeated

Start Condition

µs

HD;STA

SU;STA

SU;STD

Repeated Start Condition

Setup Time

Stop Condition Setup Time

Notes:

1.

2.

These parameters are based on design characterization and are not tested.

All AC timings for the SMBus signals are referenced at V

pins. Refer to Figure 2-14.

or V

and measured at the processor

IL_MAX

IL_MIN

3.

Rise time is measured from (V

- 0.15V) to (V

+ 0.15V). Fall time is measured from (0.9 *

IH_MIN

IL_MAX

VCC33) to (V

- 0.15V).

IL_MAX

4.

5.

Minimum time allowed between request cycles.

Following a write transaction, an internal write cycle time of 10ms must be allowed before starting the next

transaction.

46

Datasheet Volume 1 of 2

Electrical Specifications

Figure 2-14. SMBus Timing Waveform

t

F

t

HD;STA

R

t

LOW

Clk

t

SU;STO

t

HIGH

t

HD;STA

SU;STA

HD;DAT

SU;DAT

Data

t

BUF

S

P

STOP

START

STOP

Figure 2-15. SMBus Valid Delay Timing Waveform

SM_CLK

TAA

DATA VALID

SM_DAT

DATA OUTPUT

Table 2-30. FLASHROM Signal Group AC Timing Specifications

Symbol

Parameter

Min

Max

Unit

Figure

Notes

0

66.67

MHz

F

FLASHROM_CLK Frequency

FLASHROM_DATI Edge Rate

FLASHROM

0.5

0.7

10

V/ns

ns

1

2

Slew

DATAI

DATAO

FLASHROM_DATO Edge Rate

2.3

FLASHROM_CS[3:0]_N assertion

before first FLASHROM_CLK

2-16

t

CS_AS

FLASHROM_CS[3:0]_N deassertion

after last FLASHROM_CLK

12

ns

CS_DE

FLASHROM_DATI setup time

FLASHROM_DATI hold time

FLASHROM_DATO Valid Delay

6

0

ns

2-16

t

SETUP

HOLD

–2.0

2.0

DELAY

Notes:

1.

All input edge rates are specified between V (max) and V (min), and output edge rates are specified

between V (max) and V (min).

IL IH

OL

OH

2.

These values are based on driving a 50Ω transmission line into a 50Ω±pullup.

Datasheet Volume 1 of 2

47

Electrical Specifications

Figure 2-16. FLASHROM Timing Waveform

FLASHROM_CS

t_{CS_AS}

t_{CS_DE}

FLASHROM_CLK

FLASHROM_DATO

FLASHROM_DATI

t_DELAY

t_SETUP

t_HOLD

Table 2-31.TAP Signal Group AC Timing Specifications

Notes

1, 2

Symbol

Parameter

Min

Max

Unit

Figure

Transmitter and Receiver Timings

F

T

TCK Frequency

66

MHz

2-17

3

TAP

TCK Period

15

7.5

30

ns

p

TDI, TMS Setup Time

TDI, TMS Hold Time

TDO Clock to Output Delay

TRST_N Assert Time

2-17

2-18

4, 5

4, 6

6

S

H

24

X

7

Notes:

1.

2.

3.

4.

5.

Not 100% tested. These parameters are based on design characterization.

It is recommended that TMS be asserted while TRST_N is being deasserted.

This specification is based on the capabilities of the ITP-XDP debug port tool, not on processor silicon.

Referenced to the rising edge of TCK.

Specification for a minimum swing defined between TAP V to V . This assumes a minimum edge rate of

0.5 V/ns.

T-

T+

6.

7.

Referenced to the falling edge of TCK.

TRST_N must be held asserted for 2 TCK periods to be guaranteed that it is recognized by the processor.

Figure 2-17. TAP Valid Delay Timing Waveform

Tp

V

TCK

Tx

Ts

Th

V

Valid

Signal

Tp = TAP Frequency

Tx = TDO Clock to Output Delay

Ts = TDI, TMS Setup Time

Th = TDI, TMS Hold Time

V = 0.5 * VIO

48

Datasheet Volume 1 of 2

Electrical Specifications

Figure 2-18. Test Reset (TRST_N), Force_PR_N, RESET_N and PROCHOT_N Pulse Width

Waveform

V

T_q= Pulse Width

T_q

V = 0.5*VCCIO

2.9

Processor AC Timing Waveforms

The following figures are used in conjunction with the AC timing tables, Table 2-26

through Table 2-28.

Note:

For Figure 2-21 through Figure 2-29, the following apply:

• All common clock AC timings signals are referenced to the Crossing Voltage

(V_CROSS) of the SYSCLK_DP, SYSCLK_DN at rising edge of SYSCLK_DP.

• All source synchronous AC timings are referenced to their associated strobe

(address or data). Source synchronous data signals are referenced to the falling

edge of their associated data strobe. Source synchronous address signals are

referenced to the rising and falling edge of their associated address strobe.

• All AC timings for the TAP signals are referenced to the TCK at 0.5 * V_IOat the

processor lands. All TAP signal timings (TMS, TDI, and so on) are referenced at 0.5

* V_IOat the processor die (pads).

• All CMOS signal timings are referenced at 0.5 * V_IOat the processor lands.

The Intel QPI electrical test setup are shown in figures Figure 2-19 and Figure 2-20.

Figure 2-19. Intel QPI System Interface Electrical Test Setup for Validating

Standalone TX Voltage and Timing Parameters

Ideal Loads

Silicon TX

Tx Package

SI Tx pin terminations are set to optimum values

(targeted around 42.5 ohms single-ended)

Datasheet Volume 1 of 2

49

Electrical Specifications

Figure 2-20. Intel QPI System Interface Electrical Test Setup for Validating

TX + Worst-Case Interconnect Specifications

W o rs t-C a s e In te rc o n n e c t

Id e a l

L o a d s

S ilic o n

T x b it

(D a ta )

T x

P a c k a g e

Id e a l

L o a d s

S ilic o n

T x b it

(C lo c k )

L o s s le s s In te rc o n n e c t P h a s e

M a tc h e d to D a ta B it In te rc o n n e c t

Figure 2-21. Differential Clock Waveform

Overshoot

BCLK1

VH

Rising Edge

Ringback

Crossing

Voltage

Crossing

Voltage

Ringback

Margin

Threshold

Region

Falling Edge

Ringback,

BCLK0

VL

Undershoot

Tp

Tp = T1: BCLK[1:0] period

50

Datasheet Volume 1 of 2

Electrical Specifications

Figure 2-22. Differential Clock Crosspoint Specification

650

600

550

500

550 mV

550 + 0.5 (VHavg - 700)

450

400

250 + 0.5 (VHavg - 700)

350

300

250

200

250 mV

660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850

VHavg (mV)

Figure 2-23. System Common Clock Valid Delay Timing Waveform

T0

T1

T2

BCLK1

BCLK0

T_P

Common Clock

Signal (@ driver)

valid

T_Q

T_R

Common Clock

Signal (@ receiver)

valid

T_P= T10: Common Clock Output Valid Delay

T_Q= T11: Common Clock Input Setup

T_R= T12: Common Clock Input Hold Time

Figure 2-24. Differential Measurement Point for Ringback

Datasheet Volume 1 of 2

51

Electrical Specifications

Figure 2-25. Differential Measurement Points for Rise and Fall time

Figure 2-26. Single-Ended Measurement Points for Absolute Cross Point and Swing

Figure 2-27. Single-Ended Measurement Points for Delta Cross Point

52

Datasheet Volume 1 of 2

Electrical Specifications

Figure 2-28. Voltage Sequence Timing Requirements

G R O O W P D

b t e g a m t e u d s b y g i V n I a O l s e n s d r i v t i v e a l c y

5

V C t C o I O e i d ; t e t o b n e s e p d l l - u u p e v s i t s i e

V C o C v I e O . R e n i v r a b d t b o e s t n m u p i n s e t d a l e r V i o

Datasheet Volume 1 of 2

53

Electrical Specifications

Note:

1.

3.3 V supplies power to on-package parts, including the PIROM/OEM scratch pad. 3.3V must be up at a

minimum of 100ms before PWRGOOD is asserted.

2.

SKTOCC_N is pulled to an appropriate platform rail; when socket is occupied, package pulls the signal to

VSS. Here, SKTOCC_N is assumed pulled to 3.3 V.

3.

4.

VIOVIDs are pulled up to an appropriate platform rail. The package pulls appropriate VIO VIDs to VSS.

For integrated memory, Millbrook is sequenced after VIO is true. System implementation decides whether

installed hot plug memory cards are sequenced with or after system power is up.

SMB, SM_WP, SPD, SKTID inputs/bidir are 3.3 V-rail related pins. All other misc IO are VIO-related,

including other strapping pins (BOOTMODE pins), INT and error (BIDIR). Vio related pins must not be

driven above VCCIO. Resistive pull-ups need to be tied to VCCIO; actively driven signals must be gated by

VIOPWRGOOD.

5.

6.

7.

8.

Weak pullups/downs assumed on VID pins, for VID POC sampling.

Reset_N is an asynchronous input for normal production usage.

SKTID must be valid with 3.3V for proper PIROM/OEM scratch pad addressing and must stay valid. SKTID is

latched by processor only on a PWRGOOD toggle. SKTID must be driven valid before the assertion of

PWRGOOD on a cold-reset.

9.

RESET straps: During all resets, reset-latched straps must meet the following setup and hold. Cold reset:

Must be stable 2 bclks prior to assertion of PWRGOOD and Reset Warm reset: Must be stable 2 bclks prior

to assertion of Reset Hold time: Must be stable 108 bclks hold after deassertion of Reset. Reset-latched

®

straps include BOOTMODE, Intel Trusted Execution Technology for Servers, FLASHROM_CFG[2:0],

SKTDIS_N, and RUNBIST. BOOTMODE & Intel TXT pins are latched only after a processor cold-reset (that

is, system power-up or PWRGOOD-reset). RUNBIST: Is reset-deassertion latched. It is a dynamic signal.

(system can assert, during runtime but must meet reset setup/hold requirements).

10. SKTDIS_N has no affect on inputs. It also has no impact to SMB pins and package-strapped pins

(SKTOCC_N, PROCID_N). The following outputs are not tri-stated by SKTDIS#: TDO, PSI_N,

PSI_CACHE_N, VIDs, and CVIDs. SKTDIS_N is transparent while reset is asserted. SKTDIS_N is latched at

reset assertion. NOTE: SKTDIS_N has no impact on internal logic (logic is not disabled). A PWRGOOD-reset

might be required when the SKT is "enabled" again.

11. * indicates a VR11.1 value.

12. Suggested normal power down should have the opposite sequence. At the minimum, Intel Xeon Processor

E7-8800/4800/2800 Product Families processor VRs can be disabled in parallel subject to the power rail’s

capacitive drain time.

13. In order to ensure Timestamp Counter (TSC) synchronization across sockets in multi-socket systems, the

RESET# de-assertion edge should arrive at the same BCLK rising edge on all sockets and should meet Tsu

(setup) and Th (hold) requirements. This is relative to the first cold reset in the system. The delay from

cold to any warm reset needs to be the same on each socket.

Figure 2-29. VID Step Times and Vcc Waveforms

54

Datasheet Volume 1 of 2

Electrical Specifications

2.10

2.11

Flexible Motherboard Guidelines

The Flexible Motherboard (FMB) guidelines are estimates of the maximum ratings that

the Intel Xeon Processor E7-8800/4800/2800 Product Families processor will have over

certain time periods. The ratings are only estimates as actual specifications for future

processors may differ. The VR 11.1 specification is developed to meet FMB Voltage

Specification values required by all Intel Xeon Processor E7-8800/4800/2800 Product

Families processor SKUs.

Reserved (RSVD) or Unused Signals

All Reserved signals must be left unconnected on the motherboard. Any deviation in

connection of these signals to any power rail or other signals can result in component

malfunction or incompatibility with future processors. See Chapter 4 for socket land

listing of the processor and the location of all signals, including RSVD signals.

Unused Intel QPI or Intel SMI input ports may be left as no-connects.

2.12

2.13

Test Access Port Connection

The recommended TAP connectivity will be detailed in an upcoming document release.

Mixing Processors

Intel supports and validates multiple processor configurations only in which all

processors operate with the same Intel QPI frequency, core frequency, power segment,

have the same number of cores, and have the same internal cache sizes. Mixing

components operating at different internal clock frequencies is not supported and will

not be validated by Intel. Combining processors from different power segments is also

not supported.

2.14

Processor SPD Interface

The processor SPD Interface is used for memory initialization including the set up and

use of the memory thermal sensor on-board the Intel^®7500 scalable memory buffer.

Base board management controllers (BMC) can use the PECI interface to the SPD

engine for access to this thermal data.

The SPD master in the processor supports 100 kHz operation and the following set of

commands:

Send Byte and Receive Byte

Write Byte and Read Byte

Write Word and Read Word

The SPD Interface does not support bus arbitration or clock stretching.

§

Datasheet Volume 1 of 2

55

Electrical Specifications

56

Datasheet Volume 1 of 2

Processor Package Mechanical Specifications

3 Processor Package Mechanical

Specifications

3.1

Package Mechanical Specifications

The processor is packaged in a Flip-Chip Land Grid Array (FC-LGA8) package that

interfaces with the motherboard via an LGA1567 socket. The package consists of a

processor mounted on a substrate land-carrier. An integrated heat spreader (IHS) is

attached to the package substrate and core and serves as the mating surface for

processor component thermal solutions, such as a heatsink. Figure 3-1 shows a sketch

of the processor package components and how they are assembled together.

Note:

Processor package mechanical information and drawings provided in this section are

preliminary and subject to change.

The package components shown in Figure 3-1 include the following:

1. Integrated Heat Spreader (IHS)

2. Processor core (die)

3. Package substrate

4. Capacitors

Figure 3-1. Processor Package Assembly Sketch

Die

IHS

Substrate

Capacitors

Socket

System Board

Note:

1.

Socket and motherboard are included for reference and are not part of processor package.

Datasheet Volume 1 of 2

57

Processor Package Mechanical Specifications

3.1.1

Package Mechanical Drawing

The package mechanical drawings are shown in Figure 3-2 and Figure 3-3. The

drawings include dimensions necessary to design a thermal solution for the processor.

All drawing dimensions are in mm. These dimensions include:

1. Package reference with tolerances (total height, length, width, etc.)

2. IHS parallelism and tilt

3. Land dimensions

4. Top-side and back-side component keep-out dimensions

5. Reference datums

58

Datasheet Volume 1 of 2

Processor Package Mechanical Specifications

Figure 3-2. Processor Package Drawing (Sheet 1 of 2)

Datasheet Volume 1 of 2

59

Processor Package Mechanical Specifications

Figure 3-3. Processor Package Drawing (Sheet 2 of 2)

60

Datasheet Volume 1 of 2

Processor Package Mechanical Specifications

3.1.2

3.1.3

Processor Component Keep-Out Zones

The processor may contain components on the substrate that define component

keep-out zone requirements. A thermal and mechanical solution design must not

intrude into the required keep-out zones. Decoupling capacitors are typically mounted

to either the topside or land-side of the package substrate. See Figure 3-2 and

Figure 3-3 for keep-out zones. The location and quantity of package capacitors may

change due to manufacturing efficiencies but will remain within the component keep-in.

Package Loading Specifications

Table 3-1 provides dynamic and static load specifications for the processor package.

These mechanical maximum load limits should not be exceeded during heatsink

assembly, shipping conditions, or standard use condition. Also, any mechanical system

or component testing should not exceed the maximum limits. The processor package

substrate should not be used as a mechanical reference or load-bearing surface for

thermal and mechanical solution. The minimum loading specification must be

maintained by any thermal and mechanical solutions.

.

Table 3-1.

Processor Loading Specifications

Parameter

Maximum

Notes

755 N

Allowable load on the package IHS

See notes 1, 2, 3

Static Compressive Load

Dynamic Compressive Load

Transient Bend Load

490 N

778 N

See notes 1, 3, 4

See note 4

Notes:

1.

2.

These specifications apply to uniform compressive loading in a direction normal to the processor IHS.

This is the maximum static force that can be applied by the heatsink and retention solution to maintain the

heatsink and processor interface.

3.

4.

These specifications are based on limited testing for design characterization. Loading limits are for the

package only and do not include the limits of the processor socket.

Dynamic loading is defined as an 11-ms duration average load superimposed on the static load

requirement.

3.1.4

Package Handling Guidelines

Table 3-2 includes a list of guidelines on package handling in terms of recommended

maximum loading on the processor IHS relative to a fixed substrate. These package

handling loads may be experienced during heatsink removal.

Table 3-2.

Package Handling Guidelines

Parameter

Maximum

Notes

Shear

Tensile

Torque

355 N

155 N

7.9 N-m

3.1.5

Package Insertion Specifications

The processor can be inserted into and removed from an LGA1567 socket 15 times.

Datasheet Volume 1 of 2

61

Processor Package Mechanical Specifications

3.1.6

Processor Mass Specification

The typical mass of the processor is ~40g. This mass [weight] includes all the

components that are included in the package.

3.1.7

Processor Materials

Table 3-3 lists some of the package components and associated materials.

Table 3-3.

Processor Materials

Component

Material

Nickel Plated Copper

Integrated Heat Spreader (IHS)

Substrate

Fiber Reinforced Resin

Gold Plated Copper

Substrate Lands

3.1.8

Processor Markings

Figure 3-4 shows the topside markings on the processor. This diagram is to aid in the

identification of the processor.

Figure 3-4. Processor Top-Side Markings

APO Serial Number

Table 3-4.

Mark Content

Mark ID

Value

Notes

Line 1

Line 2

Line 3

INTEL [m] [c] ‘YY

SUB-BRAND

SSPEC - SUB BRAND

SSPEC XXXXX

S-SPEC: Product Specification Number

XXXXX: Country of Origin

Line 4

Line 5

PROC# FREQ/CACHE/INTC

{FPO} {e4}

INTC: Processor Interconnect Speed

{Final Process Order Number} {Lead free}

2D Matrix

PROC# S-SPEC FPO SN

62

Datasheet Volume 1 of 2

Processor Package Mechanical Specifications

3.1.9

Processor Land Coordinates

Figure 3-5 shows the top view of the processor land coordinates. The coordinates are

referred to throughout the document to identify processor lands.

.

Figure 3-5. Processor Land Coordinates and Quadrants, Top View

BM

A

1

46

§

Datasheet Volume 1 of 2

63

Processor Package Mechanical Specifications

64

Datasheet Volume 1 of 2

Pin Listing

4 Pin Listing

4.1

Processor Package Bottom Land Assignments

This section provides a sorted package bottom pin list in Table 4-1 and Table 4-2.

Table 4-1 is a listing of all processor package bottom side lands ordered alphabetically

by socket name, and Table 4-2 is a listing ordered by land number.

4.1.1

Processor Pin List, Sorted by Socket Name

Table 4-1.

Pin List, Sorted by Socket

Name (Sheet 2 of 39)

Table 4-1.

Pin List, Sorted by Socket

Name (Sheet 1 of 39)

Socket (EMTS)

Land #

Format

IO

Socket (EMTS)

Land #

Format

GTL

IO

FBD0NBIAP[13]

FBD0NBIAP[2]

FBD0NBIAP[3]

FBD0NBIAP[4]

FBD0NBIAP[5]

FBD0NBIAP[6]

FBD0NBIAP[7]

FBD0NBIAP[8]

FBD0NBIAP[9]

FBD0NBIBN[0]

FBD0NBIBN[1]

FBD0NBIBN[10]

FBD0NBIBN[11]

FBD0NBIBN[12]

FBD0NBIBN[13]

FBD0NBIBN[2]

FBD0NBIBN[3]

FBD0NBIBN[4]

FBD0NBIBN[5]

FBD0NBIBN[6]

FBD0NBIBN[7]

FBD0NBIBN[8]

FBD0NBIBN[9]

FBD0NBIBP[0]

FBD0NBIBP[1]

FBD0NBIBP[10]

FBD0NBIBP[11]

FBD0NBIBP[12]

FBD0NBIBP[13]

FBD0NBIBP[2]

BL8

BG8

BM10

BM9

BK10

BH5

BG6

BE7

BE5

BG4

BK6

BC4

BC3

BH2

BK2

BL6

BM5

BK5

BJ4

Differential

I

BOOTMODE[0]

BOOTMODE[1]

CVID[1]

BH10

BH11

BL16

BK16

BJ16

BM17

BL17

BM18

BL18

G3

I

GTL

I

CMOS

O

IO

I

CVID[2]

CMOS

CVID[3]

CMOS

CVID[4]

CMOS

CVID[5]

CMOS

CVID[6]

CMOS

CVID[7]

CMOS

ERROR0_N

GTL OD

ERROR1_N

G4

GTL OD

FBD0NBIAN[0]

FBD0NBIAN[1]

FBD0NBIAN[10]

FBD0NBIAN[11]

FBD0NBIAN[12]

FBD0NBIAN[13]

FBD0NBIAN[2]

FBD0NBIAN[3]

FBD0NBIAN[4]

FBD0NBIAN[5]

FBD0NBIAN[6]

FBD0NBIAN[7]

FBD0NBIAN[8]

FBD0NBIAN[9]

FBD0NBIAP[0]

FBD0NBIAP[1]

FBD0NBIAP[10]

FBD0NBIAP[11]

FBD0NBIAP[12]

BE8

Differential

BF8

I

BC6

BC8

BH6

BK8

BH8

BL10

BM8

BK9

BG5

BF6

I

BG1

BF1

BE3

BD2

BF4

BJ6

I

BE6

I

BD5

BD8

BF9

I

BD4

BC2

BJ2

I

BD6

BC7

BH7

I

BK3

BL7

I

Datasheet Volume 1 of 2

65

Pin Listing

Table 4-1.

Pin List, Sorted by Socket

Name (Sheet 3 of 39)

Table 4-1.

Pin List, Sorted by Socket

Name (Sheet 4 of 39)

Socket (EMTS)

Land #

Format

IO

Socket (EMTS)

Land #

Format

IO

FBD0NBIBP[3]

FBD0NBIBP[4]

FBD0NBIBP[5]

FBD0NBIBP[6]

FBD0NBIBP[7]

FBD0NBIBP[8]

FBD0NBIBP[9]

FBD0NBICLKAN0

FBD0NBICLKAP0

FBD0NBICLKBN0

FBD0NBICLKBP0

FBD0SBOAN[0]

FBD0SBOAN[1]

FBD0SBOAN[10]

FBD0SBOAN[2]

FBD0SBOAN[3]

FBD0SBOAN[4]

FBD0SBOAN[5]

FBD0SBOAN[6]

FBD0SBOAN[7]

FBD0SBOAN[8]

FBD0SBOAN[9]

FBD0SBOAP[0]

FBD0SBOAP[1]

FBD0SBOAP[10]

FBD0SBOAP[2]

FBD0SBOAP[3]

FBD0SBOAP[4]

FBD0SBOAP[5]

FBD0SBOAP[6]

FBD0SBOAP[7]

FBD0SBOAP[8]

FBD0SBOAP[9]

FBD0SBOBN[0]

FBD0SBOBN[1]

FBD0SBOBN[10]

FBD0SBOBN[2]

FBD0SBOBN[3]

FBD0SBOBN[4]

FBD0SBOBN[5]

FBD0SBOBN[6]

BM6

BL5

BK4

BH1

BF2

BE4

BE2

BJ8

Differential

I

FBD0SBOBN[7]

FBD0SBOBN[8]

FBD0SBOBN[9]

FBD0SBOBP[0]

FBD0SBOBP[1]

FBD0SBOBP[10]

FBD0SBOBP[2]

FBD0SBOBP[3]

FBD0SBOBP[4]

FBD0SBOBP[5]

FBD0SBOBP[6]

FBD0SBOBP[7]

FBD0SBOBP[8]

FBD0SBOBP[9]

FBD0SBOCLKAN0

FBD0SBOCLKAP0

FBD0SBOCLKBN0

FBD0SBOCLKBP0

FBD1NBICLKCN0

FBD1NBICLKCP0

FBD1NBICLKDN0

FBD1NBICLKDP0

FBD1NBICN[0]

FBD1NBICN[1]

FBD1NBICN[10]

FBD1NBICN[11]

FBD1NBICN[12]

FBD1NBICN[13]

FBD1NBICN[2]

FBD1NBICN[3]

FBD1NBICN[4]

FBD1NBICN[5]

FBD1NBICN[6]

FBD1NBICN[7]

FBD1NBICN[8]

FBD1NBICN[9]

FBD1NBICP[0]

FBD1NBICP[1]

FBD1NBICP[10]

FBD1NBICP[11]

FBD1NBICP[12]

AM1

AP3

AR4

AV4

AY4

AN4

AY2

AW1

AV2

AR1

AP2

AN1

AR3

AT4

AU5

AT5

AU3

AU4

AB5

AC5

AB2

AC2

AC8

AD8

V8

Differential

O

I

BJ9

I

BH3

BH4

BA5

AY7

AW8

AW5

AV6

AU7

AT8

AP7

AN6

AP8

AR6

BA6

AY8

AV8

AY5

AW6

AV7

AT7

AP6

AN5

AR8

AT6

AW4

AY3

AM4

AW2

AV1

AV3

AR2

AN2

I

O

I

Y8

I

AA6

AC6

AE8

AF6

AE5

AD6

AA8

W5

I

Y7

I

U6

I

AB8

AD9

V7

I

W8

I

AB6

I

66

Datasheet Volume 1 of 2

Pin Listing

Table 4-1.

Pin List, Sorted by Socket

Name (Sheet 5 of 39)

Table 4-1.

Pin List, Sorted by Socket

Name (Sheet 6 of 39)

Socket (EMTS)

Land #

Format

IO

Socket (EMTS)

Land #

P5

Format

IO

FBD1NBICP[13]

FBD1NBICP[2]

FBD1NBICP[3]

FBD1NBICP[4]

FBD1NBICP[5]

FBD1NBICP[6]

FBD1NBICP[7]

FBD1NBICP[8]

FBD1NBICP[9]

FBD1NBIDN[0]

FBD1NBIDN[1]

FBD1NBIDN[10]

FBD1NBIDN[11]

FBD1NBIDN[12]

FBD1NBIDN[13]

FBD1NBIDN[2]

FBD1NBIDN[3]

FBD1NBIDN[4]

FBD1NBIDN[5]

FBD1NBIDN[6]

FBD1NBIDN[7]

FBD1NBIDN[8]

FBD1NBIDN[9]

FBD1NBIDP[0]

FBD1NBIDP[1]

FBD1NBIDP[10]

FBD1NBIDP[11]

FBD1NBIDP[12]

FBD1NBIDP[13]

FBD1NBIDP[2]

FBD1NBIDP[3]

FBD1NBIDP[4]

FBD1NBIDP[5]

FBD1NBIDP[6]

FBD1NBIDP[7]

FBD1NBIDP[8]

FBD1NBIDP[9]

FBD1SBOCLKCN0

FBD1SBOCLKCP0

FBD1SBOCLKDN0

FBD1SBOCLKDP0

AC7

AF8

AF7

AF5

AE6

AA7

Y5

Differential

I

O

FBD1SBOCN[0]

FBD1SBOCN[1]

FBD1SBOCN[10]

FBD1SBOCN[2]

FBD1SBOCN[3]

FBD1SBOCN[4]

FBD1SBOCN[5]

FBD1SBOCN[6]

FBD1SBOCN[7]

FBD1SBOCN[8]

FBD1SBOCN[9]

FBD1SBOCP[0]

FBD1SBOCP[1]

FBD1SBOCP[10]

FBD1SBOCP[2]

FBD1SBOCP[3]

FBD1SBOCP[4]

FBD1SBOCP[5]

FBD1SBOCP[6]

FBD1SBOCP[7]

FBD1SBOCP[8]

FBD1SBOCP[9]

FBD1SBODN[0]

FBD1SBODN[1]

FBD1SBODN[10]

FBD1SBODN[2]

FBD1SBODN[3]

FBD1SBODN[4]

FBD1SBODN[5]

FBD1SBODN[6]

FBD1SBODN[7]

FBD1SBODN[8]

FBD1SBODN[9]

FBD1SBODP[0]

FBD1SBODP[1]

FBD1SBODP[10]

FBD1SBODP[2]

FBD1SBODP[3]

FBD1SBODP[4]

FBD1SBODP[5]

FBD1SBODP[6]

Differential

O

N6

R8

M6

L5

L8

H7

J8

Y6

V6

N8

R7

H5

R5

P6

P8

M7

M5

L7

AB4

AE4

U4

W4

AA1

AC3

AG2

AF3

AE2

AD1

Y3

H6

K8

N7

R6

J5

W2

V1

V3

P2

N1

R4

N3

L1

AA4

AD4

U3

V4

AB1

AD3

AG3

AF4

AF2

AD2

Y4

K2

H2

J4

M4

P4

H3

R2

P1

R3

N2

L2

Y2

W1

V2

K6

J6

K3

H1

K4

K1

J1

Datasheet Volume 1 of 2

67

Pin Listing

Table 4-1.

Pin List, Sorted by Socket

Name (Sheet 7 of 39)

Table 4-1.

Pin List, Sorted by Socket

Name (Sheet 8 of 39)

Socket (EMTS)

Land #

Format

IO

Socket (EMTS)

Land #

Format

IO

FBD1SBODP[7]

FBD1SBODP[8]

FBD1SBODP[9]

FLASHROM_CFG[0]

FLASHROM_CFG[1]

FLASHROM_CFG[2]

FLASHROM_CLK

FLASHROM_CS_N[0]

FLASHROM_CS_N[1]

FLASHROM_CS_N[2]

FLASHROM_CS_N[3]

FLASHROM_DATI

FLASHROM_DATO

FLASHROM_WP_N

FORCE_PR_N

ISENSE_DN

M3

Differential

GTL

O

QPI0_CLKTX_DP

QPI0_DRX_DN[0]

QPI0_DRX_DN[1]

QPI0_DRX_DN[10]

QPI0_DRX_DN[11]

QPI0_DRX_DN[12]

QPI0_DRX_DN[13]

QPI0_DRX_DN[14]

QPI0_DRX_DN[15]

QPI0_DRX_DN[16]

QPI0_DRX_DN[17]

QPI0_DRX_DN[18]

QPI0_DRX_DN[19]

QPI0_DRX_DN[2]

QPI0_DRX_DN[3]

QPI0_DRX_DN[4]

QPI0_DRX_DN[5]

QPI0_DRX_DN[6]

QPI0_DRX_DN[7]

QPI0_DRX_DN[8]

QPI0_DRX_DN[9]

QPI0_DRX_DP[0]

QPI0_DRX_DP[1]

QPI0_DRX_DP[10]

QPI0_DRX_DP[11]

QPI0_DRX_DP[12]

QPI0_DRX_DP[13]

QPI0_DRX_DP[14]

QPI0_DRX_DP[15]

QPI0_DRX_DP[16]

QPI0_DRX_DP[17]

QPI0_DRX_DP[18]

QPI0_DRX_DP[19]

QPI0_DRX_DP[2]

QPI0_DRX_DP[3]

QPI0_DRX_DP[4]

QPI0_DRX_DP[5]

QPI0_DRX_DP[6]

QPI0_DRX_DP[7]

QPI0_DRX_DP[8]

QPI0_DRX_DP[9]

BM41

BB38

AY41

BE35

BG35

BJ33

BM33

BL32

BH33

BG33

BF32

BE33

BD34

BA40

BC39

BC41

BD40

BC36

BF40

BE39

BD37

BB39

BA41

BF35

BG34

BK33

BM32

BK32

BH32

BF33

BE32

BE34

BD35

BB40

BC40

BD41

BE40

BD36

BF39

BE38

BE37

SCID Diff.

O

I

N4

O

J3

O

BL15

BM15

BJ15

BL11

BK13

BM13

BL14

BM14

BL12

BM12

BK11

C4

I

GTL

I

GTL

I

GTL

OD

I

GTL

OD

I

GTL

B5

GTL

I

ISENSE_DP

A5

GTL

I

LT-SX (Test-Lo)

MBP[0]_N

BF10

G2

GTL

I

GTL

IO

I

MBP[1]_N

F2

GTL

MBP[2]_N

F1

GTL

MBP[3]_N

E2

GTL

MBP[4]_N

F4

GTL

MBP[5]_N

E3

GTL

MBP[6]_N

E1

GTL

MBP[7]_N

E4

GTL

MEM_THROTTLE0_N

MEM_THROTTLE1_N

NMI

BC10

BD10

D5

GTL

I

GTL

I

PECI

D43

C3

CMOS

GTL

IO

O

PRDY_N

PREQ_N

D3

I

Proc_ID[0]

AW9

AY9

D2

O

Proc_ID[1]

O

PROCHOT_N

OD

O

PSI_CACHE_N

PSI_N

BF14

G7

CMOS

SCID Diff.

O

PWRGOOD

G41

BF37

BF36

BL41

I

QPI0_CLKRX_DN

QPI0_CLKRX_DP

QPI0_CLKTX_DN

I

O

68

Datasheet Volume 1 of 2

Pin Listing

Table 4-1.

Pin List, Sorted by Socket

Name (Sheet 9 of 39)

Table 4-1.

Pin List, Sorted by Socket

Name (Sheet 10 of 39)

Socket (EMTS)

Land #

Format

IO

Socket (EMTS)

Land #

Format

IO

QPI0_DTX_DN[0]

QPI0_DTX_DN[1]

QPI0_DTX_DN[10]

QPI0_DTX_DN[11]

QPI0_DTX_DN[12]

QPI0_DTX_DN[13]

QPI0_DTX_DN[14]

QPI0_DTX_DN[15]

QPI0_DTX_DN[16]

QPI0_DTX_DN[17]

QPI0_DTX_DN[18]

QPI0_DTX_DN[19]

QPI0_DTX_DN[2]

QPI0_DTX_DN[3]

QPI0_DTX_DN[4]

QPI0_DTX_DN[5]

QPI0_DTX_DN[6]

QPI0_DTX_DN[7]

QPI0_DTX_DN[8]

QPI0_DTX_DN[9]

QPI0_DTX_DP[0]

QPI0_DTX_DP[1]

QPI0_DTX_DP[10]

QPI0_DTX_DP[11]

QPI0_DTX_DP[12]

QPI0_DTX_DP[13]

QPI0_DTX_DP[14]

QPI0_DTX_DP[15]

QPI0_DTX_DP[16]

QPI0_DTX_DP[17]

QPI0_DTX_DP[18]

QPI0_DTX_DP[19]

QPI0_DTX_DP[2]

QPI0_DTX_DP[3]

QPI0_DTX_DP[4]

QPI0_DTX_DP[5]

QPI0_DTX_DP[6]

QPI0_DTX_DP[7]

QPI0_DTX_DP[8]

QPI0_DTX_DP[9]

QPI1_CLKRX_DN

BG42

BF43

BJ41

BL40

BK39

BL37

BK37

BM36

BL35

BJ36

BJ37

BH39

BF44

BF46

BH43

BH45

BJ43

BK45

BK42

BL43

BH42

BG43

BJ40

BL39

BJ39

BM37

BK36

BM35

BK35

BJ35

BH37

BH40

BF45

BG46

BH44

BJ45

BK43

BK44

BK41

BL42

AP41

SCID Diff.

O

I

QPI1_CLKRX_DP

QPI1_CLKTX_DN

QPI1_CLKTX_DP

QPI1_DRX_DN[0]

QPI1_DRX_DN[1]

QPI1_DRX_DN[10]

QPI1_DRX_DN[11]

QPI1_DRX_DN[12]

QPI1_DRX_DN[13]

QPI1_DRX_DN[14]

QPI1_DRX_DN[15]

QPI1_DRX_DN[16]

QPI1_DRX_DN[17]

QPI1_DRX_DN[18]

QPI1_DRX_DN[19]

QPI1_DRX_DN[2]

QPI1_DRX_DN[3]

QPI1_DRX_DN[4]

QPI1_DRX_DN[5]

QPI1_DRX_DN[6]

QPI1_DRX_DN[7]

QPI1_DRX_DN[8]

QPI1_DRX_DN[9]

QPI1_DRX_DP[0]

QPI1_DRX_DP[1]

QPI1_DRX_DP[10]

QPI1_DRX_DP[11]

QPI1_DRX_DP[12]

QPI1_DRX_DP[13]

QPI1_DRX_DP[14]

QPI1_DRX_DP[15]

QPI1_DRX_DP[16]

QPI1_DRX_DP[17]

QPI1_DRX_DP[18]

QPI1_DRX_DP[19]

QPI1_DRX_DP[2]

QPI1_DRX_DP[3]

QPI1_DRX_DP[4]

QPI1_DRX_DP[5]

QPI1_DRX_DP[6]

QPI1_DRX_DP[7]

AR41

AY45

AY46

AN38

AM37

AR40

AU39

AU41

AV40

AW39

AY40

AV38

BA38

AT39

AR38

AJ37

AK38

AH41

AJ40

AL39

AL41

AM40

AP39

AN39

AM38

AT40

AU40

AV41

AW40

AW38

AY39

AV37

BA37

AT38

AR37

AJ38

AK39

AJ41

AK40

AL40

AM41

SCID Diff.

I

O

I

Datasheet Volume 1 of 2

69

Pin Listing

Table 4-1.

Pin List, Sorted by Socket

Name (Sheet 11 of 39)

Table 4-1.

Pin List, Sorted by Socket

Name (Sheet 12 of 39)

Socket (EMTS)

Land #

Format

IO

Socket (EMTS)

Land #

Format

IO

QPI1_DRX_DP[8]

QPI1_DRX_DP[9]

QPI1_DTX_DN[0]

QPI1_DTX_DN[1]

QPI1_DTX_DN[10]

QPI1_DTX_DN[11]

QPI1_DTX_DN[12]

QPI1_DTX_DN[13]

QPI1_DTX_DN[14]

QPI1_DTX_DN[15]

QPI1_DTX_DN[16]

QPI1_DTX_DN[17]

QPI1_DTX_DN[18]

QPI1_DTX_DN[19]

QPI1_DTX_DN[2]

QPI1_DTX_DN[3]

QPI1_DTX_DN[4]

QPI1_DTX_DN[5]

QPI1_DTX_DN[6]

QPI1_DTX_DN[7]

QPI1_DTX_DN[8]

QPI1_DTX_DN[9]

QPI1_DTX_DP[0]

QPI1_DTX_DP[1]

QPI1_DTX_DP[10]

QPI1_DTX_DP[11]

QPI1_DTX_DP[12]

QPI1_DTX_DP[13]

QPI1_DTX_DP[14]

QPI1_DTX_DP[15]

QPI1_DTX_DP[16]

QPI1_DTX_DP[17]

QPI1_DTX_DP[18]

QPI1_DTX_DP[19]

QPI1_DTX_DP[2]

QPI1_DTX_DP[3]

QPI1_DTX_DP[4]

QPI1_DTX_DP[5]

QPI1_DTX_DP[6]

QPI1_DTX_DP[7]

QPI1_DTX_DP[8]

AN40

AP40

AT43

AR43

BA44

BA46

BB44

BC45

BD45

BC43

BE44

BA43

AW44

AV43

AN43

AM45

AP45

AR44

AR46

AU45

AV44

AV46

AT44

AP43

BA45

BB46

BB43

BC44

BE45

BD43

BE43

AY43

AW43

AU43

AN44

AM44

AP46

AR45

AT46

AU46

AV45

SCID Diff.

I

QPI1_DTX_DP[9]

QPI2_CLKRX_DN

QPI2_CLKRX_DP

QPI2_CLKTX_DN

QPI2_CLKTX_DP

QPI2_DRX_DN[0]

QPI2_DRX_DN[1]

QPI2_DRX_DN[10]

QPI2_DRX_DN[11]

QPI2_DRX_DN[12]

QPI2_DRX_DN[13]

QPI2_DRX_DN[14]

QPI2_DRX_DN[15]

QPI2_DRX_DN[16]

QPI2_DRX_DN[17]

QPI2_DRX_DN[18]

QPI2_DRX_DN[19]

QPI2_DRX_DN[2]

QPI2_DRX_DN[3]

QPI2_DRX_DN[4]

QPI2_DRX_DN[5]

QPI2_DRX_DN[6]

QPI2_DRX_DN[7]

QPI2_DRX_DN[8]

QPI2_DRX_DN[9]

QPI2_DRX_DP[0]

QPI2_DRX_DP[1]

QPI2_DRX_DP[10]

QPI2_DRX_DP[11]

QPI2_DRX_DP[12]

QPI2_DRX_DP[13]

QPI2_DRX_DP[14]

QPI2_DRX_DP[15]

QPI2_DRX_DP[16]

QPI2_DRX_DP[17]

QPI2_DRX_DP[18]

QPI2_DRX_DP[19]

QPI2_DRX_DP[2]

QPI2_DRX_DP[3]

QPI2_DRX_DP[4]

QPI2_DRX_DP[5]

AW46

AB40

AB39

AE44

AE45

AC37

AD38

AA40

Y41

SCID Diff.

O

I

O

I

O

W40

V40

U41

T40

V39

V37

Y38

AA37

AF37

AG38

AH40

AG40

AF41

AE40

AD40

AC41

AC38

AD39

Y40

W41

W39

U40

T41

T39

V38

U37

Y37

AB37

AF38

AG39

AH39

AF40

70

Datasheet Volume 1 of 2

Pin Listing

Table 4-1.

Pin List, Sorted by Socket

Name (Sheet 13 of 39)

Table 4-1.

Pin List, Sorted by Socket

Name (Sheet 14 of 39)

Socket (EMTS)

Land #

Format

IO

Socket (EMTS)

Land #

Format

IO

QPI2_DRX_DP[6]

QPI2_DRX_DP[7]

QPI2_DRX_DP[8]

QPI2_DRX_DP[9]

QPI2_DTX_DN[0]

QPI2_DTX_DN[1]

QPI2_DTX_DN[10]

QPI2_DTX_DN[11]

QPI2_DTX_DN[12]

QPI2_DTX_DN[13]

QPI2_DTX_DN[14]

QPI2_DTX_DN[15]

QPI2_DTX_DN[16]

QPI2_DTX_DN[17]

QPI2_DTX_DN[18]

QPI2_DTX_DN[19]

QPI2_DTX_DN[2]

QPI2_DTX_DN[3]

QPI2_DTX_DN[4]

QPI2_DTX_DN[5]

QPI2_DTX_DN[6]

QPI2_DTX_DN[7]

QPI2_DTX_DN[8]

QPI2_DTX_DN[9]

QPI2_DTX_DP[0]

QPI2_DTX_DP[1]

QPI2_DTX_DP[10]

QPI2_DTX_DP[11]

QPI2_DTX_DP[12]

QPI2_DTX_DP[13]

QPI2_DTX_DP[14]

QPI2_DTX_DP[15]

QPI2_DTX_DP[16]

QPI2_DTX_DP[17]

QPI2_DTX_DP[18]

QPI2_DTX_DP[19]

QPI2_DTX_DP[2]

QPI2_DTX_DP[3]

QPI2_DTX_DP[4]

QPI2_DTX_DP[5]

QPI2_DTX_DP[6]

AE41

AE39

AC40

AB41

AE43

AH43

AD43

AD46

AC45

AB46

AA45

Y46

SCID Diff.

I

QPI2_DTX_DP[7]

QPI2_DTX_DP[8]

QPI2_DTX_DP[9]

QPI3_CLKRX_DN

QPI3_CLKRX_DP

QPI3_CLKTX_DN

QPI3_CLKTX_DP

QPI3_DRX_DN[0]

QPI3_DRX_DN[1]

QPI3_DRX_DN[10]

QPI3_DRX_DN[11]

QPI3_DRX_DN[12]

QPI3_DRX_DN[13]

QPI3_DRX_DN[14]

QPI3_DRX_DN[15]

QPI3_DRX_DN[16]

QPI3_DRX_DN[17]

QPI3_DRX_DN[18]

QPI3_DRX_DN[19]

QPI3_DRX_DN[2]

QPI3_DRX_DN[3]

QPI3_DRX_DN[4]

QPI3_DRX_DN[5]

QPI3_DRX_DN[6]

QPI3_DRX_DN[7]

QPI3_DRX_DN[8]

QPI3_DRX_DN[9]

QPI3_DRX_DP[0]

QPI3_DRX_DP[1]

QPI3_DRX_DP[10]

QPI3_DRX_DP[11]

QPI3_DRX_DP[12]

QPI3_DRX_DP[13]

QPI3_DRX_DP[14]

QPI3_DRX_DP[15]

QPI3_DRX_DP[16]

QPI3_DRX_DP[17]

QPI3_DRX_DP[18]

QPI3_DRX_DP[19]

QPI3_DRX_DP[2]

QPI3_DRX_DP[3]

AH45

AG44

AF45

N45

M45

E44

D44

P41

N41

N43

L44

L43

M41

N40

L40

M38

N38

P40

R39

T42

U43

U44

R43

U46

T45

P44

P46

R41

N42

M43

M44

L42

L41

M40

L39

L38

N37

P39

R38

R42

T43

SCID Diff.

O

I

O

I

O

I

W45

I

AA44

W43

I

AB43

AM43

AN46

AL45

AK43

AK45

AH44

AG43

AG45

AF43

AJ43

AD44

AC46

AC44

AB45

Y45

I

W46

I

W44

I

AA43

Y43

I

AC43

AL43

AM46

AL46

AK44

AJ45

I

Datasheet Volume 1 of 2

71

Pin Listing

Table 4-1.

Pin List, Sorted by Socket

Name (Sheet 15 of 39)

Table 4-1.

Pin List, Sorted by Socket

Name (Sheet 16 of 39)

Socket (EMTS)

Land #

Format

IO

Socket (EMTS)

Land #

Format

IO

QPI3_DRX_DP[4]

QPI3_DRX_DP[5]

QPI3_DRX_DP[6]

QPI3_DRX_DP[7]

QPI3_DRX_DP[8]

QPI3_DRX_DP[9]

QPI3_DTX_DN[0]

QPI3_DTX_DN[1]

QPI3_DTX_DN[10]

QPI3_DTX_DN[11]

QPI3_DTX_DN[12]

QPI3_DTX_DN[13]

QPI3_DTX_DN[14]

QPI3_DTX_DN[15]

QPI3_DTX_DN[16]

QPI3_DTX_DN[17]

QPI3_DTX_DN[18]

QPI3_DTX_DN[19]

QPI3_DTX_DN[2]

QPI3_DTX_DN[3]

QPI3_DTX_DN[4]

QPI3_DTX_DN[5]

QPI3_DTX_DN[6]

QPI3_DTX_DN[7]

QPI3_DTX_DN[8]

QPI3_DTX_DN[9]

QPI3_DTX_DP[0]

QPI3_DTX_DP[1]

QPI3_DTX_DP[10]

QPI3_DTX_DP[11]

QPI3_DTX_DP[12]

QPI3_DTX_DP[13]

QPI3_DTX_DP[14]

QPI3_DTX_DP[15]

QPI3_DTX_DP[16]

QPI3_DTX_DP[17]

QPI3_DTX_DP[18]

QPI3_DTX_DP[19]

QPI3_DTX_DP[2]

QPI3_DTX_DP[3]

QPI3_DTX_DP[4]

U45

R44

T46

R45

P45

N46

J40

SCID Diff.

I

QPI3_DTX_DP[5]

QPI3_DTX_DP[6]

QPI3_DTX_DP[7]

QPI3_DTX_DP[8]

QPI3_DTX_DP[9]

RESET_N

RSVD

J46

SCID Diff.

GTL

O

I

H45

G45

F46

O

I

O

I

O

I

E46

O

I

B4

I

O

AA10

AA2

AB3

AD37

AE38

AF10

AG10

AG37

AG5

AG6

AG7

AG9

AH10

AH3

AH38

AH4

AH5

AH7

AH8

AH9

AJ4

IO

H42

C45

B44

F42

B42

A41

D42

C39

F41

E39

E40

G43

J43

RSVD

F43

K46

J45

RSVD

G44

G46

E45

J41

RSVD

J42

RSVD

AJ46

AJ5

C44

B43

E42

C42

B41

D41

C40

F40

F39

D40

H43

J44

RSVD

AJ6

RSVD

AJ7

RSVD

AJ8

RSVD

AJ9

RSVD

AK37

AK6

AK8

AK9

AL38

AL6

RSVD

AL8

F44

RSVD

AM10

72

Datasheet Volume 1 of 2

Pin Listing

Table 4-1.

Pin List, Sorted by Socket

Name (Sheet 17 of 39)

Table 4-1.

Pin List, Sorted by Socket

Name (Sheet 18 of 39)

Socket (EMTS)

Land #

Format

IO

Socket (EMTS)

Land #

Format

GTL

IO

RSVD

AM6

AM7

AM8

AM9

AN37

AP38

AT2

IO

O

RUNBIST

SKTDIS_N

SKTID[0]

SKTID[1]

SKTID[2]

SKTOCC_N

SM_WP

BJ10

BG11

BK14

BJ14

BH14

BJ13

BK12

BJ12

BH12

BG10

BG9

I

GTL

I

CMOS

I

O

I

CMOS

AT37

AU2

AU38

AW37

AY38

B46

SMBCLK

SMBDAT

SPDCLK

CMOS

I/OD

CMOS

I/OD

CMOS

I/OD

SPDDAT

SYSCLK_DN

SYSCLK_DP

SYSCLK_LAI

SYSCLK_LAI_N

TCLK

CMOS

I/OD

T38

Differential

GTL

I

U38

I

BC35

BC38

BC9

BD12

BD13

BD38

BD9

BF12

BF3

AA39

AA38

K10

I

TDI

L9

GTL

I

TDO

L10

GTL-OD

O

I

TEST[0]

TEST[1]

TEST[2]

TEST[3]

Test-Hi

A1

A46

IO

I

BM46

BM1

IO

I

BG2

BG32

BG45

BH15

BH16

C46

D4

O

AP10

BG13

F5

GTL

O

THERMALERT_N

THERMTRIP_N

TMS

CMOS

GTL-OD

GTL

OD

O

I

O

M9

O

TRST_N

M10

GTL

I

O

VCACHE

BC15

BC17

BC18

BC20

BC21

BC23

BC24

BC26

BC27

BC29

BC30

BC32

BC33

BD15

Power

I

O

I

G6

O

I

H9

O

I

J9

O

I

M39

P37

O

I

O

I

P38

O

I

P9

O

I

R9

O

I

W38

W9

O

I

IO

I

Y10

I

Y9

I

Datasheet Volume 1 of 2

73

Pin Listing

Table 4-1.

Pin List, Sorted by Socket

Name (Sheet 19 of 39)

Table 4-1.

Pin List, Sorted by Socket

Name (Sheet 20 of 39)

Socket (EMTS)

Land #

Format

Power

IO

Socket (EMTS)

Land #

Format

Power

IO

VCACHE

BD17

BD18

BD20

BD21

BD23

BD24

BD26

BD27

BD29

BD30

BD32

BD33

BE15

BE17

BE18

BE20

BE21

BE23

BE24

BE26

BE27

BE29

BE30

BF15

BF17

BF18

BF20

BF27

BF29

BF30

BG15

BG17

BG18

BG20

BG27

BG29

BG30

BH17

BH18

BH20

BH27

I

VCACHE

VCACHESENSE

VCC33

BH29

BH30

BJ18

BJ20

BJ21

BJ23

BJ24

BJ26

BJ27

BJ29

BJ30

BK20

BK21

BK23

BK24

BK26

BK27

BK29

BK30

BL20

BL21

BL23

BL24

BL26

BL27

BL29

BL30

BM20

BM21

BM26

BM27

BM29

BM30

BK18

BE10

BE11

BE12

K38

I

IO

I

Power

VCC33

VCCCORE

K37

K35

K34

74

Datasheet Volume 1 of 2

Pin Listing

Table 4-1.

Pin List, Sorted by Socket

Name (Sheet 21 of 39)

Table 4-1.

Pin List, Sorted by Socket

Name (Sheet 22 of 39)

Socket (EMTS)

Land #

Format

Power

IO

Socket (EMTS)

Land #

Format

Power

IO

VCCCORE

K32

K31

K29

K28

K26

K25

K22

K21

K19

K18

K16

K15

K13

K12

J38

J37

J35

J34

J32

J31

J29

J28

J26

J25

J22

J21

J19

J18

J16

J15

J13

J12

J10

H38

H37

H35

H34

H32

H31

H29

H28

I

VCCCORE

H26

H25

H22

H21

H19

H18

H16

H15

H13

H12

H10

G38

G37

G35

G34

G32

G31

G29

G28

G19

G18

G16

G15

G13

G12

G10

G9

I

Power

F38

F37

F35

F34

F32

F31

F29

F28

F19

F18

F16

F15

F13

F12

Datasheet Volume 1 of 2

75

Pin Listing

Table 4-1.

Pin List, Sorted by Socket

Name (Sheet 23 of 39)

Table 4-1.

Pin List, Sorted by Socket

Name (Sheet 24 of 39)

Socket (EMTS)

Land #

Format

Power

IO

Socket (EMTS)

Land #

Format

Power

IO

VCCCORE

F10

F9

I

VCCCORE

C34

C32

C31

C29

C28

C26

C25

C22

C21

C19

C18

C16

C15

C13

C12

C10

C9

I

Power

E38

E37

E35

E34

E32

E31

E29

E28

E19

E18

E16

E15

E13

E12

E10

E9

B38

B37

B35

B34

B32

B31

B29

B28

B26

B25

B22

B21

B19

B18

B16

B15

B13

B12

B10

B9

D38

D37

D35

D34

D32

D31

D29

D28

D26

D25

D22

D21

D19

D18

D16

D15

D13

D12

D10

D9

A38

A37

A35

A34

C38

C37

C35

76

Datasheet Volume 1 of 2

Pin Listing

Table 4-1.

Pin List, Sorted by Socket

Name (Sheet 25 of 39)

Table 4-1.

Pin List, Sorted by Socket

Name (Sheet 26 of 39)

Socket (EMTS)

Land #

Format

Power

IO

Socket (EMTS)

Land #

Format

POWER

IO

VCCCORE

VCORESENSE

VID[0]

A32

A31

A29

A28

A26

A21

A19

A18

A16

A15

A13

A12

A10

A9

I

VIOC

VIOF

AR42

AT42

AV36

AV42

AW42

BA36

BA42

BB37

BB42

BD42

BE42

BF41

BG36

BG37

BG38

BG39

BG41

BH34

BH35

BH41

BK34

BL34

M36

I

Power

CMOS

POWER

I

POWER

I

F7

IO

O

I

E7

VID[1]

E6

VID[2]

D7

VID[3]

D6

VID[4]

C7

VID[5]

C6

VID[6]

B7

VID[7]

A6

VIO_VID[1]

VIO_VID[2]

VIO_VID[3]

VIO_VID[4]

VIOC

BH38

BK38

BM38

BM39

AA42

AC36

AC42

AD42

AF36

AF42

AG42

AJ36

AJ42

AK42

AM36

AM42

AN42

AR36

P36

U36

V42

V43

V44

VIOC

I

V45

VIOC

I

Y36

VIOC

I

Y42

VIOC

I

AB9

VIOC

I

AC10

AC11

AE9

VIOC

I

VIOC

I

VIOC

I

AF11

AJ10

AJ11

AL10

AM11

AN10

VIOC

I

VIOC

I

VIOC

I

VIOC

I

VIOC

I

Datasheet Volume 1 of 2

77

Pin Listing

Table 4-1.

Pin List, Sorted by Socket

Name (Sheet 27 of 39)

Table 4-1.

Pin List, Sorted by Socket

Name (Sheet 28 of 39)

Socket (EMTS)

Land #

Format

POWER

IO

Socket (EMTS)

Land #

Format

POWER

IO

VIOF

VIOPWRGOOD

VREG

AN8

AP9

AR10

AR11

AT9

AU9

AV10

AV11

BA1

BA10

BA11

BA2

BA3

BA7

BA8

BB10

BB11

BB2

BB4

BB5

BB6

BB8

P10

P11

R10

R11

T1

I

VREG

VSS

AK1

AK2

AK3

AK4

AL1

AL2

AL3

AL4

AL5

A11

A14

A17

A2

I

POWER

CMOS

POWER

GND

A20

A27

A3

GND

A30

A33

A36

A39

A4

GND

A40

A42

A43

A44

A45

A7

GND

T2

A8

GND

T4

AA11

AA3

AA36

AA41

AA46

AA5

AA9

AB10

AB11

AB36

AB38

AB42

AB44

GND

T6

GND

T7

GND

T8

GND

U1

GND

U10

U11

U5

GND

U8

GND

U9

GND

Y11

H41

AJ2

GND

POWER

GND

78

Datasheet Volume 1 of 2

Pin Listing

Table 4-1.

Pin List, Sorted by Socket

Name (Sheet 29 of 39)

Table 4-1.

Pin List, Sorted by Socket

Name (Sheet 30 of 39)

Socket (EMTS)

Land #

Format

GND

IO

Socket (EMTS)

Land #

Format

GND

IO

VSS

AB7

I

VSS

AK46

AK5

I

AC1

GND

AC39

AC4

AK7

AL11

AL36

AL37

AL42

AL44

AL7

AC9

AD10

AD11

AD36

AD41

AD45

AD5

AL9

AM2

AM3

AM39

AM5

AN11

AN3

AD7

AE10

AE11

AE3

AE36

AE37

AE42

AE7

AN36

AN41

AN45

AN7

AF39

AF44

AF9

AN9

AP1

AG11

AG36

AG4

AP11

AP36

AP37

AP4

AG41

AG8

AP42

AP44

AP5

AH11

AH2

AH36

AH37

AH42

AH6

AR39

AR5

AR7

AR9

AJ1

AT1

AJ3

AT10

AT11

AT3

AJ39

AJ44

AK10

AK11

AK36

AK41

AT36

AT41

AT45

AU1

Datasheet Volume 1 of 2

79

Pin Listing

Table 4-1.

Pin List, Sorted by Socket

Name (Sheet 31 of 39)

Table 4-1.

Pin List, Sorted by Socket

Name (Sheet 32 of 39)

Socket (EMTS)

Land #

Format

GND

IO

Socket (EMTS)

Land #

Format

GND

IO

VSS

AU10

AU11

AU36

AU37

AU42

AU44

AU6

I

VSS

B45

I

GND

B6

GND

B8

BA39

BA4

BA9

BB3

AU8

BB36

BB41

BB45

BB7

AV39

AV5

AV9

AW10

AW11

AW3

AW36

AW41

AW45

AW7

AY1

BB9

BC11

BC12

BC13

BC14

BC16

BC19

BC22

BC25

BC28

BC31

BC34

BC37

BC42

BC5

AY10

AY11

AY36

AY37

AY42

AY44

AY6

B1

BD11

BD14

BD16

BD19

BD22

BD25

BD28

BD3

B11

B14

B17

B2

B20

B23

B24

B27

BD31

BD39

BD44

BD7

B3

B30

B33

B36

BE1

B39

BE13

BE14

B40

80

Datasheet Volume 1 of 2

Pin Listing

Table 4-1.

Pin List, Sorted by Socket

Name (Sheet 33 of 39)

Table 4-1.

Pin List, Sorted by Socket

Name (Sheet 34 of 39)

Socket (EMTS)

Land #

Format

GND

IO

Socket (EMTS)

Land #

Format

GND

IO

VSS

BE16

BE19

BE22

BE25

BE28

BE31

BE36

BE41

BE46

BE9

I

VSS

BJ19

BJ22

BJ25

BJ28

BJ3

I

GND

BJ31

BJ32

BJ34

BJ38

BJ42

BJ44

BJ46

BJ5

BF11

BF13

BF16

BF19

BF28

BF31

BF34

BF38

BF42

BF5

BJ7

BK1

BK15

BK19

BK22

BK25

BK28

BK31

BK40

BK46

BK7

BF7

BG12

BG14

BG16

BG19

BG28

BG3

BL1

BL13

BL19

BL2

BG31

BG40

BG44

BG7

BL22

BL25

BL28

BL3

BH13

BH19

BH28

BH31

BH36

BH46

BH9

BL31

BL33

BL36

BL38

BL4

BL44

BL45

BL46

BL9

BJ1

BJ11

BJ17

Datasheet Volume 1 of 2

81

Pin Listing

Table 4-1.

Pin List, Sorted by Socket

Name (Sheet 35 of 39)

Table 4-1.

Pin List, Sorted by Socket

Name (Sheet 36 of 39)

Socket (EMTS)

Land #

Format

GND

IO

Socket (EMTS)

Land #

Format

GND

IO

VSS

BM11

BM16

BM19

BM2

BM28

BM3

BM31

BM34

BM4

BM40

BM42

BM43

BM44

BM45

BM7

C1

I

VSS

D36

D39

D45

D46

D8

I

GND

E11

E14

E17

E20

E27

E30

E33

E36

E41

E43

E5

C11

C14

C17

C2

E8

F11

F14

F17

F20

F27

F3

C20

C23

C24

C27

C30

C33

C36

C41

C43

C5

F30

F33

F36

F45

F8

G1

G11

G14

G17

G20

G27

G30

G33

G36

G39

G40

G42

G5

C8

D1

D11

D14

D17

D20

D23

D24

D27

D30

D33

82

Datasheet Volume 1 of 2

Pin Listing

Table 4-1.

Pin List, Sorted by Socket

Name (Sheet 37 of 39)

Table 4-1.

Pin List, Sorted by Socket

Name (Sheet 38 of 39)

Socket (EMTS)

Land #

Format

GND

IO

Socket (EMTS)

Land #

Format

GND

IO

VSS

G8

I

VSS

K40

K41

K42

K43

K44

K45

K5

I

H11

H14

H17

H20

H23

H24

H27

H30

H33

H36

H39

H4

GND

K7

K9

L11

L3

L36

L37

L4

H40

H44

H46

H8

L45

L46

L6

J11

J14

J17

J2

M1

M11

M2

M37

M42

M46

M8

J20

J23

J24

J27

J30

J33

J36

J39

J7

N10

N11

N36

N39

N44

N5

K11

K14

K17

K20

K23

K24

K27

K30

K33

K36

K39

N9

P3

P42

P43

P7

R1

R36

R37

R40

R46

T10

Datasheet Volume 1 of 2

83

Pin Listing

Table 4-1.

Pin List, Sorted by Socket

Name (Sheet 39 of 39)

Socket (EMTS)

Land #

Format

GND

IO

VSS

T11

T3

I

VSS

GND

Power

I

VSS

T36

T37

T44

T5

I

VSS

I

VSS

I

VSS

I

VSS

T9

I

VSS

U2

I

VSS

U39

U42

U7

I

VSS

I

VSS

I

VSS

V10

V11

V36

V41

V46

V5

I

VSS

I

VSS

I

VSS

I

VSS

I

VSS

I

VSS

V9

I

VSS

W10

W11

W3

I

VSS

I

VSS

I

VSS

W36

W37

W42

W6

I

VSS

I

VSS

I

VSS

I

VSS

W7

I

VSS

Y1

I

VSS

Y39

Y44

BK17

F6

I

VSS

I

VSSCACHESENSE

VSSCORESENSE

IO

84

Datasheet Volume 1 of 2

Pin Listing

4.1.2

Processor Pin List, Sorted by Land Number

Table 4-2.

Pin List, Sorted by land

Number (Sheet 2 of 39)

Table 4-2.

Pin List, Sorted by land

Number (Sheet 1 of 39)

Land #

Socket (EMTS)

Format

GND

IO

Land #

Socket (EMTS)

Format

IO

A7

VSS

I

A1

TEST[0]

VCCCORE

I

A8

GND

I

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A2

POWER

I

A9

VCCCORE

POWERf

Differential

I

VSS

GND

I

AA1

FBD1NBIDN[12]

RSVD

I

VCCCORE

VSS

POWER

GND

I

AA10

AA11

AA2

IO

I

VSS

GND

I

RSVD

IO

I

VCCCORE

VSS

POWER

GND

I

AA3

VSS

GND

I

AA36

AA37

AA38

AA39

AA4

VSS

GND

I

QPI2_DRX_DN[19]

SYSCLK_LAI_N

SYSCLK_LAI

FBD1NBIDP[0]

QPI2_DRX_DN[10]

VSS

SCID Diff.

Differential

SCID Diff.

GND

I

VCCCORE

VSS

POWER

GND

I

A20

A21

A26

A27

A28

A29

A3

VSS

GND

I

AA40

AA41

AA42

AA43

AA44

AA45

AA46

AA5

I

VCCCORE

VSS

POWER

GND

I

VIOC

POWER

I

QPI2_DTX_DP[17]

QPI2_DTX_DN[17]

QPI2_DTX_DN[14]

VSS

SCID Diff.

GND

O

I

VCCCORE

VSS

POWER

GND

I

A30

A31

A32

A33

A34

A35

A36

A37

A38

A39

A4

VSS

GND

I

VSS

GND

I

VCCCORE

VSS

POWER

GND

I

AA6

FBD1NBICN[12]

FBD1NBICP[6]

FBD1NBICN[6]

VSS

Differential

GND

I

AA7

I

AA8

I

VCCCORE

VSS

POWER

GND

I

AA9

I

AB1

FBD1NBIDP[12]

VSS

Differential

GND

I

AB10

AB11

AB2

I

VCCCORE

VSS

POWER

GND

I

VSS

GND

I

FBD1NBICLKDN0

RSVD

Differential

I

AB3

IO

I

VSS

GND

I

AB36

AB37

AB38

AB39

AB4

VSS

GND

A40

A41

A42

A43

A44

A45

A46

A5

VSS

GND

I

QPI2_DRX_DP[19]

VSS

SCID Diff.

GND

I

QPI3_DTX_DN[14]

VSS

SCID Diff.

GND

O

I

QPI2_CLKRX_DP

FBD1NBIDN[0]

QPI2_CLKRX_DN

QPI2_DRX_DP[9]

VSS

SCID Diff.

Differential

SCID Diff.

GND

I

VSS

GND

I

VSS

GND

I

AB40

AB41

AB42

AB43

I

VSS

GND

I

TEST[1]

ISENSE_DP

VID[7]

IO

I

GTL

QPI2_DTX_DN[19]

SCID Diff.

O

A6

CMOS

IO

Datasheet Volume 1 of 2

85

Pin Listing

Table 4-2.

Pin List, Sorted by land

Number (Sheet 3 of 39)

Table 4-2.

Pin List, Sorted by land

Number (Sheet 4 of 39)

Land #

Socket (EMTS)

Format

GND

IO

Land #

Socket (EMTS)

Format

GND

IO

AB44

AB45

AB46

AB5

VSS

I

AD41

AD42

AD43

AD44

AD45

AD46

AD5

VSS

VIOC

I

QPI2_DTX_DP[13]

QPI2_DTX_DN[13]

FBD1NBICLKCN0

FBD1NBICP[12]

VSS

SCID Diff.

Differential

GND

O

I

POWER

SCID Diff.

GND

I

QPI2_DTX_DN[10]

QPI2_DTX_DP[10]

VSS

O

I

AB6

I

AB7

I

QPI2_DTX_DN[11]

VSS

SCID Diff.

GND

O

I

AB8

FBD1NBICP[0]

VIOF

Differential

POWER

I

AB9

I

AD6

FBD1NBICN[5]

VSS

Differential

GND

I

AC1

VSS

GND

I

AD7

I

AC10

AC11

AC2

VIOF

POWER

I

AD8

FBD1NBICN[1]

FBD1NBICP[1]

VSS

Differential

GND

I

VIOF

POWER

I

AD9

I

FBD1NBICLKDP0

FBD1NBIDN[13]

VIOC

Differential

POWER

I

AE10

AE11

AE2

I

AC3

I

VSS

GND

I

AC36

AC37

AC38

AC39

AC4

I

FBD1NBIDN[4]

VSS

Differential

GND

I

QPI2_DRX_DN[0]

QPI2_DRX_DP[0]

VSS

SCID Diff.

GND

I

AE3

I

AE36

AE37

AE38

AE39

AE4

VSS

GND

I

VSS

GND

I

VSS

GND

I

RSVD

IO

I

AC40

AC41

AC42

AC43

AC44

AC45

AC46

AC5

QPI2_DRX_DP[8]

QPI2_DRX_DN[9]

VIOC

SCID Diff.

POWER

I

QPI2_DRX_DP[7]

FBD1NBIDN[1]

QPI2_DRX_DN[7]

QPI2_DRX_DP[6]

VSS

SCID Diff.

Differential

SCID Diff.

GND

I

AE40

AE41

AE42

AE43

AE44

AE45

AE5

I

QPI2_DTX_DP[19]

QPI2_DTX_DP[12]

QPI2_DTX_DN[12]

QPI2_DTX_DP[11]

FBD1NBICLKCP0

FBD1NBICN[13]

FBD1NBICP[13]

FBD1NBICN[0]

VSS

SCID Diff.

Differential

GND

O

I

QPI2_DTX_DN[0]

QPI2_CLKTX_DN

QPI2_CLKTX_DP

FBD1NBICN[4]

FBD1NBICP[5]

VSS

SCID Diff.

Differential

GND

O

I

AC6

I

AC7

I

AE6

I

AC8

I

AE7

I

AC9

I

AE8

FBD1NBICN[2]

VIOF

Differential

POWER

I

AD1

FBD1NBIDN[5]

VSS

Differential

GND

I

AE9

I

AD10

AD11

AD2

I

AF10

AF11

AF2

RSVD

IO

I

VSS

GND

I

VIOF

POWER

FBD1NBIDP[5]

FBD1NBIDP[13]

VSS

Differential

GND

I

FBD1NBIDP[4]

FBD1NBIDN[3]

VIOC

Differential

POWER

I

AD3

I

AF3

I

AD36

AD37

AD38

AD39

AD4

I

AF36

AF37

AF38

AF39

AF4

I

RSVD

IO

I

QPI2_DRX_DN[2]

QPI2_DRX_DP[2]

VSS

SCID Diff.

GND

I

QPI2_DRX_DN[1]

QPI2_DRX_DP[1]

FBD1NBIDP[1]

QPI2_DRX_DN[8]

SCID Diff.

Differential

SCID Diff.

I

FBD1NBIDP[3]

QPI2_DRX_DP[5]

Differential

SCID Diff.

I

AD40

I

AF40

I

86

Datasheet Volume 1 of 2

Pin Listing

Table 4-2.

Pin List, Sorted by land

Number (Sheet 5 of 39)

Table 4-2.

Pin List, Sorted by land

Number (Sheet 6 of 39)

Land #

Socket (EMTS)

Format

IO

Land #

Socket (EMTS)

Format

GND

IO

AF41

AF42

AF43

AF44

AF45

AF5

QPI2_DRX_DN[6]

VIOC

SCID Diff.

POWER

I

AH42

AH43

AH44

AH45

AH5

AH6

AH7

AH8

AH9

AJ1

VSS

I

QPI2_DTX_DN[1]

SCID Diff.

O

IO

I

QPI2_DTX_DP[0]

VSS

SCID Diff.

GND

O

I

QPI2_DTX_DN[7]

QPI2_DTX_DP[7]

QPI2_DTX_DP[9]

FBD1NBICP[4]

FBD1NBICN[3]

FBD1NBICP[3]

FBD1NBICP[2]

VSS

SCID Diff.

Differential

GND

O

I

RSVD

VSS

GND

AF6

I

RSVD

IO

I

AF7

I

RSVD

AF8

I

RSVD

AF9

I

VSS

GND

AG10

AG11

AG2

RSVD

IO

I

AJ10

AJ11

AJ2

VIOF

POWER

GND

I

VSS

GND

VIOF

I

FBD1NBIDN[2]

FBD1NBIDP[2]

VSS

Differential

GND

I

VREG

I

AG3

I

AJ3

VSS

I

AG36

AG37

AG38

AG39

AG4

I

AJ36

AJ37

AJ38

AJ39

AJ4

VIOC

POWER

SCID Diff.

GND

I

RSVD

IO

I

QPI1_DRX_DN[2]

QPI1_DRX_DP[2]

VSS

I

QPI2_DRX_DN[3]

QPI2_DRX_DP[3]

VSS

SCID Diff.

GND

I

RSVD

IO

I

AG40

AG41

AG42

AG43

AG44

AG45

AG5

QPI2_DRX_DN[5]

VSS

SCID Diff.

GND

I

AJ40

AJ41

AJ42

AJ43

AJ44

AJ45

AJ46

AJ5

QPI1_DRX_DN[5]

QPI1_DRX_DP[4]

VIOC

SCID Diff.

POWER

I

VIOC

POWER

I

QPI2_DTX_DN[8]

QPI2_DTX_DP[8]

QPI2_DTX_DN[9]

RSVD

SCID Diff.

O

IO

I

QPI2_DTX_DP[1]

VSS

SCID Diff.

GND

O

I

QPI2_DTX_DP[6]

RSVD

SCID Diff.

O

IO

I

AG6

RSVD

AG7

RSVD

AJ6

RSVD

AG8

VSS

GND

AJ7

RSVD

AG9

RSVD

IO

I

AJ8

RSVD

AH10

AH11

AH2

RSVD

AJ9

RSVD

VSS

GND

AK1

VREG

POWER

GND

VSS

I

AK10

AK11

AK2

VSS

I

AH3

RSVD

IO

I

VSS

GND

I

AH36

AH37

AH38

AH39

AH4

VSS

GND

VREG

POWER

GND

I

VSS

I

AK3

VREG

I

RSVD

IO

I

AK36

AK37

AK38

AK39

AK4

VSS

I

QPI2_DRX_DP[4]

RSVD

SCID Diff.

RSVD

IO

I

IO

I

QPI1_DRX_DN[3]

QPI1_DRX_DP[3]

VREG

SCID Diff.

POWER

AH40

AH41

QPI2_DRX_DN[4]

QPI1_DRX_DN[4]

SCID Diff.

I

Datasheet Volume 1 of 2

87

Pin Listing

Table 4-2.

Pin List, Sorted by land

Number (Sheet 7 of 39)

Table 4-2.

Pin List, Sorted by land

Number (Sheet 8 of 39)

Land #

Socket (EMTS)

Format

IO

Land #

Socket (EMTS)

Format

IO

AK40

AK41

AK42

AK43

AK44

AK45

AK46

AK5

QPI1_DRX_DP[5]

SCID Diff.

GND

I

AM38

AM39

AM4

QPI1_DRX_DP[1]

VSS

SCID Diff.

GND

I

VSS

I

VIOC

POWER

SCID Diff.

GND

I

FBD0SBOBN[10]

QPI1_DRX_DN[8]

QPI1_DRX_DP[7]

VIOC

Differential

SCID Diff.

POWER

O

I

QPI2_DTX_DN[5]

O

I

AM40

AM41

AM42

AM43

AM44

AM45

AM46

AM5

QPI2_DTX_DP[5]

I

QPI2_DTX_DN[6]

I

VSS

QPI2_DTX_DN[2]

QPI1_DTX_DP[3]

QPI1_DTX_DN[3]

QPI2_DTX_DP[3]

VSS

SCID Diff.

GND

O

I

VSS

GND

I

AK6

RSVD

IO

I

AK7

VSS

GND

AK8

RSVD

IO

I

AK9

RSVD

AM6

RSVD

IO

O

I

AL1

VREG

POWER

GND

AM7

RSVD

AL10

AL11

AL2

VIOF

I

AM8

RSVD

VSS

I

AM9

RSVD

VREG

POWER

GND

I

AN1

FBD0SBOBP[7]

VIOF

Differential

POWER

GND

AL3

VREG

I

AN10

AN11

AN2

AL36

AL37

AL38

AL39

AL4

VSS

I

VSS

I

VSS

GND

I

FBD0SBOBN[6]

VSS

Differential

GND

O

I

RSVD

IO

I

AN3

QPI1_DRX_DN[6]

VREG

SCID Diff.

POWER

AN36

AN37

AN38

AN39

AN4

VSS

GND

I

RSVD

IO

I

AL40

AL41

AL42

AL43

AL44

AL45

AL46

AL5

QPI1_DRX_DP[6]

QPI1_DRX_DN[7]

VSS

SCID Diff.

GND

I

QPI1_DRX_DN[0]

QPI1_DRX_DP[0]

FBD0SBOBP[10]

QPI1_DRX_DP[8]

VSS

SCID Diff.

Differential

SCID Diff.

GND

I

O

I

QPI2_DTX_DP[2]

VSS

SCID Diff.

GND

O

I

AN40

AN41

AN42

AN43

AN44

AN45

AN46

AN5

I

QPI2_DTX_DN[4]

QPI2_DTX_DP[4]

VREG

SCID Diff.

Power

O

I

VIOC

POWER

SCID Diff.

GND

I

QPI1_DTX_DN[2]

QPI1_DTX_DP[2]

VSS

O

I

AL6

RSVD

IO

I

AL7

VSS

GND

QPI2_DTX_DN[3]

FBD0SBOAP[7]

FBD0SBOAN[7]

VSS

SCID Diff.

Differential

GND

O

I

AL8

RSVD

IO

I

AL9

VSS

GND

AN6

AM1

AM10

AM11

AM2

AM3

AM36

AM37

FBD0SBOBN[7]

RSVD

Differential

O

IO

I

AN7

AN8

VIOF

POWER

GND

I

VIOF

POWER

GND

AN9

VSS

I

VSS

I

AP1

VSS

GND

I

VSS

GND

I

AP10

AP11

AP2

Test-Hi

GTL

IO

I

VIOC

POWER

SCID Diff.

I

VSS

GND

QPI1_DRX_DN[1]

I

FBD0SBOBP[6]

Differential

O

88

Datasheet Volume 1 of 2

Pin Listing

Table 4-2.

Pin List, Sorted by land

Number (Sheet 9 of 39)

Table 4-2.

Pin List, Sorted by land

Number (Sheet 10 of 39)

Land #

Socket (EMTS)

Format

IO

Land #

Socket (EMTS)

Format

GND

IO

AP3

FBD0SBOBN[8]

VSS

Differential

GND

O

I

AT10

AT11

AT2

VSS

I

AP36

AP37

AP38

AP39

AP4

GND

I

VSS

GND

I

RSVD

IO

I

RSVD

IO

I

AT3

VSS

GND

QPI1_DRX_DN[9]

VSS

SCID Diff.

GND

AT36

AT37

AT38

AT39

AT4

VSS

I

RSVD

IO

I

AP40

AP41

AP42

AP43

AP44

AP45

AP46

AP5

QPI1_DRX_DP[9]

QPI1_CLKRX_DN

VSS

SCID Diff.

GND

I

QPI1_DRX_DP[18]

QPI1_DRX_DN[18]

FBD0SBOBP[9]

QPI1_DRX_DP[10]

VSS

SCID Diff.

Differential

SCID Diff.

GND

I

O

I

QPI1_DTX_DP[1]

VSS

SCID Diff.

GND

O

I

AT40

AT41

AT42

AT43

AT44

AT45

AT46

AT5

I

QPI1_DTX_DN[4]

QPI1_DTX_DP[4]

VSS

SCID Diff.

GND

O

I

VIOC

POWER

I

QPI1_DTX_DN[0]

QPI1_DTX_DP[0]

VSS

SCID Diff.

GND

O

I

AP6

FBD0SBOAP[6]

FBD0SBOAN[6]

FBD0SBOAN[8]

VIOF

Differential

POWER

O

I

AP7

QPI1_DTX_DP[6]

FBD0SBOCLKAP0

FBD0SBOAP[9]

FBD0SBOAP[5]

FBD0SBOAN[5]

VIOF

SCID Diff.

Differential

POWER

O

I

AP8

AP9

AT6

AR1

FBD0SBOBP[5]

VIOF

Differential

POWER

O

I

AT7

AR10

AR11

AR2

AT8

VIOF

POWER

I

AT9

FBD0SBOBN[5]

FBD0SBOBP[8]

VIOC

Differential

POWER

O

I

AU1

VSS

GND

I

AR3

AU10

AU11

AU2

VSS

GND

I

AR36

AR37

AR38

AR39

AR4

VSS

GND

I

QPI1_DRX_DP[19]

QPI1_DRX_DN[19]

VSS

SCID Diff.

GND

I

RSVD

IO

O

I

AU3

FBD0SBOCLKBN0

VSS

Differential

GND

I

AU36

AU37

AU38

AU39

AU4

FBD0SBOBN[9]

QPI1_DRX_DN[10]

QPI1_CLKRX_DP

VIOC

Differential

SCID Diff.

POWER

O

I

VSS

GND

I

AR40

AR41

AR42

AR43

AR44

AR45

AR46

AR5

RSVD

IO

I

QPI1_DRX_DN[11]

FBD0SBOCLKBP0

QPI1_DRX_DP[11]

QPI1_DRX_DN[12]

VSS

SCID Diff.

Differential

SCID Diff.

GND

I

O

I

QPI1_DTX_DN[1]

QPI1_DTX_DN[5]

QPI1_DTX_DP[5]

QPI1_DTX_DN[6]

VSS

SCID Diff.

GND

O

I

AU40

AU41

AU42

AU43

AU44

AU45

AU46

AU5

I

QPI1_DTX_DP[19]

VSS

SCID Diff.

GND

O

I

AR6

FBD0SBOAN[9]

VSS

Differential

GND

O

I

QPI1_DTX_DN[7]

QPI1_DTX_DP[7]

FBD0SBOCLKAN0

VSS

SCID Diff.

Differential

GND

O

I

AR7

AR8

FBD0SBOAP[8]

VSS

Differential

GND

O

I

AR9

AU6

AT1

VSS

GND

I

AU7

FBD0SBOAN[4]

Differential

O

Datasheet Volume 1 of 2

89

Pin Listing

Table 4-2.

Pin List, Sorted by land

Number (Sheet 11 of 39)

Table 4-2.

Pin List, Sorted by land

Number (Sheet 12 of 39)

Land #

Socket (EMTS)

Format

GND

IO

Land #

Socket (EMTS)

Format

IO

AU8

VSS

VIOF

I

AW5

AW6

AW7

AW8

AW9

AY1

FBD0SBOAN[2]

FBD0SBOAP[3]

VSS

Differential

GND

O

I

AU9

POWER

I

AV1

FBD0SBOBN[3]

VIOF

Differential

POWER

O

I

AV10

AV11

AV2

FBD0SBOAN[10]

Proc_ID[0]

VSS

Differential

CMOS

O

I

VIOF

POWER

I

FBD0SBOBP[4]

FBD0SBOBN[4]

VIOC

Differential

POWER

O

I

GND

AV3

AY10

AY11

AY2

VSS

GND

I

AV36

AV37

AV38

AV39

AV4

VSS

GND

I

QPI1_DRX_DP[16]

QPI1_DRX_DN[16]

VSS

SCID Diff.

GND

I

FBD0SBOBP[2]

FBD0SBOBN[1]

VSS

Differential

GND

O

I

AY3

I

AY36

AY37

AY38

AY39

AY4

FBD0SBOBP[0]

QPI1_DRX_DN[13]

QPI1_DRX_DP[12]

VIOC

Differential

SCID Diff.

POWER

O

I

VSS

GND

I

AV40

AV41

AV42

AV43

AV44

AV45

AV46

AV5

RSVD

IO

I

QPI1_DRX_DP[15]

FBD0SBOBP[1]

QPI1_DRX_DN[15]

QPI0_DRX_DN[1]

VSS

SCID Diff.

Differential

SCID Diff.

GND

I

O

I

QPI1_DTX_DN[19]

QPI1_DTX_DN[8]

QPI1_DTX_DP[8]

QPI1_DTX_DN[9]

VSS

SCID Diff.

GND

O

I

AY40

AY41

AY42

AY43

AY44

AY45

AY46

AY5

I

QPI1_DTX_DP[17]

VSS

SCID Diff.

GND

O

I

AV6

FBD0SBOAN[3]

FBD0SBOAP[4]

FBD0SBOAP[10]

VSS

Differential

GND

O

I

QPI1_CLKTX_DN

QPI1_CLKTX_DP

FBD0SBOAP[2]

VSS

SCID Diff.

Differential

GND

O

I

AV7

AV8

AV9

AY6

AW1

AW10

AW11

AW2

AW3

AW36

AW37

AW38

AW39

AW4

AW40

AW41

AW42

AW43

AW44

AW45

AW46

FBD0SBOBP[3]

VSS

Differential

GND

O

I

AY7

FBD0SBOAN[1]

FBD0SBOAP[1]

Proc_ID[1]

VSS

Differential

CMOS

O

I

AY8

VSS

GND

I

AY9

FBD0SBOBN[2]

VSS

Differential

GND

O

I

B1

GND

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B2

VCCCORE

VSS

POWER

GND

I

VSS

GND

I

RSVD

IO

I

VCCCORE

VSS

POWER

GND

I

QPI1_DRX_DP[14]

QPI1_DRX_DN[14]

FBD0SBOBN[0]

QPI1_DRX_DP[13]

VSS

SCID Diff.

Differential

SCID Diff.

GND

I

O

I

VCCCORE

VSS

POWER

GND

I

VIOC

POWER

I

VCCCORE

VSS

POWER

GND

I

QPI1_DTX_DP[18]

QPI1_DTX_DN[18]

VSS

SCID Diff.

GND

O

I

B20

B21

VSS

GND

I

QPI1_DTX_DP[9]

SCID Diff.

O

VCCCORE

POWER

I

90

Datasheet Volume 1 of 2

Pin Listing

Table 4-2.

Pin List, Sorted by land

Number (Sheet 13 of 39)

Table 4-2.

Pin List, Sorted by land

Number (Sheet 14 of 39)

Land #

Socket (EMTS)

Format

POWER

IO

Land #

Socket (EMTS)

Format

GND

IO

B22

B23

B24

B25

B26

B27

B28

B29

B3

VCCCORE

VSS

I

BA4

VSS

I

GND

I

BA40

BA41

BA42

BA43

BA44

BA45

BA46

BA5

QPI0_DRX_DN[2]

SCID Diff.

POWER

SCID Diff.

Differential

POWER

GND

I

VSS

GND

I

QPI0_DRX_DP[1]

I

VCCCORE

VSS

POWER

GND

I

VIOC

I

QPI1_DTX_DN[17]

O

I

QPI1_DTX_DN[10]

VCCCORE

VSS

POWER

GND

I

QPI1_DTX_DP[10]

I

QPI1_DTX_DN[11]

I

FBD0SBOAN[0]

B30

B31

B32

B33

B34

B35

B36

B37

B38

B39

B4

VSS

GND

I

BA6

FBD0SBOAP[0]

VCCCORE

VSS

POWER

GND

I

BA7

VIOF

I

BA8

VIOF

I

BA9

VSS

I

VCCCORE

VSS

POWER

GND

I

BB10

BB11

BB2

VIOF

POWER

GND

I

VIOF

I

VIOF

I

VCCCORE

VSS

POWER

GND

I

BB3

VSS

I

BB36

BB37

BB38

BB39

BB4

VSS

GND

I

VIOC

POWER

SCID Diff.

POWER

SCID Diff.

GND

I

RESET_N

VSS

GTL

I

QPI0_DRX_DN[0]

I

B40

B41

B42

B43

B44

B45

B46

B5

GND

I

QPI0_DRX_DP[0]

I

QPI3_DTX_DP[14]

QPI3_DTX_DN[13]

QPI3_DTX_DP[11]

QPI3_DTX_DN[11]

VSS

SCID Diff.

GND

O

I

VIOF

I

BB40

BB41

BB42

BB43

BB44

BB45

BB46

BB5

QPI0_DRX_DP[2]

I

VSS

I

VIOC

POWER

SCID Diff.

GND

I

QPI1_DTX_DP[12]

O

I

RSVD

IO

I

QPI1_DTX_DN[12]

ISENSE_DN

VSS

GTL

VSS

B6

GND

I

QPI1_DTX_DP[11]

SCID Diff.

POWER

GND

O

I

B7

VID[6]

CMOS

IO

I

VIOF

B8

VSS

GND

BB6

VIOF

I

B9

VCCCORE

VIOF

POWER

SCID Diff.

GND

I

BB7

VSS

I

BA1

BA10

BA11

BA2

BA3

BA36

BA37

BA38

BA39

I

BB8

VIOF

POWER

GND

I

VIOF

I

BB9

VSS

I

VIOF

I

BC10

BC11

BC12

BC13

BC14

BC15

BC16

MEM_THROTTLE0_N

GTL

I

VIOF

I

VSS

GND

I

VIOF

I

VSS

GND

I

VIOC

I

VSS

GND

I

QPI1_DRX_DP[17]

QPI1_DRX_DN[17]

VSS

I

VSS

GND

I

VCACHE

VSS

Power

I

GND

I

Datasheet Volume 1 of 2

91

Pin Listing

Table 4-2.

Pin List, Sorted by land

Number (Sheet 15 of 39)

Table 4-2.

Pin List, Sorted by land

Number (Sheet 16 of 39)

Land #

Socket (EMTS)

Format

Power

IO

Land #

Socket (EMTS)

Format

GND

IO

BC17

BC18

BC19

BC2

VCACHE

I

BD14

BD15

BD16

BD17

BD18

BD19

BD2

VSS

VCACHE

I

Power

I

POWER

GND

I

VSS

GND

I

VSS

I

FBD0NBIBP[11]

VCACHE

Differential

POWER

GND

I

VCACHE

POWER

GND

I

BC20

BC21

BC22

BC23

BC24

BC25

BC26

BC27

BC28

BC29

BC3

I

VCACHE

I

VCACHE

I

VSS

I

VSS

I

FBD0NBIBN[9]

VCACHE

Differential

POWER

GND

I

VCACHE

POWER

GND

I

BD20

BD21

BD22

BD23

BD24

BD25

BD26

BD27

BD28

BD29

BD3

I

VCACHE

I

VCACHE

I

VSS

I

VSS

I

VCACHE

POWER

GND

I

VCACHE

POWER

GND

I

VCACHE

I

VCACHE

I

VSS

I

VSS

I

VCACHE

POWER

Differential

POWER

GND

I

VCACHE

POWER

GND

I

FBD0NBIBN[11]

VCACHE

I

VCACHE

I

BC30

BC31

BC32

BC33

BC34

BC35

BC36

BC37

BC38

BC39

BC4

I

VSS

I

VSS

I

VCACHE

POWER

GND

I

VCACHE

POWER

GND

I

VSS

I

VCACHE

I

BD30

BD31

BD32

BD33

BD34

BD35

BD36

BD37

BD38

BD39

BD4

VCACHE

POWER

GND

I

VSS

I

VSS

I

RSVD

IO

I

VCACHE

POWER

SCID Diff.

I

QPI0_DRX_DN[6]

VSS

SCID Diff.

GND

VCACHE

I

QPI0_DRX_DN[19]

QPI0_DRX_DP[19]

QPI0_DRX_DP[6]

QPI0_DRX_DN[9]

RSVD

I

RSVD

IO

I

QPI0_DRX_DN[3]

FBD0NBIBN[10]

QPI0_DRX_DP[3]

QPI0_DRX_DN[4]

VSS

SCID Diff.

Differential

SCID Diff.

GND

I

BC40

BC41

BC42

BC43

BC44

BC45

BC5

I

IO

I

VSS

GND

I

FBD0NBIBP[10]

QPI0_DRX_DN[5]

QPI0_DRX_DP[4]

VIOC

Differential

SCID Diff.

POWER

I

QPI1_DTX_DN[15]

QPI1_DTX_DP[13]

QPI1_DTX_DN[13]

VSS

SCID Diff.

GND

O

I

BD40

BD41

BD42

BD43

BD44

BD45

BD5

I

QPI1_DTX_DP[15]

VSS

SCID Diff.

GND

O

I

BC6

FBD0NBIAN[10]

FBD0NBIAP[11]

FBD0NBIAN[11]

RSVD

Differential

I

BC7

I

QPI1_DTX_DN[14]

FBD0NBIAN[9]

FBD0NBIAP[10]

VSS

SCID Diff.

Differential

GND

O

I

BC8

I

BC9

IO

I

BD6

I

BD10

BD11

BD12

BD13

MEM_THROTTLE1_N

VSS

GTL

BD7

I

GND

I

BD8

FBD0NBIAP[0]

RSVD

Differential

I

RSVD

IO

BD9

IO

I

RSVD

BE1

VSS

GND

92

Datasheet Volume 1 of 2

Pin Listing

Table 4-2.

Pin List, Sorted by land

Number (Sheet 17 of 39)

Table 4-2.

Pin List, Sorted by land

Number (Sheet 18 of 39)

Land #

Socket (EMTS)

Format

POWER

IO

Land #

Socket (EMTS)

Format

IO

BE10

BE11

BE12

BE13

BE14

BE15

BE16

BE17

BE18

BE19

BE2

VCC33

I

O

I

BE6

FBD0NBIAN[8]

FBD0NBIAP[8]

FBD0NBIAN[0]

VSS

Differential

GND

I

POWER

GND

BE7

I

VCC33

BE8

I

VSS

BE9

I

VSS

GND

BF1

FBD0NBIBN[7]

LT-SX (Test-Lo)

VSS

Differential

GTL

I

VCACHE

POWER

GND

BF10

BF11

BF12

BF13

BF14

BF15

BF16

BF17

BF18

BF19

BF2

I

VSS

GND

I

VCACHE

POWER

GND

RSVD

IO

I

VCACHE

VSS

GND

VSS

PSI_CACHE_N

VCACHE

CMOS

O

I

FBD0NBIBP[9]

VCACHE

Differential

POWER

GND

POWER

GND

BE20

BE21

BE22

BE23

BE24

BE25

BE26

BE27

BE28

BE29

BE3

VSS

I

VCACHE

POWER

GND

I

VSS

VCACHE

I

VCACHE

POWER

GND

VSS

I

VCACHE

FBD0NBIBP[7]

VCACHE

Differential

POWER

GND

I

VSS

BF20

BF27

BF28

BF29

BF3

I

VCACHE

POWER

GND

VCACHE

I

VCACHE

VSS

I

VSS

VCACHE

POWER

I

VCACHE

POWER

Differential

POWER

GND

RSVD

IO

I

FBD0NBIBN[8]

VCACHE

BF30

BF31

BF32

BF33

BF34

BF35

BF36

BF37

BF38

BF39

BF4

VCACHE

POWER

BE30

BE31

BE32

BE33

BE34

BE35

BE36

BE37

BE38

BE39

BE4

VSS

GND

I

VSS

QPI0_DRX_DN[17]

QPI0_DRX_DP[16]

VSS

SCID Diff.

GND

I

QPI0_DRX_DP[17]

QPI0_DRX_DN[18]

QPI0_DRX_DP[18]

QPI0_DRX_DN[10]

VSS

SCID Diff.

GND

I

QPI0_DRX_DP[10]

QPI0_CLKRX_DP

QPI0_CLKRX_DN

VSS

SCID Diff.

GND

I

QPI0_DRX_DP[9]

QPI0_DRX_DP[8]

QPI0_DRX_DN[8]

FBD0NBIBP[8]

QPI0_DRX_DP[5]

VSS

SCID Diff.

Differential

SCID Diff.

GND

I

QPI0_DRX_DP[7]

FBD0NBIBP[0]

QPI0_DRX_DN[7]

VIOC

SCID Diff.

Differential

SCID Diff.

POWER

I

BF40

BF41

BF42

BF43

BF44

BF45

BF46

BF5

I

BE40

BE41

BE42

BE43

BE44

BE45

BE46

BE5

I

VSS

GND

I

VIOC

POWER

SCID Diff.

GND

QPI0_DTX_DN[1]

QPI0_DTX_DN[2]

QPI0_DTX_DP[2]

QPI0_DTX_DN[3]

VSS

SCID Diff.

GND

O

I

QPI1_DTX_DP[16]

QPI1_DTX_DN[16]

QPI1_DTX_DP[14]

VSS

FBD0NBIAP[9]

Differential

BF6

FBD0NBIAN[7]

Differential

I

Datasheet Volume 1 of 2

93

Pin Listing

Table 4-2.

Pin List, Sorted by land

Number (Sheet 19 of 39)

Table 4-2.

Pin List, Sorted by land

Number (Sheet 20 of 39)

Land #

Socket (EMTS)

Format

GND

IO

Land #

Socket (EMTS)

Format

IO

BF7

VSS

I

BG8

FBD0NBIAP[2]

SPDDAT

Differential

CMOS

Differential

GTL

I

BF8

FBD0NBIAN[1]

FBD0NBIAP[1]

FBD0NBIBN[6]

SPDCLK

Differential

CMOS

BG9

I/OD

BF9

BH1

FBD0NBIBP[6]

BOOTMODE[0]

BOOTMODE[1]

SMBDAT

I

BG1

BH10

BH11

BH12

BH13

BH14

BH15

BH16

BH17

BH18

BH19

BH2

I

BG10

BG11

BG12

BG13

BG14

BG15

BG16

BG17

BG18

BG19

BG2

I/OD

GTL

I

SKTDIS_N

VSS

GTL

I

CMOS

GND

I/OD

I

GND

I

VSS

THERMALERT_N

VSS

CMOS

OD

I

SKTID[2]

CMOS

I

GND

RSVD

IO

I

VCACHE

POWER

GND

I

RSVD

VSS

I

VCACHE

POWER

VCACHE

POWER

GND

I

VCACHE

POWER

I

VCACHE

I

VSS

GND

I

VSS

I

FBD0NBIBN[12]

VCACHE

Differential

POWER

I

RSVD

IO

I

BH20

BH27

BH28

BH29

BH3

I

BG20

BG27

BG28

BG29

BG3

VCACHE

POWER

GND

VCACHE

POWER

I

VCACHE

I

VSS

GND

I

VSS

I

VCACHE

POWER

I

VCACHE

POWER

GND

I

FBD0NBICLKBN0

VCACHE

Differential

POWER

I

VSS

I

BH30

BH31

BH32

BH33

BH34

BH35

BH36

BH37

BH38

BH39

BH4

I

BG30

BG31

BG32

BG33

BG34

BG35

BG36

BG37

BG38

BG39

BG4

VCACHE

POWER

GND

I

VSS

GND

I

VSS

I

QPI0_DRX_DP[15]

QPI0_DRX_DN[15]

VIOC

SCID Diff.

POWER

I

RSVD

IO

I

QPI0_DRX_DN[16]

QPI0_DRX_DP[11]

QPI0_DRX_DN[11]

VIOC

SCID Diff.

POWER

I

VIOC

POWER

I

VSS

GND

I

QPI0_DTX_DP[18]

VIO_VID[1]

QPI0_DTX_DN[19]

FBD0NBICLKBP0

QPI0_DTX_DP[19]

VIOC

SCID Diff.

CMOS

O

I

VIOC

POWER

I

VIOC

POWER

I

SCID Diff.

Differential

SCID Diff.

POWER

VIOC

POWER

I

FBD0NBIBN[0]

VSS

Differential

GND

I

BH40

BH41

BH42

BH43

BH44

BH45

BH46

BH5

O

I

BG40

BG41

BG42

BG43

BG44

BG45

BG46

BG5

I

VIOC

POWER

I

QPI0_DTX_DP[0]

QPI0_DTX_DN[4]

QPI0_DTX_DP[4]

QPI0_DTX_DN[5]

VSS

SCID Diff.

GND

O

I

QPI0_DTX_DN[0]

QPI0_DTX_DP[1]

VSS

SCID Diff.

GND

O

I

RSVD

IO

O

I

QPI0_DTX_DP[3]

FBD0NBIAN[6]

FBD0NBIAP[7]

VSS

SCID Diff.

Differential

GND

FBD0NBIAP[6]

FBD0NBIAN[12]

FBD0NBIAP[12]

FBD0NBIAN[2]

Differential

I

BH6

I

BG6

I

BH7

I

BG7

I

BH8

I

94

Datasheet Volume 1 of 2

Pin Listing

Table 4-2.

Pin List, Sorted by land

Number (Sheet 21 of 39)

Table 4-2.

Pin List, Sorted by land

Number (Sheet 22 of 39)

Land #

Socket (EMTS)

Format

GND

IO

Land #

Socket (EMTS)

Format

GND

IO

BH9

VSS

I

BJ46

BJ5

VSS

I

BJ1

GND

GTL

GND

I

BJ10

BJ11

BJ12

BJ13

BJ14

BJ15

BJ16

BJ17

BJ18

BJ19

BJ2

RUNBIST

VSS

BJ6

FBD0NBIBP[1]

VSS

Differential

GND

I

GND

CMOS

BJ7

I

SMBCLK

I/OD

O

I

BJ8

FBD0NBICLKAN0

FBD0NBICLKAP0

VSS

Differential

GND

I

SKTOCC_N

SKTID[1]

FLASHROM_CFG[2]

CVID[3]

BJ9

I

CMOS

BK1

I

GTL

I

BK10

BK11

BK12

BK13

BK14

BK15

BK16

BK17

BK18

BK19

BK2

FBD0NBIAP[5]

FLASHROM_WP_N

SM_WP

Differential

GTL

I

CMOS

O

I

OD

I

VSS

GND

CMOS

VCACHE

POWER

GND

I

FLASHROM_CS_N[0]

SKTID[0]

GTL

OD

I

VSS

I

CMOS

FBD0NBIBP[12]

VCACHE

Differential

POWER

GND

I

VSS

GND

I

BJ20

BJ21

BJ22

BJ23

BJ24

BJ25

BJ26

BJ27

BJ28

BJ29

BJ3

I

CVID[2]

CMOS

O

IO

I

VCACHE

I

VSSCACHESENSE

VCACHESENSE

VSS

POWER

GND

VSS

I

VCACHE

POWER

GND

I

VCACHE

I

FBD0NBIBN[13]

VCACHE

Differential

POWER

GND

I

VSS

I

BK20

BK21

BK22

BK23

BK24

BK25

BK26

BK27

BK28

BK29

BK3

I

VCACHE

POWER

GND

I

VCACHE

I

VCACHE

I

VSS

I

VSS

I

VCACHE

POWER

GND

I

VCACHE

POWER

GND

I

VCACHE

I

VSS

I

VSS

I

BJ30

BJ31

BJ32

BJ33

BJ34

BJ35

BJ36

BJ37

BJ38

BJ39

BJ4

VCACHE

POWER

GND

I

VCACHE

POWER

GND

I

VSS

I

VCACHE

I

VSS

GND

I

VSS

I

QPI0_DRX_DN[12]

VSS

SCID Diff.

GND

I

VCACHE

POWER

Differential

POWER

GND

I

FBD0NBIBP[13]

VCACHE

I

QPI0_DTX_DP[17]

QPI0_DTX_DN[17]

QPI0_DTX_DN[18]

VSS

SCID Diff.

GND

O

I

BK30

BK31

BK32

BK33

BK34

BK35

BK36

BK37

BK38

BK39

BK4

I

VSS

I

QPI0_DRX_DP[14]

QPI0_DRX_DP[12]

VIOC

SCID Diff.

POWER

SCID Diff.

CMOS

I

QPI0_DTX_DP[12]

FBD0NBIBN[5]

QPI0_DTX_DP[10]

QPI0_DTX_DN[10]

VSS

SCID Diff.

Differential

SCID Diff.

GND

O

I

QPI0_DTX_DP[16]

QPI0_DTX_DP[14]

QPI0_DTX_DN[14]

VIO_VID[2]

QPI0_DTX_DN[12]

FBD0NBIBP[5]

VSS

O

I

BJ40

BJ41

BJ42

BJ43

BJ44

BJ45

O

I

QPI0_DTX_DN[6]

VSS

SCID Diff.

GND

O

I

SCID Diff.

Differential

GND

QPI0_DTX_DP[5]

SCID Diff.

O

BK40

I

Datasheet Volume 1 of 2

95

Pin Listing

Table 4-2.

Pin List, Sorted by land

Number (Sheet 23 of 39)

Table 4-2.

Pin List, Sorted by land

Number (Sheet 24 of 39)

Land #

Socket (EMTS)

Format

IO

Land #

Socket (EMTS)

Format

IO

BK41

BK42

BK43

BK44

BK45

BK46

BK5

QPI0_DTX_DP[8]

QPI0_DTX_DN[8]

QPI0_DTX_DP[6]

QPI0_DTX_DP[7]

QPI0_DTX_DN[7]

VSS

SCID Diff.

GND

O

I

BL37

BL38

BL39

BL4

QPI0_DTX_DN[13]

VSS

SCID Diff.

GND

O

I

QPI0_DTX_DP[11]

VSS

SCID Diff.

GND

O

I

BL40

BL41

BL42

BL43

BL44

BL45

BL46

BL5

QPI0_DTX_DN[11]

QPI0_CLKTX_DN

QPI0_DTX_DP[9]

QPI0_DTX_DN[9]

VSS

SCID Diff.

GND

O

I

FBD0NBIBN[4]

FBD0NBIBN[1]

VSS

Differential

GND

I

BK6

I

BK7

I

BK8

FBD0NBIAN[13]

FBD0NBIAN[5]

VSS

Differential

GND

I

VSS

GND

I

BK9

I

VSS

GND

I

BL1

I

FBD0NBIBP[4]

FBD0NBIBN[2]

FBD0NBIBP[2]

FBD0NBIAP[13]

VSS

Differential

GND

I

BL10

BL11

BL12

BL13

BL14

BL15

BL16

BL17

BL18

BL19

BL2

FBD0NBIAN[3]

FLASHROM_CLK

FLASHROM_DATI

VSS

Differential

GTL

I

BL6

I

OD

I

BL7

I

GTL

BL8

I

GND

I

BL9

I

FLASHROM_CS_N[2]

FLASHROM_CFG[0]

CVID[1]

GTL

OD

I

BM1

TEST[3]

GND

IO

I

GTL

BM10

BM11

BM12

BM13

BM14

BM15

BM16

BM17

BM18

BM19

BM2

FBD0NBIAP[3]

VSS

Differential

GND

CMOS

O

I

CVID[5]

CMOS

FLASHROM_DATO

FLASHROM_CS_N[1]

FLASHROM_CS_N[3]

FLASHROM_CFG[1]

VSS

GTL

OD

I

CVID[7]

CMOS

GTL

VSS

GND

GTL

VSS

GND

I

GTL

BL20

BL21

BL22

BL23

BL24

BL25

BL26

BL27

BL28

BL29

BL3

VCACHE

POWER

GND

I

GND

I

VCACHE

I

CVID[4]

CMOS

O

I

VSS

I

CVID[6]

CMOS

VCACHE

POWER

GND

I

VSS

GND

VCACHE

I

VSS

GND

I

VSS

I

BM20

BM21

BM26

BM27

BM28

BM29

BM3

VCACHE

POWER

GND

I

VCACHE

POWER

GND

I

VCACHE

I

VCACHE

I

VCACHE

I

VSS

I

VCACHE

I

VCACHE

POWER

GND

I

VSS

I

VSS

I

VCACHE

POWER

GND

I

BL30

BL31

BL32

BL33

BL34

BL35

BL36

VCACHE

POWER

GND

I

VSS

I

VSS

I

BM30

BM31

BM32

BM33

BM34

BM35

VCACHE

POWER

GND

I

QPI0_DRX_DN[14]

VSS

SCID Diff.

GND

I

VSS

I

QPI0_DRX_DP[13]

QPI0_DRX_DN[13]

VSS

SCID Diff.

GND

I

VIOC

POWER

SCID Diff.

GND

I

QPI0_DTX_DN[16]

VSS

O

I

QPI0_DTX_DP[15]

SCID Diff.

O

96

Datasheet Volume 1 of 2

Pin Listing

Table 4-2.

Pin List, Sorted by land

Number (Sheet 25 of 39)

Table 4-2.

Pin List, Sorted by land

Number (Sheet 26 of 39)

Land #

Socket (EMTS)

Format

IO

Land #

Socket (EMTS)

Format

POWER

IO

BM36

BM37

BM38

BM39

BM4

BM40

BM41

BM42

BM43

BM44

BM45

BM46

BM5

BM6

BM7

BM8

BM9

C1

QPI0_DTX_DN[15]

QPI0_DTX_DP[13]

VIO_VID[3]

VIO_VID[4]

VSS

SCID Diff.

CMOS

GND

O

I

C31

C32

C33

C34

C35

C36

C37

C38

C39

C4

VCCCORE

I

POWER

GND

I

VSS

I

VCCCORE

VSS

POWER

GND

I

VSS

GND

I

QPI0_CLKTX_DP

VSS

SCID Diff.

GND

O

I

VCCCORE

QPI3_DTX_DN[16]

FORCE_PR_N

QPI3_DTX_DP[16]

VSS

POWER

SCID Diff.

GTL

I

VSS

GND

I

O

I

VSS

GND

I

VSS

GND

I

C40

C41

C42

C43

C44

C45

C46

C5

SCID Diff.

GND

O

I

TEST[2]

FBD0NBIBN[3]

FBD0NBIBP[3]

VSS

GND

I

Differential

GND

I

QPI3_DTX_DP[13]

VSS

SCID Diff.

GND

O

I

QPI3_DTX_DP[10]

QPI3_DTX_DN[10]

RSVD

SCID Diff.

O

IO

I

FBD0NBIAN[4]

FBD0NBIAP[4]

VSS

Differential

GND

I

VSS

GND

C10

VCCCORE

VSS

POWER

GND

I

C6

VID[5]

CMOS

GND

IO

I

C11

I

C7

VID[4]

C12

VCCCORE

VSS

POWER

GND

I

C8

VSS

C13

I

C9

VCCCORE

VSS

POWER

GND

I

C14

I

D1

I

C15

VCCCORE

VSS

POWER

GND

I

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D2

VCCCORE

VSS

POWER

GND

I

C16

I

C17

I

VCCCORE

VSS

POWER

GND

I

C18

VCCCORE

VSS

POWER

GND

I

C19

I

C2

I

VCCCORE

VSS

POWER

GND

I

C20

VSS

GND

I

C21

VCCCORE

VSS

POWER

GND

I

C22

I

VCCCORE

PROCHOT_N

VSS

POWER

GTL

I

C23

I

C24

VSS

GND

I

OD

I

C25

VCCCORE

VSS

POWER

GND

I

D20

D21

D22

D23

D24

D25

D26

GND

C26

I

VCCCORE

VSS

POWER

GND

I

C27

I

C28

VCCCORE

PRDY_N

VSS

POWER

CMOS

GND

I

C29

I

VSS

GND

I

C3

O

I

VCCCORE

POWER

I

C30

I

Datasheet Volume 1 of 2

97

Pin Listing

Table 4-2.

Pin List, Sorted by land

Number (Sheet 27 of 39)

Table 4-2.

Pin List, Sorted by land

Number (Sheet 28 of 39)

Land #

Socket (EMTS)

Format

GND

IO

Land #

Socket (EMTS)

Format

POWER

IO

D27

D28

D29

D3

VSS

VCCCORE

I

E28

E29

E3

VCCCORE

I

POWER

CMOS

GND

I

POWER

GTL

I

VCCCORE

PREQ_N

VSS

I

MBP[5]_N

VSS

IO

I

E30

E31

E32

E33

E34

E35

E36

E37

E38

E39

E4

GND

D30

D31

D32

D33

D34

D35

D36

D37

D38

D39

D4

I

VCCCORE

VSS

POWER

GND

I

VCCCORE

VSS

POWER

GND

I

VCCCORE

VSS

POWER

GND

I

VCCCORE

VSS

POWER

GND

I

VCCCORE

QPI3_DTX_DN[18]

MBP[7]_N

QPI3_DTX_DN[19]

VSS

POWER

SCID Diff.

GTL

I

VCCCORE

VSS

POWER

GND

I

O

IO

O

I

RSVD

IO

O

IO

O

I

E40

E41

E42

E43

E44

E45

E46

E5

SCID Diff.

GND

D40

D41

D42

D43

D44

D45

D46

D5

QPI3_DTX_DP[19]

QPI3_DTX_DP[15]

QPI3_DTX_DN[15]

PECI

SCID Diff.

CMOS

SCID Diff.

GND

QPI3_DTX_DP[12]

VSS

SCID Diff.

GND

O

I

QPI3_CLKTX_DN

QPI3_DTX_DN[9]

QPI3_DTX_DP[9]

VSS

SCID Diff.

GND

O

I

QPI3_CLKTX_DP

VSS

GND

I

NMI

GTL

I

E6

VID[1]

CMOS

GND

IO

I

D6

VID[3]

CMOS

GND

IO

I

E7

VID[0]

D7

VID[2]

E8

VSS

D8

VSS

E9

VCCCORE

MBP[2]_N

VCCCORE

VSS

POWER

GTL

I

D9

VCCCORE

MBP[6]_N

VCCCORE

VSS

POWER

GTL

I

F1

IO

I

E1

IO

I

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

F2

POWER

GND

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E2

POWER

GND

I

VCCCORE

VSS

POWER

GND

I

VCCCORE

VSS

POWER

GND

I

VCCCORE

VSS

POWER

GND

I

VCCCORE

VSS

POWER

GND

I

VCCCORE

MBP[1]_N

VSS

POWER

GTL

I

VCCCORE

MBP[3]_N

VSS

POWER

GTL

I

IO

I

IO

I

F20

F27

F28

GND

E20

E27

GND

VSS

GND

I

VSS

GND

I

VCCCORE

POWER

I

98

Datasheet Volume 1 of 2

Pin Listing

Table 4-2.

Pin List, Sorted by land

Number (Sheet 29 of 39)

Table 4-2.

Pin List, Sorted by land

Number (Sheet 30 of 39)

Land #

Socket (EMTS)

Format

POWER

IO

Land #

Socket (EMTS)

Format

GTL OD

IO

F29

F3

VCCCORE

VSS

I

G3

ERROR0_N

VSS

IO

I

GND

I

G30

G31

G32

G33

G34

G35

G36

G37

G38

G39

G4

GND

F30

F31

F32

F33

F34

F35

F36

F37

F38

F39

F4

VSS

GND

I

VCCCORE

VSS

POWER

GND

I

VCCCORE

VSS

POWER

GND

I

VCCCORE

VSS

POWER

GND

I

VCCCORE

VSS

POWER

GND

I

VCCCORE

VSS

POWER

GND

I

VCCCORE

QPI3_DTX_DP[18]

MBP[4]_N

QPI3_DTX_DP[17]

QPI3_DTX_DN[17]

QPI3_DTX_DN[12]

QPI3_DTX_DN[4]

QPI3_DTX_DP[4]

VSS

POWER

SCID Diff.

GTL

I

O

IO

O

I

ERROR1_N

VSS

GTL-OD

GND

IO

I

G40

G41

G42

G43

G44

G45

G46

G5

F40

F41

F42

F43

F44

F45

F46

F5

SCID Diff.

GND

PWRGOOD

VSS

CMOS

I

GND

I

QPI3_DTX_DN[2]

QPI3_DTX_DN[7]

QPI3_DTX_DP[7]

QPI3_DTX_DN[8]

VSS

SCID Diff.

GND

O

I

QPI3_DTX_DP[8]

THERMTRIP_N

VSSCORESENSE

VCORESENSE

VSS

SCID Diff.

GTL-OD

POWER

GND

O

IO

I

G6

RSVD

IO

O

I

F6

G7

PSI_N

CMOS

F7

G8

VSS

GND

F8

G9

VCCCORE

FBD1SBODP[5]

VCCCORE

VSS

POWER

Differential

POWER

GND

I

F9

VCCCORE

VSS

POWER

GND

I

H1

O

I

G1

I

H10

H11

H12

H13

H14

H15

H16

H17

H18

H19

H2

G10

G11

G12

G13

G14

G15

G16

G17

G18

G19

G2

VCCCORE

VSS

POWER

GND

I

VCCCORE

VSS

POWER

GND

I

VCCCORE

VSS

POWER

GND

I

VCCCORE

VSS

POWER

GND

I

VCCCORE

VSS

POWER

GND

I

VCCCORE

FBD1SBODN[5]

VSS

POWER

Differential

GND

I

VCCCORE

MBP[0]_N

VSS

POWER

GTL

I

O

I

IO

I

H20

H21

H22

H23

H24

G20

G27

G28

G29

GND

VCCCORE

VSS

POWER

GND

I

VSS

GND

I

VCCCORE

POWER

I

VSS

GND

I

Datasheet Volume 1 of 2

99

Pin Listing

Table 4-2.

Pin List, Sorted by land

Number (Sheet 31 of 39)

Table 4-2.

Pin List, Sorted by land

Number (Sheet 32 of 39)

Land #

Socket (EMTS)

Format

POWER

IO

Land #

Socket (EMTS)

Format

GND

IO

H25

H26

H27

H28

H29

H3

VCCCORE

I

J20

J21

J22

J23

J24

J25

J26

J27

J28

J29

J3

VSS

VCCCORE

I

POWER

GND

I

POWER

GND

I

VSS

I

VCCCORE

VSS

I

VCCCORE

FBD1SBODN[9]

VSS

POWER

Differential

GND

I

VSS

GND

I

O

I

VCCCORE

VSS

POWER

GND

I

H30

H31

H32

H33

H34

H35

H36

H37

H38

H39

H4

I

VCCCORE

VSS

POWER

GND

I

VCCCORE

FBD1SBODP[9]

VSS

POWER

Differential

GND

I

VCCCORE

VSS

POWER

GND

I

O

I

J30

J31

J32

J33

J34

J35

J36

J37

J38

J39

J4

I

VCCCORE

VSS

POWER

GND

I

VCCCORE

VSS

POWER

GND

I

VCCCORE

VSS

POWER

GND

I

VSS

GND

I

H40

H41

H42

H43

H44

H45

H46

H5

VSS

GND

I

VIOPWRGOOD

QPI3_DTX_DN[1]

QPI3_DTX_DP[2]

VSS

CMOS

I

VCCCORE

VSS

POWER

GND

I

SCID Diff.

GND

O

I

FBD1SBODN[6]

QPI3_DTX_DN[0]

QPI3_DTX_DP[0]

QPI3_DTX_DP[1]

QPI3_DTX_DN[3]

QPI3_DTX_DP[3]

QPI3_DTX_DN[6]

QPI3_DTX_DP[5]

FBD1SBOCP[9]

FBD1SBOCLKCP0

VSS

Differential

SCID Diff.

Differential

GND

O

I

QPI3_DTX_DP[6]

VSS

SCID Diff.

GND

O

I

J40

J41

J42

J43

J44

J45

J46

J5

FBD1SBOCN[9]

FBD1SBOCP[5]

FBD1SBOCN[5]

VSS

Differential

GND

O

I

H6

H7

H8

H9

RSVD

IO

O

I

J1

FBD1SBOCLKDP0

VCCCORE

VSS

Differential

POWER

GND

J10

J11

J12

J13

J14

J15

J16

J17

J18

J19

J2

J6

I

J7

VCCCORE

VSS

POWER

GND

I

J8

FBD1SBOCN[6]

RSVD

Differential

O

IO

O

I

J9

I

K1

FBD1SBOCLKDN0

TCLK

Differential

GTL

VCCCORE

VSS

POWER

GND

I

K10

K11

K12

K13

K14

K15

I

VSS

GND

I

VCCCORE

VSS

POWER

GND

I

VCCCORE

VSS

POWER

GND

I

VCCCORE

POWER

I

100

Datasheet Volume 1 of 2

Pin Listing

Table 4-2.

Pin List, Sorted by land

Number (Sheet 33 of 39)

Table 4-2.

Pin List, Sorted by land

Number (Sheet 34 of 39)

Land #

Socket (EMTS)

Format

POWER

IO

Land #

Socket (EMTS)

Format

GND

IO

K16

K17

K18

K19

K2

VCCCORE

VSS

I

L11

L2

VSS

I

GND

I

FBD1SBODP[3]

VSS

Differential

GND

O

I

VCCCORE

FBD1SBODN[4]

VSS

POWER

Differential

GND

I

L3

I

L36

L37

L38

L39

L4

VSS

GND

I

O

I

VSS

GND

I

K20

K21

K22

K23

K24

K25

K26

K27

K28

K29

K3

QPI3_DRX_DP[16]

QPI3_DRX_DP[15]

VSS

SCID Diff.

GND

I

VCCCORE

VSS

POWER

GND

I

L40

L41

L42

L43

L44

L45

L46

L5

QPI3_DRX_DN[15]

QPI3_DRX_DP[13]

QPI3_DRX_DP[12]

QPI3_DRX_DN[12]

QPI3_DRX_DN[11]

VSS

SCID Diff.

GND

I

VSS

GND

I

VCCCORE

VSS

POWER

GND

I

VCCCORE

FBD1SBODP[4]

VSS

POWER

Differential

GND

I

VSS

GND

I

O

I

FBD1SBOCN[3]

VSS

Differential

GND

O

I

K30

K31

K32

K33

K34

K35

K36

K37

K38

K39

K4

L6

VCCCORE

VSS

POWER

GND

I

L7

FBD1SBOCP[4]

FBD1SBOCN[4]

TDI

Differential

GTL

O

I

L8

I

L9

VCCCORE

VSS

POWER

GND

I

M1

VSS

GND

I

M10

M11

M2

TRST_N

GTL

I

VSS

GND

I

VCCCORE

VSS

POWER

GND

I

VSS

GND

I

M3

FBD1SBODP[7]

VIOC

Differential

POWER

GND

O

I

M36

M37

M38

M39

M4

FBD1SBODP[6]

VSS

Differential

GND

O

I

VSS

I

K40

K41

K42

K43

K44

K45

K46

K5

QPI3_DRX_DN[16]

RSVD

SCID Diff.

I

VSS

GND

I

IO

O

I

VSS

GND

I

FBD1SBODN[7]

QPI3_DRX_DP[14]

QPI3_DRX_DN[13]

VSS

Differential

SCID Diff.

GND

VSS

GND

I

M40

M41

M42

M43

M44

M45

M46

M5

VSS

GND

I

VSS

GND

I

QPI3_DTX_DN[5]

VSS

SCID Diff.

GND

O

I

QPI3_DRX_DP[10]

QPI3_DRX_DP[11]

QPI3_CLKRX_DP

VSS

SCID Diff.

GND

I

K6

FBD1SBOCLKCN0

VSS

Differential

GND

O

I

K7

I

K8

FBD1SBOCP[6]

VSS

Differential

GND

O

I

FBD1SBOCP[3]

FBD1SBOCN[2]

FBD1SBOCP[2]

VSS

Differential

GND

O

I

K9

M6

L1

FBD1SBODN[3]

TDO

Differential

GTL OD

O

M7

L10

M8

Datasheet Volume 1 of 2

101

Pin Listing

Table 4-2.

Pin List, Sorted by land

Number (Sheet 35 of 39)

Table 4-2.

Pin List, Sorted by land

Number (Sheet 36 of 39)

Land #

Socket (EMTS)

Format

GTL

IO

Land #

Socket (EMTS)

Format

IO

M9

TMS

I

P6

FBD1SBOCP[1]

VSS

Differential

GND

O

I

N1

FBD1SBODN[1]

VSS

Differential

GND

O

I

P7

N10

N11

N2

P8

FBD1SBOCP[10]

RSVD

Differential

O

IO

I

VSS

GND

I

P9

FBD1SBODP[2]

FBD1SBODN[2]

VSS

Differential

GND

O

I

R1

VSS

GND

N3

R10

R11

R2

VIOF

POWER

I

N36

N37

N38

N39

N4

VIOF

POWER

I

QPI3_DRX_DP[17]

QPI3_DRX_DN[17]

VSS

SCID Diff.

GND

I

FBD1SBODP[0]

FBD1SBODP[10]

VSS

Differential

GND

O

I

R3

I

R36

R37

R38

R39

R4

FBD1SBODP[8]

QPI3_DRX_DN[14]

QPI3_DRX_DN[1]

QPI3_DRX_DP[1]

QPI3_DRX_DN[10]

VSS

Differential

SCID Diff.

GND

O

I

VSS

GND

I

N40

N41

N42

N43

N44

N45

N46

N5

QPI3_DRX_DP[19]

QPI3_DRX_DN[19]

FBD1SBODN[10]

VSS

SCID Diff.

Differential

GND

I

O

I

R40

R41

R42

R43

R44

R45

R46

R5

I

QPI3_DRX_DP[0]

QPI3_DRX_DP[2]

QPI3_DRX_DN[5]

QPI3_DRX_DP[5]

QPI3_DRX_DP[7]

VSS

SCID Diff.

GND

I

QPI3_CLKRX_DN

QPI3_DRX_DP[9]

VSS

SCID Diff.

GND

I

N6

FBD1SBOCN[1]

FBD1SBOCP[7]

FBD1SBOCN[7]

VSS

Differential

GND

O

I

N7

I

N8

FBD1SBOCP[0]

FBD1SBOCP[8]

FBD1SBOCN[8]

FBD1SBOCN[10]

RSVD

Differential

O

IO

I

N9

R6

P1

FBD1SBODP[1]

VIOF

Differential

POWER

O

I

R7

P10

P11

P2

R8

VIOF

POWER

I

R9

FBD1SBODN[0]

VSS

Differential

GND

O

I

T1

VIOF

POWER

GND

P3

T10

T11

T2

VSS

I

P36

P37

P38

P39

P4

VIOC

POWER

I

VSS

GND

I

RSVD

IO

I

VIOF

POWER

GND

I

RSVD

T3

VSS

I

QPI3_DRX_DP[18]

FBD1SBODN[8]

QPI3_DRX_DN[18]

QPI3_DRX_DN[0]

VSS

SCID Diff.

Differential

SCID Diff.

GND

T36

T37

T38

T39

T4

VSS

GND

I

O

I

VSS

GND

I

P40

P41

P42

P43

P44

P45

P46

P5

SYSCLK_DN

QPI2_DRX_DP[15]

VIOF

Differential

SCID Diff.

POWER

SCID Diff.

GND

I

VSS

GND

I

T40

T41

T42

T43

T44

QPI2_DRX_DN[15]

QPI2_DRX_DP[14]

QPI3_DRX_DN[2]

QPI3_DRX_DP[3]

VSS

I

QPI3_DRX_DN[8]

QPI3_DRX_DP[8]

QPI3_DRX_DN[9]

FBD1SBOCN[0]

SCID Diff.

Differential

I

O

I

102

Datasheet Volume 1 of 2

Pin Listing

Table 4-2.

Pin List, Sorted by land

Number (Sheet 37 of 39)

Table 4-2.

Pin List, Sorted by land

Number (Sheet 38 of 39)

Land #

Socket (EMTS)

Format

IO

Land #

Socket (EMTS)

Format

POWER

IO

T45

T46

T5

QPI3_DRX_DN[7]

QPI3_DRX_DP[6]

VSS

SCID Diff.

GND

I

V42

V43

V44

V45

V46

V5

VIOC

I

POWER

GND

I

VIOC

I

T6

VIOF

POWER

VIOC

I

T7

VIOF

POWER

VSS

I

T8

VIOF

POWER

VSS

GND

I

T9

VSS

GND

V6

FBD1NBICP[9]

FBD1NBICP[10]

FBD1NBICN[10]

VSS

Differential

GND

I

U1

VIOF

POWER

V7

I

U10

U11

U2

VIOF

POWER

V8

I

VIOF

POWER

V9

I

VSS

GND

W1

FBD1NBIDP[8]

VSS

Differential

GND

I

U3

FBD1NBIDP[10]

VIOC

Differential

POWER

W10

W11

W2

I

U36

U37

U38

U39

U4

VSS

GND

I

QPI2_DRX_DP[17]

SYSCLK_DP

VSS

SCID Diff.

Differential

GND

FBD1NBIDN[7]

VSS

Differential

GND

I

W3

I

W36

W37

W38

W39

W4

VSS

GND

I

FBD1NBIDN[10]

QPI2_DRX_DP[13]

QPI2_DRX_DN[14]

VSS

Differential

SCID Diff.

GND

VSS

GND

I

U40

U41

U42

U43

U44

U45

U46

U5

RSVD

IO

I

QPI2_DRX_DP[12]

FBD1NBIDN[11]

QPI2_DRX_DN[12]

QPI2_DRX_DP[11]

VSS

SCID Diff.

Differential

SCID Diff.

GND

I

QPI3_DRX_DN[3]

QPI3_DRX_DN[4]

QPI3_DRX_DP[4]

QPI3_DRX_DN[6]

VIOF

SCID Diff.

POWER

W40

W41

W42

W43

W44

W45

W46

W5

I

QPI2_DTX_DN[18]

QPI2_DTX_DP[16]

QPI2_DTX_DN[16]

QPI2_DTX_DP[15]

FBD1NBICN[7]

VSS

SCID Diff.

Differential

GND

O

I

U6

FBD1NBICN[9]

VSS

Differential

GND

U7

U8

VIOF

POWER

U9

VIOF

POWER

W6

I

V1

FBD1NBIDN[8]

VSS

Differential

GND

W7

VSS

GND

I

V10

V11

V2

W8

FBD1NBICP[11]

RSVD

Differential

I

VSS

GND

W9

IO

I

FBD1NBIDP[9]

FBD1NBIDN[9]

VSS

Differential

GND

Y1

VSS

GND

V3

Y10

Y11

Y2

RSVD

IO

I

V36

V37

V38

V39

V4

VIOF

POWER

QPI2_DRX_DN[17]

QPI2_DRX_DP[16]

QPI2_DRX_DN[16]

FBD1NBIDP[11]

QPI2_DRX_DN[13]

VSS

SCID Diff.

Differential

SCID Diff.

GND

FBD1NBIDP[7]

FBD1NBIDN[6]

VIOC

Differential

POWER

I

Y3

I

Y36

Y37

Y38

Y39

I

QPI2_DRX_DP[18]

QPI2_DRX_DN[18]

VSS

SCID Diff.

GND

I

V40

V41

I

Datasheet Volume 1 of 2

103

Pin Listing

Table 4-2.

Pin List, Sorted by land

Number (Sheet 39 of 39)

Land #

Socket (EMTS)

Format

IO

Y4

FBD1NBIDP[6]

QPI2_DRX_DP[10]

QPI2_DRX_DN[11]

VIOC

Differential

SCID Diff.

POWER

I

Y40

Y41

Y42

Y43

Y44

Y45

Y46

Y5

I

QPI2_DTX_DP[18]

VSS

SCID Diff.

GND

O

I

QPI2_DTX_DP[14]

QPI2_DTX_DN[15]

FBD1NBICP[7]

FBD1NBICP[8]

FBD1NBICN[8]

FBD1NBICN[11]

RSVD

SCID Diff.

Differential

O

I

Y6

I

Y7

I

Y8

I

Y9

IO

§

104

Datasheet Volume 1 of 2

Signal Definitions

5 Signal Definitions

Table 5-1.

Signal Definitions (Sheet 1 of 6)

Name

Type

Description

BOOTMODE[1:0]

I

The BOOTMODE[1:0] inputs are to specify which mode the Intel Xeon Processor E7-

8800/4800/2800 Product Families processor will boot to. For details on the modes

refer to the Intel® Xeon® Processor 7500 Series Datasheet, Volume 2.

CVID[7:1]

O

IO

I

Voltage ID driven out to the VR 11.1 for dynamic/static adjustment of processor

voltage set point. See VCACHE below. This signal has on die termination.

ERROR[0]_N

Pulsed Signal. As output, signals un-corrected error condition of the processor. As an

input, can be programmed to signal SMI to the cores. Open drain

ERROR[1]_N

Level Signal. As output, signals fatal error condition of the processor. As an input,

can be programmed to signal SMI to the cores. Open drain.

FBD0NBI[A/B][P/N][13:0]

These differential pair data signals generated from the branch zero, channel A and B

of Intel® SMI links are input to the Intel Xeon Processor E7-8800/4800/2800

Product Families processor.

Intel

SMI

0

NB

I

A/B

P/N

[13:0]

Interface

Name

Branch

North

Input

Channel Differential Lane

Number Bound

Pair

Number

Polarity

Positive/

Negative

Example: FBD0NBIAP[0] Intel SMI branch 0, North bound data input lane 0 signal of

channel A and positive bit of the differential pair.

FBD0NBICLK[A/B][P/N]0

I

These differential pair clock signals generated from the branch zero, channel A and B

of Intel® SMI links are input to the Intel Xeon Processor E7-8800/4800/2800

Product Families processor.

Intel

SMI

0

NB

I

CLK

A/B

P/N

Interface Branch

North

Input

Clock

Channel Differential

Pair

Name

Number Bound

Polarity

Positive/

Negative

Example: FBD0NBICLKAP0 Intel SMI branch 0, Northbound clock input signal of

channel A and positive bit of the differential pair.

FBD0SBO[A/B][P/N][10:0]

O

These differential pair output data signals generated from Intel Xeon Processor E7-

8800/4800/2800 Product Families processor to the branch zero, channel A and B of

Intel® SMI links.

Intel

SMI

0

SB

O

A/B

P/N

[10:0]

Interface Branch

Name

South

Output

Channel

Differential Lane

Number Bound

Pair

Number

Polarity

Positive/

Negative

Example: FBD0SBOAP[0] Intel SMI branch 1, southbound data output lane 0 signal

of channel A and positive bit of the differential pair.

Datasheet Volume 1 of 2

105

Signal Definitions

Table 5-1.

Signal Definitions (Sheet 2 of 6)

Name

Type

Description

FBD0SBOCLK[A/B][P/N]0

O

These differential pair output clock signals generated from Intel Xeon Processor E7-

8800/4800/2800 Product Families processor are inputs to the branch zero, channel A

and B of Intel® SMI links.

Intel

SMI

0

SB

O

CLK

A/B

P/N

Interface Branch

Name

South

Output

Clock

Channel Differential

Pair

Number Bound

Polarity

Positive/

Negative

Example: FBD0SBICLKAP0 Intel SMI branch 0, south bound clock output signal of

channel A and positive bit of the differential pair.

FBD1NBI[C/D][P/N][13:0]

FBD1NBICLK[C/D][P/N]0

FBD1SBO[C/D][P/N][10:0]

I

These differential pair output data signals generated from Intel Xeon Processor E7-

8800/4800/2800 Product Families processor are inputs to the branch one, channel C

and D of Intel® SMI links.

Intel

SMI

1

NB

I

C/D

P/N

[13:0]

Interface Branch

Name

North

Input

Channe Differential Lane

Number Bound

l

Pair

Number

Polarity

Positive/

Negative

Example: FBD1NBIAP[0] Intel SMI branch 1, North bound data input lane 0 signal of

channel A and positive bit of the differential pair.

I

These differential pair clock signals generated from the branch one, channel C and D

of Intel® SMI links are input to the Intel Xeon Processor E7-8800/4800/2800

Product Families processor.

Intel

SMI

1

NB

I

CLK

C/D

P/N

Interface Branch

Name

North

Input

Clock

Channel Differential

Pair

Number Bound

Polarity

Positive/

Negative

Example: FBD1NBICLKAP0 Intel SMI branch 1, Northbound clock input signal of

channel A and positive bit of the differential pair.

O

These differential pair output data signals generated from Intel Xeon Processor E7-

8800/4800/2800 Product Families processor to the branch one, channel C and D of

Intel® SMI links.

Intel

SMI

1

NB

O

C/D

P/N

[10:0]

Interface Branch

Name

North

Output

Channel Differential Lane

Number Bound

Pair

Number

Polarity

Positive/

Negative

Example: FBD1SBOAP[0] Intel SMI branch 1, South bound data Output lane 0 signal

of channel A and positive bit of the differential pair.

106

Datasheet Volume 1 of 2

Signal Definitions

Table 5-1.

Signal Definitions (Sheet 3 of 6)

Name

FBD1SBOCLK[C/D][P/N]0

Type

Description

O

These differential pair output clock signals generated from Intel Xeon Processor E7-

8800/4800/2800 Product Families processor are inputs to the branch one, channel C

and D of Intel® SMI links.

Intel

SMI

1

SB

O

CLK

C/D

P/N

Interface

Name

Branch

South

Output

Clock

Channel Differential

Pair

Number Bound

Polarity

Positive/

Negative

Example: FBD1SBICLKAP0 Intel SMI branch 1, south bound clock output signal of

channel A and positive bit of the differential pair.

FLASHROM_CFG[2:0]

I

These are input signals to the Intel Xeon Processor E7-8800/4800/2800 Product

Families processor that would initialize and map the serial Flash ROM upon reset.

After the reset is deasserted this input would be ignored by the processor logic.

FLASHROM_CLK

FLASHROM_CS[3:0]_N

FLASHROM_DATI

FLASHROM_DATO

FLASHROM_WP_N

FORCE_PR_N

O

I

Serial flash ROM clock.

Serial Flash ROM chip selects. Up to four separate flash ROM parts may be used.

Serial Data Input (from ROM(s) to processor).

Serial Data Output (from processor to ROM(s)).

Flash ROM write-protect.

O

I

Force processor power reduction by activation of a TCC.

Current sense for Vcore VR11.1

ISENSE_D[N/P]

LT-SX (Test-Lo)

IO

I

In platforms supporting the Intel TXT feature, the Intel TXT pin on the processor

should be variable setting and driven based on the processor type installed. With

Intel Xeon Processor E7-8800/4800/2800 Product Families processor installed, the

Intel TXT pin should be driven high to support Intel TXT. With Intel® Xeon®

processor 7500 series installed the Intel TXT pin should be driven low. Note that TXT

is not supported on the Intel® Xeon® processor 7500 series. On platforms not

supporting the TXT feature, the pin can be strapped low. For Intel® Xeon®

processor 7500 series debug purposes, you will need that ability to pull Intel TXT

low.

MBP[7:0]

IO

I

Sideband signals connecting to XDP header for Run-time control and debug.

MEM_THROTTLE[1:0]_N

When asserted, the internal memory controllers throttle the memory command issue

rate to a configurable fraction of the nominal command rate settings.

MEM_Throttle[1] corresponds to mem_ctrl behind the HA xxx 11, and

MEM_Throttle[0] corresponds to mem_ctrl behind HA xxx 01.

NMI

I

IO

O

I

Interrupt input. Active high. Must be minimum of three clocks.

Processor Sideband Access via PECI interface.

Processor debug interface.

PECI

PRDY_N

PREQ_N

Proc_ID[1:0]

Processor debug interface.

O

Processor ID. 11: Intel® Xeon® processor 7500. 10: Intel Xeon Processor E7-8800/

4800/2800 Product Families. 01, 00: Reserved for future generations.

PROCHOT_N

O

The assertion of PROCHOT_N (processor hot) indicates that the processor die

temperature has reached its thermal limit. Open Drain Output.

PSI_CACHE_N

Vcache Power Status Indicator signal to the VR that the processor is in package C3

or C6 power states so the VR can use fewer phases. This signal has on die

termination of 50 ohms.

PSI_N

O

Vcore Power Status Indicator signal to the VR that the processor is in package C3 or

C6 power states so the VR can use fewer phases. This signal has on die termination

of 50 ohms.

Datasheet Volume 1 of 2

107

Signal Definitions

Table 5-1.

Signal Definitions (Sheet 4 of 6)

Name

Type

Description

PWRGOOD

I

The processor requires this signal to be a clean indication that all Intel Xeon

Processor E7-8800/4800/2800 Product Families processor clocks and power supplies

are stable and within their specifications. “Clean” implies that the signal will remain

low (capable of sinking leakage current), without glitches, from the time that the

power supplies are turned on until they come within specification. The signal must

then transition monotonically to a high state. PWRGOODcan be driven inactive at any

time, but clocks and power must again be stable before a subsequent rising edge of

PWRGOOD.

The PWRGOOD signal must be supplied to the processor at 1.1V. This signal is used

to protect internal circuits against voltage sequencing issues. It should be driven

high throughout boundary scan operation. VCCSTBY33 signal should be stable for 10

SYSCLOCKs before PWRGOOD is asserted.

QPI[3:0]_DRx_D[P/N][19:0],

QPI[3:0]_CLKRX_D[P/N]

I

O

I

These Intel QPI input data signals provide means of communication between two

Intel QPI ports via one uni-directional transfer link (In). The Rx links, are terminally

ground referenced. These signals can be configured as a full width link with 20 active

lanes, a half width link with 10 active lanes or as a quarter width link with five active

lanes.

Intel QPI

Interface

3:0

R

P/N

DAT[19:0]

Interface

Name

Port Number Receiver

Differential

Pair

Lane

Number

Polarity

Positive/

Negative

Example: QPI4RPDAT[0] represents Intel QPI port 5 Data, lane 0,receive signal and

Positive bit of the differential pair.

QPI[3:0]_DTX_D[P/

N][19:0],QPI[3:0]_clkTX_D[P/N]

These Intel QPI output data signals provide means of communication between two

Intel QPI ports via one uni-directional transfer link (Out).The links, Tx, are terminally

ground referenced. These signals can be configured as a full width link with 20 active

lanes, a half width link with 10 active lanes or as a quarter width link with five active

lanes.

Intel QPI

Interface

3:0

T

P/N

DAT[19:0]

Interface

Name

Port Number Transmitter

Differential

Pair

Lane

Number

Polarity

Positive/

Negative

Example: QPI4RPDAT[0] represents Intel QPI port 5 Data, lane 0,Transmit signal and

Positive bit of the differential pair.

RESET_N

Asserting the RESET_N signal resets the processor to a known state and invalidates

its internal caches without writing back any of their contents. BOOTMODE[0:1]

signals are sampled at the active-to-inactive transition of RESET_N for selecting

appropriate BOOTMODE. Also RUNBIST is sampled at the active-to-inactive

transition of RESET_N to select BIST operation.

RSVD

These Pins are reserved and should be treated as NO CONNECT, left unconnected.

RUNBIST

I

This input pin is sampled on a active-to-inactive transition of RESET_N. If sampled

high, this enables BIST (Recommended).

SKTDIS_N

Sampled with the rising edge of RESET_N input. Asserted, signal will disable the

socket, tri-state I/O.

SKTID[2:0]

Socket ID strapping pins. These pins determine the addresses to be used on the

SMBus to access the processor.

SKTOCC_N

SM_WP

O

I

Static signal, asserted low when the socket is occupied with processor.

WP (Write Protect) can be used to write protect the Scratch EEPROM. The Scratch

EEPROM is write-protected when this input is pulled high to VCCSTBY33.

108

Datasheet Volume 1 of 2

Signal Definitions

Table 5-1.

Signal Definitions (Sheet 5 of 6)

Name

Type

Description

SMBCLK

I/O

The SMBus Clock (SMBCLK) signal is an input clock to the system management logic

which is required for operation of the system management features of the Intel Xeon

Processor E7-8800/4800/2800 Product Families processor. This clock is driven by the

SMBus controller and is asynchronous to other clocks in the processor. This is an

open drain signal.

SMBDAT

SPDCLK

SPDDAT

I/O

I

The SMBus Data (SMBDAT) signal is the data signal for the SMBus. This signal

provides the single-bit mechanism for transferring data between SMBus devices.

This is an open drain signal.

This is a bi-directional clock signal between Intel Xeon Processor E7-8800/4800/

2800 Product Families processor, DRAM SPD registers and external components on

the board. This is an open drain signal.

This is a bi-directional data signal between Intel Xeon Processor E7-8800/4800/2800

Product Families processor, DRAM SPD registers and external components on the

board. This is an open drain signal.

SYSCLK_DP/SYSCLK_DP

The differential clock pair SYSCLK_DP/SYSCLK_DN provides the fundamental clock

source for the Intel Xeon Processor E7-8800/4800/2800 Product Families processor.

All processor link agents must receive these signals to drive their outputs and latch

their inputs. All external timing parameters are specified with respect to the rising

edge of SYSCLK crossing the falling edge of SYSCLK_N. These differential clock pair

should not be asserted until VCCCORE, VIOC, VIOF, VCACHE and VCC33 are

stabilized.

SYSCLK_LAI/SYSCLK_LAI_N

I

These are reference clocks used only for debug purposes. Electrical specifications on

these clocks are identical to SYSCLK_DP/SYSCLK_DN.

TCK

TDI

I

Test Clock (TCK) provides the clock input for the processor TAP.

Test Data In (TDI) transfers serial test data into the processor. TDI provides the

serial input needed for JTAG specification support.

TDO

O

I

Test Data Out (TDO) transfers serial test data out of the processor. TDO provides the

serial output needed for JTAG specification support. This is an open drain output.

TEST[3:0]

Four corner pins used to study socket corner joint reliability. VSS on package,

however, not required to be connected.

Test-Hi

I

Strap pins to VIO via TBD resistor.

THERMALERT_N

O

Thermal Alert (THERMALERT_N) is an output signal and is asserted when the on-die

thermal sensors readings exceed a pre-programmed threshold.

THERMTRIP_N

O

The processor protects itself from catastrophic overheating by use of an internal

thermal sensor. To ensure that there are no false trips, Thermal Trip (THERMTRIP_N)

will activate at a temperature that is about 115°C as measured at the core. Once

activated, the processor will stop all execution and the signal remains latched until

RESET_N goes active. It is strongly recommended that all power be removed from

the processor before bringing the processor back up. If the temperature has not

dropped below the trip level, the processor will continue to drive THERMTRIP_N and

remain stopped. Strapping is 1k-10k Ohms.

TMS

I

Test Mode Select (TMS) is a JTAG specification support signal used by debug tools.

TRST_N

Test Reset (TRST_N) resets the TAP logic. TRST_N must be driven electrically low

during power on Reset.

VCACHE

I

This provides power to processor LLC and system interface logic. Actual value of the

voltage is determined by the settings of CVID[7:1].

VCACHESENSE

VCC33

IO

I

VR Sense lines. (VCACHE)

VCC33 supplies 3.3V to PIROM/OEM Scratch ROM, INITROM and level translators.

This supply is required both for PIROM usage and for correct processor boot

operation.

VCCCORE

I

This provides power to the Cores on the processor. Actual value of the voltage is

determined by the settings of VID[7:0].

VSSCOREESENSE

IO

VR Sense lines. (Vcore)

Datasheet Volume 1 of 2

109

Signal Definitions

Table 5-1.

Signal Definitions (Sheet 6 of 6)

Name

Type

Description

VID[7:0]

I/O

VID[7:0] is an input only during Power On Configuration. It is an output signal

during normal operation.

As an output, VID[7:0] (Voltage ID) are signals that are used to support automatic

selection of power supply voltages (V ). Refer to the Voltage Regulator Module

CC

(VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.1 Design Guidelines for

more information. The voltage supply for these signals must be valid before the VR

can supply V to the processor. Conversely, the VR output must be disabled until

CC

the voltage supply for the VID signals become valid. The VID signals are needed to

support the processor voltage specification variations. The VR must supply the

voltage that is requested by the signals, or disable itself.

As an inputs during Power On Configuration:

VID [7] is an electronic safety key for distinguishing VR11.1 from PMPV6.

VID[6] is a spare bit reserved for future use.

VID[5:3] - IMON bits are output signals for IMON gain setting. See Voltage

Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.1

Design Guidelines for gain setting information.

VID[2:0] or MSID[2:0] - Market Segment ID, or MSID are provided to indicate the

Market Segment for the processor and may be used for future processor

compatibility or for keying. In addition, MSID protects the platform by preventing a

higher power processor from booting in a platform designed for lower power

processors. This value is latched from the platform in to the CPU, on the rising edge

of VioPWRGOOD, during the cold boot power up sequence.

VIO_VID[4:1]

O

Voltage ID driven out to the VR 11.1 for dynamic/static adjustment of processor

voltage set point. Note that these pins are either floated, or tied to ground on the

package.

VIOC

VIOF

I

VIOC provides power to the input/output interface on the Intel Xeon Processor E7-

8800/4800/2800 Product Families processor Intel® QPI I/O.

VIOF provides power to the input/output interface on the Intel Xeon Processor E7-

8800/4800/2800 Product Families processor Intel® SMI I/O.

VIOPowerGood

VREG

I

VIO Power Good signal.

~1.8 V. Voltage to PLLs.

VSS

VSS is the ground plane for the Intel Xeon Processor E7-8800/4800/2800 Product

Families processor.

VSSCACHESENSE

IO

VR Sense lines. (Vcache)

§

110

Datasheet Volume 1 of 2

Thermal Specifications

6 Thermal Specifications

6.1

Package Thermal Specifications

The Intel Xeon Processor E7-8800/4800/2800 Product Families processor requires a

thermal solution to maintain temperatures within its operating limits. Any attempt to

operate the processor outside these operating limits may result in permanent damage

to the processor and potentially other components within the system. For more

information on designing a component level thermal solution, refer to the Intel®

Xeon® Processor 7500 Series and Intel® Xeon® Processor E7-8800/4800/2800

Product Families Thermal and Mechanical Design Guide.

A complete solution includes both component and system level thermal management

features. Component level thermal solutions can include active or passive heatsinks

attached to the processor integrated heat spreader (IHS). Typical system level thermal

solutions may consist of system fans combined with ducting and venting.

6.1.1

Thermal Specifications

To allow the optimal operation and long-term reliability of Intel® processor-based

systems, the processor must remain within the minimum and maximum case

temperature (T_CASE) specifications as defined by the applicable thermal profile (see

Table 6-1 and Figure 6-1 for 130W TDP Intel Xeon Processor E7-8800/4800/2800

Product Families processor, Table 6-1 and Figure 6-2 for 105W TDP Intel Xeon

Processor E7-8800/4800/2800 Product Families processor, and Table 6-1 and

Figure 6-3 for 95W TDP Intel Xeon Processor E7-8800/4800/2800 Product Families

processor). Thermal solutions not designed to provide this level of thermal capability

may affect the long-term reliability of the processor and system. For more details on

thermal solution design, please refer to the Intel® Xeon® Processor 7500 Series and

Intel® Xeon® Processor E7-8800/4800/2800 Product Families Thermal and Mechanical

Design Guide.

Intel Xeon Processor E7-8800/4800/2800 Product Families processor implements a

methodology for managing processor temperatures which is intended to support

acoustic noise reduction through fan speed control and to ensure processor reliability.

Selection of the appropriate fan speed is based on the relative temperature data

reported by the processor’s Platform Environment Control Interface (PECI) bus as

described in Section 6.3. The temperature reported over PECI is always a negative

value and represents a delta below the onset of thermal control circuit (TCC) activation,

as indicated by PROCHOT_N (see Section 6.2, “Processor Thermal Features” on

page 118). Systems that implement fan speed control must be designed to use this

data. Systems that do not alter the fan speed only need to guarantee that the case

temperature meets the thermal profile specifications.

Intel has developed a thermal profile that can be implemented with 130W TDP Intel

Xeon Processor E7-8800/4800/2800 Product Families processor to ensure adherence to

Intel reliability requirements. The 130W TDP Intel Xeon Processor E7-8800/4800/2800

Product Families processor Thermal Profile (see Figure 6-1; Table 6-2) is representative

of a volumetrically unconstrained thermal solution (that is, industry enabled 4U

heatsink). In this scenario, it is expected that the Thermal Control Circuit (TCC) would

only be activated for very brief periods of time when running the most power intensive

Datasheet Volume 1 of 2

111

Thermal Specifications

applications. Intel has developed the thermal profile to allow customers to choose the

thermal solution and environmental parameters that best suit their platform

implementation.

The 105W TDP Intel Xeon Processor E7-8800/4800/2800 Product Families processor

(see Figure 6-2; Table 6-3) and 95W TDP Intel Xeon Processor E7-8800/4800/2800

Product Families processor (see Figure 6-3; Table 6-4) support a single Thermal Profile.

The Thermal Profiles are indicative of a constrained thermal environment. Utilization of

a thermal solution that does not meet the Thermal Profile will violate the thermal

specifications and may result in permanent damage to the processor.

The upper point of the thermal profile consists of the Thermal Design Power (TDP) and

the associated T_{CASE_MAX}value. It should be noted that the upper point associated with

the 130W TDP Intel Xeon Processor E7-8800/4800/2800 Product Families processor

Thermal Profile (x = TDP and y = T_{CASE_MAX}P @ TDP) represents a thermal solution

design point. In actuality the processor case temperature may not reach this value due

to TCC activation (see Figure 6-1 for the Performance Intel Xeon Processor E7-8800/

4800/2800 Product Families processor). The lower point of the thermal profile consists

of x = P_{_PROFILE_MIN}and y = T_{CASE_MAX}@ P_{_PROFILE_MIN}. P_{_PROFILE_MIN}is defined as the

processor power at which T_CASE, calculated from the thermal profile, is equal to 69°C.

Analysis indicates that real applications are unlikely to cause the processor to consume

maximum power dissipation for sustained time periods. Intel recommends that

complete thermal solution designs target the Thermal Design Power (TDP) instead of

the maximum processor power consumption. The Intel® Thermal Monitor feature is

intended to help protect the processor in the event that an application exceeds the TDP

recommendation for a sustained time period. For more details on this feature, refer to

Section 6.2. To ensure maximum flexibility for future requirements, systems should be

designed to the Flexible Motherboard (FMB) guidelines, even if a processor with lower

power dissipation is currently planned. The Intel Thermal Monitor 1 or Intel Thermal

Monitor 2 feature must be enabled for the processor to remain within its specifications.

Table 6-1.

Processor Thermal Specifications

Thermal

Design Power

(W)

Core

Frequency

Minimum

TCASE (°C)

Maximum

TCASE (°C)

Notes

Processor Launch to FMB

130

105

95

5

See Figure 6-1; Table 6-2; 1, 2, 3, 4, 5

See Figure 6-2; Table 6-3; 1, 2, 3, 4, 5

See Figure 6-3; Table 6-4; 1, 2, 3, 4, 5

Notes:

1.

These values are specified at V

for all processor frequencies. Systems must be designed to ensure

CC_MAX

the processor is not to be subjected to any static V and I combination wherein V exceeds V at

specified I

CC

CC_MAX

.

CC

2.

3.

4.

5.

Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the

maximum power that the processor can dissipate. TDP is measured at maximum T

.

CASE

These specifications are based on pre-silicon estimates and simulations. These specifications may be

updated with characterized data from silicon measurements in a future release of this document.

Power specifications are defined at all VIDs found in Table 2-2. The Intel Xeon Processor E7-8800/4800/

2800 Product Families processor may be shipped under multiple VIDs for each frequency.

FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor

frequency requirements.

112

Datasheet Volume 1 of 2

Thermal Specifications

Figure 6-1. 130W TDP Processor Thermal Profile

TBD

Notes:

1.

Thermal Profile is representative of a volumetrically unconstrained platform. Refer to Table 6-2 for discrete

points that constitute the thermal profile.

2.

Implementation of the Thermal Profile should result in virtually no TCC activation. Furthermore, utilization

of thermal solutions that do not meet processor Thermal Profile will result in increased probability of TCC

activation and may incur measurable performance loss. (See Section 6.2 for details on TCC activation.)

Refer to the Intel® Xeon® Processor 7500 Series and Intel® Xeon® Processor E7-8800/4800/2800

Product Families Thermal and Mechanical Design Guide for system and environmental implementation

details.

3.

Table 6-2.

130W TDP Processor Thermal Profile Table (Sheet 1 of 2)

Power (W)

T

(°C)

CASE_MAX

48.0

48.8

49.6

50.4

51.2

52.0

52.8

53.6

54.4

55.2

56.0

56.8

57.6

58.4

0

5

10

15

20

25

30

35

40

45

50

55

60

65

Datasheet Volume 1 of 2

113

Thermal Specifications

Table 6-2.

130W TDP Processor Thermal Profile Table (Sheet 2 of 2)

Power (W)

T

(°C)

CASE_MAX

59.1

59.9

60.7

61.5

62.3

63.1

63.9

64.7

65.5

66.3

67.1

67.9

69.0

70

75

80

85

90

95

100

105

110

115

120

125

130

Figure 6-2. 105W TDP Processor Thermal Profile

70.0

65.0

TCASE_MAX is a thermal solution design point

TBD

60.0

55.0

50.0

45.0

40.0

Y = .179x + 45.2

Power [W]

Notes:

1.

Thermal Profile is representative of a volumetrically constrained platform. Refer to Table 6-3 for discrete

points that constitute the thermal profile.

2.

Implementation of the Thermal Profile should result in virtually no TCC activation. Furthermore, utilization

of thermal solutions that do not meet processor Thermal Profile will result in increased probability of TCC

activation and may incur measurable performance loss. (See Section 6.2 for details on TCC activation.)

Refer to the Intel® Xeon® Processor 7500 Series and Intel® Xeon® Processor E7-8800/4800/2800

Product Families Thermal and Mechanical Design Guide for system and environmental implementation

details.

3.

114

Datasheet Volume 1 of 2

Thermal Specifications

Table 6-3.

105W TDP Processor Thermal Profile Table

Power (W)

T

(°C)

CASE_MAX

45.2

46.1

47.0

47.9

48.8

49.7

50.6

51.5

52.4

53.3

54.1

55.0

55.9

56.8

57.7

58.6

59.5

60.4

61.3

62.2

63.1

64.0

0

5

10

15

20

25

30

35

40

45

50

55

60

65

70

75

80

85

90

95

100

105

Datasheet Volume 1 of 2

115

Thermal Specifications

Figure 6-3. 95W TDP Processor Thermal Profile

TBD

Notes:

1.

Thermal profile is representative of a volumetrically constrained platform. Refer to Table 6-4 for discrete

points that constitute the thermal profile.

2.

Implementation of the Thermal Profile should result in virtually no TCC activation. Furthermore, utilization

of thermal solutions that do not meet processor Thermal Profile will result in increased probability of TCC

activation and may incur measurable performance loss. (See Section 6.2 for details on TCC activation.)

Refer to the Intel® Xeon® Processor 7500 Series and Intel® Xeon® Processor E7-8800/4800/2800

Product Families Thermal and Mechanical Design Guide for system and environmental implementation

details.

3.

Table 6-4.

95W TDP Processor Thermal Profile Table (Sheet 1 of 2)

Power (W)

T

(°C)

CASE_MAX

48.2

49.3

50.5

51.6

52.8

53.9

55.1

56.2

57.4

58.5

59.7

60.8

62.0

63.1

64.3

0

5

10

15

20

25

30

35

40

45

50

55

60

65

70

116

Datasheet Volume 1 of 2

Thermal Specifications

Table 6-4.

95W TDP Processor Thermal Profile Table (Sheet 2 of 2)

Power (W)

T

(°C)

CASE_MAX

75

80

85

90

95

65.4

66.6

67.7

68.9

70.0

6.1.2

Thermal Metrology

The minimum and maximum case temperatures (T_CASE) are specified in Table 6-2

through Table 6-4, and are measured at the geometric top center of the processor

substrate, not IHS, as in previous products. Figure 6-4 illustrates the location where

T_CASEtemperature measurements should be made. For detailed guidelines on

temperature measurement methodology, refer to the Intel® Xeon® Processor 7500

Series and Intel® Xeon® Processor E7-8800/4800/2800 Product Families Thermal and

Mechanical Design Guide.

Figure 6-4. Case Temperature (T_CASE) Measurement Location

TBD

Note: Figure is not to scale and is for reference only.

Datasheet Volume 1 of 2

117

Thermal Specifications

6.2

Processor Thermal Features

6.2.1

Thermal Monitor Features

The Intel Xeon Processor E7-8800/4800/2800 Product Families processor provides two

thermal monitor features, Intel Thermal Monitor 1 (“TM1”) and Intel Thermal Monitor 2

(“TM2”). Both Intel Thermal Monitor 1 and 2 must be enabled in BIOS for the processor

to be operating within specifications. When both are enabled, Intel Thermal Monitor 2

will be activated first and Intel Thermal Monitor 1 will be added if Intel Thermal Monitor

2 is not effective.

®

6.2.2

Intel Thermal Monitor 1

The Intel Thermal Monitor 1 feature helps control the processor temperature by

activating the Thermal Control Circuit (TCC) when the processor silicon reaches its

maximum operating temperature. The TCC reduces processor power consumption as

needed by modulating (starting and stopping) the internal processor core clocks. Intel

Thermal Monitor 1 or Intel Thermal Monitor 2 must be enabled for the processor to be

operating within specifications. The temperature at which Intel Thermal Monitor 1

activates the thermal control circuit is not user-configurable and is not software-visible.

Bus traffic is snooped in the normal manner, and interrupt requests are latched (and

serviced during the time that the clocks are on) while the TCC is active.

When Intel Thermal Monitor 1 is enabled, and a high temperature situation exists (that

is, TCC is active), the clocks will be modulated by alternately turning the clocks off and

on at a duty cycle specific to the processor (typically 30 - 50%). Cycle times are

processor speed dependent and will decrease as processor core frequencies increase. A

small amount of hysteresis has been included to prevent rapid active/inactive

transitions of the TCC when the processor temperature is near its maximum operating

temperature. Once the temperature has dropped below the maximum operating

temperature, and the hysteresis timer has expired, the TCC goes inactive and clock

modulation ceases.

With a thermal solution designed to meet the Intel Xeon Processor E7-8800/4800/2800

Product Families processor Thermal Profiles, it is anticipated that the TCC would only be

activated for very short periods of time when running the most power-intensive

applications. The processor performance impact due to these brief periods of TCC

activation is expected to be so minor that it would be immeasurable. In addition, a

thermal solution that is significantly under designed may not be capable of cooling the

processor even when the TCC is active continuously.

The duty cycle for the TCC, when activated by the Intel Thermal Monitor 1, is factory-

configured and cannot be modified. Intel Thermal Monitor 1 does not require any

additional hardware, software drivers, or interrupt handling routines.

6.2.3

Intel Thermal Monitor 2

The Intel Xeon Processor E7-8800/4800/2800 Product Families processor adds

supports for an enhanced thermal monitor capability known as Intel Thermal Monitor 2.

This mechanism provides an efficient means for limiting the processor temperature by

reducing the power consumption within the processor. Intel Thermal Monitor 1 or Intel

Thermal Monitor 2 must be enabled for the processor to be operating within

specifications. Intel Thermal Monitor 2 requires support for dynamic VID transitions in

the platform.

118

Datasheet Volume 1 of 2

Thermal Specifications

When Intel Thermal Monitor 2 is enabled, and a high temperature situation is detected,

the Thermal Control Circuit (TCC) will be activated for all processor cores. The TCC

causes the processor to adjust its operating frequency (via the bus multiplier) and

input voltage (via the VID signals). This combination of reduced frequency and VID

results in a reduction to the processor power consumption. The lowest bus multiplier

for the Intel Thermal Monitor 2 is 8:1. This results in an operating frequency of

1066 MHz.

Once the new operating frequency is engaged, the processor will transition to the new

core operating voltage by issuing a new VID code to the voltage regulator. The voltage

regulator must support dynamic VID steps in order to support the Intel Thermal

Monitor 2. During the voltage change, it will be necessary to transition through multiple

VID codes to reach the target operating voltage. Each step will be one or two VID table

entries (see Table 2-2). The processor continues to execute instructions during the

voltage transition. Operation at the lower voltage reduces the power consumption of

the processor.

A small amount of hysteresis has been included to prevent rapid active/inactive

transitions of the TCC when the processor temperature is near its maximum operating

temperature. Once the temperature has dropped below the maximum operating

temperature, and the hysteresis timer has expired, the operating frequency and

voltage transition back to the normal system operating point. Transition of the VID code

will occur first, in order to ensure proper operation once the processor reaches its

normal operating frequency. Refer to Figure 6-5 for an illustration of this ordering.

Figure 6-5. Intel® Thermal Monitor 2 Frequency and Voltage Ordering

T_TM2

Temperature

f_MAX

f_TM2

Frequency

V_NOM

V_TM2

Vcc

Time

T(hysterisis)

The PROCHOT_N signal is asserted when a high-temperature situation is detected,

regardless of whether Intel Thermal Monitor 1 or Intel Thermal Monitor 2 is enabled.

6.2.4

On-Demand Mode

The processor provides an auxiliary mechanism that allows system software to force

the processor to reduce its power consumption. This mechanism is referred to as

“On-Demand” mode and is distinct from the Intel Thermal Monitor 1 and Intel Thermal

Monitor 2 features. On-Demand mode is intended as a means to reduce system level

power consumption. Systems utilizing Intel Xeon Processor E7-8800/4800/2800

Product Families processor must not rely on software usage of this mechanism to limit

the processor temperature. There are two ways to implement On-Demand mode. If bit

Datasheet Volume 1 of 2

119

Thermal Specifications

4 of the IA32_CLOCK_MODULATION MSR is set to a ‘1’, the processor will immediately

reduce its power consumption via modulation (starting and stopping) of the internal

core clock, independent of the processor temperature. Also, a write the P_CNT I/O

address, the processor will immediately reduce power consumptions as well.

The P_CNT I/O address write controls all active cores. The MSR write only impacts the

core that performed the MSR write. The P_CNT I/O address write takes priority over the

MSR write.

When using On-Demand mode, the duty cycle of the clock modulation is programmable

via bits 3:1 of the same IA32_CLOCK_MODULATION MSR. In On-Demand mode, the

duty cycle can be programmed from 12.5% on/ 87.5% off to 87.5% on/12.5% off in

12.5% increments. On-Demand mode may be used in conjunction with the Thermal

Monitor; however, if the system tries to enable On-Demand mode at the same time the

TCC is engaged, the factory configured duty cycle of the TCC will override the duty

cycle selected by the On-Demand mode.

6.2.5

PROCHOT_N Signal

An external signal, PROCHOT_N (processor hot) is asserted when the temperature of

any processor core has reached its factory configured trip point. If Intel Thermal

Monitor 1 and Intel Thermal Monitor 2 are enabled (note that Intel Thermal Monitor 1

and Intel Thermal Monitor 2 must be enabled for the processor to be operating within

specification), the TCC will be active when PROCHOT_N is asserted. Intel Thermal

Monitor 2 activates first, and Intel Thermal Monitor 1 activates only if needed to further

reduce temperature. The processor can be configured to generate an interrupt upon

the assertion or de-assertion of PROCHOT_N. Refer to the Intel^®64 and IA-32

Architectures Software Developer’s Manual and the Intel® Xeon® Processor 7500

Series Datasheet Volume 2 for specific register and programming details.

PROCHOT_N is designed to assert at or a few degrees higher than maximum T_CASE(as

specified by Thermal Profile) when dissipating TDP power, and cannot be interpreted as

an indication of processor case temperature. This temperature delta accounts for

processor package, lifetime and manufacturing variations and attempts to ensure the

Thermal Control Circuit is not activated below maximum T_CASEwhen dissipating TDP

power. There is no defined or fixed correlation between the PROCHOT_N trip

temperature, or the case temperature. Thermal solutions must be designed to the

processor specifications and cannot be adjusted based on experimental measurements

of T_CASE, or PROCHOT_N.

This signal is only valid when power good is asserted, and CPU reset is not asserted.

6.2.6

FORCE_PR_N Signal

The FORCE_PR_N (force power reduction) input can be used by the platform to cause

Intel Xeon Processor E7-8800/4800/2800 Product Families processor to activate the

TCC. If the Thermal Monitor is enabled, the TCC will be activated upon the assertion of

the FORCE_PR_N signal. FORCE_PR_N is an asynchronous input. Assertion of the

FORCE_PR_N signal will activate TCC for all operating processor cores. The TCC will

remain active until the system deasserts FORCE_PR_N. FORCE_PR_N can be used to

thermally protect other system components. To use the VR as an example, when

FORCE_PR_N is asserted, the TCC circuit in the processor will activate, reducing the

current consumption of the processor and the corresponding temperature of the VR.

120

Datasheet Volume 1 of 2

Thermal Specifications

It should be noted that assertion of FORCE_PR_N does not automatically assert

PROCHOT_N. As mentioned previously, the PROCHOT_N signal is asserted when a high

temperature situation is detected. A minimum pulse width of 500 µs is recommended

when FORCE_PR_N is asserted by the system. Sustained activation of the FORCE_PR_N

signal may cause noticeable platform performance degradation.

6.2.7

THERMTRIP_N Signal

Regardless of whether or not the Intel Thermal Monitor 1 or 2 is enabled, in the event

of a catastrophic cooling failure, the processor will automatically shut down when any

core has reached an elevated temperature (refer to the THERMTRIP_N definition in

Table 5-1). At this point, the sideband signal THERMTRIP_N will go active and stay

active as described in Table 5-1. THERMTRIP_N activation is independent of processor

activity. If THERMTRIP_N is asserted, processor core voltage (V_CC) and processor cache

voltage (Vcache) must be removed within the time frame defined.

This signal is only valid when power good is asserted, and CPU reset is not asserted.

6.2.8

THERMALERT_N Signal

The THERMALERT_N pin activates when a pre-programmed temperature is reached on

any of the device cores. This pre-programmed temperature is an offset from Prochot,

an programmed via BIOS. There is no sign for the value, as it is always assumed that

the values is less than or equal to Prochot. When not programmed, the value is zero.

The expected usage for this signal is in fan speed control when direct PECI readings are

not used. Note that all thermal specifications must be met when using this signal as

part of an over all thermal solution.

This signal is only valid when power good is asserted, CPU reset is not asserted, and

BIOS has configured the THERMALERT threshold temperature. Note that BIOS can not

configure the THERMALERT threshold until the processor is out of reset.

6.3

Platform Environment Control Interface (PECI)

The Platform Environment Control Interface (PECI) uses a single wire for self-clocking

and data transfer. The bus requires no additional control lines. The physical layer is a

self-clocked one-wire bus that begins each bit with a driven, rising edge from an idle

level near zero volts. The duration of the signal driven high depends on whether the bit

value is a logic ‘0’ or logic ‘1’. PECI also includes variable data transfer rate established

with every message. In this way, it is highly flexible even though underlying logic is

simple.

The interface design was optimized for interfacing to Intel® processor and chipset

components in both single processor and multiple processor environments. The single

wire interface provides low board routing overhead for the multiple load connections in

the congested routing area near the processor and chipset components. Bus speed,

error checking, and low protocol overhead provides adequate link bandwidth and

reliability to transfer critical device operating conditions and configuration information.

The PECI bus offers:

• A wide speed range from 2 Kbps to 2 Mbps

• CRC check byte used to efficiently and atomically confirm accurate data delivery

• Synchronization at the beginning of every message minimizes device timing

accuracy requirements

Datasheet Volume 1 of 2

121

Thermal Specifications

What follows is a processor-specific PECI client definition, and is largely an addendum

to the PECI Network Layer and Design Recommendations sections for the PECI 2.0

Specification document.

Note:

Note that the PECI commands described in this document apply to the Intel Xeon

Processor E7-8800/4800/2800 Product Families processor only. Refer to Table 6-5 for a

list of PECI commands supported by the Intel Xeon Processor E7-8800/4800/2800

Product Families processor PECI client.

Table 6-5.

Summary of Processor-specific PECI Commands

Supported on

Command

Intel Xeon Processor E7-8800/4800/2800 Product Families

processor CPU

Ping()

Yes

GetDIB()

GetTemp()

PCIConfigRd()

PCIConfigWr()

1

MbxSend()

1

MbxGet()

Note:

1.

Refer to Table 6-9 for a summary of mailbox commands supported by the Intel Xeon Processor E7-8800/

4800/2800 Product Families processor CPU.

6.3.1

PECI Client Capabilities

The Intel Xeon Processor E7-8800/4800/2800 Product Families processor PECI client is

designed to support the following sideband functions:

• Processor and DRAM thermal management

• Platform manageability functions, including thermal, power and electrical error

monitoring

• Processor interface tuning and diagnostics capabilities (Intel^®Interconnect BIST

[Intel^®IBIST]).

6.3.1.1

Thermal Management

Processor fan speed control is managed by comparing PECI thermal readings against

the processor-specific fan speed control reference point, or T_CONTROL. Both T_CONTROL

and PECI thermal readings are accessible via the processor PECI client. These variables

are referenced to a common temperature, the TCC activation point, and are both

defined as negative offsets from that reference. Algorithms for fan speed management

using PECI thermal readings and the T_CONTROLreference are documented in

Section 6.3.2.6.

PECI-based access to DRAM thermal readings and throttling control coefficients provide

a means for Board Management Controllers (BMCs) or other platform management

devices to feed hints into on-die memory controller throttling algorithms. These control

coefficients are accessible using PCI configuration space writes via PECI. The PECI-

based configuration write functionality is defined in Section 6.3.2.5.

122

Datasheet Volume 1 of 2

Thermal Specifications

6.3.1.2

6.3.1.3

Platform Manageability

PECI allows full read access to error and status monitoring registers within the

processor’s PCI configuration space. It also provides insight into thermal monitoring

functions such as TCC activation timers and thermal error logs.

Processor Interface Tuning and Diagnostics

The Intel Xeon Processor E7-8800/4800/2800 Product Families processor Intel IBIST

allows for in-field diagnostic capabilities in Intel QPI and memory controller interfaces.

PECI provides a port to execute these diagnostics via its PCI Configuration read and

write capabilities.

6.3.2

Client Command Suite

6.3.2.1

Ping()

Ping() is a required message for all PECI devices. This message is used to enumerate

devices or determine if a device has been removed, been powered-off, etc. A Ping()

sent to a device address always returns a non-zero Write FCS if the device at the

targeted address is able to respond.

6.3.2.1.1

Command Format

The Ping() format is as follows:

Write Length: 0

Read Length: 0

Figure 6-6. Ping()

Byte #

0

1

2

3

Write Length

0x00

Read Length

0x00

Client Address

FCS

Byte

Definition

An example Ping() command to PECI device address 0x30 is shown below.

Figure 6-7. Ping() Example

Byte #

0

1

2

3

Byte

0x30

0x00

0xe1

Definition

6.3.2.2

GetDIB()

The processor PECI client implementation of GetDIB() includes an 8-byte response and

provides information regarding client revision number and the number of supported

domains. All processor PECI clients support the GetDIB() command.

Datasheet Volume 1 of 2

123

Thermal Specifications

6.3.2.2.1

Command Format

The GetDIB() format is as follows:

Write Length: 1

Read Length: 8

Command: 0xf7

Figure 6-8. GetDIB()

Byte #

0

1

2

3

4

Write Length

0x01

Read Length

0x08

Cmd Code

0xf7

Client Address

FCS

Byte

Definition

5

6

7

8

9

Revision

Number

Device Info

Reserved

10

11

12

13

Reserved

FCS

6.3.2.2.2

Device Info

The Device Info byte gives details regarding the PECI client configuration. At a

minimum, all clients supporting GetDIB will return the number of domains inside the

package via this field. With any client, at least one domain (Domain 0) must exist.

Therefore, the Number of Domains reported is defined as the number of domains in

addition to Domain 0. For example, if the number 0b1 is returned, that would indicate

that the PECI client supports two domains.

Figure 6-9. Device Info Field Definition

7 6 5 4 3 2 1 0

Reserved

# of Domains

Reserved

6.3.2.2.3

Revision Number

All clients that support the GetDIB command also support Revision Number reporting.

The revision number may be used by a host or originator to manage different command

suites or response codes from the client. Revision Number is always reported in the

second byte of the GetDIB() response. The Revision Number always maps to the

revision number of this document.

124

Datasheet Volume 1 of 2

Thermal Specifications

Figure 6-10. Revision Number Definition

7

4

0

3

Major Revision#

Minor Revision#

6.3.2.3

GetTemp()

The GetTemp() command is used to retrieve the temperature from a target PECI

address. The temperature is used by the external thermal management system to

regulate the temperature on the die. The data is returned as a negative value

representing the number of degrees centigrade below the Thermal Control Circuit

Activation temperature of the PECI device. Note that a value of zero represents the

temperature at which the Thermal Control Circuit activates. The actual value that the

thermal management system uses as a control set point (Tcontrol) is also defined as a

negative number below the Thermal Control Circuit Activation temperature. TCONTROL

may be extracted from the processor by issuing a PECI Mailbox MbxGet() (see

Section 6.3.2.8), or using a RDMSR instruction.

Refer to Section 6.3.6 for details regarding temperature data formatting.

6.3.2.3.1

Command Format

The GetTemp() format is as follows:

Write Length: 1

Read Length: 2

Command: 0x01

Multi-Domain Support: Yes (see Table 6-15)

Description: Returns the current temperature for addressed processor PECI client.

Figure 6-11. GetTemp()

Byte #

0

1

2

3

Write Length

0x01

Read Length

0x02

Cmd Code

0x01

Client Address

Byte

Definition

4

5

6

7

FCS

Temp[7:0]

Temp[15:8]

FCS

Datasheet Volume 1 of 2

125

Thermal Specifications

Example bus transaction for a thermal sensor device located at address 0x30 returning

a value of negative 10°C:

Figure 6-12. GetTemp() Example

Byte #

0

1

2

3

Byte

0x30

0x01

0x02

0x01

Definition

4

5

6

7

0xef

0x80

0xfd

0x4b

6.3.2.3.2

Supported Responses

The typical client response is a passing FCS and good thermal data. Under some

conditions, the client’s response will indicate a failure.

Table 6-6.

GetTemp() Response Definition

Response

Meaning

General Sensor Error (GSE)

0x0000

Thermal scan did not complete in time. Retry is appropriate.

Processor is running at its maximum temperature or is currently being

reset.

All other data

Valid temperature reading, reported as a negative offset from the TCC

activation temperature.

6.3.2.4

PCIConfigRd()

The PCIConfigRd() command gives sideband read access to the entire PCI configuration

space maintained in the processor. This capability does not include support for route-

through to downstream devices or sibling processors. The exact listing of supported

devices, functions, and registers can be found in the Intel® Xeon® Processor 7500

Series Datasheet Volume 2. PECI originators may conduct a device/function/register

enumeration sweep of this space by issuing reads in the same manner that BIOS

would. A response of all 1’s indicates that the device/function/register is

unimplemented.

PCI configuration addresses are constructed as shown in the following diagram. Under

normal in-band procedures, the Bus number (including any reserved bits) would be

used to direct a read or write to the proper device. Since there is a one-to-one mapping

between any given client address and the bus number, any request made with a bad

Bus number is ignored and the client will respond with a ‘pass’ completion code but all

0’s in the data. The only legal bus number is 0x00. The client will return all 1’s in the

data response and ‘pass’ for the completion code for all of the following conditions:

• Unimplemented Device

• Unimplemented Function

• Unimplemented Register

Figure 6-13. PCI Configuration Address

31

28 27

20 19

15 14

12 11

0

Reserved

Bus

Device

Function

Register

126

Datasheet Volume 1 of 2

Thermal Specifications

PCI configuration reads may be issued in byte, word, or dword granularities.

6.3.2.4.1

Command Format

The PCIConfigRd() format is as follows:

Write Length: 5

Read Length: 2 (byte data), 3 (word data), 5 (dword data)

Command: 0xc1

Multi-Domain Support: Yes (see Table 6-15)

Description: Returns the data maintained in the PCI configuration space at the PCI

configuration address sent. The Read Length dictates the desired data return size. This

command supports byte, word, and dword responses as well as a completion code. All

command responses are prepended with a completion code that includes additional

pass/fail status information. Refer to Section 6.3.4.2 for details regarding completion

codes.

Figure 6-14. PCIConfigRd()

Byte #

0

1

2

3

Write Length

0x05

Read Length

{0x02,0x03,0x05}

Cmd Code

0xc1

Client Address

Byte

Definition

4

5

6

7

8

LSB

PCI Configuration Address

MSB

FCS

9

10

8+RL

9+RL

FCS

Completion

Code

Data 0

...

Data N

Note that the 4-byte PCI configuration address defined above is sent in standard PECI

ordering with LSB first and MSB last.

6.3.2.4.2

Supported Responses

The typical client response is a passing FCS, a passing Completion Code (CC) and valid

Data. Under some conditions, the client’s response will indicate a failure.

Table 6-7.

PCIConfigRd() Response Definition

Response

Meaning

Abort FCS

CC: 0x40

CC: 0x80

Illegal command formatting (mismatched RL/WL/Command Code)

Command passed, data is valid

Error causing a response timeout. Either due to a rare, internal timing condition or a

processor RESET or processor S1 state. Retry is appropriate outside of the RESET or

S1 states.

Datasheet Volume 1 of 2

127

Thermal Specifications

6.3.2.5

PCIConfigWr()

The PCIConfigWr() command gives sideband write access to the PCI configuration

space maintained in the processor. The exact listing of supported devices, functions is

defined in the Intel® Xeon® Processor 7500 Series Datasheet Volume 2. PECI

originators may conduct a device/function/register enumeration sweep of this space by

issuing reads in the same manner that BIOS would.

PCI configuration addresses are constructed as shown in Figure 6-13, and this

command is subject to the same address configuration rules as defined in

Section 6.3.2.4. PCI configuration reads may be issued in byte, word, or dword

granularities.

Because a PCIConfigWr() results in an update to potentially critical registers inside the

processor, it includes an Assured Write FCS (AW FCS) byte as part of the write data

payload. In the event that the AW FCS mismatches with the client-calculated FCS, the

client will abort the write and will always respond with a bad Write FCS.

6.3.2.5.1

Command Format

The PCIConfigWr() format is as follows:

Write Length: 7 (byte), 8 (word), 10 (dword)

Read Length: 1

Command: 0xc5

Multi-Domain Support: Yes (see Table 6-15)

Description: Writes the data sent to the requested register address. Write Length

dictates the desired write granularity. The command always returns a completion code

indicating the pass/fail status information. Write commands issued to illegal Bus

Numbers, or unimplemented Device / Function / Register addresses are ignored but

return a passing completion code. Refer to Section 6.3.4.2 for details regarding

completion codes.

Figure 6-15. PCIConfigWr()

Byte #

0

1

2

3

Write Length

{0x07,0x08,0x10}

Read Length

0x01

Cmd Code

0xc5

Client Address

Byte

Definition

4

5

6

7

LSB

PCI Configuration Address

Data (1, 2 or 4 bytes)

MSB

8

WL-1

MSB

LSB

WL

WL+1

FCS

WL+2

WL+3

FCS

Completion

Code

AW FCS

128

Datasheet Volume 1 of 2

Thermal Specifications

Note that the 4-byte PCI configuration address and data defined above are sent in

standard PECI ordering with LSB first and MSB last.

6.3.2.5.2

Supported Responses

The typical client response is a passing FCS, a passing Completion Code and valid Data.

Under some conditions, the client’s response will indicate a failure.

Table 6-8.

PCIConfigWr() Response Definition

Response

Bad FCS

Meaning

Electrical error or AW FCS failure

Abort FCS

CC: 0x40

CC: 0x80

Illegal command formatting (mismatched RL/WL/Command Code)

Command passed, data is valid

Error causing a response timeout. Either due to a rare, internal timing condition or a

processor RESET condition or processor S1 state. Retry is appropriate outside of the RESET

or S1 states.

6.3.2.6

Mailbox

The PECI mailbox (“Mbx”) is a generic interface to access a wide variety of internal

processor states. A Mailbox request consists of sending a 1-byte request type and

4-byte data to the processor, followed by a 4-byte read of the response data. The

following sections describe the Mailbox capabilities as well as the usage semantics for

the MbxSend and MbxGet commands which are used to send and receive data.

6.3.2.6.1

Capabilities

Table 6-9.

Mailbox Command Summary (Sheet 1 of 2)

Request

MbxSend

Data

(dword)

MbxGet

Data

(dword)

Command

Name

Type

Code

(byte)

Description

Ping

0x00

0x01

0x00

Verify the operability / existence of the Mailbox.

Thermal

Status

Read/Clear

Log bit clear Thermal

mask

Read the thermal status register and optionally clear any log bits.

The thermal status has status and log bits indicating the state of

processor TCC activation, external FORCEPR_N assertion, and

Critical Temperature threshold crossings.

Status

Register

Counter

0x03

0x00

Snapshots all PECI-based counters

Snapshot

Counter Clear

Counter Read

0x04

0x05

0x00

Concurrently clear and restart all counters.

Counter

Number

Counter Data

Returns the counter number requested.

0: Total reference time

1: Total TCC Activation time counter

Icc-TDC Read

0x06

0x07

0x00

Icc-TDC

Returns the specified Icc-TDC of this part, in Amps.

Reads the thermal averaging constant.

Thermal Config

Data Read

Thermal

config data

Thermal Config

Data Write

0x08

0x09

0xB

Thermal

Config Data

0x00

Writes the thermal averaging constant.

Tcontrol Read

0x00

Tcontrol

Reads the fan speed control reference temperature, Tcontrol, in

PECI temperature format.

T-state

Throttling

Control Read

ACPI T-state

Control Word

Reads the PECI ACPI T-state throttling control word.

Datasheet Volume 1 of 2

129

Thermal Specifications

Table 6-9.

Mailbox Command Summary (Sheet 2 of 2)

Request

Type

Code

MbxSend

Data

(dword)

MbxGet

Data

(dword)

Command

Name

Description

(byte)

T-state

Throttling

Control Write

0xC

ACPI T-

state

Control

Word

0x00

Writes the PECI ACPI T-state throttling control word.

Average

Temperature

Read

0x21

0x00

Average

Temperature

Value

Intel Xeon Processor E7-8800/4800/2800 Product Families

processor only: Reads the average temperature of all cores in

PECI temperature format.

Get Uncore

0x22

0x23

0x24

0x00

Get _Uncore_

Temp

Reads the uncore temperature in PECI format.

Temperature

Write P-state

limit

WRITE_P_STA Sets an upper limit for P-state frequency ratio.

TE_LIMIT

Read P-state

limit

READ_P_STAT Reads the programmed P-state limit if set.

E_LIMIT

Any MbxSend request with a request type not defined in Table 6-9 will result in a failing

completion code.

More detailed command definitions follow.

6.3.2.6.2

6.3.2.6.3

Ping

The Mailbox interface may be checked by issuing a Mailbox ‘Ping’ command. If the

command returns a passing completion code, it is functional. Under normal operating

conditions, the Mailbox Ping command should always pass.

Thermal Status Read / Clear

The Thermal Status Read provides information on package level thermal status. Data

includes:

• The status of TCC activation / PROCHOT_N output

• FORCEPR_N input

• Critical Temperature

These status bits are a subset of the bits defined in the IA32_THERM_STATUS MSR on

the processor, and more details on the meaning of these bits may be found in the

Intel 64 and IA-32 Architectures Software Developer’s Manual, Vol. 3B.

Both status and sticky log bits are managed in this status word. All sticky log bits are

set upon a rising edge of the associated status bit, and the log bits are cleared only by

Thermal Status reads or a processor reset. A read of the Thermal Status Word always

includes a log bit clear mask that allows the host to clear any or all log bits that it is

interested in tracking.

A bit set to 0b0 in the log bit clear mask will result in clearing the associated log bit. If

a mask bit is set to 0b0 and that bit is not a legal mask, a failing completion code will

be returned. A bit set to 0b1 is ignored and results in no change to any sticky log bits.

For example, to clear the TCC Activation Log bit and retain all other log bits, the

Thermal Status Read should send a mask of 0xFFFFFFFD.

130

Datasheet Volume 1 of 2

Thermal Specifications

Figure 6-16. Thermal Status Word

6.3.2.6.4

Counter Snapshot / Read / Clear

A reference time and ‘Thermally Constrained’ time are managed in the processor. These

two counters are managed via the Mailbox. These counters are valuable for detecting

thermal runaway conditions where the TCC activation duty cycle reaches excessive

levels.

The counters may be simultaneously snapshot, simultaneously cleared, or

independently read. The simultaneous snapshot capability is provided in order to

guarantee concurrent reads even with significant read latency over the PECI bus. Each

counter is 32-bits wide.

Table 6-10. Counter Definition

Counter

Number

Counter Name

Definition

Total Time

0x00

0x01

Counts the total time the processor has been executing with a

resolution of approximately 1ms. This counter wraps at 32 bits.

Thermally Constrained Time

Counts the total time the processor has been operating at a

lowered performance due to TCC activation. This timer includes

the time required to ramp back up to the original P-state target

after TCC activation expires. This timer does not include TCC

activation time as a result of an external assertion of

FORCEPR_N.

6.3.2.6.5

6.3.2.6.6

Icc-TDC Read

Icc-TDC is the Intel Xeon Processor E7-8800/4800/2800 Product Families processor

TDC current draw specification. This data may be used to confirm matching Icc profiles

of processors in MP configurations. It may also be used during the processor boot

sequence to verify processor compatibility with motherboard Icc delivery capabilities.

This command returns Icc-TDC in units of 1 Amp.

Thermal Data Config Read / Write

The Thermal Data Configuration register allows the PECI host to control the window

over which thermal data is filtered. The default window is 256 ms. The host may

configure this window by writing a Thermal Filtering Constant as a power of two.

E.g., sending a value of 9 results in a filtering window of 2⁹or 512 ms.

Datasheet Volume 1 of 2

131

Thermal Specifications

Figure 6-17. Thermal Data Configuration Register

3

1

4

3

0

Reserved

Thermal Filter Const

6.3.2.6.7

6.3.2.6.8

TCONTROL Read

TCONTROL is used for fan speed control management. The TCONTROL limit may be

read over PECI using this Mailbox function. Unlike the in-band MSR interface, this

TCONTROL value is already adjusted to be in the native PECI temperature format of a

2-byte, 2’s complement number.

T-state Throttling Control Read / Write

PECI offers the ability to enable and configure ACPI T-state (core clock modulation)

throttling. ACPI T-state throttling forces all CPU cores into duty cycle clock modulation

where the core toggles between C0 (clocks on) and C1 (clocks off) states at the

specified duty cycle. This throttling reduces CPU performance to the duty cycle

specified and, more importantly, results in processor power reduction.

The Intel Xeon Processor E7-8800/4800/2800 Product Families processor supports

software initiated T-state throttling and automatic T-state throttling as part of the

internal Thermal Monitor response mechanism (upon TCC activation). The PECI T-state

throttling control register read/write capability is managed only in the PECI domain. In-

band software may not manipulate or read the PECI T-state control setting. In the

event that multiple agents are requesting T-state throttling simultaneously, the CPU

always gives priority to the lowest power setting, or the numerically lowest duty cycle.

On Intel Xeon Processor E7-8800/4800/2800 Product Families processors, the only

supported duty cycle is 12.5% (12.5% clocks on, 87.5% clocks off). It is expected that

T-state throttling will be engaged only under emergency thermal or power conditions.

Future products may support more duty cycles, as defined in the following table:

Table 6-11. ACPI T-state Duty Cycle Definition

Duty Cycle Code

Definition

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

Undefined

12.5% clocks on / 87.5% clocks off

25% clocks on / 75% clocks off

37.5% clocks on / 62.5% clocks off

50% clocks on / 50% clocks off

62.5% clocks on / 37.5% clocks off

75% clocks on / 25% clocks off

87.5% clocks on / 12.5% clocks off

132

Datasheet Volume 1 of 2

Thermal Specifications

The T-state control word is defined as follows:

Figure 6-18. ACPI T-state Throttling Control Read / Write Definition

Byte #

0

1

2

3

4

Request Type

Request Data

7

5

4

3

1 0

7

0

0xB / 0xC

Reserved

Data

Enable

Duty Cycle

6.3.2.6.9

Average Temperature Read

The Average Temperature Read mailbox command implemented by Intel® Xeon®

processor 7500 series provides an alternative temperature assessment to that provided

by the GetTemp() PECI command. Where GetTemp() returns the average of the hottest

sense points on the processor, the Average Temp Read returns the average of all core

temperature sense points. The values from each sensor are averaged and filtered. The

data is returned as a negative value representing the number of degrees centigrade

below the Thermal Control Circuit Activation temperature of the PECI device

6.3.2.6.10

Get Uncore Temperature

The Get Uncore Temperature command implemented by the processor is used to

retrieve the uncore temperature from a target PECI address. The temperature can be

used as an added input to the external thermal management system to regulate the

temperature on the die. The data is returned as a negative value representing the

number of degrees centigrade below the Thermal Control Circuit Activation

temperature of the PECI device. Note that a value of zero represents the temperature

at which the Thermal Control Circuit activates. The actual value that the thermal

management system uses as a control set point (Tcontrol) is also defined as a negative

number below the Thermal Control Circuit Activation temperature.

6.3.2.6.11

Write P-State Limit

This command creates a P-state frequency upper limit for OS requested P-states per

socket. The default value for this variable will correspond to P0 for Intel Xeon Processor

E7-8800/4800/2800 Product Families processors which support Intel Turbo Boost

Technology, and P1 for the remaining Intel Xeon Processor E7-8800/4800/2800 Product

Families processors. Any request for a frequency greater than P1 will be taken as a

request to have all available P-states enabled.

Depending on the current package operating state, using this function may lead to a P-

state transition.

The Intel Xeon Processor E7-8800/4800/2800 Product Families processor expects a

mailbox sideband limit request as a core clock multiplier ratio corresponding to a valid

P-state defined in the ACPI table (ACPI table is visible to PECI Host Controller).

The Intel Xeon Processor E7-8800/4800/2800 Product Families processor supports

clock ratios between MaxNonTurboRatio (P1)+1 and MaxEfficiencyRatio (Pn) as

allowable P-state requests, but it may expose only selective clock ratios as valid P-

states in the ACPI table.

Datasheet Volume 1 of 2

133

Thermal Specifications

Should a requested value be below Pn, it will be clamped at Pn. Should a requested

value be greater than P1, the value will be clipped to P1+1 for those Intel Xeon

Processor E7-8800/4800/2800 Product Families processors which support Intel Turbo

Boost Technology, and P1 for those which do not.

This setting is persistent across warm resets.

6.3.2.6.12

6.3.2.7

Read P-State Limit

This mailbox command is used by the PECI host to read out a socket's current sideband

P-state frequency ratio upper limit. If the value written is greater than allowed by the

ACPI table, the largest legal value will be returned. If the value written is lower than

allowed by the ACPI table, the lowest legal value will be returned. A value of P1+1

indicates enabling of all available P-states.

MbxSend()

The MbxSend() command is utilized for sending requests to the generic Mailbox

interface. Those requests are in turn serviced by the processor with some nominal

latency and the result is deposited in the mailbox for reading. MbxGet() is used to

retrieve the response and details are documented in Section 6.3.2.8.

The details of processor mailbox capabilities are described in Section 6.3.2.6.1, and

many of the fundamental concepts of Mailbox ownership, release, and management are

discussed in Section 6.3.2.9.

6.3.2.7.1

Write Data

Regardless of the function of the mailbox command, a request type modifier and 4-byte

data payload must be sent. For Mailbox commands where the 4-byte data field is not

applicable (for example, the command is a read), the data written should be all zeroes.

Figure 6-19. MbxSend() Command Data Format

0

1

2

3

4

Byte #

Byte

Definition

Request Type

Data[31:0]

Because a particular MbxSend() command may specify an update to potentially critical

registers inside the processor, it includes an Assured Write FCS (AW FCS) byte as part

of the write data payload. In the event that the AW FCS mismatches with the client-

calculated FCS, the client will abort the write and will always respond with a bad Write

FCS.

6.3.2.7.2

Command Format

The MbxSend() format is as follows:

Write Length: 7

Read Length: 1

Command: 0xd1

Multi-Domain Support: Yes (see Table 6-15)

134

Datasheet Volume 1 of 2

Thermal Specifications

Description: Deposits the Request Type and associated 4-byte data in the Mailbox

interface and returns a completion code byte with the details of the execution results.

Refer to Section 6.3.4.2 for completion code definitions.

Figure 6-20. MbxSend()

Byte #

0

1

2

3

Byte

Definition

Write Length

0x07

Read Length

0x01

Cmd Code

0xd1

Client Address

4

5

6

7

8

Request Type

LSB

Data[31:0]

MSB

9

10

11

12

Completion

Code

AW FCS

FCS

Note that the 4-byte data defined above is sent in standard PECI ordering with LSB first

and MSB last.

Table 6-12. MbxSend() Response Definition

Response

Bad FCS

Meaning

Electrical error

CC: 0x4X

CC: 0x80

Semaphore is granted with a Transaction ID of ‘X’

Error causing a response timeout. Either due to a rare, internal timing condition or a

processor RESET condition or processor S1 state. Retry is appropriate outside of the

RESET or S1 states.

CC: 0x86

Mailbox interface is unavailable or busy

If the MbxSend() response returns a bad Read FCS, the completion code can't be

trusted and the semaphore may or may not be taken. In order to clean out the

interface, an MbxGet() must be issued and the response data should be discarded.

6.3.2.8

MbxGet()

The MbxGet() command is utilized for retrieving response data from the generic

Mailbox interface as well as for unlocking the acquired mailbox. Please refer to

Section 6.3.2.7 for details regarding the MbxSend() command. Many of the

fundamental concepts of Mailbox ownership, release, and management are discussed

in Section 6.3.2.9.

6.3.2.8.1

Write Data

The MbxGet() command is designed to retrieve response data from a previously

deposited request. In order to guarantee alignment between the temporally separated

request (MbxSend) and response (MbxGet) commands, the originally granted

Transaction ID (sent as part of the passing MbxSend() completion code) must be issued

as part of the MbxGet() request.

Datasheet Volume 1 of 2

135

Thermal Specifications

Any mailbox request made with an illegal or unlocked Transaction ID will get a failed

completion code response. If the Transaction ID matches an outstanding transaction ID

associated with a locked mailbox, the command will complete successfully and the

response data will be returned to the originator.

Unlike MbxSend(), no Assured Write protocol is necessary for this command because

this is a read-only function.

6.3.2.8.2

Command Format

The MbxGet() format is as follows:

Write Length: 2

Read Length: 5

Command: 0xd5

Multi-Domain Support: Yes (see Table 6-15)

Description: Retrieves response data from mailbox and unlocks / releases that

mailbox resource.

Figure 6-21. MbxGet()

Byte #

0

1

2

3

Byte

Definition

Write Length

0x02

Read Length

0x05

Cmd Code

0xd5

Client Address

4

150

161

Completion

Code

Transaction ID

FCS

7

1850

1961

10

MSB

11

LSB

Response Data[31:0]

FCS

Note that the 4-byte data response defined above is sent in standard PECI ordering

with LSB first and MSB last.

Table 6-13. MbxGet() Response Definition

Response

Meaning

Aborted Write FCS Response data is not ready. Command retry is appropriate.

CC: 0x40

CC: 0x80

Command passed, data is valid

Error causing a response timeout. Either due to a rare, internal timing condition or a

processor RESET condition or processor S1 state. Retry is appropriate outside of the

RESET or S1 states.

CC: 0x81

CC: 0x82

CC: 0x83

CC: 0x84

Thermal configuration data was malformed or exceeded limits.

Thermal status mask is illegal

Invalid counter select

Invalid Machine Check Bank or Index

136

Datasheet Volume 1 of 2

Thermal Specifications

Table 6-13. MbxGet() Response Definition

Response

Meaning

CC: 0x85

CC: 0x86

CC: 0xFF

Failure due to lack of Mailbox lock or invalid Transaction ID

Mailbox interface is unavailable or busy

Unknown/Invalid Mailbox Request

6.3.2.9

Mailbox Usage Definition

Acquiring the Mailbox

6.3.2.9.1

The MbxSend() command is used to acquire control of the PECI mailbox and issue

information regarding the specific request. The completion code response indicates

whether or not the originator has acquired a lock on the mailbox, and that completion

code always specifies the Transaction ID associated with that lock (see

Section 6.3.2.9.2).

Once a mailbox has been acquired by an originating agent, future requests to acquire

that mailbox will be denied with an ‘interface busy’ completion code response.

The lock on a mailbox is not achieved until the last bit of the MbxSend() Read FCS is

transferred (in other words, it is not committed until the command completes). If the

host aborts the command at any time prior to that bit transmission, the mailbox lock

will be lost and it will remain available for any other agent to take control.

6.3.2.9.2

Transaction ID

For all MbxSend() commands that complete successfully, the passing completion code

(0x4X) includes a 4-bit Transaction ID (‘X’). That ID is the key to the mailbox and must

be sent when retrieving response data and releasing the lock by using the MbxGet()

command.

The Transaction ID is generated internally by the processor and has no relationship to

the originator of the request. On Intel Xeon Processor E7-8800/4800/2800 Product

Families processors, only a single outstanding Transaction ID is supported. Therefore, it

is recommended that all devices requesting actions or data from the Mailbox complete

their requests and release their semaphore in a timely manner.

In order to accommodate future designs, software or hardware utilizing the PECI

mailbox must be capable of supporting Transaction IDs between 0 and 15.

6.3.2.9.3

6.3.2.9.4

Releasing the Mailbox

The mailbox associated with a particular Transaction ID is only unlocked / released

upon successful transmission of the last bit of the Read FCS. If the originator aborts the

transaction prior to transmission of this bit (presumably due to an FCS failure), the

semaphore is maintained and the MbxGet() command may be retried.

Mailbox Timeouts

The mailbox is a shared resource that can result in artificial bandwidth conflicts among

multiple querying processes that are sharing the same originator interface. The

interface response time is quick, and with rare exception, back to back MbxSend() and

MbxGet() commands should result in successful execution of the request and release of

the mailbox. In order to guarantee timely retrieval of response data and mailbox

release, the mailbox semaphore has a timeout policy. If the PECI bus has a cumulative

‘0 time of 1ms since the semaphore was acquired, the semaphore is automatically

Datasheet Volume 1 of 2

137

Thermal Specifications

cleared. In the event that this timeout occurs, the originating agent will receive a failed

completion code upon issuing a MbxGet() command, or even worse, it may receive

corrupt data if this MbxGet() command so happens to be interleaved with an

MbxSend() from another process. Please refer to Table 6-13 for more information

regarding failed completion codes from MbxGet() commands.

Timeouts are undesirable, and the best way to avoid them and guarantee valid data is

for the originating agent to always issue MbxGet() commands immediately following

MbxSend() commands.

Alternately, mailbox timeout can be disabled. The BIOS may write MSR

MISC_POWER_MGMT (0x1AA), bit 11 to 0b1 in order to force a disable of this

automatic timeout.

6.3.2.9.5

Response Latency

The PECI mailbox interface is designed to have response data available within plenty of

margin to allow for back-to-back MbxSend() and MbxGet() requests. However, under

rare circumstances that are out of the scope of this specification, it is possible that the

response data is not available when the MbxGet() command is issued. Under these

circumstances, the MbxGet() command will respond with an Abort FCS and the

originator should re-issue the MbxGet() request.

6.3.3

Multi-Domain Commands

The Intel Xeon Processor E7-8800/4800/2800 Product Families processor does not

support multiple domains, but it is possible that future products will, and the following

tables are included as a reference for domain-specific definitions.

Table 6-14. Domain ID Definition

Domain ID

Domain Number

0b01

0b10

0

1

Table 6-15. Multi-Domain Command Code Reference

Domain 0

Domain 1

Code

Command Name

Code

GetTemp()

0x01

0xC1

0xC5

0xD1

0xD5

0x02

0xC2

0xC6

0xD2

0xD6

PCIConfigRd()

PCIConfigWr()

MbxSend()

MbxGet()

6.3.4

Client Responses

6.3.4.1

Abort FCS

The Client responds with an Abort FCS under the following conditions:

• The decoded command is not understood or not supported on this processor (this

includes good command codes with bad Read Length or Write Length bytes).

• Data is not ready.

138

Datasheet Volume 1 of 2

Thermal Specifications

• Assured Write FCS (AW FCS) failure. Note that under most circumstances, an

Assured Write failure will appear as a bad FCS. However, when an originator issues

a poorly formatted command with a miscalculated AW FCS, the client will

intentionally abort the FCS in order to guarantee originator notification.

6.3.4.2

Completion Codes

Some PECI commands respond with a completion code byte. These codes are designed

to communicate the pass/fail status of the command and also provide more detailed

information regarding the class of pass or fail. For all commands listed in Section 6.3.2

that support completion codes, each command’s completion codes is listed in its

respective section. What follows are some generalizations regarding completion codes.

An originator that is decoding these commands can apply a simple mask to determine

pass or fail. Bit 7 is always set on a failed command, and is cleared on a passing

command.

Table 6-16. Completion Code Pass/Fail Mask

0xxx xxxxb

1xxx xxxxb

Command passed

Command failed

Table 6-17. Device Specific Completion Code (CC) Definition

Completion

Description

Code

0x00..0x3F

0x40

Device specific pass code

Command Passed

0x4X

Command passed with a transaction ID of ‘X’ (0x40 | Transaction_ID[3:0])

Device specific pass code

0x50..0x7F

CC: 0x80

Error causing a response timeout. Either due to a rare, internal timing condition or a

processor RESET condition or processor S1 state. Retry is appropriate outside of the RESET

or S1 states.

CC: 0x81

CC: 0x82

CC: 0x83

CC: 0x84

CC: 0x85

CC: 0x86

CC:0xFF

Thermal configuration data was malformed or exceeded limits.

Thermal status mask is illegal

Invalid counter select

Invalid Machine Check Bank or Index

Failure due to lack of Mailbox lock or invalid Transaction ID

Mailbox interface is unavailable or busy

Unknown/Invalid Mailbox Request

Note:

The codes explicitly defined in this table may be useful in PECI originator response

algorithms. All reserved or undefined codes may be generated by a PECI client device,

and the originating agent must be capable of tolerating any code. The Pass/Fail mask

defined in Table 6-16 applies to all codes and general response policies may be based

on that limited information.

6.3.5

Originator Responses

The simplest policy that an originator may employ in response to receipt of a failing

completion code is to retry the request. However, certain completion codes or FCS

responses are indicative of an error in command encoding and a retry will not result in

a different response from the client. Furthermore, the message originator must have a

response policy in the event of successive failure responses.

Datasheet Volume 1 of 2

139

Thermal Specifications

Refer to the definition of each command in Section 6.3.2 for a specific definition of

possible command codes or FCS responses for a given command. The following

response policy definition is generic, and more advanced response policies may be

employed at the discretion of the originator developer.

Table 6-18. Originator Response Guidelines

Response

Bad FCS

After 1 Attempt

Retry

After 3 attempts

Fail with PECI client device error

Abort FCS

CC: Fail

Retry

Fail with PECI client device error. May be due to illegal command codes.

Either the PECI client doesn’t support the current command code, or it has

failed in its attempts to construct a response.

None (all 0’s) Force bus idle

(1ms low), retry

Fail with PECI client device error. Client may be dead or otherwise non-

responsive (in RESET or S1, for example).

CC: Pass

Pass

n/a

Good FCS

6.3.6

Temperature Data

6.3.6.1

Format

The temperature is formatted in a 16-bit, 2’s complement value representing a number

of 1/64 degrees centigrade. This format allows temperatures in a range of ±512°C to

be reported to approximately a 0.016°C resolution.

Figure 6-22. Temperature Sensor Data Format

MSB

LSB

Upper nibble

Lower nibble

Upper nibble

Lower nibble

S

x

Sign

Integer Value (0-511)

Fractional Value (~0.016)

6.3.6.2

Interpretation

The resolution of the processor’s Digital Thermal Sensor (DTS) is approximately 1°C,

which can be confirmed by a RDMSR from IA32_THERM_STATUS MSR (0x19C) where it

is architecturally defined. PECI temperatures are sent through a configurable low-pass

filter prior to delivery in the GetTemp() response data. The output of this filter produces

temperatures at the full 1/64°C resolution even though the DTS itself is not this

accurate.

Temperature readings from the processor are always negative in a 2’s complement

format, and imply an offset from the reference TCC activation temperature. As an

example, assume that the TCC activation temperature reference is 100°C. A PECI

thermal reading of -10 indicates that the processor is running approximately 10°C

below the TCC activation temperature, or 90°C. PECI temperature readings are not

reliable at temperatures above TCC activation (since the processor is operating out of

specification at this temperature). Therefore, the readings are never positive.

6.3.6.3

Temperature Filtering

The processor digital thermal sensor (DTS) provides an improved capability to monitor

device hot spots, which inherently leads to more varying temperature readings over

short time intervals. Coupled with the fact that typical fan speed controllers may only

read temperatures at 4 Hz, it is necessary for the thermal readings to reflect thermal

140

Datasheet Volume 1 of 2

Thermal Specifications

trends and not instantaneous readings. Therefore, PECI supports a configurable low-

pass temperature filtering function. By default, this filter results in a thermal reading

that is a moving average of 256 samples taken at approximately 1msec intervals. This

filter’s depth, or smoothing factor, may be configured to between 1 sample and 1024

samples, in powers of 2. See the following equation for reference where the

configurable variable is ‘X’.

T_N= T_N-1+ 1/2^X* (T_SAMPLE- T_N-1

)

Refer to Section 6.3.2.6.6 for the definition of the thermal configuration command.

6.3.6.4

Reserved Values

Several values well out of the operational range are reserved to signal temperature

sensor errors. These are summarized in the following table:

Table 6-19. Error Codes and Descriptions

Error Code

Description

0x8000

General Sensor Error (GSE)

6.3.7

Client Management

Power-up Sequencing

6.3.7.1

The PECI client is fully reset during processor RESET_N assertion. This means that any

transactions on the bus will be completely ignored, and the host will read the response

from the client as all zeroes. After processor RESET_N deassertion, the Intel Xeon

Processor E7-8800/4800/2800 Product Families processor PECI client is operational

enough to participate in timing negotiations and respond with reasonable data.

However, the client data is not guaranteed to be fully populated until approximately

500 µS after processor RESET_N is deasserted. Until that time, data may not be ready

for all commands. Note that PECI commands may time out frequently during boot. The

client responses to each command are as follows:

Table 6-20. PECI Client Response During Power-Up (During ‘Data Not Ready’)

Command

Ping()

Response

Fully functional

GetDIB()

GetTemp()

PCIConfigRd()

PCIConfigWr()

MbxSend()

MbxGet()

Client responds with a ‘hot’ reading, or 0x0000

Fully functional

Client responds with Abort FCS (if MbxSend() has been previously issued)

In the event that the processor is tri-stated using power-on-configuration controls, the

PECI client will also be tri-stated. Processor tri-state controls are described in

Chapter 7.

Datasheet Volume 1 of 2

141

Thermal Specifications

Figure 6-23. PECI Power-up Timeline

V io

V io P w rG d

S u p p ly V c c

B c lk

P w rG d

C P U R E S E T #

C S I p in s

C S I tra in in g

id le

ru n n in g

C o re e x e c u tio n

R e se t u C o d e

B o o t B IO S

P E C I C lie n t S ta tu s

D N R

F u lly O p e ra tio n a l

X

N o d e ID V a lid

P E C I N o d e ID

6.3.7.2

6.3.7.3

Device Discovery

The PECI client is available on all processors, and positive identification of the PECI

revision number can be achieved by issuing the GetDIB() command. Please refer to

Section 6.3.2.2 for details on GetDIB response formatting.

Client Addressing

The PECI client assumes a default base address of 0x30. There are three SKT_ID#

strapping pins that are used to strap each PECI socket to a different node ID (in

addition to defining the processor's socket ID). Since SKT_ID# is active low, strapping

a pin to ground results in value of 1 for that bit of the client ID, and strapping to Vio

results in a value of 0 for that bit. The Intel Xeon processor 7500 series client

addresses can therefore be strapped for values 0x30 through 0x37. These package pin

straps are evaluated at the assertion of VCCPWRGOOD.

The client address may not be changed after VCCPWRGOOD assertion, until the next

power cycle on the processor. Removal of a processor from its socket or tri-stating a

processor in a MP configuration will have no impact to the remaining non-tri-stated

PECI client address.

6.3.7.4

C-States

The Intel Xeon Processor E7-8800/4800/2800 Product Families processor PECI client is

fully functional under all core and package C-states. Support for package C-states is a

function of processor SKU and platform capabilities.

Because the Intel Xeon Processor E7-8800/4800/2800 Product Families processor takes

aggressive power savings actions under the deepest C-states, PECI requests may have

an impact to platform power. The impact is documented below:

• Ping(), GetDIB(), GetTemp() and MbxGet() have no measurable impact on

processor power under C-states.

• MbxSend(), PCIConfigRd() and PCIConfigWr() usage under package C-states may

result in increased power consumption because the processor must temporarily

return to a C0 state in order to execute the request. The exact power impact of a

142

Datasheet Volume 1 of 2

Thermal Specifications

pop-up to C0 varies by product SKU, the C-state from which the pop-up is initiated,

and the negotiated T_BIT

.

Table 6-21. Power Impact of PECI Commands vs. C-states

Command

Ping()

Power Impact

Not measurable

GetDIB()

Not measurable

GetTemp()

PCIConfigRd()

PCIConfigWr()

MbxSend()

MbxGet()

Not measurable

Requires a package ‘pop-up’ to a C0 state

Not measurable

6.3.7.5

S-States

The PECI client is always guaranteed to be operational under S0 and S1 sleep states.

Under S3 and deeper sleep states, the PECI client response is undefined and, therefore,

unreliable.

Table 6-22. PECI Client Response During S1

Command

Response

Ping()

Fully functional

GetDIB()

GetTemp()

PCIConfigRd()

PCIConfigWr()

MbxSend()

MbxGet()

6.3.7.6

Processor Reset

The Intel Xeon Processor E7-8800/4800/2800 Product Families processor PECI client is

fully reset on all RESET_N assertions. Upon deassertion of RESET_N, where power is

maintained to the processor (otherwise known as a ‘warm reset’), the following are

true:

• The PECI client assumes a bus Idle state.

• The Thermal Filtering Constant is retained.

• The GetTemp() reading resets to 0x0000.

• Any transaction in progress is aborted by the client (as measured by the client no

longer participating in the response).

• The processor client is otherwise reset to a default configuration.

§

Datasheet Volume 1 of 2

143

Thermal Specifications

144

Datasheet Volume 1 of 2

Features

7 Features

7.1

Introduction

The Intel Xeon Processor E7-8800/4800/2800 Product Families processor package

includes PECI 2.0, TAP and SMBus interfaces which allow access to processor’s package

information. The processor die is connected to the PECI2.0 and TAP, and these

interfaces can be used for access to the configuration registers of the processor. The

processor Information ROM (PIROM) and scratch EEROM, are accessed via the SMBus

connection.

Figure 7-1. Logical Schematic of Intel^®Xeon^®Processor E7-8800/4800/2800 Product

Families Package

Package Pins

Level Shifter

GTL2003

Level Shifter

GND

EEPROM

34C02

PCA9509

Processor

Die

Note:

Actual implementation may vary. This figure is provided to offer a general understanding of the architecture.

Datasheet Volume 1 of 2

145

Features

7.2

Clock Control and Low Power States

The processor supports low power states at the individual thread, core, and package

level for optimal power management.

7.2.1

Processor C-State Power Specifications

Table 7-1 lists C-State power specifications for various Intel Xeon Processor E7-8800/

4800/2800 Product Families processor SKUs.

Table 7-1.

Processor C-State Power Specifications

Intel Xeon Processor

E7-8800/4800/2800

Product Families

Intel Xeon Processor

E7-8800/4800/2800

Product Families

Intel Xeon Processor

E7-8800/4800/2800

Product Families

Package

C-State

1

processor 130W

processor 105W

processor 95W

C1E

C3

56

36

31

54

35

29

54

35

29

C6

Notes:

1. Values are with all cores in the specified C-State.

7.3

Sideband Access to Processor Information ROM

via SMBus

7.3.1

Processor Information ROM

Offset/

Section

# of

Bits

Function

Notes

Examples

Header

00h

8

Data Format Revision

PIROM Size

Two 4-bit hex digits

Start with 00h

01-02h

16

Size in bytes (MSB first)

Use a decimal to hex transfer; 128

bytes = 0080h:

03h

8

Processor Data Address

Processor Core Data Address

Processor Uncore Data Address

Package Data Address

Part Number Data Address

Thermal Reference Data Address

Feature Data Address

Other Data Address

Byte pointer, 00h if not present

Reserved for future use

0Eh

1Bh

2A

04h

05h

8

06h

8

4Ch

54h

66h

6Ch

77h

0000h

07h

8

08h

8

09h

8

0Ah

0B-0Ch

0Dh

8

16

8

Reserved

Checksum

1 byte checksum

Add up by byte and take 2’s

complement

Processor Data

0E-13h

14h

48

S-spec Number

Six 8-bit ASCII characters

First seven bits reserved

7/1

Sample/Production

0b = Sample, 1b = Production

00000001 = production

15

6

2

Number of Cores

Number of Threads

[7:2] = Number of cores

[1:0] = Threads per core

00100010 = 8 cores with 2 threads

each

1

16-17h

18-19

16

System Bus Speed

Reserved

Four 4-bit hex digits (Mhz)

Reserved for future use

0133h = 133 MHz

0000h

146

Datasheet Volume 1 of 2

Features

Offset/

Section

# of

Bits

Function

Notes

1 byte checksum

Examples

1Ah

8

Checksum

Add up by byte and take 2’s

complement

Processor Core Data

1B-1Ch

1D-1Eh

1F-20h

16

CPUID

Four 4-bit hex digits

Reserved

Reserved for future use

0000h

1

Maximum P1 Core Frequency

Non-Turbo Boost (Mhz)

2000h = 2000 MHz

Four 4-bit hex digits (Mhz)

1

21-22h

16

Maximum P0 Core Frequency

Turbo Boost (Mhz)

2400h = 2400 MHz

Four 4-bit hex digits (Mhz)

1

23-24h

25-26h

27h

16

8

Maximum Core Voltage ID

Minimum Core Voltage ID

Core Voltage Tolerance, High

Four 4-bit hex digits (mV)

1500h = 1500 mV

1

1000h = 1000 mV

1

Allowable positive DC shift

Two 4-bit hex digits (mV)

15h = 15mV

1

28h

29h

8

Core Voltage Tolerance, Low

Checksum

Allowable negative DC shift

Two 4-bit hex digits (mV)

15h = 15mV

1 byte checksum

Add up by byte and take 2’s

complement

Processor Uncore Data

1

2A-2Bh

16

Maximum Intel QPI Link Transfer

Rate

Four 4-bit hex digits (in MT/s)

6400h = 6400 MT/s

5866h = 5866 MT/s

1

2C-2Dh

16

Minimum Intel QPI Link Transfer

Rate

4800h = 4800 MT/s

2E-31h

32h

32

Intel QPI Version Number

Intel TXT

Four 8-bit ASCII Characters

First seven bits reserved

01.0

7/1

00000001 = supported

00000000 = unsupported

1

33-34h

16

Maximum Intel SMI Transfer Rate Four 4-bit hex digits (in MT/s)

6400h = 6400 MT/s

5866h = 5866 MT/s

1

35-36h

37-38h

39h

16

8

Minimum Intel SMI Transfer Rate Four 4-bit hex digits (in MT/s)

4800h = 4800 MT/s

1

VIO Voltage ID

Four 4-bit hex digits (mV)

1125h = 1125 mV

1

VIO Voltage Tolerance, High

Edge finger tolerance

15h = 15 mV

Two 4-bit hex digits (mV)

1

3Ah

8

VIO Voltage Tolerance, Low

Edge finger tolerance

15h = 15 mV

Two 4-bit hex digits (mV)

3B-3Eh

3F-40h

41-42h

32

16

Reserved

Reserved for future use

Decimal (Kb) Per CPU Core

Decimal (Kb)

00000000h

L2 Cache Size

L3 Cache Size

0100h = 256 Kb

6000h = 24576 Kb, 4800h =

18432 Kb, 3000h = 12288 Kb

1

43-44

45h

16

8

Cache Voltage ID

Four 4-bit hex digits (mV)

1500h = 1500 mV

1

Cache Voltage Tolerance, High

Allowable positive DC shift

Two 4-bit hex digits (mV)

15h = 15 mV

1

46h

8

Cache Voltage Tolerance, Low

Allowable negative DC shift

Two 4-bit hex digits (mV)

15h = 15 mV

47-4Ah

4Bh

32

8

Reserved

Reserved for future use

1 byte checksum

00000000h

Checksum

Add up by byte and take 2’s

complement.

Package

4C-4Fh

50h

32

6/2

16

8

Package Revision

Substrate Revision Software ID

Reserved

Four 8-bit ASCII characters

First 6 bits reserved

Reserved for future use

1 byte checksum

01.0

000000**

0000h

51-52h

53h

Checksum

Add up by byte and take 2’s

complement.

Datasheet Volume 1 of 2

147

Features

Offset/

Section

# of

Bits

Function

Notes

Examples

Part Numbers

54-5Ah

5B-62h

63-64h

65h

56

Processor Family Number

Processor SKU Number

Reserved

Seven 8-bit ASCII characters

Reserved for future use

1 byte checksum

AT80604

003771AA

0000h

64

16

8

Checksum

Add up by byte and take 2’s

complement.

Thermal Reference

1

66h

8

Recommended THERMALERT_N

assertion threshold value

MSB is Reserved

0h = 0C

1

67h

68h

8

Thermal calibration offset value

0h = 0C

1

T

Maximum

Maximum case temperature

Two 4-bit hex digits (mV)

69h = 69°C

CASE

1

69-6Ah

6Bh

16

8

Thermal Design Power

Checksum

Four 4-bit hex digits (in Watts)

1 byte checksum

0130h = 130 Watts

Add up by byte and take 2’s

complement.

Features

6C-6Fh

32

8

Processor Core Feature Flags

Processor Feature Flags

From CPUID function 1, EDX

contents

4387FBFFh

10001101

70h

Eight features - Binary

1 indicates functional feature

71h

72

8

Additional Processor Feature

Flags

Eight additional features - Binary

1 indicates functional feature

01110101

6/2

4/4

Multiprocessor Support

00b = UP, 01b = DP, 10b = S2S,

11b = MP/SMS

00000011 = MP/SMS

1

73h

Number of Devices in TAP Chain

First four bits reserved

One 4-bit hex digit - Bits

*0h

74-75h

76h

16

8

Reserved

Reserved for future use

1 byte checksum

0000h

Checksum

Add up by byte and take 2’s

complement.

Other

77-7Eh

64

8

Processor Serial/Electronic

Signature

Coded binary

N/A

7Fh

Checksum

1 byte checksum

Add up by byte and take 2’s

complement.

Notes:

1. Uses Binary Coded Decimal (BCD) translation.

7.3.2

Scratch EEPROM

Also available in the memory component on the processor SMBus is an EEPROM which

may be used for other data at the system or processor vendor’s discretion. The data in

this EEPROM, once programmed, can be write-protected by asserting the active-high

SM_WP signal. This signal has a weak pull-down (10 kΩ) to allow the EEPROM to be

programmed in systems with no implementation of this signal. The Scratch EEPROM

resides in the upper half of the memory component (addresses 80 - FFh). The lower

half comprises the Processor Information ROM (addresses 00 - 7Fh), which is

permanently write-protected by Intel.

148

Datasheet Volume 1 of 2

Features

7.3.3

PIROM and Scratch EEPROM Supported SMBus

Transactions

The PIROM responds to two SMBus packet types: Read Byte and Write Byte. However,

since the PIROM is write-protected, it will acknowledge a Write Byte command but

ignore the data. The Scratch EEPROM responds to Read Byte and Write Byte

commands. Table 7-2 illustrates the Read Byte command. Table 7-3 illustrates the

Write Byte command.

In the tables, ‘S’ represents a SMBus start bit, ‘P’ represents a stop bit, ‘A’ represents

an acknowledge (ACK), and ‘///’ represents a negative acknowledge (NACK). The

shaded bits are transmitted by the PIROM or Scratch EEPROM, and the bits that aren’t

shaded are transmitted by the SMBus host controller. In the tables, the data addresses

indicate 8 bits.

The SMBus host controller should transmit 8 bits with the most significant bit indicating

which section of the EEPROM is to be addressed: the PIROM (MSB = 0) or the Scratch

EEPROM (MSB = 1).

Table 7-2.

Read Byte SMBus Packet

Slave

Address

Command

Code

Slave

Address

S

Write

A

S

Read

A

Data

///

P

1

7-bits

1

8-bits

1

7-bits

1

8-bits

1

Table 7-3.

Write Byte SMBus Packet

Slave

Address

Command

Code

S

Write

A

Data

A

P

1

7-bits

1

8-bits

1

8-bits

1

7.4

SMBus Memory Component Addressing

Of the addresses broadcast across the SMBus, the memory component claims those of

the form “10100XXZb”. The “XX” bits are defined by pull-up and pull-down of the

SKTID[1:0] pins. Note that SKTID[2] does not affect the SMBus address for the

memory component. These address pins are pulled down weakly (10 k) on the

processor substrate to ensure that the memory components are in a known state in

systems which do not support the SMBus (or only support a partial implementation).

The “Z” bit is the read/write bit for the serial bus transaction.

Note that addresses of the form “0000XXXXb” are Reserved and should not be

generated by an SMBus master.

Table 7-4 describes the address pin connections and how they affect the addressing of

the memory component.

Datasheet Volume 1 of 2

149

Features

Table 7-4.

Memory Device SMBus Addressing

Upper

Address

Device Select

R/W

1

Address

(Hex)

SKTID[1]

Bit 2

SKTID[0]

Bit 1

Bits 7-4

SKTID[2]

Bit 0

A0h/A1h

A2h/A3h

A4h/A5h

A6h/A7h

10100

0

1

0

1

0

1

X

Note:

1. This addressing scheme will support up to 4 processors on a single SMBus.

7.5

Managing Data in the PIROM

The PIROM consists of the following sections:

• Header

• Processor Data

• Processor Core Data

• Processor Uncore Data

• Cache Data

• Package Data

• Part Number Data

• Thermal Reference Data

• Feature Data

• Other Data

Details on each of these sections are described below.

Note:

Reserved fields or bits SHOULD be programmed to zeros. However, OEMs should not

rely on this model.

7.5.1

Header

To maintain backward compatibility, the Header defines the starting address for each

subsequent section of the PIROM. Software should check for the offset before reading

data from a particular section of the ROM.

Example: Code looking for the processor uncore data of a processor would read offset

05h to find a value of 29. 29 is the first address within the 'Processor Uncore Data'

section of the PIROM.

7.5.1.1

DFR: Data Format Revision

This location identifies the data format revision of the PIROM data structure. Writes to

this register have no effect.

150

Datasheet Volume 1 of 2

Features

Offset:

00h

Bit

Description

7:0

Data Format Revision

The data format revision is used whenever fields within the PIROM are

redefined. The initial definition will begin at a value of 1. If a field, or bit

assignment within a field, is changed such that software needs to discern

between the old and new definition, then the data format revision field will be

incremented.

00h: Reserved

01h: Initial definition

02h: Second revision

03h: Third revision

04h: Fourth revision

05h:Fifth revision (Defined by this document)

06h-FFh: Reserved

7.5.1.2

PISIZE: PIROM Size

This location identifies the PIROM size. Writes to this register have no effect.

Offset:

01h-02h

Bit

Description

15:0

PIROM Size

The PIROM size provides the size of the device in hex bytes. The MSB is at

location 01h; the LSB is at location 02h.

0000h - 007Fh: Reserved

0080h: 128 byte PIROM size

0081- FFFFh: Reserved

7.5.1.3

PDA: Processor Data Address

This location provides the offset to the Processor Data Section. Writes to this register

have no effect.

Offset:

03h

Bit

Description

7:0

Processor Data Address

Byte pointer to the Processor Data section

00h: Processor Data section not present

01h - 0Dh: Reserved

0Eh: Processor Data section pointer value

0Fh-FFh: Reserved

Datasheet Volume 1 of 2

151

Features

7.5.1.4

7.5.1.5

7.5.1.6

PCDA: Processor Core Data Address

This location provides the offset to the Processor Core Data Section. Writes to this

register have no effect.

Offset:

04h

Bit

Description

7:0

Processor Core Data Address

Byte pointer to the Processor Core Data section

00h: Processor Core Data section not present

01h - 09h: Reserved

1Ah: Processor Core Data section pointer value

1Bh-FFh: Reserved

PUDA: Processor Uncore Data Address

This location provides the offset to the Processor Uncore Data Section. Writes to this

register have no effect.

Offset:

05h

Bit

Description

7:0

Processor Uncore Data Address

Byte pointer to the Processor Uncore Data section

00h: Processor Uncore Data section not present

01h - 28h: Reserved

29h: Processor Uncore Data section pointer value

2Ah-FFh: Reserved

PDA: Package Data Address

This location provides the offset to the Package Data Section. Writes to this register

have no effect.

Offset:

06h

Bit

Description

7:0

Package Data Address

Byte pointer to the Package Data section

00h: Package Data section not present

01h - 4Ah: Reserved

4Bh: Package Data section pointer value

4Ch-FFh: Reserved

152

Datasheet Volume 1 of 2

Features

7.5.1.7

PNDA: Part Number Data Address

This location provides the offset to the Part Number Data Section. Writes to this

register have no effect.

Offset:

07h

Bit

Description

7:0

Part Number Data Address

Byte pointer to the Part Number Data section

00h: Part Number Data section not present

01h - 52h: Reserved

53h: Part Number Data section pointer value

54h-FFh: Reserved

7.5.1.8

TRDA: Thermal Reference Data Address

This location provides the offset to the Thermal Reference Data Section. Writes to this

register have no effect.

Offset:

08h

Bit

Description

7:0

Thermal Reference Data Address

Byte pointer to the Thermal Reference Data section

00h: Thermal Reference Data section not present

01h - 64h: Reserved

65h: Thermal Reference Data section pointer value

66h-FFh: Reserved

7.5.1.9

FDA: Feature Data Address

This location provides the offset to the Feature Data Section. Writes to this register

have no effect.

Offset:

09h

Bit

Description

7:0

Feature Data Address

Byte pointer to the Feature Data section

00h: Feature Data section not present

01h - 6Ah: Reserved

6Bh: Feature Data section pointer value

6Ch-FFh: Reserved

Datasheet Volume 1 of 2

153

Features

7.5.1.10

ODA: Other Data Address

This location provides the offset to the Other Data Section. Writes to this register have

no effect.

Offset:

0Ah

Bit

Description

7:0

Other Data Address

Byte pointer to the Other Data section

00h: Other Data section not present

01h - 78h: Reserved

79h: Other Data section pointer value

7Ah- FFh: Reserved

7.5.1.11

RES1: Reserved 1

This location is reserved. Writes to this register have no effect.

Offset:

0Bh-0Ch

Bit

Description

15:0

RESERVED

0000h-FFFFh: Reserved

7.5.1.12

HCKS: Header Checksum

This location provides the checksum of the Header Section. Writes to this register have

no effect.

Offset:

0Dh

Bit

Description

7:0

Header Checksum

One-byte checksum of the Header Section

00h- FFh: See Section 7.5.10 for calculation of this value.

7.5.2

Processor Data

This section contains three pieces of data:

• The S-spec of the part in ASCII format.

• (1) 2-bit field to declare if the part is a pre-production sample or a production unit.

• The system bus speed in BCD format

7.5.2.1

SQNUM: S-Spec Number

This location provides the S-Spec number of the processor. The S-spec field is six ASCII

characters wide and is programmed with the same spec value as marked on the

processor. If the value is less than six characters in length, leading spaces (20h) are

programmed in this field. Writes to this register have no effect.

154

Datasheet Volume 1 of 2

Features

Offset:

0Eh-13h

Bit

Description

47:40

Character 6

S-Spec or 20h

00h-0FFh: ASCII character

39:32

31:24

23:16

15:8

Character 5

S-Spec or 20h

00h-0FFh: ASCII character

Character 4

S-Spec character

00h-0FFh: ASCII character

Character 3

S-Spec character

00h-0FFh: ASCII character

Character 2

S-Spec character

00h-0FFh: ASCII character

7:0

Character 1

S-Spec character

00h-0FFh: ASCII character

7.5.2.2

SAMPROD: Sample/Production

This location contains the sample/production field, which is a two-bit field and is LSB

aligned. All sample material will use a value of 00b. All S-spec material will use a value

of 01b. All other values are reserved. Writes to this register have no effect.

Example: A processor with an Sxxxx mark (production unit) will use 01h at offset 14h.

Offset:

14h

Bit

Description

7:2

RESERVED

000000b-111111b: Reserved

1:0

Sample/Production

Sample or Production indictor

00b: Sample

01b: Production

10b-11b: Reserved

7.5.2.3

Processor Thread and Core Information

This location contains information regarding the number of cores and threads on the

processor. Writes to this register have no effect. Data format is binary.

Example: The Intel Xeon Processor E7-8800/4800/2800 Product Families processor

has up to 10 cores and two threads per core.

Datasheet Volume 1 of 2

155

Features

Offset:

Bit

15h

Description

7:2

1:0

Number of cores

Number of threads per core

7.5.2.4

SBS: System Bus Speed

This location contains the system bus frequency information. Systems may need to

read this offset to decide if all installed processors support the same system bus speed.

The data provided is the speed, rounded to a whole number, and reflected in binary

coded decimal. Writes to this register have no effect.

Example: A processor with system buss speed of 1.066GHz will have a value of 1066h.

Offset:

16h-17h

Bit

Description

15:0

System Bus Speed

0000h-FFFFh: MHz

7.5.2.5

RES2: Reserved 2

This location is reserved. Writes to this register have no effect.

Offset:

18h-19h

Bit

Description

15:0

RESERVED

0000h-FFFFh: Reserved

7.5.2.6

PDCKS: Processor Data Checksum

This location provides the checksum of the Processor Data Section. Writes to this

register have no effect.

Offset:

1Ah

Bit

Description

7:0

Processor Data Checksum

One-byte checksum of the Processor Data Section

00h- FFh: See Section 7.5.10 for calculation of this value.

7.5.3

Processor Core Data

This section contains silicon-related data relevant to the processor cores.

7.5.3.1

CPUID: CPUID

This location contains the CPUID, Processor Type, Family, Model and Stepping. The

CPUID field is a copy of the results in EAX[15:0] from Function 1 of the CPUID

instruction. Writes to this register have no effect. Data format is hexidecimal.

156

Datasheet Volume 1 of 2

Features

Offset:

1Bh-1Ch

Reserved

Bit

Description

15:13

00b-11b: Reserved

12:12

11:8

7:4

Processor Type

0b-1b: Processor Type

Processor Family

0h-Fh: Processor Family

Processor Model

0h-Fh: Processor Model

3:0

Processor Stepping

0h-Fh: Processor Stepping

7.5.3.2

RES3: Reserved 3

This locations are reserved. Writes to this register have no effect.

Offset:

1Dh-1Eh

Bit

Description

15:0

RESERVED

0000h-FFFFh: Reserved

7.5.3.3

MP1CF: Maximum P1 Core Frequency

This location contains the maximum non-Turbo Boost core frequency for the processor.

The frequency should equate to the markings on the processor and/or the S-spec

speed even if the parts are not limited or locked to the intended speed. Format of this

field is in MHz, rounded to a whole number, and encoded in binary coded decimal.

Writes to this register have no effect.

Example: A 2.666 GHz processor will have a value of 2666h.

Offset:

1F-20h

Bit

Description

15:0

Maximum P1 Core Frequency

0000h-FFFFh: MHz

7.5.3.4

MP0CF: Maximum P0 Core Frequency

This location contains the maximum Turbo Boost core frequency for the processor. This

is the maximum intended speed for the part under any functional conditions. Format of

this field is in MHz, rounded to a whole number, and encoded in binary coded decimal.

Writes to this register have no effect.

Example: A processor with a maximum Turbo Boost frequency of 2.666 GHz will have

a value of 2666h.

Datasheet Volume 1 of 2

157

Features

Offset:

21h-22h

Bit

Description

15:0

Maximum P0 Core Frequency

0000h-FFFFh: MHz

7.5.3.5

MAXVID: Maximum Core VID

This location contains the maximum Core VID (Voltage Identification) voltage that may

be requested via the VID pins. This field, rounded to the next thousandth, is in mV and

is reflected in binary coded decimal. Writes to this register have no effect.

Example: A voltage of 1.350 V maximum core VID would contain 1350h.

Offset:

23h-24h

Bit

Description

15:0

Maximum Core VID

0000h-FFFFh: mV

7.5.3.6

MINVID: Minimum Core VID

This location contains the Minimum Core VID (Voltage Identification) voltage that may

be requested via the VID pins. This field, rounded to the next thousandth, is in mV and

is reflected in binary coded decimal. Writes to this register have no effect.

Example: A voltage of 1.000 V maximum core VID would contain 1000h.

Offset:

25h-26h

Bit

Description

15:0

Maximum Core VID

0000h-FFFFh: mV

7.5.3.7

VTH: Core Voltage Tolerance, High

This location contains the maximum Core Voltage Tolerance DC offset high. This field,

rounded to the next thousandth, is in mV and is reflected in binary coded decimal.

Writes to this register have no effect. A value of FF indicates that this value is

undetermined. Writes to this register have no effect.

Example: 50 mV tolerance would be saved as 50h.

Offset:

27h

Bit

Description

7:0

Core Voltage Tolerance, High

00h-FFh: mV

158

Datasheet Volume 1 of 2

Features

7.5.3.8

VTL: Core Voltage Tolerance, Low

This location contains the maximum Core Voltage Tolerance DC offset low. This field,

rounded to the next thousandth, is in mV and is reflected in binary coded decimal.

Writes to this register have no effect. A value of FF indicates that this value is

undetermined. Writes to this register have no effect.

Example: 50 mV tolerance would be saved as 50h.

Offset:

28h

Bit

Description

7:0

Core Voltage Tolerance, Low

00h-FFh: mV

7.5.3.9

PDCKS: Processor Core Data Checksum

This location provides the checksum of the Processor Core Data Section. Writes to this

register have no effect.

Offset:

29h

Bit

Description

7:0

Processor Core Data Checksum

One-byte checksum of the Processor Data Section

00h- FFh: See Section 7.5.10 for calculation of this value.

7.5.4

Processor Uncore Data

This section contains silicon-related data relevant to the processor Uncore.

7.5.4.1

MAXQPI: Maximum Intel QPI Transfer Rate

Systems may need to read this offset to decide if all installed processors support the

same Intel QPI Link Transfer Rate. The data provided is the transfer rate, rounded to a

whole number, and reflected in binary coded decimal. Writes to this register have no

effect.

Example: The Intel Xeon Processor E7-8800/4800/2800 Product Families processor

supports a maximum Intel QPI link transfer rate of 6.4 GT/s. Therefore, offset 2Ah-2Bh

has a value of 6400.

Offset:

2Ah-2Bh

Bit

Description

15:0

Maximum Intel QPI Transfer Rate

0000h-FFFFh: MHz

7.5.4.2

MINQPI: Minimum Operating Intel QPI Transfer Rate

Systems may need to read this offset to decide if all installed processors support the

same Intel QPI Link Transfer Rate. This does not relate to the “link power up” transfer

rate of 1/4th Ref Clk. The data provided is the transfer rate, rounded to a whole

number, and reflected in binary coded decimal. Writes to this register have no effect.

Datasheet Volume 1 of 2

159

Features

Example: The Intel Xeon Processor E7-8800/4800/2800 Product Families processor

supports a minimum operating Intel QPI link transfer rate of 4.8 GT/s. Therefore, offset

2Bh-2Ch has a value of 4800.

Offset:

2Ch-2Dh

Bit

Description

15:0

Minimum Intel QPI Transfer Rate

0000h-FFFFh: MHz

7.5.4.3

QPIVN: Intel QPI Version Number

The Intel QPI Version Number is provided as four 8-bit ASCII characters. Writes to this

register have no effect.

Example: The Intel Xeon Processor E7-8800/4800/2800 Product Families processor

supports Intel QPI Version Number 1.0. Therefore, offset 2Eh-31h has an ASCII value

of “01.0”, which is 30, 31, 2E, 30.

Offset:

2Eh-31h

Bit

Description

31:0

Intel QPI Version Number

00000000h-FFFFFFFFh: MHz

7.5.4.4

TXT: TXT

This location contains the TXT location, which is a two-bit field and is LSB aligned. A

value of 00b indicates TXT is not supported. A value of 01b indicates TXT is supported.

Writes to this register have no effect.

Example: A processor supporting TXT will have offset 32h set to 01h.

Offset:

32h

Bit

Description

7:2

RESERVED

000000b-111111b: Reserved

1:0

TXT

TXT support indicator

00b: Not supported

01b: Supported

10b-11b: Reserved

7.5.4.5

MAXSMI: Maximum Intel SMI Transfer Rate

Systems may need to read this offset to decide on compatible processors and Intel

7500 scalable memory buffer capabilities. The data provided is the transfer rate,

rounded to a whole number, and reflected in binary coded decimal. Writes to this

register have no effect.

160

Datasheet Volume 1 of 2

Features

Example: The Intel Xeon Processor E7-8800/4800/2800 Product Families processor

supports a maximum Intel SMI transfer rate of 6.4 GT/s. Therefore, offset 33h-34h has

a value of 6400h.

Offset:

33h-34h

Bit

Description

15:0

Maximum Intel SMI Transfer Rate

0000h-FFFFh: MHz

7.5.4.6

MINSMI: Minimum Intel SMI Transfer Rate

This listing provides the minimum “operating” Intel SMI transfer rate. Systems may

need to read this offset to decide if processors and Intel 7500 scalable memory buffer s

support the same Intel SMI Transfer Rate. The data provided is the transfer rate,

rounded to a whole number, and reflected in binary coded decimal. Writes to this

register have no effect.

Example: The Intel Xeon Processor E7-8800/4800/2800 Product Families processor

supports a minimum operating Intel SMI transfer rate of 4.8 GT/s. Therefore, offset

35h-36h has a hex value of 4800h.

Offset:

35h-36h

Bit

Description

15:0

Minimum Intel SMI Transfer Rate

0000h-FFFFh: MHz

7.5.4.7

VIOVID: VIO VID

Offset 37h-38h is the Processor VIO VID (Voltage Identification) field and contains the

voltage requested via the VID pins. This field, rounded to the next thousandth, is in mV

and is reflected in binary coded decimal. Some systems read this offset to determine if

all processors support the same default VID setting. Writes to this register have no

effect.

Example: A voltage of 1.350 V maximum core VID would contain 1350h in Offset 36-

37h.

Offset:

37h-38h

Bit

Description

15:0

VIO VID

0000h-FFFFh: mV

7.5.4.8

VIOVTH: VIO Voltage Tolerance, High

Offset 39h contains the VIO voltage tolerance, high. This is the maximum voltage

swing above the required voltage allowed. This field, rounded to the next thousandth,

is in mV and is reflected in binary coded decimal. A value of FF indicates that this value

is undetermined. Writes to this register have no effect.

Example: A 50 mV tolerance would be saved as 50h.

Datasheet Volume 1 of 2

161

Features

Offset:

39h

Bit

Description

7:0

VIO Voltage Tolerance, High

00h-FFh: mV

7.5.4.9

VIOVTL: Voltage Tolerance, Low

Offset 3Ah contains the VIO voltage tolerance, low. This is the minimum voltage swing

under the required voltage allowed. This field, rounded to the next thousandth, is in mV

and is reflected in binary coded decimal. A value of FF indicates that this value is

undetermined. Writes to this register have no effect.

Example: A 50 mV tolerance would be saved as 50h.

Offset:

3Ah

Bit

Description

7:0

Core Voltage Tolerance, Low

00h-FFh: mV

7.5.4.10

RES4: Reserved 4

This location is reserved. Writes to this register have no effect.

Offset:

3Bh-3Eh

Bit

Description

31:0

RESERVED

00000000h-FFFFFFFFh: Reserved

7.5.4.11

7.5.4.12

L2SIZE: L2 Cache Size

This location contains the size of the level-two cache in kilobytes. Writes to this register

have no effect. Data format is decimal.

Example: The Intel Xeon Processor E7-8800/4800/2800 Product Families processor

has a 2.5 MB L2 cache. Thus, offset 3Fh-40h will contain a value of 0A00h.

L3SIZE: L3 Cache Size

Offset:

3Fh-40h

Bit

Description

15:0

L2 Cache Size

0000h-FFFFh: KB

This location contains the size of the level-three cache in kilobytes. Writes to this

register have no effect. Data format is decimal.

Example: The Intel Xeon Processor E7-8800/4800/2800 Product Families processor

has up to a 30 MB L3 cache. Thus, offset 41h-42h will contain a value of 8700h.

162

Datasheet Volume 1 of 2

Features

Offset:

41h-42h

Bit

Description

15:0

L3 Cache Size

0000h-FFFFh: KB

7.5.4.13

CVID: Cache Voltage ID

This field contains the voltage requested via the CVID pins. This field is in mV and is

reflected in hex. Some systems read this offset to determine if all processors support

the same default CVID setting. Writes to this register have no effect.

Example: A voltage of 1.350 V CVID would contain an Offset 43-44h value of 1350h.

Offset:

43h-44h

Bit

Description

15:0

Cache Voltage ID

0000h-FFFFh: mV

7.5.4.14

CVTH: Cache Voltage Tolerance, High

This location contains the maximum Cache Voltage Tolerance DC offset high. This field,

rounded to the next thousandth, is in mV and is reflected in binary coded decimal. A

value of FF indicates that this value is undetermined. Writes to this register have no

effect.

Example: A 50 mV tolerance would be saved as 50h.

Offset:

45h

Bit

Description

7:0

Cache Voltage Tolerance, High

00h-FFh: mV

7.5.4.15

CVTL: Cache Voltage Tolerance, Low

This location contains the maximum Cache Voltage Tolerance DC offset low. This field,

rounded to the next thousandth, is in mV and is reflected in binary coded decimal. A

value of FF indicates that this value is undetermined. Writes to this register have no

effect.

Example: A 50 mV tolerance would be saved as 50h.

Offset:

46h

Bit

Description

7:0

Cache Voltage Tolerance, Low

00h-FFh: mV

Datasheet Volume 1 of 2

163

Features

7.5.4.16

RES5: Reserved 5

This location is reserved. Writes to this register have no effect.

Offset:

47h-4Ah

Bit

Description

31:0

RESERVED

00000000h-FFFFFFFFh: Reserved

7.5.4.17

PUDCKS: Processor Uncore Data Checksum

This location provides the checksum of the Processor Uncore Data Section. Writes to

this register have no effect.

Offset:

4Bh

Bit

Description

7:0

Processor Uncore Data Checksum

One-byte checksum of the Processor Uncore Data Section

00h- FFh: See Section 7.5.10 for calculation of this value.

7.5.5

Package Data

This section contains substrate and other package related data.

7.5.5.1

PREV: Package Revision

This location tracks the highest level package revision. It is provided in an ASCII format

of four characters (8 bits x 4 characters = 32 bits). The package is documented as 1.0,

2.0, etc. If only three ASCII characters are consumed, a leading space is provided in

the data field. Writes to this register have no effect.

Example: The Intel Xeon Processor E7-8800/4800/2800 Product Families processor

utilizes the first revision of the LGA-1567 package. Thus, at offset 4C-4F-35h, the data

is a space followed by 1.0. In hex, this would be 20h, 31h, 2Eh, 30h.

Offset:

4Ch-4Fh

Bit

Description

31:24

Character 4

ASCII character or 20h

00h-0FFh: ASCII character

23:16

15:8

7:0

Character 3

ASCII character

00h-0FFh: ASCII character

Character 2

ASCII character

00h-0FFh: ASCII character

Character 1

ASCII character

00h-0FFh: ASCII character

164

Datasheet Volume 1 of 2

Features

7.5.5.2

Substrate Revision Software ID

This location is a place holder for the Substrate Revision Software ID. Writes to this

register have no effect.

Offset:

50h

Bit

Description

7:0

Substrate Revision Software ID

00h-FFh: Reserved

7.5.5.3

RES6: Reserved 6

This location is reserved. Writes to this register have no effect.

Offset:

51h-52h

Bit

Description

15:0

RESERVED

0000h-FFFFh: Reserved

7.5.5.4

PDCKS: Package Data Checksum

This location provides the checksum of the Package Data Section. Writes to this register

have no effect.

Offset:

53h

Bit

Description

7:0

Package Data Checksum

One-byte checksum of the Package Data Section

00h- FFh: See Section 7.5.10 for calculation of this value.

7.5.6

Part Number Data

This section provides device traceability.

7.5.6.1

PFN: Processor Family Number

This location contains seven ASCII characters reflecting the Intel® family number for

the processor. This number is the same on all Intel Xeon Processor E7-8800/4800/2800

Product Families processors. Combined with the Processor SKU Number below, this is

the complete processor part number. This information is typically marked on the

outside of the processor. If the part number is less than 15 total characters, a leading

space is inserted into the value. The part number should match the information found

in the marking specification found in Chapter 3. Writes to this register have no effect.

Example: A processor with a part number of AT80604******** will have the following

data found at offset 38-3Eh: 41h, 54h, 38h, 30h, 36h, 30h, 34h.

Datasheet Volume 1 of 2

165

Features

Offset:

54h-5Ah

Bit

Description

55:48

Character 7

ASCII character or 20h

00h-0FFh: ASCII character

47:40

39:32

31:24

23:16

15:8

Character 6

ASCII character or 20h

00h-0FFh: ASCII character

Character 5

ASCII character or 20h

00h-0FFh: ASCII character

Character 4

ASCII character

00h-0FFh: ASCII character

Character 3

ASCII character

00h-0FFh: ASCII character

Character 2

ASCII character

00h-0FFh: ASCII character

7:0

Character 1

ASCII character

00h-0FFh: ASCII character

7.5.6.2

PSN: Processor SKU Number

This location contains eight ASCII characters reflecting the Intel® SKU number for the

processor. Added to the end of the Processor Family Number above, this is the

complete processor part number. This information is typically marked on the outside of

the processor. If the part number is less than 15 total characters, a leading space is

inserted into the value. The part number should match the information found in the

marking specification found in Chapter 3. Writes to this register have no effect.

Example: A processor with a part number of *******003771AA will have the following

data found at offset 58-62h: 30h, 30h, 33h, 37h, 37h, 31h, 41h, 41h.

166

Datasheet Volume 1 of 2

Features

Offset:

5Bh=62h

Bit

Description

63:56

Character 8

00h-0FFh: ASCII character

55:48

47:40

39:32

31:24

23:16

15:8

Character 7

ASCII character or 20h

00h-0FFh: ASCII character

Character 6

ASCII character or 20h

00h-0FFh: ASCII character

Character 5

ASCII character or 20h

00h-0FFh: ASCII character

Character 4

ASCII character

00h-0FFh: ASCII character

Character 3

ASCII character

00h-0FFh: ASCII character

Character 2

ASCII character

00h-0FFh: ASCII character

7:0

Character 1

ASCII character

00h-0FFh: ASCII character

7.5.6.3

RES7: Reserved 7

This location is reserved. Writes to this register have no effect.

Offset:

63h-64h

Bit

Description

15:0

RESERVED

0000h-FFFFh: Reserved

7.5.6.4

PNDCKS: Part Number Data Checksum

This location provides the checksum of the Part Number Data Section. Writes to this

register have no effect.

Offset:

65h

Bit

Description

7:0

Part Number Data Checksum

One-byte checksum of the Part Number Data Checksum

00h- FFh: See Section 7.5.10 for calculation of this value.

Datasheet Volume 1 of 2

167

Features

7.5.7

Thermal Reference Data

7.5.7.1

TUT: Thermalert Upper Threshold

This location is a place holder for the Thermalert Upper Threshold Byte. Writes to this

register have no effect.

Offset:

66h

Bit

Description

7:0

Thermalert Upper Threshold

0000h-FFFFh: Reserved

7.5.7.2

TCO: Thermal Calibration Offset

This location is a place holder for the Thermal Calibration Offset Byte. Writes to this

register have no effect.

Offset:

67h

Bit

Description

7:0

Thermal Calibration Offset

0000h-FFFFh: Reserved

7.5.7.3

TCASE: T

Maximum

CASE

This location provides the maximum T_CASEfor the processor. The field reflects

temperature in degrees Celsius in binary coded decimal format. This data can be found

in Chapter 6. The thermal specifications are specified at the case Integrated Heat

Spreader (IHS). Writes to this register have no effect.

Example: A temperature of 66°C would contain a value of 66h.

Offset:

68h

Bit

Description

7:0

T

Maximum

CASE

00h-FFh: Degrees Celsius

7.5.7.4

TDP: Thermal Design Power

This location contains the maximum Thermal Design Power for the part. The field

reflects power in watts in binary coded decimal format. Writes to this register have no

effect. A zero value means that the value was not programmed.

Example: A 130W TDP would be saved as 0130h.

Offset:

69h-6Ah

Bit

Description

15:0

Thermal Design Power

0000h-FFFFh: Watts

168

Datasheet Volume 1 of 2

Features

7.5.7.5

TRDCKS: Thermal Reference Data Checksum

This location provides the checksum of the Thermal Reference Data Section. Writes to

this register have no effect.

Offset:

6Bh

Bit

Description

7:0

Thermal Reference Data Checksum

One-byte checksum of the of Thermal Reference Data Checksum

00h- FFh: See Section 7.5.10 for calculation of this value.

7.5.8

Feature Data

This section provides information on key features that the platform may need to

understand without powering on the processor.

7.5.8.1

PCFF: Processor Core Feature Flags

This location contains a copy of results in EDX[31:0] from Function 1 of the CPUID

instruction. These details provide instruction and feature support by product family.

Writes to this register have no effect.

Example: A value of BFEBFBFFh can be found at offset 6C - 6Fh.

Offset:

6Ch-6Fh

Bit

Description

31:0

Processor Core Feature Flags

00000000h-FFFFFFFFF: Feature Flags

7.5.8.2

PFF: Processor Feature Flags

This location contains additional feature information from the processor. Writes to this

register have no effect.

Note:

Bit 5 and Bit 6 are mutually exclusive (only one bit will be set).

Offset:

Bit

70h

Description

7

6

5

4

3

2

1

0

Multi-Core (set if the processor is a multi-core processor)

Serial signature (set if there is a serial signature at offset 5B- 62h)

Electronic signature present (set if there is a electronic signature at 5B- 62h)

Thermal Sense Device present (set if an SMBus thermal sensor is on package)

Reserved

OEM EEPROM present (set if there is a scratch ROM at offset 80 - FFh)

Core VID present (set if there is a VID provided by the processor)

L3 Cache present (set if there is a level-3 cache on the processor)

Bits are set when a feature is present, and cleared when they are not.

Datasheet Volume 1 of 2

169

Features

7.5.8.3

APFF: Additional Processor Feature Flags

This location contains additional feature information from the processor. Writes to this

register have no effect.

Offset:

Bit

71h

Description

7

6

5

4

3

2

1

0

Reserved

Intel® Cache Safe Technology

Extended Halt State (C1E)

Intel® Virtualization Technology

Execute Disable

®

Intel 64

®

Intel Thermal Monitor 2

®

Enhanced Intel SpeedStep Technology

Bits are set when a feature is present, and cleared when they are not.

7.5.8.4

MPSUP: Multiprocessor Support

This location contains 2 bits for representing the supported number of physical

processors on the bus. These two bits are LSB aligned where 00b equates to non-

scalable 2 socket (2S) operation, 01b to scalable 2 socket (S2S), 10 to scalable 4

socket (S4S), and scalable 8 socket (S8S). Intel Xeon Processor E7-8800/4800/2800

Product Families processor is a S2S, S4S, or S8S processor. The first six bits in this field

are reserved for future use. Writes to this register have no effect.

Example: A scalable 8 socket processor will have a value of 03h at offset 71h.

Offset:

72h

Bit

Description

7:2

RESERVED

000000b-111111b: Reserved

1:0

Multiprocessor Support

2S, S2S, S4S or S8S indicator

00b: Non-Scalable 2 Socket

01b: Scalable 2 Socket

10b: Scalable 4 Socket

11b: Scalable 8 Socket

7.5.8.5

TCDC: Tap Chain Device Count

At offset 73, a 4-bit hex digit is used to tell how many devices are in the TAP Chain.

Because the Intel Xeon Processor E7-8800/4800/2800 Product Families processor has

ten cores, this field would be set to Ah.

170

Datasheet Volume 1 of 2

Features

Offset:

73h

Bit

Description

7:0

TAP Chain Device Count

0000h-FFFFh: Reserved

7.5.8.6

RES9: Reserved 9

This location is reserved. Writes to this register have no effect.

Offset:

74h-75h

Bit

Description

15:0

RESERVED

0000h-FFFFh: Reserved

7.5.8.7

TRDCKS: Thermal Reference Data Checksum

This location provides the checksum of the Thermal Reference Data Section. Writes to

this register have no effect.

Offset:

76h

Bit

Description

7:0

Thermal Reference Data Checksum

One-byte checksum of the Thermal Reference Data Checksum

00h- FFh: See Section 7.5.10 for calculation of this value.

7.5.9

Other Data

This section contains a large reserved area, and items added after the original format

for the Intel Xeon Processor E7-8800/4800/2800 Product Families processor PIROM

was set.

7.5.9.1

PS/ESIG: Processor Serial/Electronic Signature

This location contains a 64-bit identification number. The value in this field is either a

serial signature or an electronic signature. Writes to this register have no effect.

Offset:

77h-7Eh

Bit

Description

63:0

Processor Serial/Electronic Signature

0000000000000000h-FFFFFFFFFFFFFFFFh: Electronic Signature

Datasheet Volume 1 of 2

171

Features

7.5.9.2

ODCKS: Other Data Checksum

This location provides the checksum for the Other Data Section. Writes to this register

have no effect.

Offset:

7Fh

Bit

Description

7:0

Other Data Checksum

One-byte checksum of the Other Data Checksum

00h- FFh: See Section 7.5.10 for calculation of this value.

7.5.10

Checksums

The PIROM includes multiple checksums. Table 7-5 includes the checksum values for

each section defined in the 128-byte ROM.

Table 7-5.

128-Byte ROM Checksum Values

Section

Checksum Address

Header

0Dh

1Ah

29h

4Bh

53h

65h

76h

7Fh

Processor Data

Processor Core Data

Processor Uncore Data

Package Data

Part Number Data

Feature Data

Other Data

Checksums are automatically calculated and programmed by Intel®. The first step in

calculating the checksum is to add each byte from the field to the next subsequent

byte. This result is then negated to provide the checksum.

Example: For a byte string of AA445Ch, the resulting checksum will be B6h.

AA = 10101010

44 = 01000100

5C = 0101100

AA + 44 + 5C = 01001010

Negate the sum: 10110101 +1 = 101101 (B6h)

§

172

Datasheet Volume 1 of 2

Debug Tools Specifications

8 Debug Tools Specifications

For debug purposes, the socket LS pin definition has allocated signals to install a logic

analyzer probe head to observe Intel QPI traffic.

8.1

Logic Analyzer Interface

Due to the complexity of Intel Xeon Processor E7-8800/4800/2800 Product Families

processor-based multiprocessor systems, the Logic Analyzer Interface (LAI) is critical in

providing the ability to probe and capture high-speed signals. There are two sets of

considerations to keep in mind when designing a Intel Xeon Processor E7-8800/4800/

2800 Product Families processor-based system that can make use of an LAI:

mechanical and electrical.

8.1.1

Mechanical Considerations

The LAI is installed between the processor socket and the processor. The LAI pins plug

into the socket, while the processor pins plug into a socket on the LAI. Cabling that is

part of the LAI egresses the system to allow an electrical connection between the

processor and a logic analyzer. The maximum volume occupied by the LAI, known as

the keepout volume, as well as the cable egress restrictions, should be obtained from

the logic analyzer vendor. System designers must make sure that the keepout volume

remains unobstructed inside the system. Note that it is possible that the keepout

volume reserved for the LAI may differ from the space normally occupied by the Intel

Xeon Processor E7-8800/4800/2800 Product Families processor heatsink. If this is the

case, the logic analyzer vendor will provide a cooling solution as part of the LAI.

8.1.2

Electrical Considerations

Instrumented Intel QPI links will require equalization settings unique for that topology.

The platform will need to load updated optimized equalization settings for instrumented

links. The method of obtaining the new set of E.Q settings is via the Signal Integrity

Support Tools for Advanced Interfaces (SISTAI) tools, following the same procedures.

§

Datasheet Volume 1 of 2

173

Debug Tools Specifications

174

Datasheet Volume 1 of 2


型号：	325119-001
厂家：	INTEL
描述：	IntelÂ® XeonÂ® Processor E7-8800/4800/2800 Product Families 英特尔® XeonÂ®处理器E7-8800 / 2800分之4800产品系列
文件：	总174页 (文件大小：3951K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

325119-001 [INTEL]

相关型号：

325123M025JS0E

325123T016JL0E

325123T016JL1

325123T025JS1

325123T6R3HJ0

325123T6R3HJ0E

325123U016JL1

325123U025JS1

325123U6R3HJ1

32512MHXP

32512MMXP

325132M025GE0E