313064 [INTEL]
Dual-Core Intel Xeon Processor; 双核英特尔®至强®处理器
| 型号： | 313064 |
| 厂家： | 
INTEL |
| 描述： | Dual-Core Intel Xeon Processor |
| 文件： | 总104页 (文件大小：3687K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual-Core Intel® Xeon®
Processor 5000 Series
Datasheet
May 2006
Document Number: 313079-001
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED,
BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS
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AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING
LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY
PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or
life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future
changes to them.
The Dual-Core Intel® Xeon® Processor 5000 Series may contain design defects or errors known as errata which may cause the
product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Intel, Pentium, Intel Xeon, Intel SpeedStep, Intel NetBurst, Intel Architecture, Intel Virtualization Technology, and the Intel logo
are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2004-2006, Intel Corporation.
2
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Contents
1
Introduction.................................................................................................................9
1.1
1.2
1.3
Terminology ..................................................................................................... 11
State of Data.................................................................................................... 12
References ....................................................................................................... 12
2
Electrical Specifications ............................................................................................... 15
2.1
2.2
2.3
Front Side Bus and GTLREF ................................................................................ 15
Power and Ground Lands.................................................................................... 15
Decoupling Guidelines........................................................................................ 16
2.3.1 VCC Decoupling...................................................................................... 16
2.3.2 VTT Decoupling...................................................................................... 16
2.3.3 Front Side Bus AGTL+ Decoupling ............................................................ 16
Front Side Bus Clock (BCLK[1:0]) and Processor Clocking....................................... 16
2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0]).................................. 17
2.4.2 Phase Lock Loop (PLL) and Filter .............................................................. 18
Voltage Identification (VID) ................................................................................ 19
Reserved or Unused Signals................................................................................ 21
Front Side Bus Signal Groups.............................................................................. 21
GTL+ Asynchronous and AGTL+ Asynchronous Signals........................................... 23
Test Access Port (TAP) Connection....................................................................... 23
2.4
2.5
2.6
2.7
2.8
2.9
2.10 Mixing Processors.............................................................................................. 24
2.11 Absolute Maximum and Minimum Ratings ............................................................. 24
2.12 Processor DC Specifications ................................................................................ 25
2.12.1 VCC Overshoot Specification.................................................................... 31
2.12.2 Die Voltage Validation............................................................................. 32
3
Mechanical Specifications............................................................................................. 33
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
Package Mechanical Drawings ............................................................................. 33
Processor Component Keepout Zones................................................................... 37
Package Loading Specifications ........................................................................... 37
Package Handling Guidelines............................................................................... 38
Package Insertion Specifications.......................................................................... 38
Processor Mass Specifications ............................................................................. 38
Processor Materials............................................................................................ 38
Processor Markings............................................................................................ 39
Processor Land Coordinates................................................................................ 40
4
Land Listing............................................................................................................... 43
4.1
Dual-Core Intel Xeon Processor 5000 Series Land Assignments ............................... 43
4.1.1 Land Listing by Land Name...................................................................... 43
4.1.2 Land Listing by Land Number................................................................... 52
5
6
Signal Definitions ...................................................................................................... 61
5.1 Signal Definitions .............................................................................................. 61
Thermal Specifications ................................................................................................ 69
6.1
Package Thermal Specifications........................................................................... 69
6.1.1 Thermal Specifications ............................................................................ 69
6.1.2 Thermal Metrology ................................................................................. 75
Processor Thermal Features................................................................................ 77
6.2.1 Thermal Monitor..................................................................................... 77
6.2.2 On-Demand Mode .................................................................................. 77
6.2.3 PROCHOT# Signal.................................................................................. 78
6.2.4 FORCEPR# Signal................................................................................... 78
6.2.5 THERMTRIP# Signal ............................................................................... 78
6.2
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
3
6.2.6 Tcontrol and Fan Speed Reduction ............................................................79
6.2.7 Thermal Diode........................................................................................79
7
Features....................................................................................................................83
7.1
7.2
Power-On Configuration Options ..........................................................................83
Clock Control and Low Power States.....................................................................83
7.2.1 Normal State .........................................................................................84
7.2.2 HALT or Enhanced Powerdown States........................................................84
7.2.3 Stop-Grant State ....................................................................................85
7.2.4 Enhanced HALT Snoop or HALT Snoop State,
Stop Grant Snoop State...........................................................................86
Enhanced Intel SpeedStep® Technology...............................................................86
7.3
8
Boxed Processor Specifications .....................................................................................89
8.1
8.2
Introduction......................................................................................................89
Mechanical Specifications....................................................................................90
8.2.1 Boxed Processor Heat Sink Dimensions (CEK).............................................91
8.2.2 Boxed Processor Heat Sink Weight............................................................99
8.2.3 Boxed Processor Retention Mechanism and
Heat Sink Support (CEK) .........................................................................99
Electrical Requirements ......................................................................................99
8.3.1 Fan Power Supply (Active CEK).................................................................99
8.3.2 Boxed Processor Cooling Requirements....................................................100
Boxed Processor Contents.................................................................................101
8.3
8.4
9
Debug Tools Specifications.........................................................................................103
9.1
9.2
Debug Port System Requirements......................................................................103
Target System Implementation..........................................................................103
9.2.1 System Implementation.........................................................................103
Logic Analyzer Interface (LAI) ..........................................................................103
9.3.1 Mechanical Considerations .....................................................................104
9.3.2 Electrical Considerations........................................................................104
9.3
Figures
2-1
2-2
Phase Lock Loop (PLL) Filter Requirements............................................................18
Dual-Core Intel® Xeon® Processor 5000 Series (1066 MHz)
Load Current versus Time...................................................................................27
2-3
Dual-Core Intel® Xeon® Processor 5000 Series (667 MHz) and
Dual-Core Intel® Xeon® Processor 5063 (MV) Load Current versus Time..................28
VCC Static and Transient Tolerance Load Lines ......................................................29
VCC Overshoot Example Waveform......................................................................32
Processor Package Assembly Sketch.....................................................................33
Processor Package Drawing (Sheet 1 of 3) ............................................................34
Processor Package Drawing (Sheet 2 of 3) ............................................................35
Processor Package Drawing (Sheet 3 of 3) ............................................................36
Dual-Core Intel Xeon Processor 5000 Series Top-side Markings................................39
Dual-Core Intel Xeon Processor 5063 (MV) Top-side Markings..................................39
Processor Land Coordinates, Top View..................................................................40
Processor Land Coordinates, Bottom View.............................................................41
Dual-Core Intel Xeon Processor 5000 Series (1066 MHz)
2-4
2-5
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
6-1
Thermal Profiles A and B.....................................................................................71
Dual-Core Intel Xeon Processor 5000 Series (667 MHz) Thermal Profiles ...................73
Dual-Core Intel Xeon Processor 5063 (MV) Thermal Profile......................................75
Case Temperature (TCASE) Measurement Location.................................................76
Stop Clock State Machine....................................................................................85
6-2
6-3
6-4
7-1
4
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
8-1
Boxed Dual-Core Intel Xeon Processor 5000 Series 1U
Passive/2U Active Combination Heat Sink (With Removable Fan) ............................. 89
Boxed Dual-Core Intel Xeon Processor 5000 Series 2U Passive Heat Sink.................. 90
2U Passive Dual-Core Intel Xeon Processor 5000 Series
8-2
8-3
Thermal Solution (Exploded View) ....................................................................... 90
Top Side Board Keep-Out Zones (Part 1) .............................................................. 92
Top Side Board Keep-Out Zones (Part 2) .............................................................. 93
Bottom Side Board Keep-Out Zones..................................................................... 94
Board Mounting Hole Keep-Out Zones.................................................................. 95
Volumetric Height Keep-Ins ................................................................................ 96
4-Pin Fan Cable Connector (For Active CEK Heat Sink) ........................................... 97
8-4
8-5
8-6
8-7
8-8
8-9
8-10 4-Pin Base Board Fan Header (For Active CEK Heat Sink)........................................ 98
8-11 Fan Cable Connector Pin Out for 4-Pin Active CEK Thermal Solution ....................... 100
Tables
1-1
Dual-Core Intel® Xeon® Processor 5000 Series Features ....................................... 10
Core Frequency to FSB Multiplier Configuration ..................................................... 17
BSEL[2:0] Frequency Table ................................................................................ 17
Voltage Identification Definition........................................................................... 19
Loadline Selection Truth Table for LL_ID[1:0] ....................................................... 20
Market Segment Selection Truth Table for MS_ID[1:0]........................................... 20
FSB Signal Groups............................................................................................. 22
Signal Description Table..................................................................................... 23
Signal Reference Voltages .................................................................................. 23
Processor Absolute Maximum Ratings................................................................... 24
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10 Voltage and Current Specifications....................................................................... 25
2-11 VCC Static and Transient Tolerance ..................................................................... 28
2-12 BSEL[2:0], VID[5:0] Signal Group DC Specifications.............................................. 30
2-13 AGTL+ Signal Group DC Specifications ................................................................. 30
2-14 PWRGOOD Input and TAP Signal Group DC Specifications ....................................... 30
2-15 GTL+ Asynchronous and AGTL+ Asynchronous Signal Group
DC Specifications .............................................................................................. 31
2-16 VTTPWRGD DC Specifications.............................................................................. 31
2-17 VCC Overshoot Specifications.............................................................................. 32
3-1
3-2
3-3
4-1
4-2
5-1
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
Package Loading Specifications ........................................................................... 37
Package Handling Guidelines............................................................................... 38
Processor Materials............................................................................................ 38
Land Listing by Land Name................................................................................. 43
Land Listing by Land Number.............................................................................. 52
Signal Definitions .............................................................................................. 61
Dual-Core Intel Xeon Processor 5000 Series (1066 MHz) Thermal Specifications ........ 70
Dual-Core Intel Xeon Processor 5000 Series (1066 MHz) Thermal Profile A Table ....... 71
Dual-Core Intel Xeon Processor 5000 Series (1066 MHz) Thermal Profile B Table ....... 72
Dual-Core Intel Xeon Processor 5000 Series (667 MHz) Thermal Specifications.......... 72
Dual-Core Intel Xeon Processor 5000 Series (667 MHz) Thermal Profile A Table......... 73
Dual-Core Intel Xeon 5000 Series (667 MHz) Thermal Profile B Table ....................... 74
Dual-Core Intel Xeon Processor 5063 (MV) Thermal Specifications ........................... 74
Dual-Core Intel Xeon Processor 5063 (MV) Thermal Profile Table............................. 75
Thermal Diode Parameters using Diode Model ....................................................... 80
6-10 Thermal Diode Interface..................................................................................... 81
6-11 Thermal Diode Parameters using Transistor Model ................................................. 81
6-12 Parameters for Tdiode Correction Factor............................................................... 81
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
5
7-1
8-1
8-2
8-3
Power-On Configuration Option Lands...................................................................83
PWM Fan Frequency Specifications for 4-Pin Active CEK Thermal Solution................100
Fan Specifications for 4-pin Active CEK Thermal Solution.......................................100
Fan Cable Connector Pin Out for 4-Pin Active CEK Thermal Solution........................100
6
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Revision History
Revision
Description
Date
001
Initial release
May 2006
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
7
Features
Dual-Core processor
Available at 3.73 GHz processor speed
Includes 16-KB Level 1 data cache per core (2 x 16-KB)
Includes 12-KB Level 1 trace cache per core (2 x 12-KB)
2-MB Advanced Transfer Cache per core (2 x 2-MB, On-die, full speed Level 2 (L2) Cache) with 8-
way associativity and Error Correcting Code (ECC)
667/1066 MHz front side bus
65 nm process technology
Dual processing (DP) server support
Intel® NetBurst® microarchitecture
Hyper-Threading Technology allowing up to 8 threads per platform
Hardware support for multi-threaded applications
Intel® Virtualization Technology
Intel® Extended Memory 64 Technology (Intel® EM64T)
Execute Disable Bit (XD Bit)
Enables system support of up to 64 GB of physical memory
Enhanced branch prediction
Enhanced floating-point and multimedia unit for enhanced video, audio, encryption, and 3D
performance
Advanced Dynamic Execution
Very deep out-of-order execution
System Management mode
Machine Check Architecture (MCA)
Interfaces to Memory Controller Hub
The Dual-Core Intel Xeon Processor 5000 series are designed for high-performance dual-processor
server and workstation applications. Based on the Intel NetBurst® microarchitecture and Hyper-
Threading Technology (HT Technology), it is binary compatible with previous Intel® Architecture
(IA-32) processors. The Dual-Core Intel Xeon Processor 5000 series are scalable to two processors in
a multiprocessor system, providing exceptional performance for applications running on advanced
operating systems such as Windows* XP, Windows Server 2003, Linux*, and UNIX*.
The Dual-Core Intel Xeon Processor 5000 series deliver compute power at unparalleled value and
flexibility for powerful servers, internet infrastructure, and departmental server applications. The Intel
NetBurst micro-architecture, Intel Virtualization Technology and Hyper-Threading Technology deliver
outstanding performance and headroom for peak internet server workloads, resulting in faster
response times, support for more users, and improved scalability.
§
8
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Introduction
1 Introduction
The Dual-Core Intel® Xeon® Processor 5000 series are Intel dual core products for dual
processor (DP) servers and workstations. The Dual-Core Intel Xeon Processor 5000
series are 64-bit server/workstation processors utilizing two physical Intel NetBurst®
microarchitecture cores in one package. The Dual-Core Intel Xeon Processor 5000
series include enhancements to the Intel NetBurst microarchitecture while maintaining
the tradition of compatibility with IA-32 software. Some key features include Hyper
Pipelined Technology and an Execution Trace Cache. Hyper Pipelined Technology
includes a multi-stage pipeline depth, allowing the processor to reach higher core
frequencies. The Dual-Core Intel Xeon Processor 5000 series contain a total of 4 MB of
L2 Advanced Transfer Cache, 2 MB per core. The 1066 MHz Front Side Bus (FSB) is a
quad-pumped bus running off a 266 MHz system clock making 8.5 GBytes per second
data transfer rates possible. The 667 MHz Front Side Bus (FSB) is a quad-pumped bus
running off a 166 MHz system clock making 5.3 GBytes per second data transfer rates
possible.
In addition, enhanced thermal and power management capabilities are implemented
including Thermal Monitor (TM1) and Enhanced Intel SpeedStep® technology. These
technologies are targeted for dual processor (DP) systems in enterprise environments.
TM1 provides efficient and effective cooling in high temperature situations. Enhanced
Intel SpeedStep technology provides power management capabilities to servers and
workstations.
The Dual-Core Intel Xeon Processor 5000 series also include Hyper-Threading
Technology (HT Technology) resulting in four logical processors per package. This
feature allows multi-threaded applications to execute more than one thread per
physical processor core, increasing the throughput of applications and enabling
improved scaling for server and workstation workloads. More information on Hyper-
Threading Technology can be found at http://www.intel.com/technology/hyperthread.
Other features within the Intel NetBurst microarchitecture include Advanced Dynamic
Execution, Advanced Transfer Cache, enhanced floating point and multi-media units,
and Streaming SIMD Extensions 3 (SSE3). Advanced Dynamic Execution improves
speculative execution and branch prediction internal to the processor. The Advanced
Transfer Cache in each core is a 2 MB level 2 (L2) cache. The floating point and multi-
media units include 128-bit wide registers and a separate register for data movement.
Streaming SIMD3 (SSE3) instructions provide highly efficient double-precision floating
point, SIMD integer, and memory management operations. Other processor
enhancements include core frequency improvements and microarchitectural
improvements.
The Dual-Core Intel Xeon Processor 5000 series support Intel® Extended Memory 64
Technology (Intel® EM64T) as an enhancement to Intel's IA-32 architecture. This
enhancement allows the processor to execute operating systems and applications
written to take advantage of the 64-bit extension technology. Further details on Intel
Extended Memory 64 Technology and its programming model can be found in the
64-bit Extension Technology Software Developer's Guide at http://developer.intel.com/
technology/64bitextensions/.
In addition, the Dual-Core Intel Xeon Processor 5000 series support the Execute
Disable Bit functionality. When used in conjunction with a supporting operating system,
Execute Disable allows memory to be marked as executable or non executable. This
feature can prevent some classes of viruses that exploit buffer overrun vulnerabilities
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
9
Introduction
and can thus help improve the overall security of the system. For further information on
Execute Disable Bit functionality see http://www.intel.com/cd/ids/developer/asmo-na/
eng/149308.htm.
The Dual-Core Intel Xeon Processor 5000 series support Intel® Virtualization
Technology, virtualization within the processor. Intel Virtualization Technology is a set of
hardware enhancements that can improve virtualization solutions. Intel Virtualization
Technology is used in conjunction with Virtual Machine Monitor software enabling
multiple, independent software environments inside a single platform. More
information on Intel Virtualization Technology can be found at http://www.intel.com/
technology/computing/vptech/index.htm.
The Dual-Core Intel Xeon Processor 5000 series are intended for high performance
workstation and server systems. The Dual-Core Intel Xeon Processor 5063 is a lower
power version of the Dual-Core Intel Xeon Processor 5000 series. The Dual-Core Intel
Xeon Processor 5000 series support a new Dual Independent Bus (DIB) architecture
with one processor socket on each bus, up to two processor sockets in a system. The
DIB architecture provides improved performance by allowing increased FSB speeds and
bandwidth. The Dual-Core Intel Xeon Processor 5000 series will be packaged in an FC-
LGA6 Land Grid Array package with 771 lands for improved power delivery. It utilizes a
surface mount LGA771 socket that supports Direct Socket Loading (DSL).
Table 1-1.
Dual-Core Intel® Xeon® Processor 5000 Series Features
# Cores Per
Package
L2 Advanced
Transfer Cache
Hyper-Threading
Technology
Front Side Bus
Frequency
Package
1
2
2 MB per core
4 MB total
Yes
667 MHz
1066 MHz
FC-LGA6
771 Lands
Notes:
1. Total accessible size of L2 caches may vary by one cache line pair (128 bytes) per core, depending on usage
and operating environment.
The Dual-Core Intel Xeon Processor 5000 series-based platforms implement
independent core voltage (VCC) power planes for each processor. FSB termination
voltage (VTT) is shared and must connect to all FSB agents. The processor core voltage
utilizes power delivery guidelines specified by VRM/EVRD 11.0 and its associated load
line. Refer to the appropriate platform design guidelines for implementation details.
The Dual-Core Intel Xeon Processor 5000 series support a 1066/667 MHz Front Side
Bus frequency. The FSB utilizes a split-transaction, deferred reply protocol and Source-
Synchronous Transfer (SST) of address and data to improve performance. The
processor transfers data four times per bus clock (4X data transfer rate, as in AGP 4X).
Along with the 4X data bus, the address bus can deliver addresses two times per bus
clock and is referred to as a ‘double-clocked’ or a 2X address bus. In addition, the
Request Phase completes in one clock cycle. Working together, the 4X data bus and 2X
address bus provide a data bus bandwidth of up to 8.5 GBytes/second. (5.3 GBytes/
second for Dual-Core Intel Xeon Processor 5000 series 667) Finally, the FSB is also
used to deliver interrupts.
Signals on the FSB use Assisted Gunning Transceiver Logic (AGTL+) level voltages.
Section 2.1 contains the electrical specifications of the FSB while implementation
details are fully described in the appropriate platform design guidelines (refer to
Section 1.3).
10
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Introduction
1.1
Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in
the asserted state when driven to a low level. For example, when RESET# is low, a
reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has
occurred. In the case of signals where the name does not imply an active state but
describes part of a binary sequence (such as address or data), the ‘#’ symbol implies
that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and
D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).
Commonly used terms are explained here for clarification:
• Dual-Core Intel® Xeon® Processor 5000 Series – Processor in the FC-LGA6
package with two physical processor cores. Dual-Core Intel Xeon processor 5000
series refers to the “Full Power” Dual-Core Intel Xeon Processor 5000 series with
1066 MHz Front Side Bus. For this document, “processor” is used as the generic
term for the “Dual-Core Intel® Xeon® Processor 5000 series”.
• Dual-Core Intel® Xeon® Processor 5063 (MV) – This is a lower power version
of the Dual-Core Intel Xeon Processor 5000 series. Dual-Core Intel Xeon Processor
5063 (MV) refers to the “Mid Power” Dual-Core Intel Xeon Processor 5000 series.
Unless otherwise noted, the terms “Dual-Core Intel Xeon 5000 series” and
“processor” also refer to the “Dual-Core Intel Xeon Processor 5063”.
• FC-LGA6 (Flip Chip Land Grid Array) Package – The Dual-Core Intel Xeon
Processor 5000 series package is a Land Grid Array, consisting of a processor core
mounted on a pinless substrate with 771 lands, and includes an integrated heat
spreader (IHS).
• FSB (Front Side Bus) – The electrical interface that connects the processor to the
chipset. Also referred to as the processor front side bus or the front side bus. All
memory and I/O transactions as well as interrupt messages pass between the
processor and chipset over the FSB.
• Functional Operation – Refers to the normal operating conditions in which all
processor specifications, including DC, AC, FSB, signal quality, mechanical and
thermal are satisfied.
• Storage Conditions – Refers to a non-operational state. The processor may be
installed in a platform, in a tray, or loose. Processors may be sealed in packaging or
exposed to free air. Under these conditions, processor lands should not be
connected to any supply voltages, have any I/Os biased or receive any clocks.
Upon exposure to “free air” (that is, unsealed packaging or a device removed from
packaging material) the processor must be handled in accordance with moisture
sensitivity labeling (MSL) as indicated on the packaging material.
• Priority Agent – The priority agent is the host bridge to the processor and is
typically known as the chipset.
• Symmetric Agent – A symmetric agent is a processor which shares the same I/O
subsystem and memory array, and runs the same operating system as another
processor in a system. Systems using symmetric agents are known as Symmetric
Multiprocessing (SMP) systems.
• Integrated Heat Spreader (IHS) – A component of the processor package used
to enhance the thermal performance of the package. Component thermal solutions
interface with the processor at the IHS surface.
• Enhanced Intel SpeedStep Technology – The next generation implementation
of Intel SpeedStep technology which extends power management capabilities of
servers and workstations.
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
11
Introduction
• Thermal Design Power – Processor thermal solutions should be designed to meet
this target. It is the highest expected sustainable power while running known
power intensive real applications. TDP is not the maximum power that the
processor can dissipate.
• LGA771 socket – The Dual-Core Intel Xeon Processor 5000 series interfaces to
the baseboard through this surface mount, 771 Land socket. See the LGA771
Socket Design Guidelines for details regarding this socket.
• Processor – A single package that contains one or more complete execution cores.
• Processor core – Processor core die with integrated L2 cache. All AC timing and
signal integrity specifications are at the pads of the processor core.
• Intel® Virtualization Technology – Processor virtualization which when used in
conjunction with Virtual Machine Monitor software enables multiple, robust
independent software environments inside a single platform.
• VRM (Voltage Regulator Module) – DC-DC converter built onto a module that
interfaces with a card edge socket and supplies the correct voltage and current to
the processor based on the logic state of the processor VID bits.
• EVRD (Enterprise Voltage Regulator Down) – DC-DC converter integrated onto
the system board that provides the correct voltage and current to the processor
based on the logic state of the processor VID bits.
• VCC – The processor core power supply.
• VSS – The processor ground.
• VTT – FSB termination voltage.
1.2
1.3
State of Data
The data contained within this document is subject to change. It is the most accurate
information available by the publication date of this document and is based on final
silicon characterization. All specifications in this version of the Dual-Core Intel® Xeon®
Processor 5000 Series Datasheet can be used for platform design purposes (layout
studies, characterizing thermal capabilities, and so forth).
References
Material and concepts available in the following documents may be beneficial when
reading this document:
Document
Intel Order Number
AP-485, Intel® Processor Identification and the CPUID Instruction
241618
®
IA-32 Intel Architecture Software Developer's Manual
•
•
•
•
•
Volume 1: Basic Architecture
253665
253666
253667
253668
253669
Volume 2A: Instruction Set Reference, A-M
Volume 2B: Instruction Set Reference, N-Z
Volume 3A: System Programming Guide
Volume 3B: System Programming Guide
64-bit Extension Technology Software Developer's Guide
•
•
Volume 1
Volume 2
®
300834
300835
IA-32 Intel Architecture Optimization Reference Manual
248966
12
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Introduction
Document
Intel Order Number
®
®
Dual-Core Intel Xeon Processor 5000 Series Specifications Update
313065
EPS12V Power Supply Design Guide: A Server system Infrastructure (SSI)
Specification for Entry Chassis Power Supplies
http://
www.ssiforum.org
Entry-Level Electronics-Bay Specifications: A Server System Infrastructure (SSI)
Specification for Entry Pedestal Servers and Workstations
http://
www.ssiforum.org
Dual-Core Intel® Xeon® Processor 5000 Series Thermal/Mechanical Design
Guidelines
313062
313064
Dual-Core Intel® Xeon® Processor 5000 Series Boundary Scan Descriptive
Language (BSDL) Model
Notes: Contact your Intel representative for the latest revision of those documents.
§
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
13
Introduction
14
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Electrical Specifications
2 Electrical Specifications
2.1
Front Side Bus and GTLREF
Most Dual-Core Intel Xeon Processor 5000 series FSB signals use Assisted Gunning
Transceiver Logic (AGTL+) signaling technology. This technology provides improved
noise margins and reduced ringing through low voltage swings and controlled edge
rates. AGTL+ buffers are open-drain and require pull-up resistors to provide the high
logic level and termination. AGTL+ output buffers differ from GTL+ buffers with the
addition of an active PMOS pull-up transistor to “assist” the pull-up resistors during the
first clock of a low-to-high voltage transition. Platforms implement a termination
voltage level for AGTL+ signals defined as VTT. Because platforms implement separate
power planes for each processor (and chipset), separate VCC and VTT supplies are
necessary. This configuration allows for improved noise tolerance as processor
frequency increases. Speed enhancements to data and address buses have made
signal integrity considerations and platform design methods even more critical than
with previous processor families.
The AGTL+ inputs require reference voltages (GTLREF), which are used by the
receivers to determine if a signal is a logical 0 or a logical 1. GTLREF must be generated
on the baseboard. GTLREF is a generic name for GTLREF_DATA_C[1:0], the reference
voltages for the 4X data bus and GTLREF_ADD_C[1:0], the reference voltages for the
2X address bus and common clock signals. Refer to the applicable platform design
guidelines for details. Termination resistors (RTT) for AGTL+ signals are provided on the
processor silicon and are terminated to VTT. The on-die termination resistors are always
enabled on the Dual-Core Intel Xeon Processor 5000 series to control reflections on the
transmission line. Intel chipsets also provide on-die termination, thus eliminating the
need to terminate the bus on the baseboard for most AGTL+ signals.
Some FSB signals do not include on-die termination (RTT) and must be terminated on
the baseboard. See Table 2-7 for details regarding these signals.
The AGTL+ bus depends on incident wave switching. Therefore, timing calculations for
AGTL+ signals are based on flight time as opposed to capacitive deratings. Analog
signal simulation of the FSB, including trace lengths, is highly recommended when
designing a system. Contact your Intel Field Representative to obtain the processor
signal integrity models, which includes buffer and package models.
2.2
Power and Ground Lands
For clean on-chip processor core power distribution, the processor has 223 VCC (power)
and 271 VSS (ground) inputs. All Vcc lands must be connected to the processor power
plane, while all VSS lands must be connected to the system ground plane. The
processor VCC lands must be supplied with the voltage determined by the processor
Voltage IDentification (VID) signals. See Table 2-3 for VID definitions.
Twenty two lands are specified as VTT, which provide termination for the FSB and power
to the I/O buffers. The platform must implement a separate supply for these lands
which meets the VTT specifications outlined in Table 2-10.
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
15
Electrical Specifications
2.3
Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the Dual-Core
Intel Xeon Processor 5000 series are capable of generating large average current
swings between low and full power states. This may cause voltages on power planes to
sag below their minimum values if bulk decoupling is not adequate. Larger bulk storage
(CBULK), such as electrolytic capacitors, supply current during longer lasting changes in
current demand by the component, such as coming out of an idle condition. Similarly,
they act as a storage well for current when entering an idle condition from a running
condition. Care must be taken in the baseboard design to ensure that the voltage
provided to the processor remains within the specifications listed in Table 2-10. Failure
to do so can result in timing violations or reduced lifetime of the component. For further
information and guidelines, refer to the appropriate platform design guidelines.
2.3.1
2.3.2
V Decoupling
CC
Vcc regulator solutions need to provide bulk capacitance with a low Effective Series
Resistance (ESR), and the baseboard designer must assure a low interconnect
resistance from the regulator (EVRD or VRM pins) to the LGA771 socket. Bulk
decoupling must be provided on the baseboard to handle large current swings. The
power delivery solution must insure the voltage and current specifications are met (as
defined in Table 2-10). For further information regarding power delivery, decoupling
and layout guidelines, refer to the appropriate platform design guidelines.
VTT Decoupling
Bulk decoupling must be provided on the baseboard. Decoupling solutions must be
sized to meet the expected load. To insure optimal performance, various factors
associated with the power delivery solution must be considered including regulator
type, power plane and trace sizing, and component placement. A conservative
decoupling solution consists of a combination of low ESR bulk capacitors and high
frequency ceramic capacitors. For further information regarding power delivery,
decoupling and layout guidelines, refer to the appropriate platform design guidelines.
2.3.3
Front Side Bus AGTL+ Decoupling
The Dual-Core Intel Xeon Processor 5000 series integrate signal termination on the die,
as well as a portion of the required high frequency decoupling capacitance on the
processor package. However, additional high frequency capacitance must be added to
the baseboard to properly decouple the return currents from the FSB. Bulk decoupling
must also be provided by the baseboard for proper AGTL+ bus operation. Decoupling
guidelines are described in the appropriate platform design guidelines.
2.4
Front Side Bus Clock (BCLK[1:0]) and Processor
Clocking
BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the
processor. As in previous processor generations, the Dual-Core Intel Xeon Processor
5000 series core frequency is a multiple of the BCLK[1:0] frequency. The processor bus
ratio multiplier is set during manufacturing. The default setting is for the maximum
speed of the processor. It is possible to override this setting using software (see the
IA-32 Intel® Architecture Software Developer’s Manual, Volume 3A &3B). This permits
operation at lower frequencies than the processor’s tested frequency.
16
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Electrical Specifications
The processor core frequency is configured during reset by using values stored
internally during manufacturing. The stored value sets the highest bus fraction at which
the particular processor can operate. If lower speeds are desired, the appropriate ratio
can be configured via the IA32_FLEX_BRVID_SEL MSR. For details of operation at core
frequencies lower than the maximum rated processor speed, refer to the IA-32 Intel®
Architecture Software Developer’s Manual, Volume 3A &3B.
Clock multiplying within the processor is provided by the internal phase locked loop
(PLL), which requires a constant frequency BCLK[1:0] input, with exceptions for spread
spectrum clocking. The Dual-Core Intel Xeon Processor 5000 series utilize differential
clocks. Table 2-1 contains processor core frequency to FSB multipliers and their
corresponding core frequencies.
Table 2-1.
Core Frequency to FSB Multiplier Configuration
Core Frequency to FSB
Multiplier
Core Frequency with
166 MHz FSB Clock
Processor Number
Notes
1/16
1/18
2.67 GHz
3 GHz
5030
5050
1, 2, 3, 4
1, 2, 3, 4
Core Frequency to FSB
Multiplier
Core Frequency with
266 MHz FSB Clock
Notes
1/12
1/12
1/14
3.20 GHz
3.20 GHz
3.73 GHz
5063
5060
5080
1, 2, 3, 4
1, 2, 3, 5
1, 2, 3
Notes:
1.
2.
3.
Individual processors operate only at or below the frequency marked on the package.
Listed frequencies are not necessarily committed production frequencies.
For valid processor core frequencies, refer to the Dual-Core Intel Xeon Processor 5000 series
Specification Update.
Mid-voltage (MV) processors only.
®
®
4.
5.
The lowest bus ratio supported by the Dual-Core Intel Xeon Processor 5000 series is 1/12.
2.4.1
Front Side Bus Frequency Select Signals (BSEL[2:0])
Upon power up, the FSB frequency is set to the maximum supported by the individual
processor. BSEL[2:0] are open drain outputs which must be pulled up to VTT, and are
used to select the FSB frequency. Please refer to Table 2-12 for DC specifications.
Table 2-2 defines the possible combinations of the signals and the frequency associated
with each combination. The frequency is determined by the processor(s), chipset, and
clock synthesizer. All FSB agents must operate at the same core and FSB frequency.
See the appropriate platform design guidelines for further details.
Table 2-2.
BSEL[2:0] Frequency Table
BSEL2
BSEL1
BSEL0
Bus Clock Frequency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
266.67 MHz
Reserved
Reserved
166.67 MHz
Reserved
Reserved
Reserved
Reserved
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
17
Electrical Specifications
2.4.2
Phase Lock Loop (PLL) and Filter
VCCA and VCCIOPLL are power sources required by the PLL clock generators on the Dual-
Core Intel Xeon Processor 5000 series. Since these PLLs are analog in nature, they
require low noise power supplies for minimum jitter. Jitter is detrimental to the system:
it degrades external I/O timings as well as internal core timings (that is, maximum
frequency). To prevent this degradation, these supplies must be low pass filtered from
VTT.
The AC low-pass requirements are as follows:
• < 0.2 dB gain in pass band
• < 0.5 dB attenuation in pass band < 1 Hz
• > 34 dB attenuation from 1 MHz to 66 MHz
• > 28 dB attenuation from 66 MHz to core frequency
The filter requirements are illustrated in Figure 2-1. For recommendations on
implementing the filter, refer to the appropriate platform design guidelines.
Figure 2-1. Phase Lock Loop (PLL) Filter Requirements
0.2 dB
0 dB
-0.5 dB
forbidden
zone
-28 dB
forbidden
zone
-34 dB
DC
passband
1 Hz
fpeak
1 MHz
66 MHz
fcore
high frequency
band
CS00141
Notes:
1.
2.
3.
4.
Diagram not to scale.
No specifications for frequencies beyond f
(core frequency).
core
f
f
, if existent, should be less than 0.05 MHz.
peak
core
represents the maximum core frequency supported by the platform.
18
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Electrical Specifications
2.5
Voltage Identification (VID)
The Voltage Identification (VID) specification for the Dual-Core Intel Xeon Processor
5000 series set by the VID signals is the reference VR output voltage to be delivered to
the processor Vcc pins. VID signals are open drain outputs, which must be pulled up to
VTT. Please refer to Table 2-12 for the DC specifications for these signals. A minimum
voltage is provided in Table 2-10 and changes with frequency. This allows processors
running at a higher frequency to have a relaxed minimum voltage specification. The
specifications have been set such that one voltage regulator can operate with all
supported frequencies.
Individual processor VID values may be calibrated during manufacturing such that two
devices at the same core frequency may have different default VID settings. This is
reflected by the VID range values provided in Table 2-3.
The Dual-Core Intel Xeon Processor 5000 series use six voltage identification signals,
VID[5:0], to support automatic selection of power supply voltages. The processor uses
the VTTPWRGD input to determine that the supply voltage for VID[5:0] is stable and
within specification.Table 2-3 specifies the voltage level corresponding to the state of
VID[5:0]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers to a low
voltage level. The definition provided in Table 2-3 is not related in any way to previous
Intel® Xeon® processors or voltage regulator designs. If the processor socket is empty
(VID[5:0] = x11111), or the voltage regulation circuit cannot supply the voltage that is
requested, it must disable itself.
The Dual-Core Intel Xeon Processor 5000 series provide the ability to operate while
transitioning to an adjacent VID and its associated processor core voltage (VCC). This
will represent a DC shift in the load line. It should be noted that a low-to-high or high-
to-low voltage state change may result in as many VID transitions as necessary to
reach the target core voltage. Transitions above the specified VID are not permitted.
Table 2-10 includes VID step sizes and DC shift ranges. Minimum and maximum
voltages must be maintained as shown in Table 2-11 and Figure 2-4.
The VRM or EVRD utilized must be capable of regulating its output to the value defined
by the new VID. DC specifications for dynamic VID transitions are included in
Table 2-10 and Table 2-11.
Power source characteristics must be guaranteed to be stable whenever the supply to
the voltage regulator is stable.
Table 2-3.
Voltage Identification Definition (Sheet 1 of 2)
VID4 VID3 VID2 VID1 VID0 VID5 VCC_MAX
VID4 VID3 VID2 VID1 VID0 VID5 VCC_MAX
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
0.8375
0.8500
0.8625
0.8750
0.8875
0.9000
0.9125
0.9250
0.9375
0.9500
0.9625
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1.2125
1.2250
1.2375
1.2500
1.2625
1.2750
1.2875
1.3000
1.3125
1.3250
1.3375
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
19
Electrical Specifications
Table 2-3.
Voltage Identification Definition (Sheet 2 of 2)
VID4 VID3 VID2 VID1 VID0 VID5 VCC_MAX
VID4 VID3 VID2 VID1 VID0 VID5 VCC_MAX
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0.9750
0.9875
1.0000
1.0125
1.0250
1.0375
1.0500
1.0625
1.0750
1.0875
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.3500
1.3625
1.3750
1.3875
1.4000
1.4125
1.4250
1.4375
1.4500
1.4625
1.4750
1.4875
1.5000
1.5125
1.5250
1.5375
1.5500
1.5625
1.5750
1.5875
1.6000
1
OFF
1
OFF
1.1000
1.1125
1.1250
1.1375
1.1500
1.1625
1.1750
1.1875
1.2000
Notes:
1.
2.
When this VID pattern is observed, the voltage regulator output should be disabled.
Shading denotes the expected VID range of the Dual-Core Intel Xeon Processor 5000 series [1.0750 V -
1.3500 V].
Table 2-4.
Loadline Selection Truth Table for LL_ID[1:0]
LL_ID1
LL_ID0
Description
0
0
1
1
0
1
0
1
Reserved
Dual-Core Intel Xeon Processor 5000 Series
Reserved
Reserved
Note:
1.
2.
3.
4.
The LL_ID[1:0] signals are used to select the correct loadline slope for the processor.
These signals are not connected to the processor die.
A logic 0 is achieved by pulling the signal to ground on the package.
A logic 1 is achieved by leaving the signal as a no connect on the package.
Table 2-5.
Market Segment Selection Truth Table for MS_ID[1:0]
MS_ID1
MS_ID0
Description
0
0
1
1
0
1
0
1
Dual-Core Intel Xeon Processor 5000 Series
Reserved
Reserved
Reserved
20
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Electrical Specifications
Note:
1.
The MS_ID[1:0] signals are provided to indicate the Market Segment for the processor and may be used
for future processor compatibility or for keying. System management software may utilize these signals to
identify the processor installed.
2.
3.
4.
These signals are not connected to the processor die.
A logic 0 is achieved by pulling the signal to ground on the package.
A logic 1 is achieved by leaving the signal as a no connect on the package.
2.6
Reserved or Unused Signals
All Reserved signals must remain unconnected. Connection of these signals to VCC, VTT,
VSS, or to any other signal (including each other) can result in component malfunction
or incompatibility with future processors. See Chapter 4, “Land Listing” for a land
listing of the processor and the location of all Reserved signals.
For reliable operation, always connect unused inputs or bidirectional signals to an
appropriate signal level. Unused active high inputs, should be connected through a
resistor to ground (VSS). Unused outputs can be left unconnected; however, this may
interfere with some TAP functions, complicate debug probing, and prevent boundary
scan testing. A resistor must be used when tying bidirectional signals to power or
ground. When tying any signal to power or ground, a resistor will also allow for system
testability. Resistor values should be within ± 20% of the impedance of the baseboard
trace for FSB signals. For unused AGTL+ input or I/O signals, use pull-up resistors of
the same value as the on-die termination resistors (RTT).
TAP, Asynchronous GTL+ inputs, and Asynchronous GTL+ outputs do not include on-die
termination. Inputs and utilized outputs must be terminated on the baseboard. Unused
outputs may be terminated on the baseboard or left unconnected. Note that leaving
unused outputs unterminated may interfere with some TAP functions, complicate debug
probing, and prevent boundary scan testing. Signal termination for these signal types
is discussed in the appropriate platform design guidelines.
The TESTHI signals must be tied to the processor VTT using a matched resistor, where a
matched resistor has a resistance value within +/-20% of the impedance of the board
transmission line traces. For example, if the trace impedance is 50 Ω, then a value
between 40 Ω and 60 Ω is required.
The TESTHI signals may use individual pull-up resistors or be grouped together as
detailed below. A matched resistor must be used for each group:
• TESTHI[1:0] - can be grouped together with a single pull-up to VTT
• TESTHI[7:2] - can be grouped together with a single pull-up to VTT
• TESTHI8 – cannot be grouped with other TESTHI signals
• TESTHI9 – cannot be grouped with other TESTHI signals
• TESTHI10 – cannot be grouped with other TESTHI signals
• TESTHI11 – cannot be grouped with other TESTHI signals
2.7
Front Side Bus Signal Groups
The FSB signals have been combined into groups by buffer type. AGTL+ input signals
have differential input buffers, which use GTLREF as a reference level. In this
document, the term “AGTL+ Input” refers to the AGTL+ input group as well as the
AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers to the AGTL+
output group as well as the AGTL+ I/O group when driving. AGTL+ asynchronous
outputs can become active anytime and include an active PMOS pull-up transistor to
assist the during the first clock of a low-to-high voltage transition.
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
21
Electrical Specifications
With the implementation of a source synchronous data bus comes the need to specify
two sets of timing parameters. One set is for common clock signals whose timings are
specified with respect to rising edge of BCLK0 (ADS#, HIT#, HITM#, and so forth) and
the second set is for the source synchronous signals which are relative to their
respective strobe lines (data and address) as well as rising edge of BCLK0.
Asynchronous signals are still present (A20M#, IGNNE#, and so forth) and can become
active at any time during the clock cycle. Table 2-6 identifies which signals are common
clock, source synchronous and asynchronous.
Table 2-6.
FSB Signal Groups
1
Signal Group
Type
Signals
AGTL+ Common Clock Input
Synchronous to BCLK[1:0]
BPRI#, DEFER#, RESET#, RS[2:0]#, RSP#,
TRDY#
2
2
AGTL+ Common Clock I/O
Synchronous to BCLK[1:0]
ADS#, AP[1:0]#, BINIT# , BNR# ,
BPM[5:0]#, BR[1:0]#, DBSY#, DP[3:0]#,
2
2
2
DRDY#, HIT# , HITM# , LOCK#, MCERR#
AGTL+ Source Synchronous I/O Synchronous to assoc.
strobe
Signals
Associated Strobe
REQ[4:0]#,A[16:3]
#
ADSTB0#
A[35:17]#
ADSTB1#
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
DSTBP0#, DSTBN0#
DSTBP1#, DSTBN1#
DSTBP2#, DSTBN2#
DSTBP3#, DSTBN3#
AGTL+ Strobes I/O
Synchronous to BCLK[1:0]
Asynchronous
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
FERR#/PBE#, IERR#, PROCHOT#
AGTL+ Asynchronous Output
GTL+ Asynchronous Input
Asynchronous
A20M#, FORCEPR#, IGNNE#, INIT#, LINT0/
INTR, LINT1/NMI, SMI#, STPCLK#
GTL+ Asynchronous Output
FSB Clock
Asynchronous
Clock
THERMTRIP#
BCLK1, BCLK0
TCK, TDI, TMS TRST#
TDO
TAP Input
Synchronous to TCK
Synchronous to TCK
Power/Other
TAP Output
Power/Other
BSEL[2:0], COMP[7:0], GTLREF_ADD_C[1:0],
GTLREF_DATA_C[1:0], LL_ID[1:0],
MS_ID[1:0], PWRGOOD, Reserved, SKTOCC#,
TEST_BUS, TESTHI[11:0], THERMDA,
THEMRDA2, THERMDC, THERMDC2, V , V
,
CC
CCA
V
VCC_DIE_SENSE, VCC_DIE_SENSE2,
CCIOPLL,
VID[5:0], VID_SELECT, VSS_DIE_SENSE,
VSS_DIE_SENSE2, V , V
, V , VTTOUT,
SS
SSA
TT
VTTPWRGD
Notes:
1.
2.
Refer to Section 5 for signal descriptions.
These signals may be driven simultaneously by multiple agents (Wired-OR).
22
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Electrical Specifications
Table 2-7 outlines the signals which include on-die termination (RTT). Open drain
signals are also included. Table 2-8 provides signal reference voltages.
Table 2-7.
Signal Description Table
Signals with R
Signals with no R
TT
TT
A[35:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#, A20M#, BCLK[1:0], BPM[5:0]#, BR[1:0]#, BSEL[2:0],
BNR#, BPRI#, COMP[7:4], D[63:0]#, DBI[3:0]#, COMP[3:0], FERR#/PBE#, GTLREF_ADD_C[1:0],
DBSY#, DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#, GTLREF_DATA_C[1:0], IERR#, IGNNE#, INIT#, LINT0/
DSTBP[3:0]#, FORCEPR#, HIT#, HITM#, LOCK#,
MCERR#, PROCHOT#, REQ[4:0]#, RS[2:0]#,
INTR, LINT1/NMI, LL_ID[1:0], MS_ID[1:0], PWRGOOD,
RESET#, SKTOCC#, SMI#, STPCLK#, TDO,
TESTHI[11:0], THERMDA, THERMDA2, THERMDC,
THERMDC2, THERMTRIP#, VCC_DIE_SENSE,
VCC_DIE_SENSE2, VID[5:0], VID_SELECT,
2
2
2
RSP#, TCK , TDI , TEST_BUS, TMS , TRDY#,
2
TRST#
VSS_DIE_SENSE, VSS_DIE_SENSE2, VTTPWRGD
1
Open Drain Signals
BPM[5:0]#, BR0#, FERR#/PBE#, IERR#, PROCHOT#, TDO, THERMTRIP#
Notes:
1.
2.
Signals that do not have R , nor are actively driven to their high voltage level.
TT
The on-die termination for these signals is not R . TCK, TDI, and TMS have an approximately 150 KΩ
TT
pullup to V .
TT
Table 2-8.
Signal Reference Voltages
GTLREF
VTT / 2
1
A[35:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#, A20M#, IGNNE#, INIT#, PWRGOOD , SMI#, STPCLK#,
1
1
1
1
BNR#, BPM[5:0]#, BPRI#, BR[1:0]#, D[63:0]#,
DBI[3:0]#, DBSY#, DEFER#, DP[3:0]#, DRDY#,
TCK , TDI , TMS , TRST# , VTTPWRGD
2
DSTBN[3:0]#, DSTBP[3:0]#, FORCEPR# , HIT#,
HITM#, IERR#, LINT0/INTR, LINT1/NMI, LOCK#,
MCERR#, RESET#, REQ[4:0]#, RS[2:0]#, RSP#,
TRDY#
Notes:
1.
2.
These signals also have hysteresis added to the reference voltage. See Table 2-14 for more information.
Use Table 2-15 for signal FORCEPR# specifications.
2.8
GTL+ Asynchronous and AGTL+ Asynchronous
Signals
Input signals such as A20M#, FORCEPR#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI,
SMI# and STPCLK# utilize GTL+ input buffers. Legacy output FERR#/PBE# and other
non-AGTL+ signals IERR#, THERMTRIP# and PROCHOT# utilize GTL+ output buffers.
All of these asynchronous GTL+ signals follow the same DC requirements as AGTL+
signals; however, the outputs are not driven high (during the electrical 0-to-1
transition) by the processor. FERR#/PBE#, IERR#, and IGNNE# have now been defined
as AGTL+ asynchronous signals as they include an active p-MOS device. Asynchronous
GTL+ and asynchronous AGTL+ signals do not have setup or hold time specifications in
relation to BCLK[1:0]; however, all of the asynchronous GTL+ and asynchronous
AGTL+ signals are required to be asserted/deasserted for at least six BCLKs in order for
the processor to recognize them. See Table 2-15 for the DC specifications for the
asynchronous GTL+ signal groups.
2.9
Test Access Port (TAP) Connection
Due to the voltage levels supported by other components in the Test Access Port (TAP)
logic, it is recommended that the processor(s) be first in the TAP chain and followed by
any other components within the system. A translation buffer should be used to
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
23
Electrical Specifications
connect to the rest of the chain unless one of the other components is capable of
accepting an input of the appropriate voltage. Similar considerations must be made for
TCK, TMS, and TRST#. Two copies of each signal may be required with each driving a
different voltage level.
2.10
Mixing Processors
Intel supports and validates dual processor configurations only in which both
processors operate with the same FSB frequency, core frequency, and have the same
internal cache sizes. Mixing components operating at different internal clock
frequencies is not supported and will not be validated by Intel [Note: Processors within
a system must operate at the same frequency per bits [15:8] of the
IA32_FLEX_BRVID_SEL MSR; however this does not apply to frequency transitions
initiated due to thermal events, Enhanced HALT, Enhanced Intel SpeedStep®
Technology transitions, or assertion of the FORCEPR# signal (See Chapter 6, “Thermal
Specifications”)]. Low voltage (LV), mid-voltage (MV) and full-power 64-bit Intel Xeon
processors should not be mixed within a system. Not all operating systems can support
dual processors with mixed frequencies. Intel does not support or validate operation of
processors with different cache sizes. Mixing processors of different steppings but the
same model (as per CPUID instruction) is supported. Details regarding the CPUID
instruction are provided in the AP-485 Intel® Processor Identification and the CPUID
Instruction application note.
2.11
Absolute Maximum and Minimum Ratings
Table 2-9 specifies absolute maximum and minimum ratings. Within functional
operation limits, functionality and long-term reliability can be expected.
At conditions outside functional operation condition limits, but within absolute
maximum and minimum ratings, neither functionality nor long term reliability can be
expected. If a device is returned to conditions within functional operation limits after
having been subjected to conditions outside these limits, but within the absolute
maximum and minimum ratings, the device may be functional, but with its lifetime
degraded depending on exposure to conditions exceeding the functional operation
condition limits.
At conditions exceeding absolute maximum and minimum ratings, neither functionality
nor long-term reliability can be expected. Moreover, if a device is subjected to these
conditions for any length of time then, when returned to conditions within the
functional operating condition limits, it will either not function or its reliability will be
severely degraded.
Although the processor contains protective circuitry to resist damage from static
electric discharge, precautions should always be taken to avoid high static voltages or
electric fields
.
Table 2-9.
Processor Absolute Maximum Ratings
1, 2
Symbol
Parameter
Min
Max
Unit
Notes
V
V
Core voltage with respect to VSS
-0.30
-0.30
1.55
1.55
V
V
CC
TT
FSB termination voltage with respect to
V
SS
T
Processor case temperature
See
See
° C
° C
CASE
Section 6
Section 6
T
Storage temperature
-40
85
3, 4, 5
STORAGE
24
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Electrical Specifications
Notes:
1.
2.
3.
For functional operation, all processor electrical, signal quality, mechanical and thermal specifications must
be satisfied.
Overshoot and undershoot voltage guidelines for input, output, and I/O signals are outlined in Section 3.
Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor.
Storage temperature is applicable to storage conditions only. In this scenario, the processor must not
receive a clock, and no lands can be connected to a voltage bias. Storage within these limits will not affect
the long-term reliability of the device. For functional operation, please refer to the processor case
temperature specifications.
4.
5.
This rating applies to the processor and does not include any tray or packaging.
Failure to adhere to this specification can affect the long term reliability of the processor.
2.12
Processor DC Specifications
The processor DC specifications in this section are defined at the processor
core (pads) unless noted otherwise. See Section 4.1 for the Dual-Core Intel Xeon
Processor 5000 series land listings and Section 5.1 for signal definitions. Voltage and
current specifications are detailed in Table 2-10. For platform planning refer to
Table 2-11, which provides Voltage-Current projections. This same information is
presented graphically in Figure 2-4.
BSEL[2:0] and VID[5:0] signals are specified in Table 2-12. The DC specifications for
the AGTL+ signals are listed in Table 2-13. Legacy signals and Test Access Port (TAP)
signals follow DC specifications similar to GTL+. The DC specifications for the
PWRGOOD input and TAP signal group are listed in Table 2-14 and the Asynchronous
GTL+ signal group is listed in Table 2-15. The VTTPWRGD signal is detailed in
Table 2-16.
Table 2-10 through Table 2-16 list the DC specifications for the processor and are valid
only while meeting specifications for case temperature (TCASE as specified in Table 6-1),
clock frequency, and input voltages. Care should be taken to read all notes
associated with each parameter.
Table 2-10. Voltage and Current Specifications (Sheet 1 of 2)
Notes
1,13
Symbol
VID
Parameter
Min
Typ
Max
Unit
VID range
1.0750
1.3500
V
V
V
V
for Dual-Core Intel Xeon
CC
Processor 5000 series core. FMB
processor.
See Table 2-11 and Figure 2-4
2, 3, 4, 6,
11
CC
V
V
VID step size during a transition
12.5
425
mV
mV
VID_STEP
Total allowable DC load line shift
from VID steps
12
VID_SHIFT
V
FSB termination voltage (DC + AC
specification)
1.140
1.20
1.260
115
V
A
10, 14
TT
I
I
I
I
I
for Dual-Core Intel Xeon
CC
4, 5, 6, 11
CC
Processor 5000 series with multiple
VID (667 MHz)
I
for Dual-Core Intel Xeon
CC
150
115
115
A
A
A
4, 5, 6, 11
4, 5, 6, 11
18
CC
Processor 5000 series with multiple
VID (1066 MHz)
I
for Dual-Core Intel Xeon
CC
CC
Processor 5063 (MV) with multiple
VID
I
for Dual-Core Intel Xeon
CC_RESET
CC_RESET
Processor 5000 series with multiple
VID (667 MHz)
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
25
Electrical Specifications
Table 2-10. Voltage and Current Specifications (Sheet 2 of 2)
Notes
Symbol
Parameter
Min
Typ
Max
Unit
1,13
I
I
I
I
for Dual-Core Intel Xeon
CC_RESET
150
A
18
CC_RESET
Processor 5000 series with multiple
VID (1066 MHz)
I
for Dual-Core Intel Xeon
CC_RESET
115
6.1
A
A
18
16
CC_RESET
TT
Processor 5063 (MV) with multiple
VID
Steady-state FSB Termination
Current
I
I
Power-up FSB Termination Current
8.0
A
A
19
TT_POWER-UP
CC_TDC
Thermal Design Current (TDC) for
Dual-Core Intel Xeon Processor
5000 series (667 MHz)
100
6,15
I
I
I
Thermal Design Current (TDC) for
Dual-Core Intel Xeon Processor
5000 series (1066 MHz)
130
100
580
A
A
6,15
6,15
17
CC_TDC
Thermal Design Current (TDC) for
Dual-Core Intel Xeon Processor
5063 (MV)
CC_TDC
DC current that may be drawn
mA
CC_VTTOUT
from V
per land
TTOUT
I
I
I
I
I
I
I
I
for PLL power lands
for PLL power lands
for GTLREF
120
100
200
150
mA
mA
µA
A
8
8
9
CC_VCCA
CC_VCCIOPLL
CC_GTLREF
TCC
CC
CC
CC
CC
during active thermal control
circuit (TCC) for Dual-Core Intel
Xeon Processor 5000 series
I
I
I
I
I
during active thermal control
CC
115
50
A
A
A
A
TCC
circuit (TCC) for Dual-Core Intel
Xeon Processor 5063 (MV)
I
Stop-Grant for Dual-Core Intel
CC
7
7
7
SGNT
SGNT
SGNT
Xeon Processor 5000 series (667
MHz)
I
Stop-Grant for Dual-Core Intel
60
CC
Xeon Processor 5000 series (1066
MHz)
I
Stop-Grant for Dual-Core Intel
40
CC
Xeon Processor 5063 (MV)
Notes:
1.
2.
3.
Unless otherwise noted, all specifications in this table apply to all processors and are based on final silicon
validation/characterization.
These voltages are targets only. A variable voltage source should exist on systems in the event that a
different voltage is required. See Section 2.5 for more information.
The voltage specification requirements are measured across the VCC_DIE_SENSE and VSS_DIE_SENSE
lands and across the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands with a 100 MHz bandwidth
oscilloscope, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length of
ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled
in the scope probe.
4.
5.
The processor must not be subjected to any static V level that exceeds the V
associated with any
CC
CC_MAX
particular current. Failure to adhere to this specification can shorten processor lifetime.
is specified at V . The processor is capable of drawing I for up to 10 ms. Refer to
I
CC_MAX
CC_MAX
CC_MAX
Figure 2-2 and Figure 2-3 for further details on the average processor current draw over various time
durations.
6.
7.
8.
9.
10.
26
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Electrical Specifications
11. Minimum VCC and maximum ICC are specified at the maximum processor case temperature (TCASE)
shown in Table 6-1.
12. This specification refers to the total reduction of the load line due to VID transitions below the specified
VID.
13. Individual processor VID values may be calibrated during manufacturing such that two devices at the same
frequency may have different VID settings.
14. Baseboard bandwidth is limited to 20 MHz.
15.
I
is the sustained (DC equivalent) current that the processor is capable of drawing indefinitely and
CC_TDC
should be used for the voltage regulator temperature assessment. The voltage regulator is responsible for
monitoring its temperature and asserting the necessary signal to inform the processor of a thermal
excursion. Please see the applicable design guidelines for further details. The processor is capable of
drawing I
indefinitely. Refer to Figure 2-2 and Figure 2-3 for further details on the average processor
CC_TDC
current draw over various time durations. This parameter is based on design characterization and is not
tested.
16. This specification is per-processor. This is a steady-state I current specification, which is applicable when
TT
both V and V are high. This parameter is based on design characterization and is not tested. Please
TT
CC
refer to the I Analysis of System Bus Components - Bensley Platform Whitepaper for platform
TT
implementation guidance.
17. ICC_VTTOUT is specified at 1.2 V.
18.I
is specified while PWRGOOD and RESET# are asserted.
CC_RESET
19. This specification is per-processor. This is a power-up peak current specification, which is applicable when
is powered up and V is not. This parameter is based on design characterization and is not tested.
V
TT
CC
Figure 2-2. Dual-Core Intel® Xeon® Processor 5000 Series (1066 MHz) Load Current
versus Time
155
150
145
140
135
130
125
0.01
0.1
1
10
100
1000
Time Duration (s)
Notes:
1.
Processor or Voltage Regulator thermal protection circuitry should not trip for load currents greater than
I
.
CC_TDC
2.
Not 100% tested. Specified by design characterization.
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
27
Electrical Specifications
Figure 2-3. Dual-Core Intel® Xeon® Processor 5000 Series (667 MHz) and Dual-Core
Intel® Xeon® Processor 5063 (MV) Load Current versus Time
Notes:
1.
Processor or Voltage Regulator thermal protection circuitry should not trip for load currents greater than
I
.
CC_TDC
2.
Not 100% tested. Specified by design characterization.
Table 2-11. VCC Static and Transient Tolerance (Sheet 1 of 2)
I
(A)
V
(V)
V
(V)
V (V)
CC_Min
Notes
CC
CC_Max
CC_Typ
0
VID - 0.000
VID - 0.006
VID - 0.013
VID - 0.019
VID - 0.025
VID - 0.031
VID - 0.038
VID - 0.044
VID - 0.050
VID - 0.056
VID - 0.063
VID - 0.069
VID - 0.075
VID - 0.081
VID - 0.087
VID - 0.094
VID - 0.015
VID - 0.021
VID - 0.028
VID - 0.034
VID - 0.040
VID - 0.046
VID - 0.053
VID - 0.059
VID - 0.065
VID - 0.071
VID - 0.078
VID - 0.084
VID - 0.090
VID - 0.096
VID - 0.103
VID - 0.109
VID - 0.030
VID - 0.036
VID - 0.043
VID - 0.049
VID - 0.055
VID - 0.061
VID - 0.068
VID - 0.074
VID - 0.080
VID - 0.086
VID - 0.093
VID - 0.099
VID - 0.105
VID - 0.111
VID - 0.118
VID - 0.124
1, 2, 3, 4
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
28
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Electrical Specifications
Table 2-11. VCC Static and Transient Tolerance (Sheet 2 of 2)
I
(A)
V
(V)
V
(V)
V (V)
CC_Min
Notes
CC
CC_Max
CC_Typ
80
VID - 0.100
VID - 0.106
VID - 0.113
VID - 0.119
VID - 0.125
VID - 0.131
VID - 0.138
VID - 0.144
VID - 0.150
VID - 0.156
VID - 0.163
VID - 0.169
VID - 0.175
VID - 0.181
VID - 0.188
VID - 0.115
VID - 0.121
VID - 0.128
VID - 0.134
VID - 0.140
VID - 0.146
VID - 0.153
VID - 0.159
VID - 0.165
VID - 0.171
VID - 0.178
VID - 0.184
VID - 0.190
VID - 0.196
VID - 0.203
VID - 0.130
VID - 0.136
VID - 0.143
VID - 0.149
VID - 0.155
VID - 0.161
VID - 0.168
VID - 0.174
VID - 0.180
VID - 0.186
VID - 0.193
VID - 0.199
VID - 0.205
VID - 0.211
VID - 0.218
85
90
95
100
105
110
115
120
125
130
135
140
145
150
Notes:
1.
The V
and V
loadlines represent static and transient limits. Please see Section 2.12.1 for V
CC_MAX CC
CC_MIN
overshoot specifications.
This table is intended to aid in reading discrete points on Figure 2-4.
2.
3.
The loadlines specify voltage limits at the die measured at the VCC_DIE_SENSE and VSS_DIE_SENSE lands
and at the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Voltage regulation feedback for voltage
regulator circuits must also be taken from processor VCC_DIE_SENSE and VSS_DIE_SENSE lands and
VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Please refer to the appropriate platform design guide for
details on VR implementation.
4.
Non-shading denotes the expected I range applies to both Dual-Core Intel Xeon Processor 5000 series
CC
(1066 MHz & 667 MHz) and Dual-Core Intel Xeon Processor 5063 (MV). Shading denotes the expected I
CC
range applies to Dual-Core Intel Xeon Processor 5000 series (1066 MHz) only. [120 A - 150 A]
Figure 2-4. VCC Static and Transient Tolerance Load Lines
Icc [A]
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
VID - 0.000
VID - 0.020
VID - 0.040
VID - 0.060
VID - 0.080
VID - 0.100
VID - 0.120
VID - 0.140
VID - 0.160
VID - 0.180
VID - 0.200
VID - 0.220
VID - 0.240
VID - 0.260
Vcc
Maximum
Vcc
Minimum
Vcc
Typical
Notes:
1.
The V
and V
loadlines represent static and transient limits. Please see Section 2.12.1 for VCC
CC_MAX
CC_MIN
overshoot specifications.
2.
Refer to Table 2-10 for processor VID information.
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
29
Electrical Specifications
3.
4.
Refer to Table 2-11 for processor VCC information.
The load lines specify voltage limits at the die measured at the VCC_DIE_SENSE and VSS_DIE_SENSE
lands and at the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Voltage regulation feedback for voltage
regulator circuits must also be taken from processor VCC_DIE_SENSE and VSS_DIE_SENSE lands and
VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Please refer to the appropriate platform design guide for
details on VR implementation.
Table 2-12. BSEL[2:0], VID[5:0] Signal Group DC Specifications
1
Symbol
Parameter
Min
Max
Units
Notes
R
BSEL[2:0], VID[5:0]
Buffer On Resistance
N/A
120
2
ON
Ω
I
I
Output Low Current
Output High Current
Voltage Tolerance
N/A
N/A
2.4
460
mA
µA
V
2, 3
2, 3
4
OL
OH
V
0.95 * V
1.05 * V
TT
TOL
TT
Notes:
1.
2.
3.
4.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
These parameters are based on design characterization and are not tested.
I
is measured at 0.10*V , I
is measured at 0.90*V .
OL
TT OH TT
Please refer to the appropriate platform design guide for implementation details.
Table 2-13. AGTL+ Signal Group DC Specifications
1
Symbol
Parameter
Min
Max
Unit
Notes
V
V
V
Input Low Voltage
Input High Voltage
Output High Voltage
Output Low Current
0.0
GTLREF - (0.10 * V
)
TT
V
V
2
3, 4
4
IL
IH
GTLREF + (0.10 * V
)
V
V
TT
TT
TT
0.90 * V
N/A
V
OH
OL
TT
I
V
/
mA
4
TT
(0.50 * R
+ R
)
ON_MIN
TT_MIN
I
I
Input Leakage Current
Output Leakage Current
Buffer On Resistance
N/A
N/A
7
± 200
± 200
11
µA
µA
5, 6
5, 6
7
LI
LO
R
ON
Ω
Notes:
1.
2.
3.
4.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
V
V
V
is defined as the voltage range at a receiving agent that will be interpreted as an electrical low value.
is defined as the voltage range at a receiving agent that will be interpreted as an electrical high value.
IL
IH
IH
and V
may experience excursions above V . However, input signal drivers must comply with the
OH
TT
signal quality specifications in Section 3.
Leakage to V with land held at V .
5.
6.
7.
SS
TT
Leakage to V with land held at 300 mV.
TT
This parameter is based on design characterization and is not tested
Table 2-14. PWRGOOD Input and TAP Signal Group DC Specifications (Sheet 1 of 2)
1,
Notes
2
Symbol
Parameter
Min
Max
Unit
V
V
Input Hysteresis
120
396
mV
V
3
HYS
t+
PWRGOOD Input Low to
High Threshold Voltage
0.5 * (V + V
+
0.5 * (V + V
HYS_MAX
+
)
TT
HYS_MIN
TT
0.24)
0.24)
TAP Input Low to High
Threshold Voltage
0.5 * (V + V
)
0.5 * (V + V
V
V
V
V
TT
HYS_MIN
TT
HYS_MAX
TT
PWRGOOD Input High to
Low Threshold Voltage
0.4 * V
0.6 * V
0.5 * (V - V
TT
V
V
t-
TAP Input High to Low
Threshold Voltage
0.5 * (V -V
TT
)
)
HYS_MIN
HYS_MAX
TT
Output High Voltage
N/A
V
4
OH
TT
30
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Electrical Specifications
Table 2-14. PWRGOOD Input and TAP Signal Group DC Specifications (Sheet 2 of 2)
1,
Notes
2
Symbol
Parameter
Min
Max
Unit
I
I
Input Leakage Current
Output Leakage Current
Buffer On Resistance
N/A
N/A
7
± 200
± 200
11
µA
µA
LI
LO
R
5
ON
Ω
Notes:
1.
2.
3.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
All outputs are open drain.
V
represents the amount of hysteresis, nominally centered about 0.5 * V for all PWRGOOD and TAP
HYS
TT
inputs.
4.
5.
PWRGOOD input and the TAP signal group must meet system signal quality specification in Section 3.
The maximum output current is based on maximum current handling capability of the buffer and is not
specified into the test load.
Table 2-15. GTL+ Asynchronous and AGTL+ Asynchronous Signal Group
DC Specifications
1
Symbol
Parameter
Min
Max
(0.5 * V ) - (0.10 * V )
TT
Unit Notes
V
Input Low Voltage
0.0
V
V
3, 11
IL
TT
4, 5, 7,
11
V
Input High Voltage
Output High Voltage
Output Low Current
Input Leakage Current
(0.5 * V ) + (0.10 * V
)
V
V
IH
TT
TT
TT
TT
V
0.90*V
-
V
2, 5, 7
OH
OL
TT
V
/
TT
I
I
A
8
9
[(0.50*R
)+(R
)]
ON_MIN
TT_MIN
I
N/A
N/A
± 200
µA
µA
LI
Output Leakage
Current
± 200
11
10
LO
R
Buffer On Resistance
7
6
Ω
ON
Notes:
1.Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.All outputs are open drain.
3.V is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.
IL
4.V is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.
IH
IH
5.V and V
may experience excursions above V . However, input signal drivers must comply with the signal
OH
TT
quality specifications in Section 3.
6.Refer to the processor HSPICE* I/O Buffer Models for I/V characteristics.
7.The V referred to in these specifications refers to instantaneous V .
TT
TT
8.The maximum output current is based on maximum current handling capability of the buffer and is not
specified into the test load.
9.Leakage to V with land held at V .
SS
TT
10.Leakage to V with land held at 300 mV.
TT
11.LINT0/INTR and LINT1/NMI use GTLREF_ADD as a reference voltage. For these two signals V
=
IH
GTLREF_ADD + (0.10 * V ) and V = GTLREF_ADD - (0.10 * V ).
TT
IL
TT
Table 2-16. VTTPWRGD DC Specifications
Symbol
Parameter
Min
Max
Unit
V
V
Input Low Voltage
Input High Voltage
0.0
0.30
V
V
IL
0.90
V
TT
IH
2.12.1
V
Overshoot Specification
CC
The Dual-Core Intel Xeon Processor 5000 series can tolerate short transient overshoot
events where VCC exceeds the VID voltage when transitioning from a high-to-low
current load condition. This overshoot cannot exceed VID + VOS_MAX (VOS_MAX is the
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
31
Electrical Specifications
maximum allowable overshoot above VID). These specifications apply to the processor
die voltage as measured across the VCC_DIE_SENSE and VSS_DIE_SENSE lands and
across the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands.
Table 2-17. VCC Overshoot Specifications
Symbol
Parameter
Magnitude of V overshoot above VID
Min
Max
Units
Figure
Notes
V
50
25
mV
µs
2-5
2-5
OS_MAX
CC
T
Time duration of V overshoot above VID
CC
OS_MAX
Figure 2-5. VCC Overshoot Example Waveform
Example Overshoot Waveform
VOS
VID + 0.050
VID - 0.000
TOS
0
5
10
15
20
25
Time [us]
TOS: Overshoot time above VID
OS: Overshoot above VID
V
Notes:
1.
2.
V
is the measured overshoot voltage above VID.
is the measured time duration above VID.
OS
OS
T
2.12.2
Die Voltage Validation
Core voltage (VCC) overshoot events at the processor must meet the specifications in
Table 2-17 when measured across the VCC_DIE_SENSE and VSS_DIE_SENSE lands
and across the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Overshoot events that
are < 10 ns in duration may be ignored. These measurement of processor die level
overshoot should be taken with a 100 MHz bandwidth limited oscilloscope.
§
32
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Mechanical Specifications
3 Mechanical Specifications
The Dual-Core Intel Xeon Processor 5000 series are packaged in a Flip Chip Land Grid
Array (FC-LGA6) package that interfaces to the baseboard via a LGA771 socket. The
package consists of a processor core mounted on a pinless substrate with 771 lands. An
integrated heat spreader (IHS) is attached to the package substrate and core and
serves as the interface for processor component thermal solutions such as a heatsink.
Figure 3-1 shows a sketch of the processor package components and how they are
assembled together. .
The package components shown in Figure 3-1 include the following:
1. Integrated Heat Spreader (IHS)
2. Thermal Interface Material (TIM)
3. Processor Core (die)
4. Package Substrate
5. Landside capacitors
6. Package Lands
Figure 3-1. Processor Package Assembly Sketch
TIM
Core (die)
IHS
Substrate
Package Lands
Capacitors
LGA771 Socket
System Board
Note: This drawing is not to scale and is for reference only.
3.1
Package Mechanical Drawings
The package mechanical drawings are shown in Figure 3-2 through Figure 3-4. The
drawings include dimensions necessary to design a thermal solution for the processor
including:
1. Package reference and tolerance dimensions (total height, length, width, an so
forth)
2. IHS parallelism and tilt
3. Land dimensions
4. Top-side and back-side component keepout dimensions
5. Reference datums
Note:
All drawing dimensions are in mm [in.].
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
33
Mechanical Specifications
Figure 3-2. Processor Package Drawing (Sheet 1 of 3)
Note: Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the
cooling solution is available in the processor Thermal/Mechanical Design Guidelines.
34
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Mechanical Specifications
Figure 3-3. Processor Package Drawing (Sheet 2 of 3)
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
35
Mechanical Specifications
Figure 3-4. Processor Package Drawing (Sheet 3 of 3)
36
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Mechanical Specifications
3.2
3.3
Processor Component Keepout Zones
The processor may contain components on the substrate that define component
keepout zone requirements. A thermal and mechanical solution design must not intrude
into the required keepout zones. Decoupling capacitors are typically mounted to either
the topside or land-side of the package substrate. See Figure 3-4 for keepout zones.
Package Loading Specifications
Table 3-1 provides dynamic and static load specifications for the processor package.
These mechanical load limits should not be exceeded during heatsink assembly,
mechanical stress testing or standard drop and shipping conditions. The heatsink
attach solutions must not include continuous stress onto the processor with the
exception of a uniform load to maintain the heatsink-to-processor thermal interface.
Also, any mechanical system or component testing should not exceed these limits. The
processor package substrate should not be used as a mechanical reference or load-
bearing surface for thermal or mechanical solutions. Please refer to the Dual-Core
Intel® Xeon® Processor 5000 Series Thermal/Mechanical Design Guidelines for further
details.
Table 3-1.
Package Loading Specifications
Board
Thickness
Parameter
R
Min
Max
Unit
Notes
Static
Compressive Load
Apply for all
board thickness
from 1.57 mm
(0.062”) to
2.54 mm
25mm
<R<
45mm
80
18
133
30
N
lbf
1, 2, 3, 9,
10, 11,
12, 13
R>45mm
80
18
311
70
N
lbf
(0.100”)
Dynamic
Compressive Load
NA
NA
NA
311 N (max static
compressive load) +
222 N dynamic loading
N
1, 3, 4, 5,
6
lbf
70 lbf (max static
compressive load) +
50 lbf dynamic loading
Transient Bend
Limits
1.57 mm
0.062”
NA
NA
750
µε
1,3,7,8
2.16 mm
0.085”
700
650
2.54 mm
0.100”
Notes:
1.
These specifications apply to uniform compressive loading in a direction perpendicular to the IHS top
surface.
2.
This is the minimum and maximum static force that can be applied by the heatsink and retention solution
to maintain the heatsink and processor interface.
3.
4.
5.
Loading limits are for the LGA771 socket.
Dynamic compressive load applies to all board thickness.
Dynamic loading is defined as an 11 ms duration average load superimposed on the static load
requirement.
6.
Test condition used a heatsink mass of 1 lbm with 50 g acceleration measured at heatsink mass. The
dynamic portion of this specification in the product application can have flexibility in specific values, but the
ultimate product of mass times acceleration should not exceed this dynamic load.
Transient bend is defined as the transient board deflection during manufacturing such as board assembly
and system integration. It is a relatively slow bending event compared to shock and vibration tests.
For more information on the transient bend limits, please refer to the MAS document entitled
7.
8.
®
Manufacturing with Intel Components using 771-land LGA Package that Interfaces with the Motherboard
via a LGA771 Socket.
®
®
9.
Refer to the Dual-Core Intel Xeon Processor 5000 Series Thermal/Mechanical Design Guidelines for
information on heatsink clip load metrology.
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
37
Mechanical Specifications
10. R is defined as the radial distance from the center of the LGA771 socket ball array to the center of heatsink
load reaction point closest to the socket.
11. Applies to populated sockets in fully populated and partially populated socket configurations.
12. Through life or product. Condition must be satisfied at the beginning of life and at the end of life.
13. Rigid back is not allowed. The board should flex in the enabled configuration.
3.4
Package Handling Guidelines
Table 3-2 includes a list of guidelines on a package handling in terms of recommended
maximum loading on the processor IHS relative to a fixed substrate. These package
handling loads may be experienced during heatsink removal.
Table 3-2.
Package Handling Guidelines
Parameter
Maximum Recommended
Units
Notes
Shear
311
70
N
lbf
1,4,5
Tensile
Torque
111
25
N
lbf
2,4,5
3,4,5
3.95
35
N-m
LBF-in
Notes:
1.
2.
3.
A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface.
A tensile load is defined as a pulling load applied to the IHS in a direction normal to the IHS surface.
A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the IHS top
surface.
4.
5.
These guidelines are based on limited testing for design characterization and incidental applications (one
time only).
Handling guidelines are for the package only and do not include the limits of the processor socket.
3.5
3.6
Package Insertion Specifications
The Dual-Core Intel Xeon Processor 5000 Series can be inserted and removed 15 times
from an LGA771 socket.
Processor Mass Specifications
The typical mass of the Dual-Core Intel Xeon Processor 5000 series is 21.5 grams [0.76
oz.]. This includes all components which make up the entire processor product.
3.7
Processor Materials
The Dual-Core Intel Xeon Processor 5000 series are assembled from several
components. The basic material properties are described in Table 3-3.
Table 3-3.
Processor Materials
Component
Material
Integrated Heat Spreader (IHS)
Substrate
Nickel over copper
Fiber-reinforced resin
Gold over nickel
Substrate Lands
38
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Mechanical Specifications
3.8
Processor Markings
Figure 3-5 and Figure 3-6 shows the topside markings on the processor. This diagram
aids in the identification of the Dual-Core Intel Xeon Processor 5000 series.
Figure 3-5. Dual-Core Intel Xeon Processor 5000 Series Top-side Markings
Legend:
Mark Text (Production Mark):
3733DP/4M/1066
Intel ® Xeon ®
5080 SXXX COO
i (M) © ‘05
GROUP1LINE1
GROUP1LINE2
GROUP1LINE3
GROUP1LINE4
GROUP1LINE5
GROUP1LINE1
GROUP1LINE2
GROUP1LINE3
GROUP1LINE4
GROUP1LINE5
FPO
ATPO
S/N
Figure 3-6. Dual-Core Intel Xeon Processor 5063 (MV) Top-side Markings
Legend:
Mark Text (Production Mark):
3200DP/4M/1066/MV
Intel ® Xeon ®
5063 SXXX COO
i (M) © ‘05
GROUP1LINE1
GROUP1LINE2
GROUP1LINE3
GROUP1LINE4
GROUP1LINE5
GROUP1LINE1
GROUP1LINE2
GROUP1LINE3
GROUP1LINE4
GROUP1LINE5
FPO
ATPO
S/N
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
39
Mechanical Specifications
3.9
Processor Land Coordinates
Figure 3-7 and Figure 3-8 show the top and bottom view of the processor land
coordinates, respectively. The coordinates are referred to throughout the document to
identify processor lands.
Figure 3-7. Processor Land Coordinates, Top View
VCC / VSS
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2 1
AN
AM
AL
AK
AJ
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
AH
AG
AF
AE
AD
AC
AB
AA
Y
Address /
Common Clock /
Async
W
W
V
Socket 771
Quadrants
Top View
V
U
U
T
T
R
R
P
N
M
L
P
N
M
L
K
J
K
J
H
G
F
H
G
F
E
D
C
B
A
E
D
C
B
A
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2 1
Data
VTT / Clocks
40
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Mechanical Specifications
Figure 3-8. Processor Land Coordinates, Bottom View
VCC / VSS
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
Address /
Common Clock /
Async
W
V
W
V
Socket 771
Quadrants
Bottom View
U
U
T
T
R
R
P
P
N
N
M
M
L
L
K
K
J
J
H
H
G
G
F
F
E
E
D
D
C
C
B
B
A
A
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Data
VTT / Clocks
§
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
41
Mechanical Specifications
42
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Land Listing
4 Land Listing
4.1
Dual-Core Intel Xeon Processor 5000 Series Land
Assignments
This section provides sorted land list in Table 4-1 and Table 4-2. Table 4-1 is a listing of
all processor lands ordered alphabetically by land name. Table 4-2 is a listing of all
processor lands ordered by land number.
4.1.1
Land Listing by Land Name
Table 4-1.
Land Listing by Land Name (Sheet 1 of 9)
Land SignalBuffer
Land SignalBuffer
Land Name
Direction
Land Name
Direction
No.
Type
No.
Type
A03#
A04#
A05#
A06#
A07#
A08#
A09#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
A32#
COMP5
COMP6
COMP7
D00#
D01#
M5
P6
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Power/Other
Power/Other
Power/Other
Source Sync
Source Sync
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input
A33#
A34#
AH5
AJ5
AJ6
K3
Source Sync
Source Sync
Source Sync
ASync GTL+
Common Clk
Source Sync
Source Sync
Common Clk
Common Clk
Clk
Input/Output
Input/Output
Input/Output
Input
L5
A35#
L4
A20M#
ADS#
M4
R4
D2
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input
ADSTB0#
ADSTB1#
AP0#
R6
T5
AD5
U2
U6
T4
AP1#
U3
U5
BCLK0
BCLK1
BINIT#
BNR#
F28
G28
AD3
C2
U4
Clk
Input
V5
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input
V4
W5
AB6
W6
Y6
BPM0#
BPM1#
BPM2#
BPM3#
BPM4#
BPM5#
BPRI#
BR0#
AJ2
AJ1
AD2
AG2
AF2
AG3
G8
Y4
AA4
AD6
AA5
AB5
AC5
AB4
AF5
AF4
AG6
AG4
AG5
AH4
T2
F3
Input/Output
Input
BR1#
H5
BSEL0
BSEL1
BSEL2
COMP0
COMP1
COMP2
COMP3
COMP4
D40#
G29
H30
G30
A13
T1
Output
Output
Output
Input
Input
G2
Input
R1
Input
J2
Input
E19
F20
E21
F21
G21
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Y3
Input
D41#
AE3
B4
Input
D42#
Input/Output
Input/Output
D43#
C5
D44#
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
43
Land Listing
Table 4-1.
Land Listing by Land Name (Sheet 2 of 9)
Land SignalBuffer
Land SignalBuffer
Land Name
Direction
Land Name
Direction
No.
Type
No.
Type
D02#
D03#
A4
C6
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
ASync GTL+
ASync GTL+
Power/Other
Power/Other
Power/Other
Power/Other
Common Clk
Common Clk
ASync GTL+
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Output
D45#
D46#
E22
D22
G22
D20
D17
A14
C15
C14
B15
C18
B16
A17
B18
C21
B21
B19
A19
A22
B22
A8
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Power/Other
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Output
D04#
A5
D47#
D05#
B6
D48#
D06#
B7
D49#
D07#
A7
D50#
D08#
A10
A11
B10
C11
D8
D51#
D09#
D52#
D10#
D53#
D11#
D54#
D12#
D55#
D13#
B12
C12
D11
G9
D56#
D14#
D57#
D15#
D58#
D16#
D59#
D17#
F8
D60#
D18#
F9
D61#
D19#
E9
D62#
D20#
D7
D63#
D21#
E10
D10
F11
F12
D13
E13
G13
F14
G14
F15
G15
G16
E15
E16
G18
G17
F17
F18
E18
C17
R3
DBI0#
D22#
DBI1#
G11
D19
C20
AC2
B2
D23#
DBI2#
D24#
DBI3#
D25#
DBR#
D26#
DBSY#
DEFER#
DP0#
Input/Output
Input
D27#
G7
D28#
J16
H15
H16
J17
C1
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
D29#
DP1#
D30#
DP2#
D31#
DP3#
D32#
DRDY#
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
D33#
C8
D34#
G12
G20
A16
B9
D35#
D36#
D37#
D38#
E12
G19
E23
E24
E5
D39#
DSTBP3#
FERR#/PBE#
FORCEPR#
GTLREF_ADD_C0
GTLREF_ADD_C1
GTLREF_DATA_C0
GTLREF_DATA_C1
HIT#
AK6
H1
Input
Input
E6
H2
Input
E7
G10
F2
Input
F23
F29
F6
Input
D4
Input/Output
Input/Output
Output
HITM#
IERR#
E4
G5
AB2
G6
44
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Land Listing
Table 4-1.
Land Listing by Land Name (Sheet 3 of 9)
Land SignalBuffer
Land SignalBuffer
Land Name
Direction
Land Name
Direction
No.
Type
No.
Type
IGNNE#
INIT#
N2
P3
ASync GTL+
ASync GTL+
ASync GTL+
ASync GTL+
Power/Other
Power/Other
Common Clk
Common Clk
Power/Other
Power/Other
ASync GTL+
Power/Other
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Input
Input
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESET#
RS0#
J3
N4
LINT0
K1
Input
N5
LINT1
L1
Input
P5
LL_ID0
V2
Output
W2
Y1
LL_ID1
AA2
C3
Output
I
LOCK#
Input/Output
Input/Output
Output
G23
B3
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Power/Other
ASync GTL+
ASync GTL+
TAP
Input
Input
Input
Input
Input
Output
Input
Input
Input
Input
Output
MCERR#
MS_ID0
MS_ID1
PROCHOT#
PWRGOOD
REQ0#
AB3
W1
V1
RS1#
F5
Output
RS2#
A3
AL2
N1
Output
RSP#
H4
Input
SKTOCC#
SMI#
AE8
P2
K4
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
REQ1#
J5
STPCLK#
TCK
M3
REQ2#
M6
AE1
AD1
AF1
AH2
F26
W3
F25
G25
G27
G26
G24
F24
G3
REQ3#
K6
TDI
TAP
REQ4#
J6
TDO
TAP
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
THERMDC2
THERMTRIP#
TMS
A20
AC4
AE4
AE6
AK3
AJ3
AM5
AN5
AN6
B13
C9
TEST_BUS
TESTHI00
TESTHI01
TESTHI02
TESTHI03
TESTHI04
TESTHI05
TESTHI06
TESTHI07
TESTHI08
TESTHI09
TESTHI10
TESTHI11
THERMDA
THERMDA2
THERMDC
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
G4
D1
P1
D14
D16
D23
E1
L2
AL1
AJ7
AK1
AF8
AF9
AH7
M2
Power/Other
ASync GTL+
TAP
Output
Output
Input
VCC
AC1
E3
VCC
AG11 Power/Other
AG12 Power/Other
AG14 Power/Other
AG15 Power/Other
AG18 Power/Other
AG19 Power/Other
AG21 Power/Other
AG22 Power/Other
AG25 Power/Other
AG26 Power/Other
AG27 Power/Other
AG28 Power/Other
AG29 Power/Other
TRDY#
Common Clk
TAP
Input
VCC
TRST#
AG1
AA8
AB8
Input
VCC
VCC
Power/Other
Power/Other
VCC
VCC
VCC
VCC
AC23 Power/Other
AC24 Power/Other
AC25 Power/Other
AC26 Power/Other
AC27 Power/Other
AC28 Power/Other
AC29 Power/Other
AC30 Power/Other
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
45
Land Listing
Table 4-1.
Land Listing by Land Name (Sheet 4 of 9)
Land SignalBuffer
Land SignalBuffer
No. Type
Land Name
Direction
Land Name
Direction
No.
Type
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AC8
Power/Other
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AG30 Power/Other
AD23 Power/Other
AD24 Power/Other
AD25 Power/Other
AD26 Power/Other
AD27 Power/Other
AD28 Power/Other
AD29 Power/Other
AD30 Power/Other
AG8
AG9
Power/Other
Power/Other
AH11 Power/Other
AH12 Power/Other
AH14 Power/Other
AH15 Power/Other
AH18 Power/Other
AH19 Power/Other
AH21 Power/Other
AH22 Power/Other
AH25 Power/Other
AH26 Power/Other
AH27 Power/Other
AH28 Power/Other
AH29 Power/Other
AH30 Power/Other
AD8
Power/Other
AE11 Power/Other
AE12 Power/Other
AE14 Power/Other
AE15 Power/Other
AE18 Power/Other
AE19 Power/Other
AE21 Power/Other
AE22 Power/Other
AE23 Power/Other
AH8
AH9
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AE9
Power/Other
AJ11
AJ12
AJ14
AJ15
AJ18
AJ19
AJ21
AJ22
AJ25
AF11 Power/Other
AF12 Power/Other
AF14 Power/Other
AF15 Power/Other
AF18 Power/Other
AF19 Power/Other
AF21 Power/Other
AF22 Power/Other
AJ26
AJ8
Power/Other
Power/Other
Power/Other
AN12 Power/Other
AN14 Power/Other
AN15 Power/Other
AN18 Power/Other
AN19 Power/Other
AN21 Power/Other
AN22 Power/Other
AN25 Power/Other
AN26 Power/Other
AJ9
AK11 Power/Other
AK12 Power/Other
AK14 Power/Other
AK15 Power/Other
AK18 Power/Other
AK19 Power/Other
AK21 Power/Other
AK22 Power/Other
AK25 Power/Other
AK26 Power/Other
AN8
AN9
J10
J11
J12
J13
J14
J15
J18
J19
J20
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AK8
AK9
Power/Other
Power/Other
AL11 Power/Other
AL12 Power/Other
AL14 Power/Other
AL15 Power/Other
AL18 Power/Other
46
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Land Listing
Table 4-1.
Land Listing by Land Name (Sheet 5 of 9)
Land SignalBuffer
Land SignalBuffer
Land Name
Direction
Land Name
Direction
No.
Type
No.
Type
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AL19 Power/Other
AL21 Power/Other
AL22 Power/Other
AL25 Power/Other
AL26 Power/Other
AL29 Power/Other
AL30 Power/Other
VCC
VCC
J21
J22
J23
J24
J25
J26
J27
J28
J29
J30
J8
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
VCC
VCC
VCC
VCC
AL9
Power/Other
VCC
AM11 Power/Other
AM12 Power/Other
AM14 Power/Other
AM15 Power/Other
AM18 Power/Other
AM19 Power/Other
AM21 Power/Other
AM22 Power/Other
AM25 Power/Other
AM26 Power/Other
AM29 Power/Other
AM30 Power/Other
VCC
VCC
VCC
VCC
J9
VCC
K23
K24
K25
K26
K27
K28
K29
K30
K8
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AM8
AM9
Power/Other
Power/Other
VCC
VCC
L8
AN11 Power/Other
VCC
M23
W28
W29
W30
W8
M24
M25
M26
M27
M28
M29
M30
M8
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
VCC
VCC
VCC
VCC
Y23
Y24
Y25
Y26
Y27
Y28
Y29
Y30
Y8
VCC
VCC
VCC
N23
N24
N25
N26
N27
N28
N29
N30
N8
VCC
VCC
VCC
VCC
VCC
VCC_DIE_SENSE
VCC_DIE_SENSE2
VCCA
VCCIOPLL
VID0
VID1
VID2
VID3
VID4
VID5
VID_SELECT
VSS
AN3
AL8
A23
C23
AM2
AL5
AM3
AL6
AK4
AL4
AN7
A12
Output
Output
Input
Input
P8
Output
Output
Output
Output
Output
Output
Output
R8
T23
T24
T25
T26
T27
T28
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
47
Land Listing
Table 4-1.
Land Listing by Land Name (Sheet 6 of 9)
Land SignalBuffer
Land SignalBuffer
Land Name
Direction
Land Name
Direction
No.
Type
No.
Type
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
T29
T30
T8
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A15
A18
A2
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
U23
U24
U25
U26
U27
U28
U29
U30
U8
A21
A24
A6
A9
AA23 Power/Other
AA24 Power/Other
AA25 Power/Other
AA26 Power/Other
AA27 Power/Other
AA28 Power/Other
AA29 Power/Other
V8
W23
W24
W25
W26
W27
AB1
AA3
Power/Other
AA30 Power/Other
AA6
AA7
Power/Other
Power/Other
AF30 Power/Other
AB23 Power/Other
AB24 Power/Other
AB25 Power/Other
AB26 Power/Other
AB27 Power/Other
AB28 Power/Other
AB29 Power/Other
AB30 Power/Other
AF6
AF7
Power/Other
Power/Other
AG10 Power/Other
AG13 Power/Other
AG16 Power/Other
AG17 Power/Other
AG20 Power/Other
AG23 Power/Other
AG24 Power/Other
AB7
AC3
AC6
AC7
AD4
AD7
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AG7
AH1
Power/Other
Power/Other
AH10 Power/Other
AH13 Power/Other
AH16 Power/Other
AH17 Power/Other
AH20 Power/Other
AH23 Power/Other
AH24 Power/Other
AE10 Power/Other
AE13 Power/Other
AE16 Power/Other
AE17 Power/Other
AE2
Power/Other
AH3
AH6
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AE20 Power/Other
AE24 Power/Other
AE25 Power/Other
AE26 Power/Other
AE27 Power/Other
AE28 Power/Other
AE29 Power/Other
AE30 Power/Other
AJ10
AJ13
AJ16
AJ17
AJ20
AJ23
AJ24
AJ27
AJ28
AE5
AE7
Power/Other
Power/Other
48
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Land Listing
Table 4-1.
Land Listing by Land Name (Sheet 7 of 9)
Land SignalBuffer
Land SignalBuffer
Land Name
Direction
Land Name
Direction
No.
Type
No.
Type
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AF10 Power/Other
AF13 Power/Other
AF16 Power/Other
AF17 Power/Other
AF20 Power/Other
AF23 Power/Other
AF24 Power/Other
AF25 Power/Other
AF26 Power/Other
AF27 Power/Other
AF28 Power/Other
AF29 Power/Other
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ29
AJ30
AJ4
Power/Other
Power/Other
Power/Other
AK10 Power/Other
AK13 Power/Other
AK16 Power/Other
AK17 Power/Other
AK2
Power/Other
AK20 Power/Other
AK23 Power/Other
AK24 Power/Other
AK27 Power/Other
AK28 Power/Other
AF3
Power/Other
AK29 Power/Other
AK30 Power/Other
C10
C13
C16
C19
C22
C24
C4
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AK5
AK7
Power/Other
Power/Other
AL10 Power/Other
AL13 Power/Other
AL16 Power/Other
AL17 Power/Other
AL20 Power/Other
AL23 Power/Other
AL24 Power/Other
AL27 Power/Other
AL28 Power/Other
C7
D12
D15
D18
D21
D24
D3
AL3
Power/Other
Power/Other
AM1
D5
AM10 Power/Other
AM13 Power/Other
AM16 Power/Other
AM17 Power/Other
AM20 Power/Other
AM23 Power/Other
AM24 Power/Other
AM27 Power/Other
AM28 Power/Other
D6
D9
E11
E14
E17
E2
E20
E25
E26
E27
E28
E29
E8
AM4
AM7
AN1
Power/Other
Power/Other
Power/Other
AN10 Power/Other
AN13 Power/Other
AN16 Power/Other
AN17 Power/Other
F1
F10
F13
F16
F19
F22
F4
AN2
Power/Other
AN20 Power/Other
AN23 Power/Other
AN24 Power/Other
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
49
Land Listing
Table 4-1.
Land Listing by Land Name (Sheet 8 of 9)
Land SignalBuffer
Land SignalBuffer
Land Name
Direction
Land Name
Direction
No.
Type
No.
Type
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
B1
B11
B14
B17
B20
B24
B5
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
VSS
F7
G1
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
H10
H11
H12
H13
H14
H17
P28
P29
P30
P4
VSS
VSS
VSS
VSS
B8
VSS
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H29
H3
VSS
VSS
VSS
VSS
VSS
P7
VSS
R2
VSS
R23
R24
R25
R26
R27
R28
R29
R30
R5
VSS
VSS
VSS
VSS
VSS
VSS
H6
VSS
H7
VSS
H8
VSS
R7
H9
VSS
T3
J4
VSS
T6
J7
VSS
T7
K2
VSS
U1
K5
VSS
U7
K7
VSS
V23
V24
V25
V26
V27
V28
V29
V3
L23
L24
L25
L26
L27
L28
L29
L3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
V30
V6
L30
L6
VSS
VSS
V7
L7
VSS
W4
W7
Y2
M1
VSS
M7
VSS
N3
VSS
Y5
N6
VSS
Y7
N7
VSS_DIE_SENSE
VSS_DIE_SENSE2
VSSA
AN4
AL7
B23
Output
Output
Input
P23
P24
50
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Land Listing
Table 4-1.
Land Listing by Land Name (Sheet 9 of 9)
Land SignalBuffer
Land SignalBuffer
Land Name
Direction
Land Name
Direction
No.
Type
No.
Type
VSS
VSS
VSS
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
P25
P26
P27
B26
B27
B28
B29
B30
C25
C26
C27
C28
C29
C30
D25
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VTT
VTT
A25
A26
B25
D26
D27
D28
D29
D30
E30
F30
AA1
J1
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT_OUT
VTT_OUT
RESERVED
VTTPWRGD
Output
Output
F27
AM6
Power/Other
Input
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
51
Land Listing
4.1.2
Land Listing by Land Number
Table 4-2.
Land Listing by Land Number (Sheet 1 of 9)
Land
No.
SignalBuffer
Type
Land
No.
SignalBuffer
Type
Land Name
Direction
Land Name
Direction
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A2
D08#
D09#
VSS
Source Sync
Source Sync
Power/Other
Power/Other
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Power/Other
Input/Output
Input/Output
AB1
AB2
VSS
IERR#
VSS
Power/Other
ASync GTL+
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Common Clk
Power/Other
Source Sync
Source Sync
Source Sync
Power/Other
Power/Other
TAP
Output
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB3
COMP0
D50#
VSS
Input
VSS
Input/Output
VSS
VSS
DSTBN3#
D56#
VSS
Input/Output
Input/Output
VSS
VSS
VSS
D61#
VSS
Input/Output
MCERR#
VSS
Input/Output
AB30
AB4
A20
A21
A22
A23
A24
A25
A26
A3
RESERVED
VSS
A26#
A24#
A17#
VSS
Input/Output
Input/Output
Input/Output
Power/Other
Source Sync
Power/Other
Power/Other
Power/Other
Power/Other
Common Clk
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Sync
Source Sync
Power/Other
Power/Other
Power/Other
Common Clk
Power/Other
Power/Other
Source Sync
Source Sync
AB5
D62#
VCCA
VSS
Input/Output
Input
AB6
AB7
AB8
VCC
VTT
AC1
TMS
Input
VTT
AC2
DBR#
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Output
RS2#
D02#
D04#
VSS
Input
AC23
AC24
AC25
AC26
AC27
AC28
AC29
AC3
A4
Input/Output
Input/Output
VCC
A5
VCC
A6
VCC
A7
D07#
DBI0#
VSS
Input/Output
Input/Output
VCC
A8
VCC
A9
VCC
AA1
AA2
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AA3
AA30
AA4
AA5
AA6
AA7
AA8
AD3
AD30
AD4
AD5
AD6
VTT_OUT
LL_ID1
VSS
Output
Output
VSS
AC30
AC4
VCC
RESERVED
A25#
VSS
VSS
AC5
Source Sync
Power/Other
Power/Other
Power/Other
TAP
Input/Output
VSS
AC6
VSS
AC7
VSS
VSS
AC8
VCC
VSS
AD1
TDI
Input
VSS
AD2
BPM2#
VCC
Common Clk
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Input/Output
VSS
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AF15
AF16
AF17
AF18
AF19
VSS
VCC
A21#
A23#
VSS
Input/Output
Input/Output
VCC
VCC
VCC
VSS
VCC
VCC
VCC
BINIT#
VCC
Input/Output
VCC
VSS
VSS
VSS
ADSTB1#
A22#
Input/Output
Input/Output
VCC
VCC
52
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Land Listing
Table 4-2.
Land Listing by Land Number (Sheet 2 of 9)
Land
No.
SignalBuffer
Type
Land
No.
SignalBuffer
Type
Land Name
Direction
Land Name
Direction
AD7
AD8
VSS
VCC
Power/Other
Power/Other
TAP
AF2
AF20
AF21
AF22
AF23
AF24
AF25
AF26
AF27
AF28
AF29
AF3
BPM4#
VSS
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A28#
A27#
VSS
VSS
VCC
VCC
TRST#
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
BPM3#
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
BPM0#
Common Clk
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Sync
Source Sync
Power/Other
Power/Other
Power/Other
Power/Other
TAP
Input/Output
AE1
TCK
Input
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE2
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
AF30
AF4
VSS
Input/Output
Input/Output
AE20
AE21
AE22
AE23
AE24
AE25
AE26
AE27
AE28
AE29
AE3
VSS
AF5
VCC
AF6
VCC
AF7
VCC
AF8
VSS
AF9
VSS
AG1
Input
VSS
AG10
AG11
AG12
AG13
AG14
AG15
AG16
AG17
AG18
AG19
AG2
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Common Clk
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Common Clk
VSS
VSS
VSS
COMP7
VSS
Input
AE30
AE4
RESERVED
VSS
AE5
Power/Other
AE6
RESERVED
VSS
AE7
Power/Other
Power/Other
Power/Other
TAP
AE8
SKTOCC#
VCC
Output
Output
Input/Output
AE9
AG20
AG21
AG22
AG23
AG24
AG25
AG26
AJ11
AJ12
AJ13
AJ14
AJ15
AJ16
AJ17
AJ18
AJ19
AJ2
AF1
TDO
AF10
AF11
AF12
AF13
AF14
AG27
AG28
AG29
AG3
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Common Clk
Power/Other
Source Sync
Source Sync
Source Sync
Power/Other
Power/Other
VCC
VCC
VSS
VCC
VCC
VCC
VCC
BPM5#
VCC
Input/Output
AG30
AG4
A30#
A31#
A29#
VSS
Input/Output
Input/Output
Input/Output
AG5
AG6
AG7
AG8
VCC
Input/Output
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
53
Land Listing
Table 4-2.
Land Listing by Land Number (Sheet 3 of 9)
Land
No.
SignalBuffer
Type
Land
No.
SignalBuffer
Type
Land Name
Direction
Land Name
Direction
AG9
AH1
VCC
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Sync
Source Sync
Power/Other
Power/Other
Power/Other
Power/Other
Common Clk
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AJ20
AJ21
AJ22
AJ23
AJ24
AJ25
AJ26
AJ27
AJ28
AJ29
AJ3
VSS
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AH10
AH11
AH12
AH13
AH14
AH15
AH16
AH17
AH18
AH19
AH2
VSS
VCC
VCC
VSS
VCC
VSS
VSS
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VCC
RESERVED
VSS
VCC
AJ30
AJ4
Power/Other
Power/Other
Source Sync
Source Sync
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
TEST_BUS
VSS
VSS
AH20
AH21
AH22
AH23
AH24
AH25
AH26
AH27
AH28
AH29
AH3
AJ5
A34#
A35#
THERMDA2
VCC
Input/Output
Input/Output
Output
VCC
AJ6
VCC
AJ7
VSS
AJ8
VSS
AJ9
VCC
VCC
AK1
THERMDC
VSS
Output
VCC
AK10
AK11
AK12
AK13
AK14
AK15
AK16
AK17
AK18
AK19
AK2
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VCC
AH30
AH4
VCC
VCC
A32#
A33#
VSS
Input/Output
Input/Output
VSS
AH5
VSS
AH6
VCC
AH7
THERMDC2
VCC
Output
VCC
AH8
VSS
AH9
VCC
AK20
AK21
AK22
AL8
VSS
AJ1
BPM1#
VSS
Input/Output
VCC
AJ10
AK23
AK24
AK25
AK26
AK27
AK28
AK29
AK3
VCC
VSS
VCC_DIE_SENSE2
VCC
Output
VSS
AL9
VCC
AM1
VSS
VCC
AM10
AM11
AM12
AM13
AM14
AM15
AM16
AM17
AM18
AM19
AM2
VSS
VSS
VCC
VSS
VCC
VSS
VSS
RESERVED
VSS
VCC
AK30
AK4
Power/Other
Power/Other
Power/Other
ASync GTL+
Power/Other
Power/Other
Power/Other
VCC
VID4
VSS
Output
Input
VSS
AK5
VSS
AK6
FORCEPR#
VSS
VCC
AK7
VCC
AK8
VCC
VID0
VSS
Output
AK9
VCC
AM20
54
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Land Listing
Table 4-2.
Land Listing by Land Number (Sheet 4 of 9)
Land
No.
SignalBuffer
Type
Land
No.
SignalBuffer
Type
Land Name
Direction
Land Name
Direction
AL1
AL10
AL11
AL12
AL13
AL14
AL15
AL16
AL17
AL18
AL19
AL2
THERMDA
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
ASync GTL+
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Output
AM21
AM22
AM23
AM24
AM25
AM26
AM27
AM28
AM29
AM3
AM30
AM4
AM5
AM6
AM7
AM8
AM9
AN1
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
B8
VCC
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
VSS
VCC
VSS
VSS
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VCC
VCC
VID2
VCC
Output
Input
VCC
PROCHOT#
VSS
Output
VSS
AL20
AL21
AL22
AL23
AL24
AL25
AL26
AL27
AL28
AL29
AL3
RESERVED
VTTPWRGD
VSS
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Sync
Common Clk
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Common Clk
Source Sync
Source Sync
Power/Other
Power/Other
Power/Other
Power/Other
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VSS
VCC
VSS
VCC
VCC
VSS
VSS
VCC
AL30
AL4
VCC
VCC
VID5
Output
Output
Output
Output
VSS
AL5
VID1
VSS
AL6
VID3
VCC
AL7
VSS_DIE_SENSE2
VSS
VCC
AN2
VSS
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN3
VSS
B9
DSTBP0#
DRDY#
VSS
Input/Output
Input/Output
VCC
C1
VCC
C10
VSS
C11
D11#
D14#
VSS
Input/Output
Input/Output
VSS
C12
VCC
C13
VCC
C14
D52#
D51#
VSS
Input/Output
Input/Output
VCC_DIE_SENSE
VSS_DIE_SENSE
RESERVED
RESERVED
VID_SELECT
VCC
Output
Output
C15
AN4
C16
AN5
C17
DSTBP3#
D54#
VSS
Input/Output
Input/Output
AN6
C18
AN7
Power/Other
Power/Other
Power/Other
Power/Other
Source Sync
Power/Other
Source Sync
Output
C19
AN8
C2
BNR#
DBI3#
D58#
VSS
Input/Output
Input/Output
Input/Output
AN9
VCC
C20
B1
VSS
C21
B10
D10#
VSS
Input/Output
Input/Output
C22
B11
C23
VCCIOPLL
VSS
Input
B12
D13#
RESERVED
C24
B13
C25
VTT
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
55
Land Listing
Table 4-2.
Land Listing by Land Number (Sheet 5 of 9)
Land
No.
SignalBuffer
Type
Land
No.
SignalBuffer
Type
Land Name
Direction
Land Name
Direction
B14
B15
B16
B17
B18
B19
B2
VSS
D53#
D55#
VSS
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Common Clk
Power/Other
Source Sync
Source Sync
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Common Clk
Power/Other
Source Sync
Power/Other
Source Sync
Source Sync
Common Clk
Source Sync
Power/Other
Source Sync
C26
C27
C28
C29
C3
VTT
VTT
Power/Other
Power/Other
Power/Other
Power/Other
Common Clk
Power/Other
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Input/Output
Input/Output
VTT
VTT
D57#
D60#
DBSY#
VSS
Input/Output
Input/Output
Input/Output
LOCK#
VTT
Input/Output
C30
C4
VSS
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B3
C5
D01#
Input/Output
Input/Output
D59#
D63#
VSSA
VSS
Input/Output
Input/Output
Input
C6
D03#
C7
VSS
C8
DSTBN0#
RESERVED
RESERVED
D22#
Input/Output
C9
VTT
D1
VTT
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
E4
Source Sync
Source Sync
Power/Other
Source Sync
Input/Output
Input/Output
VTT
D15#
VTT
VSS
VTT
D25#
Input/Output
RS0#
VTT
Input
RESERVED
VSS
B30
B4
Power/Other
D00#
VSS
Input/Output
RESERVED
D49#
B5
Source Sync
Power/Other
Source Sync
Common Clk
Input/Output
B6
D05#
D06#
ADS#
D48#
VSS
Input/Output
Input/Output
Input/Output
Input/Output
VSS
B7
DBI2#
HITM#
RESERVED
RESERVED
RESERVED
VSS
Input/Output
Input/Output
D2
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D3
E5
E6
D46#
RESERVED
VSS
Input/Output
E7
E8
Power/Other
Source Sync
Power/Other
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Power/Other
Source Sync
Source Sync
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Common Clk
Power/Other
Power/Other
Source Sync
Source Sync
Power/Other
E9
D19#
Input/Output
VTT
F1
VSS
VTT
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F2
VSS
VTT
D23#
Input/Output
Input/Output
VTT
D24#
VTT
VSS
VSS
D28#
Input/Output
Input/Output
D30
D4
VTT
D30#
HIT#
VSS
Input/Output
VSS
D5
D37#
Input/Output
Input/Output
D6
VSS
D38#
D7
D20#
D12#
VSS
Input/Output
Input/Output
VSS
D8
GTLREF_DATA_C1
D41#
Input
D9
F20
F21
F22
F23
F24
F25
F26
Input/Output
Input/Output
E1
RESERVED
D21#
VSS
D43#
E10
E11
E12
E13
E14
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Input/Output
VSS
RESERVED
TESTHI07
TESTHI02
TESTHI00
DSTBP1#
D26#
VSS
Input/Output
Input/Output
Power/Other
Power/Other
Power/Other
Input
Input
Input
56
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Land Listing
Table 4-2.
Land Listing by Land Number (Sheet 6 of 9)
Land
No.
SignalBuffer
Type
Land
No.
SignalBuffer
Type
Land Name
Direction
Land Name
Direction
E15
E16
E17
E18
E19
E2
D33#
D34#
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Power/Other
Source Sync
Source Sync
Input/Output
Input/Output
F27
F28
F29
F3
RESERVED
BCLK0
RESERVED
BR0#
VTT
Clk
Input
VSS
D39#
Input/Output
Input/Output
Common Clk
Power/Other
Power/Other
Common Clk
Input/Output
D40#
F30
F4
VSS
VSS
E20
E21
E22
E23
E24
E25
E26
E27
E28
E29
E3
VSS
F5
RS1#
RESERVED
VSS
Input
D42#
Input/Output
Input/Output
F6
D45#
F7
Power/Other
Source Sync
Source Sync
Power/Other
Power/Other
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Power/Other
Power/Other
Power/Other
Power/Other
Common Clk
Common Clk
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Common Clk
Common Clk
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
RESERVED
RESERVED
VSS
F8
D17#
D18#
VSS
Input/Output
Input/Output
F9
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Common Clk
Power/Other
Source Sync
Source Sync
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Source Sync
Common Clk
Power/Other
Power/Other
Power/Other
Power/Other
Clk
G1
VSS
G10
G11
G12
G13
G14
G15
H28
H29
H3
GTLREF_DATA_C0
DBI1#
DSTBN1#
D27#
D29#
D31#
VSS
Input
VSS
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
VSS
VSS
TRDY#
VTT
Input
E30
G16
G17
G18
G19
G2
D32#
Input/Output
Input/Output
Input/Output
Input/Output
Input
D36#
VSS
D35#
VSS
DSTBP2#
COMP2
DSTBN2#
D44#
H30
H4
BSEL1
RSP#
BR1#
VSS
Output
Input
Input
G20
G21
G22
G23
G24
G25
G26
G27
G28
G29
G3
Input/Output
Input/Output
Input/Output
Input
H5
H6
D47#
H7
VSS
RESET#
TESTHI06
TESTHI03
TESTHI05
TESTHI04
BCLK1
BSEL0
TESTHI08
BSEL2
TESTHI09
RESERVED
RESERVED
DEFER#
BPRI#
D16#
H8
VSS
Input
H9
VSS
Input
J1
VTT_OUT
VCC
Output
Input
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J2
Input
VCC
Input
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Output
VCC
Input
VCC
G30
G4
Output
VCC
Input
DP0#
DP3#
VCC
Input/Output
Input/Output
G5
G6
G7
Common Clk
Common Clk
Source Sync
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Common Clk
Input
Input
VCC
G8
COMP4
VCC
Input
G9
Input/Output
Input
J20
J21
J22
J23
J24
J25
J26
J27
H1
GTLREF_ADD_C0
VSS
VCC
H10
H11
H12
H13
H14
H15
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
DP1#
Input/Output
VCC
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
57
Land Listing
Table 4-2.
Land Listing by Land Number (Sheet 7 of 9)
Land
No.
SignalBuffer
Type
Land
No.
SignalBuffer
Type
Land Name
Direction
Land Name
Direction
H16
H17
H18
H19
H2
DP2#
VSS
Common Clk
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
ASync GTL+
Power/Other
Source Sync
Power/Other
Source Sync
Power/Other
Power/Other
ASync GTL+
ASync GTL+
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Sync
Source Sync
Power/Other
Power/Other
Power/Other
Power/Other
ASync GTL+
Power/Other
Power/Other
Power/Other
Power/Other
Input/Output
J28
J29
J3
VCC
VCC
Power/Other
Power/Other
VSS
RESERVED
VCC
VSS
J30
J4
Power/Other
Power/Other
Source Sync
Source Sync
Power/Other
Power/Other
Power/Other
ASync GTL+
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
ASync GTL+
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
GTLREF_ADD_C1
VSS
Input
VSS
H20
H21
H22
H23
H24
H25
H26
H27
K24
K25
K26
K27
K28
K29
K3
J5
REQ1#
REQ4#
VSS
Input/Output
Input/Output
VSS
J6
VSS
J7
VSS
J8
VCC
VSS
J9
VCC
VSS
K1
LINT0
VSS
Input
VSS
K2
VSS
K23
M7
M8
N1
VCC
VCC
VSS
VCC
VCC
VCC
PWRGOOD
IGNNE#
VCC
Input
Input
VCC
N2
VCC
N23
N24
N25
N26
N27
N28
N29
N3
VCC
VCC
A20M#
VCC
Input
VCC
K30
K4
VCC
REQ0#
VSS
Input/Output
Input/Output
VCC
K5
VCC
K6
REQ3#
VSS
VCC
K7
VSS
K8
VCC
N30
N4
VCC
L1
LINT1
TESTHI11
VSS
Input
Input
RESERVED
RESERVED
VSS
L2
N5
L23
L24
L25
L26
L27
L28
L29
L3
N6
Power/Other
Power/Other
Power/Other
Power/Other
ASync GTL+
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
ASync GTL+
Power/Other
Power/Other
VSS
N7
VSS
VSS
N8
VCC
VSS
P1
TESTHI10
SMI#
VSS
Input
Input
VSS
P2
VSS
P23
P24
P25
P26
P27
P28
P29
P3
VSS
VSS
VSS
VSS
L30
L4
VSS
VSS
A06#
A05#
VSS
Input/Output
Input/Output
VSS
L5
VSS
L6
VSS
L7
VSS
INIT#
VSS
Input
L8
VCC
P30
P4
M1
VSS
VSS
M2
THERMTRIP#
VCC
Output
P5
RESERVED
A04#
VSS
M23
M24
M25
M26
P6
Source Sync
Power/Other
Power/Other
Power/Other
Input/Output
Input
VCC
P7
VCC
P8
VCC
VCC
R1
COMP3
58
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Land Listing
Table 4-2.
Land Listing by Land Number (Sheet 8 of 9)
Land
No.
SignalBuffer
Type
Land
No.
SignalBuffer
Type
Land Name
Direction
Land Name
Direction
M27
M28
M29
M3
M30
M4
M5
M6
R3
VCC
VCC
Power/Other
Power/Other
Power/Other
ASync GTL+
Power/Other
Source Sync
Source Sync
Source Sync
ASync GTL+
Power/Other
Source Sync
Power/Other
Source Sync
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Sync
Source Sync
Power/Other
Power/Other
Power/Other
Power/Other
Common Clk
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Common Clk
Power/Other
Source Sync
Source Sync
Source Sync
Power/Other
Power/Other
Power/Other
R2
R23
R24
R25
R26
R27
R28
R29
V24
V25
V26
V27
V28
V29
V3
VSS
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Sync
Source Sync
Power/Other
Power/Other
Power/Other
Power/Other
VCC
VSS
STPCLK#
VCC
Input
VSS
VSS
A07#
A03#
REQ2#
FERR#/PBE#
VSS
Input/Output
Input/Output
Input/Output
Output
VSS
VSS
VSS
VSS
R30
R4
VSS
A08#
VSS
Input/Output
Input/Output
VSS
R5
VSS
R6
ADSTB0#
VSS
VSS
R7
VSS
R8
VCC
VSS
T1
COMP1
COMP5
VCC
Input
Input
V30
V4
VSS
T2
A15#
A14#
VSS
Input/Output
Input/Output
T23
T24
T25
T26
T27
T28
T29
T3
V5
VCC
V6
VCC
V7
VSS
VCC
V8
VCC
VCC
W1
MS_ID0
RESERVED
VCC
Output
VCC
W2
VCC
W23
W24
W25
W26
W27
W28
W29
W3
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Sync
Source Sync
Power/Other
Power/Other
VSS
VCC
T30
T4
VCC
VCC
A11#
A09#
VSS
Input/Output
Input/Output
VCC
T5
VCC
T6
VCC
T7
VSS
VCC
T8
VCC
TESTHI01
VCC
Input
U1
VSS
W30
W4
U2
AP0#
VCC
Input/Output
VSS
U23
U24
U25
U26
U27
U28
U29
U3
W5
A16#
A18#
VSS
Input/Output
Input/Output
VCC
W6
VCC
W7
VCC
W8
VCC
VCC
I
Y1
RESERVED
VSS
VCC
Y2
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
Y23
Y24
Y25
Y26
Y27
Y28
Y29
Y3
VCC
AP1#
VCC
Input/Output
VCC
U30
U4
VCC
A13#
A12#
A10#
VSS
Input/Output
Input/Output
Input/Output
VCC
U5
VCC
U6
VCC
U7
VCC
U8
VCC
COMP6
VCC
Input
V1
MS_ID1
Output
Y30
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
59
Land Listing
Table 4-2.
Land Listing by Land Number (Sheet 9 of 9)
Land
No.
SignalBuffer
Type
Land
No.
SignalBuffer
Type
Land Name
Direction
Land Name
Direction
V2
V23
Y6
LL_ID0
VSS
Power/Other
Power/Other
Source Sync
Power/Other
Power/Other
Output
Y4
Y5
A20#
VSS
Source Sync
Power/Other
Input/Output
A19#
VSS
Input/Output
Y7
Y8
VCC
§
60
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Signal Definitions
5 Signal Definitions
5.1
Signal Definitions
Table 5-1.
Signal Definitions (Sheet 1 of 8)
Name
Type
Description
Notes
36
A[35:3]#
I/O
A[35:3]# (Address) define a 2 -byte physical memory address space. In sub-phase
1 of the address phase, these signals transmit the address of a transaction. In sub-
phase 2, these signals transmit transaction type information. These signals must
connect the appropriate pins of all agents on the FSB. A[35:3]# are protected by
parity signals AP[1:0]#. A[35:3]# are source synchronous signals and are latched
into the receiving buffers by ADSTB[1:0]#.
3
On the active-to-inactive transition of RESET#, the processors sample a subset of the
A[35:3]# lands to determine their power-on configuration. See Section 7.1.
A20M#
I
If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit
20 (A20#) before looking up a line in any internal cache and before driving a read/
write transaction on the bus. Asserting A20M# emulates the 8086 processor's
address wrap-around at the 1 MB boundary. Assertion of A20M# is only supported in
real mode.
2
A20M# is an asynchronous signal. However, to ensure recognition of this signal
following an I/O write instruction, it must be valid along with the TRDY# assertion of
the corresponding I/O write bus transaction.
ADS#
I/O
I/O
ADS# (Address Strobe) is asserted to indicate the validity of the transaction address
on the A[35:3]# lands. All bus agents observe the ADS# activation to begin parity
checking, protocol checking, address decode, internal snoop, or deferred reply ID
match operations associated with the new transaction. This signal must connect the
appropriate pins on all Dual-Core Intel Xeon Processor 5000 series FSB agents.
3
3
ADSTB[1:0]#
Address strobes are used to latch A[35:3]# and REQ[4:0]# on their rising and falling
edge. Strobes are associated with signals as shown below.
Signals
Associated Strobes
REQ[4:0], A[16:3]#
A[35:17]#
ADSTB0#
ADSTB1#
AP[1:0]#
I/O
AP[1:0]# (Address Parity) are driven by the request initiator along with ADS#,
A[35:3]#, and the transaction type on the REQ[4:0]# signals. A correct parity signal
is high if an even number of covered signals are low and low if an odd number of
covered signals are low. This allows parity to be high when all the covered signals are
high. AP[1:0]# should connect the appropriate pins of all Dual-Core Intel Xeon
Processor 5000 series FSB agents. The following table defines the coverage model of
these signals.
3
Request Signals
Subphase 1
Subphase 2
A[35:24]#
A[23:3]#
AP0#
AP1#
AP1#
AP1#
AP0#
AP0#
REQ[4:0]#
BCLK[1:0]
I
The differential bus clock pair BCLK[1:0] (Bus Clock) determines the FSB frequency.
All processor FSB agents must receive these signals to drive their outputs and latch
their inputs.
3
All external timing parameters are specified with respect to the rising edge of BCLK0
crossing V
.
CROSS
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
61
Signal Definitions
Table 5-1.
Signal Definitions (Sheet 2 of 8)
Name
Type
Description
Notes
BINIT#
I/O
BINIT# (Bus Initialization) may be observed and driven by all processor FSB agents
and if used, must connect the appropriate pins of all such agents. If the BINIT#
driver is enabled during power on configuration, BINIT# is asserted to signal any bus
condition that prevents reliable future operation.
3
If BINIT# observation is enabled during power-on configuration (see Figure 7.1) and
BINIT# is sampled asserted, symmetric agents reset their bus LOCK# activity and
bus request arbitration state machines. The bus agents do not reset their I/O Queue
(IOQ) and transaction tracking state machines upon observation of BINIT# assertion.
Once the BINIT# assertion has been observed, the bus agents will re-arbitrate for
the FSB and attempt completion of their bus queue and IOQ entries.
If BINIT# observation is disabled during power-on configuration, a priority agent
may handle an assertion of BINIT# as appropriate to the error handling architecture
of the system.
BNR#
I/O
BNR# (Block Next Request) is used to assert a bus stall by any bus agent who is
unable to accept new bus transactions. During a bus stall, the current bus owner
cannot issue any new transactions.
Since multiple agents might need to request a bus stall at the same time, BNR# is a
wired-OR signal which must connect the appropriate pins of all processor FSB agents.
In order to avoid wired-OR glitches associated with simultaneous edge transitions
driven by multiple drivers, BNR# is activated on specific clock edges and sampled on
specific clock edges.
3
2
BPM[5:0]#
I/O
BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals.
They are outputs from the processor which indicate the status of breakpoints and
programmable counters used for monitoring processor performance. BPM[5:0]#
should connect the appropriate pins of all FSB agents.
BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. PRDY# is a
processor output used by debug tools to determine processor debug readiness.
BPM5# provides PREQ# (Probe Request) functionality for the TAP port. PREQ# is
used by debug tools to request debug operation of the processors.
BPM[5:4]# must be bussed to all bus agents. Please refer to the appropriate
platform design guidelines for more detailed information.
BPRI#
I
BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor FSB.
It must connect the appropriate pins of all processor FSB agents. Observing BPRI#
active (as asserted by the priority agent) causes all other agents to stop issuing new
requests, unless such requests are part of an ongoing locked operation. The priority
agent keeps BPRI# asserted until all of its requests are completed, then releases the
bus by deasserting BPRI#.
3
3
BR[1:0]#
BSEL[2:0]
I/O
O
The BR[1:0]# signals are sampled on the active-to-inactive transition of RESET#.
The signal which the agent samples asserted determines its agent ID. BR0# drives
the BREQ0# signal in the system and is used by the processor to request the bus.
These signals do not have on-die termination and must be terminated.
The BCLK[1:0] frequency select signals BSEL[2:0] are used to select the processor
input clock frequency. Table 2-2 defines the possible combinations of the signals and
the frequency associated with each combination. The required frequency is
determined by the processors, chipset, and clock synthesizer. All FSB agents must
operate at the same frequency. The Dual-Core Intel Xeon Processor 5000 series
currently operate at either 667 or 1066 MHz FSB frequency. For more information
about these signals, including termination recommendations, refer to the appropriate
platform design guideline.
COMP[3:0]
COMP[7:4]
I
I
COMP[3:0] must be terminated to V on the baseboard using precision resistors.
SS
These inputs configure the AGTL+ drivers of the processor. Refer to the appropriate
platform design guidelines for implementation details.
COMP[7:4] must be terminated to V on the baseboard using precision resistors.
TT
These inputs configure the AGTL+ drivers of the processor. Refer to the appropriate
platform design guidelines for implementation details.
62
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Signal Definitions
Table 5-1.
Signal Definitions (Sheet 3 of 8)
Name
Type
Description
Notes
D[63:0]#
I/O
D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path
between the processor FSB agents, and must connect the appropriate pins on all
such agents. The data driver asserts DRDY# to indicate a valid data transfer.
3
D[63:0]# are quad-pumped signals, and will thus be driven four times in a
common clock period. D[63:0]# are latched off the falling edge of both
DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals
correspond to a pair of one DSTBP# and one DSTBN#. The following table
shows the grouping of data signals to strobes and DBI#.
DSTBN#/
DSTBP#
Data Group
DBI#
D[15:0]#
D[31:16]#
D[47:32]#
D[63:48]#
0
1
2
3
0
1
2
3
Furthermore, the DBI# signals determine the polarity of the data signals.
Each group of 16 data signals corresponds to one DBI# signal. When the
DBI# signal is active, the corresponding data group is inverted and
therefore sampled active high.
DBI[3:0]#
I/O
DBI[3:0]# (Data Bus Inversion) are source synchronous and indicate the polarity of
the D[63:0]# signals. The DBI[3:0]# signals are activated when the data on the data
bus is inverted. If more than half the data bits, within, within a 16-bit group, would
have been asserted electronically low, the bus agent may invert the data bus signals
for that particular sub-phase for that 16-bit group.
3
DBI[3:0]# Assignment to Data Bus
Bus Signal
Data Bus Signals
DBI0#
DBI1#
DBI2#
DBI3#
D[15:0]#
D[31:16]#
D[47:32]#
D[63:48]#
DBR#
O
DBR# is used only in systems where no debug port connector is implemented on the
system board. DBR# is used by a debug port interposer so that an in-target probe
can drive system reset. If a debug port connector is implemented in the system,
DBR# is treated as a no connect for the processor socket. DBR# is not a processor
signal.
DBSY#
I/O
I
DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the
processor FSB to indicate that the data bus is in use. The data bus is released after
DBSY# is deasserted. This signal must connect the appropriate pins on all processor
FSB agents.
3
3
DEFER#
DEFER# is asserted by an agent to indicate that a transaction cannot be guaranteed
in-order completion. Assertion of DEFER# is normally the responsibility of the
addressed memory or I/O agent. This signal must connect the appropriate pins of all
processor FSB agents.
DP[3:0]#
DRDY#
I/O
I/O
DP[3:0]# (Data Parity) provide parity protection for the D[63:0]# signals. They are
driven by the agent responsible for driving D[63:0]#, and must connect the
appropriate pins of all processor FSB agents.
3
3
DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating
valid data on the data bus. In a multi-common clock data transfer, DRDY# may be
deasserted to insert idle clocks. This signal must connect the appropriate pins of all
processor FSB agents.
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
63
Signal Definitions
Table 5-1.
Signal Definitions (Sheet 4 of 8)
Name
Type
Description
Data strobe used to latch in D[63:0]#.
Notes
DSTBN[3:0]#
I/O
3
Signals
Associated Strobes
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP[3:0]#
I/O
Data strobe used to latch in D[63:0]#.
3
Signals
Associated Strobes
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
FERR#/PBE#
O
FERR#/PBE# (floating-point error/pending break event) is a multiplexed signal and
its meaning is qualified by STPCLK#. When STPCLK# is not asserted, FERR#/PBE#
indicates a floating-point error and will be asserted when the processor detects an
unmasked floating-point error. When STPCLK# is not asserted, FERR#/PBE# is
similar to the ERROR# signal on the Intel 387 coprocessor, and is included for
compatibility with systems using MS-DOS*-type floating-point error reporting. When
STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the processor has a
pending break event waiting for service. The assertion of FERR#/PBE# indicates that
the processor should be returned to the Normal state. For additional information on
the pending break event functionality, including the identification of support of the
feature and enable/disable information, refer to Vol. 3 of the Intel Architecture
Software Developer’s Manual and the Intel Processor Identification and the CPUID
Instruction application note.
2
FORCEPR#
I
I
The FORCEPR# (force power reduction) input can be used by the platform to cause
the Dual-Core Intel Xeon Processor 5000 series to activate the Thermal Control
Circuit (TCC).
GTLREF_ADD_C0
GTLREF_ADD_C1
GTLREF_ADD_C0 and GTLREF_ADD_C1 determine the signal reference level for
AGTL+ address and common clock input lands on processor core 0 and processor
core 1 respectively. GTLREF_ADD is used by the AGTL+ receivers to determine if a
signal is a logical 0 or a logical 1. Please refer to the appropriate platform design
guidelines for additional details.
GTLREF_DATA_C0
GTLREF_DATA_C1
I
GTLREF_DATA_C0 AND GTLREF_DATA_C1 determine the signal reference level for
AGTL+ data input lands on processor core 0 and processor core 1 respectively.
GTLREF_DATA is used by the AGTL+ receivers to determine if a signal is a logical 0 or
a logical 1. Please refer to the appropriate platform design guidelines for additional
details.
HIT#
HITM#
I/O
I/O
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation
results. Any FSB agent may assert both HIT# and HITM# together to indicate that it
requires a snoop stall, which can be continued by reasserting HIT# and HITM#
together.
3
2
IERR#
O
IERR# (Internal Error) is asserted by a processor as the result of an internal error.
Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the
processor FSB. This transaction may optionally be converted to an external error
signal (for example, NMI) by system core logic. The processor will keep IERR#
asserted until the assertion of RESET#.
This signal does not have on-die termination.
64
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Signal Definitions
Table 5-1.
Signal Definitions (Sheet 5 of 8)
Name
Type
Description
Notes
IGNNE#
I
IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a
numeric error and continue to execute noncontrol floating-point instructions. If
IGNNE# is deasserted, the processor generates an exception on a noncontrol
floating-point instruction if a previous floating-point instruction caused an error.
IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.
2
IGNNE# is an asynchronous signal. However, to ensure recognition of this signal
following an I/O write instruction, it must be valid along with the TRDY# assertion of
the corresponding I/O write bus transaction.
INIT#
I
I
INIT# (Initialization), when asserted, resets integer registers inside all processors
without affecting their internal caches or floating-point registers. Each processor then
begins execution at the power-on Reset vector configured during power-on
configuration. The processor continues to handle snoop requests during INIT#
assertion. INIT# is an asynchronous signal and must connect the appropriate pins of
all processor FSB agents.
2
2
LINT[1:0]
LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all FSB
agents. When the APIC functionality is disabled, the LINT0/INTR signal becomes
INTR, a maskable interrupt request signal, and LINT1/NMI becomes NMI, a
nonmaskable interrupt. INTR and NMI are backward compatible with the signals of
®
those names on the Pentium processor. Both signals are asynchronous.
These signals must be software configured via BIOS programming of the APIC
register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC is
enabled by default after Reset, operation of these pins as LINT[1:0] is the default
configuration.
LL_ID[1:0]
LOCK#
O
The LL_ID[1:0] signals are used to select the correct loadline slope for the processor.
The Dual-Core Intel Xeon Processor 5000 series pull these signals to ground on the
package for a logic 0 as these signals are not connected to the processor die. A logic
1 is a no-connect on the Dual-Core Intel Xeon Processor 5000 series package.
I/O
LOCK# indicates to the system that a transaction must occur atomically. This signal
must connect the appropriate pins of all processor FSB agents. For a locked series of
transactions, LOCK# is asserted from the beginning of the first transaction to the end
of the last transaction.
3
When the priority agent asserts BPRI# to arbitrate for ownership of the processor
FSB, it will wait until it observes LOCK# deasserted. This enables symmetric agents
to retain ownership of the processor FSB throughout the bus locked operation and
ensure the atomicity of lock.
MCERR#
I/O
MCERR# (Machine Check Error) is asserted to indicate an unrecoverable
error without a bus protocol violation. It may be driven by all processor
FSB agents.
MCERR# assertion conditions are configurable at a system level. Assertion
options are defined by the following options:
• Enabled or disabled.
• Asserted, if configured, for internal errors along with IERR#.
• Asserted, if configured, by the request initiator of a bus transaction
after it observes an error.
• Asserted by any bus agent when it observes an error in a bus
transaction.
For more details regarding machine check architecture, refer to the IA-32 Software
Developer’s Manual, Volume 3: System Programming Guide.
MS_ID[1:0]
PROCHOT#
O
O
These signals are provided to indicate the Market Segment for the processor and
may be used for future processor compatibility or for keying. The Dual-Core Intel
Xeon Processor 5000 series pull these signals to ground on the package for a logic 0
as these signals are not connected to the processor die. A logic 1 is a no-connect on
the Dual-Core Intel Xeon Processor 5000 series package.
PROCHOT# (Processor Hot) will go active when the processor’s temperature
monitoring sensor detects that the processor has reached its maximum safe
operating temperature. This indicates that the Thermal Control Circuit (TCC) has
been activated, if enabled. The TCC will remain active until shortly after the
processor deasserts PROCHOT#. See Section 6.2.3 for more details. PROCHOT#
from each processor socket should be kept separated and not tied together on
platform designs.
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
65
Signal Definitions
Table 5-1.
Signal Definitions (Sheet 6 of 8)
Name
Type
Description
Notes
PWRGOOD
I
PWRGOOD (Power Good) is an input. The processor requires this signal to be a clean
indication that all processor clocks and power supplies are stable and within their
specifications. “Clean” implies that the signal will remain low (capable of sinking
leakage current), without glitches, from the time that the power supplies are turned
on until they come within specification. The signal must then transition monotonically
to a high state.PWRGOOD can be driven inactive at any time, but clocks and power
must again be stable before a subsequent rising edge of PWRGOOD. It must also
meet the minimum pulse width specification in Table 2-15, and be followed by a
1-10 ms RESET# pulse.
2
The PWRGOOD signal must be supplied to the processor; it is used to protect internal
circuits against voltage sequencing issues. It should be driven high throughout
boundary scan operation.
REQ[4:0]#
RESET#
I/O
REQ[4:0]# (Request Command) must connect the appropriate pins of all processor
FSB agents. They are asserted by the current bus owner to define the currently
active transaction type. These signals are source synchronous to ADSTB[1:0]#.
Refer to the AP[1:0]# signal description for details on parity checking of these
signals.
3
3
I
Asserting the RESET# signal resets all processors to known states and invalidates
their internal caches without writing back any of their contents. For a power-on
Reset, RESET# must stay active for at least 1 ms after VCC and BCLK have reached
their proper specifications. On observing active RESET#, all FSB agents will deassert
their outputs within two clocks. RESET# must not be kept asserted for more than 10
ms while PWRGOOD is asserted.
A number of bus signals are sampled at the active-to-inactive transition of RESET#
for power-on configuration. These configuration options are described in the
Section 7.1.
This signal does not have on-die termination and must be terminated on the
system board.
RS[2:0]#
RSP#
I
I
RS[2:0]# (Response Status) are driven by the response agent (the agent responsible
for completion of the current transaction), and must connect the appropriate pins of
all processor FSB agents.
3
3
RSP# (Response Parity) is driven by the response agent (the agent responsible for
completion of the current transaction) during assertion of RS[2:0]#, the signals for
which RSP# provides parity protection. It must connect to the appropriate pins of all
processor FSB agents.
A correct parity signal is high if an even number of covered signals are low and low if
an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is also high,
since this indicates it is not being driven by any agent guaranteeing correct parity.
SKTOCC#
SMI#
O
I
SKTOCC# (Socket occupied) will be pulled to ground by the processor to indicate that
the processor is present. There is no connection to the processor silicon for this
signal.
SMI# (System Management Interrupt) is asserted asynchronously by system logic.
On accepting a System Management Interrupt, processors save the current state and
enter System Management Mode (SMM). An SMI Acknowledge transaction is issued,
and the processor begins program execution from the SMM handler.
If SMI# is asserted during the deassertion of RESET# the processor will tri-state its
outputs.
2
2
STPCLK#
I
STPCLK# (Stop Clock), when asserted, causes processors to enter a low power Stop-
Grant state. The processor issues a Stop-Grant Acknowledge transaction, and stops
providing internal clock signals to all processor core units except the FSB and APIC
units. The processor continues to snoop bus transactions and service interrupts while
in Stop-Grant state. When STPCLK# is deasserted, the processor restarts its internal
clock to all units and resumes execution. The assertion of STPCLK# has no effect on
the bus clock; STPCLK# is an asynchronous input.
TCK
I
TCK (Test Clock) provides the clock input for the processor Test Bus (also known as
the Test Access Port).
TDI
I
O
TDI (Test Data In) transfers serial test data into the processor. TDI provides the
serial input needed for JTAG specification support.
TDO
TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the
serial output needed for JTAG specification support.
TEST_BUS
Other
Must be connected to all other processor TEST_BUS signals in the system. See the
appropriate platform design guideline for termination details.
66
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Signal Definitions
Table 5-1.
Signal Definitions (Sheet 7 of 8)
Name
Type
Description
Notes
TESTHI[11:0]
I
TESTHI[11:0] must be connected to a VTT power source through a resistor for proper
processor operation. Refer to Section 2.6 for TESTHI grouping restrictions.
THERMDA
THERMDA2
Other
Other
O
Thermal Diode Anode. THERMDA connects to processor core 0, THERMDA2 connects
to processor core 1. Refer to the appropriate platform design guidelines for
implementation details.
THERMDC
THERMDC2
Thermal Diode Cathode. THERMDC connects to processor core 0. THERMDC2
connects to processor core 1. Refer to the appropriate platform design guidelines for
implementation details.
THERMTRIP#
Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction
temperature has reached a temperature beyond which permanent silicon damage
may occur. Measurement of the temperature is accomplished through an internal
thermal sensor. Upon assertion of THERMTRIP#, the processor will shut off its
internal clocks (thus halting program execution) in an attempt to reduce the
1
processor junction temperature. To protect the processor its core voltage (V ) must
CC
be removed following the assertion of THERMTRIP#. Intel is currently evaluating
whether V must also be removed.
TT
Driving of the THERMTRIP# signals is enabled within 10 ms of the assertion of
PWRGOOD and is disabled on de-assertion of PWRGOOD. Once activated,
THERMTRIP# remains latched until PWRGOOD is de-asserted. While the de-assertion
of the PWRGOOD signal will de-assert THERMTRIP#, if the processor’s junction
temperature remains at or above the trip level, THERMTRIP# will again be asserted
within 10 ms of the assertion of PWRGOOD.
TMS
I
I
TMS (Test Mode Select) is a JTAG specification support signal used by debug tools.
See the eXtended Debug Port: Debug Port Design Guide for UP and DP Platforms for
further information.
TRDY#
TRST#
TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive
a write or implicit writeback data transfer. TRDY# must connect the appropriate pins
of all FSB agents.
I
I
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven
low during power on Reset.
V
V
V
provides isolated power for the analog portion of the internal processor core
CCA
CCA
PLL’s. Refer to the appropriate platform design guidelines for complete
implementation details.
I
V
provides isolated power for digital portion of the internal processor core
CCIOPLL
CCIOPLL
PLL’s. Follow the guidelines for V
, and refer to the appropriate platform design
CCA
guidelines for complete implementation details.
VCC_DIE_SENSE
VCC_DIE_SENSE2
O
VCC_DIE_SENSE and VCC_DIE_SENSE2 provide an isolated, low impedance
connection to each processor core power and ground. These signals should be
connected to the voltage regulator feedback signal, which insures the output voltage
(that is, processor voltage) remains within specification. Please see the applicable
platform design guide for implementation details.
VID[5:0]
O
VID[5:0] (Voltage ID) pins are used to support automatic selection of power supply
voltages (V ). These are CMOS signals that are driven by the processor and must be
CC
pulled up through a resistor. Conversely, the voltage regulator output must be
disabled prior to the voltage supply for these pins becomes invalid. The VID pins are
needed to support processor voltage specification variations. See Table 2-3 for
definitions of these pins. The VR must supply the voltage that is requested by these
pins, or disable itself.
VID_SELECT
O
O
VID_SELECT is an output from the processor which selects the appropriate VID table
for the Voltage Regulator. Dual-Core Intel Xeon Processor 5000 series pull this signal
to ground on the package as this signal is not connected to the processor die.
VSS_DIE_SENSE
VSS_DIE_SENSE2
VSS_DIE_SENSE and VSS_DIE_SENSE2 provide an isolated, low impedance
connection to each processor core power and ground. These signals should be
connected to the voltage regulator feedback signal, which insures the output voltage
(that is, processor voltage) remains within specification. Please see the applicable
platform design guide for implementation details.
V
I
V
provides an isolated, internal ground for internal PLL’s. Do not connect directly
SSA
SSA
to ground. This pin is to be connected to V
circuit.
and V
through a discrete filter
CCA
CCIOPLL
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
67
Signal Definitions
Table 5-1.
Signal Definitions (Sheet 8 of 8)
Name
Type
Description
Notes
V
P
The FSB termination voltage input pins. Refer to Table 2-10 for further details.
TT
VTT_OUT
O
The VTT_OUT signals are included in order to provide a local VTT for some signals that
require termination to VTT on the motherboard.
VTTPWRGD
I
The processor requires this input to determine that the supply voltage for BSEL[2:0]
and VID[5:0] is stable and within specification.
Notes:
1.
2.
3.
For this pin on Dual-Core Intel Xeon Processor 5000 series, the maximum number of symmetric agents is one. Maximum
number of priority agents is zero.
For this pin on Dual-Core Intel Xeon Processor 5000 series, the maximum number of symmetric agents is two. Maximum
number of priority agents is zero.
For this pin on Dual-Core Intel Xeon Processor 5000 series, the maximum number of symmetric agents is two. Maximum
number of priority agents is one.
§
68
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Thermal Specifications
6 Thermal Specifications
6.1
Package Thermal Specifications
The Dual-Core Intel Xeon Processor 5000 series require a thermal solution to maintain
temperatures within its operating limits. Any attempt to operate the processor outside
these operating limits may result in permanent damage to the processor and
potentially other components within the system. As processor technology changes,
thermal management becomes increasingly crucial when building computer systems.
Maintaining the proper thermal environment is key to reliable, long-term system
operation.
A complete solution includes both component and system level thermal management
features. Component level thermal solutions can include active or passive heatsinks
attached to the processor integrated heat spreader (IHS). Typical system level thermal
solutions may consist of system fans combined with ducting and venting.
This section provides data necessary for developing a complete thermal solution. For
more information on designing a component level thermal solution, refer to the Dual-
Core Intel® Xeon® Processor 5000 Series Thermal/Mechanical Design Guidelines.
Note:
The boxed processor will ship with a component thermal solution. Refer to Chapter 8,
“Boxed Processor Specifications”for details on the boxed processor.
6.1.1
Thermal Specifications
To allow the optimal operation and long-term reliability of Intel processor-based
systems, the processor must remain within the minimum and maximum case
temperature (TCASE) specifications as defined by the applicable thermal profile (refer to
Table 6-1, Table 6-4 and Table 6-7; Figure 6-1, Figure 6-2 and Figure 6-3). Thermal
solutions not designed to provide this level of thermal capability may affect the long-
term reliability of the processor and system. For more details on thermal solution
design, please refer to the processor thermal/mechanical design guidelines.
The Dual-Core Intel Xeon Processor 5000 series implement a methodology for
managing processor temperatures, which is intended to support acoustic noise
reduction through fan speed control and to ensure processor reliability. Selection of the
appropriate fan speed is based on the temperature reported by the processor’s Thermal
Diode. If the diode temperature is greater than or equal to Tcontrol (refer to
Section 6.2.6), then the processor case temperature must remain at or below the
temperature specified by the thermal profile (refer to Figure 6-1, Figure 6-2 and
Figure 6-3). If the diode temperature is less than Tcontrol, then the case temperature
is permitted to exceed the thermal profile, but the diode temperature must remain at
or below Tcontrol. Systems that implement fan speed control must be designed to take
these conditions into account. Systems that do not alter the fan speed only need to
guarantee the case temperature meets the thermal profile specifications.
Intel has developed two thermal profiles, either of which can be implemented with the
Dual-Core Intel Xeon Processor 5000 series. Both ensure adherence to Intel reliability
requirements. Thermal Profile A (refer to Figure 6-1, Figure 6-2; Table 6-2 and
Table 6-5) is representative of a volumetrically unconstrained thermal solution (that is,
industry enabled 2U heatsink). In this scenario, it is expected that the Thermal Control
Circuit (TCC) would only be activated for very brief periods of time when running the
most power intensive applications. Thermal Profile B (refer to Figure 6-1 and
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
69
Thermal Specifications
Figure 6-2; Table 6-3 and Table 6-6) is indicative of a constrained thermal environment
(that is, 1U form factor). Because of the reduced cooling capability represented by this
thermal solution, the probability of TCC activation and performance loss is increased.
Additionally, utilization of a thermal solution that does not meet Thermal Profile B will
violate the thermal specifications and may result in permanent damage to the
processor. Intel has developed these thermal profiles to allow OEMs to choose the
thermal solution and environmental parameters that best suit their platform
implementation. Refer to the Dual-Core Intel® Xeon® Processor 5000 Series Thermal/
Mechanical Design Guidelines for details on system thermal solution design, thermal
profiles and environmental considerations.
The Dual-Core Intel Xeon Processor 5063 (MV) supports a single Thermal Profile
targeted at volumetrically constrained thermal environments (for example, blades, 1U
form factors.) With this Thermal Profile, it’s expected that the Thermal Control Circuit
(TCC) would only be activated for very brief periods of time when running the most
power-intensive applications. Refer to the Dual-Core Intel® Xeon® Processor 5000
Series Thermal/Mechanical Design Guidelines for further details.
The upper point of the thermal profile consists of the Thermal Design Power (TDP)
defined in Table 6-1, Table 6-4, Table 6-7 and the associated TCASE value. It should be
noted that the upper point associated with Thermal Profile B (x = TDP and y =
TCASE_MAX_B @ TDP) represents a thermal solution design point. In actuality the
processor case temperature will not reach this value due to TCC activation (refer to
Figure 6-1 and Figure 6-2). The lower point of the thermal profile consists of x =
P_profile_min and y = TCASE_MAX @ P_profile_min. P_profile_min is defined as the
processor power at which TCASE , calculated from the thermal profile, is equal to 50 °C.
The case temperature is defined at the geometric top center of the processor IHS.
Analysis indicates that real applications are unlikely to cause the processor to consume
maximum power dissipation for sustained time periods. Intel recommends that
complete thermal solution designs target the Thermal Design Power (TDP) indicated in
Table 6-1, Table 6-4 and Table 6-7, instead of the maximum processor power
consumption. The Thermal Monitor feature is intended to help protect the processor in
the event that an application exceeds the TDP recommendation for a sustained time
period. For more details on this feature, refer to Section 6.2. To ensure maximum
flexibility for future requirements, systems should be designed to the Flexible
Motherboard (FMB) guidelines, even if a processor with lower power dissipation is
currently planned. The Thermal Monitor feature must be enabled for the
processor to remain within its specifications.
Table 6-1.
Dual-Core Intel Xeon Processor 5000 Series (1066 MHz) Thermal
Specifications
Thermal
Design Power
(W)
Minimum
TCASE
(°C)
Maximum TCASE
(°C)
Core Frequency
Notes
Launch to FMB
130
5
Refer to Figure 6-1; Table 6-2; Table 6-3 1, 2, 3, 4, 5
Notes:
1.
These values are specified at V
for all processor frequencies. Systems must be designed to ensure
CC_MAX
the processor is not to be subjected to any static V and I combination wherein V exceeds V at
CC
CC
CC
CC_MAX
specified I . Please refer to the loadline specifications in Chapter 2, “Electrical Specifications”.
CC
2.
Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the
maximum power that the processor can dissipate. TDP is measured at maximum T
These specifications are based on final silicon validation/characterization.
Power specifications are defined at all VIDs found in Table 2-10. The Dual-Core Intel Xeon Processor 5000
series may be shipped under multiple VIDs for each frequency.
FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor
frequency requirements.
.
CASE
3.
4.
5.
70
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Thermal Specifications
Figure 6-1. Dual-Core Intel Xeon Processor 5000 Series (1066 MHz) Thermal Profiles A
and B
TCASE_MAX is a thermal solution design point. In actuality, units will not significantly
exceed TCASE_MAX_A due to TCC activation.
85
TCASE_MAX_B@TDP
TCASE_MAX_A@TDP
80
75
70
65
60
55
50
45
40
Thermal Profile B
Y = 0.260*x + 44.2
Thermal Profile A
Y = 0.203*x + 42.6
0
10
20
30
40
50
60
70
80
90
100
110
120
130
Pow er [W]
Notes:
1.
Thermal Profile A is representative of a volumetrically unconstrained platform. Please refer to Table 6-2 for
discrete points that constitute the thermal profile.
Implementation of Thermal Profile A should result in virtually no TCC activation. Furthermore, utilization of
thermal solutions that do not meet processor Thermal Profile A will result in increased probability of TCC
activation and may incur measurable performance loss. (Refer to Section 6.2 for details on TCC activation.)
Thermal Profile B is representative of a volumetrically constrained platform. Please refer to Table 6-3 for
discrete points that constitute the thermal profile.
Implementation of Thermal Profile B will result in increased probability of TCC activation and measurable
performance loss. Furthermore, utilization of thermal solutions that do not meet Thermal Profile B do not
meet the processor’s thermal specifications and may result in permanent damage to the processor.
2.
3.
4.
®
®
5.
Refer to the Dual-Core Intel Xeon processor 5000 Series Thermal/Mechanical Design Guidelines for
system and environmental implementation details.
Table 6-2.
Dual-Core Intel Xeon Processor 5000 Series (1066 MHz) Thermal Profile A
Table
Power (W)
T
(° C)
Power (W)
T
(° C)
CASE_MAX
50.0
CASE_MAX
59.9
P_profile_min =36.5
_A
85
90
40
45
50
55
60
65
70
75
80
50.7
60.9
51.7
95
61.9
52.8
100
105
110
115
120
125
130
62.9
53.8
63.9
54.8
64.9
55.8
65.9
56.8
67.0
57.8
68.0
58.8
69.0
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
71
Thermal Specifications
Table 6-3.
Dual-Core Intel Xeon Processor 5000 Series (1066 MHz) Thermal Profile B
Table
Power (W)
T
(° C)
Power (W)
T
(° C)
CASE_MAX
50.0
52.0
53.3
54.6
55.9
57.2
58.5
59.8
61.1
62.4
63.7
CASE_MAX
65.0
66.3
67.6
68.9
70.2
71.5
72.8
74.1
75.4
76.7
78.0
P_profile_min =22.3
_B
80
85
30
35
40
45
50
55
60
65
70
75
90
95
100
105
110
115
120
125
130
Table 6-4.
Dual-Core Intel Xeon Processor 5000 Series (667 MHz) Thermal Specifications
Thermal
Core Frequency Design Power
(W)
Minimum
TCASE
(°C)
Maximum TCASE
(°C)
Notes
Launch to FMB
95
5
Refer to Figure 6-2;
Table 6-5; Table 6-6
1, 2, 3, 4,
5
Notes:
1.
These values are specified at V
for all processor frequencies. Systems must be designed to ensure
CC_MAX
the processor is not to be subjected to any static V and I combination wherein V exceeds V at
CC
CC
CC
CC_MAX
specified I . Please refer to the loadline specifications in Chapter 2, “Electrical Specifications.”
Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the
CC
2.
maximum power that the processor can dissipate. TDP is measured at maximum T
These specifications are based on final silicon validation/characterization.
Power specifications are defined at all VIDs found in Table 2-10. The Dual-Core Intel Xeon Processor 5000
series may be shipped under multiple VIDs for each frequency.
FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor
frequency requirements.
.
CASE
3.
4.
5.
72
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Thermal Specifications
Figure 6-2. Dual-Core Intel Xeon Processor 5000 Series (667 MHz) Thermal Profiles
TCASE_MAX is a thermal solution design point. In actuality, units will not significantly exceed
TCASE_MAX_A due to TCC activation.
70
TCASE_MAX_B@TDP
65
TCASE_MAX_A@TDP
60
Thermal Profile B
Y = 0.260*x + 42.3
55
Thermal Profile A
Y = 0.203*x + 41.7
50
45
40
0
10
20
30
40
50
60
70
80
90
100
Pow er [W]
Notes:
1.
Thermal Profile A is representative of a volumetrically unconstrained platform. Please refer to Table 6-5 for
discrete points that constitute the thermal profile.
Implementation of Thermal Profile A should result in virtually no TCC activation. Furthermore, utilization of
thermal solutions that do not meet processor Thermal Profile A will result in increased probability of TCC
activation and may incur measurable performance loss. (Refer to Section 6.2 for details on TCC activation).
Thermal Profile B is representative of a volumetrically constrained platform. Please refer to Table 6-6 for
discrete points that constitute the thermal profile.
Implementation of Thermal Profile B will result in increased probability of TCC activation and measurable
performance loss. Furthermore, utilization of thermal solutions that do not meet Thermal Profile B do not
meet the processor’s thermal specifications and may result in permanent damage to the processor.
2.
3.
4.
®
®
5.
Refer to the Dual-Core Intel Xeon Processor 5000 Series Thermal/Mechanical Design Guidelines for
system and environmental implementation details.
Table 6-5.
Dual-Core Intel Xeon Processor 5000 Series (667 MHz) Thermal Profile A
Table
Power (W)
T
(° C)
Power (W)
T
(° C)
CASE_MAX
50.0
CASE_MAX
57.9
P_profile_min =40.9
_A
80
85
90
95
45
50
55
60
65
70
75
50.8
59.0
51.9
60.0
52.9
61.0
53.9
54.9
55.9
56.9
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
73
Thermal Specifications
Table 6-6.
Dual-Core Intel Xeon 5000 Series (667 MHz) Thermal Profile B Table
Power (W)
T
(° C)
Power (W)
T
(° C)
CASE_MAX
50.0
CASE_MAX
61.8
P_profile_min =29.6
_B
75
80
85
90
95
35
40
45
50
55
60
65
70
51.4
63.1
52.7
64.4
54.0
65.7
55.3
67.0
56.6
57.9
59.2
60.5
Table 6-7.
Dual-Core Intel Xeon Processor 5063 (MV) Thermal Specifications
Thermal
Core Frequency Design Power
(W)
Minimum
TCASE
(°C)
Maximum TCASE
(°C)
Notes
Launch to FMB
95
5
Refer to Figure 6-3;
Table 6-8
1, 2, 3, 4,
5
Notes:
1.
These values are specified at V
for all processor frequencies. Systems must be designed to ensure
CC_MAX
the processor is not to be subjected to any static V and I combination wherein V exceeds V at
CC
CC
CC
CC_MAX
specified I . Please refer to the loadline specifications in Chapter 2, “Electrical Specifications.”
CC
2.
Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the
maximum power that the processor can dissipate. TDP is measured at maximum T
These specifications are based on final silicon validation/characterization.
Power specifications are defined at all VIDs found in Table 2-10. The Dual-Core Intel Xeon Processor 5000
series may be shipped under multiple VIDs for each frequency.
FMB, or Flexible Motherboard, guideline provide a design target for meeting all planned processor
frequency requirements.
.
CASE
3.
4.
5.
74
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Thermal Specifications
Figure 6-3. Dual-Core Intel Xeon Processor 5063 (MV) Thermal Profile
Thermal Profile
70
TCASE_MAX@TDP
65
Thermal Profile
Y = 0.260*x + 42.3
60
55
50
45
40
0
10
20
30
40
50
60
70
80
90
100
Power [W]
Notes:
1.
Thermal Profile is representative of a volumetrically constrained platform. Please refer to Table 6-8 for
discrete points that constitute the thermal profile.
2.
Implementation of Thermal Profile should result in virtually no TCC activation. Furthermore, utilization of
thermal solutions that do not meet Thermal Profile will not meet the processor’s thermal specifications and
may result in permanent damage to the processor.
®
®
3.
Refer to the Dual-Core Intel Xeon Processor 5000 Series Thermal/Mechanical Design Guidelines for
system and environment implementation details.
Table 6-8.
Dual-Core Intel Xeon Processor 5063 (MV) Thermal Profile Table
Power (W)
T
(° C)
Power (W)
T
(° C)
CASE_MAX
50.0
CASE_MAX
61.8
P_profile_min =29.6
_B
75
80
85
90
95
35
40
45
50
55
60
65
70
51.4
63.1
52.7
64.4
54.0
65.7
55.3
67.0
56.6
57.9
59.2
60.5
6.1.2
Thermal Metrology
The minimum and maximum case temperatures (TCASE) specified in Table 6-2,
Table 6-3, Table 6-5, and Table 6-6 are measured at the geometric top center of the
processor integrated heat spreader (IHS). Figure 6-4 illustrates the location where
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
75
Thermal Specifications
TCASE temperature measurements should be made. For detailed guidelines on
temperature measurement methodology, refer to the Dual-Core Intel® Xeon®
Processor 5000 Series Thermal/Mechanical Design Guidelines.
Figure 6-4. Case Temperature (TCASE) Measurement Location
Note: Figure is not to scale and is for reference only.
76
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Thermal Specifications
6.2
Processor Thermal Features
6.2.1
Thermal Monitor
The Thermal Monitor (TM1) feature helps control the processor temperature by
activating the Thermal Control Circuit (TCC) when the processor silicon reaches its
maximum operating temperature. The TCC reduces processor power consumption as
needed by modulating (starting and stopping) the internal processor core clocks. The
Thermal Monitor (TM1) must be enabled for the processor to be operating within
specifications. The temperature at which Thermal Monitor activates the thermal control
circuit is not user configurable and is not software visible. Bus traffic is snooped in the
normal manner, and interrupt requests are latched (and serviced during the time that
the clocks are on) while the TCC is active.
When the Thermal Monitor is enabled and a high temperature situation exists (that is,
TCC is active), the clocks will be modulated by alternately turning the clocks off and on
at a duty cycle specific to the processor (typically 30 -50%). Cycle times are processor
speed dependent and will decrease as processor core frequencies increase. A small
amount of hysteresis has been included to prevent rapid active/inactive transitions of
the TCC when the processor temperature is near its maximum operating temperature.
Once the temperature has dropped below the maximum operating temperature, and
the hysteresis timer has expired, the TCC goes inactive and clock modulation ceases.
With a thermal solution designed to meet Thermal Profile A, it is anticipated that the
TCC would only be activated for very short periods of time when running the most
power intensive applications. The processor performance impact due to these brief
periods of TCC activation is expected to be so minor that it would be immeasurable. A
thermal solution that is designed to Thermal Profile B may cause a noticeable
performance loss due to increased TCC activation. Thermal Solutions that exceed
Thermal Profile B will exceed the maximum temperature specification and affect the
long-term reliability of the processor. In addition, a thermal solution that is significantly
under designed may not be capable of cooling the processor even when the TCC is
active continuously. Refer to the Dual-Core Intel® Xeon® Processor 5000 Series
Thermal/Mechanical Design Guidelines for information on designing a thermal solution.
The duty cycle for the TCC, when activated by the TM1, is factory configured and
cannot be modified. The TM1 does not require any additional hardware, software
drivers, or interrupt handling routines.
6.2.2
On-Demand Mode
The processor provides an auxiliary mechanism that allows system software to force
the processor to reduce its power consumption. This mechanism is referred to as “On-
Demand” mode and is distinct from the Thermal Monitor feature. On-Demand mode is
intended as a means to reduce system level power consumption. Systems utilizing the
Dual-Core Intel Xeon Processor 5000 series must not rely on software usage of this
mechanism to limit the processor temperature. If bit 4 of the
IA32_CLOCK_MODULATION MSR is set to a ‘1’, the processor will immediately reduce
its power consumption via modulation (starting and stopping) of the internal core clock,
independent of the processor temperature. When using On-Demand mode, the duty
cycle of the clock modulation is programmable via bits 3:1 of the same
IA32_CLOCK_MODULATION MSR. In On-Demand mode, the duty cycle can be
programmed from 12.5% on/ 87.5% off to 87.5% on/12.5% off in 12.5% increments.
On-Demand mode may be used in conjunction with the Thermal Monitor; however, if
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
77
Thermal Specifications
the system tries to enable On-Demand mode at the same time the TCC is engaged, the
factory configured duty cycle of the TCC will override the duty cycle selected by the On-
Demand mode.
6.2.3
PROCHOT# Signal
An external signal, PROCHOT# (processor hot) is asserted when the processor die
temperature has reached its factory configured trip point. If Thermal Monitor is enabled
(note that Thermal Monitor must be enabled for the processor to be operating within
specification), the TCC will be active when PROCHOT# is asserted. The processor can
be configured to generate an interrupt upon the assertion or de-assertion of
PROCHOT#. Refer to the Intel Architecture Software Developer’s Manual for specific
register and programming details.
PROCHOT# is designed to assert at or a few degrees higher than maximum TCASE (as
specified by Thermal Profile A) when dissipating TDP power and cannot be interpreted
as an indication of processor case temperature. This temperature delta accounts for
processor package, lifetime and manufacturing variations and attempts to ensure the
Thermal Control Circuit is not activated below maximum TCASE when dissipating TDP
power. There is no defined or fixed correlation between the PROCHOT# trip
temperature, the case temperature or the thermal diode temperature. Thermal
solutions must be designed to the processor specifications and cannot be adjusted
based on experimental measurements of TCASE, PROCHOT#, or Tdiode on random
processor samples.
6.2.4
FORCEPR# Signal
The FORCEPR# (force power reduction) input can be used by the platform to cause the
Dual-Core Intel Xeon Processor 5000 series to activate the TCC. If the Thermal Monitor
is enabled, the TCC will be activated upon the assertion of the FORCEPR# signal.
Assertion of the FORCEPR# signal will activate TCC for both processor cores. The TCC
will remain active until the system deasserts FORCEPR#. FORCEPR# is an
asynchronous input. FORCEPR# can be used to thermally protect other system
components. To use the VR as an example, when FORCEPR# is asserted, the TCC
circuit in the processor will activate, reducing the current consumption of the processor
and the corresponding temperature of the VR.
It should be noted that assertion of FORCEPR# does not automatically assert
PROCHOT#. As mentioned previously, the PROCHOT# signal is asserted when a high
temperature situation is detected. A minimum pulse width of 500 µs is recommended
when FORCEPR# is asserted by the system. Sustained activation of the FORCEPR#
signal may cause noticeable platform performance degradation. Refer to the
appropriate platform design guidelines for details on implementing the FORCEPR#
signal feature.
6.2.5
THERMTRIP# Signal
Regardless of whether or not Thermal Monitor is enabled, in the event of a catastrophic
cooling failure, the processor will automatically shut down when the silicon has reached
an elevated temperature (refer to the THERMTRIP# definition in Table 5-1). At this
point, the FSB signal THERMTRIP# will go active and stay active as described in
Table 5-1. THERMTRIP# activation is independent of processor activity and does not
generate any bus cycles. Intel also recommends the removal of VTT.
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Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Thermal Specifications
6.2.6
Tcontrol and Fan Speed Reduction
Tcontrol is a temperature specification based on a temperature reading from the
thermal diode. The value for Tcontrol will be calibrated in manufacturing and configured
for each processor. The Tcontrol value is set identically for both processor cores. The
Tcontrol temperature for a given processor can be obtained by reading the
IA32_TEMPERATURE_TARGET MSR in the processor. The Tcontrol value that is read
from the IA32_TEMPERATURE_TARGET MSR must be converted from Hexadecimal to
Decimal and added to a base value of 60° C. The value of Tcontrol may vary from 0x00h
to 0x1Eh.
When Tdiode is above Tcontrol, then TCASE must be at or below TCASE_MAX as defined by
the thermal profile. (Refer to Figure 6-1, Figure 6-2 and Figure 6-3 ; Table 6-2,
Table 6-3, Table 6-5, Table 6-6 and Table 6-8). Otherwise, the processor temperature
can be maintained at or below Tcontrol.
6.2.7
Thermal Diode
The Dual-Core Intel Xeon Processor 5000 series incorporates an on-die PNP transistor
whose base emitter junction is used as a thermal “diode”, one per core, with its
collector shorted to Ground. A thermal sensor located on the system board may
monitor the die temperature of the processor for thermal management and fan speed
control. Table 6-9, Table 6-11 and Table 6-12 provide the “diode” parameters and
interface specifications. Two different sets of “diode” parameters are listed in Table 6-9
and Table 6-11. The Diode Model parameters (Table 6-9) apply to traditional thermal
sensors that use the Diode Equation to determine the processor temperature.
Transistor Model parameters (Table 6-11) have been added to support thermal sensors
that use the transistor equation method. The Transistor Model may provide more
accurate temperature measurements when the diode ideality factor is closer to the
maximum or minimum limits. This thermal “diode” is separate from the Thermal
Monitor’s thermal sensor and cannot be used to predict the behavior of the Thermal
Monitor.
When calculating a temperature based on thermal diode measurements, a number of
parameters must be either measured or assumed. Most devices measure the diode
ideality and assume a series resistance and ideality trim value, although some are
capable of also measuring the series resistance. Calculating the temperature is then
accomplished by using the equations listed under Table 6-9. In most temperature
sensing devices, an expected value for the diode ideality is designed-in to the
temperature calculation equation. If the designer of the temperature sensing device
assumes a perfect diode, the ideality value (also called ntrim) will be 1.000. Given that
most diodes are not perfect, the designers usually select an ntrim value that more
closely matches the behavior of the diodes in the processor. If the processors diode
ideality deviates from that of ntrim, each calculated temperature will be offset by a fixed
amount. The temperature offset can be calculated with the equation:
Terror(nf) = Tmeasured X (1- nactual/ntrim
)
where Terror(nf) is the offset in degrees C, Tmeasured is in Kelvin, nactual is the measured
ideality of the diode, and ntrim is the diode ideality assumed by the temperature sensing
device.
In order to improve the accuracy of diode based temperature measurements, a new
register (Tdiode_Offset) has been added to Dual-Core Intel Xeon Processor 5000 series
which will contain thermal diode characterization data. During manufacturing each
processor’s thermal diode will be evaluated for its behavior relative to a theoretical
diode. Using the equation above, the temperature error created by the difference
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
79
Thermal Specifications
between ntrim and the actual ideality of the particular processor will be calculated. This
value (Tdiode_Offset) will be programmed into the new diode correction MSR and then
added to the Tdiode_Base value can be used to correct temperatures read by diode
based temperature sensing devices.
If the ntrim value used to calculating Tdiode_Offset differs from the ntrim value used in a
temperature sensing device, the Terror(nf) may not be accurate. If desired, the
Tdiode_Offset can be adjusted by calculating nactual and then recalculating the offset
using the actual ntrim as defined in the temperature sensor manufacturers’ datasheet.
The parameters used to calculate the Thermal Diode (Tdiode) Correction Factor are
listed in Table 6-12. For Dual-Core Intel Xeon Processor 5000 series, the range of
Tdiode Correction Factor is ±14°C.
.
Table 6-9.
Thermal Diode Parameters using Diode Model
Symbol
Parameter
Min
Typ
Max
Unit
Notes
I
Forward Bias Current
Diode Ideality Factor
Series Resistance
5
-
200
1.050
6.24
µA
-
1
FW
n
1.000
2.79
1.009
4.52
2, 3, 4
2, 3, 5
R
T
Ω
Notes:
1.
2.
3.
4.
Intel does not support or recommend operation of the thermal diode under reverse bias.
Characterized across a temperature range of 50-80°C.
Not 100% tested. Specified by design characterization.
The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode
qVD/nkT
equation: I
= I * (e
- 1)
FW
S
Where I = saturation current, q = electronic charge, V = voltage across the diode, k = Boltzmann
S
D
Constant, and T = absolute temperature (Kelvin).
5.
The series resistance, R , is provided to allow for a more accurate measurement of the junction
T
temperature. R , as defined, includes the lands of the processor but does not include any socket resistance
T
or board trace resistance between the socket and external remote diode thermal sensor. R can be used by
T
remote diode thermal sensors with automatic series resistance cancellation to calibrate out this error term.
Another application is that a temperature offset can be manually calculated and programmed into an offset
register in the remote diode thermal sensors as exemplified by the equation:
Terror = [R * (N-1) * I min] / [nk/q *ln N]
T
FW
Where Terror=sensor temperature error, N=sensor current ratio, k=Boltzmann Constant, q=electronic
charge.
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Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Thermal Specifications
Table 6-10. Thermal Diode Interface
Land Name
Land Number
Description
THERMDA
AL1
AK1
AJ7
diode anode
diode cathode
diode anode
diode cathode
THERMDC
THERMDA2
THERMDC2
AH7
.
Table 6-11. Thermal Diode Parameters using Transistor Model
Symbol
Parameter
Min
Typ
Max
Unit
Notes
I
Forward Bias Current
Emitter Current
Transistor Ideality
-
5
-
-
200
200
µA
µA
-
1, 2
FW
I
5
E
n
0.997
0.391
2.79
1.001
-
1.005
0.760
6.24
3, 4, 5
3, 4
Q
Beta
-
R
Series Resistance
4.52
3, 6
T
Ω
Notes:
1.
2.
3.
4.
5.
Intel does not support or recommend operation of the thermal diode under reverse bias.
Same as I in the diode model in Table 6-9.
Characterized across a temperature range of 50-80°C.
Not 100% tested. Specified by design characterization.
The ideality factor, n , represents the deviation from ideal transistor model behavior as exemplified by the
equation for the collector current: I = I * (e
FW
Q
qVBE/n kT
- 1)
BE
C
S
Q
Where I = saturation current, q = electronic charge, V = voltage across the transistor based emitter
S
junction (same nodes as V ), k = Boltzmann Constant, and T = absolute temperature (Kelvin).
The series resistance, R provided in Table 6-9 can be used for more accurate readings as needed.
D
6.
T
Table 6-12. Parameters for Tdiode Correction Factor
Symbol
Parameter
Typ
Unit
Notes
n
Diode Ideality used to calculate
Tdiode_Offset
1.008
1
trim
Tdiode_Base
0
°C
1
Notes:
1.
®
®
See the Dual-Core Intel Xeon Processor 5000 Series Thermal/Mechanical Design Guidelines for more
information on how to use the Tdiode_Offset, Tdiode_Base and n
parameters for fan speed control.
trim
§
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
81
Thermal Specifications
82
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Features
7 Features
7.1
Power-On Configuration Options
Several configuration options can be configured by hardware. The Dual-Core Intel Xeon
Processor 5000 series samples its hardware configuration at reset, on the active-to-
inactive transition of RESET#. For specifics on these options, please refer to Table 7-1.
The sampled information configures the processor for subsequent operation. These
configuration options cannot be changed except by another reset. All resets reconfigure
the processor, for reset configuration purposes, the processor does not distinguish
between a “warm” reset (PWRGOOD signal remains asserted during reset) and a
“power-on” reset.
Table 7-1.
Power-On Configuration Option Lands
Configuration Option
Output tri state
Land Name
Notes
SMI#
A3#
1,2
1,2
1,2
Execute BIST (Built-In Self Test)
In Order Queue de-pipelining (set IOQ depth to
1)
A7#
Disable MCERR# observation
Disable BINIT# observation
Disable bus parking
A9#
A10#
1,2
1,2
A15#
1,2
Symmetric agent arbitration ID
Force single logical processor
BR[1:0]#
A31#
1,2
1,2,3
Notes:
1.
2.
3.
Asserting this signal during RESET# will select the corresponding option.
Address pins not identified in this table as configuration options should not be asserted during RESET#.
This mode is not tested.
7.2
Clock Control and Low Power States
The Dual-Core Intel Xeon Processor 5000 series support the Enhanced HALT
Powerdown state in addition to the HALT Powerdown state and Stop-Grant states to
reduce power consumption by stopping the clock to internal sections of the processor,
depending on each particular state. See Figure 7-1 for a visual representation of the
processor low power states.
The Enhanced HALT state is enabled by default in the Dual-Core Intel Xeon Processor
5000 series. The Enhanced HALT state must remain enabled via the BIOS for the
processor to remain within its specifications. For processors that are already running at
the lowest core to bus ratio for its nominal operating point, the processor will transition
to the HALT Powerdown state instead of the Enhanced HALT state.
The Stop Grant state requires chipset and BIOS support on multiprocessor systems. In
a multiprocessor system, all the STPCLK# signals are bussed together, thus all
processors are affected in unison. The Hyper-Threading Technology feature adds the
conditions that all logical processors share the same STPCLK# signal internally. When
the STPCLK# signal is asserted, the processor enters the Stop Grant state, issuing a
Stop Grant Special Bus Cycle (SBC) for each processor or logical processor. The chipset
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
83
Features
needs to account for a variable number of processors asserting the Stop Grant SBC on
the bus before allowing the processor to be transitioned into one of the lower processor
power states. Refer to the applicable chipset specification for more information.
7.2.1
7.2.2
Normal State
This is the normal operating state for the processor.
HALT or Enhanced Powerdown States
The Enhanced HALT power down state is enabled by default in the Dual-Core Intel Xeon
Processor 5000 series. The Enhanced HALT power down state must remain enabled
via the BIOS. The Enhanced HALT state requires support for dynamic VID transitions in
the platform.
7.2.2.1
HALT Powerdown State
HALT is a low power state entered when all logical processors have executed the HALT
or MWAIT instruction. When one of the logical processors executes the HALT or MWAIT
instruction, that logical processor is halted; however, the other processor continues
normal operation. The processor will transition to the Normal state upon the occurrence
of SMI#, BINIT#, INIT#, LINT[1:0] (NMI, INTR), or an interrupt delivered over the
front side bus. RESET# will cause the processor to immediately initialize itself.
The return from a System Management Interrupt (SMI) handler can be to either
Normal Mode or the HALT Power Down state. Refer to the IA-32 Intel® Architecture
Software Developer's Manual, Volume III: System Programming Guide for more
information.
The system can generate a STPCLK# while the processor is in the HALT Power Down
state. When the system deasserts the STPCLK#, the processor will return execution to
the HALT state.
While in HALT Power Down state, the processor will process front side bus snoops and
interrupts.
7.2.2.2
Enhanced HALT Powerdown State
Enhanced HALT state is a low power state entered when all logical processors have
executed the HALT or MWAIT instructions. When one of the logical processors executes
the HALT instruction, that logical processor is halted; however, the other processor
continues normal operation. The Enhanced HALT state is generally a lower power state
than the Stop Grant state.
The processor will automatically transition to a lower core frequency and voltage
operating point before entering the Enhanced HALT state. Note that the processor FSB
frequency is not altered; only the internal core frequency is changed. When entering
the low power state, the processor will first switch to the lower bus ratio and then
transition to the lower VID.
While in the Enhanced HALT state, the processor will process bus snoops.
The processor exits the Enhanced HALT state when a break event occurs. When the
processor exits the Enhanced HALT state, it will first transition the VID to the original
value and then change the bus ratio back to the original value.
84
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Features
The Enhanced HALT state must be enabled by way of the BIOS for the processor to
remain within its specifications. The Enhanced HALT state requires support for dynamic
VID transitions in the platform.
Figure 7-1. Stop Clock State Machine
HALT or MWAIT Instruction and
HALT Bus Cycle Generated
Enhanced HALT or HALT State
BCLK running
Normal State
INIT#, BINIT#, INTR, NMI, SMI#,
RESET#, FSB interrupts
Normal execution
Snoops and interrupts allowed
Snoop
Event
Occurs Serviced
Snoop
Event
STPCLK#
Asserted
STPCLK#
De-asserted
Enhanced HALT Snoop or HALT
Snoop State
BCLK running
Service snoops to caches
Snoop Event Occurs
Snoop Event Serviced
Stop Grant State
Stop Grant Snoop State
BCLK running
BCLK running
Snoops and interrupts allowed
Service snoops to caches
7.2.3
Stop-Grant State
When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20
bus clocks after the response phase of the processor-issued Stop Grant Acknowledge
special bus cycle. Once the STPCLK# pin has been asserted, it may only be deasserted
once the processor is in the Stop Grant state. For the Dual-Core Intel Xeon Processor
5000 series, all logical processor cores will enter the Stop-Grant state once the
STPCLK# pin is asserted. Additionally, all logical cores must be in the Stop Grant state
before the deassertion of STPCLK#.
Since the AGTL+ signal pins receive power from the front side bus, these pins should
not be driven (allowing the level to return to VTT) for minimum power drawn by the
termination resistors in this state. In addition, all other input pins on the front side bus
should be driven to the inactive state.
BINIT# will not be serviced while the processor is in Stop-Grant state. The event will be
latched and can be serviced by software upon exit from the Stop Grant state.
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
85
Features
RESET# will cause the processor to immediately initialize itself, but the processor will
stay in Stop-Grant state. A transition back to the Normal state will occur with the de-
assertion of the STPCLK# signal.
A transition to the Grant Snoop state will occur when the processor detects a snoop on
the front side bus (see Section 7.2.4.1).
While in the Stop-Grant state, SMI#, INIT#, BINIT# and LINT[1:0] will be latched by
the processor, and only serviced when the processor returns to the Normal state. Only
one occurrence of each event will be recognized upon return to the Normal state.
While in Stop-Grant state, the processor will process snoops on the front side bus and it
will latch interrupts delivered on the front side bus.
The PBE# signal can be driven when the processor is in Stop-Grant state. PBE# will be
asserted if there is any pending interrupt latched within the processor. Pending
interrupts that are blocked by the EFLAGS.IF bit being clear will still cause assertion of
PBE#. Assertion of PBE# indicates to system logic that it should return the processor to
the Normal state.
7.2.4
Enhanced HALT Snoop or HALT Snoop State,
Stop Grant Snoop State
The Enhanced HALT Snoop state is used in conjunction with the Enhanced HALT state.
If the Enhanced HALT state is not enabled in the BIOS, the default Snoop state entered
will be the HALT Snoop state. Refer to the sections below for details on HALT Snoop
state, Stop Grant Snoop state and Enhanced HALT Snoop state.
7.2.4.1
HALT Snoop State, Stop Grant Snoop State
The processor will respond to snoop or interrupt transactions on the front side bus
while in Stop-Grant state or in HALT Power Down state. During a snoop or interrupt
transaction, the processor enters the HALT/Grant Snoop state. The processor will stay
in this state until the snoop on the front side bus has been serviced (whether by the
processor or another agent on the front side bus) or the interrupt has been latched.
After the snoop is serviced or the interrupt is latched, the processor will return to the
Stop-Grant state or HALT Power Down state, as appropriate.
7.2.4.2
7.3
86
Enhanced HALT Snoop State
The Enhanced HALT Snoop state is the default Snoop state when the Enhanced HALT
state is enabled via the BIOS. The processor will remain in the lower bus ratio and VID
operating point of the Enhanced HALT state.
While in the Enhanced HALT Snoop state, snoops and interrupt transactions are
handled the same way as in the HALT Snoop state. After the snoop is serviced or the
interrupt is latched, the processor will return to the Enhanced HALT state.
Enhanced Intel SpeedStep® Technology
The Dual-Core Intel Xeon Processor 5000 series support Enhanced Intel SpeedStep
Technology. This technology enables the processor to switch between multiple
frequency and voltage points, which results in platform power savings. Enhanced Intel
SpeedStep Technology requires support for dynamic VID transitions in the platform.
Switching between voltage/frequency states is software controlled.
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Features
Note:
Not all Dual-Core Intel Xeon Processor 5000 series are capable of supporting Enhanced
Intel SpeedStep Technology. More details on which processor frequencies will support
this feature will be provided in future releases of the Dual-Core Intel® Xeon® Processor
5000 Series Specification Update when available.
Enhanced Intel SpeedStep Technology creates processor performance states (P-states)
or voltage/frequency operating points. P-states are lower power capability states within
the Normal state as shown in Figure 7-1. Enhanced Intel SpeedStep Technology
enables real-time dynamic switching between frequency and voltage points. It alters
the performance of the processor by changing the bus to core frequency ratio and
voltage. This allows the processor to run at different core frequencies and voltages to
best serve the performance and power requirements of the processor and system. The
Dual-Core Intel Xeon Processor 5000 series have hardware logic that coordinates the
requested processor voltage between the processor cores. The highest voltage that is
requested for either of the processor cores is selected for that processor. Note that the
front side bus is not altered; only the internal core frequency is changed. In order to
run at reduced power consumption, the voltage is altered in step with the bus ratio.
The following are key features of Enhanced Intel SpeedStep Technology:
• Multiple voltage/frequency operating points provide optimal performance at
reduced power consumption.
• Voltage/frequency selection is software controlled by writing to processor MSR’s
(Model Specific Registers), thus eliminating chipset dependency.
— If the target frequency is higher than the current frequency, VCC is incremented
in steps (+12.5 mV) by placing a new value on the VID signals and the
processor shifts to the new frequency. Note that the top frequency for the
processor can not be exceeded.
— If the target frequency is lower than the current frequency, the processor shifts
to the new frequency and VCC is then decremented in steps (-12.5 mV) by
changing the target VID through the VID signals.
§
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
87
Features
88
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Boxed Processor Specifications
8 Boxed Processor Specifications
8.1
Introduction
Intel boxed processors are intended for system integrators who build systems from
components available through distribution channels. The Dual-Core Intel® Xeon®
Processor 5000 series will be offered as an Intel boxed processor.
Intel will offer the Dual-Core Intel Xeon Processor 5000 series boxed processor with
two heat sink configurations available for each processor frequency: 1U passive/2U
active combination solution and a 2U passive only solution. The 1U passive/2U active
combination solution is based on a 1U passive heat sink with a removable fan that will
be pre-attached at shipping. This heat sink solution is intended to be used as either a
1U passive heat sink or a 2U+ active heat sink. Although the active combination
solution with removable fan mechanically fits into a 2U keepout, additional design
considerations may need to be addressed to provide sufficient airflow to the fan inlet.
The 1U passive/2U active combination solution in the active fan configuration is
primarily designed to be used in a pedestal chassis where sufficient air inlet space is
present and strong side directional airflow is not an issue. The 1U passive/active
combination solution with the fan removed and the 2U passive thermal solution require
the use of chassis ducting and are targeted for use in rack mount servers. The
retention solution used for these products is called the Common Enabling Kit, or CEK.
The CEK base is compatible with both thermal solutions and uses the same hole
locations as the Intel® Xeon® processor with 800 MHz FSB.
The 1U passive/active combination solution will utilize a removable fan with a 4-pin
pulse width modulated (PWM) T-diode control. Use of a 4-pin PWM T-diode controlled
active thermal solution helps customers meet acoustic targets in pedestal platforms
through the motherboards’s ability to directly control the RPM of the processor heat
sink fan. Please see Section 8.3 for more details. Figure 8-1 through Figure 8-3 are
representations of the two heat sink solutions.
Figure 8-1. Boxed Dual-Core Intel Xeon Processor 5000 Series 1U Passive/2U Active
Combination Heat Sink (With Removable Fan)
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
89
Boxed Processor Specifications
Figure 8-2. Boxed Dual-Core Intel Xeon Processor 5000 Series 2U Passive Heat Sink
Figure 8-3. 2U Passive Dual-Core Intel Xeon Processor 5000 Series Thermal Solution
(Exploded View)
Heat sink screw
springs
Heat sink
screws
Heat sink
Heat sink standoffs
Thermal Interface
Material
Motherboard
and
processor
Protective Tape
CEK spring
Chassis pan
Notes:
1.
2.
3.
The heat sinks represented in these images are for reference only, and may not represent the final boxed
processor heat sinks.
The screws, springs, and standoffs will be captive to the heat sink. This image shows all of the components
in an exploded view.
It is intended that the CEK spring will ship with the base board and be pre-attached prior to shipping.
8.2
Mechanical Specifications
This section documents the mechanical specifications of the boxed processor.
90
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Boxed Processor Specifications
8.2.1
Boxed Processor Heat Sink Dimensions (CEK)
The boxed processor will be shipped with an unattached thermal solution. Clearance is
required around the thermal solution to ensure unimpeded airflow for proper cooling.
The physical space requirements and dimensions for the boxed processor and
assembled heat sink are shown in Figure 8-4 through Figure 8-8. Figure 8-9 through
Figure 8-10 are the mechanical drawings for the 4-pin board fan header and 4-pin
connector used for the active CEK fan heat sink solution.
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
91
Boxed Processor Specifications
Figure 8-4. Top Side Board Keep-Out Zones (Part 1)
92
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Boxed Processor Specifications
Figure 8-5. Top Side Board Keep-Out Zones (Part 2)
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Boxed Processor Specifications
Figure 8-6. Bottom Side Board Keep-Out Zones
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Boxed Processor Specifications
Figure 8-7. Board Mounting Hole Keep-Out Zones
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Figure 8-8. Volumetric Height Keep-Ins
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Figure 8-9. 4-Pin Fan Cable Connector (For Active CEK Heat Sink)
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Boxed Processor Specifications
Figure 8-10. 4-Pin Base Board Fan Header (For Active CEK Heat Sink)
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Boxed Processor Specifications
8.2.2
Boxed Processor Heat Sink Weight
8.2.2.1
Thermal Solution Weight
The 1U passive/2U active combination heat sink solution and the 2U passive heat sink
solution will not exceed a mass of 1050 grams. Note that this is per processor, so a dual
processor system will have up to 2100 grams total mass in the heat sinks. This large
mass will require a minimum chassis stiffness to be met in order to withstand force
during shock and vibration.
See Section 3 for details on the processor weight.
8.2.3
Boxed Processor Retention Mechanism and
Heat Sink Support (CEK)
Baseboards and chassis designed for use by a system integrator should include holes
that are in proper alignment with each other to support the boxed processor. Refer to
the Server System Infrastructure Specification (SSI-EEB 3.6, TEB 2.1 or CEB 1.1).
These specification can be found at: http://www.ssiforum.org.
Figure 8-3 illustrates the Common Enabling Kit (CEK) retention solution. The CEK is
designed to extend air-cooling capability through the use of larger heat sinks with
minimal airflow blockage and bypass. CEK retention mechanisms can allow the use of
much heavier heat sink masses compared to legacy limits by using a load path directly
attached to the chassis pan. The CEK spring on the secondary side of the baseboard
provides the necessary compressive load for the thermal interface material. The
baseboard is intended to be isolated such that the dynamic loads from the heat sink are
transferred to the chassis pan via the stiff screws and standoffs. The retention scheme
reduces the risk of package pullout and solder joint failures.
All components of the CEK heat sink solution will be captive to the heat sink and will
only require a Phillips screwdriver to attach to the chassis pan. When installing the
CEK, the CEK screws should be tightened until they will no longer turn easily. This
should represent approximately 8 inch-pounds of torque. Avoid applying more than 10
inch-pounds of torque; otherwise, damage may occur to retention mechanism
components.
8.3
Electrical Requirements
8.3.1
Fan Power Supply (Active CEK)
The 4-pin PWM/T-diode controlled active thermal solution is being offered to help
provide better control over pedestal chassis acoustics. This is achieved though more
accurate measurement of processor die temperature through the processor’s
temperature diode (T-diode). Fan RPM is modulated through the use of an ASIC located
on the baseboard that sends out a PWM control signal to the 4th pin of the connector
labeled as Control. This thermal solution requires a constant +12 V supplied to pin 2 of
the active thermal solution and does not support variable voltage control or 3-pin PWM
control. See Table 8-2 for details on the 4-pin active heat sink solution connectors.
If the 4-pin active fan heat sink solution is connected to an older 3-pin baseboard CPU
fan header it will default back to a thermistor controlled mode, allowing compatibility
with legacy 3-wire designs. When operating in thermistor controlled mode, fan RPM is
automatically varied based on the TINLET temperature measured by a thermistor
located at the fan inlet of the heat sink solution.
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Boxed Processor Specifications
The fan power header on the baseboard must be positioned to allow the fan heat sink
power cable to reach it. The fan power header identification and location must be
documented in the suppliers platform documentation, or on the baseboard itself. The
baseboard fan power header should be positioned within 177.8 mm [7 in.] from the
center of the processor socket.
Table 8-1.
Table 8-2.
PWM Fan Frequency Specifications for 4-Pin Active CEK Thermal Solution
Description
Min Frequency
Nominal Frequency
Max Frequency
Unit
PWM Control
21,000
25,000
28,000
Hz
Frequency Range
Fan Specifications for 4-pin Active CEK Thermal Solution
Typ
Steady
Max
Steady
Max
Startup
Description
Min
Unit
+12 V: 12 volt fan power supply
IC: Fan Current Draw
10.8
N/A
2
12
1
12
1.25
2
13.2
1.5
2
V
A
SENSE: SENSE frequency
2
Pulses per fan
revolution
Figure 8-11. Fan Cable Connector Pin Out for 4-Pin Active CEK Thermal Solution
Table 8-3.
Fan Cable Connector Pin Out for 4-Pin Active CEK Thermal Solution
Pin Number
Signal
Color
1
2
3
4
Ground
Black
Yellow
Green
Blue
Power: (+12 V)
Sense: 2 pulses per revolution
Control: 21 KHz-28 KHz
8.3.2
Boxed Processor Cooling Requirements
As previously stated the boxed processor will be available in two product
configurations. Each configuration will require unique design considerations. Meeting
the processor’s temperature specifications is also the function of the thermal design of
the entire system, and ultimately the responsibility of the system integrator. The
processor temperature specifications are found in Chapter 6, “Thermal Specifications”
of this document.
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8.3.2.1
1U Passive/2U Active Combination Heat Sink Solution (1U Rack
Passive)
In the 1U configuration it is assumed that a chassis duct will be implemented to provide
sufficient airflow to pass through the heat sink fins. Currently the actual airflow target
is within the range of 15-27 CFM. The duct should be designed as precisely as possible
and should not allow any air to bypass the heat sink (0” bypass) and a back pressure of
0.38 in. H2O. It is assumed that a 40°C TLA is met. This requires a superior chassis
design to limit the TRISE at or below 5°C with an external ambient temperature of 35°C.
Following these guidelines will allow the designer to meet Thermal Profile B and
conform to the thermal requirements of the processor.
8.3.2.2
1U Passive/2U Active Combination Heat Sink Solution (Pedestal
Active)
The active configuration of the combination solution is designed to help pedestal
chassis users to meet the thermal processor requirements without the use of chassis
ducting. It may be still be necessary to implement some form of chassis air guide or air
duct to meet the TLA temperature of 40°C depending on the pedestal chassis layout.
Also, while the active thermal solution is designed to mechanically fit into a 2U
volumetric, it may require additional space at the top of the thermal solution to allow
sufficient airflow into the heat sink fan. Therefore, additional design criteria may need
to be considered if this thermal solution is used in a 2U rack mount chassis, or in a
chassis that has drive bay obstructions above the inlet to the fan heat sink. Use of the
active configuration in rackmount chassis is not recommended.
It is recommended that the ambient air temperature outside of the chassis be kept at
or below 35°C. The air passing directly over the processor thermal solution should not
be preheated by other system components. Meeting the processor’s temperature
specification is the responsibility of the system integrator.
8.3.2.3
2U Passive Heat Sink Solution (2U+ Rack or Pedestal)
A chassis duct is required for the 2U passive heat sink. In this configuration the thermal
profile (see Section 6) should be followed by supplying 27 CFM of airflow through the
fins of the heat sink with a 0” or no duct bypass and a back pressure of 0.182 in. H2O.
The TLA temperature of 40°C should be met. This may require the use of superior
design techniques to keep TRISE at or below 5°C based on an ambient external
temperature of 35°C.
8.4
Boxed Processor Contents
A direct chassis attach method must be used to avoid problems related to shock and
vibration, due to the weight of the thermal solution required to cool the processor. The
board must not bend beyond specification in order to avoid damage. The boxed
processor contains the components necessary to solve both issues. The boxed
processor will include the following items:
• Dual-Core Intel Xeon Processor 5000 series
• Unattached Heat Sink Solution
• 4 screws, 4 springs, and 4 heat sink standoffs (all captive to the heat sink)
• Thermal Interface Material (pre-applied on heat sink)
• Installation Manual
• Intel Branding Logo
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The other items listed in Figure 8-3 that are required to compete this solution will be
shipped with either the chassis or boards. They are as follows:
• CEK Spring (supplied by baseboard vendors)
• Heat sink standoffs (supplied by chassis vendors)
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Debug Tools Specifications
9 Debug Tools Specifications
Please refer to the eXtended Debug Port: Debug Port Design Guide for UP and DP
Platforms and the appropriate platform design guidelines for information regarding
debug tool specifications. Section 1.3 provides collateral details.
9.1
Debug Port System Requirements
The Dual-Core Intel Xeon Processor 5000 series debug port is the command and
control interface for the In-Target Probe (ITP) debugger. The ITP enables run-time
control of the processors for system debug. The debug port, which is connected to the
FSB, is a combination of the system, JTAG and execution signals. There are several
mechanical, electrical and functional constraints on the debug port that must be
followed. The mechanical constraint requires the debug port connector to be installed in
the system with adequate physical clearance. Electrical constraints exist due to the
mixed high and low speed signals of the debug port for the processor. While the JTAG
signals operate at a maximum of 75 MHz, the execution signals operate at the common
clock FSB frequency. The functional constraint requires the debug port to use the JTAG
system via a handshake and multiplexing scheme.
In general, the information in this chapter may be used as a basis for including all run-
control tools in Dual-Core Intel Xeon Processor 5000 series-based system designs,
including tools from vendors other than Intel.
Note:
The debug port and JTAG signal chain must be designed into the processor board to
utilize the XDP for debug purposes except for interposer solutions.
9.2
Target System Implementation
9.2.1
System Implementation
Specific connectivity and layout guidelines for the Debug Port are provided in the
eXtended Debug Port: Debug Port Design Guide for UP and DP Platforms and the
appropriate platform design guidelines.
9.3
Logic Analyzer Interface (LAI)
Intel is working with two logic analyzer vendors to provide logic analyzer interfaces
(LAIs) for use in debugging Dual-Core Intel Xeon Processor 5000 series systems.
Tektronix and Agilent should be contacted to obtain specific information about their
logic analyzer interfaces. The following information is general in nature. Specific
information must be obtained from the logic analyzer vendor.
Due to the complexity of Dual-Core Intel Xeon Processor 5000 series-based
multiprocessor systems, the LAI is critical in providing the ability to probe and capture
FSB signals. There are two sets of considerations to keep in mind when designing a
Dual-Core Intel Xeon Processor 5000 series-based system that can make use of an LAI:
mechanical and electrical.
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9.3.1
Mechanical Considerations
The LAI is installed between the processor socket and the processor. The LAI plugs into
the socket, while the processor plugs into a socket on the LAI. Cabling that is part of
the LAI egresses the system to allow an electrical connection between the processor
and a logic analyzer. The maximum volume occupied by the LAI, known as the keepout
volume, as well as the cable egress restrictions, should be obtained from the logic
analyzer vendor. System designers must make sure that the keepout volume remains
unobstructed inside the system. Note that it is possible that the keepout volume
reserved for the LAI may include differerent requirements from the space normally
occupied by the heatsink. If this is the case, the logic analyzer vendor will provide a
cooling solution as part of the LAI.
9.3.2
Electrical Considerations
The LAI will also affect the electrical performance of the FSB, therefore it is critical to
obtain electrical load models from each of the logic analyzer vendors to be able to run
system level simulations to prove that their tool will work in the system. Contact the
logic analyzer vendor for electrical specifications and load models for the LAI solution
they provide.
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