273804-002 [INTEL]
Ultra-Low Voltage Intel-R Celeron-R Processor (0.13 u in the Micro FC-BGA Package; 超低电压的英特尔-R赛扬-R处理器（ 0.13 ü在微FC- BGA封装
| 型号： | 273804-002 |
| 厂家： | 
INTEL |
| 描述： | Ultra-Low Voltage Intel-R Celeron-R Processor (0.13 u in the Micro FC-BGA Package |
| 文件： | 总82页 (文件大小：1500K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultra-Low Voltage Intel® Celeron®
Processor (0.13 µ) in the Micro FC-BGA
Package
at 650 MHz and 400 MHz
Datasheet
Product Features
■ Ultra-Low Voltage Intel® Celeron®
Processor (0.13µ) with the following
processor core/bus speeds:
■ Micro-FCBGA packaging technologies
—Supports small form factor applied
computing designs
—650/100 MHz at 1.10 V
—400/100 MHz at 0.95 V
—Exposed die enables more efficient heat
dissipation
■ Supports the Intel Architecture with
■ Fully compatible with previous Intel
Dynamic Execution
microprocessors
■ On-die primary 16-Kbyte instruction cache
—Binary compatible with all applications
—Support for MMX™ technology
and 16-Kbyte write-back data cache
■ On-die second level cache (256-Kbyte)
with Advanced Transfer Cache
Architecture
—Support for Streaming SIMD Extensions
■ Power Management Features
■ Data Prefetch Logic
■ Integrated AGTL termination
■ Integrated math co-processor
—Quick Start and Deep Sleep modes
provide low power dissipation
■ On-die thermal diode
Order Number: 273804-002
May 2003
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Ultra Low Voltage Intel® Celeron® Processor (0.13 µ) in the Micro FC-BGA Package at 650 Mhz and 400 MHz may contain design defects or
errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation, 2003
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*Other names and brands may be claimed as the property of others.
2
Datasheet
Contents
Contents
1.0 Introduction....................................................................................................................................9
1.1
1.2
1.3
1.4
Overview...............................................................................................................................9
State of the Data.................................................................................................................10
Terminology........................................................................................................................10
References .........................................................................................................................10
2.0 Ultra-Low Voltage Intel® Celeron® Processor Features...........................................................13
2.1
New Features in the Ultra-Low Voltage Intel® Celeron® Processor....................................13
2.1.1 100-MHz PSB With AGTL Signaling......................................................................13
2.1.2 256-K On-die Integrated L2 Cache........................................................................13
2.1.3 Data Prefetch Logic ...............................................................................................13
2.1.4 Differential Clocking...............................................................................................13
2.1.5 Signal Differences Between the Mobile Intel® Celeron®
Processor in BGA2 and Micro-PGA2 Packages and
the Ultra-Low Voltage Intel® Celeron® Processor in Micro FC-BGA Packages.....13
Power Management............................................................................................................14
2.2.1 Clock Control Architecture .....................................................................................14
2.2.2 Normal State..........................................................................................................14
2.2.3 Auto Halt State.......................................................................................................14
2.2.4 Quick Start State....................................................................................................15
2.2.5 HALT/Grant Snoop State.......................................................................................16
2.2.6 Deep Sleep State...................................................................................................16
2.2.7 Operating System Implications of Low-power States ............................................16
AGTL Signals......................................................................................................................17
Ultra-Low Voltage Intel® Celeron® Processor CPUID ........................................................17
2.2
2.3
2.4
3.0 Electrical Specifications .............................................................................................................19
3.1
Processor System Signals..................................................................................................19
3.1.1 Power Sequencing Requirements .........................................................................20
3.1.2 Test Access Port (TAP) Connection ......................................................................21
3.1.3 Catastrophic Thermal Protection ...........................................................................21
3.1.4 Unused Signals......................................................................................................21
3.1.5 Signal State in Low-power States..........................................................................21
Power Supply Requirements ..............................................................................................22
3.2.1 Decoupling Guidelines...........................................................................................22
3.2.2 Voltage Planes.......................................................................................................23
3.2.3 PLL RLC Filter Specification..................................................................................23
3.2.4 Voltage Identification .............................................................................................26
3.2.5 VTTPWRGD Signal Quality Specification..............................................................27
System Bus Clock and Processor Clocking........................................................................28
Maximum Ratings ...............................................................................................................29
DC Specifications ...............................................................................................................30
AC Specifications................................................................................................................34
3.6.1 System Bus, Clock, APIC, TAP, CMOS, and Open-drain AC Specifications ........34
3.2
3.3
3.4
3.5
3.6
4.0 System Signal Simulations.........................................................................................................47
4.1
System Bus Clock (BCLK) and PICCLK DC
Datasheet
3
Contents
Specifications and AC Signal Quality Specifications47
4.2
4.3
AGTL AC Signal Quality Specifications..............................................................................48
Non-AGTL Signal Quality Specifications............................................................................50
4.3.1 PWRGOOD, VTTPWRGD Signal Quality Specifications ......................................50
5.0 Mechanical Specifications..........................................................................................................53
5.1
5.2
Surface Mount Micro FC-BGA Package.............................................................................53
Signal Listings.....................................................................................................................55
6.0 VCC Thermal Specifications.......................................................................................................65
6.1 Thermal Diode ....................................................................................................................66
7.0 Processor Initialization and Configuration ...............................................................................67
7.1
Description..........................................................................................................................67
7.1.1 Quick Start Enable.................................................................................................67
7.1.2 System Bus Frequency..........................................................................................67
7.1.3 APIC Enable ..........................................................................................................67
Clock Frequencies and Ratios............................................................................................67
7.2
8.0 Processor Interface.....................................................................................................................69
8.1
Alphabetical Signal Reference............................................................................................69
8.1.1 A[35:3]# (I/O – AGTL)............................................................................................69
8.1.2 A20M# (I - 1.5V Tolerant) ......................................................................................69
8.1.3 ADS# (I/O - AGTL).................................................................................................69
8.1.4 AERR# (I/O - AGTL)..............................................................................................69
8.1.5 AP[1:0]# (I/O - AGTL) ............................................................................................69
8.1.6 BCLK, BCLK# (I)....................................................................................................70
8.1.7 BERR# (I/O - AGTL)..............................................................................................70
8.1.8 BINIT# (I/O - AGTL)...............................................................................................70
8.1.9 BNR# (I/O - AGTL) ................................................................................................71
8.1.10 BP[3:2]# (I/O - AGTL) ............................................................................................71
8.1.11 BPM[1:0]# (I/O - AGTL) .........................................................................................71
8.1.12 BPRI# (I - AGTL) ...................................................................................................71
8.1.13 BREQ0# (I/O - AGTL)............................................................................................71
8.1.14 BSEL[1:0] (O – 3.3V Tolerant)...............................................................................71
8.1.15 CLKREF (Analog)..................................................................................................72
8.1.16 CMOSREF (Analog) ..............................................................................................72
8.1.17 D[63:0]# (I/O - AGTL) ............................................................................................72
8.1.18 DBSY# (I/O - AGTL) ..............................................................................................72
8.1.19 DEFER# (I - AGTL)................................................................................................72
8.1.20 DEP[7:0]# (I/O - AGTL)..........................................................................................73
8.1.21 DRDY# (I/O - AGTL)..............................................................................................73
8.1.22 DPSLP# (I - 1.5 V Tolerant)...................................................................................73
8.1.23 EDGCTRLP (I-Analog) ..........................................................................................73
8.1.24 FERR# (O - 1.5 V Tolerant Open-drain)................................................................73
8.1.25 FLUSH# (I - 1.5 V Tolerant)...................................................................................73
8.1.26 HIT# (I/O - AGTL), HITM# (I/O - AGTL).................................................................73
8.1.27 IERR# (O - 1.5 V Tolerant Open-drain) .................................................................74
8.1.28 IGNNE# (I - 1.5 V Tolerant) ...................................................................................74
8.1.29 INIT# (I - 1.5 V Tolerant)........................................................................................74
8.1.30 INTR (I - 1.5 V Tolerant) ........................................................................................74
4
Datasheet
Contents
8.1.31 LINT[1:0] (I - 1.5 V Tolerant)..................................................................................74
8.1.32 LOCK# (I/O - AGTL) ..............................................................................................75
8.1.33 NCTRL (I - Analog) ................................................................................................75
8.1.34 NMI (I - 1.5 V Tolerant) ..........................................................................................75
8.1.35 PICCLK (I – 2.0 V Tolerant)...................................................................................75
8.1.36 PICD[1:0] (I/O - 1.5 V Tolerant Open-drain) ..........................................................75
8.1.37 PLL1, PLL2 (Analog) .............................................................................................75
8.1.38 PRDY# (O - AGTL) ................................................................................................76
8.1.39 PREQ# (I - 1.5 V Tolerant) ....................................................................................76
8.1.40 PWRGOOD (I – 1.8 V Tolerant).............................................................................76
8.1.41 REQ[4:0]# (I/O - AGTL) .........................................................................................76
8.1.42 RESET# (I - AGTL)................................................................................................76
8.1.43 RP# (I/O - AGTL)...................................................................................................77
8.1.44 RS[2:0]# (I/O - AGTL) ............................................................................................77
8.1.45 RSP# (I - AGTL) ....................................................................................................77
8.1.46 RTTIMPEDP (I-Analog) .........................................................................................77
8.1.47 SMI# (I - 1.5 V Tolerant) ........................................................................................77
8.1.48 STPCLK# (I - 1.5 V Tolerant).................................................................................77
8.1.49 TCK (I - 1.5 V Tolerant) .........................................................................................78
8.1.50 TDI (I - 1.5 V Tolerant)...........................................................................................78
8.1.51 TDO (O - 1.5 V Tolerant Open-drain) ....................................................................78
8.1.52 TESTHI[2:1] (I - 1.25 V Tolerant)...........................................................................78
8.1.53 TESTLO[2:1] (I - 1.5 V Tolerant)............................................................................78
8.1.54 THERMDA, THERMDC (Analog)...........................................................................78
8.1.55 TMS (I - 1.5 V Tolerant) .........................................................................................78
8.1.56 TRDY# (I/O - AGTL) ..............................................................................................78
8.1.57 TRST# (I - 1.5 V Tolerant) .....................................................................................78
8.1.58 VID[4:0] (O – Open-drain)......................................................................................79
8.1.59 V
(Analog) ........................................................................................................79
REF
8.1.60 VTTPWRGD (I – 1.25 V) .......................................................................................79
Signal Summaries...............................................................................................................79
8.2
Figures
1
2
3
4
5
6
7
8
9
Clock Control States...................................................................................................................15
PLL RLC Filter ............................................................................................................................23
PLL Filter Specifications .............................................................................................................24
VTTPWRGD System-Level Connections ...................................................................................27
Noise Estimation.........................................................................................................................28
BCLK (Single Ended)/PICCLK/TCK Generic Clock Timing Waveform.......................................39
Differential BCLK/BCLK# Waveform (Common Mode) ..............................................................39
BCLK/BCLK# Waveform (Differential Mode)..............................................................................40
Valid Delay Timings....................................................................................................................40
10 Setup and Hold Timings .............................................................................................................40
11 Cold/Warm Reset and Configuration Timings ............................................................................41
12 Power-on Sequence and Reset Timings ....................................................................................42
13 Power Down Sequencing and Timings (V
Leading)...............................................................43
CC
14 Power Down Sequencing and Timings (VCCT Leading)............................................................44
15 Test Timings (Boundary Scan) ...................................................................................................45
Datasheet
5
Contents
16 Test Reset Timings.....................................................................................................................45
17 Quick Start/Deep Sleep Timing (BCLK Stopping Method) .........................................................46
18 Quick Start/Deep Sleep Timing (DPSLP# Assertion Method) ....................................................46
19 BCLK (Single Ended)/PICCLK Generic Clock Waveform ..........................................................48
20 Maximum Acceptable Overshoot/Undershoot Waveform...........................................................49
21 VTTPWRGD Noise Specification ...............................................................................................52
22 Micro FC-BGA Package – Top and Bottom Isometric Views .....................................................54
23 Micro FC-BGA Package – Top and Side Views .........................................................................54
24 Micro FC-BGA Package – Bottom View .....................................................................................55
25 Ball Map – Top View...................................................................................................................56
Tables
1
New and Revised Ultra-Low Voltage Intel® Celeron® Processor (0.13 µ) Signals.....................14
2
3
4
5
6
7
8
9
Clock State Characteristics ........................................................................................................16
Ultra-Low Voltage Intel® Celeron® Processor CPUID ................................................................17
Ultra-Low Voltage Intel® Celeron® Processor CPUID Cache and TLB Descriptors...................17
System Signal Groups................................................................................................................19
Recommended Resistors for Ultra-Low Voltage Intel® Celeron® Processor Signals .................20
PLL Filter Inductor Recommendations .......................................................................................25
PLL Filter Capacitor Recommendations.....................................................................................25
PLL Filter Resistor Recommendations .......................................................................................25
10 Ultra-Low Voltage Intel® Celeron® Processor VID Values .........................................................26
11 VTTPWRGD Noise Specification ...............................................................................................27
12 VTTPWRGD Transition Time Specification................................................................................27
13 Ultra-Low Voltage Intel® Celeron® Processor Absolute Maximum Ratings................................29
14 Power Specifications for the Ultra-Low Voltage Intel® Celeron® Processor...............................30
15 VCC Tolerances for the Ultra-Low Voltage Intel® Celeron® Processor: VID = 1.1 V .................31
16 VCC Tolerances for the Ultra-Low Voltage Intel® Celeron® Processor in the
Deep Sleep State: VID = 1.1 V...................................................................................................31
17 VCC Tolerances for the Ultra-Low Voltage Intel® Celeron® Processor: VID = 0.95 V ...............32
18 VCC Tolerances for the Ultra-Low Voltage Intel® Celeron® Processor in the
Deep Sleep State: VID = 0.95 V.................................................................................................32
19 AGTL Signal Group DC Specifications.......................................................................................32
20 AGTL Bus DC Specifications......................................................................................................33
21 CLKREF, APIC, TAP, CMOS, and Open-drain Signal Group DC Specifications.......................33
22 System Bus Clock AC Specifications .........................................................................................35
23 Valid Ultra-Low Voltage Intel® Celeron® Processor Frequencies...............................................35
24 AGTL Signal Groups AC Specifications .....................................................................................35
25 CMOS and Open-drain Signal Groups AC Specifications..........................................................36
26 Reset Configuration AC Specifications and Power On/Power Down Timings............................36
27 APIC Bus Signal AC Specifications............................................................................................37
28 TAP Signal AC Specifications ....................................................................................................38
29 Quick Start/Deep Sleep AC Specifications.................................................................................39
30 BCLK (Differential) DC Specifications and AC Signal Quality Specifications.............................47
31 BCLK (Single Ended) DC Specifications and AC Signal Quality Specifications.........................47
32 PICCLK DC Specifications and AC Signal Quality Specifications..............................................48
33 100-MHz AGTL Signal Group Overshoot/Undershoot Tolerance
at the Processor Core.................................................................................................................49
6
Datasheet
Contents
34 Non-AGTL Signal Group Overshoot/Undershoot Tolerance at the Processor Core ..................50
35 VTTPWRGD Noise Parameter Specification..............................................................................51
36 VTTPWRGD Transition Parameter Recommendation ...............................................................51
37 Micro FC-BGA Package Mechanical Specifications...................................................................53
38 Signal Listing in Order by Ball Number.......................................................................................57
39 Signal Listing in Order by Signal Name......................................................................................60
40 Voltage and No-Connect Ball Locations.....................................................................................63
41 Power Specifications for the Ultra-Low Voltage Intel® Celeron® Processor...............................65
42 Thermal Diode Interface .............................................................................................................66
43 Thermal Diode Specifications.....................................................................................................66
44 BSEL[1:0] Encoding....................................................................................................................72
45 Input Signals...............................................................................................................................79
46 Output Signals ............................................................................................................................80
47 Input/Output Signals (Single Driver) ...........................................................................................80
48 Input/Output Signals (Multiple Driver).........................................................................................81
Datasheet
7
Contents
Revision History
Date
Revision
Description
Removed Figure 6, “Illustration of VCC Static and Transient
Tolerances.
May 2003
002
001
Removed Figure 7, “Illustration of Deep Sleep VCC Static and
Transient Tolerances.
October 2002
Initial document release
8
Datasheet
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
1.0
Introduction
Using Intel’s advanced 0.13-micron process technology with copper interconnect, the Ultra-Low
Voltage Intel® Celeron® processor offers high-performance and low power consumption. The
Ultra-Low Voltage Intel Celeron processor (0.13µ) in the Micro FC-BGA packages (hereafter
referred to as the ULV Intel Celeron processor) is based on the same core as existing Intel®
Pentium® III processors. Key performance features include Internet Streaming SIMD instructions,
Advanced Transfer Cache architecture, and a processor system bus speed of 100 MHz. These
features are offered in a Micro FC-BGA packages for surface mount small form factor boards.
The 256-Kbyte integrated L2 cache based on the Advanced Transfer Cache architecture runs at full
speed and is designed to help improve performance. It complements the system bus by providing
critical data faster and reducing total system power consumption. The processor also features Data
Prefetch Logic that speculatively fetches data to the L2 cache, resulting in improved performance.
The Intel Celeron processor’s 64-bit wide Assisted Gunning Transceiver Logic (AGTL) system bus
provides a glueless, point-to-point interface for a memory controller hub.
This document covers the electrical, mechanical, and thermal specifications for the Ultra-Low
Voltage Intel Celeron processor at 650 MHz at 1.10 V and 400 MHz at 0.95 V.
1.1
Overview
• Performance features
— Supports the Intel Architecture with Dynamic Execution
— Supports Intel MMX™ technology
— Supports Streaming SIMD Extensions for enhanced video, sound, and 3D performance
— Integrated Intel Floating Point Unit compatible with the IEEE 754 standard
— Data Prefetch Logic
• On-die primary (L1) instruction and data caches
— 4-way set associative, 32-byte line size, 1 line per sector
— 16-Kbyte instruction cache and 16-Kbyte write-back data cache
— Cacheable range controlled by processor programmable registers
• On-die second level (L2) cache
— 8-way set associative, 32-byte line size, 1 line per sector
— Operates at full core speed
— 256-Kbyte ECC protected cache data array
• AGTL system bus interface
— 64-bit data bus, 100-MHz
— Uniprocessor, two loads only (processor and chipset)
— Integrated termination
• Processor clock control
Datasheet
9
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
— Quick Start for low power, low exit latency clock “throttling”
— Deep Sleep mode for lower power dissipation
• Thermal diode for measuring processor temperature
1.2
1.3
State of the Data
All information in this document is the best available information at the time of publication.
Revisions of this document will be provided on an as-required basis.
Terminology
Term
Definition
#
A “#” symbol following a signal name indicates that the signal is active low. This means that when
the signal is asserted (based on the name of the signal) it is in an electrical low state. Otherwise,
signals are driven in an electrical high state when they are asserted. In state machine diagrams, a
signal name in a condition indicates the condition of that signal being asserted
!
Indicates the condition of that signal not being asserted. For example, the condition “!STPCLK# and
HS” is equivalent to “the active low signal STPCLK# is unasserted (i.e., it is at 1.5V) and the HS
condition is true.”
L
Electrical low signal levels
Electrical high signal levels
H
0
Logical low. For example, BD[3:0] = “1010” = “HLHL” refers to a hexadecimal “A,” and D[3:0]# =
“1010” = “LHLH” also refers to a hexadecimal “A.”
1
Logical high. For example, BD[3:0] = “1010” = “HLHL” refers to a hexadecimal “A,” and D[3:0]# =
“1010” = “LHLH” also refers to a hexadecimal “A.”
ULV
TBD
X
Ultra-Low Voltage
Specifications that are yet to be determined and will be updated in future revisions of the document.
Don’t care condition
1.4
References
• P6 Family of Processors Hardware Developer’s Manual (244001)
• Intel® Architecture Optimization Reference Manual (245127)
• Intel® Architecture Software Developer’s Manual
— Volume I: Basic Architecture (245470)
— Volume II: Instruction Set Reference (245471)
— Volume III: System Programming Guide (245472)
• CK-408 (CK-Titan) Clock Synthesizer/Driver Specification (Contact your Intel Field Sales
Representative)
• Mobile Intel® Pentium® III Processor-M I/O Buffer Models, IBIS Format (Contact your Intel
Field Sales Representative)
10
Datasheet
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
• Intel® Mobile Voltage Positioning -II (IMVP-II) Design Guide (Contact your Intel Field Sales
Representative)
• Mobile Intel® Pentium® III Processor-M /440MX Platform Design Guide (Contact your Intel
Field Sales Representative)
• Intel Processor Identification and the CPUID Instruction Application Note AP-485 (241618)
Datasheet
11
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
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12
Datasheet
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
2.0
Ultra-Low Voltage Intel® Celeron® Processor
Features
®
®
2.1
New Features in the Ultra-Low Voltage Intel Celeron
Processor
2.1.1
100-MHz PSB With AGTL Signaling
The ULV Intel® Celeron® processor uses Assisted GTL (AGTL) signaling on the Processor System
Bus (PSB) interface. The main difference between AGTL and GTL+ used on previous Intel
processors is V
= 1.25 V for AGTL versus 1.5 V for GTL+. The lower voltage swing enables
CCT
high performance at lower power.
2.1.2
2.1.3
256-K On-die Integrated L2 Cache
The 256-K on die integrated L2 cache on the ULV Intel Celeron processor is double the L2 cache
size of previous Intel Celeron processors (0.18 µ). The L2 cache runs at the processor core speed
and the increased cache size provides superior processing power.
Data Prefetch Logic
The ULV Intel Celeron processor features Data Prefetch Logic that speculatively fetches data to the
L2 cache before an L1 cache request occurs. This reduces transactions between the cache and
system memory reducing or eliminating bus cycle penalties, resulting in improved performance.
The processor also includes extensions to memory order and reorder buffers that boost
performance.
2.1.4
2.1.5
Differential Clocking
Differential clocking requires the use of two complementary clocks: BCLK and BCLK#. Benefits
of differential clocking include easier scaling to lower voltages, reduced EMI, and less jitter. All
references to BCLK in this document apply to BCLK# also even if not explicitly stated. The ULV
Intel Celeron processor will also support Single Ended Clocking. The processor will configure
itself for Differential or Single Ended Clocking based on the waveforms detected on the BCLK and
BCLK#/CLKREF signal lines.
Signal Differences Between the Mobile Intel® Celeron®
Processor in BGA2 and Micro-PGA2 Packages and
the Ultra-Low Voltage Intel® Celeron® Processor in Micro FC-BGA
Packages
A list of new and changed signals is shown in Table 1.
Datasheet
13
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
Table 1. New and Revised Ultra-Low Voltage Intel® Celeron® Processor (0.13 µ) Signals
Signals
Function
BCLK,
BCLK#
Differential host clock signals.
CLKREF
BSEL[1:0]
DPSLP#
NCTRL
Host Clock reference signal in Single Ended Clocking mode.
Signals are output only instead of I/O. Refer to Section 3.2.3 for details.
Deep Sleep pin (replaces SLP# pin on the mobile Celeron processor (0.18 µ))
AGTL output buffer pull down impedance control.
Voltage Identification (different implementation from mobile Celeron processor (0.18 µ)). Refer
to Section 3.2.4 for details.
VID[4:0]
Power Good signal for VCCT, which indicates that, the VID signals are stable. Refer to Figure 4
for VTTPWRGD system level connections.
VTTPWRGD
2.2
Power Management
2.2.1
Clock Control Architecture
The ULV Intel® Celeron® processor clock control architecture (Figure 1) has been optimized for
leading edge computer designs. The clock control architecture consists of six different clock states:
Normal, Auto Halt, Quick Start, HALT/Grant Snoop and Deep Sleep states. The Auto Halt state
provides a low-power clock state that may be controlled through the software execution of the HLT
instruction. The Quick Start state provides a very low power and low exit latency clock state that
may be used for hardware controlled “idle” computer states. The Deep Sleep state provides
extremely low-power states that may be used for “Power-On-Suspend” computer states, which is
an alternative to shutting off the processor’s power. The exit latency of the Deep Sleep state is 30
ms in the Intel Celeron processor. Performing state transitions not shown in Figure 1 is neither
recommended nor supported. Figure 2 provides the clock state characteristics, which are described
in detail in the following sections.
2.2.2
2.2.3
Normal State
The Normal state of the processor is the normal operating mode where the processor’s core clock is
running and the processor is actively executing instructions.
Auto Halt State
This is a low-power mode entered by the processor through the execution of the HLT instruction. A
transition to the Normal state is made by a halt break event (one of the following signals going
active: NMI, INTR, BINIT#, INIT#, RESET#, FLUSH#, or SMI#).
Asserting the STPCLK# signal while in the Auto Halt state will cause the processor to transition to
the Quick Start state. Deasserting STPCLK# will cause the processor to return to the Auto Halt
state without issuing a new Halt bus cycle.
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Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
The SMI# interrupt is recognized in the Auto Halt state. The return from the System Management
Interrupt (SMI) handler may be to either the Normal state or the Auto Halt state. See the Intel®
Architecture Software Developer’s Manual, Volume III: System Programmer’s Guide for more
information. No Halt bus cycle is issued when returning to the Auto Halt state from the System
Management Mode (SMM).
The FLUSH# signal is serviced in the Auto Halt state. After the on-chip and off-chip caches have
been flushed, the processor will return to the Auto Halt state without issuing a Halt bus cycle.
Transitions in the A20M# and PREQ# signals are recognized while in the Auto Halt state.
Figure 1. Clock Control States
STPCLK#1
BCLK stopped
or DPSLP#
Normal
HS=false
Quick Start
Deep Sleep 2
(!STPCLK# and !HS)
or RESET#
BCLK on
and !DPSLP#
STPCLK#1
halt
break
snoop
serviced
HLT
snoop
occurs
!STPCLK#
and HS
instruction1
snoop
occurs
Auto Halt
HS=true
HALT/Grant
Snoop
snoop
V0001-022
serviced
NOTES:
1. State transition does not occur until the Stop Grant or Auto Halt acknowledge bus cycle completes
Halt break - A20M#, BINIT#, FLUSH#, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt
HLT - HLT instruction executed
HS - Processor Halt State
2. Restrictions apply to the use of both methods of entering Deep Sleep. See Deep Sleep state description for
details.
2.2.4
Quick Start State
The processor is required to be configured for the Quick Start state by strapping the A15# signal
low. In the Quick Start state the processor is only capable of acting on snoop transactions generated
by the system bus priority device. Because of its snooping behavior, Quick Start may only be used
in a uniprocessor (UP) configuration.
A transition to the Deep Sleep state may be made by stopping the clock input to the processor or
asserting the DPSLP# signal. A transition back to the Normal state (from the Quick Start state) is
made only if the STPCLK# signal is deasserted.
While in this state the processor is limited in its ability to respond to input. It is incapable of
latching any interrupts, servicing snoop transactions from symmetric bus masters, or responding to
FLUSH# or BINIT# assertions. While the processor is in the Quick Start state, it will not respond
Datasheet
15
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
properly to any input signal other than STPCLK#, RESET#, or BPRI#. If any other input signal
changes, then the behavior of the processor will be unpredictable. No serial interrupt messages may
begin or be in progress while the processor is in the Quick Start state.
RESET# assertion will cause the processor to immediately initialize itself, but the processor will
stay in the Quick Start state after initialization until STPCLK# is deasserted.
2.2.5
2.2.6
HALT/Grant Snoop State
The processor will respond to snoop transactions on the system bus while in the Auto Halt or Quick
Start state. When a snoop transaction is presented on the system bus the processor will enter the
HALT/Grant Snoop state. The processor will remain in this state until the snoop has been serviced
and the system bus is quiet. After the snoop has been serviced, the processor will return to its
previous state. If the HALT/Grant Snoop state is entered from the Quick Start state, then the input
signal restrictions of the Quick Start state still apply in the HALT/Grant Snoop state, except for
those signal transitions that are required to perform the snoop.
Deep Sleep State
The Deep Sleep state is a very low power state that the processor may enter while maintaining its
context. The Deep Sleep state is entered by stopping the BCLK and BCLK# inputs to the processor
or by asserting the DPSLP# signal, while it is in the Quick Start state. Note that either one of the
methods may be used to enter Deep Sleep but not both at the same time. When BCLK and BCLK#
are stopped, they must obey the DC levels specified in Table 33.
The processor will return to the Quick Start state from the Deep Sleep state when the BCLK and
BCLK# inputs are restarted or the DPSLP# signal is deasserted. Due to the PLL lock latency, there
is a delay of up to 30 µs after the clocks have started before this state transition happens. PICCLK
may be removed in the Deep Sleep state. PICCLK should be designed to turn on when BCLK and
BCLK# turn on or DPSLP# is deasserted when transitioning out of the Deep Sleep state.
Table 2. Clock State Characteristics
Clock State
Normal
Exit Latency
Snooping?
System Uses
Normal program execution
N/A
Yes
Yes
Auto Halt
10 µs
S/W controlled entry idle mode
Through snoop, to HALT/
Grant Snoop state:
immediate
Quick Start
Yes
H/W controlled entry/exit mobile throttling
Through STPCLK#, to
Normal state: 10 µs
HALT/Grant
Snoop
A few bus clocks after
snoop completion
Yes
No
Supports snooping in the low power states
H/W controlled entry/exit mobile powered-on
suspend support
Deep Sleep 30 µs
2.2.7
Operating System Implications of Low-power States
The time-stamp counter and the performance monitor counters are not ensured to count in the
Quick Start state. The local APIC timer and performance monitor counter interrupts should be
disabled before entering the Deep Sleep state or the resulting behavior will be unpredictable.
16
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Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
2.3
AGTL Signals
The ULV Intel®Celeron® processor system bus signals use a variation of the low-voltage swing
GTL signaling technology. The AGTL system bus depends on incident wave switching and uses
flight time for timing calculations of the AGTL signals, as opposed to capacitive derating. Intel
recommends analog signal simulation of the system bus including trace lengths. Contact your field
sales representative to receive the IBIS models for the Mobile Intel Celeron processor for
simulation.
The AGTL system bus of the ULV Intel Celeron processor is designed to support high-speed data
transfers with multiple loads on a long bus that behaves like a transmission line. However, in UP
embedded systems the system bus only has two loads (the processor and the chipset) and the bus
traces are short. It is possible to change the layout and termination of the system bus to take
advantage of this environment using the same AGTL I/O buffers. This termination is provided on
the processor core (except for the RESET# signal).
2.4
Ultra-Low Voltage Intel® Celeron® Processor CPUID
When the CPUID version information is loaded with EAX=01H, the EAX and EBX registers
contain the values shown in Table 3. After a power-on RESET, the EDX register contains the
processor version information (type, family, model, stepping). Table 4 shows the CPUID Cache
and TLB descriptor values after the L2 cache is initialized. See the Intel Processor Identification
and the CPUID Instruction Application Note AP-485 for further information.
Table 3. Ultra-Low Voltage Intel® Celeron® Processor CPUID
EAX[31:0]
EBX[7:0]
Model
[7:4]
Reserved [31:14]
Type [13:12]
Family [11:8]
Stepping [3:0]
Brand ID
X
0
6
B
X
01
Table 4. Ultra-Low Voltage Intel® Celeron® Processor CPUID Cache and TLB Descriptors
Cache and TLB Descriptors
01H, 02H, 03H, 04H, 08H, 0CH, 83H
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Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
3.0
Electrical Specifications
3.1
Processor System Signals
Table 5 lists the processor system signals by type. All AGTL signals are synchronous with the
BCLK and BCLK# signals. All TAP signals are synchronous with the TCK signal except TRST#.
All CMOS input signals may be applied asynchronously.
Table 5. System Signal Groups
Group Name
Signals
AGTL Input
BPRI#, DEFER#, RESET#, RSP#
PRDY#
AGTL Output
A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#,
BPM[1:0]#, BREQ0#, D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, HIT#, HITM#,
LOCK#, REQ[4:0]#, RP#, RS[2:0]#, TRDY#
AGTL I/O
A20M#, DPSLP#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI,
PREQ#, SMI#, STPCLK#
1.5 V CMOS Input
1.8 V CMOS Input
1.5 V Open Drain Output
3.3 V Open Drain Output
1.25 V input
PWRGOOD
FERR#, IERR#
BSEL[1:0], VID[4:0]
VTTPWRGD
Clock
BCLK, BCLK# (Differential Mode)
BCLK (Single Ended Mode)
PICCLK
2.5 V Clock Input
APIC Clock
APIC I/O
PICD[1:0]
Thermal Diode
TAP Input
THERMDC, THERMDA
TCK, TDI, TMS, TRST#
TDO
TAP Output
CLKREF, CMOSREF, EDGECTRLP, NC, NCTRL, PLL1, PLL2, RTTIMPEDP,
VCC, VCCT, VREF, VSS,
Power/Other
NOTES:
1. VCC is the power supply for the core logic.
2. PLL1 and PLL2 are power/ground for the PLL analog section. See Section 3.2.2 for details.
3. VCCT is the power supply for the system bus buffers.
4. VREF is the voltage reference for the AGTL input buffers.
5. VSS is system ground.
The APIC data and TAP outputs are Open-drain and should be pulled up to 1.5 V using resistors
with the values shown in Table 6. If Open-drain drivers are used for input signals, then they should
also be pulled up to the appropriate voltage using resistors with the values shown in Table 6.
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Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
Table 6. Recommended Resistors for Ultra-Low Voltage Intel® Celeron® Processor Signals
Recommended
Resistor Value (Ω)
Ultra-Low Voltage Intel® Celeron® Processor Signal 1, 2
10 pull-down
14 pull-up
BREQ0#3
NCTRL
39 pull-up
TMS
39 pull-down
56.2 pull-up
56.2 pull-down
110 pull-down
150 pull-up
TCK
PRDY#, RESET#4
RTTIMPEDP
EDGECTRLP
PICD[1:0], TDO
PREQ#, TDI
200-300 pull-up
500 pull-down
1K pull-up
TRST#
BSEL[1:0], TESTHI, VID[4:0], VTTPWRGD
TESTLO
1K pull-down
1.5k pull-up
3K pull-up
FERR#, IERR#, PWRGOOD
FLUSH#
Additional Pull-up/Pull-down Resistor Recommendations6
270 pull-up
680 pull-up
1.5k pull-up
SMI#
STPCLK#
A20M#, DPSLP#, INIT#, IGNNE#, LINT0/INTR, LINT1/NMI
NOTES:
1. The recommendations above are only for signals that are being used. These recommendations are
maximum values only; stronger pull-ups may be used. Pull-ups for the signals driven by the chipset should
not violate the chipset specification. Refer to Section 3.1.4 for the required pull-up or pull-down resistors for
signals that are not being used.
2. Open-drain signals must never violate the undershoot specification in Section 4.3. Use stronger pull-ups if
there is too much undershoot.
3. A pull-down on BREQ0# is an alternative to having the central agent to drive BREQ0# low at reset.
4. A 56.2 Ω 1% terminating resistor connected to VCCT is required.
5. The following signals are actively driven high by the ICH3-M component and do not need external pull up
resistors on ICH3-M based platforms: A20M#, DPSLP#, INIT#, IGNNE#, LINT0/INTR, LINT1/NMI, SMI#,
STPCLK#.
6. These pull up recommendations apply to systems on which these signals are not actively pulled high such
as those utilizing the 82443MX chipset.
3.1.1
Power Sequencing Requirements
Unlike the Mobile Intel® Celeron® processor (0.18 µ), the ULV Intel Celeron processor (0.13 µ)
does have specific power sequencing requirements. The power on sequencing and timings are
shown in Figure 12 and Table 26. Power down timing requirements are shown in Figure 13, Figure
14, and Table 26. The V power plane must not rise too fast. At least 200 µs (T ) must pass from
CC
R
the time that V is at 10% of its nominal value until the time that V is at 90% of its nominal
CC
CC
value. For more details, refer to the Intel® Mobile Voltage Positioning -II (IMVP-II) Design Guide
(contact your Field Sales Representative).
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Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
3.1.2
Test Access Port (TAP) Connection
The TAP interface is an implementation of the IEEE 1149.1 (“JTAG”) standard. Due to the voltage
levels supported by the TAP interface, Intel recommends that the ULV Intel® Celeron® processor
and the other 1.5-V JTAG specification compliant devices be last in the JTAG chain after any
devices with 3.3-V or 5.0-V JTAG interfaces within the system. A translation buffer should be used
to reduce the TDO output voltage of the last 3.3/5.0 V device down to the 1.5-V range that the ULV
Intel Celeron processor may tolerate. Multiple copies of TMS and TRST# must be provided, one
for each voltage level.
A Debug Port and connector may be placed at the start and end of the JTAG chain containing the
processor, with TDI to the first component coming from the Debug Port and TDO from the last
component going to the Debug Port. There are no requirements for placing the ULV Intel Celeron
processor in the JTAG chain, except for those that are dictated by voltage requirements of the TAP
signals.
3.1.3
3.1.4
Catastrophic Thermal Protection
The ULV Intel Celeron processor does not support catastrophic thermal protection or the
THERMTRIP# signal. An external thermal sensor must be used to protect the processor and the
system against excessive temperatures. If the external thermal sensor detects a processor junction
temperature of 101° C (maximum), both the V and V
supplies to the processor must be
CC
CCT
reduced to at least 50% of the nominal values within 500 ms and are recommended to be turned off
completely within 1 second to prevent damage to the processor. processor temperature must be
monitored in all states including low power states.
Unused Signals
All signals named NC must be unconnected. Unused AGTL inputs, outputs, and bidirectional
signals should be unconnected. Unused CMOS active low inputs should be connected to 1.5 V and
unused active high inputs should be connected to V . Unused Open-drain outputs should be
SS
unconnected. When tying any signal to power or ground, a resistor will allow for system testability.
For unused signals, Intel suggests that 1.5-kΩ resistors are used for pull-ups and 1.0-kΩ resistors
are used for pull-downs.
PICCLK must be driven with a clock that meets specification and the PICD[1:0] signals must be
pulled up separately to 1.5 V with 150-Ω resistors, even if the local APIC is not used.
If the TAP signals are not used then the inputs should be pulled to ground with 1-kΩ resistors and
TDO should be left unconnected.
3.1.5
Signal State in Low-power States
System Bus Signals
3.1.5.1
All of the system bus signals have AGTL input, output, or input/output drivers. Except when
servicing snoops, the system bus signals are tri-stated and pulled up by the termination resistors.
Snoops are not permitted in the Deep Sleep state.
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Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
3.1.5.2
CMOS and Open-drain Signals
The CMOS input signals are allowed to be in either the logic high or low state when the processor
is in a low-power state. In the Auto Halt state these signals are allowed to toggle. These input
buffers have no internal pull-up or pull-down resistors and system logic may use CMOS or
Open-drain drivers to drive them.
The Open-drain output signals have open drain drivers and external pull-up resistors are required.
One of the two output signals (IERR#) is a catastrophic error indicator and is tri-stated (and
pulled-up) when the processor is functioning normally. The FERR# output may be either tri-stated
or driven to V when the processor is in a low-power state depending on the condition of the
SS
floating-point unit. Since this signal is a DC current path when it is driven to V , Intel
SS
recommends that the software clears or masks any floating-point error condition before putting the
processor into the Deep Sleep state.
3.1.5.3
Other Signals
The system bus clocks (BCLK, BCLK#) must be driven in all of the low-power states except the
Deep Sleep state. The APIC clock (PICCLK) must be driven whenever BCLK and BCLK# are
driven. Otherwise, it is permitted to turn off PICCLK by holding it at V . BCLK and BCLK#
SS
should be obey the DC levels in Table 33.
In the Auto Halt state, the APIC bus data signals (PICD[1:0]) may toggle due to APIC bus
messages. These signals are required to be tri-stated and pulled-up when the processor is in the
Quick Start or Deep Sleep states.
3.2
Power Supply Requirements
3.2.1
Decoupling Guidelines
The ULV Intel® Celeron® processor in Micro FC-BGA package has eight 0805IDC, 0.68-µF
surface mount decoupling capacitors. Six capacitors are on the V supply and two capacitors are
CC
on V
In addition to the package capacitors, sufficient board level capacitors are also necessary
CCT.
for power supply decoupling. The guidelines are as follows:
• High and Mid Frequency V decoupling – Place twenty-four 0.22-µF 0603 capacitors
CC
directly under the package on the solder side of the motherboard using at least two vias per
capacitor node. Ten 10-µF X7 6.3V 1206-size ceramic capacitors should be placed around the
package periphery near the balls. Trace lengths to the vias should be designed to minimize
inductance. Avoid bending traces to minimize ESL.
• High and Mid Frequency V
decoupling – Place ten 1-µF X7R 0603 ceramic capacitors
close to the package. Via and trace guidelines are the same as above.
CCT
• Bulk V decoupling – Minimum of 1200-µF capacitance with Equivalent Series Resistance
CC
(ESR) less than or equal to 3.5 mΩ.
• Bulk V
decoupling – Platform dependent but recommendation is minimum of 660-µF with
ESR less than or equal to 7 mΩ.
CCT
Refer to the appropriate platform design guidelines for bulk decoupling recommendations.
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Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
3.2.2
Voltage Planes
All V and V pins/balls must be connected to the appropriate voltage plane. All V and
CCT
CC
SS
V
pins/balls must be connected to the appropriate traces on the system electronics. In addition
REF
to the main V , V
, and V power supply signals, PLL1 and PLL2 provide analog decoupling
CC
CCT
SS
to the PLL section. PLL1 and PLL2 should be connected according to Figure 2. Do not connect
PLL2 directly to V . Section 3.2.3 contains the RLC filter specification.
SS
Figure 2. PLL RLC Filter
L1
R1
PLL1
PLL2
VCCT
C1
V0027-01
3.2.3
PLL RLC Filter Specification
Introduction
3.2.3.1
All Intel® Celeron® processors have internal PLL clock generators, which are analog in nature and
require quiet power supplies for minimum jitter. Jitter is detrimental to a system; it degrades
external I/O timings as well as internal core timings (i.e. maximum frequency). The PLL RLC filter
specifications for the ULV Intel Celeron processor are the same as those for the mobile Intel
Pentium® III processor-M, and the Mobile Intel Celeron processor. The general desired topology is
shown in Figure 2. Excluded from the external circuitry are parasitics associated with each
component.
3.2.3.2
Filter Specification
The function of the filter is two fold. It protects the PLL from external noise through low-pass
attenuation. It also protects the PLL from internal noise through high-pass filtering. In general, the
low-pass description forms an adequate description for the filter.
The AC low-pass specification, with input at V
follows:
and output measured across the capacitor, is as
CCT
• < 0.2-dB gain in pass band
• < 0.5-dB attenuation in pass band < 1 Hz (see DC drop in next set of requirements)
• 34-dB attenuation from 1 MHz to 66 MHz
• 28-dB attenuation from 66 MHz to core frequency
• The filter specification (AC) is graphically shown in Figure 3.
Other requirements:
• Use a shielded type inductor to minimize magnetic pickup
Datasheet
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Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
• The filter should support a DC current of at least 30 mA
• The DC voltage drop from V
to PLL1 should be less than 60 mV, which in practice implies
series resistance of less than 2 Ω. This also means that the pass band (from DC to 1 Hz)
CCT
attenuation below 0.43 dB for V = 1.25 V.
CCT
3.2.3.3
Recommendation for Embedded Systems
Figure 3. PLL Filter Specifications
0.2 dB
0 dB
x dB
Forbidden
zone
-28 dB
-34 dB
Forbidden
zone
DC
Passband
x = 20.log[(Vcct-60 mV)/ Vcct]
1 Hz
fpeak
1 MHz
66 MHz
fcore
High Frequency
Band
NOTES:
1. Diagram is not to scale
2. No specification for frequencies beyond fcore.
3. Fpeak, if it exists, should be less than 0.05 MHz.
The following LC components are recommended. The tables will be updated as other suitable
components and specifications are identified.
24
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Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
Table 7. PLL Filter Inductor Recommendations
Min Damping R
Needed
Inductor
Part Number
Value
Tol
SRF
Rated I
DCR
L1
L2
TDK MLF2012A4R7KT
4.7 µH
4.7 µH
10%
10%
35 MHz
47 MHz
30 mA
30 mA
0.56 Ω (1Ω max)
0.7 Ω (+/-50%)
0 Ω
0 Ω
Murata*
LQG21N4R7K10
Murata*
LQG21C4R7N00
L3
4.7 µH
30%
35 MHz
30 mA
0.3 Ω max
0.2 Ω (assumed)
NOTE: Minimum damping resistance is calculated from 0.35 Ω – DCRmin. From vendor provided data, L1 and
L2 DCRmin is 0.4 Ω and 0.5 Ω respectively, qualifying them for zero required trace resistance. DCRmin
for L3 is not known and is assumed to be 0.15 Ω. Products with equivalent specifications may also be
used.
Table 8. PLL Filter Capacitor Recommendations
Capacitor
Part Number
Value
Tolerance
ESL
ESR
C1
C2
Kemet* T495D336M016AS
AVX TPSD336M020S0200
33 µF
33 µF
20%
20%
2.5 nH
0.225 Ω
0.2 Ω
unknown
Table 9. PLL Filter Resistor Recommendations
Resistor
Part Number
Value
1Ω
Tolerance
10%
Power
R1
Various
1/16 W
To satisfy damping requirements, total series resistance in the filter (from VCCT to the top plate of
the capacitor) must be at least 0.35 Ω. This resistor may be in the form of a discrete component, or
routing, or both. For example, if the picked inductor has minimum DCR of 0.25 Ω, then a routing
resistance of at least 0.10 Ω is required. Be careful not to exceed the maximum resistance rule
(2 Ω). For example, if using discrete R1, the maximum DCR of the L should be less than
2.0 - 1.1 = 0.9 Ω, which precludes using L2 and possibly L1.
Other routing requirements include:
• The capacitor should be close to the PLL1 and PLL2 pins, with less than 0.1 Ω per route
(These routes do not count towards the minimum damping resistance requirement).
• The PLL2 route should be parallel and next to the PLL1 route (minimize loop area).
• The inductor should be close to the capacitor; any routing resistance should be inserted
between VCCT and the inductor.
• Any discrete resistor should be inserted between VCCT and the inductor.
3.2.3.4
Comments
• A magnetically shielded inductor protects the circuit from picking up external flux noise. This
should provide better timing margins than with an unshielded inductor.
• A discrete or routed resistor is required because the LC filter by nature has an under-damped
response, which may cause resonance at the LC pole. Noise amplification at this band,
although not in the PLL-sensitive spectrum, could cause a fatal headroom reduction for analog
circuitry. The resistor serves to dampen the response. Systems with tight space constraints
Datasheet
25
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
should consider a discrete resistor to provide the required damping resistance. Too large of a
damping resistance may cause a large IR drop, which means less analog headroom and lower
frequency.
• Ceramic capacitors have very high self-resonance frequencies, but they are not available in
large capacitance values. A high self-resonant frequency coupled with low ESL/ESR is crucial
for sufficient rejection in the PLL and high frequency band. The recommended tantalum
capacitors have acceptably low ESR and ESL.
• The capacitor must be close to the PLL1 and PLL2 pins; otherwise the value of the low ESR
tantalum capacitor is wasted. Note the distance constraint should be translated from the 0.1-Ω
requirement.
3.2.4
Voltage Identification
There are five voltage identification balls/pins on the ULV Intel® Celeron® processor. These
signals may be used to support automatic selection of VCC voltages. They are needed to cleanly
support voltage specification variations on current and future processors. VID[4:0] are defined in
Table 10. The VID[4:0] signals are open drain on the processor and need pull-up resistors to 3.3 V
on the motherboard. Refer to the appropriate VR guidelines provided by Intel for additional
information.
Table 10. Ultra-Low Voltage Intel® Celeron® Processor VID Values
VID[4:0]
VCC (V)
VID[4:0]
VCC (V)
VID[4:0]
VCC (V)
VID[4:0]
VCC (V)
00000
00001
00010
00011
00100
00101
00110
00111
1.750
1.700
1.650
1.600
1.550
1.500
1.450
1.400
01000
01001
01010
01011
01100
01101
01110
01111
1.350
1.300
1.250
1.200
1.150
1.100
1.050
1.000
10000
10001
10010
10011
10100
10101
10110
10111
0.975
0.950
0.925
0.900
0.875
0.850
0.825
0.800
11000
11001
11010
11011
11100
11101
11110
11111
0.775
0.750
0.725
0.700
0.675
0.650
0.625
0.600
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Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
Figure 4 shows the system level connections for the VTTPWRGD signal. Refer to the appropriate
VR and system level guidelines provided by Intel for more details.
Figure 4. VTTPWRGD System-Level Connections
Vcct
Vcct
Processor
Voltage Regulator
1k
Vcct
Vttpwrgd
(output)
Vttpwrgd
(input)
3.3V
100k
10k
Clock Generator
Vttpwrgd#
(input)
1.2V to 3.3V Level Shifter
3.2.5
VTTPWRGD Signal Quality Specification
The VTTPWRGD signal is an input to the processor used to determine that the VTT power is
stable and the VID and BSEL signals should be driven to their final state by the processor. To
ensure the processor correctly reads this signal, it must meet the following requirement while the
signal is in its transition region of 300 mV to 900 mV. Also, VTTPWRGD should only enter the
transition region once, after VTT is at nominal values, for the assertion of the signal.
Table 11. VTTPWRGD Noise Specification
Parameter
Specification
Amount of noise (glitch)
Less than 100 mV
In addition, the VTTPWRGD signal should have reasonable transition time through the transition
region. A sharp edge on the signal transition will minimize the chance of noise causing a glitch on
this signal. Intel recommends the following transition time for the VTTPWRGD signal.
Table 12. VTTPWRGD Transition Time Specification
Parameter
Recommendation
Transition time (300 mV to 900 mV)
Less than or equal to 100 µs
3.2.5.1
Transition Region
The transition region covered by this requirement is 300 mV to 900 mV. Once the VTTPWRGD
signal is in that voltage range, the processor is more sensitive to noise, which may be present on the
signal. The transition region when the signal first crosses the 300 mV voltage level and continues
until the last time it is below 900 mV.
Datasheet
27
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
3.2.5.2
3.2.5.3
Transition Time
The transition time is defined as the time the signal takes to move through the transition region. A
100-µs transition time will ensure that the processor receives a good transition edge.
Noise
The signal quality of the VTTPWRGD signal is critical to the correct operation of the processor.
Every effort should be made to ensure this signal is monotonic in the transition region. If noise or
glitches are present on this signal, it must be kept to less than 100 mV of a voltage drop from the
highest voltage level received to that point. This glitch must remain less than 100 mV until the
excursion ends by the voltage returning to the highest voltage previously received. Please see
Figure 5 for an example graph of this situation and requirements.
Figure 5. Noise Estimation
3.3
System Bus Clock and Processor Clocking
The BCLK and BCLK# clock inputs directly control the operating speed of the system bus
interface. All system bus timing parameters are specified with respect to the crossing point of the
rising edge of the BCLK input and falling edge of the BCLK# input. The ULV Intel® Celeron®
processor core frequency is a multiple of the BCLK frequency. The processor core frequency is
configured during manufacturing. The configured bus ratio is visible to software in the Power-on
configuration register. See Section 7.2 for details.
28
Datasheet
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
Multiplying the bus clock frequency is necessary to increase performance while allowing for easier
distribution of signals within the system. Clock multiplication within the processor is provided by
the internal Phase Lock Loop (PLL), which requires constant frequency BCLK and BCLK# inputs.
During Reset or on exit from the Deep Sleep state, the PLL requires some amount of time to
acquire the phase of BCLK and BCLK#. This time is called the PLL lock latency, which is
specified in Section 3.6, AC timing parameters T18 and T47.
3.4
Maximum Ratings
Table 13 contains the ULV Intel® Celeron® processor stress ratings. Functional operation at the
absolute maximum and minimum is neither implied nor ensured. The processor should not receive
a clock while subjected to these conditions. Functional operating conditions are provided in the AC
and DC tables. Extended exposure to the maximum ratings may affect device reliability. Although
the processor contains protective circuitry to resist damage from static electric discharge, you
should always take precautions to avoid high static voltages or electric fields.
Table 13. Ultra-Low Voltage Intel® Celeron® Processor Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
Notes
TStorage
Storage Temperature
–40
–0.5
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
—
85
1.75
1.75
1.75
1.75
2.0
° C
V
1
VCC(Abs) Supply Voltage with respect to VSS
VCCT
VIN GTL
VIN125
VIN15
System Bus Buffer Voltage with respect to VSS
V
System Bus Buffer DC Input Voltage with respect to VSS
1.25 V Buffer DC Input Voltage with respect to VSS
1.5 V Buffer DC Input Voltage with respect to VSS
1.8 V Buffer DC Input Voltage with respect to VSS
2.0 V Buffer DC Input Voltage with respect to VSS
2.5 V Buffer DC Input Voltage with respect to VSS
VID ball/pin DC Input Voltage with respect to VSS
VID Current
V
2, 3
4
V
V
5
VIN18
2.0
V
6
VIN20
2.4
V
7
VIN25
3.3
V
9
VINVID
IVID
3.465
3.6
V
8
-0.3
mA
8
NOTES:
1. The shipping container is only rated for 65° C.
2. Parameter applies to the AGTL signal groups only. Compliance with both V
specifications is required.
IN GTL
3. The voltage on the AGTL signals must never be below –0.3 V or above 1.75 V with respect to ground.
4. Parameter applies to CLKREF, TESTHI, VTTPWRGD signals.
5. Parameter applies to CMOS, Open-drain, APIC, TESTLO and TAP bus signal groups only.
6. Parameter applies to PWRGOOD signal.
7. Parameter applies to PICCLK signal.
8. Parameter applies to each VID pin/ball individually.
9. Parameter applies to BCLK signal in Single Ended Clocking Mode.
Datasheet
29
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
3.5
DC Specifications
Tables 14 through 21 list the DC specifications for the ULV Intel® Celeron® processor.
Specifications are valid only while meeting specifications for the junction temperature, clock
frequency, and input voltages. The junction temperature range for all DC specifications is 0° C to
100° C unless otherwise noted. Care should be taken to read all notes associated with each
parameter. Unlike the Mobile Intel Pentium® III processor, the Vcc tolerances for the ULV Intel
Celeron processor are not specified as a percentage of nominal. The tolerances are instead specified
in the form of load lines for the static and transient cases in Tables 15 through 18.
Table 14. Power Specifications for the Ultra-Low Voltage Intel® Celeron® Processor
Symbol
Parameter
Min
Typ
Max
Unit
Notes1
1.10
0.95
V
V
VCC
Transient VCC for core logic
9, 10
1.10
0.95
V
V
VCC,DC
VCCT
Static VCC for core logic
9, 10
VCC for System Bus Buffers, Transient
tolerance
1.138 1.25
1.188 1.25
1.362
1.312
V
V
± 9%, 7, 10
± 5%, 2, 10
VCC for System Bus Buffers, Static
tolerance
VCCT,DC
Current for VCC at core frequency
7.58
4.20
ICC
A
4
650 MHz and 1.10 V
400 MHz and 0.95 V
ICCT
Current for VCCT
2.7
A
A
3, 4
4
Processor Auto Halt current at
1.10 V
0.95 V
3.09
1.88
ICC,AH
Processor Quick Start current at
1.10 V
0.95 V
2.91
1.82
ICC,QS
A
A
4
4
Processor Deep Sleep Leakage current at
1.10 V
0.95 V
2.65
1.40
ICC,DSLP
ILVID
dICC/dt
VID leakage current
0.5
mA
8
VCC power supply current slew rate
400
A/µs
5, 6
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. Processors will
comply with the ICCx max specification for the current mode of operation.
,
2. Static voltage regulation includes: DC output initial voltage set point adjust, output ripple and noise,
temperature and warm up.
3. ICCT is the current supply for the system bus buffers, including the on-die termination.
4. ICCx max
18, VCCT max
,
specifications are specified at VCC static (typical) derived from the tolerances in Tables 15 through
, Tjmax, and under maximum signal loading conditions.
,
5. Based on simulations and averaged over the duration of any change in current. Use to compute the
maximum inductance and reaction time of the voltage regulator. This parameter is not tested.
6. Maximum values specified by design/characterization at nominal VCC and VCCT
7. VCCx must be within this range under all operating conditions, including maximum current transients. VCCx
must return to within the static voltage specification, VCCx DC, within 100 µs after a transient event.
8. VID leakage current is < 100 µA for VID voltages under 3.0 V.
.
,
9. Typical VCC indicates the VID encoded voltage. Voltage supplied must conform to the load line specification
shown in Tables 15 through 18.
10.Voltages are measured at the package ball on the Micro FC-BGA device.
30
Datasheet
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
Table 15. V Tolerances for the Ultra-Low Voltage Intel® Celeron® Processor: VID = 1.1 V
CC
ICC (A)
VCC (V)
Static
Min
Transient
Typ
Max
Min
Max
0.0
1.0
1.100
1.096
1.092
1.088
1.084
1.080
1.076
1.072
1.068
1.064
1.060
1.056
1.052
1.048
1.075
1.071
1.067
1.063
1.059
1.055
1.051
1.047
1.043
1.039
1.035
1.031
1.027
1.023
1.125
1.121
1.117
1.113
1.109
1.105
1.101
1.097
1.093
1.089
1.085
1.081
1.077
1.073
1.055
1.051
1.047
1.043
1.039
1.035
1.031
1.027
1.023
1.019
1.015
1.011
1.007
1.003
1.145
1.141
1.137
1.133
1.129
1.125
1.121
1.117
1.113
1.109
1.105
1.101
1.097
1.093
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
11.0
12.0
13.0
Table 16. V Tolerances for the Ultra-Low Voltage Intel® Celeron® Processor in the
CC
Deep Sleep State: VID = 1.1 V
ICC (A)
VCC (V)
Static
Min
Transient
Typ
Max
Min
Max
0.0
1.0
2.0
3.0
4.0
5.0
1.068
1.064
1.060
1.056
1.052
1.048
1.043
1.039
1.035
1.031
1.027
1.023
1.093
1.089
1.085
1.081
1.077
1.073
1.023
1.019
1.015
1.011
1.007
1.003
1.113
1.109
1.105
1.101
1.097
1.093
Datasheet
31
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
Table 17. V Tolerances for the Ultra-Low Voltage Intel® Celeron® Processor: VID = 0.95 V
CC
ICC (A)
VCC (V)
Static
Min
Transient
Typ
Max
Min
Max
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
0.938
0.934
0.930
0.926
0.922
0.918
0.914
0.910
0.906
0.913
0.909
0.905
0.901
0.897
0.893
0.889
0.885
0.881
0.963
0.959
0.955
0.951
0.947
0.943
0.939
0.935
0.931
0.893
0.889
0.885
0.881
0.877
0.873
0.869
0.865
0.861
0.983
0.979
0.975
0.971
0.967
0.963
0.959
0.955
0.951
Table 18. V Tolerances for the Ultra-Low Voltage Intel® Celeron® Processor in the
CC
Deep Sleep State: VID = 0.95 V
ICC (A)
VCC (V)
Static
Min
Transient
Typ
Max
Min
Max
0.0
1.0
2.0
3.0
4.0
0.922
0.918
0.914
0.910
0.906
0.897
0.893
0.889
0.885
0.881
0.947
0.943
0.939
0.935
0.931
0.865
0.861
0.857
0.853
0.849
0.967
0.963
0.959
0.955
0.951
Table 19. AGTL Signal Group DC Specifications
Symbol
Parameter
Input Low Voltage
Min
Max
Unit
Notes
VIL
-0.15
VREF-0.2
VCCT
V
V
See VCCT,max in
Table 14
VIH
Input High Voltage
Output High Voltage
VREF+0.2
—
See VCCT,max in
Table 14
VOH
—
V
RON
IL
16.67
100
W
2
1
Output Low Drive Strength
Leakage Current for Inputs, Outputs and I/Os
µA
NOTES:
1. Specification applies to leakage high only, for pins with on die RTT, (0 < V
2. Refer to IBIS models for I/V characteristics.
≤ V
).
IN/OUT
CCT
32
Datasheet
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
Table 20. AGTL Bus DC Specifications
Symbol
Parameter
Min
Typ
Max
Unit
Notes
VCCT
VREF
Bus Termination Voltage
Input Reference Voltage
Bus Termination Strength
1.25
2/3VCCT
56
V
V
1
2/3VCCT – 2%
50
2/3VCCT + 2%
65
±2%, 2
RTT
W
On-die RTT, 3
NOTES:
1. Refer to Table 14 for minimum and maximum values.
2. V should be created from V by a voltage divider.
REF
CCT
3. The RESET# signal does not have an on-die RTT. It requires an off-die 56.2 Ω ±1% terminating resistor connected to V
.
CCT
Table 21. CLKREF, APIC, TAP, CMOS, and Open-drain Signal Group DC Specifications
(Sheet 1 of 2)
Symbol
Parameter
Min
Max
Unit
Notes
Input Low Voltage, 1.5 V
CMOS
VIL15
–0.15
VCMOSREFmin – 300 mV
V
Input Low Voltage, 1.8 V
CMOS
VIL18
VIH15
VIH15PICD
VIH18
–0.36
0.36
2.0
V
V
V
V
1, 2
10
Input High Voltage, 1.5 V
CMOS
VCMOSREFmax + 250 mV
VCMOSREFmax + 200 mV
1.44
Input High Voltage, 1.5 V
PICD[1:0]
2.0
11
Input High Voltage, 1.8 V
CMOS
2.0
1, 2
All outputs
are
Open-drain
Output High Voltage, 1.5 V
CMOS
VOH15
N/A
2.0
1.615
V
Output High Voltage, 3.3 V
signals
VOH33
VOL33
3.465
0.8
V
V
3.3V + 5%
Output Low Voltage, 3.3 V
signals
VOL
VCMOSREF
VCLKREF
NOTES:
Output Low Voltage
CMOSREF Voltage
CLKREF Voltage
0.3
1.10
1.312
V
V
V
8
4
9
0.90
1.187
1. Parameter applies to the PWRGOOD signal only.
2. VIlx,min and VIhx,max only apply when BCLK, BCLK# and PICCLK are stopped. PICCLK should be stopped in the low state.
See Tables 28 and 29 for DC levels when BCLK and BCLK# are stopped.
3. Measured at 9 mA.
4. VCMOSREF should be created from a stable 1.5-V supply using a voltage divider. It must track the voltage supply to maintain
noise immunity. The same 1.5-V supply should be used to power the chipset CMOS I/O buffers that drive these signals.
5. (0 ≤ VIN/OUT ≤ VIhx,max).
6. Specified as the minimum amount of current that the output buffer must be able to sink. However, VOL,max cannot be ensured
if this specification is exceeded.
7. Parameter applies to VTTPWRGD signal only.
8. Applies to non-AGTL signals except BCLK, PWRGOOD, PICCLK, BSEL[1:0], VID[4:0].
9. ±5% DC tolerance. CLKREF must be generated from the 2.5-V supply used to generate the BCLK signal. AC Tolerance must
be less than –40 dB @ 1 MHz.
10.Applies to all TAP and CMOS signals (not to APIC signals).
11.Applies to PICD[1:0].
Datasheet
33
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
Table 21. CLKREF, APIC, TAP, CMOS, and Open-drain Signal Group DC Specifications
(Sheet 2 of 2)
Symbol
Parameter
Min
Max
Unit
Notes
Input Low Voltage,
VTTPWRGD
VILVTTPWR
0.4
V
7
Input High Voltage,
VTTPWRGD
VIHVTTPWR
1.0
10
V
7
RON
IOL
30
W
3
6
Output Low Current
mA
Leakage Current for Inputs,
Outputs and I/Os
IL
± 100
µA
5
NOTES:
1. Parameter applies to the PWRGOOD signal only.
2. VIlx,min and VIhx,max only apply when BCLK, BCLK# and PICCLK are stopped. PICCLK should be stopped in the low state.
See Tables 28 and 29 for DC levels when BCLK and BCLK# are stopped.
3. Measured at 9 mA.
4. VCMOSREF should be created from a stable 1.5-V supply using a voltage divider. It must track the voltage supply to maintain
noise immunity. The same 1.5-V supply should be used to power the chipset CMOS I/O buffers that drive these signals.
5. (0 ≤ VIN/OUT ≤ VIhx,max).
6. Specified as the minimum amount of current that the output buffer must be able to sink. However, VOL,max cannot be ensured
if this specification is exceeded.
7. Parameter applies to VTTPWRGD signal only.
8. Applies to non-AGTL signals except BCLK, PWRGOOD, PICCLK, BSEL[1:0], VID[4:0].
9. ±5% DC tolerance. CLKREF must be generated from the 2.5-V supply used to generate the BCLK signal. AC Tolerance must
be less than –40 dB @ 1 MHz.
10.Applies to all TAP and CMOS signals (not to APIC signals).
11.Applies to PICD[1:0].
3.6
AC Specifications
3.6.1
System Bus, Clock, APIC, TAP, CMOS, and Open-drain AC
Specifications
All system bus AC specifications for the AGTL signal group are relative to the crossing point of the
rising edge of the BCLK input and falling edge of the BCLK# input. All AGTL timings are
referenced to VREF for both 0 and 1 logic levels unless otherwise specified. All APIC, TAP,
CMOS, and Open-drain signals except PWRGOOD are referenced to 1.0 V. All minimum and
maximum specifications are at points within the power supply ranges shown in Tables 15 through 18
and junction temperatures (Tj) in the range 0° C to 100° C unless otherwise noted. Tj must be less
than or equal to 100° C (or the otherwise-noted given value) for all functional processor states.
34
Datasheet
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
Table 22. System Bus Clock AC Specifications
Symbol
Parameter
Min
Typ
Max
Unit
Notes1
System Bus Frequency
BCLK Period
100
10
MHz
ns
T1S1
2
2
BCLK Period – Instantaneous
Minimum
T1S1abs
9.75
ns
T2S1
T3S1
BCLK Period Stability
BCLK High Time
BCLK Low Time
BCLK Rise Time
BCLK Fall Time
± 250
ps
ns
ns
ns
ns
2, 3, 4
at >2.0 V
at <0.5 V
5
2.70
2.45
0.4
T4S1
T5S1
1.6
1.6
T6S1
0.4
5
NOTES:
1. All AC timings for AGTL and CMOS signals are referenced to the BCLK rising edge at 1.25 V.
2. Period, jitter, skew and offset measured at 1.25 V.
3. Not 100% tested. Specified by design/characterization.
4. Measured on the rising edge of adjacent BCLKs at 1.25 V. The jitter present must be accounted for as a
component of BCLK skew between devices.
5. Measured between 0.5 V and 2.0 V.
Table 23. Valid Ultra-Low Voltage Intel® Celeron® Processor Frequencies
BCLK Frequency
(MHz)
Core Frequency
(MHz)
Power-on Configuration
bits [27,25:22]
Frequency Multiplier
100
100
6.5
4
650
400
0, 1111
0, 0010
NOTE: While other combinations of bus and core frequencies are defined, operation at frequencies other
than those listed above will not be validated by Intel and are not ensured. The frequency multiplier is
programmed into the processor when it is manufactured, and it cannot be changed.
Table 24. AGTL Signal Groups AC Specifications
RTT = 56Ω internally terminated to VCCT; VREF = 2/3VCCT; load = 50 ohms
Symbol
Parameter
Min
Max
Unit
Figure
Notes1
T7
T8
AGTL Output Valid Delay
AGTL Input Setup Time
AGTL Input Hold Time
RESET# Pulse Width
0.40
1.30
1
3.25
ns
ns
ns
ms
7
8
2, 3
4
T9
8
T10
1
9, 10
NOTES:
1. All AC timings for AGTL signals are referenced to the crossing point of the BCLK rising edge and the
BCLK# falling edge for Differential Clocking and to the BCLK rising edge at 1.25 V for Single Ended
Clocking. All AGTL signals are referenced at VREF. RESET# may be asserted (active) asynchronously, but
must be deasserted synchronously.
2. Specification is for a minimum 0.40-V swing from VREF-200 mV to VREF+200 mV.
3. Specification is for a maximum 0.8-V swing from Vcct-0.8 V to Vcct.
4. After VCC, VCCT, and BCLK, BCLK# become stable and PWRGOOD is asserted.
Datasheet
35
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
Table 25. CMOS and Open-drain Signal Groups AC Specifications
Symbol
Parameter
Min
Max
Unit
Figure
Notes1, 2
1.5V Input Pulse Width, except
PWRGOOD and LINT[1:0]
Active and
inactive states
T14
2
BCLKs
7
T14B
T15
LINT[1:0] Input Pulse Width
6
2
BCLKs
µs
7
3
PWRGOOD Inactive Pulse Width
10
4, 5
NOTES:
1. All AC timings for CMOS and Open-drain signals are referenced to the crossing point of the BCLK rising
edge and BCLK# falling edge for Differential Clocking and to the rising edge of BCLK at 1.25 V for Single
Ended Clocking. All CMOS and Open-drain signals are referenced at 1.0 V.
2. Minimum output pulse width on CMOS outputs is 2 BCLKs.
3. This specification only applies when the APIC is enabled and the LINT1 or LINT0 signal is configured as an
edge triggered interrupt with fixed delivery, otherwise specification T14 applies.
4. When driven inactive, or after VCC, VCCT and BCLK, BCLK# become stable. PWRGOOD must remain
below VIL18,MAX until all the voltage planes meet the voltage tolerance specifications in Tables 15 through
18. and BCLK, BCLK# have met the BCLK, BCLK# AC specifications in Tables 30 and 31 for at least 2 µs.
PWRGOOD must rise error-free and monotonically to 1.8 V.
5. If the BCLK Settling Time specification (T60) may be ensured at power-on reset then the PWRGOOD
Inactive Pulse Width specification (T15) is waived and BCLK may start after PWRGOOD is asserted.
PWRGOOD must still remain below V
specifications.
until all the voltage planes meet the voltage tolerance
IL25,max
Table 26. Reset Configuration AC Specifications and Power On/Power Down Timings
(Sheet 1 of 2)
Symbol
Parameter
Min
Typ
Max
Unit
Figure
Notes
Reset Configuration Signals
(A[15:5]#, BREQ0#, FLUSH#, INIT#,
PICD0) Setup Time
Before
deassertion of
RESET#
T16
4
BCLKs
9
Reset Configuration Signals
(A[15:5]#, BREQ0#, FLUSH#, INIT#,
PICD0) Hold Time
After clock that
deasserts
RESET#
T17
T18
2
20
BCLKs
ms
9
Before
RESET#/PWRGOOD Setup Time
1
1
10
deassertion of
RESET# †
T18A
T18B
VCCT to VTTPWRGD Setup Time
VCC to PWRGOOD Setup Time
ms
ms
10
10
10
BSEL, VID valid time before
VTTPWRGD
T18C
1
µs
10
assertion
T18D
T18E
RESET# inactive to Valid Outputs
RESET# inactive to Drive Signals
1
4
BCLK
9
9
BCLKs
VCC (nominal) is
the VID voltage
setting
Time from VCC (nominal)-12% to
PWRGOOD low
T19A
0
ns
11
All outputs valid after PWRGOOD
low
T19B
T19C
0
0
ns
ns
11
11
All inputs required valid after
PWRGOOD low
†
At least 1 ms must pass after PWRGOOD rises above V
specification until RESET# may be deasserted.
and BCLK, BCLK# meet their AC timing
IH18min
36
Datasheet
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
Table 26. Reset Configuration AC Specifications and Power On/Power Down Timings
(Sheet 2 of 2)
Symbol
Parameter
Min
Typ
Max
Unit
Figure
Notes
Time from VCCT-12% to
VTTPWRGD low
T20A
0
ns
12
All outputs valid after VTTPWRGD
low
T20B
T20C
T20D
0
0
0
ns
ns
ns
12
12
12
All inputs required valid after
VTTPWRGD low
VID, BSEL signals valid after
VTTPWRGD low
Measurement
from 300 mV to
900 mV. Amount
of noise (glitch)
less than 100
T20E
VTTPWRGD Transition Time
100
µs
mV. See Section
4.3.1 for details
†
At least 1 ms must pass after PWRGOOD rises above V
specification until RESET# may be deasserted.
and BCLK, BCLK# meet their AC timing
IH18min
Table 27. APIC Bus Signal AC Specifications
Symbol
Parameter
Min
Max
Unit
Figure
Notes1
T21
T22
T23
T24
T25
T26
T27
T28
PICCLK Frequency
PICCLK Period
2
33.3
500
MHz
ns
2
30
PICCLK High Time
PICCLK Low Time
PICCLK Rise Time
PICCLK Fall Time
PICD[1:0] Setup Time
PICD[1:0] Hold Time
10.5
10.5
0.25
0.25
8.0
ns
at>1.6 V
at<0.4 V
(0.4 V – 1.6 V)
(1.6 V – 0.4 V)
3
ns
3.0
3.0
ns
ns
ns
7
7
2.5
ns
3
PICD[1:0] Valid Delay
(Rising Edge)
1.5
1.5
8.7
T29
ns
6
3, 4
PICD[1:0] Valid Delay
(Falling Edge)
12.0
NOTES:
1. All AC timings for APIC signals are referenced to the PICCLK rising edge at 1.0 V. All CMOS signals are
referenced at 1.0 V.
2. The minimum frequency is 2 MHz when PICD0 is at 1.5 V at reset Referenced to PICCLK Rising Edge.
3. For Open-drain signals, Valid Delay is synonymous with Float Delay.
4. Valid delay timings for these signals are specified into 150 Ω to 1.5 V and 0 pF of external load. For real
system timings these specifications must be derated for external capacitance at 105 ps/pF.
Datasheet
37
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
Table 28. TAP Signal AC Specifications
Symbol
Parameter
TCK Frequency
Min
Max
Unit
Figure
Notes1
T30
T31
T32
T33
—
60
16.67 MHz
TCK Period
—
ns
ns
ns
TCK High Time
TCK Low Time
25.0
25.0
≥ VCMOSREF+0.2 V, 2
≤ VCMOSREF-0.2 V, 2
(VCMOSREF-0.2 V) –
T34
T35
TCK Rise Time
TCK Fall Time
5.0
5.0
ns
ns
(VCMOSREF+0.2 V), 2, 3
(VCMOSREF+0.2 V) –
(VCMOSREF-0.2 V), 2, 3
T36
T37
T38
T39
T40
TRST# Pulse Width
TDI, TMS Setup Time
TDI, TMS Hold Time
TDO Valid Delay
40.0
5.0
ns
ns
ns
ns
ns
14
13
13
13
13
Asynchronous, 2
4
4
14.0
1.0
10.0
25.0
5, 6
2, 5, 6
TDO Float Delay
All Non-Test Outputs Valid
Delay
T41
T42
2.0
25.0
25.0
ns
ns
13
13
5, 7, 8
All Non-Test Outputs Float
Delay
2, 5, 7, 8
T43
T44
All Non-Test Inputs Setup Time
All Non-Test Inputs Hold Time
5.0
ns
ns
13
13
4, 7, 8
4, 7, 8
13.0
NOTES:
1. All AC timings for TAP signals are referenced to the TCK rising edge at 1.0 V. All TAP and CMOS signals
are referenced at 1.0 V.
2. Not 100% tested. Specified by design/characterization.
3. 1 ns may be added to the maximum TCK rise and fall times for every 1 MHz below 16 MHz.
4. Referenced to TCK rising edge.
5. Referenced to TCK falling edge.
6. Valid delay timing for this signal is specified into 150 Ω terminated to 1.5 V and 0 pF of external load. For
real system timings these specifications must be derated for external capacitance at 105 ps/pF.
7. Non-Test Outputs and Inputs are the normal output or input signals (except TCK, TRST#, TDI, TDO, and
TMS). These timings correspond to the response of these signals due to boundary scan operations.
8. During Debug Port operation use the normal specified timings rather than the TAP signal timings.
38
Datasheet
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
Table 29. Quick Start/Deep Sleep AC Specifications
Symbol
Parameter
Min Max
Unit
Figure
Notes1
Quick Start Cycle Completion to Clock Stop or
DPSLP# assertion
T45
100
BCLKs
15, 16
Quick Start Cycle Completion to Input Signals
Stable
T46
0
µs
15, 16
T47
T48
Deep Sleep PLL Lock Latency
0
0
30
µs
ns
15, 16
15, 16
2
STPCLK# Hold Time from PLL Lock
Input Signal Hold Time from STPCLK#
Deassertion
T49
8
BCLKs
15, 16
NOTES:
1. Input signals other than RESET# and BPRI# must be held constant in the Quick Start state.
2. The BCLK, BCLK# Settling Time specification (T60) applies to Deep Sleep state exit under all conditions.
Figure 6. BCLK (Single Ended)/PICCLK/TCK Generic Clock Timing Waveform
T
h
T
r
VH
VTRIP
CLK
VL
T
f
T
l
T
p
D0003-01
Figure 7. Differential BCLK/BCLK# Waveform (Common Mode)
V2,V3 (max)
BCLK#
Vcross
BCLK
V1,V3 (min)
Datasheet
39
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
Figure 8. BCLK/BCLK# Waveform (Differential Mode)
T1
VIH_DIFF
V4
0V
V5
VIl_DIFF
T5
T6
Figure 9. Valid Delay Timings
Vc
Vc
CLK
TX
T
x
V
Valid
Valid
Signal
TPW
D0004-00
NOTES:
1. Tx = T7, T11, T29 (Valid Delay)
2. Tpw = T14, T14B (Pulse Width)
3. V = VREF for AGTL signal group; 1.0V for CMOS, Open-drain, APIC, and TAP signal groups
4. Vc = Crossing point of BCLK rising edge and BCLK# falling edge for BCLK references (Differential Clock)
= 1.25V (Single Ended Clock)
Figure 10. Setup and Hold Timings
Vc
CLK
Th
Ts
V
Valid
Signal
D0005-00
NOTES:
1. Ts = T8, T27 (Setup Time)
2. Th =T9, T28 (Hold Time)
3. V = VREF for AGTL signals; 1.0 V for CMOS, APIC, and TAP signals
4. Vc = Crossing point of BCLK rising edge and BCLK# falling edge for BCLK references (Differential Clock)
= 1.25 V (Single Ended Clock)
40
Datasheet
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
‘
Figure 11. Cold/Warm Reset and Configuration Timings
VC
BCLK
T
u
T
t
RESET#
V
T
v
T
T
x
w
Configuration
(A[15:5], BREQ0#,
FLUSH#, INIT#,
PICD0)
Valid
T
y
PICD[1:0]
AGTL/non-AGTL
outputs
Valid
T
z
Non-configuration
inputs
Active
D0006-02
NOTES:
1. Tt = T9 (AGTL Input Hold Time)
2. Tu = T8 (AGTL Input Setup Time)
3. Tv = T10 (RESET# Pulse Width)
4. Tw = T16 (Reset Configuration Signals (A[15:5]#, BREQ0#, FLUSH#, INIT#, PICD0) Setup Time)
5. Tx = T17 (Reset Configuration Signals (A[15:5]#, BREQ0#, FLUSH#, INIT#, PICD0) Hold Time)
6. Ty = T18D (RESET# inactive to Valid Outputs)
7. Tz = T18E (RESET# inactive to Drive Signals)
8. Vc = Crossing point of BCLK rising edge and BCLK# falling edge (Differential Clock)
= 1.25 V (Single Ended Clock)
Datasheet
41
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
Figure 12. Power-on Sequence and Reset Timings
BCLK/BCLK#
VCCT
T
d
VIHVTTPWR,min
VTTPWRGD
VILVTTPWR,max
T
e
VID[4:0]/
BSEL[1:0]
Valid
CMOSREF/
CLKREF/VREF
VCC
T
a
T
c
VIH18,min
PWRGOOD
VIL18,max
T
b
RESET#
V0040-00
NOTES:
1. Ta = T15 (PWRGOOD Inactive Pulse Width)
2. Tb = T18 (RESET#/PWRGOOD Setup Time)
3. Tc = T18B (Setup time from VCC valid until PWRGOOD assertion)
4. Td = T18A (Setup time from VCCT valid to VTTPWRGD assertion)
5. Te = T18C(VID, BSEL valid time before VTTPWRGD assertion)
42
Datasheet
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
Figure 13. Power Down Sequencing and Timings (V Leading)
CC
VCCT, VREF
VCCMOS,
CMOSREF,
CLKREF
VID[4:0]
BSEL[1:0]
VTTPWRGD
VCC
VCC-12%
BCLK/BCLK#
Valid
Valid
PICCLK
Ta
VIL18
PWRGOOD
RESET#
PICD[1:0]
Valid
Valid
Valid
Tb
AGTL OUTPUTS
OTHER CMOS OUTPUTS
ALL INPUTS
Tc
V0044-00
NOTES:
1. Ta = T19A (Time from VCC (nominal) -12% to PWRGOOD low)
2. Tb = T19B (All outputs valid after PWRGOOD low)
3. Tc = T19C (All inputs required valid after PWRGOOD low)
Datasheet
43
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
Figure 14. Power Down Sequencing and Timings (V
Leading)
CCT
VCCT-12%
VCCT, VREF
VCMOS,
CMOSREF,
CLKREF
Ta
VTTPWRGD
VILVTTPWR
VID[4:0]
Valid
BSEL[1:0]
VCC
Tb, Tc, Td
BCLK/BCLK#
Valid
PICCLK
Valid
PWRGOOD
RESET#
PICD[1:0]
Valid
Valid
Valid
AGTL OUTPUTS
OTHER CMOS OUTPUTS
ALL INPUTS
V0045-00
NOTES:
1. Ta = T20A (Time from VCCT-12% to VTTPWRGD low)
2. Tb = T20B (All outputs valid after VTTPWRGD low)
3. Tc = T20C (All inputs required valid after VTTPWRGD low)
4. Td = T20D (VID, BSEL signals valid after VTTPWRGD low)
44
Datasheet
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
Figure 15. Test Timings (Boundary Scan)
TCK
T
T
w
v
0.75V
TDI, TMS
T
T
s
r
Input
Signals
T
T
u
x
TDO
T
T
z
y
Output
Signals
D0008-01
NOTES:
1. Tr = T43 (All Non-Test Inputs Setup Time)
2. Ts = T44 (All Non-Test Inputs Hold Time)
3. Tu = T40 (TDO Float Delay)
4. Tv = T37 (TDI, TMS Setup Time)
5. Tw = T38 (TDI, TMS Hold Time)
6. Tx = T39 (TDO Valid Delay)
7. Ty = T41 (All Non-Test Outputs Valid Delay)
8. Tz = T42 (All Non-Test Outputs Float Delay)
Figure 16. Test Reset Timings
0.75V
TRST#
T
q
D0009-01
NOTE: Tq=T36 (TRST# Pulse Width)
Datasheet
45
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
Figure 17. Quick Start/Deep Sleep Timing (BCLK Stopping Method)
Normal
Quick Start
Deep Sleep
Stopped
Normal
Quick Start
BCLK
Tv
STPCLK#
Ty
Tx
CPU bus
DPSLP#
stpgnt
Tz
Tw
Changing
Compatibility
Signals
Frozen
V00102-00
NOTES:
1. Tv = T45 (Stop Grant Acknowledge Bus Cycle Completion to Clock Shut Off Delay)
2. Tw = T46 (Setup Time to Input Signal Hold Requirement)
3. Tx = T47 (Deep Sleep PLL Lock Latency)
4. Ty = T48 (PLL lock to STPCLK# Hold Time)
5. Tz = T49 (Input Signal Hold Time)
Figure 18. Quick Start/Deep Sleep Timing (DPSLP# Assertion Method)
Normal
Quick Start
Deep Sleep
Normal
Quick Start
BCLK
Tv
STPCLK#
Ty
Tx
CPU bus
DPSLP#
stpgnt
Tz
Tw
Changing
Compatibility
Signals
Frozen
V00103-00
NOTES:
1. Tv = T45 (Stop Grant Acknowledge Bus Cycle Completion to DPSLP# assertion)
2. Tw = T46 (Setup Time to Input Signal Hold Requirement)
3. Tx = T47 (Deep Sleep PLL Lock Latency)
4. Ty = T48 (PLL lock to STPCLK# Hold Time)
5. Tz = T49 (Input Signal Hold Time)
46
Datasheet
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
4.0
System Signal Simulations
Systems must be simulated using IBIS models to determine if they are compliant with this
specification. All references to BCLK signal quality also apply to BCLK# for Differential
Clocking.
4.1
System Bus Clock (BCLK) and PICCLK DC
Specifications and AC Signal Quality Specifications
Table 30. BCLK (Differential) DC Specifications and AC Signal Quality Specifications
Symbol
Parameter
Min
Max
Unit Figure
Notes
V1
V2
VIL,BCLK
VIH,BCLK
-0.2
0.35
1.45
V
V
1
1
0.92
Undershoot/
Overshoot, 2
V3
VIN Absolute Voltage Range
-0.2
1.45
V
V4
V5
BCLK Rising Edge Ringback
BCLK Falling Edge Ringback
0.35
V
V
6
6
3
3
-0.35
1.45
BCLK Voltage in Deep Sleep
State
VBCLK_DPSLP
0.4
0
V
V
4
4
VBCLK_DPSLP
- 0.2 V
BCLK# Voltage in Deep Sleep
State
VBCLK#_DPSLP
NOTES:
1. The clock must rise/fall monotonically between VIL,BCLK and VIH,BCLK.
2. These specifications apply only when BCLK, BCLK# are running.
3. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) voltage
the differential waveform may go to after passing the VIH_DIFF (rising) or VIL_DIFF (falling) levels.
VIL_DIFF (max) = -0.57 V, VIH_DIFF (min) = 0.57 V.
4. Applies when BCLK and BCLK# are stopped in Deep Sleep State.
Table 31. BCLK (Single Ended) DC Specifications and AC Signal Quality Specifications
Symbol
Parameter
Min Max Unit
Figure
Notes
V1
V2
VIL,BCLK
VIH,BCLK
IN Absolute Voltage Range
0.3
V
V
V
V
V
18
18
18
18
18
1
2.2
1
V3
V
-0.5 3.1
2.0
Undershoot/Overshoot, 2
Absolute Value, 3
Absolute Value, 3
V4
BCLK Rising Edge Ringback
BCLK Falling Edge Ringback
V5
0.5
NOTES:
1. The clock must rise/fall monotonically between VIL,BCLK and VIH,BCLK. BCLK must be stopped in the low
state.
2. These specifications apply only when BCLK is running. BCLK may not be above VIH,BCLK,max or below
V
BCLK,min for more than 50% of the clock cycle.
IL,
3. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the BCLK signal may go to after passing the VIH,BCLK (rising) or VIL,BCLK (falling) voltage limits.
Datasheet
47
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
Table 32. PICCLK DC Specifications and AC Signal Quality Specifications
Symbol
Parameter
Min Max Unit
Figure
Notes
V1
V2
VIL20
VIH20
0.4
2.4
0.4
V
V
V
V
V
18
18
18
18
18
1
1.6
-0.5
1.6
1
V3
V
IN Absolute Voltage Range
Undershoot, Overshoot, 2
Absolute Value, 3
Absolute Value, 3
V4
PICCLK Rising Edge Ringback
PICCLK Falling Edge Ringback
V5
NOTES:
1. The clock must rise/fall monotonically between V
2. These specifications apply only when PICCLK is running. See the DC specifications for when PICCLK is
and V
.
IL20
IH20
stopped. PICCLK may not be above V
3. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
or below V
for more than 50% of the clock cycle.
IH20,max
IL20,min
voltage the PICCLK signal may go to after passing the V
(rising) or V
(falling) voltage limits.
IH20
IL20
Figure 19. BCLK (Single Ended)/PICCLK Generic Clock Waveform
V3max
V4
V2
V1
V5
V3min
V0012-01
4.2
AGTL AC Signal Quality Specifications
Ringback specifications for the AGTL signals are as follows: Ringback below VREF,max + 200 mV
is not authorized during low to high transitions. Ringback above VREF,min – 200 mV is not
authorized during high to low transitions.
Overshoot and undershoot specifications are documented in Table 33 and illustrated in Figure 20.
48
Datasheet
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
Figure 20. Maximum Acceptable Overshoot/Undershoot Waveform
Time Dependant Overshoot
Max
Vss
Min
Time Dependant Undershoot
Table 33. 100-MHz AGTL Signal Group Overshoot/Undershoot Tolerance
at the Processor Core
Max VCCT + Overshoot/
Allowed Pulse Duration (ns) [Tj=100C (see Note 7)]
Undershoot Magnitude (volts)
Activity Factor =
0.01
Activity Factor =
0.1
Activity Factor = 1
1.78
1.73
1.68
1.63
1.58
1.53
1.48
1.6
4.5
9.5
20
0.16
0.45
0.95
2.0
0.016
0.045
0.095
0.2
20
4.2
0.42
0.85
1.9
20
8.5
20
19
NOTES:
1. Under no circumstances should the sum of the Max VCCT and absolute value of the Overshoot/Undershoot
voltage exceed 1.78 V.
2. Activity factor of 1 represents the same toggle rate as the 100-MHz clock.
3. Ringbacks below VCCT cannot be subtracted from overshoots. Lesser undershoot does not allocate longer
or larger overshoot.
4. Ringbacks above ground cannot be subtracted from undershoots. Lesser overshoot does not allocate
longer or larger undershoot.
5. System designers are encouraged to follow Intel provided AGTL layout guidelines.
6. All values are specified by design characterization and are not tested.
7. Tj = 85° C for 1.33 GHz.
Datasheet
49
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
4.3
Non-AGTL Signal Quality Specifications
Signals driven to the ULV Intel® Celeron® processor should meet signal quality specifications to
ensure that the processor reads data properly and that incoming signals do not affect the long-term
reliability of the processor. The overshoot and undershoot specifications for non-AGTL signals are
shown in Table 34. Ringback must not exceed the CMOS VIH and VIL specification levels in Table
21.
Table 34. Non-AGTL Signal Group Overshoot/Undershoot Tolerance at the Processor Core
Max VCmos + Overshoot/
Allowed Pulse Duration (ns) [Tj=100C (see Note 6)]
Undershoot Magnitude (volts)
Activity Factor = 0.01 Activity Factor = 0.1 Activity Factor = 1
2.38
2.33
2.28
2.23
2.18
2.13
2.08
6.5
13
29
60
60
60
60
0.65
1.3
2.9
6
0.065
0.13
0.29
0.6
12
1.2
26
2.6
56
5.6
NOTES:
1. VCMOS(nominal) = 1.5 V.
2. Under no circumstances should the sum of the Max VCMOS and absolute value of the Overshoot/
Undershoot voltage exceed 2.38 V.
3. Activity factor of 1 represents a toggle rate of 33 MHz.
4. System designers are encouraged to follow Intel provided non-AGTL layout guidelines.
5. All values are specified by design characterization, and are not tested.
6. Tj = 85° C for 1.33 GHz.
4.3.1
PWRGOOD, VTTPWRGD Signal Quality Specifications
The processor requires PWRGOOD to be a clean indication that clocks and the power supplies
(VCC, VCCT, etc.) are stable and within their specifications. Clean implies that the signal will
remain below V
and without errors from the time that the power supplies are turned on, until
IL18
they come within specification. The signal will then transition monotonically to a high (1.8 V)
state. The VTTPWRGD signal must also transition monotonically.
The VTTPWRGD signal is an input to the processor used to determine that the VTT power is
stable and the VID and BSEL signals should be driven to their final state by the processor. To
ensure the processor correctly reads this signal, the processor must meet the requirement shown in
Table 35 while the signal is in its transition region of 300 mV to 900 mV. Also, VTTPWRGD
should only enter the transition region once, after VTT is at nominal values, for the assertion of the
signal.
50
Datasheet
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
4.3.1.1
VTTPWRGD Noise Parameter Specification
Table 35. VTTPWRGD Noise Parameter Specification
Parameter
Specification
Amount of noise (glitch)
Less than 100 mV
In addition, the VTTPWRGD signal should have reasonable transition time through the transition
region. A sharp edge on the signal transition will minimize the chance of noise causing a glitch on
this signal. Intel recommends the following transition time for the VTTPWRGD signal.
4.3.1.2
VTTPWRGD Transition Parameter Recommendation
Table 36. VTTPWRGD Transition Parameter Recommendation
Parameter
Recommendation
Transition time (300 mV to 900 mV)
Less than or equal to 100 µs
In addition, the VTT_PWRGD signal should have reasonable transition time through the transition
region. A sharp edge on the signal transition will minimize the chance of noise causing a glitch on
this signal. Intel recommends the following transition time for the VTT_PWRGD signal.
4.3.1.2.1 Transition Region
The transition region covered by this requirement is 300 mV to 900 mV. Once the VTTPWRGD
signal is in that voltage range, the processor is more sensitive to noise, which may be present on the
signal. The transition region when the signal first crosses the 300-mV voltage level and continues
until the last time it is below 900 mV.
4.3.1.2.2 Transition Time
The transition time is defined as the time the signal takes to move through the transition region. A
100-µs transition time will ensure that the processor receives a good transition edge.
4.3.1.2.3 Noise
The signal quality of the VTTPWRGD signal is critical to the correct operation of the processor.
Every effort should be made to ensure this signal is monotonic in the transition region. If noise or
glitches are present on this signal, the noise or glitches must be kept to less than 100 mV of a
voltage drop from the highest voltage level received to that point. This glitch must remain less than
100 mV until the excursion ends by the voltage returning to the highest voltage previously
received. See Figure 21 for an example graph of this situation and requirements.
Datasheet
51
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
Figure 21. VTTPWRGD Noise Specification
52
Datasheet
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
5.0
Mechanical Specifications
5.1
Surface Mount Micro FC-BGA Package
The ULV Intel® Celeron® processor is packaged in a surface mount, 479-ball Micro FC-BGA
package. Mechanical specifications are shown in Table 37. Figure 22 through Figure 24 illustrate
different views of the package.
The Micro FC-BGA package may have capacitors placed in the area surrounding the die. Because
the die-side capacitors are electrically conductive, and only slightly shorter than the die height, care
should be taken to avoid contacting the capacitors with electrically conductive materials. Doing so
may short the capacitors, and possibly damage the device or render it inactive. The use of an
insulating material between the capacitors and any thermal solution should be considered to
prevent capacitor shorting.
Table 37. Micro FC-BGA Package Mechanical Specifications
Symbol
Parameter
Overall height, as delivered1
Min
Max
Unit
A
A2
b
2.27
2.77
mm
mm
mm
mm
mm
Die height
0.854
0.78
Ball diameter
D
Package substrate length
Package substrate width
34.9
34.9
35.1
35.1
E
3
11.18
10.82
D1
E1
Die length
Die width
mm
mm
4
3
7.20
6.85
4
e
Ball pitch
1.27
479
5
mm
each
mm
mm
mm
mm
mm
kPa
g
N
Ball count
K
K1
Keep-out outline from edge of package
Keep-out outline at corner of package
Capacitor keep-out height
Package edge to first ball center
Solder ball coplanarity
7
K2
-
0.7
S
1.625
0.2
--
Pdie
W
Allowable pressure on the die for thermal solution
Package weight
-
689
4.5
NOTES:
1. All dimensions are subject to change.
2. Overall height as delivered. Values were based on design specifications and tolerances. Final height after
surface mount depends on OEM motherboard design and SMT process.
3. Dimension for CPUID = 0x06B1.
4. Dimension for CPUID = 0x06B4.
Datasheet
53
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
Figure 22. Micro FC-BGA Package – Top and Bottom Isometric Views
PACKAGE KEEPOUT
CAPACITOR AREA
DIE
LABEL
TOP VIEW
BOTTOM VIEW
Figure 23. Micro FC-BGA Package – Top and Side Views
SUBSTRATE KEEPOUT ZONE
DO NOT CONTACT PACKAGE
INSIDE THIS LINE
7 (K1)
8 places
0.20
A
5 (K)
4 places
A2
D1
35 (D)
Ø0.78 (b)
479 places
K2
E1
35 (E)
PIN A1 CORNER
NOTE: All dimensions are in millimeters. Values shown are for reference only. See Table 36 for specific details.
54
Datasheet
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
Figure 24. Micro FC-BGA Package – Bottom View
1.625 (S)
4 places
AF
AD
AB
Y
AE
AC
AA
W
U
1.625 (S)
4 places
V
T
R
P
N
M
K
L
J
H
G
F
E
D
C
B
A
1
3
13 15 17
11
10 12 14 16 18
5
7
9
19 21 23 25
25X 1.27
(e)
2
4
6
8
22 24 26
20
25X 1.27
(e)
NOTE: All dimensions are in millimeters. Values shown are for reference only. See Table 39 for specific details.
5.2
Signal Listings
Figure 25 is a top-side view of the ball map of the ULV Intel® Celeron® processor with the voltage
balls called out. Table 38 lists the signals in ball number order. Table 39 lists the signals in signal
name order.
Datasheet
55
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
Figure 25. Ball Map – Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
A
B
A
B
NC
A10# VREF
NC
A17#
VCCT
VCCT
VCC
VSS
VCC
VSS
VCC
VSS
NC
A31# BREQ0# A23#
A27#
A20#
A24#
VSS
NC
A35#
VSS
A26#
A34#
A33#
A32#
D0#
D2#
D1#
D15#
VSS
D9#
D4#
D7#
VSS
D5#
VREF
D17#
VCCT
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
D8#
VSS
NC
D10#
D18#
VSS
D11#
D14#
D20#
D13#
D23#
D21#
D25#
D26#
D34#
D31#
D28#
D39#
NC
VSS
D24#
VSS
D22#
VSS
D36#
VSS
VCCT
VSS
D30#
NC
NC
NC
VSS
A16#
VSS
A25#
A28#
A13#
VSS
NC
VSS
A21#
VSS
A18#
VSS RESET# VSS
C
C
A19# VCCT
A22# VCCT A30# VCCT A29# VCCT BERR# VCCT
D6#
VCC
VSS
VCC
VCCT D12# VCCT
D
D
NC
VSS
VCCT
VSS
VCC
VCCT
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCCT
INIT#
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
D3#
E
E
VTT
PWRGD
NC
TESTHI
VSS
D16#
VSS
D19#
D27#
D32#
F
F
NC
A14#
G
G
A9#
A12#
A4#
A3#
A5#
A15# VCCT
VCCT
VSS
H
H
VSS
A8#
VSS
D29# VREF
J
J
A7#
A11# VCCT
VCCT
VSS
VSS
D33#
VSS
D45#
VSS
D41#
VSS
D57#
VSS
D46#
VSS
D53#
VSS
D38#
D35#
D42#
D48#
D37#
NC
K
K
VSS
A6#
VSS
L
L
REQ4# BNR# REQ1# VCCT
VCCT
VSS
M
N
M
N
TESTLO
VSS
VSS
PLL1
API#
VSS
NC
RSP#
VCC
NC
VREF PLL2
VCCT
VSS
P
P
NC
VSS
NC
D49#
D43#
D47#
D52#
D63#
D59#
D58#
D62#
D61#
R
R
REQ0# BPRI# VID4
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCCT
VSS
D44#
D51#
D40#
D55#
D54#
D60#
D50#
T
T
REQ2# VSS DEFER# RP#
U
U
REQ3# HITM# RS2#
VSS
VCCT
VSS
V
V
RS1#
VSS LOCK# VCCT
W
Y
W
Y
TRDY# AERR# DBSY# VSS
VCCT
VSS
DRDY# VSS
RS0#
TESTLO
AA
AB
AC
AD
AE
AF
AA
AB
AC
AD
AE
AF
VREF
VID0
HIT#
VSS
ADS# VCCT
VCC
VSS
VCC
TDI
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
TDO
VSS
VCC
VSS
VCC
VSS
VCC
NC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCCT
VSS
PWR
AP0#
D56# VREF
GOOD
BCLK
VID1 A20M# VCCT
VCCT DEP3# VSS DEP6#
BCLK#
CLKREF
/
CMOS
REF
VSS
SMI#
NC
VCCT IGNNE# TCK
VCCT
VCCT LINT0 NCTRL PICD1 VCCT PICD0 VCCT BPM 1# BPM 0#
NC
DEP7# DEP1# DEP5#
RTT
IMPEDP
VSS
VID2 VCCT STPCLK# VSS
VSS
NC
VSS
NC
VSS BSEL0 VSS
CMOS
LINT1
VSS
VSS
NC
VCCT
NC
VSS
BP3#
VSS PRDY# VSS DEP0# DEP2# VSS
EDGE
CTRLP
THRMDATHRMDC
VCCT VCCT
VID3 IERR# FLUSH# FERR# TMS DPSLP# VREF BSEL1 TESTHI
TRST#
PREQ# PICCLK VREF BP2# BINIT# DEP4# VSS
VSS
REF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
VCC
VSS VCCT Other
NOTE: A2 pin is de-populated on Micro-FCPGA package.
56
Datasheet
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
Table 38. Signal Listing in Order by Ball Number (Sheet 1 of 4)
No.
Signal Name
No.
Signal Name
No.
Signal Name
No.
Signal Name
A3
A4
A10#
VREF
NC
B18
B19
B20
B21
B22
B23
B24
B25
B26
C1
VSS
D4#
D7
D8
VSS
VCC
VSS
E22
E23
E24
E25
E26
F1
VSS
D16#
D23#
VSS
D19#
NC
A5
VSS
D9
A6
A31#
BREQ0#
A23#
A27#
A24#
NC
D17#
VSS
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
E1
VCC
VSS
A7
A8
D18#
D14#
D24#
VSS
VCC
VSS
A9
F2
VSS
A14#
VSS
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
D21#
D36#
D27#
A9#
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
B1
VCC
VSS
F3
F4
A35#
A26#
A33#
A32#
D0#
NC
VCC
VSS
F5
C2
A16#
A28#
NC
F6
C3
VCC
VSS
F7
C4
F8
C5
VCCT
A19#
VCCT
A22#
VCCT
A30#
VCCT
A29#
VCCT
BERR#
VCCT
D6#
VCC
VSS
F9
D2#
C6
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
G1
D15#
D9#
C7
VCC
D3#
C8
D7#
C9
D13#
D22#
NC
VREF
D8#
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
D1
D10#
D11#
VSS
NC
E2
TESTHI
VTTPWRGD
VCCT
VCC
VCCT
VCC
VSS
E3
VCCT
NC
E4
E5
B2
VSS
VCCT
D12#
VCCT
D5#
E6
B3
A25#
VSS
E7
B4
E8
B5
A17#
VSS
E9
VCC
VSS
B6
VCCT
NC
E10
E11
E12
E13
E14
E15
E16
E17
B7
A21#
VSS
VCC
VSS
B8
VSS
B9
A20#
VSS
D20#
VSS
VCC
VSS
G2
A5#
B10
B11
B12
B13
G3
A15#
VCCT
VCC
VSS
A18#
VSS
D30#
NC
VCC
VSS
G4
G5
A34#
D2
VSS
VCC
G6
Datasheet
57
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
Table 38. Signal Listing in Order by Ball Number (Sheet 2 of 4)
No.
Signal Name
No.
Signal Name
No.
Signal Name
No.
Signal Name
B14
B15
B16
B17
G25
G26
H1
VSS
RESET#
VSS
D1#
D3
D4
A13#
VSS
E18
E19
E20
E21
P23
P24
P25
P26
P26
R1
VSS
VCC
G21
G22
G23
G24
V2
VCC
VSS
D5
VCCT
VCC
VCCT
NC
VSS
VCCT
D25#
VSS
D6
VCC
VSS
D32#
A12#
VSS
VSS
A8#
L4
VSS
L5
D49#
D41#
NC
V3
LOCK#
VCCT
VSS
L6
VSS
V4
H2
L21
L21
L22
L23
L24
L25
L26
M1
VCC
VCC
VSS
V5
H2
NC
V5
VSS
H3
REQ0#
BPRI#
VID4
VSS
V6
VCC
H4
VSS
VSS
VCC
VSS
VCC
VSS
D26#
D29#
VREF
A4#
VCCT
D28#
VSS
R2
V21
V22
V23
V24
V25
V26
W1
W2
W3
W4
W5
W6
W21
W22
W23
W24
W25
W26
Y1
VSS
H5
R3
VCC
H6
R4
VSS
H21
H22
H23
H24
H25
H26
J1
D42#
TESTLO
VSS
R5
VCC
D63#
D46#
D55#
TRDY#
AERR#
DBSY#
VSS
R6
VSS
M2
R21
R22
R23
R24
R25
R26
T1
VCC
M3
VSS
VSS
M4
VSS
VCCT
D43#
VSS
M5
RSP#
VCC
VSS
M6
J2
A7#
M21
M22
M23
M24
M25
M26
N1
D44#
REQ2#
VSS
VCC
J3
A11#
VCCT
VCC
VSS
VCC
VSS
VCCT
D34#
VSS
D38#
A3#
VCC
VSS
VSS
J4
T2
VCC
J5
D39#
D45#
D48#
VREF
PLL2
PLL1
NC
T3
DEFER#
RP#
VSS
J6
T4
VCCT
D59#
VSS
J21
J22
J23
J24
J25
J26
K1
T5
VSS
T6
VCC
N2
T21
T22
T23
T24
T25
T26
U1
VSS
D54#
DRDY#
VSS
N3
VCC
N4
VSS
Y2
N5
VCC
VSS
D47#
D57#
D51#
REQ3#
HITM#
RS2#
VSS
Y3
RS0#
TESTLO
VSS
N6
Y4
K2
VSS
A6#
N21
N22
N23
N24
N25
N26
VCC
VSS
Y5
K3
Y6
VCC
K4
VSS
VSS
VCC
VSS
VCCT
NC
U2
Y21
Y22
Y23
Y24
VSS
K5
U3
VCC
K6
VSS
U4
VSS
K21
D37#
U5
VCC
D58#
58
Datasheet
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
Table 38. Signal Listing in Order by Ball Number (Sheet 3 of 4)
No.
Signal Name
No.
Signal Name
No.
Signal Name
No.
Signal Name
K22
K23
VCC
VSS
P1
NC
VSS
API#
NC
U6
VSS
VCC
Y25
Y26
D53#
D60#
P2
U21
K24
D31#
D33#
D35#
REQ4#
BNR#
REQ1#
VCC
P3
U22
VSS
AA1
VREF
K25
P4
U23
VCCT
D52#
VSS
AA2
HIT#
K26
P5
NC
U24
AA3
ADS#
L1
P6
VCC
VSS
VCC
VCC
VSS
D61#
D56#
VREF
BCLK
VID1
A20M#
VCCT
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCCT
DEP3#
VSS
U25
AA4
VCCT
VCC
L2
P21
U26
D40#
RS1#
TDO
AA5
L3
P22
V1
AA6
VSS
AA7
AA8
AA9
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA26
AB1
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
AB10
AB22
AB23
AB24
AB25
AB26
AC1
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AE1
AE26
AF1
VSS
VSS
VCCT
NC
VCCT
VCCT
VID3
VCC
AF2
VSS
VCCT
LINT0
NCTRL
PICD1
VCCT
PICD0
VCCT
BPM1#
BPM0#
NC
AF3
VCC
AF4
IERR#
FLUSH#
FERR#
TMS
VSS
AF5
VCC
AC2
AF6
VSS
AC3
AF7
VCC
AC4
AF8
DPSLP#
VREF
VSS
AC5
AF9
VCC
AC6
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
BSEL1
TESTHI
CMOSREF
THRMDA
THRMDC
TRST#
EDGECTRLP
NC
VSS
AC7
VCC
AC8
VSS
AC9
DEP7#
DEP1#
DEP5#
VSS
VCC
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
VSS
VCCT
D62#
VSS
AE2
VID2
AE3
VCCT
STPCLK#
VSS
NC
D50#
VID0
VSS
AE4
PREQ#
PICCLK
VREF
AE5
AE6
INIT#
VSS
AP0#
PWRGOOD
VSS
AE7
BP2#
AE8
NC
BINIT#
DEP4#
VSS
AE9
VSS
VCC
AE10
AE11
AE12
AE13
AE14
NC
VSS
VSS
VSS
VCC
BSEL0
VSS
VSS
VCC
LINT1
Datasheet
59
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
Table 38. Signal Listing in Order by Ball Number (Sheet 4 of 4)
No.
Signal Name
No.
Signal Name
No.
Signal Name
No.
Signal Name
AB11
VSS
AC26
DEP6#
AE15
VSS
BCLK#/
CLKREF
AB12
VCC
AD1
AE16
RTTIMPEDP
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
VSS
SMI#
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
VSS
VCCT
VSS
NC
CMOSREF
VCCT
TDI
BP3#
VSS
PRDY#
VSS
VCCT
IGNNE#
TCK
DEP0#
DEP2#
Table 39. Signal Listing in Order by Signal Name (Sheet 1 of 3)
No.
Signal Name
Signal Buffer Type
No.
Signal Name
Signal Buffer Type
K1
J1
A3#
A4#
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AF23
L2
BINIT#
BNR#
BP2#
AGTL I/O
AGTL I/O
G2
K3
J2
A5#
AF22
AE20
AD22
AD21
R2
AGTL I/O
A6#
BP3#
AGTL I/O
A7#
BPM0#
BPM1#
BPRI#
BREQ0#
BSEL0
BSEL1
CMOSREF
CMOSREF
D0#
AGTL I/O
H3
G1
A3
J3
A8#
AGTL I/O
A9#
AGTL Input
AGTL I/O
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A7
AE12
AF10
AD5
AF12
A16
B17
A17
D23
B19
C20
C16
A20
A22
A19
3.3 V CMOS Output
3.3 V CMOS Output
CMOS Reference Voltage
CMOS Reference Voltage
AGTL I/O
H1
D3
F3
G3
C2
B5
B11
C6
B9
B7
C8
A8
A10
D1#
AGTL I/O
D2#
AGTL I/O
D3#
AGTL I/O
D4#
AGTL I/O
D5#
AGTL I/O
D6#
AGTL I/O
D7#
AGTL I/O
D8#
AGTL I/O
D9#
AGTL I/O
60
Datasheet
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
Table 39. Signal Listing in Order by Signal Name (Sheet 2 of 3)
No.
Signal Name
Signal Buffer Type
No.
Signal Name
Signal Buffer Type
B3
A25#
A26#
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
1.5V CMOS Input
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
Clock Input
Clock Input
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
AGTL I/O
A23
A24
C18
D24
B24
A18
E23
B21
B23
E26
C24
F24
D10#
D11#
AGTL I/O
AGTL I/O
A13
A9
A27#
D12#
AGTL I/O
C3
A28#
D13#
AGTL I/O
C12
C10
A6
A29#
D14#
AGTL I/O
A30#
D15#
AGTL I/O
A31#
D16#
AGTL I/O
A15
A14
B13
A12
AC3
AA3
W2
A32#
D17#
AGTL I/O
A33#
D18#
AGTL I/O
A34#
D19#
AGTL I/O
A35#
D20#
AGTL I/O
A20M#
ADS#
AERR#
AP0#
AP1#
BCLK
BCLK#/CLKREF
BERR#
D29#
D21#
AGTL I/O
D25
E24
B25
G24
H24
F26
D22#
AGTL I/O
D23#
AGTL I/O
AB3
P3
D24#
AGTL I/O
D25#
AGTL I/O
AC1
AD1
C14
H25
C26
K24
G26
K25
J24
K26
F25
N26
J26
M24
U26
P25
L26
R24
R26
M25
V25
T24
D26#
AGTL I/O
D27#
AGTL I/O
L24
D28#
AGTL I/O
AF24
AD26
AC26
AD24
Y1
DEP4#
DEP5#
DEP6#
DEP7#
DRDY#
DPSLP#
EDGECTRLP
FERR#
FLUSH#
HIT#
AGTL I/O
D30#
AGTL I/O
D31#
AGTL I/O
D32#
AGTL I/O
D33#
AGTL I/O
D34#
AF8
AF16
AF6
AF5
AA2
U2
1.5 V CMOS Input
AGTL Control
1.5 V Open Drain Output
1.5 V CMOS Input
AGTL I/O
D35#
D36#
D37#
D38#
D39#
HITM#
IERR#
IGNNE#
INIT#
AGTL I/O
D40#
AF4
AD9
AE6
AD15
V3
1.5 V Open Drain Output
1.5 V CMOS Input
1.5 V CMOS Input
1.5 V CMOS Input
AGTL I/O
D41#
D42#
D43#
INTR/LINT0
LOCK#
NMI/LINT1
NCTRL
PICCLK
D44#
D45#
AE14
AD16
AF20
1.5 V CMOS Input
AGTL impedance control
1.8 V APIC Clock Input
D46#
D47#
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61
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
Table 39. Signal Listing in Order by Signal Name (Sheet 3 of 3)
No.
Signal Name
Signal Buffer Type
No.
Signal Name
Signal Buffer Type
M26
P24
D48#
D49#
AGTL I/O
AGTL I/O
AD19
AD17
N3
PICD0
PICD1
1.5 V Open Drain I/O
1.5 V Open Drain I/O
PLL Analog Voltage
PLL Analog Voltage
AGTL Output
1.5 V CMOS Input
1.8 V CMOS Input
AGTL I/O
AA26
T26
D50#
AGTL I/O
PLL1
D51#
AGTL I/O
N2
PLL2
U24
Y25
D52#
AGTL I/O
AE22
AF19
AB4
R1
PRDY#
PREQ#
PWRGOOD
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
RESET#
RP#
D53#
AGTL I/O
W26
V26
D54#
AGTL I/O
D55#
AGTL I/O
AB25
T25
D56#
AGTL I/O
L3
AGTL I/O
D57#
AGTL I/O
T1
AGTL I/O
Y24
D58#
AGTL I/O
U1
AGTL I/O
W24
Y26
D59#
AGTL I/O
L1
AGTL I/O
D60#
AGTL I/O
B15
T4
AGTL Input
AB24
AA24
V24
D61#
AGTL I/O
AGTL I/O
D62#
AGTL I/O
Y3
RS0#
AGTL I/O
D63#
AGTL I/O
V1
RS1#
AGTL I/O
W3
DBSY#
DEFER#
DEP0#
DEP1#
DEP2#
DEP3#
TCK
AGTL I/O
U3
RS2#
AGTL I/O
T3
AGTL Input
AGTL I/O
M5
RSP#
AGTL Input
AE24
AD25
AE25
AC24
AD10
AD7
AD11
E2
AE16
AD3
AE4
RTTIMPEDP
SMI#
AGTL Pull-up Control
1.5 V CMOS Input
1.5 V CMOS Input
AGTL I/O
AGTL I/O
STPCLK#
AGTL I/O
1.5V JTAG Clock Input
JTAG Input
JTAG Output
Test Use Only
Test Use Only
Test Use Only
Test Use Only
Thermal Diode Anode
AC2
AE2
AF3
R3
VID1
VID2
Voltage Identification
Voltage Identification
TDI
TDO
VID3
Voltage Identification
TESTHI
TESTHI
TESTLO
TESTLO
THERMDA
VID4
Voltage Identification
AF11
M1
A4
VREF
VREF
VREF
VREF
AGTL Reference Voltage
AGTL Reference Voltage
AGTL Reference Voltage
AGTL Reference Voltage
A21
N1
Y4
AF13
AF9
Thermal Diode
Cathode
AF14
THERMDC
AF21
VREF
AGTL Reference Voltage
AF7
W1
TMS
TRDY#
TRST#
VID0
JTAG Input
AGTL I/O
AA1
AB26
H26
E3
VREF
VREF
AGTL Reference Voltage
AGTL Reference Voltage
AGTL Reference Voltage
VCCT power good signal
AF15
AB1
JTAG Input
VREF
Voltage Identification
VTTPWRGD
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Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
Table 40. Voltage and No-Connect Ball Locations
Signal
Name
Pin/Ball Numbers
A2, A5, A11, B1, C1, C4, C22, D1, D26, E1, F1, L5, N4, N24, P1, P4, P5, P26, AD4, AD13, AD23,
AE8, AE10, AF17, AF18
NC
D6, D8, D10, D12, D14, D16, D18, D20, D22, E5, E7, E9, E11, E13, E15, E17, E19, E21, F6, F8,
F10, F12, F14, F16, F18, F20, F22, G5, G21, H6, H22, J5, J21, K6, K22, L21, M6, M22, N5, N21,
P6, P22, R5, R21, T6, T22, U5, U21, V6, V22, W5, W21, Y6, Y22, AA5, AA7, AA9, AA11, AA13,
AA15, AA17, AA19, AA21, AB6, AB8, AB10, AB12, AB14, AB16, AB18, AB20, AB22, AC5,
AC7, AC9, AC11, AC13, AC15, AC17, AC19, AC21
VCC
A26, C5, C7, C9, C11, C13, C15, C17, C19, C21, D5, E4, E6, G4, G23, J4, J23, L4, L23, N23,
R23, U23, V4, W23, AA4, AA23, AC4, AC23, AD6, AD8, AD12, AD14, AD18, AD20, AE3, AE18,
AF1, AF2
VCCT
A25, B2, B4, B6, B8, B10, B12, B14, B16, B18, B20, B22, B26, C23, C25, D2, D4, D7, D9, D11,
D13, D15, D17, D19, D21, E8, E10, E12, E14, E16, E18, E20, E22, E25, F2, F4, F5, F7, F9, F11,
F13, F15, F17, F19, F21, F23, G6, G22, G25, H2, H4, H5, H21, H23, J6, J22, J25, K2, K4, K5,
K21, K23, L6, L22, L25, M2, M3, M4, M21, M23, N6, N22, N25, P2, P21, P23, R4, R6, R22, R25,
T2, T5, T21, T23, U4, U6, U22, U25, V2, V5, V21, V23, W4, W6, W22, W25, Y2, Y5, Y21, Y23,
AA6, AA8, AA10, AA12, AA14, AA16, AA18, AA20, AA22, AA25, AB2, AB5, AB7, AB9, AB11,
AB13, AB15, AB17, AB19, AB21, AB23, AC6, AC8, AC10, AC12, AC14, AC16, AC18, AC20,
AC22, AC25, AD2, AE1, AE5, AE7, AE9, AE11, AE13, AE15, AE17, AE19, AE21, AE23, AE26,
AF25, AF26
VSS
NOTE: A2 pin is de-populated on the Micro-FCPGA package.
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Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
6.0
V Thermal Specifications
CC
In order to achieve proper cooling of the processor, a thermal solution (e.g., heat spreader, heat
pipe, or other heat transfer system) must make firm contact to the exposed processor die. The
processor die must be clean before the thermal solution is attached or the processor may be
damaged.
Table 41 provides the Thermal Design Power (TDP) dissipation and the minimum and maximum
TJ temperatures for the ULV Intel® Celeron® processor. The thermal solution should be designed
to ensure the junction temperature never exceeds the specified value while operating at the
Thermal Design Power. Additionally, a secondary fail-safe mechanism in hardware should be
provided to shutdown the processor at 101° C to prevent permanent damage, as described in
Section 3.1.3. TDP is a thermal design power specification based on the worst case power
dissipation of the processor while executing publicly available software under normal operating
conditions at nominal voltages. Contact your Intel Field Sales Representative for further
information.
Table 41. Power Specifications for the Ultra-Low Voltage Intel® Celeron® Processor
Thermal
Thermal
Symbol
Core Frequency/Voltage
Design Power Design Power Unit
Notes
(typ)
(max)
650 MHz and 1.10 V
400 MHz and 0.95 V
7.00
3.40
8.30
4.23
TDP
W
At 100° C, 1, 4
Symbol
Parameter
Min
Max
Unit
Notes
Auto Halt power at
1.10 V
0.95 V
1.9
1.0
PAH
W
W
At 50° C, 2
At 50° C, 2
Quick Start power at
1.10 V
0.95 V
1.7
0.9
PQS
Deep Sleep power at
1.10 V
0.95 V
1.6
0.7
PDSLP
W
At 35° C, 2
3
TJ
Junction Temperature
0
100
° C
NOTES:
1. TDP (typ) is defined as the worst case power dissipated by the processor while executing publicly
available software under normal operating conditions at nominal voltages that meet the load line
specifications. The TDP number shown is a specification based on Icc (maximum) and indirectly tested by
Icc (maximum) testing. The Intel TDP specification is a recommended design point and is not
representative of the absolute maximum power the processor may dissipate under worst case conditions.
2. Not 100% tested. These power specifications are determined by characterization of the processor currents
at higher temperatures and extrapolating the values for the temperature indicated.
3. TJ is measured with the on-die thermal diode.
4. TDP (max) is defined as the worst case power dissipated by the processor while executing a worst case
instruction mix, operating at typical Vcc and under normal operating conditions.
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Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
6.1
Thermal Diode
The ULV Intel® Celeron® processor has an on-die thermal diode that should be used to monitor the
die temperature (TJ). A thermal sensor located on the motherboard, or a stand-alone measurement
kit, should monitor the die temperature of the processor for thermal management or
instrumentation purposes. Tables 42 and 43 provide the diode interface and specifications.
Note: The reading of the thermal sensor connected to the thermal diode will not necessarily reflect the
temperature of the hottest location on the die. This is due to inaccuracies in the thermal sensor, on-
die temperature gradients between the location of the thermal diode and the hottest location on the
die, and time based variations in the die temperature measurement. Time based variations may
occur when the sampling rate of the thermal diode (by the thermal sensor) is slower than the rate at
which the TJ temperature may change.
Table 42. Thermal Diode Interface
Signal Name
Pin/Ball Number
Signal Description
THERMDA
THERMDC
AF13
AF14
Thermal diode anode
Thermal diode cathode
Table 43. Thermal Diode Specifications
Symbol
Parameter
Min
Typ
Max
Unit
Notes
n
n
Diode Ideality Factor (5-150 µA)
Diode Ideality Factor (5-300 µA)
1.0011
1.0003
1.0067
1.0091
1.0122
1.0178
1, 2, 3, 4, 6
1, 2, 3, 5, 6
NOTES:
1. Intel does not support or recommend operation of the thermal diode under reverse bias. Intel does not
support or recommend operation of the thermal diode when the processor power supplies are not within
their specified tolerance range.
2. Characterized at 100° C.
3. Not 100% tested. Specified by design/characterization.
4. Specified for Forward Bias Current = 5 µA (min) and 150 µA (max).
5. Specified for Forward Bias Current = 5 µA (min) and 300 µA (max).
6. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode
equation: Where Is = saturation current, q = electronic charge, Vd = voltage across the diode,
k = Boltzmann Constant, and T = absolute temperature (Kelvin).
IFW = IS ⋅ (eqVD – 1)
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Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
7.0
Processor Initialization and Configuration
7.1
Description
The ULV Intel® Celeron® processor has some configuration options that are determined by
hardware and some that are determined by software. The processor samples its hardware
configuration at reset on the active-to-inactive transition of RESET#. The P6 Family of Processors
Developer’s Manual describes these configuration options. Some of the configuration options for
the ULV Intel Celeron processor are described in the remainder of this section.
7.1.1
Quick Start Enable
Quick Start enabling is mandatory on the ULV Intel Celeron processor by strapping A15# low.
When the STPCLK# signal is asserted it will enter the Quick Start state when A15# is sampled
active on the RESET# signal’s active-to-inactive transition. The Quick Start state supports snoops
from the bus priority device but it does not support symmetric master snoops nor is the latching of
interrupts supported. A “1” in bit position 5 of the Power-on Configuration register indicates that
the Quick Start state has been enabled.
7.1.2
7.1.3
System Bus Frequency
The current generation ULV Intel Celeron processor will only function with a system bus
frequency of 100 MHz.
APIC Enable
The processor APIC must be hardware enabled by pulling the PICD[1:0] signals separately up to
1.5 V and supplying an active PICCLK to the processor. Software may be used to disable the APIC
if it is not being used, after PICD[1:0] are sampled high when RESET# is deasserted and the
processor has started executing instructions.
7.2
Clock Frequencies and Ratios
The ULV Intel Celeron processor uses a clock design in which the bus clock is multiplied by a ratio
to produce the processor’s internal (or core) clock. The ratio used is programmed into the processor
during manufacturing. The bus ratio programmed into the processor is visible in bit positions 22 to
25 and 27 of the Power-on Configuration register. Table 23 shows the 5-bit codes in the Power-on
Configuration register and their corresponding bus ratios.
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Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
8.0
Processor Interface
8.1
Alphabetical Signal Reference
8.1.1
A[35:3]# (I/O – AGTL)
The A[35:3]# (Address) signals define a 236-byte physical memory address space. When ADS# is
active, these signals transmit the address of a transaction; when ADS# is inactive, these signals
transmit transaction information. These signals must be connected to the appropriate pins/balls of
both agents on the system bus. The A[35:24]# signals are protected with the AP1# parity signal,
and the A[23:3]# signals are protected with the AP0# parity signal.
On the active-to-inactive transition of RESET#, each processor bus agent samples A[35:3]# signals
to determine its power-on configuration. See P6 Family of Processors Developer’s Manual for
details.
8.1.2
8.1.3
A20M# (I - 1.5V Tolerant)
If the A20M# (Address-20 Mask) input signal is asserted, the processor masks physical address bit
20 (A20#) before looking up a line in any internal cache and before driving a read/write transaction
on the bus. Asserting A20M# emulates the 8086 processor's address wrap-around at the 1-Mbyte
boundary. Assertion of A20M# is only supported in Real mode.
ADS# (I/O - AGTL)
The ADS# (Address Strobe) signal is asserted to indicate the validity of a transaction address on
the A[35:3]# signals. Both bus agents observe the ADS# activation to begin parity checking,
protocol checking, address decode, internal snoop or deferred reply ID match operations associated
with the new transaction. This signal must be connected to the appropriate pins/balls on both agents
on the system bus.
8.1.4
AERR# (I/O - AGTL)
The AERR# (Address Parity Error) signal is observed and driven by both system bus agents, and if
used, must be connected to the appropriate pins/balls of both agents on the system bus. AERR#
observation is optionally enabled during power-on configuration; if enabled, a valid assertion of
AERR# aborts the current transaction.
If AERR# observation is disabled during power-on configuration, a central agent may handle an
assertion of AERR# as appropriate to the error handling architecture of the system.
8.1.5
AP[1:0]# (I/O - AGTL)
The AP[1:0]# (Address Parity) signals are driven by the request initiator along with ADS#,
A[35:3]#, REQ[4:0]# and RP#. AP1# covers A[35:24]#. AP0# covers A[23:3]#. A correct parity
signal is high if an even number of covered signals is low and low if an odd number of covered
signals are low. This allows parity to be high when all the covered signals are high. AP[1:0]#
should be connected to the appropriate pins/balls on both agents on the system bus.
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Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
8.1.6
BCLK, BCLK# (I)
The BCLK and BCLK# signals determines the system bus frequency.
On systems with Differential Clocking, both system bus agents must receive these signals to drive
their outputs and latch their inputs on the BCLK rising edge and BCLK# falling edge. All external
timing parameters are specified with respect to the crossing point of the BCLK rising edge and
BCLK# falling edge.
On systems with Single Ended Clocking, both system bus agents must receive the BCLK signal to
drive their outputs and latch their inputs on the BCLK rising edge. All external timing parameters
are specified with respect to the BCLK signal. The BCLK# signal functions as the CLKREF input.
8.1.7
BERR# (I/O - AGTL)
The BERR# (Bus Error) signal is asserted to indicate an unrecoverable error without a bus protocol
violation. It may be driven by either system bus agent and must be connected to the appropriate
pins/balls of both agents, if used. However, the ULV Intel® Celeron® processors do not observe
assertions of the BERR# signal.
BERR# assertion conditions are defined by the system configuration. Configuration options enable
the BERR# driver as follows:
• Enabled or disabled
• Asserted optionally for internal errors along with IERR#
• Asserted optionally by the request initiator of a bus transaction after it observes an error
• Asserted by any bus agent when it observes an error in a bus transaction
8.1.8
BINIT# (I/O - AGTL)
The BINIT# (Bus Initialization) signal may be observed and driven by both system bus agents and
must be connected to the appropriate pins/balls of both agents, if used. If the BINIT# driver is
enabled during the power-on configuration, BINIT# is asserted to signal any bus condition that
prevents reliable future information.
If BINIT# is enabled during power-on configuration, and BINIT# is sampled asserted, all bus state
machines are reset and any data which was in transit is lost. All agents reset their rotating ID for
bus arbitration to the state after reset, and internal count information is lost. The L1 and L2 caches
are not affected.
If BINIT# is disabled during power-on configuration, a central agent may handle an assertion of
BINIT# as appropriate to the Machine Check Architecture (MCA) of the system.
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Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
8.1.9
BNR# (I/O - AGTL)
The BNR# (Block Next Request) signal is used to assert a bus stall by any bus agent that is unable
to accept new bus transactions. During a bus stall, the current bus owner cannot issue any new
transactions.
Since multiple agents may need to request a bus stall simultaneously, BNR# is a wired-OR signal
that must be connected to the appropriate pins/balls of both agents on the system bus. In order to
avoid wire-OR glitches associated with simultaneous edge transitions driven by multiple drivers,
BNR# is activated on specific clock edges and sampled on specific clock edges.
8.1.10
8.1.11
BP[3:2]# (I/O - AGTL)
The BP[3:2]# (Breakpoint) signals are the System Support group Breakpoint signals. They are
outputs from the processor that indicate the status of breakpoints.
BPM[1:0]# (I/O - AGTL)
The BPM[1:0]# (Breakpoint Monitor) signals are breakpoint and performance monitor signals.
They are outputs from the processor that indicate the status of breakpoints and programmable
counters used for monitoring processor performance.
8.1.12
8.1.13
BPRI# (I - AGTL)
The BPRI# (Bus Priority Request) signal is used to arbitrate for ownership of the system bus. It
must be connected to the appropriate pins/balls on both agents on the system bus. Observing
BPRI# active (as asserted by the priority agent) causes the processor to stop issuing new requests,
unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI#
asserted until all of its requests are completed and then releases the bus by deasserting BPRI#.
BREQ0# (I/O - AGTL)
The BREQ0# (Bus Request) signal is a processor Arbitration Bus signal. The processor indicates
that it wants ownership of the system bus by asserting the BREQ0# signal.
During power-up configuration, the central agent must assert the BREQ0# bus signal. The
processor samples BREQ0# on the active-to-inactive transition of RESET#. Optionally, this signal
may be grounded with a 10-Ω resistor.
8.1.14
BSEL[1:0] (O – 3.3V Tolerant)
The BSEL[1:0] (Select Processor System Bus Speed) signal is used to configure the processor for
the system bus frequency. The chipset and system clock generator also uses the BSEL signals. The
VTTPWRGD signal informs the processor to output the BSEL signals. During power up the BSEL
signals will be indeterminate for a small period of time. The chipset and clock generator should not
sample the BSEL signals until the VTTPWRGD signal is asserted. The assertion of the
VTTPWRGD signal indicates that the BSEL signals are stable and driven to a final state by the
processor. Refer to Figure 12 for the timing relationship between the BSEL and VTTPWRGD
signals.
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Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
Table 44 shows the encoding scheme for BSEL[1:0]. The only supported system bus frequency for
the ULV Intel® Celeron® processor is 100 MHz. If another frequency is used, then the processor is
not ensured to function properly.
Table 44. BSEL[1:0] Encoding
BSEL[1:0]
System Bus Frequency
01
100 MHz
8.1.15
8.1.16
CLKREF (Analog)
The CLKREF (System Bus Clock Reference) signal provides a reference voltage to define the trip
point for the BCLK signal on platforms supporting Single Ended Clocking. This signal should be
connected to a resistor divider to generate 1.25 V from the 2.5-V supply. A minimum of 1-µF
decoupling capacitance is recommended on CLKREF. On systems with Differential Clocking, the
CLKREF pin functions as the BCLK# input.
CMOSREF (Analog)
The CMOSREF (CMOS Reference Voltage) signal provides a DC level reference voltage for the
CMOS input buffers. CMOSREF must be generated from a stable 1.5V supply (815 chipset
family), 2.5 V (440MX chipset family) and must meet the VCMOSREF specification. The same
1.5 V (815 chipset family) or 2.5 V (440MX chipset family) supply should be used to power the
chipset CMOS I/O buffers that drive the CMOS signals. The Thevenin equivalent impedance of the
VCMOSREF generation circuits must be less than 0.5 K Ω/1 K Ω (i.e., top resistor 500 Ω, bottom
resistor 1 K Ω) for the Intel 815 Chipset family. The Thevenin equivalent impedance of the
VCMOSREF generation circuits must be less than 0.75 K Ω/0.5 K Ω (i.e., top resistor 750 Ω,
bottom resistor 500 Ω) for the Intel 440MX chipset family.
8.1.17
8.1.18
D[63:0]# (I/O - AGTL)
The D[63:0]# (Data) signals are the data signals. These signals provide a 64-bit data path between
both system bus agents, and must be connected to the appropriate pins/balls on both agents. The
data driver asserts DRDY# to indicate a valid data transfer.
DBSY# (I/O - AGTL)
The DBSY# (Data Bus Busy) signal is asserted by the agent responsible for driving data on the
system bus to indicate that the data bus is in use. The data bus is released after DBSY# is
deasserted. This signal must be connected to the appropriate pins/balls on both agents on the
system bus.
8.1.19
DEFER# (I - AGTL)
The DEFER# (Defer) signal is asserted by an agent to indicate that the transaction cannot be
ensured in-order completion. Assertion of DEFER# is normally the responsibility of the addressed
memory agent or I/O agent. This signal must be connected to the appropriate pins/balls on both
agents on the system bus.
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Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
8.1.20
8.1.21
8.1.22
DEP[7:0]# (I/O - AGTL)
The DEP[7:0]# (Data Bus ECC Protection) signals provide optional ECC protection for the data
bus. They are driven by the agent responsible for driving D[63:0]#, and must be connected to the
appropriate pins/balls on both agents on the system bus if they are used. During power-on
configuration, DEP[7:0]# signals may be enabled for ECC checking or disabled for no checking.
DRDY# (I/O - AGTL)
The DRDY# (Data Ready) signal is asserted by the data driver on each data transfer, indicating
valid data on the data bus. In a multi-cycle data transfer, DRDY# may be deasserted to insert idle
clocks. This signal must be connected to the appropriate pins/balls on both agents on the system
bus.
DPSLP# (I - 1.5 V Tolerant)
The DPSLP# (Deep Sleep) signal, when asserted in the Quick Start state, causes the processor to
enter the Deep Sleep state. In order to return to the Quick Start state BCLK, BCLK# must be
running and the DPSLP# pin must be deasserted.
8.1.23
8.1.24
EDGCTRLP (I-Analog)
The EDGCTRLP (Edge Rate Control) signal is used to configure the edge rate of the AGTL output
buffers. Connect the signal to VSS with a 110-Ω, 1% resistor.
FERR# (O - 1.5 V Tolerant Open-drain)
The FERR# (Floating-point Error) signal is asserted when the processor detects an unmasked
floating-point error. FERR# is similar to the ERROR# signal on the Intel 387 coprocessor, and it is
included for compatibility with systems using DOS-type floating-point error reporting.
8.1.25
8.1.26
FLUSH# (I - 1.5 V Tolerant)
When the FLUSH# (Flush) input signal is asserted, the processor writes back all internal cache
lines in the Modified state and invalidates all internal cache lines. At the completion of a flush
operation, the processor issues a Flush Acknowledge transaction. The processor stops caching any
new data while the FLUSH# signal remains asserted.
On the active-to-inactive transition of RESET#, each processor bus agent samples FLUSH# to
determine its power-on configuration.
HIT# (I/O - AGTL), HITM# (I/O - AGTL)
The HIT# (Snoop Hit) and HITM# (Hit Modified) signals convey transaction snoop operation
results, and must be connected to the appropriate pins/balls on both agents on the system bus.
Either bus agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall,
which may be continued by reasserting HIT# and HITM# together.
Datasheet
73
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
8.1.27
IERR# (O - 1.5 V Tolerant Open-drain)
The IERR# (Internal Error) signal is asserted by the processor as the result of an internal error.
Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the system bus. This
transaction may optionally be converted to an external error signal (e.g., NMI) by system logic.
The processor will keep IERR# asserted until it is handled in software or with the assertion of
RESET#, BINIT, or INIT#.
8.1.28
8.1.29
IGNNE# (I - 1.5 V Tolerant)
The IGNNE# (Ignore Numeric Error) signal is asserted to force the processor to ignore a numeric
error and continue to execute non-control floating-point instructions. If IGNNE# is deasserted, the
processor freezes on a non-control floating-point instruction if a previous instruction caused an
error. IGNNE# has no affect when the NE bit in control register 0 (CR0) is set.
INIT# (I - 1.5 V Tolerant)
The INIT# (Initialization) signal is asserted to reset integer registers inside the processor without
affecting the internal (L1 or L2) caches or the floating-point registers. The processor begins
execution at the power-on reset vector configured during power-on configuration. The processor
continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous input.
If INIT# is sampled active on RESET#'s active-to-inactive transition, then the processor executes
its built-in self-test (BIST).
8.1.30
8.1.31
INTR (I - 1.5 V Tolerant)
The INTR (Interrupt) signal indicates that an external interrupt has been generated. INTR becomes
the LINT0 signal when the APIC is enabled. The interrupt is maskable using the IF bit in the
EFLAGS register. If the IF bit is set, the processor vectors to the interrupt handler after completing
the current instruction execution. Upon recognizing the interrupt request, the processor issues a
single Interrupt Acknowledge (INTA) bus transaction. INTR must remain active until the INTA
bus transaction to ensure its recognition.
LINT[1:0] (I - 1.5 V Tolerant)
The LINT[1:0] (Local APIC Interrupt) signals must be connected to the appropriate pins/balls of
all APIC bus agents, including the processor and the system logic or I/O APIC component. When
APIC is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and
LINT1 becomes NMI, a non-maskable interrupt. INTR and NMI are backward compatible with the
same signals for the Pentium processor. Both signals are asynchronous inputs.
Both of these signals must be software configured by programming the APIC register space to be
used either as NMI/INTR or LINT[1:0] in the BIOS. If the APIC is enabled at reset, then
LINT[1:0] is the default configuration.
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Datasheet
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
8.1.32
LOCK# (I/O - AGTL)
The LOCK# (Lock) signal indicates to the system that a sequence of transactions must occur
atomically. This signal must be connected to the appropriate pins/balls on both agents on the
system bus. For a locked sequence of transactions, LOCK# is asserted from the beginning of the
first transaction through the end of the last transaction.
When the priority agent asserts BPRI# to arbitrate for bus ownership, it waits until it observes
LOCK# deasserted. This enables the processor to retain bus ownership throughout the bus locked
operation and ensure the atomicity of lock.
8.1.33
8.1.34
NCTRL (I - Analog)
The NCTRL signal provides the AGTL pull down impedance control. The processor samples this
input to determine the N-channel pull-down device strength when it is the driving agent. An
external 14 Ω (1% tolerance) pull-up resistor to VCCT is required for this signal. Refer to platform
design guide for implementation details.
NMI (I - 1.5 V Tolerant)
The NMI (Non-Maskable Interrupt) indicates that an external interrupt has been generated. NMI
becomes the LINT1 signal when the APIC is disabled. Asserting NMI causes an interrupt with an
internally supplied vector value of two. An external interrupt-acknowledge transaction is not
generated. If NMI is asserted during the execution of an NMI service routine, it remains pending
and is recognized after the IRET is executed by the NMI service routine. At most, one assertion of
NMI is held pending. NMI is rising edge sensitive.
8.1.35
8.1.36
PICCLK (I – 2.0 V Tolerant)
The PICCLK (APIC Clock) signal is an input clock to the processor and system logic or I/O APIC
that is required for operation of the processor, system logic, and I/O APIC components on the
APIC bus.
PICD[1:0] (I/O - 1.5 V Tolerant Open-drain)
The PICD[1:0] (APIC Data) signals are used for bi-directional serial message passing on the APIC
bus. They must be connected to the appropriate pins/balls of all APIC bus agents, including the
processor and the system logic or I/O APIC components. If the PICD0 signal is sampled low on the
active-to-inactive transition of the RESET# signal, then the APIC is hardware disabled. For the
ULV Intel® Celeron® processor, the APIC is required to be hardware enabled as described in
Section 7.1.3.
8.1.37
PLL1, PLL2 (Analog)
The PLL1 and PLL2 signals provide isolated analog decoupling is required for the internal PLL.
See Section 3.2.2 for a description of the analog decoupling circuit.
Datasheet
75
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
8.1.38
8.1.39
8.1.40
PRDY# (O - AGTL)
The PRDY# (Probe Ready) signal is a processor output used by debug tools to determine processor
debug readiness.
PREQ# (I - 1.5 V Tolerant)
The PREQ# (Probe Request) signal is used by debug tools to request debug operation of the
processor.
PWRGOOD (I – 1.8 V Tolerant)
PWRGOOD (Power Good) is a 1.8-V tolerant input. The processor requires this signal to be a
clean indication that clocks and the power supplies (VCC, VCCT, etc.) are stable and within their
specifications. Clean implies that the signal will remain low, (capable of sinking leakage current)
and without glitches, from the time that the power supplies are turned on, until they come within
specification. The signal will then transition monotonically to a high (1.8 V) state. Figure 12
through Figure 14 illustrate the relationship of PWRGOOD to other system signals. PWRGOOD
may be driven inactive at any time, but clocks and power must again be stable before the rising
edge of PWRGOOD. It must also meet the minimum pulse width specified in Table 25 (Section
3.6) and be followed by a 1 ms RESET# pulse.
The PWRGOOD signal, which must be supplied to the processor, is used to protect internal circuits
against voltage sequencing issues. The PWRGOOD signal should be driven high throughout
boundary scan operation.
8.1.41
8.1.42
REQ[4:0]# (I/O - AGTL)
The REQ[4:0]# (Request Command) signals must be connected to the appropriate pins/balls on
both agents on the system bus. They are asserted by the current bus owner when it drives A[35:3]#
to define the currently active transaction type.
RESET# (I - AGTL)
Asserting the RESET# signal resets the processor to a known state and invalidates the L1 and L2
caches without writing back Modified (M state) lines. For a power-on type reset, RESET# must
stay active for at least 1 ms after VCC and BCLK, BCLK# have reached their proper DC and AC
specifications and after PWRGOOD has been asserted. When observing active RESET#, all bus
agents will deassert their outputs within two clocks. RESET# is the only AGTL signal that does not
have on-die AGTL termination. A 56.2 Ω 1% terminating resistor connected to VCCT is required.
A number of bus signals are sampled at the active-to-inactive transition of RESET# for the power-
on configuration. The configuration options are described in Section 4.0 and in the P6 Family of
Processors Developer’s Manual.
Unless its outputs are tri-stated during power-on configuration, after an active-to-inactive transition
of RESET#, the processor optionally executes its built-in self-test (BIST) and begins program
execution at reset-vector 000FFFF0H or FFFFFFF0H. RESET# must be connected to the
appropriate pins/balls on both agents on the system bus.
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Datasheet
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
8.1.43
RP# (I/O - AGTL)
The RP# (Request Parity) signal is driven by the request initiator and provides parity protection on
ADS# and REQ[4:0]#. RP# should be connected to the appropriate pins/balls on both agents on the
system bus.
A correct parity signal is high if an even number of covered signals is low and low if an odd
number of covered signals are low. This definition allows parity to be high when all covered
signals are high.
8.1.44
8.1.45
RS[2:0]# (I/O - AGTL)
The RS[2:0]# (Response Status) signals are driven by the response agent (the agent responsible for
completion of the current transaction) and must be connected to the appropriate pins/balls on both
agents on the system bus.
RSP# (I - AGTL)
The RSP# (Response Parity) signal is driven by the response agent (the agent responsible for
completion of the current transaction) during assertion of RS[2:0]#. RSP# provides parity
protection for RS[2:0]#. RSP# should be connected to the appropriate pins/balls on both agents on
the system bus.
A correct parity signal is high if an even number of covered signals are low, and it is low if an odd
number of covered signals are low. During Idle state of RS[2:0]# (RS[2:0]#=000), RSP# is also
high since it is not driven by any agent ensuring correct parity.
8.1.46
8.1.47
RTTIMPEDP (I-Analog)
The RTTIMPEDP (RTT Impedance/PMOS) signal is used to configure the on-die AGTL
termination. Connect the RTTIMPEDP signal to VSS with a 56.2-Ω, 1% resistor.
SMI# (I - 1.5 V Tolerant)
The SMI# (System Management Interrupt) is asserted asynchronously by system logic. On
accepting a System Management Interrupt, the processor saves the current state and enters System
Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins
program execution from the SMM handler.
8.1.48
STPCLK# (I - 1.5 V Tolerant)
The STPCLK# (Stop Clock) signal, when asserted, causes the processor to enter a low-power
Quick Start state. The processor issues a Stop Grant Acknowledge special transaction and stops
providing internal clock signals to all units except the bus and APIC units. The processor continues
to snoop bus transactions and service interrupts while in the Quick Start state. When STPCLK# is
deasserted and other conditions in are met, the processor restarts its internal clock to all units and
resumes execution. The assertion of STPCLK# has no affect on the bus clock.
Datasheet
77
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
8.1.49
8.1.50
8.1.51
8.1.52
8.1.53
8.1.54
TCK (I - 1.5 V Tolerant)
The TCK (Test Clock) signal provides the clock input for the test bus (also known as the test access
port).
TDI (I - 1.5 V Tolerant)
The TDI (Test Data In) signal transfers serial test data to the processor. TDI provides the serial
input needed for JTAG support.
TDO (O - 1.5 V Tolerant Open-drain)
The TDO (Test Data Out) signal transfers serial test data from the processor. TDO provides the
serial output needed for JTAG support.
TESTHI[2:1] (I - 1.25 V Tolerant)
The TESTHI[2:1] (Test input High) signals are used during processor test and need to be pulled
high during normal operation.
TESTLO[2:1] (I - 1.5 V Tolerant)
The TESTLO[2:1] (Test input Low) signals are used during processor test and needs to be pulled to
ground during normal operation.
THERMDA, THERMDC (Analog)
The THERMDA (Thermal Diode Anode) and THERMDC (Thermal Diode Cathode) signals
connect to the anode and cathode of the on-die thermal diode.
8.1.55
8.1.56
TMS (I - 1.5 V Tolerant)
The TMS (Test Mode Select) signal is a JTAG support signal used by debug tools.
TRDY# (I/O - AGTL)
The TRDY# (Target Ready) signal is asserted by the target to indicate that the target is ready to
receive write or implicit write-back data transfer. TRDY# must be connected to the appropriate
pins/balls on both agents on the system bus.
8.1.57
TRST# (I - 1.5 V Tolerant)
The TRST# (Test Reset) signal resets the Test Access Port (TAP) logic. The ULV Intel Celeron
processors do not self-reset during power on; therefore, it is necessary to drive this signal low
during power-on reset.
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Datasheet
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
8.1.58
8.1.59
VID[4:0] (O – Open-drain)
The VID[4:0] (Voltage ID) pins/balls may be used to support automatic selection of power supply
voltages. Refer to Section 3.2.4 for details.
V
(Analog)
REF
The VREF (AGTL Reference Voltage) signal provides a DC level reference voltage for the AGTL
input buffers. A voltage divider should be used to divide VCCT by 2/3. Resistor values of 1.00 kΩ
and 2.00 kΩ are recommended. Decouple the VREF signal with three 0.1-µF high-frequency
capacitors close to the processor.
8.1.60
VTTPWRGD (I – 1.25 V)
The VTTPWRGD signal informs the processor to output the VID signals. During power up, the
VID signals will be in an indeterminate state for a small period of time. The voltage regulator
should not sample and/or latch the VID signals until the VTTPWRGD signal is asserted. The
assertion of the VTTPWRGD signal indicates that the VID signals are stable and are driven to the
final state by the processor. Refer to Figure 12 for the power up sequence. (Also see Section 4.3.1.)
8.2
Signal Summaries
Table 45. Input Signals (Sheet 1 of 2)
Name
A20M#
Active Level
Low
Clock
Signal Group
Qualified
Asynch
—
CMOS
System Bus
System Bus
System Bus
System Bus
CMOS
Always
Always
BCLK
BCLK#
BPRI#
High
Low
Low
Low
Low
Low
Low
High
High
High
High
High
Low
High
Low
Low
Low
—
Always
BCLK
BCLK
Asynch
Asynch
Asynch
Asynch
Asynch
Asynch
Asynch
—
Always
DEFER#
FLUSH#
IGNNE#
INIT#
Always
Always
CMOS
Always
System Bus
CMOS
Always
INTR
APIC disabled mode
APIC enabled mode
APIC disabled mode
LINT[1:0]
NMI
APIC
CMOS
NCTRL
PICCLK
PREQ#
PWRGOOD
RESET#
RSP#
APIC
Always
Always
Always
Always
Always
Always
Asynch
Asynch
BCLK
BCLK
Asynch
Implementation
Implementation
System Bus
System Bus
CMOS
SMI#
Datasheet
79
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
Table 45. Input Signals (Sheet 2 of 2)
Name
Active Level
Clock
Signal Group
Qualified
STPCLK#
TCK
Low
Asynch
—
Implementation
JTAG
Always
High
TDI
TCK
JTAG
TMS
TCK
JTAG
TRST#
VTTPWRGD
Low
Asynch
Asynch
JTAG
High
Power/Other
Table 46. Output Signals
Name
Active Level
Clock
Signal Group
BSEL[1:0]
FERR#
IERR#
High
Low
Low
Low
High
High
Asynch
Asynch
Asynch
BCLK
Open-drain
Open-drain
Open-drain
Implementation
JTAG
PRDY#
TDO
TCK
VID[4:0]
Asynch
Power/Other
Table 47. Input/Output Signals (Single Driver)
Name
Active Level
Clock
Signal Group
Qualified
A[35:3]#
ADS#
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
System Bus
System Bus
System Bus
System Bus
System Bus
System Bus
System Bus
System Bus
System Bus
System Bus
System Bus
System Bus
System Bus
System Bus
System Bus
ADS#, ADS#+1
Always
AP[1:0]#
BREQ0#
BP[3:2]#
BPM[1:0]#
D[63:0]#
DBSY#
ADS#, ADS#+1
Always
Always
Always
DRDY#
Always
DEP[7:0]#
DRDY#
LOCK#
DRDY#
Always
Always
REQ[4:0]#
RP#
ADS#, ADS#+1
ADS#, ADS#+1
Always
RS[2:0]#
TRDY#
Response phase
80
Datasheet
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
Table 48. Input/Output Signals (Multiple Driver)
Name
Active Level
Clock
Signal Group
Qualified
AERR#
BERR#
BINIT#
BNR#
Low
Low
Low
Low
Low
Low
High
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
PICCLK
System Bus
System Bus
System Bus
System Bus
System Bus
System Bus
APIC
ADS#+3
Always
Always
Always
Always
Always
Always
HIT#
HITM#
PICD[1:0]
Datasheet
81
Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
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