272420-007 [INTEL]
Intel386 EX Embedded Microprocessor; 英特尔386 EX嵌入式微处理器
| 型号： | 272420-007 |
| 厂家： | 
INTEL |
| 描述： | Intel386 EX Embedded Microprocessor |
| 文件： | 总56页 (文件大小：690K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Intel386™ EX Embedded
Microprocessor
Datasheet
Product Features
■ Static Intel386™ CPU Core
—Low Power Consumption
—Operating Power Supply
EXTB: 2.7 V to 3.6 V
■ Extended Temperature Range
■ Integrated Memory Management Unit
—Virtual Memory Support
—Optional On-chip Paging
—4 Levels of Hardware-enforced
Protection
—MMU Fully Compatible with MMUs of
the 80286 and Intel386 DX Processors
EXTC: 4.5 V to 5.5 V
—Operating Frequency
20 MHz EXTB at 2.7 V to 3.6 V
25 MHz EXTB at 3.0 V to 3.6 V;
25/33 MHz EXTC at 4.5 V to 5.5 V
■ Virtual 8086 Mode Allows Execution of
8086 Software in a Protected and Paged
System
■ Large Uniform Address Space
—64 Megabyte Physical
■ Transparent Power-management System
Architecture
—Intel System Management Mode
Architecture Extension for Truly
Compatible Systems
—Power Management Transparent to
Operating Systems and Application
Programs
—64 Terabyte Virtual
—4 Gigabyte Maximum Segment Size
■ On-chip Debugging Support Including
Breakpoint Registers
—Programmable Power-management
Modes
■ Complete System Development Support
■ High Speed CHMOS Technology
■ Two Package Types
■ Powerdown Mode
—Clock Stopping at Any Time
—Only 10–20 µA Typical CPU Sink
Current
—132-pin Plastic Quad Flatpack
—144-pin Thin Quad Flatpack
■ Integrated Peripheral Functions
—Clock and Power Management Unit
—Chip-select Unit
■ Full 32-bit Internal Architecture
—8-, 16-, 32-bit Data Types
—8 General Purpose 32-bit Registers
—Interrupt Control Unit
—Timer/Counter Unit
—Watchdog Timer Unit
—Asynchronous Serial I/O Unit
—Synchronous Serial I/O Unit
—Parallel I/O Unit
—DMA and Bus Arbiter Unit
—Refresh Control Unit
■ Runs Intel386 Architecture Software in a
Cost-effective 16-bit Hardware
Environment
—Runs Same Applications and Operating
Systems as the Intel386 SX and Intel386
DX Processors
—Object Code Compatible with 8086,
80186, 80286, and Intel386 Processors
—JTAG-compliant Test-logic Unit
■ High-performance 16-bit Data Bus
—Two-clock Bus Cycles
—Address Pipelining Allows Use of
Slower, Inexpensive Memories
This datasheet applies to devices marked EXTB and EXTC. If you require information about
devices marked EXSA or EXTA, refer to a previous revision of this datasheet, order number
272420-004.
Order Number: 272420-007
October 1998
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel386™ EX Microprocessor may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation, 1998
*Third-party brands and names are the property of their respective owners.
Datasheet
Intel386™ EX Embedded Microprocessor
Contents
1.0
2.0
3.0
4.0
Introduction..................................................................................................................7
Pin Assignment...........................................................................................................8
Pin Description..........................................................................................................12
Functional Description...........................................................................................19
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
Clock Generation and Power Management Unit.................................................19
Chip-select Unit...................................................................................................19
Interrupt Control Unit...........................................................................................19
Timer/Counter Unit..............................................................................................20
Watchdog Timer Unit...........................................................................................20
Asynchronous Serial I/O Unit ..............................................................................20
Synchronous Serial I/O Unit................................................................................21
Parallel I/O Unit ...................................................................................................21
DMA and Bus Arbiter Unit ...................................................................................21
Refresh Control Unit............................................................................................22
JTAG Test-logic Unit ...........................................................................................22
5.0
6.0
Design Considerations ..........................................................................................23
5.1
5.2
5.3
Instruction Set .....................................................................................................23
Component and Revision Identifiers ...................................................................24
Package Thermal Specifications.........................................................................24
Electrical Specifications........................................................................................27
6.1
6.2
6.3
Maximum Ratings................................................................................................27
DC Specifications................................................................................................28
AC Specifications ................................................................................................30
7.0
Bus Cycle Waveforms............................................................................................47
Figures
1
2
3
4
Intel386™ EX Embedded Processor Block Diagram ............................................7
Intel386™ EX Embedded Processor 132-Pin PQFP Pin Assignment ..................8
Intel386™ EX Embedded Processor 144-Pin TQFP Pin Assignment.................10
Maximum Case Temperature vs. Frequency for Typical Power Values
(132-lead PQFP, V = 5.5 V) .............................................................................25
cc
5
6
7
Maximum Case Temperature vs. Frequency for Typical Power Values
(144-lead TQFP, V = 5.5 V nominal)................................................................25
cc
Maximum Case Temperature vs. Frequency for Typical Power Values
(132-lead PQFP, V = 3.6 V) .............................................................................26
cc
Maximum Case Temperature vs. Frequency for Typical Power Values
(144-lead TQFP, V = 3.6 V)..............................................................................26
cc
8
9
10
Drive Levels and Measurement Points for AC Specifications (EXTC) ................30
Drive Levels and Measurement Points for AC Specifications (EXTB) ................31
AC Test Loads.....................................................................................................42
Datasheet
3
Intel386™ EX Embedded Microprocessor
11
12
13
14
CLK2 Waveform..................................................................................................42
AC Timing Waveforms — Input Setup and Hold Timing .....................................43
AC Timing Waveforms — Output Valid Delay Timing.........................................44
AC Timing Waveforms — Output Valid Delay Timing for
External Late READY#........................................................................................44
AC Timing Waveforms — Output Float Delay and HLDA Valid Delay Timing ....45
AC Timing Waveforms — RESET Setup and Hold Timing and Internal Phase..45
AC Timing Waveforms — Relative Signal Timing...............................................46
AC Timing Waveforms — SSIO Timing ..............................................................46
AC Timing Waveforms — Timer/Counter Timing................................................46
Basic Internal and External Bus Cycles ..............................................................47
Nonpipelined Address Read Cycles....................................................................48
Pipelined Address Cycle .....................................................................................49
16-bit Cycles to 8-bit Devices (using BS8#)........................................................50
Basic External Bus Cycles ..................................................................................51
Nonpipelined Address Write Cycles....................................................................52
Halt Cycle............................................................................................................53
Basic Refresh Cycle............................................................................................54
Refresh Cycle During HOLD/HLDA ....................................................................55
LOCK# Signal During Address Pipelining ...........................................................56
Interrupt Acknowledge Cycles.............................................................................56
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Tables
1
2
3
4
132-Pin PQFP Pin Assignment .............................................................................9
144-Pin TQFP Pin Assignment ...........................................................................11
Pin Type and Output State Nomenclature ..........................................................12
Intel386™ EX Microprocessor Pin Descriptions .................................................13
Microprocessor Clocks Per Instruction................................................................23
5
6
Thermal Resistances (0°C/W) θ , θ ................................................................24
JA JC
7
8
9
10
11
12
5 V Intel386 EXTC Processor Maximum Ratings ...............................................27
3 V Intel386 EXTB Processor Maximum Ratings................................................27
5-Volt DC Characteristics....................................................................................28
3-Volt DC Characteristics....................................................................................29
5-Volt AC Characteristics....................................................................................32
3-Volt AC Characteristics....................................................................................37
4
Datasheet
Intel386™ EX Embedded Microprocessor
Revision History
This datasheet applies to devices marked EXTB and EXTC. If you require information about
devices marked EXSA or EXTA, refer to a previous revision of this datasheet, order number
272420-004.
Revision
Date
Description
007
10/98
The document was updated to the larger page size. All known device errata for
the datasheet have been incorporated into this new revision.
006
005
004
5/96
12/95
9/94
Corrections added.
This datasheet applied to the new EXTB and EXTC devices.
This datasheet applied to devices marked EXSA or EXTA.
Datasheet
5
Intel386™ EX Embedded Microprocessor
1.0
Introduction
The Intel386™ EXTB embedded processor operates at 20 or 25 MHz at 3 Volts nominal. The
Intel386 EXTC embedded processor operates at 25 or 33 MHz at 5 Volts. In this datasheet,
“Intel386 EX processor” refers to both the Intel386 EXTB and EXTC processors.
The Intel386 EX embedded processor is a highly integrated, 32-bit, fully static processor optimized
for embedded control applications. With a 16-bit external data bus, a 26-bit external address bus,
and Intel’s System Management Mode (SMM), the Intel386 EX microprocessor brings the vast
software library of Intel386 architecture to embedded systems. It provides the performance benefits
of 32-bit programming with the cost savings associated with 16-bit hardware systems.
Figure 1. Intel386™ EX Embedded Processor Block Diagram
Bus Interface
Unit
Chip-select
Unit
JTAG Unit
Address
Clock and Power
Management Unit
Processor Core
DRAM Refresh
Control Unit
Data
Watchdog Timer Unit
Bus Monitor
Asynchronous Serial I/O
2 channels
(16450 compatible)
Synchronous Serial I/O
1 channel, full duplex
Timer/counter Unit
3 channels
(82C54 compatible)
I/O Ports
INTR
Interrupt Control Unit
DMA Controller
2 channels
(8237A compatible)
and Bus Arbiter Unit
A2849-02
Datasheet
7
Intel386™ EX Embedded Microprocessor
2.0
Pin Assignment
Figure 2. Intel386™ EX Embedded Processor 132-Pin PQFP Pin Assignment
UCS#
1
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
FLT#
CS6#/REFRESH#
VSS
LBA#
D0
2
DSR1#/STXCLK
VSS
3
4
INT7/TMRGATE1
INT6/TMRCLK1
INT5/TMRGATE0
INT4/TMRCLK0
BUSY#/TMRGATE2
ERROR#/TMROUT2
NMI
5
D1
6
D2
7
D3
8
VCC
D4
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
D5
PEREQ/TMRCLK2
VCC
D6
D7
P3.7/COMCLK
P3.6/PWRDOWN
P3.5/INT3
D8
VCC
D9
P3.4/INT2
TOP VIEW
VSS
D10
VSS
P3.3/INT1
D11
VCC
D12
P3.2/INT0
D13
RTS1#/SSIOTX
RI1#/SSIORX
DTR1#/SRXCLK
TCK
D14
D15
TDO
TDI
P3.1/TMROUT1/INT8
P3.0/TMROUT0/INT9
SMI#
TMS
M/IO#
VCC
D/C#
W/R#
VSS
READY#
BS8#
A25
VCC
A24
VSS
A23
A22
Note:
NC = No Connection
A2212-02
8
Datasheet
Intel386™ EX Embedded Microprocessor
Table 1. 132-Pin PQFP Pin Assignment
Pin
Symbol
Pin
Symbol
RD#
Pin
Symbol
Pin
Symbol
1
UCS#
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
A22
A23
VSS
100 VSS
2
CS6#/REFRESH#
VSS
WR#
VSS
101 P1.0/DCD0#
102 P1.1/RTS0#
103 CLKOUT
3
4
LBA#
D0
BLE#
VCC
A24
VCC
5
104 P1.2/DTR0#
105 P1.3/DSR0#
106 P1.4/RI0#
107 P1.5/LOCK#
108 P1.6/HOLD
109 VCC
6
D1
BHE#
ADS#
NA#
A1
A25
SMI#
7
D2
8
D3
P3.0/TMROUT0/INT9
P3.1/TMROUT1/INT8
TCK
9
VCC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
D4
A2
D5
A3
DTR1#/SRXCLK
RI1#/SSIORX
RTS1#/SSIOTX
P3.2/INT0
110
111
112
113
114
115
116
117
118
119
RESET
D6
A4
P1.7/HLDA
DACK1#/TXD1
EOP#/CTS1#
WDTOUT
CLK2
D7
VSS
D8
VCC
Vcc
A5
VCC
D9
A6
P3.3/INT1
Vss
A7
VSS
VSS
D10
D11
A8
P3.4/INT2
DRQ0/DCD1#
DRQ1/RXD1
TRST#
A9
P3.5/INT3
D12
D13
D14
D15
TDO
TDI
A10
A11
P3.6/PWRDOWN
P3.7/COMCLK
VCC
120 SMIACT#
121 VCC
A12
A13
A14
A15
A16/CAS0
VCC
PEREQ/TMRCLK2
NMI
122 P2.0/CS0#
123 P2.1/CS1#
124 P2.2/CS2#
125 P2.3/CS3#
126 P2.4/CS4#
127 VCC
ERROR#/TMROUT2
BUSY#/TMRGATE2
INT4/TMRCLK0
INT5/TMRGATE0
INT6/TMRCLK1
INT7/TMRGATE1
VSS
TMS
M/IO#
VCC
A17/CAS1
A18/CAS2
A19
VSS
D/C#
W/R#
VSS
128 DACK0#/CS5#
129 P2.5/RXD0
130 VSS
READY#
BS8#
A20
A21
DSR1#/STXCLK
FLT#
131 P2.6/TXD0
132 P2.7/CTS0#
Datasheet
9
Intel386™ EX Embedded Microprocessor
Figure 3. Intel386™ EX Embedded Processor 144-Pin TQFP Pin Assignment
UCS#
1
108
107
106
105
104
103
102
101
100
99
VSS
CS6#/REFRESH#
VSS
LBA#
D0
2
FLT#
3
DSR1#/STXCLK
VSS
4
5
INT7/TMRGATE1
INT6/TMRCLK1
INT5/TMRGATE0
INT4/TMRCLK0
BUSY#/TMRGATE2
ERROR#/TMROUT2
NMI
D1
6
D2
7
D3
8
VCC
D4
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
VSS
D5
98
97
VSS
D6
96
PEREQ/TMRCLK2
VCC
D7
95
D8
94
P3.7/COMCLK
P3.6/PWRDOWN
P3.5/INT3
P3.4/INT2
VSS
VCC
D9
93
92
VSS
D10
91
TOP VIEW
90
D11
89
P3.3/INT1
VCC
D12
88
D13
87
P3.2/INT0
RTS1#/SSIOTX
RI1#/SSIORX
DTR1#/SRXCLK
VSS
D14
86
VSS
D15
85
84
TDO
TDI
83
82
TCK
TMS
M/IO#
VCC
D/C#
W/R#
VSS
READY#
BS8#
VSS
81
P3.1/TMROUT1/INT8
P3.0/TMROUT0/INT9
SMI#
80
79
78
A25
77
VCC
76
A24
75
VSS
74
A23
73
A22
A2213-03
10
Datasheet
Intel386™ EX Embedded Microprocessor
Table 2. 144-Pin TQFP Pin Assignment
Pin
Symbol
Pin
Symbol
RD#
Pin
Symbol
Pin
109
Symbol
1
UCS#
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
A22
A23
VSS
VSS
2
CS6#/REFRESH#
VSS
WR#
VSS
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
P1.0/DCD0#
P1.1/RTS0#
CLKOUT
P1.2/DTR0#
P1.3/DSR0#
P1.4/RI0#
P1.5/LOCK#
P1.6/HOLD
VCC
3
4
LBA#
D0
BLE#
VCC
A24
VCC
5
6
D1
BHE#
ADS#
NA#
A1
A25
SMI#
7
D2
8
D3
P3.0/TMROUT0/INT9
P3.1/TMROUT1/INT8
TCK
9
VCC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
D4
A2
VSS
VSS
VSS
RESET
D5
A3
DTR1#/SRXCLK
RI1#/SSIORX
RTS1#/SSIOTX
P3.2/INT0
VSS
D6
A4
P1.7/HLDA
DACK1#/TXD1
EOP#/CTS1#
WDTOUT
CLK2
D7
VSS
D8
VCC
VCC
A5
VCC
D9
A6
P3.3/INT1
VSS
A7
VSS
VSS
D10
D11
D12
D13
D14
VSS
A8
P3.4/INT2
DRQ0/DCD1#
DRQ1/RXD1
TRST#
A9
P3.5/INT3
A10
A11
P3.6/PWRDOWN
P3.7/COMCLK
VCC
SMIACT#
VCC
A12
VSS
PEREQ/TMRCLK2
VSS
VSS
D15
TDO
TDI
A13
A14
A15
A16/CAS0
VCC
P2.0/CS0#
P2.1/CS1#
P2.2/CS2#
P2.3/CS3#
P2.4/CS4#
VCC
NMI
ERROR#/TMROUT2
TMS
M/IO#
VCC
100 BUSY#/TMRGATE2
101 INT4/TMRCLK0
102 INT5/TMRGATE0
103 INT6/TMRCLK1
104 INT7/TMRGATE1
105 VSS
A17/CAS1
A18/CAS2
A19
VSS
D/C#
W/R#
VSS
DACK0#/CS5#
P2.5/RXD0
VSS
READY#
BS8#
VSS
A20
A21
VSS
106 DSR1#/STXCLK
107 FLT#
P2.6/TXD0
P2.7/CTS0#
VSS
108 VSS
Datasheet
11
Intel386™ EX Embedded Microprocessor
3.0
Pin Description
Table 4 lists the Intel386 EX embedded processor pin descriptions. Table 3 defines the
abbreviations used in the Type and Output States columns of Table 4.
Table 3. Pin Type and Output State Nomenclature
Symbol
Description
Pin Type
#
I
O
I/O
I/OD
ST
P
The named signal is active low.
Standard TTL input signal.
Standard CMOS output signal.
Input and output signal.
Input and open-drain output signal.
Schmitt-triggered input signal.
Power pin.
G
Ground pin.
Output State
H(1)
H(0)
H(Z)
H(Q)
H(X)
Output driven to VCC during Bus Hold
Output driven to VSS during Bus Hold
Output floats during Bus Hold
Output remains active during Bus Hold
Output retains current state during Bus Hold
R(WH)
R(WL)
R(1)
R(0)
R(Z)
Output Weakly Held at VCC during Reset
Output Weakly Held at VSS during Reset
Output driven to VCC during Reset
Output driven to VSS during Reset
Output floats during Reset
R(Q)
Output remains active during Reset
R(X)
Output retains current state during Reset
I(1)†
I(0)
I(Z)
I(Q)
I(X)
Output driven to VCC during Idle Mode
Output driven to VSS during Idle Mode
Output floats during Idle Mode
Output remains active during Idle Mode
Output retains current state during Idle Mode
P(1)
P(0)
P(Z)
P(Q)
P(X)
Output driven to VCC during Powerdown Mode
Output driven to VSS during Powerdown Mode
Output floats during Powerdown Mode
Output remains active during Powerdown Mode
Output retains current state during Powerdown Mode
†
The idle mode output states assume that no internal bus master (DMA or RCU) has control of the bus
during idle mode
12
Datasheet
Intel386™ EX Embedded Microprocessor
Table 4. Intel386™ EX Microprocessor Pin Descriptions (Sheet 1 of 6)
Symbol
Type
Output States
Name and Function
H(Z)
R(1)
I(1)
Address Bus outputs physical memory or port I/O addresses.
These signals are valid when ADS# is active and remain valid
until the next T1, T2P, or Ti. During HOLD cycles they are driven
to a high-impedance state. A18:16 are multiplexed with CAS2:0.
A25:1
O
P(1)
H(Z)
R(1)
I(1)
Address Status indicates that the processor is driving a valid
bus-cycle definition and address (W/R#, D/C#, M/IO#, A25:1,
BHE#, BLE#) onto its pins.
ADS#
BHE#
O
O
P(1)
H(Z)
R(0)
I(X)
Byte High Enable indicates that the processor is transferring a
high data byte.
P(0)
H(Z)
R(0)
I(X)
Byte Low Enable indicates that the processor is transferring a
low data byte.
BLE#
O
I
P(1)
Bus Size indicates that an 8-bit device is currently being
addressed.
BS8#
Busy indicates that the math coprocessor is busy. If BUSY# is
sampled LOW at the falling edge of RESET, the processor
performs an internal self test. BUSY# is multiplexed with
TMRGATE2 and has a temporary weak pull-up resistor.
BUSY#
I
H(Z)
R(1)
I(1)
Cascade Address carries the slave address information from
the 8259A master interrupt module during interrupt acknowledge
bus cycles. CAS2:0 are multiplexed with A18:16.
CAS2:0
CLK2
O
ST
O
P(1)
Clock Input is connected to an external clock that provides the
fundamental timing for the device.
H(Q)
R(Q)
I(Q)
CLKOUT
CLKOUT is a PH1P clock output.
P(0)
Serial Communications Baud Clock is an alternate clock
source for the asynchronous serial ports. COMCLK is
multiplexed with P3.7 and has a temporary weak pull-down
resistor.
COMCLK
CS4:0#
CS6:5#
I
H(1)
R(WH)
I(Q)
Chip-selects are activated when the address of a memory or I/O
bus cycle is within the address region programmed by the user.
They are multiplexed as follows: CS6# with REFRESH#, CS5#
with DACK0#, and CS4:0# with P2.4:0.
O
O
P(X)
H(1)
R(1)
I(Q)
Chip-selects are activated when the address of a memory or I/O
bus cycle is within the address region programmed by the user.
They are multiplexed as follows: CS6# with REFRESH#, CS5#
with DACK0#, and CS4:0# with P2.4:0.
P(X)
Clear to Send SIO1 and SIO0 prevent the transmission of data
to the asynchronous serial port’s RXD1 and RXD0 pins,
respectively. CTS1# is multiplexed with EOP#, and CTS0# is
multiplexed with P2.7. CTS1# requires an external pull-up
resistor. Both have temporary weak pull-up resistors.
CTS1:0#
I
NOTES:
1. X if clock source is internal; Q if clock source is external
2. Q if JTAG unit is shifting out data, Z if it is not
Datasheet
13
Intel386™ EX Embedded Microprocessor
Table 4. Intel386™ EX Microprocessor Pin Descriptions (Sheet 2 of 6)
Symbol
Type
Output States
Name and Function
Data Bus inputs data during memory read, I/O read, and
interrupt acknowledge cycles and outputs data during memory
and I/O write cycles. During writes, this bus is driven during
phase 2 of T1 and remains active until phase 2 of the next T1,
T1P, or Ti. During reads, data is latched on the falling edge of
phase 2.
H(Z)
R(Z)
P(Z)
D15:0
I/O
H(1)
R(1)
I(Q)
DMA Acknowledge 1 and 0 signal to an external device that the
processor has acknowledged the corresponding DMA request
and is relinquishing the bus. DACK1# is multiplexed with TXD1,
and DACK0# is multiplexed with CS5#.
DACK1:0#
D/C#
O
O
P(X)
H(Z)
R(1)
I(0)
Data/Control indicates whether the current bus cycle is a data
cycle (memory or I/O read or write) or a control cycle (interrupt
acknowledge, halt, or code fetch).
P(0)
Data Carrier Detect SIO1 and SIO0 indicate that the modem or
data set has detected the corresponding asynchronous serial
channel’s data carrier. DCD1# is multiplexed with DRQ0, and
DCD0# is multiplexed with P1.0 and has a temporary weak pull-
up resistor.
DCD1:0
I
DMA External Request 1 and 0 indicate that a peripheral
requires DMA service. DRQ1 is multiplexed with RXD1, and
DRQ0 is multiplexed with DCD1#.
DRQ1:0
I
Data Set Ready SIO1 and SIO0 indicate that the modem or data
set is ready to establish a communication link with the
corresponding asynchronous serial channel. DSR1# is
multiplexed with STXCLK and has a permanent weak pull-up
resistor, and DSR0# is multiplexed with P1.3 and has a
temporary weak pull-up resistor.
DSR1:0#
DTR1:0#
I
H(X)
R(WH)
I(X)
Data Terminal Ready SIO1 and SIO0 indicate that the
corresponding asynchronous serial channel is ready to establish
a communication link with the modem or data set. DTR1# is
multiplexed with SRXCLK, and DTR0# is multiplexed with P1.2.
O
P(X)
H(Z)
R(WH)
I(Z)
End of Process indicates that the processor has reached
terminal count during a DMA transfer. An external device can
also pull this pin LOW. EOP# is multiplexed with CTS1#.
EOP#
I/OD
I
P(Z)
Error indicates that the math coprocessor has an error condition.
ERROR# is multiplexed with TMROUT2 and has a temporary
weak pull-up resistor.
ERROR#
Float forces all bidirectional and output signals except TDO to a
high-impedance state. It has a permanent weak pull-up resistor.
FLT#
I
This pin should be tied to VCC through a 3 to 7 KOhm pull-up
resistor.
H(1)
R(WL)
I(Q)
Bus Hold Acknowledge indicates that the processor has
surrendered control of its local bus to another bus master. HLDA
is multiplexed with P1.7.
HLDA
O
I
P(X)
Bus Hold Request allows another bus master to request control
of the local bus. HLDA active indicates that bus control has been
granted. HOLD is multiplexed with P1.6. It has a temporary weak
pull-down resistor.
HOLD
NOTES:
1. X if clock source is internal; Q if clock source is external
2. Q if JTAG unit is shifting out data, Z if it is not
14
Datasheet
Intel386™ EX Embedded Microprocessor
Table 4. Intel386™ EX Microprocessor Pin Descriptions (Sheet 3 of 6)
Symbol
Type
Output States
Name and Function
Interrupt Requests are maskable inputs that cause the CPU to
suspend execution of the current program and then execute an
interrupt acknowledge cycle. They are multiplexed as follows:
INT9 with TMROUT0 and P3.0, INT8 with TMROUT1 and P3.1,
INT7 with TMRGATE1, INT6 with TMRCLK1, INT5 with
TMRGATE0, INT4 with TMRCLK0, and INT3:0 with P3.5:2.
INT9, INT8, and INT3:0 have temporary weak pull-down
resistors.
INT9:0
I
H(1)
R(1)
I(Q)
Local Bus Access is asserted whenever the processor provides
the READY# signal to terminate a bus transaction. This occurs
when an internal peripheral address is accessed or when the
chip-select unit provides the READY# signal.
LBA#
O
O
O
P(X)
H(Z)
R(WH)
I(X)
Bus Lock prevents other bus masters from gaining control of the
system bus.
LOCK#
M/IO#
LOCK# is multiplexed with P1.5.
P(X)
H(Z)
R(0)
I(1)
Memory/IO Indicates whether the current bus cycle is a memory
cycle or an I/O cycle. When M/IO# is HIGH, the bus cycle is a
memory cycle; when M/IO# is LOW, the bus cycle is an I/O cycle.
P(1)
NA#
NMI
I
Next Address requests address pipelining.
Nonmaskable Interrupt Request is a non-maskable input that
causes the CPU to suspend execution of the current program
and execute an interrupt acknowledge cycle.
ST
Processor Extension Request indicates that the math
coprocessor has data to transfer to the processor. PEREQ is
multiplexed with TMRCLK2 and has a temporary weak pull-down
resistor.
PEREQ
P1.5:0
I
H(X)
R(WH)
I(X)
Port 1, Pins 7:0 are multipurpose bidirectional port pins. They
are multiplexed as follows: P1.7 with HLDA, P1.6 with HOLD,
P1.5 with LOCK#, P1.4 with RI0#, P1.3 with DSR0#, P1.2 with
DTR0#, P1.1 with RTS0#, and P1.0 with DCD0#.
I/O
I/O
I/O
I/O
I/O
P(X)
H(X)
R(WL)
I(X)
Port 1, Pins 7:0 are multipurpose bidirectional port pins. They
are multiplexed as follows: P1.7 with HLDA, P1.6 with HOLD,
P1.5 with LOCK#, P1.4 with RI0#, P1.3 with DSR0#, P1.2 with
DTR0#, P1.1 with RTS0#, and P1.0 with DCD0#.
P1.7:6
P(X)
H(X)
R(WH)
I(X)
Port 2, Pins 7:0 are multipurpose bidirectional port pins. They
are multiplexed as follows: P2.7 with CTS0#, P2.6 with TXD0,
P2.5 with RXD0, and P2.4:0 with CS4:0#.
P2.7,4:0
P2.6:5
P(X)
H(X)
R(WL)
I(X)
Port 2, Pins 7:0 are multipurpose bidirectional port pins. They
are multiplexed as follows: P2.7 with CTS0#, P2.6 with TXD0,
P2.5 with RXD0, and P2.4:0 with CS4:0#.
P(X)
H(X)
R(WL)
I(X)
Port 3, Pins 7:0 are multipurpose bidirectional port pins. They
are multiplexed as follows: P3.7 with COMCLK, P3.6 with
PWRDOWN, P3.5:2 with INT3:0, and P3.1:0 with TMROUT1:0
and INT8:9.
P3.7:0
P(X)
NOTES:
1. X if clock source is internal; Q if clock source is external
2. Q if JTAG unit is shifting out data, Z if it is not
Datasheet
15
Intel386™ EX Embedded Microprocessor
Table 4. Intel386™ EX Microprocessor Pin Descriptions (Sheet 4 of 6)
Symbol
Type
Output States
Name and Function
H(Q)
R(WL)
I(X)
Powerdown indicates that the processor is in powerdown mode.
PWRDOWN is multiplexed with P3.6.
PWRDOWN
O
P(1)
H(1)
R(1)
I(1)
RD#
O
Read Enable indicates that the current bus cycle is a read cycle.
P(1)
H(Z)
R(Z)
I(Z)
Ready indicates that the current bus transaction has completed.
An external device or an internal signal can drive READY#.
Internally, the chip-select wait-state logic can generate the ready
signal and drive the READY# pin active.
READY#
RESET
I/O
ST
O
P(Z)
Reset suspends any operation in progress and places the
processor into a known reset state.
H(1)
R(1)
I(Q)
Refresh indicates that the current bus cycle is a refresh cycle.
REFRESH# is multiplexed with CS6#.
REFRESH#
P(X)
Ring Indicator SIO1 and SIO0 indicate that the modem or data
set has received a telephone ringing signal. RI1# is multiplexed
with SSIORX, and RI0# is multiplexed with P1.4 and has a
temporary weak pull-up resistor.
RI1:0#
RTS1#
RTS0#
I
H(X)
R(WL)
I(X)
Request-to-send SIO1 and SIO0 indicate that corresponding
asynchronous serial channel is ready to exchange data with the
modem or data set. RTS1# is multiplexed with SSIOTX, and
RTS0# is multiplexed with P1.1.
O
O
P(X)
H(X)
R(WH)
I(X)
Request-to-send SIO1 and SIO0 indicate that corresponding
asynchronous serial channel is ready to exchange data with the
modem or data set. RTS1# is multiplexed with SSIOTX, and
RTS0# is multiplexed with P1.1.
P(X)
Receive Data SIO1 and SIO0 accept serial data from the
modem or data set to the corresponding asynchronous serial
channel. RXD1 is multiplexed with DRQ1, and RXD0 is
multiplexed with P2.5 and has a temporary weak pull-down
resistor.
RXD1:0
I
System Management Interrupt invokes System Management
Mode (SMM). SMI# is the highest priority external interrupt. It is
latched on its falling edge and forces the CPU into SMM upon
completion of the current instruction. SMI# is recognized on an
instruction boundary and at each iteration for repeat string
instructions. SMI# cannot interrupt LOCKed bus cycles or a
currently executing SMM. When the processor receives a
second SMI# while in SMM, it latches the second SMI# on the
SMI# falling edge. However, the processor must exit SMM by
executing a resume instruction (RSM) before it can service the
second SMI#. SMI# has a permanent weak pull-up resistor.
SMI#
ST
System Management Interrupt Active indicates that the
processor is operating in System Management Mode (SMM). It
is asserted when the processor initiates an SMM sequence and
remains asserted (LOW) until the processor executes the
resume instruction (RSM).
H(1)
R(1)
I(X)
SMIACT#
O
P(X)
NOTES:
1. X if clock source is internal; Q if clock source is external
2. Q if JTAG unit is shifting out data, Z if it is not
16
Datasheet
Intel386™ EX Embedded Microprocessor
Table 4. Intel386™ EX Microprocessor Pin Descriptions (Sheet 5 of 6)
Symbol
Type
Output States
Name and Function
H(Q)
R(WH)
SSIO Receive Clock synchronizes data being accepted by the
synchronous serial port. SRXCLK is multiplexed with DTR1#.
SRXCLK
I/O
I(Q)
P(X)/P(Q)Note 1
SSIO Receive Serial Data accepts serial data (most-significant
bit first) being sent to the synchronous serial port. SSIORX is
multiplexed with RI1#.
SSIORX
SSIOTX
I
SSIO Transmit Serial Data sends serial data (most-significant
bit first) from the synchronous serial port. SSIOTX is multiplexed
with RTS1#.
H(Q)
R(WL)
O
I(Q)
Intel does not specify a data hold time for SSIOTX. Slower
external devices may require additional hardware to properly
interface the SSIO unit.
P(X)/P(Q)Note 1
H(Q)
R(WH)
SSIO Transmit Clock synchronizes data being sent by the
synchronous serial port. STXCLK is multiplexed with DSR1.
STXCLK
I/O
I(Q)
P(X)/P(Q)Note 1
TAP (Test Access Port) Controller Clock provides the clock
input for the JTAG logic. It has a permanent weak pull-up
resistor.
TCK
TDI
I
I
TAP (Test Access Port) Controller Data Input is the serial
input for test instructions and data. It has a permanent weak pull-
up resistor.
H(Z)/H(Q)Note 2
R(Z)/R(Q)Note 2 TAP (Test Access Port) Controller Data Output is the serial
TDO
O
I
I(Z)/I(Q)Note 2
output for test instructions and data.
P(Z)/ P(Q)Note 2
Timer/Counter Clock Inputs can serve as external clock inputs
for the corresponding timer/counters. (The timer/counters can
also be clocked internally.) They are multiplexed as follows:
TMRCLK2 with PEREQ, TMRCLK1 with INT6, and TMRCLK0
with INT4. TMRCLK2 has a temporary weak pull-down resistor.
TMRCLK2:0
Timer/Counter Gate Inputs can control the corresponding
timer/counter’s counting (enable, disable, or trigger, depending
on the programmed mode). They are multiplexed as follows:
TMRGATE2 with BUSY#, TMRGATE1 with INT7, and
TMRGATE0 with INT5. TMRGATE2 has a temporary weak pull-
up resistor.
TMRGATE2:0
I
Timer/Counter Outputs provide the output of the corresponding
timer/counter. The form of the output depends on the
programmed mode. They are multiplexed as follows: TMROUT2
with ERROR#, TMROUT1 with P3.1 and INT8, and TMROUT0
with P3.0 and INT9.
H(Q)
R(WH)
TMROUT2
O
I(Q)
P(X)/P(Q)Note 1
Timer/Counter Outputs provide the output of the corresponding
timer/counter. The form of the output depends on the
programmed mode. They are multiplexed as follows: TMROUT2
with ERROR#, TMROUT1 with P3.1 and INT8, and TMROUT0
with P3.0 and INT9.
H(Q)
R(WL)
TMROUT1:0
O
I
I(Q)
P(X)/P(Q)Note 1
TAP (Test Access Port) Controller Mode Select controls the
sequence of the TAP controller’s states. It has a permanent
weak pull-up resistor.
TMS
NOTES:
1. X if clock source is internal; Q if clock source is external
2. Q if JTAG unit is shifting out data, Z if it is not
Datasheet
17
Intel386™ EX Embedded Microprocessor
Table 4. Intel386™ EX Microprocessor Pin Descriptions (Sheet 6 of 6)
Symbol
Type
Output States
Name and Function
TAP (Test Access Port) Controller Reset resets the TAP
controller at power-up and each time it is activated. It has a
permanent weak pull-up resistor.
TRST#
ST
H(Q)
R(1)
Transmit Data SIO1 and SIO0 transmit serial data from the
individual serial channels. TXD1 is multiplexed with DACK1#,
and TXD0 is multiplexed with P2.6.
TXD1
TXD0
UCS#
O
O
O
I(Q)
P(X)/P(Q)Note 1
H(Q)
R(WL)
Transmit Data SIO1 and SIO0 transmit serial data from the
individual serial channels. TXD1 is multiplexed with DACK1#,
and TXD0 is multiplexed with P2.6.
I(Q)
P(X)/P(Q)Note 1
H(1)
R(0)
I(Q)
Upper Chip-select is activated when the address of a memory
or I/O bus cycle is within the address region programmed by the
user.
P(X)
System Power provides the nominal DC supply input. This pin is
connected externally to a VCC board plane.
VCC
P
System Ground provides the 0 V connection from which all
inputs and outputs are measured. This pin is connected
externally to a ground board plane.
VSS
G
H(Q)
R(0)
I(Q)
Watchdog Timer Output indicates that the watchdog timer has
expired.
WDTOUT
W/R#
O
O
O
P(X)
H(Z)
R(0)
I(1)
Write/Read indicates whether the current bus cycle is a write
cycle or a read cycle. When W/R# is HIGH, the bus cycle is a
write cycle; when W/R# is LOW, the bus cycle is a read cycle.
P(1)
H(1)
R(1)
I(1)
WR#
Write Enable indicates that the current bus cycle is a write cycle.
P(1)
NOTES:
1. X if clock source is internal; Q if clock source is external
2. Q if JTAG unit is shifting out data, Z if it is not
18
Datasheet
Intel386™ EX Embedded Microprocessor
4.0
Functional Description
The Intel386 EX microprocessor is a fully static, 32-bit processor optimized for embedded
applications. It features low power and low voltage capabilities, integration of many commonly
used DOS-type peripherals, and a 32-bit programming architecture compatible with the large
software base of Intel386 processors. The following sections provide an overview of the integrated
peripherals.
4.1
Clock Generation and Power Management Unit
The clock generation circuit includes a divide-by-two counter, a programmable divider for
generating a prescaled clock (PSCLK), a divide-by-two counter for generating baud-rate clock
inputs, and Reset circuitry. The CLK2 input provides the fundamental timing for the chip. It is
divided by two internally to generate a 50% duty cycle Phase1 (PH1) and Phase 2 (PH2) for the
core and integrated peripherals. For power management, separate clocks are routed to the core
(PH1C/PH2C) and the peripheral modules (PH1P/PH2P). To help synchronize with external
devices, the PH1P clock is provided on the CLKOUT output pin.
Two Power Management modes are provided for flexible power-saving options. During Idle mode,
the clocks to the CPU core are frozen in a known state (PH1C low and PH2C high), while the
clocks to the peripherals continue to toggle. In Powerdown mode, the clocks to both core and
peripherals are frozen in a known state (PH1C low and PH2C high). The Bus Interface Unit will
not honor any DMA, DRAM refresh, or HOLD requests in Powerdown mode because the clocks to
the entire device are frozen.
4.2
Chip-select Unit
The Chip-Select Unit (CSU) decodes bus cycle address and status information and enables the
appropriate chip-selects. The individual chip-selects become valid in the same bus state as the
address and become inactive when either a new address is selected or the current bus cycle is
complete.
The CSU is divided into eight separate chip-select regions, each of which can enable one of the
eight chip-select pins. Each chip-select region can be mapped into memory or I/O space. A
memory-mapped chip-select region can start on any 2(n+1) Kbyte address location (where n = 0–15,
depending upon the mask register). An I/O-mapped chip-select region can start on any 2(n+1) byte
address location (where n = 0–15, depending upon the mask register). The size of the region is also
dependent upon the mask used.
4.3
Interrupt Control Unit
The Intel386 EX processor’s Interrupt Control Unit (ICU) contains two 8259A modules connected
in a cascade mode. These modules are similar to the industry-standard 8259A architecture.
The Interrupt Control Unit directly supports up to ten external (INT9:0) and up to eight internal
interrupt request signals. Pending interrupt requests are posted in the Interrupt Request Registers,
which contain one bit for each interrupt request signal. When an interrupt request is asserted, the
corresponding Interrupt Request Register bit is set. The 8259A modules can be programmed to
Datasheet
19
Intel386™ EX Embedded Microprocessor
recognize either an active-high level or a positive transition on the interrupt request lines. An
internal Priority Resolver decides which pending interrupt request (if more than one exists) is the
highest priority, based on the programmed operating mode. The Priority Resolver controls the
single interrupt request line to the CPU. The Priority Resolver’s default priority scheme places the
master interrupt controller’s IR0 as the highest priority and the master’s IR7 as the lowest. The
priority can be modified through software.
Besides the ten interrupt request inputs available to the Intel386 EX microprocessor, additional
interrupts can be supported by cascaded external 8259A modules. Up to four external 8259A units
can be cascaded to the master through connections to the INT3:0 pins. In this configuration, the
interrupt acknowledge (INTA#) signal can be decoded externally using the ADS#, D/C#, W/R#,
and M/IO# signals.
4.4
4.5
Timer/Counter Unit
The Timer/Counter Unit (TCU) on the Intel386 EX microprocessor has the same basic
functionality as the industry-standard 82C54 counter/timer. The TCU provides three independent
16-bit counters, each capable of handling clock inputs up to 8 MHz. This maximum frequency
must be considered when programming the input clocks for the counters. Six programmable timer
modes allow the counters to be used as event counters, elapsed-time indicators, programmable one-
shots, and in many other applications. All modes are software programmable.
Watchdog Timer Unit
The Watchdog Timer (WDT) unit consists of a 32-bit down-counter that decrements every PH1P
cycle, allowing up to 4.3 billion count intervals. The WDTOUT pin is driven high for sixteen
CLK2 cycles when the down-counter reaches zero (the WDT times out). The WDTOUT signal can
be used to reset the chip, to request an interrupt, or to indicate to the user that a ready-hang
situation has occurred. The down-counter can also be updated with a user-defined 32-bit reload
value under certain conditions. Alternatively, the WDT unit can be used as a bus monitor or as a
general-purpose timer.
4.6
Asynchronous Serial I/O Unit
The Intel386 EX microprocessor’s asynchronous Serial I/O (SIO) unit is a Universal
Asynchronous Receiver/ Transmitter (UART). Functionally, it is equivalent to the National
Semiconductor NS16450 and INS8250. The Intel386 EX embedded processor contains two full-
duplex, asynchronous serial channels.
The SIO unit converts serial data characters received from a peripheral device or modem to parallel
data and converts parallel data characters received from the CPU to serial data. The CPU can read
the status of the serial port at any time during its operation. The status information includes the type
and condition of the transfer operations being performed and any errors (parity, framing, overrun,
or break interrupt).
20
Datasheet
Intel386™ EX Embedded Microprocessor
Each asynchronous serial channel includes full modem control support (CTS#, RTS#, DSR#,
DTR#, RI#, and DCD#) and is completely programmable. The programmable options include
character length (5, 6, 7, or 8 bits), stop bits (1, 1.5, or 2), and parity (even, odd, forced, or none). In
addition, it contains a programmable baud-rate generator capable of clock rates from 0 to 512
Kbaud.
4.7
Synchronous Serial I/O Unit
The Synchronous Serial I/O (SSIO) unit provides for simultaneous, bidirectional communications.
It consists of a transmit channel, a receive channel, and a dedicated baud-rate generator. The
transmit and receive channels can be operated independently (with different clocks) to provide
non-lockstep, full-duplex communications; either channel can originate the clocking signal (Master
Mode) or receive an externally generated clocking signal (Slave Mode).
The SSIO provides numerous features for ease and flexibility of operation. With a maximum clock
input of CLK2/4 to the baud-rate generator, the SSIO can deliver a baud rate of up to 8.25 Mbits
per second with a processor clock of 33 MHz. Each channel is double buffered. The two channels
share the baud-rate generator and a multiply-by-two transmit and receive clock. The SSIO supports
16-bit serial communications with independently enabled transmit and receive functions and gated
interrupt outputs to the interrupt controller.
4.8
4.9
Parallel I/O Unit
The Intel386 EX microprocessor has three 8-bit, general-purpose I/O ports. All port pins are
bidirectional, with TTL-level inputs and CMOS-level outputs. All pins have both a standard
operating mode and a peripheral mode (a multiplexed function), and all have similar sets of control
registers located in I/O address space.
DMA and Bus Arbiter Unit
The Intel386 EX microprocessor’s DMA controller is a two-channel DMA; each channel operates
independently of the other. Within the operation of the individual channels, several different data
transfer modes are available. These modes can be combined in various configurations to provide a
very versatile DMA controller. Its feature set has enhancements beyond the 8237 DMA family;
however, it can be configured such that it can be used in an 8237-like mode. Each channel can
transfer data between any combination of memory and I/O with any combination (8 or 16 bits) of
data path widths. An internal temporary register that can disassemble or assemble data to or from
either an aligned or a nonaligned destination or source optimizes bus bandwidth.
The bus arbiter, a part of the DMA controller, works much like the priority resolving circuitry of a
DMA. It receives service requests from the two DMA channels, the external bus master, and the
DRAM Refresh Control Unit. The bus arbiter requests bus ownership from the core and resolves
priority issues among all active requests when bus mastership is granted.
Each DMA channel consists of three major components: the Requestor, the Target, and the Byte
Count. These components are identified by the contents of programmable registers that define the
memory or I/O device being serviced by the DMA. The Requestor is the device that requires and
requests service from the DMA controller. Only the Requestor is considered capable of initializing
Datasheet
21
Intel386™ EX Embedded Microprocessor
or terminating a DMA process. The Target is the device with which the Requestor wishes to
communicate. The DMA process considers the Target a slave that is incapable of controlling the
process. The Byte Count dictates the amount of data that must be transferred.
4.10
Refresh Control Unit
The Refresh Control Unit (RCU) simplifies dynamic memory controller design with its integrated
address and clock counters. Integrating the RCU into the processor allows an external DRAM
controller to use chip-selects, wait state logic, and status lines.
The Refresh Control Unit:
• Provides a programmable-interval timer
• Provides the bus arbitration logic to gain control of the bus to run refresh cycles
• Contains the logic to generate row addresses to refresh DRAM rows individually
• Contains the logic to signal the start of a refresh cycle
The RCU contains a 13-bit address counter that forms the refresh address, supporting DRAMs with
up to 13 rows of memory cells (13 refresh address bits). This includes all practical DRAM sizes for
the Intel386 EX microprocessor’s 64 Mbyte address space.
4.11
JTAG Test-logic Unit
The JTAG Test-logic Unit provides access to the device pins and to a number of other testable areas
on the device. It is fully compliant with the IEEE 1149.1 standard and thus interfaces with five
dedicated pins: TRST#, TCK, TMS, TDI, and TDO. It contains the Test Access Port (TAP) finite-
state machine, a 4-bit instruction register, a 32-bit identification register, and a single-bit bypass
register. The test-logic unit also contains the necessary logic to generate clock and control signals
for the Boundary Scan chain.
Since the test-logic unit has its own clock and reset signals, it can operate autonomously. While the
rest of the microprocessor is in Reset or Powerdown, the JTAG unit can read or write various
register chains.
22
Datasheet
Intel386™ EX Embedded Microprocessor
5.0
Design Considerations
This section describes the Intel386 EX microprocessor’s instruction set and its component and
revision identifiers.
5.1
Instruction Set
The Intel386 EX microprocessor uses the same instruction set as the Intel386 SX microprocessor
with the following exceptions.
The Intel386 EX microprocessor has one new instruction (RSM). This Resume instruction causes
the processor to exit System Management Mode (SMM). RSM requires 338 clocks per instruction
(CPI).
The Intel386 EX microprocessor requires more clock cycles than the Intel386 SX microprocessor
to execute some instructions. Table 5 lists these instructions and the Intel386 EX microprocessor
clock count. For the equivalent Intel386 SX microprocessor clock count, refer to the “Instruction
Set Clock Count Summary” table in the Intel386™ SX Microprocessor datasheet (order number
240187).
Table 5. Microprocessor Clocks Per Instruction
Clock Count (1)
Instruction
Real Address Mode
or Virtual 8086 Mode
Virtual 8086 Mode(2)
Protected Virtual Address Mode(3)
POPA
29
35
IN:
Fixed Port
Variable Port
27
28
14
15
8/29
9/29
OUT:
Fixed Port
Variable Port
27
28
14
15
8/29
9/29
INS
30
17
10/32
OUTS
31
18
11/33
REP INS
REP OUTS
HLT
31+6n (Note 4)
30+8n (Note 4)
17+7n (Note 4)
11+7n/32+6n (Note 4)
16+8n (Note 4)
10+8n/31+8n (Note 4)
7
7
MOV CR0, reg
10
10
NOTES:
1. For IN, OUT, INS, OUTS, REP INS, and REP OUTS instructions, add one clock count for each wait state
generated by the peripheral being accessed (the values in the table are for zero wait state).
2. The clock count values in this column apply if I/O permission allows I/O to the port in virtual 8086 mode. If
the I/O bit map denies permission, exception fault 13 occurs; see clock counts for the INT 3 instruction in
the “Instruction Set Clock Count Summary” table in the Intel386™ SX Microprocessor datasheet (order
number 240187).
3. When two clock counts are listed, the smaller value refers to the case where CPL ≤ IOPL and the larger
value refers to the case where CPL>IOPL. CPL is the current privilege level, and IOPL is the I/O privilege
level.
4. n = the number of times repeated.
Datasheet
23
Intel386™ EX Embedded Microprocessor
5.2
Component and Revision Identifiers
To assist users, the microprocessor holds a component identifier and revision identifier in its DX
register after reset. The upper 8 bits of DX hold the component identifier, 23H. (The lower nibble,
3H, identifies the Intel386 architecture, while the upper nibble, 2H, identifies the second member
of the Intel386 microprocessor family.)
The lower 8 bits of DX hold the revision level identifier. The revision identifier will, in general,
chronologically track those component steppings that are intended to have certain improvements or
distinction from previous steppings. The revision identifier will track that of the Intel386 CPU
whenever possible. However, the revision identifier value is not guaranteed to change with every
stepping revision or to follow a completely uniform numerical sequence, depending on the type or
intent of the revision or the manufacturing materials required to be changed. Intel has sole
discretion over these characteristics of the component. The initial revision identifier for the
Intel386 EX microprocessor is 09H.
5.3
Package Thermal Specifications
The Intel386 EX microprocessor is specified for operation with a minimum case temperature
(T
) of -40° C and a maximum case temperature (T
) dependent on power
CASE(MIN)
CASE(MAX)
dissipation (see Figures 4 through 7). The case temperature can be measured in any environment to
determine whether the microprocessor is within the specified operating range. The case
temperature should be measured at the center of the top surface opposite the pins.
An increase in the ambient temperature (T ) causes a proportional increase in the case temperature
A
(T
) and the junction temperature (T ), which is the junction temperature on the die itself. A
CASE
J
packaged device produces thermal resistance between junction and case temperatures (θ ) and
JC
between junction and ambient temperatures (θ ). The relationships between the temperature and
JA
thermal resistance parameters are expressed by these equations:
TJ = TCASE + P × θJC
TA = TJ – P × θJA
TCASE = TA + P × [θJA – θJC]
P = power dissipated as heat = VCC × ICC
A safe operating temperature can be calculated from the above equations by using the maximum
safe TJ of 120° C, the power drawn by the chip in the specific design, and the θ value from Table
JC
6. The θ value depends on the airflow (measured at the top of the chip) provided by the system
JA
ventilation, board layout, board thickness, and potentially other factors in the design of the
application. The θ values are given for reference only and are not guaranteed.
JA
Table 6. Thermal Resistances (0°C/W) θ , θ
JA JC
θJA vs. Airflow (ft/min)
Package
θJC
0
100
200
132 PQFP
144 TQFP
7
4
28
36
24
31
22
27
Figures 4 through 7 provide maximum case temperature as a function of frequency.
24
Datasheet
Intel386™ EX Embedded Microprocessor
Figure 4. Maximum Case Temperature vs. Frequency for Typical Power Values
(132-lead PQFP, VCC = 5.5 V)
113.9
114
113
112
132 Lead PQFP
112.25
111
Tc
110.7
(deg C)
110
109
108
107
107.8
16
20
25
33
Operating Frequency (MHz)
A3346-02
Figure 5. Maximum Case Temperature vs. Frequency for Typical Power Values
(144-lead TQFP, VCC = 5.5 V nominal)
116
114.9
115
114
113
112
111
110
109
108
144 Lead TQFP
113.5
112.25
Tc
(deg C)
109.8
16
20
25
33
Operating Frequency (MHz)
A3347-02
Datasheet
25
Intel386™ EX Embedded Microprocessor
Figure 6. Maximum Case Temperature vs. Frequency for Typical Power Values
(132-lead PQFP, VCC = 3.6 V)
117.5
117.5
132 Lead PQFP
117.0
117.0
116.5
Tc
(deg C)
116.5
16
20
25
Operating Frequency (MHz)
A3348-02
Figure 7. Maximum Case Temperature vs. Frequency for Typical Power Values
(144-lead TQFP, VCC = 3.6 V)
118.0
144 Lead TQFP
117.5
118.0
117.5
117.0
Tc
(deg C)
117.0
16
20
25
Operating Frequency (MHz)
A3349-01
26
Datasheet
Intel386™ EX Embedded Microprocessor
6.0
Electrical Specifications
6.1
Maximum Ratings
Warning: Stressing the device beyond the “Maximum Ratings” may cause permanent damage. These are
stress ratings only.
Table 7. 5 V Intel386 EXTC Processor Maximum Ratings
Parameter
Storage Temperature
Maximum Rating
–65°C to +150°C
–0.5 V to 6.5 V
Supply Voltage with Respect to VSS
Voltage on Other Pins
–0.5 V to VCC + 0.5 V
4.5 V to 5.5 V
VCC (Digital Supply Voltage)
TCASE (Case Temperature Under Bias)
TCASE(MIN)
TCASE(MAX)
-40°C
(see Figures 4 and 5)
FOSC (Operating Frequency)
0 MHz to 33 MHz
Table 8. 3 V Intel386 EXTB Processor Maximum Ratings
Parameter
Storage Temperature
Maximum Rating
–65°C to +150°C
–0.5 V to 4.6 V
Supply Voltage with Respect to VSS
Voltage on Other Pins
–0.5 V to VCC + 0.5 V
20 MHz — 2.7 V to 3.6 V
25 MHz — 3.0 V to 3.6 V
VCC (Digital Supply Voltage)
TCASE (Case Temperature Under Bias)
TCASE(MIN)
TCASE(MAX)
-40°C
(see Figures 6 and 7)
FOSC (Operating Frequency)
0 MHz to 25 MHz
Datasheet
27
Intel386™ EX Embedded Microprocessor
6.2
DC Specifications
Table 9. 5-Volt DC Characteristics
Symbol
Parameter
Min.
Max.
Unit
Test Condition
Input Low Voltage for all input pins
except CLK2, TRST#, RESET,
SMI#, and NMI
VIL
–0.3
0.8
V
Input High Voltage for all input pins
except CLK2, TRST#, RESET,
SMI#, and NMI
VIH
2.0
VCC + 0.3
0.8
V
Input Low Voltage for CLK2,
TRST#, RESET, SMI#, and NMI
VILC
VIHC
-0.3
V
V
Input High Voltage for CLK2,
TRST#, RESET, SMI#, and NMI
VCC-0.8 VCC+0.3
Output Low Voltage
VOL
All pins except Port 3
Port 3
0.45
0.45
V
V
I
I
OL = 8 mA
OL = 16 mA
Output High Voltage
All output pins
V
2.45
2.45
CC-0.5
V
V
V
IOH = –0.2 mA
IOH = –8 mA
VOH
All pins except Port 3
Port 3 pins (2 max)
IOH = –16 mA
VOLC
VOHC
CLKOUT
CLKOUT
0.45
V
V
IOL = 2 mA
VCC-0.5
2.45
IOH = –0.2 mA
IOH = –2 mA
±15
±15
0 ≤ VIN ≤ VCC
FLT# is not tested for ILI
ILI
Input Leakage Current
Output Leakage Current
µA
ILO
µA 0.45V ≤ VOUT ≤ VCC
320
250
mA FOSC =33 MHz
mA FOSC =25 MHz
(tested with device held in
reset, inputs held in their
inactive state)
ICC
Supply Current
110
85
mA FOSC =33 MHz
IIDLE
Idle Mode Current
mA
FOSC =25 MHz
IPD
CS
Powerdown Current
100
10
µA
Pin Capacitance (any pin to VSS
)
pF Not tested
28
Datasheet
Intel386™ EX Embedded Microprocessor
Table 10. 3-Volt DC Characteristics
Symbol
Parameter
Min.
Max.
Unit
Test Condition
Input Low Voltage for all
input pins except CLK2,
TRST#, RESET, SMI#, and
NMI
VIL
–0.3
0.8
V
Input High Voltage for all
input pins except CLK2,
TRST#, RESET, SMI#, and
NMI
VIH
2.0
V
CC + 0.3
V
V
Input Low Voltage for CLK2,
TRST#, RESET, SMI#, and
NMI
VILC
-0.3
0.8
Input High Voltage for CLK2,
TRST#, RESET, SMI#, and
NMI
VIHC
VCC-0.6
VCC+0.3
0.20
V
V
IOL = 100 µA, 2.7 V ≤ VCC ≤ 3.6 V
Output Low Voltage
(LVCMOS)
VOL
All pins except Port 3
Port 3 pins (2 max)
0.45
0.45
V
V
IOL = 4mA, 3.0 V≤VCC≤3.6 V (LVTTL)
IOL = 8mA, 3.0 V≤VCC≤3.6 V (LVTTL)
VCC-0.2
V
IOH= -100 µA, 2.7 V≤VCC≤3.6 V
(LVCMOS)
Output High Voltage
VOH
V
CC-0.65
CC-0.65
V
V
I
OH= -4mA, 3.0 V≤VCC≤3.6V (LVTTL)
All pins except Port 3
Port 3
V
IOH= -8mA, 3.0 V≤VCC≤3.6V (LVTTL)
IOL = 100 µA, 2.7 V ≤ VCC ≤ 3.6 V
OL = 1 mA, 3.0 V ≤ VCC ≤ 3.6 V
(LVTTL)
0.2
0.45
VOLC
CLKOUT
CLKOUT
V
I
IOH = -100 µA, 2.7 V ≤ VCC ≤ 3.6 V
VCC-0.2
CC-0.65
VOHC
V
IOH = -1 mA, 3.0 V ≤ VCC ≤ 3.6 V
(LVTTL)
V
±5
0 ≤ VIN ≤ VCC
FLT# is not tested for ILI
ILI
Input Leakage Current
Output Leakage Current
µA
ILO
±15
µA 0.45V ≤ VOUT ≤ VCC
140
110
mA FOSC = 25 MHz, VCC=3.6 V
mA FOSC = 20 MHz, VCC=3.6 V
ICC
Supply Current
(tested with device held in reset,
inputs held in their inactive state)
50
40
mA FOSC = 25 MHz, VCC=3.6 V
IIDLE
IPD
Idle Mode Current
mA
FOSC = 20 MHz, VCC=3.6 V
Powerdown Current
100
10
µA
Pin Capacitance (any pin to
CS
pF Not tested
VSS
)
Datasheet
29
Intel386™ EX Embedded Microprocessor
6.3
AC Specifications
Table 11 lists output delays, input setup requirements, and input hold requirements for the 5 V
EXTC processor; Table 12 is for the EXTB processor. All AC specifications are relative to the
CLK2 rising edge crossing the VCC/2 level for the EXTB, or 2.0 Volts for the EXTC.
Figures 8 and 9 show the measurement points for AC specifications for the EXTB and EXTC
processors. Inputs must be driven to the indicated voltage levels when AC specifications are
measured. Output delays are specified with minimum and maximum limits measured as shown.
The minimum delay times are hold times provided to external circuitry. Input setup and hold times
are specified as minimums, defining the smallest acceptable sampling window. Within the
sampling window, a synchronous input signal must be stable for correct operation.
Outputs ADS#, W/R#, CS5:0#, UCS#, D/C#, M/IO#, LOCK#, BHE#, BLE#, REFRESH#/CS6#,
READY#, LBA#, A25:1, HLDA and SMIACT# change only at the beginning of phase one. D15:0
(write cycles) and PWRDOWN change only at the beginning of phase two. RD# and WR# change
to their active states at the beginning of phase two. RD# changes to its inactive state (end of cycle)
at the beginning of phase one. See the Intel386™ EX Embedded Microprocessor User's Manual for
a detailed explanation of early READY# vs. late READY#.
The READY#, HOLD, BUSY#, ERROR#, PEREQ, BS8#, and D15:0 (read cycles) inputs are
sampled at the beginning of phase one. The NA#, SMI#, and NMI inputs are sampled at the
beginning of phase two.
Figure 8. Drive Levels and Measurement Points for AC Specifications (EXTC)
Tx
PH1
PH2
b
CLK2
A
B
OUTPUTS
(A25:1,BHE#
BLE#,ADS#,M/IO#
D/C#W/R#,LOCK#
HLDA, SMIACT#)
Min
Max
Valid
Valid
a
a
Output n+1
Output n
A
B
Min
Max
Valid
Valid
a
Output n
OUTPUTS
(D15:0)
a
Output n+1
C
D
3.0V
0V
INPUTS
(N/A#,INTR
NMI,SMI#)
Valid
Input
c
c
C
D
INPUTS
(READY#,HOLD
FLT#,ERROR#
BUSY#,PEREQ
D15:0,A20)
3.0V
0V
Valid
Input
c
c
LEGEND
a - VCC /2
b - 2.0V
c = 1.5V
A - Maximum Output Delay Spec
B - Minimum Output Delay Spec
C - Minimum Input Setup Spec
D - Minimum Input Hold Spec
30
Datasheet
Intel386™ EX Embedded Microprocessor
Figure 9. Drive Levels and Measurement Points for AC Specifications (EXTB)
Tx
PH1
PH2
a
CLK2
A
B
OUTPUTS
(A25:1,BHE#
BLE#,ADS#,M/IO#
D/C#W/R#,LOCK#
HLDA, SMIACT#)
Min
Max
Valid
Valid
a
a
Output n+1
Output n
A
B
Min
Max
Valid
Valid
a
Output n
OUTPUTS
(D15:0)
a
Output n+1
C
D
2.0V
0V
INPUTS
(N/A#,INTR
NMI,SMI#)
Valid
Input
b
b
C
D
INPUTS
(READY#,HOLD
FLT#,ERROR#
BUSY#,PEREQ
D15:0,A20)
2.0V
0V
Valid
Input
b
b
LEGEND
a - VCC/2
b = 1.5V
A - Maximum Output Delay Spec
B - Minimum Output Delay Spec
C - Minimum Input Setup Spec
D - Minimum Input Hold Spec
A2600-02
Datasheet
31
Intel386™ EX Embedded Microprocessor
Table 11. 5-Volt AC Characteristics (Sheet 1 of 5)
33 MHz
25 MHz
Symbol
Parameter
Test Condition
Min.
(ns)
Max.
(ns)
Min.
(ns)
Max.
(ns)
one-half CLK2 frequency
in MHz (1)
Operating Frequency
0
33
0
25
t1
CLK2 Period
15
6.25
4
20
7
t2a
t2b
t3a
t3b
t4
CLK2 High Time
(2)
CLK2 High Time
4
(2)
CLK2 Low Time
6.25
4.5
7
(2)
CLK2 Low Time
5
(2)
CLK2 Fall Time
4
7
(2)
t5
CLK2 Rise Time
4
7
(2)
t6
A25:1 Valid Delay
A25:1 Float Delay
BHE#, BLE#, LOCK# Valid Delay
SMIACT# Valid Delay
BHE#, BLE#, LOCK# Float Delay
4
4
4
4
4
21
28
21
21
28
4
4
4
4
4
24
28
24
24
28
CL = 50 pF
(3)
t7
t8
CL = 50 pF
CL = 50 pF
(3)
t8a
t9
M/IO#, D/C#, W/R#, ADS#,
REFRESH# Valid Delay
t10
4
4
21
18
4
4
24
22
CL = 50 pF
t10a
RD#, WR# Valid Delay
WR# Valid Delay for the rising
edge with respect to phase two
(external late READY#)
t10b
4
4
28
28
4
4
28
28
(6)
(3)
M/IO#, D/C#, W/R#, REFRESH#,
ADS# Float Delay
t11
t12
D15:0 Write Data Valid Delay
D15:0 Write Data Float delay
HLDA Valid Delay
4
4
23
22
18
4
4
23
22
22
CL = 50 pF
(3)
t13
t14
4
4
CL = 50 pF
t15
NA# Setup Time
5
5
t16
NA# Hold Time
3
3
t19
READY# Setup Time
BS8# Setup Time
8
9
t19a
11
11
NOTE:
1. Tested at maximum operating frequency and guaranteed by design characterization at lower operating
frequencies.
2. These are not tested. They are guaranteed by characterization.
3. Float condition occurs when maximum output current becomes less than ILO in magnitude. Float delay is not
fully tested.
4. These inputs may be asynchronous to CLK2. The setup and hold specifications are given to ensure recognition
within a specific CLK2 period.
5. These specifications are for information only and are not tested. They are intended to assist the designer in
selecting memory speeds. For each wait state in the design add two CLK2 cycles to the specification.
6. This specification assumes that READY# goes active after the rising edge of phase 2, so that WR# goes
inactive as a result of READY# falling.
7. This specification assumes that READY# goes active before the rising edge of phase 2, so that WR# goes
inactive as a result of phase 2 rising.
8. This specification applies if READY# is generated internally.
32
Datasheet
Intel386™ EX Embedded Microprocessor
Table 11. 5-Volt AC Characteristics (Sheet 2 of 5)
33 MHz
25 MHz
Symbol
Parameter
Test Condition
Min.
(ns)
Max.
(ns)
Min.
(ns)
Max.
(ns)
t20
t21
t22
t23
t24
t25
t26
t27
t27a
t28
t28a
READY#, BS8# Hold Time
D15:0 Read Setup Time
D15:0 Read Hold Time
HOLD Setup Time
HOLD Hold Time
4
7
4
8
3
5
2
6
6
6
6
4
7
4
8
3
5
3
6
6
6
6
RESET Setup Time
RESET Hold Time
NMI Setup Time
(4)
(4)
(4)
(4)
SMI# Setup Time
NMI Hold Time
SMI# Hold Time
PEREQ, ERROR#, BUSY# Setup
Time
t29
t30
6
5
6
5
(4)
(4)
PEREQ, ERROR#, BUSY# Hold
Time
t31
t32
t33
READY# Valid Delay
READY# Float Delay
LBA# Valid Delay
4
4
4
24
34
20
4
4
4
26
34
22
CL = 30 pF
24 (25 in
SMM)
t34
CS6:0#, UCS# Valid Delay
4
4
30
CL = 30 pF
CL = 30 pF
t35
t36
CLKOUT Valid Delay
2
4
9
2
4
14
18
PWRDOWN Valid Delay
15
A25:1, BHE#, BLE# Valid to WR#
Low
t41
0
0
0
0
0
0
t41a
t42
UCS#, CS6:0# Valid to WR# Low
A25:1, BHE#, BLE# Hold After
WR# High
(6)
UCS#, CS6:0# Hold after WR#
High
t42a
0
0
A25:1. BHE#, BLE# Hold After
WR# High
t42b
10
10
(7, 8)
NOTE:
1. Tested at maximum operating frequency and guaranteed by design characterization at lower operating
frequencies.
2. These are not tested. They are guaranteed by characterization.
3. Float condition occurs when maximum output current becomes less than ILO in magnitude. Float delay is not
fully tested.
4. These inputs may be asynchronous to CLK2. The setup and hold specifications are given to ensure recognition
within a specific CLK2 period.
5. These specifications are for information only and are not tested. They are intended to assist the designer in
selecting memory speeds. For each wait state in the design add two CLK2 cycles to the specification.
6. This specification assumes that READY# goes active after the rising edge of phase 2, so that WR# goes
inactive as a result of READY# falling.
7. This specification assumes that READY# goes active before the rising edge of phase 2, so that WR# goes
inactive as a result of phase 2 rising.
8. This specification applies if READY# is generated internally.
Datasheet
33
Intel386™ EX Embedded Microprocessor
Table 11. 5-Volt AC Characteristics (Sheet 3 of 5)
33 MHz
25 MHz
Symbol
Parameter
Test Condition
Min.
(ns)
Max.
(ns)
Min.
(ns)
Max.
(ns)
2CLK2
–10
2CLK2
– 10
t43
D15:0 Output Valid to WR# High
(5)
(3)
CLK2
–10
CLK2
–10
t44
D15:0 Output Hold After WR# High
CLK2
+ 10
CLK2
+ 10
t45
WR# High to D15:0 Float
WR# Pulse Width
2CLK2
–10
2CLK2
–10
t46
t47
t47a
t48
(7)
(5)
(5)
(5)
A25:1, BHE#, BLE# Valid to D15:0
Valid
4CLK2 -
28
4CLK2-
31
UCS#, CS6:0# Valid to D15-D0
Valid
4CLK2 -
31
4CLK2 -
35
3CLK2 –
25
3CLK2 –
29
RD# Low to D15:0 Input Valid
t49
t50
D15:0 Hold After RD# High
RD# High to D15:0 Float
0
0
CLK2
CLK2 (3)
A25:1, BHE#, BLE# Hold After
RD# High
t51
0
0
0
0
UCS#, CS6:0# Hold after RD#
High
t51a
t52
3CLK2
–10
3CLK2
–10
RD# Pulse Width
Synchronous Serial I/O (SSIO) Unit
STXCLK, SRXCLK Frequency
(Master Mode)
t100
CLK2/8
CLK2/8
CLK2/8 (Unit is MHz)
CLK2/8 (Unit is MHz)
STXCLK, SRXCLK Frequency
(Slave Mode)
t101
t102
t103
t104
STXCLK, SRXCLK Low Time
STXCLK, SRXCLK High Time
STXCLK Low to SSIOTX Delay
7CLK2/2
7CLK2/2
7CLK2/2
7CLK2/2
(2)
(2)
3CLK2
3CLK2
SSIORX to SRXCLK High Setup
Time
t105
0
0
(2)
t106
SSIORX from SRXCLK Hold Time 3CLK2
3CLK2
NOTE:
1. Tested at maximum operating frequency and guaranteed by design characterization at lower operating
frequencies.
2. These are not tested. They are guaranteed by characterization.
3. Float condition occurs when maximum output current becomes less than ILO in magnitude. Float delay is not
fully tested.
4. These inputs may be asynchronous to CLK2. The setup and hold specifications are given to ensure recognition
within a specific CLK2 period.
5. These specifications are for information only and are not tested. They are intended to assist the designer in
selecting memory speeds. For each wait state in the design add two CLK2 cycles to the specification.
6. This specification assumes that READY# goes active after the rising edge of phase 2, so that WR# goes
inactive as a result of READY# falling.
7. This specification assumes that READY# goes active before the rising edge of phase 2, so that WR# goes
inactive as a result of phase 2 rising.
8. This specification applies if READY# is generated internally.
34
Datasheet
Intel386™ EX Embedded Microprocessor
Table 11. 5-Volt AC Characteristics (Sheet 4 of 5)
33 MHz
25 MHz
Symbol
Parameter
Test Condition
Min.
(ns)
Max.
(ns)
Min.
(ns)
Max.
(ns)
Timer Control Unit (TCU) Inputs
t107
t108
t109
t110
t111
TMRCLKn Frequency
TMRCLKn Low
8
8
(Unit is MHz)
60
60
50
50
60
60
50
50
TMRCLKn High
TMRGATEn High Width
TMRGATEn Low Width
TMRGATEn to TMRCLK Setup
Time (external TMRCLK only)
t112
10
11
10
11
TMRGATEn to TMRCLK Hold
Time (external TMRCLK only)
t112a
Timer Control Unit (TCU) Outputs
TMRGATEn Low to TMROUT
Valid
t113
29
29
32
32
t114
TMRCLKn Low to TMROUT Valid
Interrupt Control Unit (ICU) Inputs
D7:0 Setup Time
t115
7
4
7
4
(INTA# Cycle 2)
D7:0 Hold Time
t116
(INTA# Cycle 2)
Interrupt Control Unit (ICU) Outputs
t117
DMA Unit Inputs
DREQ Setup Time
CLK2 High to CAS2:0 Valid
25
28
t118
t119
t120
15
4
15
4
(Sync Mode)
DREQ Hold Time
(Sync Mode)
(2)
(2)
DREQ Setup Time
(Async Mode)
9
9
DREQ Hold Time
(Async Mode)
t121
9
9
NOTE:
1. Tested at maximum operating frequency and guaranteed by design characterization at lower operating
frequencies.
2. These are not tested. They are guaranteed by characterization.
3. Float condition occurs when maximum output current becomes less than ILO in magnitude. Float delay is not
fully tested.
4. These inputs may be asynchronous to CLK2. The setup and hold specifications are given to ensure recognition
within a specific CLK2 period.
5. These specifications are for information only and are not tested. They are intended to assist the designer in
selecting memory speeds. For each wait state in the design add two CLK2 cycles to the specification.
6. This specification assumes that READY# goes active after the rising edge of phase 2, so that WR# goes
inactive as a result of READY# falling.
7. This specification assumes that READY# goes active before the rising edge of phase 2, so that WR# goes
inactive as a result of phase 2 rising.
8. This specification applies if READY# is generated internally.
Datasheet
35
Intel386™ EX Embedded Microprocessor
Table 11. 5-Volt AC Characteristics (Sheet 5 of 5)
33 MHz
25 MHz
Symbol
Parameter
Test Condition
Min.
(ns)
Max.
(ns)
Min.
(ns)
Max.
(ns)
EOP# Setup Time
t122
t123
t124
t125
15
15
(Sync Mode)
EOP# Hold Time
(Sync Mode)
4
9
9
4
9
9
EOP# Setup Time
(Async Mode)
EOP# Hold Time
(Async Mode)
DMA Unit Outputs
t126
t127
t128
DACK# Output Valid Delay
4
4
4
21
25
25
4
4
4
25
25
25
EOP# Active Delay
EOP# Float Delay
(3)
JTAG Test-logic Unit
t129
TCK Frequency
10
10
(Unit is MHz)
NOTE:
1. Tested at maximum operating frequency and guaranteed by design characterization at lower operating
frequencies.
2. These are not tested. They are guaranteed by characterization.
3. Float condition occurs when maximum output current becomes less than ILO in magnitude. Float delay is not
fully tested.
4. These inputs may be asynchronous to CLK2. The setup and hold specifications are given to ensure recognition
within a specific CLK2 period.
5. These specifications are for information only and are not tested. They are intended to assist the designer in
selecting memory speeds. For each wait state in the design add two CLK2 cycles to the specification.
6. This specification assumes that READY# goes active after the rising edge of phase 2, so that WR# goes
inactive as a result of READY# falling.
7. This specification assumes that READY# goes active before the rising edge of phase 2, so that WR# goes
inactive as a result of phase 2 rising.
8. This specification applies if READY# is generated internally.
36
Datasheet
Intel386™ EX Embedded Microprocessor
Table 12. 3-Volt AC Characteristics (Sheet 1 of 5)
25 MHz
3.0 V to 3.6 V
20 MHz
2.7 V to 3.6 V
Symbol
Parameter
Test Condition
Min.
(ns)
Max.
(ns)
Min.
(ns)
Max.
(ns)
one-half CLK2 frequency
in MHz(1)
Operating Frequency
0
25
0
20
t1
CLK2 Period
20
7
25
8
t2a
t2b
t3a
t3b
t4
CLK2 High Time
CLK2 High Time
CLK2 Low Time
CLK2 Low Time
CLK2 Fall Time
CLK2 Rise Time
A25:1 Valid Delay
A25:1 Float Delay
(2)
4
5
(2)
7
8
(2)
5
6
(2)
7
7
8
8
(2)
t5
(2)
t6
4
4
32
29
4
4
36
36
CL = 50 pF
(3)
t7
BHE#, BLE#, LOCK# Valid
Delay
t8
4
4
4
32
32
23
4
4
4
34
34
32
CL = 50 pF
CL = 50 pF
(3)
t8a
t9
SMIACT# Valid Delay
BHE#, BLE#, LOCK# Float
Delay
M/IO#, D/C#, W/R#, ADS#,
REFRESH# Valid Delay
t10
4
4
32
30
4
4
34
32
CL = 50 pF
t10a
RD#, WR# Valid Delay
WR# Valid Delay for the rising
edge with respect to phase
two (external late READY#)
t10b
4
4
37
30
4
4
37
34
(6)
(3)
M/IO#, D/C#, W/R#,
REFRESH#, ADS# Float
Delay
t11
t12
D15:0 Write Data Valid Delay
D15:0 Write Data Float delay
HLDA Valid Delay
4
4
31
20
30
4
4
34
28
32
CL = 50 pF
(3)
t13
t14
4
4
CL = 50 pF
t15
NA# Setup Time
9
9
t16
NA# Hold Time
12
15
NOTE:
1. Tested at maximum operating frequency and guaranteed by design characterization at lower operating
frequencies.
2. These are not tested. They are guaranteed by characterization.
3. Float condition occurs when maximum output current becomes less than ILO in magnitude. Float delay is not
fully tested.
4. These inputs may be asynchronous to CLK2. The setup and hold specifications are given to ensure
recognition within a specific CLK2 period.
5. These specifications are for information only and are not tested. They are intended to assist the designer in
selecting memory speeds. For each wait state in the design add two CLK2 cycles to the specification.
6. This specification assumes that READY# goes active after the rising edge of phase 2, so that WR# goes
inactive as a result of READY# falling.
7. This specification assumes that READY# goes active before the rising edge of phase 2, so that WR# goes
inactive as a result of phase 2 rising.
8. This specification applies if READY# is generated internally.
Datasheet
37
Intel386™ EX Embedded Microprocessor
Table 12. 3-Volt AC Characteristics (Sheet 2 of 5)
25 MHz
3.0 V to 3.6 V
20 MHz
2.7 V to 3.6 V
Symbol
Parameter
Test Condition
Min.
(ns)
Max.
(ns)
Min.
(ns)
Max.
(ns)
t19
t19a
t20
t21
t22
t23
t24
t25
t26
t27
t27a
t28
t28a
READY# Setup Time
BS8# Setup Time
READY#, BS8# Hold Time
D15:0 Read Setup Time
D15:0 Read Hold Time
HOLD Setup Time
HOLD Hold Time
15
17
4
17
19
4
9
11
6
6
17
5
22
5
RESET Setup Time
RESET Hold Time
NMI Setup Time
12
4
13
4
16
16
16
16
16
16
16
16
(4)
(4)
(4)
(4)
SMI# Setup Time
NMI Hold Time
SMI# Hold Time
PEREQ, ERROR#, BUSY#
Setup Time
t29
t30
14
5
16
5
(4)
(4)
PEREQ, ERROR#, BUSY#
Hold Time
t31
t32
t33
READY# Valid Delay
READY# Float Delay
LBA# Valid Delay
4
4
4
33
33
31
4
4
4
42
42
40
CL = 30 pF
33 (34 in
SMM)
t34
CS6:0#, UCS# Valid Delay
4
4
42
CL = 30 pF
CL = 30 pF
t35
t36
CLKOUT Valid Delay
4
4
14
26
4
4
18
29
PWRDOWN Valid Delay
A25:1, BHE#, BLE# Valid to
WR# Low
t41
0
0
0
0
0
0
UCS#, CS6:0# Valid to WR#
Low
t41a
A25:1, BHE#, BLE# Hold
After WR# High
t42
(6)
NOTE:
1. Tested at maximum operating frequency and guaranteed by design characterization at lower operating
frequencies.
2. These are not tested. They are guaranteed by characterization.
3. Float condition occurs when maximum output current becomes less than ILO in magnitude. Float delay is not
fully tested.
4. These inputs may be asynchronous to CLK2. The setup and hold specifications are given to ensure
recognition within a specific CLK2 period.
5. These specifications are for information only and are not tested. They are intended to assist the designer in
selecting memory speeds. For each wait state in the design add two CLK2 cycles to the specification.
6. This specification assumes that READY# goes active after the rising edge of phase 2, so that WR# goes
inactive as a result of READY# falling.
7. This specification assumes that READY# goes active before the rising edge of phase 2, so that WR# goes
inactive as a result of phase 2 rising.
8. This specification applies if READY# is generated internally.
38
Datasheet
Intel386™ EX Embedded Microprocessor
Table 12. 3-Volt AC Characteristics (Sheet 3 of 5)
25 MHz
3.0 V to 3.6 V
20 MHz
2.7 V to 3.6 V
Symbol
Parameter
Test Condition
Min.
(ns)
Max.
(ns)
Min.
(ns)
Max.
(ns)
UCS#, CS6:0# Hold after
WR# High
t42a
t42b
t43
0
0
A25:1. BHE#, BLE# Hold
After WR# High
10
10
(7, 8)
D15:0 Output Valid to WR#
High
2CLK2
– 10
2CLK2
– 10
(5)
D15:0 Output Hold After WR#
High
CLK2
–10
CLK2
–10
t44
CLK2
+ 10
CLK2
+10
t45
WR# High to D15:0 Float
WR# Pulse Width
(3)
2CLK2
–10
2CLK2
–10
t46
t47
t47a
t48
(7)
(5)
(5)
(5)
A25:1, BHE#, BLE# Valid to
D15:0 Valid
4CLK2-
41
4CLK2
- 45
UCS#, CS6:0# Valid to D15-
D0 Valid
4CLK2 -
42
4CLK2
- 53
3CLK2 –
39
3CLK2
– 43
RD# Low to D15:0 Input Valid
t49
t50
D15:0 Hold After RD# High
RD# High to D15:0 Float
0
0
CLK2
CLK2
(3)
A25:1, BHE#, BLE# Hold
After RD# High
t51
0
0
0
0
UCS#, CS6:0# Hold after
RD# High
t51a
t52
3CLK2
–13
3CLK2
–15
RD# Pulse Width
Synchronous Serial I/O (SSIO) Unit
STXCLK, SRXCLK
t100
CLK2/8
CLK2/8
CLK2/8 (Unit is MHz)
CLK2/8 (Unit is MHz)
(2)
Frequency (Master Mode)
STXCLK, SRXCLK
t101
Frequency (Slave Mode)
7CLK2/
2
7CLK2/
2
t102
STXCLK, SRXCLK Low Time
NOTE:
1. Tested at maximum operating frequency and guaranteed by design characterization at lower operating
frequencies.
2. These are not tested. They are guaranteed by characterization.
3. Float condition occurs when maximum output current becomes less than ILO in magnitude. Float delay is not
fully tested.
4. These inputs may be asynchronous to CLK2. The setup and hold specifications are given to ensure
recognition within a specific CLK2 period.
5. These specifications are for information only and are not tested. They are intended to assist the designer in
selecting memory speeds. For each wait state in the design add two CLK2 cycles to the specification.
6. This specification assumes that READY# goes active after the rising edge of phase 2, so that WR# goes
inactive as a result of READY# falling.
7. This specification assumes that READY# goes active before the rising edge of phase 2, so that WR# goes
inactive as a result of phase 2 rising.
8. This specification applies if READY# is generated internally.
Datasheet
39
Intel386™ EX Embedded Microprocessor
Table 12. 3-Volt AC Characteristics (Sheet 4 of 5)
25 MHz
3.0 V to 3.6 V
20 MHz
2.7 V to 3.6 V
Symbol
Parameter
Test Condition
Min.
(ns)
Max.
(ns)
Min.
(ns)
Max.
(ns)
7CLK2/
2
7CLK2/
2
t103
t104
t105
t106
STXCLK, SRXCLK High Time
(2)
(2)
STXCLK Low to SSIOTX
Delay
3CLK2
3CLK2
SSIORX to SRXCLK High
Setup Time
0
0
SSIORX from SRXCLK Hold
Time
3CLK2
3CLK2
Timer Control Unit (TCU) Inputs
t107
t108
t109
t110
t111
TMRCLKn Frequency
TMRCLKn Low
8
8
(Unit is MHz)
60
60
50
50
60
60
50
50
TMRCLKn High
TMRGATEn High Width
TMRGATEn Low Width
TMRGATEn to TMRCLK
Setup Time (external
TMRCLK only)
t112
10
19
15
19
TMRGATEn to TMRCLK Hold
Time (external TMRCLK only)
t112a
Timer Control Unit (TCU) Outputs
TMRGATEn Low to TMROUT
Valid
t113
44
48
52
52
TMRCLKn Low to TMROUT
Valid
t114
NOTE:
1. Tested at maximum operating frequency and guaranteed by design characterization at lower operating
frequencies.
2. These are not tested. They are guaranteed by characterization.
3. Float condition occurs when maximum output current becomes less than ILO in magnitude. Float delay is not
fully tested.
4. These inputs may be asynchronous to CLK2. The setup and hold specifications are given to ensure
recognition within a specific CLK2 period.
5. These specifications are for information only and are not tested. They are intended to assist the designer in
selecting memory speeds. For each wait state in the design add two CLK2 cycles to the specification.
6. This specification assumes that READY# goes active after the rising edge of phase 2, so that WR# goes
inactive as a result of READY# falling.
7. This specification assumes that READY# goes active before the rising edge of phase 2, so that WR# goes
inactive as a result of phase 2 rising.
8. This specification applies if READY# is generated internally.
40
Datasheet
Intel386™ EX Embedded Microprocessor
Table 12. 3-Volt AC Characteristics (Sheet 5 of 5)
25 MHz
3.0 V to 3.6 V
20 MHz
2.7 V to 3.6 V
Symbol
Parameter
Test Condition
Min.
(ns)
Max.
(ns)
Min.
(ns)
Max.
(ns)
Interrupt Control Unit (ICU) Inputs
D7:0 Setup Time
t115
9
6
11
6
(INTA# Cycle 2)
D7:0 Hold Time
t116
(INTA# Cycle 2)
Interrupt Control Unit (ICU) Outputs
t117
DMA Unit Inputs
DREQ Setup Time
CLK2 High to CAS2:0 Valid
36
46
t118
t119
t120
t121
t122
t123
t124
t125
19
4
21
4
(Sync Mode)
DREQ Hold Time
(Sync Mode)
(2)
(2)
DREQ Setup Time
(Async Mode)
11
11
17
4
11
11
21
4
DREQ Hold Time
(Async Mode)
EOP# Setup Time
(Sync Mode)
EOP# Hold Time
(Sync Mode)
EOP# Setup Time
(Async Mode)
11
11
11
11
EOP# Hold Time
(Async Mode)
DMA Unit Outputs
t126
t127
t128
DACK# Output Valid Delay
4
4
4
31
27
27
4
4
4
33
33
33
EOP# Active Delay
EOP# Float Delay
(3)
JTAG Test-logic Unit
t129
TCK Frequency
10
10
(Unit is MHz)
NOTE:
1. Tested at maximum operating frequency and guaranteed by design characterization at lower operating
frequencies.
2. These are not tested. They are guaranteed by characterization.
3. Float condition occurs when maximum output current becomes less than ILO in magnitude. Float delay is not
fully tested.
4. These inputs may be asynchronous to CLK2. The setup and hold specifications are given to ensure
recognition within a specific CLK2 period.
5. These specifications are for information only and are not tested. They are intended to assist the designer in
selecting memory speeds. For each wait state in the design add two CLK2 cycles to the specification.
6. This specification assumes that READY# goes active after the rising edge of phase 2, so that WR# goes
inactive as a result of READY# falling.
7. This specification assumes that READY# goes active before the rising edge of phase 2, so that WR# goes
inactive as a result of phase 2 rising.
8. This specification applies if READY# is generated internally.
Datasheet
41
Intel386™ EX Embedded Microprocessor
Figure 10. AC Test Loads
CPU Output
C
L
Figure 11. CLK2 Waveform
t
1
t
2a
t
2b
A
CLK2
B
C
t
t
5
4
t
t
3b
3a
A = Vcc – 0.8 for Vcc = 4.5 – 5.5, Vcc – 0.6 for Vcc = 2.7 – 3.6
B = Vcc/2
C = 0.8V
42
Datasheet
Intel386™ EX Embedded Microprocessor
Figure 12. AC Timing Waveforms — Input Setup and Hold Timing
TX
PH2
PH1
TX
PH2
PH1
TX
CLK2
t
t
t
t
t
t
19a, 118, 120 119, 121
t
t
t
122, 124
123, 125
t
t
19
20
READY# (Input)
BS8#
DREQ
EOP# (Input)
t
t
23
24
HOLD
t
t
116
22
115
21
t
t
D15:0
(Input)
t
t
29
30
BUSY#
ERROR#
PEREQ
t
t
16
15
NA#
t
t
28a
27a
t
t
27
28
NMI
SMI#
A2736-01
Datasheet
43
Intel386™ EX Embedded Microprocessor
Figure 13. AC Timing Waveforms — Output Valid Delay Timing
TX
PH2
PH1
TX
PH2
PH1
TX
CLK2
t
t
8, 8a
Max
Max
Max
Min
Min
Min
Valid n
Valid n+1
Valid n+1
BHE#, BLE#
LOCK#, SMIACT#
t
t
t
t
10, 31, 33
126, 127
t
t
W/R#, M/IO#, D/C#
ADS#,REFRESH#
LBA#, DACK#
Valid n
EOP# (Output)
READY# (Output)
t
t
10a, 6, 34
A25:1, CS6:0#,UCS#,
RD# Inactive
Valid n
Valid n+1
Max
t
t
, t
117, 10a 12
Min
D15:0, CAS2:0
RD#, WR# Active,
WR# Inactive
Valid n
Valid n+1
(early READY#)
HLDA
A2737-01
Figure 14. AC Timing Waveforms — Output Valid Delay Timing for
External Late READY#
T1
T1
T2
CLK2
ADS#
External
READY#
t10b
WR#
A4398-01
44
Datasheet
Intel386™ EX Embedded Microprocessor
Figure 15. AC Timing Waveforms — Output Float Delay and HLDA Valid Delay Timing
Th
TI or T1
PH2
PH1
PH2
PH1
PH2
CLK2
t
8
t
9
Max
Max
Min
Min
Min
Min
Min
BHE#, BLE#
LOCK#
(High Z)
t
t
t
32, 11
10
Max
Max
Max
W/R#, M/IO#
D/C#, ADS#
REFRESH#
(High Z)
t
READY# (Output)
t
6
7
Min Max
A25:1
D15:0
(High Z)
Max
t
t
13
12
Max
Min
Min
(High Z)
t
Also applies to data float when write
cycle is followed by read or idle.
13
t
t
14
14
Max
Min
Max
Min
HLDA
A2738-01
Figure 16. AC Timing Waveforms — RESET Setup and Hold Timing and Internal Phase
Initialization Sequence
PH2
Reset
PH2 or PH1
PH2 or PH1
PH1
CLK2
t
26
RESET
t
25
Datasheet
45
Intel386™ EX Embedded Microprocessor
Figure 17. AC Timing Waveforms — Relative Signal Timing
T1
T2
Ti
CLK2
PH2
A25:1, BLE#, BHE#
UCS#, CS6:0#
t42
t41a
t41
t42a
t46
t43
WR#
t44
t45
D15:0 (Out)
RD#
t51
t51a
t52
t48
t50
t47a
t49
t47
D15:0 (In)
A2705-01
Figure 18. AC Timing Waveforms — SSIO Timing
t100, t101
t102
t103
STXCLK
SSIOTX
t104
Valid TX Data
t100, t101
t102
t103
SRXCLK
SSIORX
t105
t106
Valid RX Data
A2712-01
Figure 19. AC Timing Waveforms — Timer/Counter Timing
t107
t108
t111
t109
TMRCLK
t112
t112a
t110
TMRGATE
TMROUT
t114
t113
46
Datasheet
Intel386™ EX Embedded Microprocessor
7.0
Bus Cycle Waveforms
Figures 20 through 30 present various bus cycles that are generated by the processor. What is
shown in the figure is the relationship of the various bus signals to CLK2. These figures along with
the information present in AC Specifications allow the user to determine critical timing analysis for
a given application.
Figure 20. Basic Internal and External Bus Cycles
Idle
Cycle 1
Cycle 2
Cycle 3
Idle
Cycle 4
Idle
Cycle
Nonpipelined Nonpipelined Nonpipelined Cycle Nonpipelined Cycle
External
(Write)
Internal
(Read)
Internal
(Write)
External
(Read)
[Late Ready]
[Early Ready]
T1
T2
T1
T2
T1
T2
Ti
T1
T2
Ti
Ti
State
CLK2
CLKOUT
A25:1, BHE#
BLE#, D/C#
M/IO#
Valid 1
Valid 2
Valid 3
Valid 4
REFRESH#
W/R#
WR#
RD#
ADS#
NA#
READY#
End Cycle 2
End Cycle 3
End Cycle 1
End Cycle 4
LBA#
BS8#
Valid 1
Valid 2
Valid 3
Out 3
Valid 4
LOCK#
In
In
Out 1
D15:0
2
4
A2486-03
Datasheet
47
Intel386™ EX Embedded Microprocessor
Figure 21. Nonpipelined Address Read Cycles
Idle
Cycle 1
Non-pipelined
External
Cycle 2
Non-pipelined
External
Idle
Ti
(Read)
(Read)
Ti
T1
T2
T1
T2
T2
CLK2
CLKOUT
BHE#, BLE#, A25:1
M/IO#, D/C#
Valid1
Valid2
REFRESH#
W/R#
WR#
RD#
ADS#
NA#
READY#
End Cycle
End Cycle
LBA#
BS8#
LOCK#
D15:0
Valid1
Valid2
In1
In2
A2487-03
48
Datasheet
Intel386™ EX Embedded Microprocessor
Figure 22. Pipelined Address Cycle
Cycle 1
Pipelined
(Write)
Cycle 2
Non-pipelined
(Read)
Cycle 3
Pipelined
(Write)
Cycle 4
Pipelined
(Read)
[Late Ready]
[Late Ready]
T1P
T2P
T2P
T1P
T2
T2P
T1P
T2i
T2P
T1P
T2
CLK2
CLKOUT
BHE#, BLE#, A25:1,
Valid2
Valid3
Valid4
M/IO#, D/C#
ADS# is asserted as
soon as the CPU has
another bus cycle to
perform, which is not
always immediately
after NA# is asserted.
W/R#
WR#
RD#
ADS#
Note ADS# is
asserted in
every T2P state.
As long as the CPU enters the T2P
state during Cycle 3, address
pipelining is maintained in Cycle 4.
NA#
Asserting NA# more
NA# could have been asserted in T1P
if desired. Assertion now is the latest
time possible to allow the CPU to enter
T2P state to maintain pipelining in cycle 3.
than once during
any cycle has no
additional effects
READY#
LBA#
BS8#
Valid 1
LOCK#
D15:0
Valid 2
Valid 3
Valid 4
In
Out
Out 1
Out 3
2
A2477-03
Datasheet
49
Intel386™ EX Embedded Microprocessor
Figure 23. 16-bit Cycles to 8-bit Devices (using BS8#)
Low Byte
Write
[Late Ready]
High Byte
Write
[Late Ready]
Low Byte
Read
High Byte
Read
Idle
Cycles
State
CLK2
T1
T2
T1
T2
T1
T2
T1
T2
Ti
Ti
CLKOUT
A25:1
M/IO#
D/C#
Valid 1
Valid 2
BLE#
BHE#
W/R#
WR#
RD#
ADS#
NA#
Must be high
READY#
BS8#
Valid 1
Valid 2
LOCK#
D15:8
D7:0
Data Out High
Data
In
Data
Data Out
Low
Data Out
High
In
Low
High
A3375-01
50
Datasheet
Intel386™ EX Embedded Microprocessor
Figure 24. Basic External Bus Cycles
Cycle 1
Cycle 2
Idle
Cycle 3
Cycle 4
Nonpipelined Nonpipelined Cycle Nonpipelined Nonpipelined
External
(Write)
External
(Read)
External
(Write)
External
(Read)
[Late Ready]
[Late Ready]
State
CLK2
T1
T2
T1
T2
Ti
T1
T2
T1
T2
CLKOUT
A25:1, BHE#
BLE#, D/C#
M/IO#
Valid 1
Valid 2
Valid 3
Valid 4
REFRESH#
W/R#
WR#
RD#
ADS#
NA#
READY#
LBA#
BS8#
LOCK#
Valid 1
Valid 2
Valid 3
Valid 4
Out 1
In 2
Out 3
In 4
D15:0
A2305-02
Datasheet
51
Intel386™ EX Embedded Microprocessor
Figure 25. Nonpipelined Address Write Cycles
Idle
Cycle 1
Nonpipelined
External
(Write)
[Late Ready]
Cycle 2
Nonpipelined
External
(Write)
[Early Ready]
Idle
Ti
Ti
T1
T2
T1
T2
T2
CLK2
CLKOUT
BHE#, BLE#, A25:1
M/IO#, D/C#
Valid1
Valid2
REFRESH#
W/R#
WR#
RD#
ADS#
NA#
READY#
End Cycle 1
End Cycle 2
LBA#
BS8#
Valid 2
LOCK#
D15:0
Valid 1
Out 1
Out 2
A2488-02
52
Datasheet
Intel386™ EX Embedded Microprocessor
Figure 26. Halt Cycle
Cycle 1
Cycle 2
Idle
Nonpipelined Nonpipelined
(Write)
(Halt)
[Late Ready]
T1
T2
T1
T2
Ti
Ti
Ti
Ti
CLK2
CLKOUT
CPU remains halted until INTR, SMI#,
NMI, or RESET is asserted.
BHE#, A1, M/IO#, W/R#
Valid 1
Valid 1
CPU responds to HOLD input
while in the HALT state.
A25:2, BLE#, D/C#
WR#
RD#
ADS#
NA#
READY#
LBA#
†
Valid 1
Valid 2
LOCK#
D15:0
Float
Undefined
Out
† HALT cycle must be acknowledged by READY# asserted. This READY# could be
generated internally or externally.
A2492-02
Datasheet
53
Intel386™ EX Embedded Microprocessor
Figure 27. Basic Refresh Cycle
Idle
Cycle 1
Nonpipelined
External
Idle
Ti
Cycle 2
Refresh
Idle
Cycle 3
Nonpipelined
External
(Write)
[Late Ready]
(Read)
Ti
T1
T2
T1
T2
T2
Ti
Ti
T1
T2
CLK2
CLKOUT
UCS#, CS6:0#,
BHE#, BLE#
M/IO#, D/C#
Valid 1
Valid 3
Valid 1
Valid 2
Valid 3
A25:1
REFRESH#
W/R#
WR#
RD#
ADS#
NA#
READY#
LBA#
Valid 1
Valid 2
Out
LOCK#
D15:0
Float
In
HOLD
HLDA
A2491-02
54
Datasheet
Intel386™ EX Embedded Microprocessor
Figure 28. Refresh Cycle During HOLD/HLDA
Idle
Ti
HOLD
Acknowledge
Idle
Ti
Idle
HOLD
Acknowledge
Cycle 1
Refresh
Th
Th
Th
T1
T2
Ti
Ti
Th
Th
CLK2
CLKOUT
Floating
Floating
BHE#, BLE#
M/IO#, D/C#
REFRESH#
A25:1
Floating
Floating
Floating
Floating
Valid 1
W/R#
WR#
RD#
Floating
Floating
Floating
Floating
ADS#
NA#
READY#
LBA#
Floating
Floating
Floating
LOCK#
D15:0
HOLD
HLDA
Due to refresh pending.
A2493-02
Datasheet
55
Intel386™ EX Embedded Microprocessor
Figure 29. LOCK# Signal During Address Pipelining
Unlocked
Bus Cycle
Locked
Bus Cycle
Locked
Bus Cycle
Unlocked
Bus Cycle
CLKOUT
Address Asserted
BLE#, BHE#, A25:1
LOCK Deasserted
LOCK#
READY#
A2489-02
Figure 30. Interrupt Acknowledge Cycles
Previous Interrupt
Idle
Interrupt
Acknowledge
Cycle 2
Idle
Acknowledge
Cycle 1
Cycle
(Four bus states)
(Internal)
(Internal)
T2
T1
T2
Ti
Ti
Ti
Ti
T1
T2
Ti
Ti
CLK2
CLKOUT
BHE#
BLE#, A25:19,
CAS2:0,A15:3, A1
M/IO#, D/C#, W/R#
A2
WR#
RD#
ADS#
READY#
LBA#
LOCK#
A2490-03
56
Datasheet
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