10M08SFM153C8 [INTEL]
Field Programmable Gate Array, PBGA153, 8 X 8 MM, 0.50 MM PITCH, MBGA-153;
| 型号： | 10M08SFM153C8 |
| 厂家： | 
INTEL |
| 描述： | Field Programmable Gate Array, PBGA153, 8 X 8 MM, 0.50 MM PITCH, MBGA-153 栅 |
| 文件： | 总14页 (文件大小：604K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MAX 10 FPGA Device Overview
2014.09.22
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M10-OVERVIEW
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MAX® 10 devices are the industry’s first single chip, non-volatile programmable logic devices (PLDs) to
integrate the optimal set of system components.
The following lists the highlights of the MAX 10 devices:
•
•
•
•
Internally stored dual images with self-configuration
Comprehensive design protection features
Integrated ADCs
Hardware to implement the Nios II 32-bit microcontroller IP
MAX 10 devices are the ideal solution for system management, I/O expansion, communication control
planes, industrial, automotive, and consumer applications.
Related Information
MAX 10 FPGA Device Datasheet
Key Advantages of MAX 10 Devices
Table 1: Key Advantages of the MAX 10 Device Family
Advantage
Simple and fast configuration
Flexibility and integration
Supporting Feature
Secure on-die configuration in less than 10 ms
•
Single device integrating PLD logic, RAM, flash memory,
digital signal processing (DSP), ADC, phase-locked loop
(PLL), and I/Os
•
•
•
Small packages available from 3 mm x 3 mm
Low power
Sleep mode — significant standby power reduction and
resume in less than 1 ms
Longer battery life — resume from full power-off in less
than 10 ms
20 years estimated life cycle
Built on TSMC's 55 nm process technology
©
2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
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M10-OVERVIEW
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Summary of MAX 10 Device Features
Advantage
Supporting Feature
High productivity design tools
•
•
•
•
Quartus® II web edition
Qsys system integration tool
DSP Builder
Nios® II Embedded Design Suite (EDS)
Summary of MAX 10 Device Features
Table 2: Summary of Features for MAX 10 Devices
Feature
Description
Technology
Packaging
55 nm TSMC Embedded Flash (EmbFlash) process technology
•
•
Low cost and small package sizes
Multiple device densities with compatible package footprints
for seamless migration between different device densities
RoHS6-compliant
•
•
Core architecture
4-input look-up table (LUT) and single register logic element
(LE)
•
•
•
•
•
LEs arranged in logic array block (LAB)
Embedded RAM and user flash memory
Clocks and PLLs
Embedded multiplier blocks
General purpose I/Os
Internal memory blocks
User Flash Memory
•
•
M9K—9 kilobits (Kb) memory blocks
Cascadable blocks to create RAM, dual port, and FIFO
functions
•
•
•
•
•
User accessible non-volatile storage
High speed operating frequency
Large memory size
High data retention
Multiple interface option
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Summary of MAX 10 Device Features
Description
Feature
Embedded
multiplier
blocks
•
•
Support for one 18 x 18 or two 9 x 9 multiplier modes
Cascadable blocks enabling creation of filters, arithmetic
functions, and image processing pipelines
ADC
•
•
•
•
12-bits successive approximation register (SAR) type
Up to 17 analog inputs
Cumulative speed up to 1 million samples per second ( MSPS)
Integrated temperature sensing capability
Embedded hard IP
Flash memory Support for dual-boot self-configuration technology
IP
Clock networks
•
•
Support for global clocks
High speed frequency in clock network
Internal Oscillator
PLLs
Built-in internal ring oscillator
•
•
•
•
•
•
Analog-based
Low jitter
High precision clock synthesis
Clock delay compensation
Zero delay buffering
Multiple output taps
General-purpose I/Os (GPIOs)
External memory interface
•
•
•
Support multiple I/O standards
On-chip termination (OCT)
Up to 830 megabits per second (Mbps) LVDS receiver,
800 Mbps LVDS transmitter
Supports up to 600 Mbps external memory interfaces:
•
DDR3, DDR3L, DDR2, LPDDR2 (Only for 10M16, 10M25,
10M40, and 10M50).
•
SRAM (Hardware support only. Use your own design to
interface with SRAM devices.)
Configuration
•
•
•
Internal configuration
JTAG
Advanced Encryption Standard (AES) 128-bit encryption and
compression options
•
Flash memory data retention of 10 years
Flexible power supply schemes
•
•
•
Single and dual supply device options
Dynamically controlled input buffer power down
Sleep mode for dynamic power reduction
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MAX 10 Device Feature Options
MAX 10 Device Feature Options
Table 3: Feature Options for MAX 10 Devices
Option
Feature
Compact
Flash
Devices with core architecture featuring single-boot self-configuration capability
Devices with core architecture featuring:
•
•
Dual-image self-configuration
Remote system upgrade capability
Analog
Devices with core architecture featuring:
•
•
•
Dual-image self-configuration
Remote system upgrade capability
Integrated analog-to-digital converter
MAX 10 Device Ordering Information
Figure 1: Sample Ordering Code and Available Options for MAX 10 Devices - Preliminary
Feature Options
Package Type
SC S:ingle supply, compact features
SF S:ingle supply, flash features
SA S:ingle supply, analog features
DC D:ual supply, compact features
DF D:ual supply, flash features
DA D:ual supply, analog features
V
E
: Wafer-Level Chip Scale (WLCSP)
: Plastic Enhanced Quad Flat Pack (EQFP)
: Micro FineLine BGA (MBGA)
: Ultra FineLine BGA (UBGA)
: FineLine BGA (FBGA)
M
U
F
Operating Temperature
C
I
A
:
:
:
Commercial (T = 0° C to 85° C)
J
Family Signature
10M : MAX 10
10M 16 DA
U
484
I
7 G
Industrial (T = -40° C to 100° C)
J
Automotive (T = -40° C to 125° C)
J
FPGA Fabric
Speed Grade
Member Code
Optional Suffix
02: 2K logic elements
04: 4K logic elements
08: 8K logic elements
16: 16K logic elements
25: 25K logic elements
40: 40K logic elements
50: 50K logic elements
Indicates specific device
options or shipment method
6 (fastest)
7
8
G
:
RoHS6
ES : Engineering sample
Package Code
WLCSP Package Type
UBGA Package Type
169 : 169 pins, 11 mm x 11 mm
324 : 324 pins, 15 mm x 15 mm
36
81
:
:
36 pins, 3 mm x 3 mm
81 pins, 4 mm x 4 mm
EQFP Package Type
FBGA Package Type
256 : 256 pins, 17 mm x 17 mm
484 : 484 pins, 23 mm x 23 mm
672 : 672 pins, 27 mm x 27 mm
144 : 144 pins, 22 mm x 22 mm
MBGA Package Type
153 : 153 pins, 8 mm x 8 mm
Note: The –I6 speed grade MAX 10 FPGA device option is not available by default in the Quartus II
software. Contact your local Altera sales representatives for support.
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MAX 10 Device Maximum Resources
Related Information
Altera Product Selector
Provides the latest information about Altera products.
MAX 10 Device Maximum Resources
Table 4: Maximum Resource Counts for MAX 10 Devices—Preliminary
Device
Resource
10M02
2
10M04
4
10M08
8
10M16
16
10M25
25
10M40
40
10M50
50
Logic Elements (LE) (K)
M9K Memory (Kb)
Flash Memory (Kb) (1)
18 x 18 Multiplier
PLL
108
96
189
1,248
20
378
1,376
24
549
2,368
45
675
3,200
55
1,260
5,888
125
4
1,638
5,888
144
4
16
2
2
2
4
4
GPIO
160
10
246
15
250
15
320
22
380
26
500
30
500
30
Dedicated
Transmitter
Emulated
LVDS
73
73
1
114
114
2
116
116
2
151
151
2
181
181
2
241
241
2
241
241
2
Transmitter
Dedicated
Receiver
Internal Configuration
Image
ADC
—
1
1
1
2
2
2
MAX 10 Devices I/O Resources Per Package
Table 5: Package Plan for MAX 10 Single Power Supply Devices—Preliminary
Package
Type
M153
U169
E144
153-pin MBGA
169-pin UBGA
144-pin EQFP
Device
Size
8 mm × 8 mm
0.5 mm
11 mm × 11 mm
0.8 mm
22 mm × 22 mm
0.5 mm
Ball Pitch
10M02
112
130
101
(1)
The flash memory capacities include user flash memory and configuration flash memory. For more
information, refer to MAX 10 User Flash Memory User Guide.
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MAX 10 Vertical Migration Support
Package
Type
M153
U169
E144
153-pin MBGA
169-pin UBGA
144-pin EQFP
Device
Size
8 mm × 8 mm
11 mm × 11 mm
22 mm × 22 mm
Ball Pitch
0.5 mm
112
112
—
0.8 mm
130
130
130
—
0.5 mm
101
10M04
10M08
10M16
10M25
10M40
10M50
101
101
—
101
—
—
101
—
—
101
Table 6: Package Plan for MAX 10 Dual Power Supply Devices—Preliminary
Package
Type
V36
V81
U324
F256
F484
F672
36-pin
WLCSP
81-pin
WLCSP
324-pin
UBGA
256-pin
FBGA
484-pin
FBGA
672-pin FBGA
Device
Size
3 mm × 3
mm
4 mm × 4
mm
15 mm × 15 17 mm × 17 23 mm × 23
27 mm × 27 mm
1.0 mm
mm
mm
mm
Ball
0.4 mm
0.4 mm
0.8 mm
1.0 mm
1.0 mm
Pitch
10M02
10M04
10M08
10M16
10M25
10M40
10M50
27
—
—
—
—
—
—
—
—
56
—
—
—
—
160
246
246
246
—
—
—
—
—
178
178
178
178
178
178
—
250
320
360
360
360
—
—
380
500
500
—
—
Related Information
MAX 10 General Purpose I/O User Guide
MAX 10 Vertical Migration Support
Vertical migration supports the migration of your design to other MAX 10 devices of different densities in
the same package with similar I/O and ADC resources.
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MAX 10 I/O Vertical Migration Support
MAX 10 I/O Vertical Migration Support
Figure 2: Migration Capability Across MAX 10 Devices—Preliminary
•
•
The arrows indicate the migration paths. The devices included in each vertical migration path are
shaded. Some packages have several migration paths. Devices with lesser I/O resources in the same
path have lighter shades.
To achieve the full I/O migration across product lines in the same migration path, restrict I/Os usage
to match the product line with the lowest I/O count.
Package
U324
Device
V36
V81
M153 U169
F256
E144
F484
F672
10M02
10M04
10M08
10M16
10M25
10M40
10M50
Note: To verify the pin migration compatibility, use the Pin Migration View window in the Quartus II
software Pin Planner.
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MAX 10 ADC Vertical Migration Support
MAX 10 ADC Vertical Migration Support
Figure 3: ADC Vertical Migration Across MAX 10 Devices—Preliminary
The arrows indicate the ADC migration paths. The devices included in each vertical migration path are
shaded.
Package
F256
Device
M153
U169
U324
E144
F484
F672
10M04
10M08
10M16
10M25
10M40
10M50
Dual ADC Device: Each ADC (ADC1 and ADC2) supports 1 dedicated analog input pin and 8 dual function pins.
Single ADC Device: Single ADC supports 1 dedicated analog input pin and 16 dual function pins.
Table 7: Pin Migration Conditions for ADC Migration
Source
Target
Migratable Pins
Single ADC device
Dual ADC device
Single ADC device
Dual ADC device
Single ADC device
Dual ADC device
Dual ADC device
Single ADC device
You can migrate all ADC input pins
•
•
One dedicated analog input pin.
Eight dual function pins from the ADC1
block of the source device to the ADC1
block of the target device.
Logic Elements and Logic Array Blocks
The LAB consists of 16 logic elements and a LAB-wide control block. An LE is the smallest unit of logic in
the MAX 10 device architecture. Each LE has four inputs, a four-input look-up table (LUT), a register,
and output logic. The four-input LUT is a function generator that can implement any function with four
variables.
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Analog-to-Digital Converter
Figure 4: MAX 10 Device Family LEs
Register Chain
Routing from
previous LE
Register Bypass
LAB-Wide
Synchronous
Load
LAB-Wide
Synchronous
Clear
ammable
Progr
er
Regist
LE Carry-In
data 1
Row, Column,
And Direct Link
Routing
data 2
data 3
Synchronous
Load and
Clear Logic
Carry
Chain
Look-Up Table
(LUT)
D
Q
data 4
ENA
CLRN
Row, Column,
And Direct Link
Routing
labclr1
labclr2
Asynchronous
Clear Logic
Chip-Wide
Reset
(DEV_CLRn)
Local
Routing
Register Feedback
Clock &
Clock Enable
Select
Register Chain
Output
labclk1
labclk2
LE Carry-Out
labclkena1
labclkena2
Analog-to-Digital Converter
MAX 10 devices feature up to two analog-to-digital converters (ADC). The ADCs of the MAX 10 devices
monitor the internal temperature of the die and support external analog signal conversion.
Table 8: ADC Features
Feature
Description
12 bits resolution
•
•
Translates analog quantities to digital data for informa‐
tion processing, computing, data transmission, and
control systems
Provides a 12 bit digital representation of the observed
analog signal
Up to 1 MSPS sampling rate
Monitors single-ended external inputs with a cumulative
sampling rate of 1 MSPS in normal mode
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User Flash Memory
Feature
Description
Up to 17 single-ended external inputs for
single ADC devices
One dedicated analog and 16 dual function input pins
Up to 18 single-ended external inputs for
dual ADC devices
•
•
One dedicated analog and eight dual function input pins
in each ADC block
Simultaneous measurement capability for dual ADC
devices
On-chip temperature sensor
Monitors external temperature data input with a sampling
rate of up to 50 kilosamples per second
User Flash Memory
The user flash memory (UFM) block in MAX 10 devices stores non-volatile information.
The UFM provides an ideal storage solution that you can access using the following protocols:
•
•
Avalon Memory Mapped (Avalon-MM) slave interface to UFM
SPI slave interface through Avalon-MM to UFM (available in version 14.1 of the Quartus II software
onwards)
Table 9: UFM Features
Features
Capacity
Up to 10,000 times read and write cycle counts
Maximum 116 MHz
Endurance
Operating frequency
Data length storage
Up to 32-bit length
Embedded Multipliers and Digital Signal Processing Support
MAX 10 devices support up to 144 embedded multiplier blocks. Each block supports one individual
18 × 18-bit multiplier or two individual 9 × 9-bit multipliers.
In addition to embedded multipliers, the MAX 10 device includes a combination of on-chip resources and
external interfaces to increase performance, reduce system cost, and lower the power consumption of
digital signal processing (DSP) systems. You can use the MAX 10 device on its own or as a DSP device co-
processor to improve price-to-performance ratios of DSP systems.
You can control the operation of the embedded multiplier blocks using the following options:
•
•
Parameterize relevant IP cores with the Quartus II parameter editor
Infer the multipliers directly with VHDL or Verilog
System design features provided for MAX 10 devices:
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Embedded Memory Blocks
•
DSP IP cores:
•
Common DSP processing functions such as finite impulse response (FIR), fast Fourier transform
(FFT), and numerically controlled oscillator (NCO) functions
•
Suites of common video and image processing functions
•
•
Complete reference designs for end-market applications
DSP Builder interface tool between the Quartus II software and the MathWorks Simulink and
MATLAB design environments
•
DSP development kits
Embedded Memory Blocks
Each M9K memory block of the MAX 10 device provides 9 Kb of on-chip memory capable of operating at
up to 284 MHz. The embedded memory structure consists of M9K memory blocks columns. You can
configure the columns of the embedded M9K memory blocks as either one of the following:
•
•
•
RAM
First-in first-out (FIFO) buffers
ROM
The MAX 10 device memory blocks are optimized for applications such as high throughput packet
processing, embedded processor program, and embedded data storage.
You can utilize the M9K memory blocks using the following options:
•
•
Parameterize relevant IP cores with the Quartus II parameter editor
Infer the multipliers directly with VHDL or Verilog
Table 10: M9K Supported Operation Modes and Configurations
M9K Operation Modes
Port Widths Configuration
Single-port
×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, and ×36
×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, and ×36
×1, ×2, ×4, ×8, ×9, ×16, and ×18
Simple dual-port
True dual-port
Clocking and PLL
MAX 10 devices support up to 20 global clock (GCLK) networks with operating frequency up to
450 MHz. The GCLK networks have high drive strength and low skew.
MAX 10 devices have built-in internal oscillator.
The high precision and low jitter PLLs have the following usages:
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FPGA General Purpose I/O
•
•
Reduction in the number of oscillators required on the board
Reduction in the device clock pins through multiple clock frequency synthesis from a single reference
clock source
•
•
•
•
•
•
•
•
•
•
•
Frequency synthesis
On-chip clock de-skew
Jitter attenuation
Dynamic phase-shift
Zero delay buffer
Counters reconfiguration
Bandwidth reconfiguration
Programmable output duty cycle
PLL cascading
Reference clock switchover
Driving of the ADC block
FPGA General Purpose I/O
The MAX 10 device I/O buffers support the following programmable features:
•
•
•
•
•
•
•
•
•
•
Programmable current strength
Programmable output slew-rate control
Programmable IOE delay
PCI clamp diode
Programmable pre-emphasis
Programmable emulated differential output
Programmable dynamic power down
Programmable bus hold
Programmable weak pull up
Programmable open drain
External Memory Interface
The MAX 10 devices feature one soft memory controller for DDR3, DDR3L, DDR2, and LPDDR2
SDRAM interfaces on the right side of the device. The external memory controller in MAX 10 devices
supports 16 bit SDRAM components with error correction coding (ECC).
The external memory interface feature is available for dual supply MAX 10 devices only.
Table 11: External Memory Interface Performance
External Memory Interface(2)
DDR3 SDRAM
I/O Standard
SSTL-15
Maximum Width
16 bit + 8 bit ECC
16 bit + 8 bit ECC
Maximum Frequency (MHz)
303
303
DDR3L SDRAM
SSTL-135
(2)
The device hardware supports SRAM. Use your own design to interface with SRAM devices.
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Configuration
External Memory Interface(2)
I/O Standard
SSTL-18
Maximum Width
16 bit + 8 bit ECC
16 bit without ECC
Maximum Frequency (MHz)
DDR2 SDRAM
200
200
LPDDR2 SDRAM
HSUL-12
Note: MAX 10 FPGA support for the DDR3, DDR3L, DDR2, and LPDDR2 external memory interfaces is
not available by default in the Quartus II software. Contact your local sales representative for
support.
Related Information
External Memory Interface Spec Estimator
Provides a parametric tool that allows you to find and compare the performance of the supported external
memory interfaces in Altera devices.
Configuration
Table 12: Configuration Features
Feature
Description
Dual-image configuration
•
•
Stores two configuration images in the configuration flash memory
(CFM)
Selects the first configuration image to boot using the BOOT_SEL
pin
Design security
•
•
Supports 128 bit key with non-volatile key programming
Limits access of the JTAG instruction during power-up in the JTAG
secure mode
SEU Mitigation(3)
•
•
Auto-detects cyclic redundancy check (CRC) errors during configu‐
ration
Provides optional CRC error detection and identification in user
mode.
Dual-purpose configuration pin
Configuration data compression
•
•
Functions as configuration pins prior to user mode
Provides option to be used as configuration pins or user I/O pins in
user mode
•
•
Receives compressed configuration bitstream and decompresses the
data in real-time during configuration
Reduces the configuration image size stored in the CFM
(2)
The device hardware supports SRAM. Use your own design to interface with SRAM devices.
The SEU mitigation feature for single supply devices is disabled by default in the Quartus II software. For
more information and support, contact your local sales representative.
(3)
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Power Management
Feature
Description
Instant-on
Provides the fastest power-up mode for MAX 10 devices without any
POR delay
Table 13: Configuration Modes for MAX 10 Devices
Configuration Mode
Compression
Encryption
Dual Image
Configuration
Data Width
Internal Configuration
JTAG
Yes
—
Yes
—
Yes
—
—
1
Power Management
Table 14: Power Options
Power Options
Advantage
Single supply device option
Dual supply device option
Saves board space and costs
•
•
Consumes less power than the single supply device option
Offers higher performance than the single supply device option
Power management controller
scheme
•
•
Reduces dynamic power consumption when certain applications
are in standby mode
Provides a fast wake-up time of less than 1 ms.
Document Revision History for MAX 10 FPGA Device Overview
Date
Version
Changes
September 2014
2014.09.22 Initial release.
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相关型号：
10M08SFU169C8G
Field Programmable Gate Array, PBGA169, 11 X 11 MM, 0.80 MM PITCH, ROHS COMPLIANT, UBGA-169
INTEL
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