10AX066H4F34I3SG [INTEL]
Field Programmable Gate Array, 660000-Cell, CMOS, PBGA1152, 35 X 35 MM, ROHS COMPLIANT, FBGA-1152;型号: | 10AX066H4F34I3SG |
厂家: | INTEL |
描述: | Field Programmable Gate Array, 660000-Cell, CMOS, PBGA1152, 35 X 35 MM, ROHS COMPLIANT, FBGA-1152 栅 可编程逻辑 |
文件: | 总110页 (文件大小:1391K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Arria 10 Device Datasheet
2015.12.31
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This datasheet describes the electrical characteristics, switching characteristics, configuration specifications, and I/O timing for Arria® 10 devices.
Arria 10 devices are offered in extended and industrial grades. Extended devices are offered in –E1 (fastest), –E2, and –E3 speed grades. Industrial
grade devices are offered in the –I1, –I2, and –I3 speed grades.
The suffix after the speed grade denotes the power options offered in Arria 10 devices.
•
•
•
•
L—Low static power
S—Standard power
M—Enabled with the VCC PowerManager feature (you can power VCC and VCCP at nominal voltage of 0.90 V or lower voltage of 0.83 V)
V—Supported with the SmartVID feature (lowest static power)
Related Information
Arria 10 Device Overview
Provides more information about the densities and packages of devices in the Arria 10 family.
Electrical Characteristics
The following sections describe the operating conditions and power consumption of Arria 10 devices.
Operating Conditions
Arria 10 devices are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of the Arria 10
devices, you must consider the operating requirements described in this section.
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2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent
and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera
ISO
9001:2008
Registered
warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without
notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are
advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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Absolute Maximum Ratings
Absolute Maximum Ratings
This section defines the maximum operating conditions for Arria 10 devices. The values are based on experiments conducted with the devices and
theoretical modeling of breakdown and damage mechanisms. The functional operation of the device is not implied for these conditions.
Caution: Conditions outside the range listed in the following table may cause permanent damage to the device. Additionally, device operation at
the absolute maximum ratings for extended periods of time may have adverse effects on the device.
Table 1: Absolute Maximum Ratings for Arria 10 Devices—Preliminary
Symbol
Description
Condition
Minimum
–0.50
Maximum
1.21
Unit
V
VCC
Core voltage power supply
—
—
VCCP
Periphery circuitry and transceiver fabric interface power
supply
–0.50
1.21
V
VCCERAM
VCCPT
Embedded memory power supply
—
—
–0.50
–0.50
1.36
2.46
V
V
Power supply for programmable power technology and I/O
pre-driver
VCCBAT
Battery back-up power supply for design security volatile key
register
—
–0.50
2.46
V
(1)
VCCPGM
VCCIO
Configuration pins power supply
–0.50
–0.50
–0.50
–0.50
–0.50
–0.50
–0.50
–0.50
–0.50
–0.50
2.46
4.10
2.46
2.46
1.34
1.34
2.46
1.27
4.10
2.46
V
V
V
V
V
V
V
V
V
V
3 V I/O
I/O buffers power supply
LVDS I/O
VCCA_PLL
VCCT_GXB
VCCR_GXB
VCCH_GXB
VCCL_HPS
Phase-locked loop (PLL) analog power supply
Transmitter power
—
—
Receiver power
—
Transmitter output buffer power
HPS core voltage and periphery circuitry power supply
—
—
3 V I/O
LVDS I/O
VCCIO_HPS
HPS I/O buffers power supply
(1)
The LVDS I/O values are applicable to all dedicated and dual-function configuration I/Os.
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Maximum Allowed Overshoot and Undershoot Voltage
Symbol
Description
HPS I/O pre-driver power supply
HPS PLL power supply
Condition
Minimum
–0.50
–0.50
–25
Maximum
2.46
Unit
V
VCCIOREF_HPS
VCCPLL_HPS
IOUT
—
—
—
—
—
2.46
V
DC output current per pin
25
mA
°C
°C
TJ
Operating junction temperature
Storage temperature (no bias)
–55
125
TSTG
–65
150
Maximum Allowed Overshoot and Undershoot Voltage
During transitions, input signals may overshoot to the voltage listed in the following table and undershoot to –2.0 V for input currents less than
100 mA and periods shorter than 20 ns.
The maximum allowed overshoot duration is specified as a percentage of high time over the lifetime of the device. A DC signal is equivalent to
100% duty cycle.
For example, a signal that overshoots to 2.70 V for LVDS I/O can only be at 2.70 V for ~4% over the lifetime of the device.
Table 2: Maximum Allowed Overshoot During Transitions for Arria 10 Devices—Preliminary
This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime. The LVDS I/O
values are applicable to the VREFP_ADCand VREFN_ADCI/O pins.
Condition (V)
Symbol
Description
Overshoot Duration as % at TJ = 100°C
Unit
LVDS I/O (2)
2.50
3 V I/O
3.80
100
%
%
%
%
%
%
2.55
3.85
42
2.60
3.90
18
Vi (AC)
AC input voltage
2.65
3.95
9
2.70
4.00
4
> 2.70
> 4.00
No overshoot allowed
(2)
The LVDS I/O values are applicable to all dedicated and dual-function configuration I/Os.
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Recommended Operating Conditions
Recommended Operating Conditions
This section lists the functional operation limits for the AC and DC parameters for Arria 10 devices.
Recommended Operating Conditions
Table 3: Recommended Operating Conditions for Arria 10 Devices—Preliminary
This table lists the steady-state voltage values expected from Arria 10 devices. Power supply ramps must all be strictly monotonic, without plateaus.
Symbol
Description
Condition
Standard and low power
VCC PowerManager (5)
SmartVID (6)
Minimum (3)
Typical
0.9 (4)
0.83, 0.9
—
0.9 (4)
0.83, 0.9
—
Maximum (3)
Unit
0.87
0.93
V
V
V
V
V
V
V
V
V
V
VCC
Core voltage power supply
0.8, 0.87
0.8
0.86, 0.93
0.93
Standard and low power
VCC PowerManager (5)
SmartVID (6)
0.87
0.93
Periphery circuitry and transceiver
fabric interface power supply
VCCP
0.8, 0.87
0.8
0.86, 0.93
0.93
1.8 V
1.71
1.8
1.89
VCCPGM
Configuration pins power supply
Embedded memory power supply
1.5 V
1.425
1.14
1.5
1.575
1.2 V
1.2
0.9(4)
1.26
VCCERAM
0.9 V
0.87
0.93
(3)
(4)
This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the
PDN tool for the additional budget for the dynamic tolerance requirements.
You can operate –1 and –2 speed grade devices at 0.9 V or 0.95 V typical value. You can operate -3 speed grade device at only 0.9 V typical value.
Core performance shown in this datasheet is applicable for the operation at 0.9 V. Operating at 0.95 V results in higher core performance and higher
power consumption. For more information about the performance and power consumption of 0.95 V operation, refer to the Quartus® Prime
software timing reports, PowerPlay Power Analyzer report, and Early Power Estimator (EPE).
You can operate VCC PowerManager devices at either 0.83 V or 0.9 V. Power VCC and VCCP at 0.9 V to achieve –1 speed grade performance. Power
VCC and VCCP at 0.83 V to achieve lower performance using the lowest power.
SmartVID is supported in devices with –2V and –3V speed grades only.
(5)
(6)
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Recommended Operating Conditions
Symbol
Description
Condition
1.8 V
Minimum (3)
1.71
Typical
Maximum (3)
1.89
Unit
Battery back-up power supply
(For design security volatile key
register)
1.8
1.2
V
V
(7)
VCCBAT
VCCPT
1.2 V
1.14
1.26
Power supply for programmable
1.8 V
1.71
1.8
1.89
V
power technology and I/O pre-driver
3.0 V (for 3 V I/O only)
2.85
2.375
1.71
3.0
2.5
3.15
2.625
1.89
V
V
V
V
V
V
V
V
2.5 V (for 3 V I/O only)
1.8 V
1.5 V
1.35 V
1.25 V
1.2 V
—
1.8
VCCIO
I/O buffers power supply
1.425
(8)
1.5
1.575
(8)
1.35
1.25
1.2
1.19
(8)
1.31
(8)
VCCA_PLL
PLL analog voltage regulator power
supply
1.71
1.8
1.89
VREFP_ADC
Precision voltage reference for
voltage sensor
—
1.2475
1.25
1.2525
V
3 V I/O
LVDS I/O
—
–0.3
–0.3
0
—
—
—
—
—
3.3
2.19
VCCIO
100
V
V
(9)
VI
DC input voltage
VO
TJ
Output voltage
V
Extended
Industrial
0
°C
°C
Operating junction temperature
–40
100
(3)
(7)
This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the
PDN tool for the additional budget for the dynamic tolerance requirements.
If you do not use the design security feature in Arria 10 devices, connect VCCBAT to a 1.5-V or 1.8-V power supply. Arria 10 power-on reset (POR)
circuitry monitors VCCBAT. Arria 10 devices do not exit POR if VCCBAT is not powered up.
(8)
(9)
For minimum and maximum voltage values, refer to the I/O Standard Specifications section.
The LVDS I/O values are applicable to all dedicated and dual-function configuration I/Os.
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Transceiver Power Supply Operating Conditions
Symbol
Description
Condition
Standard POR
Fast POR
Minimum (3)
200 µs
Typical
—
Maximum (3)
100 ms
Unit
—
—
(10)(11)
tRAMP
Power supply ramp time
200 µs
—
4 ms
Related Information
I/O Standard Specifications on page 17
Transceiver Power Supply Operating Conditions
Table 4: Transceiver Power Supply Operating Conditions for Arria 10 GX/SX Devices—Preliminary
Symbol
Description
Condition (12)
Chip-to-Chip ≤ 17.4 Gbps
Or
Minimum (13)
Typical
Maximum
Unit
1.0
1.03
1.06
V
Backplane (14) ≤ 16.0 Gbps
VCCT_GXB[L,R]
Transmitter power supply
Chip-to-Chip ≤ 11.3 Gbps
Or
0.92
0.95
0.98
V
Backplane (14) ≤ 10.3125 Gbps
(3)
This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the
PDN tool for the additional budget for the dynamic tolerance requirements.
(10)
This is also applicable to HPS power supply. For HPS power supply, refer to tRAMP specifications for standard POR when HPS_PORSEL = 0 and
tRAMP specifications for fast POR when HPS_PORSEL = 1.
(11)
(12)
tramp is the ramp time of each individual power supply, not the ramp time of all combined power supplies.
These data rate ranges vary depending on the transceiver speed grade. Refer to Transceiver Performance for Arria 10 GX/SX Devices for exact data
rate ranges.
This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the
PDN tool for the additional budget for the dynamic tolerance requirements.
Backplane applications assume advanced equalization circuitry, such as decision feedback equalization (DFE), is enabled to compensate for signal
impairments. Chip-to-chip links are assumed to be applications with short reach channels that do not require DFE.
(13)
(14)
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Transceiver Power Supply Operating Conditions
Symbol
Description
Condition (12)
Chip-to-Chip ≤ 17.4 Gbps
Or
Minimum (13)
Typical
Maximum
Unit
1.0
1.03
1.06
V
Backplane (14) ≤ 16.0 Gbps
VCCR_GXB[L,R]
Receiver power supply
Chip-to-Chip ≤ 11.3 Gbps
Or
0.92
0.95
1.8
0.98
V
V
Backplane (14) ≤ 10.3125 Gbps
VCCH_GXB[L,R]
Transceiver high voltage
power
—
1.710
1.890
Note: Most VCCR_GXB and VCCT_GXB pins associated with unused transceiver channels can be grounded on a per-side basis to minimize
power consumption. Refer to the Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines and the Quartus Prime pin report for
information about pinning out the package to minimize power consumption for your specific design.
(12)
(13)
These data rate ranges vary depending on the transceiver speed grade. Refer to Transceiver Performance for Arria 10 GX/SX Devices for exact data
rate ranges.
This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the
PDN tool for the additional budget for the dynamic tolerance requirements.
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Transceiver Power Supply Operating Conditions
Table 5: Transceiver Power Supply Operating Conditions for Arria 10 GT Devices—Preliminary
Symbol
Description
Condition (15)
Chip-to-Chip < 28.3 Gbps (16)
Or
Minimum (13)
Typical
Maximum
Unit
1.10
1.12
1.14
V
V
V
V
V
V
Backplane (14) < 17.4 Gbps
Chip-to-Chip < 15 Gbps
Or
Backplane (14) < 14.2 Gbps
1.0
0.92
1.10
1.0
1.03
0.95
1.12
1.03
0.95
1.06
0.98
1.14
1.06
0.98
VCCT_GXB[L,R]
Transmitter power supply
Chip-to-Chip < 11.3 Gbps
Or
Backplane (14) < 10.3125 Gbps
Chip-to-Chip < 28.3 Gbps
Or
Backplane (14) < 17.4 Gbps
Chip-to-Chip < 15 Gbps
Or
Backplane (14) < 14.2 Gbps
VCCR_GXB[L,R]
Receiver power supply
Chip-to-Chip < 11.3 Gbps
Or
0.92
Backplane (14) < 10.3125 Gbps
(15)
These data rate ranges vary depending on the transceiver speed grade. Refer to Transceiver Performance for Arria 10 GT Devices table for exact data
rate ranges.
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HPS Power Supply Operating Conditions
Symbol
Description
Condition (15)
Minimum (13)
Typical
Maximum
Unit
VCCH_GXB[L,R]
Transceiver high voltage power
supply
—
1.710
1.8
1.890
V
Related Information
•
•
•
Transceiver Performance for Arria 10 GT Devices on page 26
Provides the data rate ranges for different transceiver speed grades.
Transceiver Performance for Arria 10 GX/SX Devices on page 23
Provides the data rate ranges for different transceiver speed grades.
Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
HPS Power Supply Operating Conditions
Table 6: HPS Power Supply Operating Conditions for Arria 10 SX Devices—Preliminary
This table lists the steady-state voltage and current values expected from Arria 10 system-on-a-chip (SoC) devices with ARM®-based hard processor system
(HPS). Power supply ramps must all be strictly monotonic, without plateaus. Refer to Recommended Operating Conditions for Arria 10 Devices table for
the steady-state voltage values expected from the FPGA portion of the Arria 10 SoC devices.
Symbol
Description
Condition
Minimum (17)
Typical
Maximum (17)
Unit
HPS processor speed =
1.2 GHz
0.87
0.9
0.93
V
HPS core voltage and periphery
circuitry power supply
VCCL_HPS
HPS processor speed =
1.5 GHz, –1 speed grade
0.92
0.95
0.98
V
3.0 V
2.5 V
1.8 V
2.85
2.375
1.71
3.0
2.5
1.8
3.15
2.625
1.89
V
V
V
VCCIO_HPS
HPS I/O buffers power supply
(15)
These data rate ranges vary depending on the transceiver speed grade. Refer to Transceiver Performance for Arria 10 GT Devices table for exact data
rate ranges.
28.3 Gbps is the maximum data rate for GT channels. 17.4 Gbps is the maximum data rate for GX channels.
This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the
PDN tool for the additional budget for the dynamic tolerance requirements.
(16)
(17)
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DC Characteristics
Symbol
Description
Condition
Minimum (17)
1.71
Typical
1.8
Maximum (17)
1.89
Unit
VCCIOREF_HPS
VCCPLL_HPS
HPS I/O pre-driver power supply
—
—
V
V
HPS PLL analog voltage regulator
power supply
1.71
1.8
1.89
Related Information
Recommended Operating Conditions on page 4
Provides the steady-state voltage values for the FPGA portion of the device.
DC Characteristics
The OCT variation after power-up calibration specifications will be available in a future release of the Arria 10 Device Datasheet.
Supply Current and Power Consumption
Altera offers two ways to estimate power for your design—the Excel-based Early Power Estimator (EPE) and the Quartus Prime PowerPlay Power
Analyzer feature.
Use the Excel-based EPE before you start your design to estimate the supply current for your design. The EPE provides a magnitude estimate of the
device power because these currents vary greatly with the usage of the resources.
The Quartus Prime PowerPlay Power Analyzer provides better quality estimates based on the specifics of the design after you complete place-and-
route. The PowerPlay Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities that, when
combined with detailed circuit models, yield very accurate power estimates.
Related Information
•
PowerPlay Early Power Estimator User Guide
Provides more information about power estimation tools.
PowerPlay Power Analysis chapter, Quartus Prime Handbook
Provides more information about power estimation tools.
•
(17)
This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the
PDN tool for the additional budget for the dynamic tolerance requirements.
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I/O Pin Leakage Current
I/O Pin Leakage Current
Table 7: I/O Pin Leakage Current for Arria 10 Devices—Preliminary
If VO = VCCIO to VCCIOMAX, 300 μA of leakage current per I/O is expected.
Symbol
Description
Condition
Min
–80
–80
Max
80
Unit
µA
II
Input pin
Tri-stated I/O pin
VI = 0 V to VCCIOMAX
VO = 0 V to VCCIOMAX
IOZ
80
µA
Bus Hold Specifications
The bus-hold trip points are based on calculated input voltages from the JEDEC standard.
Table 8: Bus Hold Parameters for Arria 10 Devices—Preliminary
VCCIO (V)
Parameter
Symbol Condition
1.2
1.5
1.8
2.5
3.0
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Bus-hold,
low,
ISUSL
VIN > VIL
(max)
8 (18)
,
—
12 (18)
,
—
30 (18)
,
—
60
—
70
—
µA
µA
µA
26 (19)
32 (19)
55 (19)
sustaining
current
Bus-hold,
high,
ISUSH VIN < VIH –8 (18)
,
—
–12 (18)
,
—
–30 (18)
,
—
–60
—
—
–70
—
—
(min)
–26 (19)
–32 (19)
–55 (19)
sustaining
current
Bus-hold,
low,
IODL
0 V < VIN
< VCCIO
—
125
—
175
—
200
300
500
overdrive
current
(18)
This value is only applicable for LVDS I/O bank.
This value is only applicable for 3 V I/O bank.
(19)
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OCT Calibration Accuracy Specifications
VCCIO (V)
1.8
Parameter
Symbol Condition
1.2
1.5
2.5
3.0
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Bus-hold,
high,
IODH
0 V < VIN
< VCCIO
—
–125
—
–175
—
–200
—
–300
—
–500
µA
V
overdrive
current
Bus-hold
trip point
VTRIP
—
0.3
0.9
0.38
1.13
0.68
1.07
0.70
1.7
0.8
2
OCT Calibration Accuracy Specifications
If you enable on-chip termination (OCT) calibration, calibration is automatically performed at power up for I/Os connected to the calibration
block.
Table 9: OCT Calibration Accuracy Specifications for Arria 10 Devices—Preliminary
Calibration accuracy for the calibrated on-chip series termination (RS OCT) and on-chip parallel termination (RT OCT) are applicable at the moment of
calibration. When process, voltage, and temperature (PVT) conditions change after calibration, the tolerance may change.
Calibration Accuracy
Symbol
Description
Condition (V)
Unit
–E1, –I1
–E2, –I2
–E3, –I3
48-Ω, 60-Ω, 80-Ω,
and 240-Ω RS
Internal series termination with
calibration (48-Ω, 60-Ω, 80-Ω, and
240-Ω setting)
VCCIO = 1.2
15
15
15
%
34-Ω and 40-Ω RS
25-Ω RS
Internal series termination with
VCCIO = 1.5, 1.35, 1.25,
15
15
15
15
15
15
15
15
15
%
%
%
calibration (34-Ω and 40-Ω setting) 1.2
Internal series termination with
calibration
VCCIO = 1.8, 1.5, 1.2
VCCIO = 1.8, 1.5, 1.2
50-Ω RS
Internal series termination with
calibration
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OCT Without Calibration Resistance Tolerance Specifications
Calibration Accuracy
Unit
Symbol
Description
Condition (V)
–E1, –I1
–E2, –I2
–E3, –I3
34-Ω, 40-Ω, 48-Ω,
and 60-Ω RS
Internal series termination with
calibration (34-Ω, 40-Ω, 48-Ω, and
60-Ωsetting)
POD12 I/O standard,
VCCIO = 1.2
15
15
15
%
%
34-Ω, 40-Ω, 48-Ω,
Internal parallel termination with
POD12 I/O standard,
VCCIO = 1.2
15
15
15
60-Ω, 80-Ω, 120-Ω, calibration (34-Ω, 40-Ω, 48-Ω, 60-Ω,
and 240-Ω RT
80-Ω, 120-Ω, and 240-Ω setting)
60-Ω and 120-Ω RT Internal parallel termination with
VCCIO = 1.5, 1.35, 1.25,
–10 to +40
–10 to +40
–10 to +40
–10 to +40
–10 to +40
–10 to +40
–10 to +40
–10 to +40
–10 to +40
%
%
%
calibration (60-Ω and 120-Ω setting) 1.2
30-Ω and 40-Ω RT
50-Ω RT
Internal parallel termination with
calibration (30-Ω and 40-Ω setting)
VCCIO = 1.5, 1.35, 1.25
VCCIO = 1.8, 1.5, 1.2
Internal parallel termination with
calibration (50-Ω setting)
OCT Without Calibration Resistance Tolerance Specifications
Table 10: OCT Without Calibration Resistance Tolerance Specifications for Arria 10 Devices—Preliminary
This table lists the Arria 10 OCT without calibration resistance tolerance to PVT changes.
Resistance Tolerance
Symbol
Description
Condition (V)
Unit
–E1, –I1
–E2, –I2
40
–E3, –I3
40
VCCIO = 2.5, 3.0
VCCIO = 1.8, 1.5
VCCIO = 1.2
–40 to +30
–50 to +30
–50 to +30
–50 to +30
–50 to +30
–50 to +30
%
%
%
%
%
%
Internal series termination without
calibration
25-Ω RS
50
50
(25-Ω setting)
50
50
VCCIO = 1.5, 1.35, 1.25
VCCIO = 1.2
50
50
Internal series termination without
calibration
34-Ω RS
50
50
(34-Ω setting)
POD12 I/O standard
50
50
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OCT Without Calibration Resistance Tolerance Specifications
Resistance Tolerance
Symbol
Description
Condition (V)
Unit
–E1, –I1
–E2, –I2
50
–E3, –I3
50
VCCIO = 1.5, 1.35, 1.25
VCCIO = 1.2
–50 to +30
–50 to +30
–50 to +30
–50 to +30
–50 to +30
–40 to +30
–50 to +30
–50 to +30
–50 to +30
%
%
%
%
%
%
%
%
%
Internal series termination without
calibration
40-Ω RS
50
50
(40-Ω setting)
POD12 I/O standard
VCCIO = 1.2
50
50
50
50
Internal series termination without
calibration(48-Ω setting)
48-Ω RS
POD12 I/O standard
VCCIO = 2.5, 3.0
VCCIO = 1.8, 1.5
VCCIO = 1.2
50
50
40
40
Internal series termination without
calibration
50-Ω RS
60-Ω RS
50
50
(50-Ω setting)
50
50
Internal series termination without VCCIO = 1.2
50
50
calibration
(60-Ω setting)
100-Ω RD
120-Ω RS
Internal differential termination
(100-Ω setting)
VCCIO = 1.8, 1.5
25
35
50
40
50
%
%
Internal series termination without VCCIO = 1.2
–50 to +30
calibration
(120-Ω setting)
Figure 1: Equation for OCT Variation Without Recalibration—Preliminary
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Pin Capacitance
The definitions for the equation are as follows:
•
•
•
•
•
•
The ROCT value calculated shows the range of OCT resistance with the variation of temperature and VCCIO
RSCAL is the OCT resistance value at power-up.
.
ΔT is the variation of temperature with respect to the temperature at power up.
ΔV is the variation of voltage with respect to the VCCIO at power up.
dR/dT is the percentage change of RSCAL with temperature.
dR/dV is the percentage change of RSCAL with voltage.
Pin Capacitance
Table 11: Pin Capacitance for Arria 10 Devices—Preliminary
Symbol
Description
Value
2.5
Unit
pF
CIO_COLUMN
COUTFB
Input capacitance on column I/O pins
Input capacitance on dual-purpose clock output/feedback pins
2.5
pF
Internal Weak Pull-Up and Weak Pull-Down Resistor
All I/O pins, except configuration, test, and JTAG pins, have an option to enable weak pull-up. The weak pull-down feature is only available for the
pins as described in the Internal Weak Pull-Down Resistor Values for Arria 10 Devices table.
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Internal Weak Pull-Up and Weak Pull-Down Resistor
Table 12: Internal Weak Pull-Up Resistor Values for Arria 10 Devices—Preliminary
Symbol
Description
Condition (V) (20)
Value (21)
Unit
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
VCCIO = 3.0 5%
25
25
25
25
25
25
25
VCCIO = 2.5 5%
VCCIO = 1.8 5%
VCCIO = 1.5 5%
VCCIO = 1.35 5%
VCCIO = 1.25 5%
VCCIO = 1.2 5%
Value of the I/O pin pull-up resistor before and during
configuration, as well as user mode if you have enabled the
programmable pull-up resistor option.
RPU
Table 13: Internal Weak Pull-Down Resistor Values for Arria 10 Devices—Preliminary
Pin Name
Description
Condition (V)
Value (21)
Unit
nIO_PULLUP
Dedicated input pin that determines the
internal pull-ups on user I/O pins and dual-
purpose I/O pins.
VCC = 0.9 3.33%
25
kΩ
VCCPGM = 1.8 5 %
VCCPGM = 1.5 5%
VCCPGM = 1.2 5%
VCCPGM = 1.8 5%
VCCPGM = 1.5 5%
VCCPGM = 1.2 5%
25
25
25
25
25
25
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
TCK
Dedicated JTAG test clock input pin.
Configuration input pins that set the
MSEL[0:2]
configuration scheme for the FPGA device.
Related Information
Arria 10 Device Family Pin Connection Guidelines
Provides more information about the pins that support internal weak pull-up and internal weak pull-down features.
(20)
(21)
Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO
Valid with 25% tolerances to cover changes over PVT.
.
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I/O Standard Specifications
I/O Standard Specifications
Tables in this section list the input voltage (VIH and VIL), output voltage (VOH and VOL), and current drive characteristics (IOH and IOL) for various
I/O standards supported by Arria 10 devices.
For minimum voltage values, use the minimum VCCIO values. For maximum voltage values, use the maximum VCCIO values.
You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards.
Related Information
Recommended Operating Conditions on page 4
Single-Ended I/O Standards Specifications
Table 14: Single-Ended I/O Standards Specifications for Arria 10 Devices—Preliminary
VCCIO (V)
VIL (V)
Max
VIH (V)
VOL (V)
Max
0.4
VOH (V)
Min
(22)
IOL
I/O Standard
IOH (22) (mA)
(mA)
Min
Typ
Max
Min
Min
Max
3.0-V
2.85
3
3.15
–0.3
0.8
0.8
0.7
1.7
3.3
2.4
2
–2
LVTTL
3.0-V
2.85
3
3.15
–0.3
1.7
3.3
0.2
VCCIO – 0.2
0.1
–0.1
LVCMOS
2.5 V
1.8 V
1.5 V
1.2 V
2.375
1.71
2.5
1.8
1.5
1.2
2.625
1.89
–0.3
–0.3
–0.3
–0.3
1.7
3.3
0.4
2
1
2
2
2
–1
–2
–2
–2
0.35 × VCCIO 0.65 × VCCIO VCCIO + 0.3
0.45
VCCIO – 0.45
1.425
1.14
1.575
1.26
0.35 × VCCIO 0.65 × VCCIO VCCIO + 0.3 0.25 × VCCIO 0.75 × VCCIO
0.35 × VCCIO 0.65 × VCCIO VCCIO + 0.3 0.25 × VCCIO 0.75 × VCCIO
(22)
To meet the IOL and IOH specifications, you must set the current strength settings accordingly. For example, to meet the 3.0-V LVTTL specification
(2 mA), you should set the current strength settings to 2 mA. Setting at lower current strength may not meet the IOL and IOH specifications in the
datasheet.
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Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications
Table 15: Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications for Arria 10 Devices—Preliminary
VCCIO (V)
Typ
VREF (V)
Typ
VTT (V)
Typ
I/O Standard
Min
Max
Min
Max
Min
Max
SSTL-18
1.71
1.8
1.89
0.833
0.9
0.969
VREF – 0.04
VREF
VREF + 0.04
Class I, II
SSTL-15
1.425
1.5
1.575
0.49 × VCCIO 0.5 × VCCIO 0.51 × VCCIO 0.49 × VCCIO 0.5 × VCCIO
0.51 × VCCIO
Class I, II
SSTL-135
SSTL-125
SSTL-12
1.283
1.19
1.14
1.71
1.35
1.25
1.2
1.418
1.31
1.26
1.89
0.49 × VCCIO 0.5 × VCCIO 0.51 × VCCIO 0.49 × VCCIO 0.5 × VCCIO
0.49 × VCCIO 0.5 × VCCIO 0.51 × VCCIO 0.49 × VCCIO 0.5 × VCCIO
0.49 × VCCIO 0.5 × VCCIO 0.51 × VCCIO 0.49 × VCCIO 0.5 × VCCIO
0.51 × VCCIO
0.51 × VCCIO
0.51 × VCCIO
—
HSTL-18
Class I, II
1.8
0.85
0.9
0.95
—
—
—
VCCIO/2
VCCIO/2
VCCIO/2
HSTL-15
Class I, II
1.425
1.14
1.5
1.2
1.575
1.26
0.68
0.75
0.9
—
—
HSTL-12
Class I, II
0.47 × VCCIO 0.5 × VCCIO 0.53 × VCCIO
HSUL-12
POD12
1.14
1.16
1.2
1.2
1.3
0.49 × VCCIO 0.5 × VCCIO 0.51 × VCCIO
0.69 × VCCIO 0.7 × VCCIO 0.71 × VCCIO
—
—
—
—
—
1.24
VCCIO
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Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications
Table 16: Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications for Arria 10 Devices—Preliminary
VIL(DC) (V)
Max
VIH(DC) (V)
VIL(AC) (V)
Max
VIH(AC) (V)
Min
VOL (V)
Max
VOH (V)
Min
(23)
(23)
IOL
IOH
I/O Standard
(mA)
(mA)
Min
Min
Max
SSTL-18
Class I
–0.3 VREF –0.125 VREF + 0.125 VCCIO + 0.3
VREF – 0.25
VREF + 0.25
VTT – 0.603
VTT + 0.603
6.7
–6.7
SSTL-18
Class II
–0.3 VREF –0.125 VREF + 0.125 VCCIO + 0.3
VREF – 0.25
VREF + 0.25
0.28
VCCIO –0.28 13.4
–13.4
–8
SSTL-15
Class I
—
—
VREF – 0.1
VREF – 0.1
VREF + 0.1
VREF + 0.1
—
—
VREF – 0.175 VREF + 0.175 0.2 × VCCIO
VREF – 0.175 VREF + 0.175 0.2 × VCCIO
0.8 × VCCIO
0.8 × VCCIO
8
SSTL-15
Class II
16
–16
SSTL-135
SSTL-125
SSTL-12
—
—
—
—
VREF – 0.09
VREF – 0.09
VREF – 0.10
VREF –0.1
VREF + 0.09
VREF + 0.09
VREF + 0.10
VREF + 0.1
—
—
—
—
VREF – 0.16
VREF – 0.15
VREF – 0.15
VREF – 0.2
VREF + 0.16
VREF + 0.15
VREF + 0.15
VREF + 0.2
0.2 × VCCIO
0.2 × VCCIO
0.2 × VCCIO
0.4
0.8 × VCCIO
0.8 × VCCIO
0.8 × VCCIO
VCCIO – 0.4
—
—
—
8
—
—
—
–8
HSTL-18
Class I
HSTL-18
Class II
—
—
—
VREF – 0.1
VREF – 0.1
VREF – 0.1
VREF + 0.1
VREF + 0.1
VREF + 0.1
—
—
—
VREF – 0.2
VREF – 0.2
VREF – 0.2
VREF + 0.2
VREF + 0.2
VREF + 0.2
0.4
0.4
0.4
VCCIO – 0.4
VCCIO – 0.4
VCCIO –0.4
16
8
–16
–8
HSTL-15
Class I
HSTL-15
Class II
16
8
–16
–8
HSTL-12
Class I
–0.15 VREF – 0.08
VREF + 0.08 VCCIO + 0.15 VREF – 0.15
VREF + 0.15 0.25 × VCCIO 0.75 × VCCIO
(23)
To meet the IOL and IOH specifications, you must set the current strength settings accordingly. For example, to meet the SSTL15CI specification
(8 mA), you should set the current strength settings to 8 mA. Setting at lower current strength may not meet the IOL and IOH specifications in the
datasheet.
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Differential SSTL I/O Standards Specifications
VIL(DC) (V)
VIH(DC) (V)
VIL(AC) (V)
Max
VIH(AC) (V)
Min
VOL (V)
Max
VOH (V)
Min
(23)
(23)
IOL
IOH
I/O Standard
(mA)
(mA)
Min
Max
Min
Max
HSTL-12
Class II
–0.15 VREF – 0.08
VREF + 0.08 VCCIO + 0.15 VREF – 0.15
VREF + 0.15 0.25 × VCCIO 0.75 × VCCIO
16
–16
HSUL-12
POD12
—
VREF – 0.13
VREF + 0.13
—
VREF – 0.22
VREF + 0.22 0.1 × VCCIO 0.9 × VCCIO
—
—
—
—
–0.15 VREF – 0.08
VREF + 0.08 VCCIO + 0.15 VREF – 0.15
VREF + 0.15 (0.7 – 0.15) × (0.7 + 0.15) ×
VCCIO
VCCIO
Differential SSTL I/O Standards Specifications
Table 17: Differential SSTL I/O Standards Specifications for Arria 10 Devices—Preliminary
VCCIO (V)
Typ
VSWING(DC) (V)
VSWING(AC) (V)
VIX(AC) (V)
I/O Standard
Min
Max
Min
Max
Min
Max
Min
Typ
Max
SSTL-18
1.71
1.8
1.89
0.25
VCCIO + 0.6
0.5
VCCIO + 0.6
VCCIO/2 –
0.175
—
VCCIO/2 + 0.175
VCCIO/2 + 0.15
VCCIO/2 + 0.15
VCCIO/2 + 0.15
VREF + 0.15
Class I, II
(24)
(24)
(24)
(24)
SSTL-15
1.425
1.283
1.19
1.5
1.35
1.25
1.2
1.575
1.45
1.31
1.26
1.24
0.2
2(VIH(AC)
–
–
–
–
2(VREF
–
)
VCCIO/2 –
0.15
—
Class I, II
VREF)
VIL(AC)
SSTL-135
SSTL-125
SSTL-12
POD12
(23)
0.18
0.18
0.16
0.16
2(VIH(AC)
VREF
2(VIL(AC)
VREF
–
–
–
VCCIO/2 –
0.15
VCCIO/2
VCCIO/2
VCCIO/2
—
)
)
2(VIH(AC)
VREF
2(VIL(AC)
VREF
VCCIO/2 –
0.15
)
)
1.14
2(VIH(AC)
2(VIL(AC)
VREF – 0.15
VREF
0.3
)
VREF
—
)
1.16
1.2
—
VREF – 0.08
VREF + 0.08
To meet the IOL and IOH specifications, you must set the current strength settings accordingly. For example, to meet the SSTL15CI specification
(8 mA), you should set the current strength settings to 8 mA. Setting at lower current strength may not meet the IOL and IOH specifications in the
datasheet.
(24)
The maximum value for VSWING(DC) is not defined. However, each single-ended signal needs to be within the respective single-ended limits (VIH(DC)
and VIL(DC)).
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Differential HSTL and HSUL I/O Standards Specifications
Differential HSTL and HSUL I/O Standards Specifications
Table 18: Differential HSTL and HSUL I/O Standards Specifications for Arria 10 Devices—Preliminary
VCCIO (V)
Typ
VDIF(DC) (V)
VDIF(AC) (V)
VIX(AC) (V)
Typ
VCM(DC) (V)
I/O Standard
Min
Max
Min
Max
Min
Max
Min
Max
Min
Typ
Max
HSTL-18 1.71
Class I, II
1.8
1.89
0.2
—
0.4
0.4
0.3
—
0.78
—
1.12
0.78
—
1.12
HSTL-15 1.425 1.5 1.575
Class I, II
0.2
—
—
0.68
—
—
0.9
—
0.68
—
0.9
HSTL-12 1.14
Class I, II
1.2
1.26
0.16
VCCIO
0.3
+
VCCIO
0.48
+
–
0.5 ×
0.4 ×
0.5 ×
0.6 ×
VCCIO
VCCIO VCCIO
VCCIO
HSUL-12 1.14
1.2
1.3
2(VIH(DC) 2(VREF
–
2(VIH(AC) 2(VREF
– VREF
0.5 ×
VCCIO
0.12
0.5 ×
0.5 ×
VCCIO
+0.12
0.4 ×
0.5 ×
0.6 ×
– VREF VIH(DC)
)
)
)
VIH(AC)
)
–
VCCIO
VCCIO VCCIO
VCCIO
Differential I/O Standards Specifications
Table 19: Differential I/O Standards Specifications for Arria 10 Devices—Preliminary
Differential inputs are powered by VCCPT which requires 1.8 V.
(26)
(26)
VCCIO (V)
VID (mV) (25)
VICM(DC) (V)
Condition
VOD (V)
Typ
VOCM (V)
Typ
I/O Standard
Min
Typ
Max
Min
Condition Max
Min
Max
Min
Max
Min
Max
PCML
Transmitter, receiver, and input reference clock pins of high-speed transceivers use the CML I/O standard. For transmitter, receiver, and
reference clock I/O pin specifications, refer to Transceiver Specifications for Arria 10 GX, SX, and GT Devices table.
(25)
The minimum VID value is applicable over the entire common mode range, VCM
RL range: 90 ≤ RL ≤ 110 Ω.
.
(26)
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Switching Characteristics
(26)
(26)
VCCIO (V)
VID (mV) (25)
VICM(DC) (V)
Condition
VOD (V)
Typ
VOCM (V)
Typ
I/O Standard
Min
Typ
Max
Min
Condition Max
Min
Max
Min
0.247
0.1
Max
Min
Max
0
DMAX
1.85
≤700 Mbps
VCM
=
(27)
LVDS
1.71
1.8
1.89
100
—
—
0.6
1.125 1.25
1.375
1.25 V
1
DMAX
>
1.6
1.4
700 Mbps
—
RSDS (HIO) 1.71
1.8
1.8
1.89
1.89
100
200
VCM
=
—
0.3
0.4
0.6
1
0.2
—
0.6
0.5
1
1.2
1.2
1.4
1.4
(28)
1.25 V
—
Mini-LVDS
(HIO) (29)
1.71
600
—
1.325 0.25
1.7
600
DMAX
≤700 Mbps
LVPECL (30)
1.71
1.8
1.89
300
—
—
—
—
—
—
—
—
DMAX
>
1.6
700 Mbps
Related Information
Transceiver Specifications for Arria 10 GX, SX, and GT Devices on page 29
Provides the specifications for transmitter, receiver, and reference clock I/O pin.
Switching Characteristics
This section provides the performance characteristics of Arria 10 core and periphery blocks for extended grade devices.
(25)
(26)
(27)
The minimum VID value is applicable over the entire common mode range, VCM
RL range: 90 ≤ RL ≤ 110 Ω.
.
For optimized LVDS receiver performance, the receiver voltage input range must be within 1.0 V to 1.6 V for data rates above 700 Mbps and 0 V to
1.85 V for data rates below 700 Mbps.
(28)
(29)
(30)
For optimized RSDS receiver performance, the receiver voltage input range must be within 0.3 V to 1.4 V.
For optimized Mini-LVDS receiver performance, the receiver voltage input range must be within 0.4 V to 1.325 V.
For optimized LVPECL receiver performance, the receiver voltage input range must be within 0.85 V to 1.75 V for data rates above 700 Mbps and
0.45 V to 1.95 V for data rates below 700 Mbps.
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Transceiver Performance Specifications
Transceiver Performance Specifications
Transceiver Performance for Arria 10 GX/SX Devices
Table 20: Transmitter and Receiver Data Rate Performance—Preliminary
Symbol/Description
Transceiver
Transceiver
Transceiver
Transceiver
Transceiver
Condition
Speed Grade 5
Unit
Speed Grade 1 Speed Grade 2 Speed Grade 3 Speed Grade 4
(31)
Maximum data rate
17.4
11.3
15
14.2
12.5
11.3
8
8
Gbps
VCCR_GXB = VCCT_GXB
= 1.03 V
Chip-to-Chip (32) Maximum data rate
11.3
11.3
1.0 (33)
12.5
Gbps
Gbps
Gbps
VCCR_GXB = VCCT_GXB
= 0.95 V
Minimum Data Rate
Maximum data rate
16
14.2
10.3125
10.3125
6.5536
6.5536
VCCR_GXB = VCCT_GXB
= 1.03 V
Backplane (32)
Maximum data rate
10.3125
10.3125
10.3125
1.0 (33)
Gbps
Gbps
VCCR_GXB = VCCT_GXB
= 0.95 V
Minimum Data Rate
Transceiver speed grade 5 supports PCI Express® (PCIe®) Gen3.
Backplane applications assume advanced equalization circuitry, such as decision feedback equalization (DFE), is enabled to compensate for signal
impairments. Chip-to-chip links are assumed to be applications with short reach channels that do not require DFE.
Arria 10 transceivers can support data rates down to 125 Mbps with over sampling.
(31)
(32)
(33)
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Transceiver Performance for Arria 10 GX/SX Devices
Table 21: ATX PLL Performance—Preliminary
Symbol/Descrip‐
tion
Transceiver
Speed Grade 1
Transceiver
Speed Grade 2
Transceiver
Speed Grade 3
Transceiver
Speed Grade 4
Transceiver
Speed Grade 5
Condition
Unit
GHz
MHz
Maximum
Frequency
8.7
7.5
7.1
6.25
4
Supported
Output
Frequency
Minimum
Frequency
500
Table 22: Fractional PLL Performance—Preliminary
Symbol/
Description
Transceiver
Speed Grade 1
Transceiver
Speed Grade 2
Transceiver
Speed Grade 3
Transceiver
Speed Grade 4
Transceiver
Speed Grade 5
Condition
Unit
GHz
MHz
Maximum
Frequency
6.25
6.25
6.25
500
6.25
4
Supported
Output
Frequency
Minimum
Frequency
Table 23: CMU PLL Performance—Preliminary
Symbol/
Description
Transceiver
Speed Grade 1
Transceiver
Speed Grade 2
Transceiver
Speed Grade 3
Transceiver
Speed Grade 4
Transceiver
Speed Grade 5
Condition
Unit
GHz
MHz
Maximum
Frequency
5.15625
5.15625
5.15625
500
5.15625
4
Supported
Output
Frequency
Minimum
Frequency
Related Information
Transceiver Power Supply Operating Conditions on page 6
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High-Speed Serial Transceiver-Fabric Interface Performance for Arria 10...
High-Speed Serial Transceiver-Fabric Interface Performance for Arria 10 GX/SX Devices
Table 24: High-Speed Serial Transceiver-Fabric Interface Performance for Arria 10 GX/SX Devices—Preliminary
Core Speed Grade with Power Options
Symbol/Description
Condition (V)
Unit
-E1M /
-I1M
-E1L / -E1S / -I1L
-E2L / -I2L
-E3S /
-I3S / M3
20-bit interface - FIFO
VCC = 0.9
VCC = 0.9
VCC = 0.9
VCC = 0.9
VCC = 0.9
VCC = 0.9
VCC = 0.9
VCC = 0.83
VCC = 0.83
VCC = 0.83
VCC = 0.83
VCC = 0.83
VCC = 0.83
VCC = 0.83
516
491
441
441
272
272
300
400
400
335
335
222
222
250
516
491
441
441
272
272
300
—
400
400
404
404
234
234
250
—
400
400
335
335
222
222
250
—
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
20-bit interface - Registered
32-bit interface - FIFO
32-bit interface - Registered
64-bit interface - FIFO
64-bit interface - Registered
PCIe Gen3 HIP-Fabric interface
20-bit interface - FIFO
20-bit interface - Registered
32-bit interface - FIFO
—
—
—
—
—
—
32-bit interface - Registered
64-bit interface - FIFO
—
—
—
—
—
—
64-bit interface - Registered
PCIe Gen3 HIP-Fabric interface
—
—
—
—
—
—
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Transceiver Performance for Arria 10 GT Devices
Transceiver Performance for Arria 10 GT Devices
Table 25: Transmitter and Receiver Data Rate Performance—Preliminary
Symbol/Description
Condition
Transceiver
Transceiver
Transceiver
Unit
Speed Grade 2 Speed Grade 3 Speed Grade 4
Maximum data rate
GT Channel
28.3/28.1 (36)
17.4
26
15
20
15
Gbps
Gbps
(35)
VCCR_GXB = VCCT_GXB = 1.12
V
GX Channel
GX Channel
Maximum data rate
15
14.2
12.5
11.3
Gbps
VCCR_GXB = VCCT_GXB = 1.03
V
Chip-to-chip (34)
Maximum data rate
GX Channel
11.3
11.3
Gbps
Gbps
VCCR_GXB = VCCT_GXB = 0.95
V
GT Channel
GX Channel
Minimum data rate
1.0 (37)
(34)
Backplane applications assume advanced equalization circuitry, such as decision feedback equalization (DFE), is enabled to compensate for signal
impairments. Chip-to-chip links are assumed to be applications with short reach channels that do not require DFE.
GT channels are only available when VCCT_GXB = 1.12 V and VCCR_GXB = 1.12 V.
(35)
(36)
To achieve 28.3 Gbps, you must use a -1 core speed grade and a -2 transceiver speed grade device configuration. To achieve 28.1 Gbps, you must use
a -2 core speed grade and a -2 transceiver speed grade device configuration.
(37)
Arria 10 transceivers can support data rates down to 125 Mbps with over sampling.
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Transceiver Performance for Arria 10 GT Devices
Symbol/Description
Condition
Transceiver
Transceiver
Transceiver
Unit
Speed Grade 2 Speed Grade 3 Speed Grade 4
Maximum data rate
GX Channel
GX Channel
17.4
14.2
14.2
12.5
14.2
Gbps
VCCR_GXB = VCCT_GXB = 1.12
V
Maximum data rate
10.3125
10.3125
Gbps
VCCR_GXB = VCCT_GXB = 1.03
V
Backplane (34)
Maximum data rate
GX Channel
GX Channel
10.3125
10.3125
1.0 (37)
Gbps
Gbps
VCCR_GXB = VCCT_GXB = 0.95
V
Minimum data rate
Table 26: ATX PLL Performance—Preliminary
Symbol/Description
Condition
Transceiver Speed
Grade 2
Transceiver Speed
Grade 3
Transceiver Speed
Grade 4
Unit
Maximum frequency
Minimum frequency
14.15
13
10
GHz
MHz
Supported Output
Frequency
500
Table 27: Fractional PLL Performance—Preliminary
Symbol/Description
Condition
Transceiver Speed
Grade 2
Transceiver Speed
Grade 3
Transceiver Speed
Grade 4
Unit
Maximum frequency
Minimum frequency
6.25
500
GHz
MHz
Supported Output
Frequency
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High-Speed Serial Transceiver-Fabric Interface Performance for Arria 10...
Table 28: CMU PLL Performance—Preliminary
Symbol/Description
Condition
Transceiver Speed
Grade 2
Transceiver Speed
Grade 3
Transceiver Speed
Grade 4
Unit
Maximum frequency
Minimum frequency
5.15625
5.15625
500
5.15625
GHz
MHz
Supported Output
Frequency
Related Information
Transceiver Power Supply Operating Conditions on page 6
High-Speed Serial Transceiver-Fabric Interface Performance for Arria 10 GT Devices
Table 29: High-Speed Serial Transceiver-Fabric Interface Performance for Arria 10 GT Devices—Preliminary
Core Speed Grade with Power Options
Symbol/Description
Condition (V)
Unit
-1
-2
-3
20-bit interface - FIFO
VCC = 0.9
VCC = 0.9
VCC = 0.9
VCC = 0.9
VCC = 0.9
VCC = 0.9
VCC = 0.9
516
491
441
441
439
439
300
400
400
404
404
407
407
250
400
400
335
335
313
313
250
MHz
MHz
MHz
MHz
MHz
MHz
MHz
20-bit interface - Registered
32-bit interface - FIFO
32-bit interface - Registered
64-bit interface - FIFO
64-bit interface - Registered
PCIe Gen3 HIP-Fabric interface
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Transceiver Specifications for Arria 10 GX, SX, and GT Devices
Transceiver Specifications for Arria 10 GX, SX, and GT Devices
Table 30: Reference Clock Specifications—Preliminary
Transceiver Speed Grades 1, 2, 3, 4, and 5
Symbol/Description
Condition
Unit
Min
Typ
Max
Dedicated reference clock
pin
CML, Differential LVPECL, LVDS, and HCSL
Supported I/O Standards
RX reference clock pin
CML, Differential LVPECL, and LVDS
Input Reference Clock Frequency (CMU
PLL)
61
100
20
—
—
—
800
800
800
MHz
MHz
MHz
Input Reference Clock Frequency (ATX
PLL)
Input Reference Clock Frequency (fPLL
PLL)
Rise time
Fall time
Duty cycle
20% to 80%
80% to 20%
—
—
—
45
30
—
—
—
—
400
400
55
ps
ps
%
Spread-spectrum modulating clock
frequency
33
kHz
PCIe
Spread-spectrum downspread
On-chip termination resistors
PCIe
—
—
—
—
0 to –0.5
100
—
—
%
Ω
V
Dedicated reference clock
pin
—
1.6
Absolute VMAX
RX reference clock pin
—
—
—
—
1.2
—
V
V
Absolute VMIN
—
—
–0.4
200
Peak-to-peak differential input voltage
1600
mV
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Transceiver Specifications for Arria 10 GX, SX, and GT Devices
Transceiver Speed Grades 1, 2, 3, 4, and 5
Symbol/Description
Condition
Unit
Min
—
Typ
0.95
1.03
1.12
—
Max
—
VCCR_GXB = 0.95 V
VCCR_GXB = 1.03 V
VCCR_GXB = 1.12 V
V
V
VICM (AC coupled)
—
—
—
—
V
VICM (DC coupled)
HCSL I/O standard for
PCIe reference clock
250
550
mV
100 Hz
1 kHz
—
—
—
—
—
—
—
—
—
—
—
—
–70
–90
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ps (rms)
Transmitter REFCLKPhase Noise (622
10 kHz
100 kHz
≥ 1 MHz
–100
–110
–120
4.2
MHz) (38)
Transmitter REFCLKPhase Jitter (100
MHz)
1.5 to 100 MHz (PCIe)
RREF
—
—
2.0 k 1%
—
Ω
TSSC-MAX-PERIOD-SLEW
Max SSC df/dt
0.75
Table 31: Transceiver Clocks Specifications—Preliminary
Transceiver Speed Grades 1, 2, 3, 4, and 5
Typ
Symbol/Description
Condition
Unit
Min
Max
CLKUSRpin for
transceiver
calibration
Transceiver
Calibration
100
—
125
MHz
(38)
To calculate the REFCLKphase noise requirement at frequencies other than 622 MHz, use the following formula: REFCLKphase noise at f (MHz) =
REFCLKphase noise at 622 MHz + 20*log(f/622).
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Transceiver Specifications for Arria 10 GX, SX, and GT Devices
Transceiver Speed Grades 1, 2, 3, 4, and 5
Symbol/Description
Condition
Unit
Min
Typ
Max
Reconfiguration
interface
reconfig_clk
100
—
125
MHz
Table 32: Transceiver Clock Network Maximum Data Rate Specifications
Maximum Performance
Clock Network
Channel Span
Unit
ATX (39)
17.4
fPLL
12.5
12.5
12.5
10.5
CMU
10.3125
N/A
x1
6 channels
6 channels
Side-wide
Gbps
Gbps
Gbps
Gbps
x6
17.4
x6 PLL feedback
xN at 0.95 V
17.4
N/A
10.5
N/A
Up two banks and
down two banks
xN at 1.03 V
xN at 1.12 V
15.0
16.0
12.5
12.5
N/A
N/A
Up two banks and
down two banks
Gbps
Gbps
Up two banks and
down two banks
Table 33: Receiver Specifications—Preliminary
Transceiver Speed Grades 1, 2, 3, 4, and 5
Typ
Symbol/Description
Condition
Unit
Min
Max
Supported I/O
Standards
—
—
High Speed Differential I/O, CML, Differential LVPECL, and LVDS
1.2 V
Absolute VMAX for
a receiver pin (40)
—
—
(39)
ATX maximum data rate support per speed grade.
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Transceiver Specifications for Arria 10 GX, SX, and GT Devices
Transceiver Speed Grades 1, 2, 3, 4, and 5
Typ
Symbol/Description
Condition
Unit
Min
Max
Absolute VMIN for
a receiver pin (40)
—
—
-0.4
—
—
V
Maximum peak-
to-peak differen‐
tial input voltage
VID (diff p-p)
—
—
1.6
V
before device
configuration (41)
Maximum peak-
to-peak differen‐
tial input voltage
VID (diff p-p) after
VCCR_GXB = 1.12 V
VCCR_GXB = 1.03 V
—
—
—
—
2.0
2.0
V
V
device configura‐ VCCR_GXB = 0.95 V
—
—
2.4
V
tion (41)
Minimum
differential eye
opening at
—
50
—
—
mV
receiver serial
input pins (42)
Differential on-
chip termination
resistors
85-Ω setting
100-Ω setting
—
—
85 30%
—
—
Ω
Ω
100 30%
(40)
The device cannot tolerate prolonged operation at this absolute maximum.
DC coupling specifications are pending silicon characterization.
The differential eye opening specification at the receiver input pins assumes that Receiver Equalization is disabled. If you enable Receiver Equaliza‐
tion, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.
(41)
(42)
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Transceiver Specifications for Arria 10 GX, SX, and GT Devices
Transceiver Speed Grades 1, 2, 3, 4, and 5
Symbol/Description
Condition
Unit
Min
—
Typ
600
700
700
—
Max
—
VCCR_GXB = 0.95 V
VCCR_GXB = 1.03 V
VCCR_GXB = 1.12 V
—
mV
mV
mV
µs
VICM (AC and DC
coupled)
—
—
—
—
(43)
tLTR
—
10
(44)
tLTD
—
4
—
—
µs
(45)
tLTD_manual
—
4
—
—
µs
(46)
tLTR_LTD_manual
—
15
—
—
µs
Run Length
—
—
—
200
300
1000
—
UI
PCIe-only
-300
-1000
—
—
PPM
PPM
dB
CDR PPM
tolerance
All other protocols
DC Gain Setting = 0
DC Gain Setting = 1
DC Gain Setting = 2
DC Gain Setting = 3
DC Gain Setting = 4
—
-10
-6.5
-3
—
—
dB
Programmable DC
Gain
—
—
dB
—
0.5
4
—
dB
—
—
dB
(43)
(44)
(45)
tLTR is the time required for the receive CDR to lock to the input reference clock frequency after coming out of reset.
tLTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodatasignal goes high.
tLTD_manual is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodatasignal goes high when the CDR is
functioning in the manual mode.
tLTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtorefsignal goes high when the
CDR is functioning in the manual mode.
(46)
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Transceiver Specifications for Arria 10 GX, SX, and GT Devices
Table 34: Transmitter Specifications—Preliminary
Transceiver Speed Grades 1, 2, 3, 4, and 5
Typ
Symbol/Description
Condition
Unit
Min
Max
Supported I/O
Standards
—
High Speed Differential I/O (47)
—
85-Ω setting
100-Ω setting
120-Ω setting
150-Ω setting
VCCT = 0.95 V
VCCT = 1.03 V
VCCT = 1.12 V
VCCT = 0.95 V
VCCT = 1.03 V
VCCT = 1.12 V
20% to 80%
—
—
—
—
—
—
—
—
—
—
20
20
85 20%
100 20%
120 20%
150 20%
450
—
—
Ω
Ω
Differential on-
chip termination
resistors
—
Ω
—
Ω
—
mV
mV
mV
mV
mV
mV
ps
VOCM (AC
coupled)
500
—
550
—
450
—
VOCM (DC
coupled)
500
—
550
—
Rise time (48)
Fall time (48)
—
130
130
80% to 20%
—
ps
Intra-differential TX VCM = 0.5 V and
pair skew(49)
slew rate of 15 ps
—
—
15
ps
(47)
(48)
(49)
High Speed Differential I/O is the dedicated I/O standard for the transmitter in Arria 10 transceivers.
The Quartus Prime software automatically selects the appropriate slew rate depending on the configured data rate or functional mode.
In QPI mode, if VCM < 0.17 V, the input Vid must be greater than 100 mV. If VCM > 0.17 V, the input Vid must be greater than 70 mV.
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Transceiver Specifications for Arria 10 GX, SX, and GT Devices
Table 35: Typical Transmitter VOD Settings—Preliminary
Symbol
VOD Setting
VOD/VCCT Ratio
1.00
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
0.97
0.93
0.90
0.87
0.83
0.80
0.77
0.73
0.70
VOD differential value = VOD/VCCT ratio x
VCCT
0.67
0.63
0.60
0.57
0.53
0.50
0.47
0.43
0.40
0.37
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Core Performance Specifications
Core Performance Specifications
Clock Tree Specifications
Table 36: Clock Tree Performance for Arria 10 Devices—Preliminary
Performance
Parameter
Unit
–E1L,–E1M (50), –E1S, –I1L,
–I1M (50), –I1S
–E2L, –E2S, –I2L, –I2S
–E1M (51), –I1M (51), –E3S,
–I3S
Global clock, regional clock, and small
periphery clock
644
644
525
644
MHz
MHz
Large periphery clock
525
525
PLL Specifications
Fractional PLL Specifications
Table 37: Fractional PLL Specifications for Arria 10 Devices—Preliminary
Symbol
Parameter
Condition
Min
30
Typ
—
Max
800
700
Unit
fIN
fINPFD
Input clock frequency
—
—
MHz
MHz
Input clock frequency to the phase
frequency detector (PFD)
30
—
fVCO
PLL voltage-controlled oscillator
(VCO) operating range
—
—
3.5
45
—
—
7.05
55
GHz
%
tEINDUTY
Input clock duty cycle
(50)
(51)
(52)
When you power VCC and VCCP at nominal voltage of 0.90 V.
When you power VCC and VCCP at lower voltage of 0.83 V.
This specification is limited in the Quartus Prime software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O
standard.
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Fractional PLL Specifications
Symbol
Parameter
Condition
Min
Typ
Max
Unit
fOUT
Output frequency for internal global
or regional clock
—
—
—
644
MHz
fDYCONFIGCLK Dynamic configuration clock for
—
—
—
—
—
—
100
1
MHz
ms
reconfig_clk
tLOCK
Time required to lock from end-of-
device configuration or deassertion of
pll_powerdown
tDLOCK
Time required to lock dynamically
(after switchover or reconfiguring any
non-post-scale counters/delays)
—
—
—
1
ms
fCLBW
PLL closed-loop bandwidth
Accuracy of PLL phase shift
—
—
—
—
—
10
TBD
—
—
50
—
MHz
ps
tPLL_PSERR
tARESET
Minimum pulse width on the pll_
powerdownsignal
—
ns
FREF ≥ 100 MHz
FREF < 100 MHz
FOUT ≥ 100 MHz
FOUT < 100 MHz
FOUT ≥ 100 MHz
FOUT < 100 MHz
FOUT ≥ 100 MHz
FOUT < 100 MHz
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
UI (p-p)
ps (p-p)
(53)(54)
tINCCJ
Input clock cycle-to-cycle jitter
ps (p-p)
Period jitter for clock output in
fractional mode
(55)
tFOUTPJ
mUI (p-p)
ps (p-p)
Cycle-to-cycle jitter for clock output
in fractional mode
(55)
tFOUTCCJ
mUI (p-p)
ps (p-p)
Period jitter for clock output in
integer mode
(55)
tOUTPJ
mUI (p-p)
(53)
A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter
< 120 ps.
(54)
(55)
FREF is fIN/N, specification applies when N = 1.
External memory interface clock output jitter specifications use a different measurement method, which are available in Memory Output Clock Jitter
Specification for Arria 10 Devices table.
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I/O PLL Specifications
Symbol
Parameter
Condition
FOUT ≥ 100 MHz
FOUT < 100 MHz
—
Min
—
Typ
—
Max
TBD
TBD
—
Unit
ps (p-p)
mUI (p-p)
bit
Cycle-to-cycle jitter for clock output
in integer mode
(55)
tOUTCCJ
dKBIT
—
—
Bit number of Delta Sigma Modulator
(DSM)
—
32
Related Information
Memory Output Clock Jitter Specifications on page 58
Provides more information about the external memory interface clock output jitter specifications.
I/O PLL Specifications
Table 38: I/O PLL Specifications for Arria 10 Devices—Preliminary
Symbol
Parameter
Condition
–1 speed grade
–2 speed grade
–3 speed grade
—
Min
10
Typ
—
—
—
—
—
—
—
—
—
Max
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
%
800 (56)
700 (56)
650 (56)
325
fIN
Input clock frequency
10
10
fINPFD
Input clock frequency to the PFD
PLL VCO operating range
10
–1 speed grade
–2 speed grade
–3 speed grade
—
600
600
600
0.1
40
1600
1434
1250
8
fVCO
fCLBW
PLL closed-loop bandwidth
tEINDUTY
Input clock or external feedback clock
input duty cycle
—
60
fOUT
Output frequency for internal global or
–1, –2, –3 speed
grade
—
—
644
MHz
regional clock (Ccounter)
(56)
This specification is limited in the Quartus Prime software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O
standard.
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I/O PLL Specifications
Symbol
Parameter
Condition
–1 speed grade
–2 speed grade
–3 speed grade
—
Min
—
Typ
—
Max
800
720
650
55
Unit
MHz
MHz
MHz
%
Output frequency for external clock
output
fOUT_EXT
—
—
—
—
tOUTDUTY
tFCOMP
fDYCONFIGCLK
tLOCK
Duty cycle for dedicated external clock
output (when set to 50%)
45
50
External feedback clock compensation
time
—
—
—
—
—
—
—
—
—
10
100
1
ns
MHz
ms
Dynamic configuration clock for
mgmt_clkand scanclk
Time required to lock from end-of-
device configuration or deassertion of
areset
tDLOCK
Time required to lock dynamically
(after switchover or reconfiguring any
non-post-scale counters/delays)
—
—
—
1
ms
tPLL_PSERR
tARESET
Accuracy of PLL phase shift
—
—
—
10
—
—
50
—
ps
ns
Minimum pulse width on the areset
signal
FREF ≥ 100 MHz
FREF < 100 MHz
FOUT ≥ 100 MHz
FOUT < 100 MHz
FOUT ≥ 100 MHz
FOUT < 100 MHz
—
—
—
—
—
—
—
—
—
—
—
—
TBD
TBD
TBD
TBD
TBD
TBD
UI (p-p)
ps (p-p)
(57)(58)
tINCCJ
Input clock cycle-to-cycle jitter
ps (p-p)
tOUTPJ_DC
Period jitter for dedicated clock output
mUI (p-p)
ps (p-p)
Cycle-to-cycle jitter for dedicated clock
output
tOUTCCJ_DC
mUI (p-p)
(57)
(58)
A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter
< 120 ps.
FREF is fIN/N, specification applies when N = 1.
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DSP Block Specifications
Symbol
Parameter
Condition
Min
—
—
—
—
—
—
Typ
—
—
—
—
—
—
Max
TBD
TBD
TBD
TBD
TBD
TBD
Unit
FOUT ≥ 100 MHz
FOUT < 100 MHz
FOUT ≥ 100 MHz
FOUT < 100 MHz
FOUT ≥ 100 MHz
FOUT < 100 MHz
ps (p-p)
mUI (p-p)
ps (p-p)
Period jitter for clock output on the
regular I/O
(59)
tOUTPJ_IO
Cycle-to-cycle jitter for clock output on
the regular I/O
(59)
tOUTCCJ_IO
mUI (p-p)
ps (p-p)
Period jitter for dedicated clock output
in cascaded PLLs
tCASC_OUTPJ_DC
mUI (p-p)
Related Information
Memory Output Clock Jitter Specifications on page 58
Provides more information about the external memory interface clock output jitter specifications.
DSP Block Specifications
Table 39: DSP Block Performance Specifications for Arria 10 Devices (VCC and VCCP at 0.9 V Typical Value)—Preliminary
Performance
Mode
Unit
–E1L, –E1M
(60), –E1S
–I1L, –
–E2L, –E2S, – –I2L, –I2S, –
–E1M (61), –
E3S, –E3V
–I1M (61), –
I3S, –I3V
I1M (60), –I1S
E2V
I2V
Fixed-point 18 × 19 multiplication
mode
548
541
548
528
522
529
456
438
364
358
370
346
344
351
MHz
MHz
MHz
Fixed-point 27 × 27 multiplication
mode
450
459
434
440
Fixed-point 18 × 18 multiplier adder
mode
(59)
External memory interface clock output jitter specifications use a different measurement method, which are available in Memory Output Clock Jitter
Specification for Arria 10 Devices table.
(60)
(61)
When you power VCC and VCCP at nominal voltage of 0.90 V.
When you power VCC and VCCP at lower voltage of 0.83 V.
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DSP Block Specifications
Performance
Mode
Unit
–E1L, –E1M
(60), –E1S
–I1L, –
–E2L, –E2S, – –I2L, –I2S, –
–E1M (61), –
E3S, –E3V
–I1M (61), –
I3S, –I3V
I1M (60), –I1S
E2V
I2V
Fixed-point 18 × 18 multiplier adder
summed with 36-bit input mode
539
517
444
422
349
326
MHz
Fixed-point 18 × 19 systolic mode
Complex 18 × 19 multiplication mode
Floating point multiplication mode
Floating point adder or substract mode
548
548
548
488
483
529
528
527
471
465
459
456
447
388
386
440
438
427
369
368
370
364
347
288
290
351
346
326
266
270
MHz
MHz
MHz
MHz
MHz
Floating point multiplier adder or
substract mode
Floating point multiplier accumulate
mode
510
490
418
393
326
294
MHz
Floating point vector one mode
Floating point vector two mode
502
474
482
455
404
383
382
367
306
293
282
278
MHz
MHz
Table 40: DSP Block Performance Specifications for Arria 10 Devices (VCC and VCCP at 0.95 V Typical Value)—Preliminary
Performance
Mode
Unit
–I1L, –I1M (60), –I1S
–I2L, –I2S
517
Fixed-point 18 × 19 multiplication mode
Fixed-point 27 × 27 multiplication mode
Fixed-point 18 × 18 multiplier adder mode
635
633
635
631
MHz
MHz
MHz
MHz
517
516
Fixed-point 18 × 18 multiplier adder summed with 36-bit input
mode
509
Fixed-point 18 × 19 systolic mode
635
516
MHz
(60)
(61)
When you power VCC and VCCP at nominal voltage of 0.90 V.
When you power VCC and VCCP at lower voltage of 0.83 V.
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Memory Block Specifications
Performance
–I1L, –I1M (60), –I1S
Mode
Unit
–I2L, –I2S
517
Complex 18 × 19 multiplication mode
Floating point multiplication mode
Floating point adder or substract mode
Floating point multiplier adder or substract mode
Floating point multiplier accumulate mode
Floating point vector one mode
635
635
564
564
581
574
550
MHz
MHz
MHz
MHz
MHz
MHz
MHz
501
468
475
482
471
Floating point vector two mode
450
Memory Block Specifications
To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL
and set to 50% output duty cycle. Use the Quartus Prime software to report timing for the memory block clocking schemes.
When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in fMAX
.
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Memory Block Specifications
Table 41: Memory Block Performance Specifications for Arria 10 Devices (VCC and VCCP at 0.9 V Typical Value)—Preliminary
Performance
–E1L,
–E1M (62)
–E1S
–I1, –I1M (62), – –E2L, –E2S, –
–E3S, –
–I1M (63), –I3S,
–I3V
Unit
Memory
Mode
,
I1S
660
660
450
E2V, –I2L, –
I2S, –I2V
E1M (63), –E3V
Single port, all supported widths
(×16/×32)
700
700
460
570
570
400
490
490
330
490
490
330
MHz
MHz
MHz
Simple dual-port, all supported
widths (×16/×32)
MLAB
Simple dual-port with the read-
during-write option set to Old Data,
all supported widths
ROM, all supported width (×16/×32)
Single-port, all supported widths
700
730
730
660
690
690
570
625
625
490
530
530
490
510
510
MHz
MHz
MHz
Simple dual-port, all supported
widths
Simple dual-port with the read-
during-write option set to Old Data,
all supported widths
550
520
470
410
410
MHz
M20K
Block
Simple dual-port with ECC enabled,
512 × 32
470
620
450
590
410
520
360
470
360
470
MHz
MHz
Simple dual-port with ECC and
optional pipeline registers enabled,
512 × 32
True dual port, all supported widths
ROM, all supported widths
730
730
690
690
600
625
480
530
480
510
MHz
MHz
(62)
(63)
When you power VCC and VCCP at nominal voltage of 0.90 V.
When you power VCC and VCCP at lower voltage of 0.83 V.
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Temperature Sensing Diode Specifications
Table 42: Memory Block Performance Specifications for Arria 10 Devices (VCC and VCCP at 0.95 V Typical Value)—Preliminary
Performance
Memory
Mode
–I1L, –I1M (62), –I1S
–I2L, –I2S
610
Unit
Single port, all supported widths (×16/×32)
706
706
482
MHz
MHz
MHz
Simple dual-port, all supported widths (×16/×32)
610
MLAB
Simple dual-port with read and write at the same
address
428
ROM, all supported width (×16/×32)
Single-port, all supported widths
706
735
735
555
610
670
670
500
MHz
MHz
MHz
MHz
Simple dual-port, all supported widths
Simple dual-port with the read-during-write option set
to Old Data, all supported widths
M20K Block
Simple dual-port with ECC enabled, 512 × 32
480
630
440
555
MHz
MHz
Simple dual-port with ECC and optional pipeline
registers enabled, 512 × 32
True dual port, all supported widths
ROM, all supported widths
735
735
640
670
MHz
MHz
Temperature Sensing Diode Specifications
Internal Temperature Sensing Diode Specifications
Table 43: Internal Temperature Sensing Diode Specifications for Arria 10 Devices—Preliminary
Temperature Range
Accuracy
Offset Calibrated Option
Sampling Rate
Conversion Time
Resolution
–40 to 125 °C
5 °C
No
1 MHz
< 5 ms
10 bits
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External Temperature Sensing Diode Specifications
Related Information
Transfer Function for Internal TSD
Provides the transfer function for the internal TSD.
External Temperature Sensing Diode Specifications
Table 44: External Temperature Sensing Diode Specifications for Arria 10 Devices—Preliminary
•
•
•
The typical value is at 25°C.
Diode accuracy improves with lower injection current.
Absolute accuracy is dependent on third party external diode ADC and integration specifics.
Description
Min
10
Typ
—
Max
100
0.9
< 1
—
Unit
μA
V
Ibias, diode source current
Vbias, voltage across diode
Series resistance
0.3
—
—
—
Ω
Diode ideality factor
—
1.03
—
Internal Voltage Sensor Specifications
Table 45: Internal Voltage Sensor Specifications for Arria 10 Devices—Preliminary
Parameter
Minimum
Typical
—
Maximum
Unit
Resolution
—
—
—
—
—
—
—
0.1
6
500
1
Bit
Ksps
LSB
LSB
%
Sampling rate
—
Differential non-linearity (DNL)
Integral non-linearity (INL)
Gain error
—
—
1
—
1
Offset error
—
1
LSB
pF
Input capacitance
Clock frequency
20
—
11
—
MHz
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Periphery Performance Specifications
Parameter
Minimum
Typical
—
Maximum
1.5
Unit
V
Input signal range for Vsigp
0
0
0
Unipolar Input
Mode
Common mode voltage on Vsign
Input signal range for Vsigp – Vsign
—
0.25
V
—
1.25
V
Periphery Performance Specifications
This section describes the periphery performance, high-speed I/O, and external memory interface.
Actual achievable frequency depends on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/
IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.
High-Speed I/O Specifications
Table 46: High-Speed I/O Specifications for Arria 10 Devices—Preliminary
When serializer/deserializer (SERDES) factor J = 3 to 10, use the SERDES block.
For LVDS applications, you must use the PLLs in integer PLL mode.
You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin,
transmitter channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin.
–E1L, –E1M (64), –E1S, –I1L,
–I1M (64), –I1S
–E2L, –E2S, –I2L, –I2S
–E1M (65), –I1M (65), –E3S,
–I3S
Symbol
Condition
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
fHSCLK_in (input clock frequency)
True Differential I/O Standards
Clock boost
factor
10
—
800
10
—
700
10
—
625
MHz
W = 1 to 40 (66)
(64)
(65)
(66)
When you power VCC and VCCP at nominal voltage of 0.90 V.
When you power VCC and VCCP at lower voltage of 0.83 V.
Clock Boost Factor (W) is the ratio between the input data rate and the input clock rate.
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High-Speed I/O Specifications
–E1L, –E1M (64), –E1S, –I1L,
–I1M (64), –I1S
–E2L, –E2S, –I2L, –I2S
–E1M (65), –I1M (65), –E3S,
–I3S
Symbol
Condition
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
fHSCLK_in (input clock frequency)
Single Ended I/O Standards
Clock boost
factor
10
—
625
10
—
625
10
—
525
MHz
W = 1 to 40 (66)
fHSCLK_OUT (output clock
frequency)
—
—
—
800 (67)
—
—
700 (67)
—
—
625 (67)
MHz
(64)
(65)
(67)
When you power VCC and VCCP at nominal voltage of 0.90 V.
When you power VCC and VCCP at lower voltage of 0.83 V.
This is achieved by using the PHY clock network.
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High-Speed I/O Specifications
Symbol
–E1L, –E1M (64), –E1S, –I1L,
–I1M (64), –I1S
–E2L, –E2S, –I2L, –I2S
–E1M (65), –I1M (65), –E3S,
–I3S
Condition
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
(71)
(71)
(71)
SERDES factor
—
1600 (72)
—
1434 (72)
—
1250 (72)
Mbps
J = 4 to 10 (69)(71)
(70)
(71)
(71)
(72)
(71)
(71)
(72)
(71)
(71)
(72)
SERDES factor
J = 3 (69)(71)(70)
—
—
—
—
—
—
Mbps
Mbps
True Differential I/O
Standards - fHSDR
(data rate) (68)
SERDES factor J
= 2, uses DDR
registers
333 (73)
275 (73)
250 (73)
(71)
(71)
(71)
SERDES factor J
= 1, uses DDR
registers
—
—
333 (73)
160
—
—
275 (73)
200
—
—
250 (73)
250
Mbps
ps
Total jitter for
data rate,
—
—
—
Transmitter
600 Mbps –
1.6 Gbps
tx Jitter - True
Differential I/O
Standards
Total jitter for
data rate,
—
45
—
50
0.1
55
—
45
—
50
0.12
55
—
45
—
50
0.15
55
UI
%
< 600 Mbps
(74)
tDUTY
TX output clock
duty cycle for
Differential I/O
Standards
(70)
tRISE & & tFALL
True Differential
I/O Standards
—
—
—
—
160
150
—
—
—
—
180
150
—
—
—
—
200
150
ps
ps
(75)
TCCS (74)(68)
True Differential
I/O Standards
(64)
When you power VCC and VCCP at nominal voltage of 0.90 V.
When you power VCC and VCCP at lower voltage of 0.83 V.
(65)
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High-Speed I/O Specifications
–E1L, –E1M (64), –E1S, –I1L,
–I1M (64), –I1S
–E2L, –E2S, –I2L, –I2S
–E1M (65), –I1M (65), –E3S,
–I3S
Symbol
Condition
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
SERDES factor
—
—
1600
—
—
1434
—
—
1250
Mbps
Mbps
Mbps
Mbps
J = 4 to 10 (69)(71)(70)
True Differential I/O
Standards - fHSDRDPA
(data rate)
(72)
(76)
(73)
(72)
(76)
(73)
(72)
(76)
(73)
SERDES factor
J = 3 (69)(71)(70)
—
—
—
—
—
—
—
—
—
—
—
—
(71)
(71)
(71)
SERDES factor
J = 3 to 10
Receiver
(71)
(71)
(71)
(71)
(71)
(71)
SERDES factor J
= 2, uses DDR
registers
fHSDR (data rate)
(without DPA) (68)
(73)
(73)
(73)
SERDES factor J
= 1, uses DDR
registers
—
—
—
—
—
—
Mbps
UI
DPA (FIFO DPA run length
mode)
—
—
10000
—
10000
—
10000
(68)
(69)
Requires package skew compensation with PCB trace length.
The Fmax specification is based on the fast clock used for serial data. The interface Fmax is also dependent on the parallel clock domain which is design
dependent and requires timing analysis.
(70)
(71)
The VCC and VCCP must be on a combined power layer and a maximum load of 5 pF for chip-to-chip interface.
The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional, or
local) that you use. The I/O differential buffer and serializer do not have a minimum toggle rate.
Pending silicon characterization.
The maximum ideal data rate is the SERDES factor (J) x the PLL maximum output frequency (fOUT) provided you can close the design timing and
the signal integrity meets the interface requirements.
Not applicable for DIVCLK= 1.
This applies to default pre-emphasis and VOD settings only.
(72)
(73)
(74)
(75)
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DPA Lock Time Specifications
Symbol
–E1L, –E1M (64), –E1S, –I1L,
–I1M (64), –I1S
–E2L, –E2S, –I2L, –I2S
–E1M (65), –I1M (65), –E3S,
–I3S
Condition
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
SGMII/GbE
protocol
—
—
5
—
—
5
—
—
5
UI
—
DPA (soft
All other
protocols
—
—
50 data
transition
per 208
UI
—
—
50 data
transition
per 208
UI
—
—
50 data
transition
per 208
UI
DPA run length
CDR mode)
Soft CDR
mode
Soft-CDR ppm
tolerance
—
—
—
—
—
—
300
—
—
—
—
300
—
—
—
—
300
ppm
ps
Non DPA
mode
Sampling Window
300
300
300
DPA Lock Time Specifications
Figure 2: DPA Lock Time Specifications with DPA PLL Calibration Enabled
rx_reset
DPA Lock Time
rx_dpa_locked
256 data
transitions
96 core
clock cycles
256 data
transitions
96 core
clock cycles
256 data
transitions
(64)
(65)
(76)
When you power VCC and VCCP at nominal voltage of 0.90 V.
When you power VCC and VCCP at lower voltage of 0.83 V.
You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board
skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported.
When you power VCC and VCCP at nominal voltage of 0.90 V.
(64)
(65)
When you power VCC and VCCP at lower voltage of 0.83 V.
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DPA Lock Time Specifications
Table 47: DPA Lock Time Specifications for Arria 10 Devices—Preliminary
The specifications are applicable to both commercial and industrial grades. The DPA lock time is for one channel. One data transition is defined as a 0-to-1
or 1-to-0 transition.
Standard
Training Pattern
Number of Data Transitions in Number of Repetitions per
Maximum Data Transition
(77)
One Repetition of the
Training Pattern
256 Data Transitions
SPI-4
00000000001111111111
00001111
2
2
4
8
8
128
128
64
640
640
640
640
640
Parallel Rapid I/O
Miscellaneous
10010000
10101010
32
01010101
32
(77)
This is the number of repetitions for the stated training pattern to achieve the 256 data transitions.
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LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications
LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications
Figure 3: LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications for a Data Rate Equal to 1.6 Gbps
LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification
25
8.5
0.28
0.1
F3
F2
F1
F4
Jitter Frequency (Hz)
Table 48: LVDS Soft-CDR/DPA Sinusoidal Jitter Mask Values for a Data Rate Equal to 1.6 Gbps—Preliminary
Jitter Frequency (Hz)
Sinusoidal Jitter (UI)
F1
F2
F3
F4
10,000
17,565
25.00
25.00
0.28
1,493,000
50,000,000
0.28
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Memory Standards Supported by the Hard Memory Controller
Figure 4: LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications for a Data Rate Less than 1.6 Gbps
Sinusoidal Jitter Amplitude
20db/dec
0.1 UI
P-P
Frequency
20 MHz
baud/1667
Memory Standards Supported by the Hard Memory Controller
Table 49: Memory Standards Supported by the Hard Memory Controller for Arria 10 Devices—Preliminary
This table lists the overall capability of the hard memory controller. For specific details, refer to the External Memory Interface Spec Estimator.
Maximum Frequency (MHz)
Ping Pong PHY
Memory Standard
Rate Support
Speed Grade
Support
LVDS I/O Bank
1,067
1,333
933
3 V I/O Bank
Yes
—
—
—
—
—
—
—
–1
–2
–3
Yes
—
DDR4 SDRAM
Quarter rate
1,067
800
Yes
—
933
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Memory Standards Supported by the Hard Memory Controller
Maximum Frequency (MHz)
LVDS I/O Bank 3 V I/O Bank
Ping Pong PHY
Support
Memory Standard
Rate Support
Speed Grade
Yes
—
467
533
467
533
450
450
333
333
533
533
450
450
333
333
–1
–2
–3
–1
–2
–3
Yes
—
467
Half rate
533
Yes
—
400
533
DDR3 SDRAM
Yes
—
933
1,067
933
Yes
—
Quarter rate
1,067
800
Yes
—
933
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Memory Standards Supported by the Hard Memory Controller
Maximum Frequency (MHz)
Ping Pong PHY
Memory Standard
Rate Support
Speed Grade
Support
LVDS I/O Bank
467
3 V I/O Bank
467
Yes
—
–1
–2
–3
–1
–2
–3
533
533
Yes
—
467
450
Half rate
533
450
Yes
—
400
333
533
333
DDR3L SDRAM
Yes
—
933
533
1,067
833
533
Yes
—
450
Quarter rate
1,067
800
450
Yes
—
333
933
333
–1
–2
–3
–1
–2
–3
—
400
400
Half rate
—
400
400
—
333
333
LPDDR3 SDRAM
—
800
533
Quarter rate
—
800
450
—
667
333
Related Information
External Memory Interface Spec Estimator
Provides the specific details of the memory standards supported.
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Memory Standards Supported by the Soft Memory Controller
Memory Standards Supported by the Soft Memory Controller
Table 50: Memory Standards Supported by the Soft Memory Controller for Arria 10 Devices—Preliminary
This table lists the overall capability of the soft memory controller. For specific details, refer to the External Memory Interface Spec Estimator.
Maximum Frequency (MHz)
Memory Standard
Rate Support
Speed Grade
LVDS I/O Bank
1,200
1,066
933
3 V I/O Bank
533
–1
–2
–3
–1
–2
–3
–1
–2
–3
–1
–2
–3
RLDRAM 3
Quarter rate
450
333
1,066
1,066
933
533
QDR IV SRAM
Quarter rate
Full rate
450
333
333
333
333
333
333
333
QDR II/II+/II+ Xtreme SRAM
633
533
Half rate
550
450
500
333
Related Information
External Memory Interface Spec Estimator
Provides the specific details of the memory standards supported.
(78)
Arria 10 devices support this external memory interface using hard PHY with soft memory controller.
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DLL Range Specifications
DLL Range Specifications
Table 51: DLL Frequency Range Specifications for Arria 10 Devices—Preliminary
Arria 10 devices support memory interface frequencies lower than 667 MHz, although the reference clock that feeds the DLL must be at least 667 MHz. To
support interfaces below 667 MHz, multiply the reference clock feeding the DLL to ensure the frequency is within the supported range.
Parameter
Performance (for All Speed Grades)
Unit
DLL operating frequency range
667 – 1333
MHz
DQS Logic Block Specifications
Table 52: DQS Phase Shift Error Specifications for DLL-Delayed Clock (tDQS_PSERR) for Arria 10 Devices—Preliminary
This error specification is the absolute maximum and minimum error.
Symbol
Performance (for All Speed Grades)
Unit
tDQS_PSERR
5
ps
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Memory Output Clock Jitter Specifications
Memory Output Clock Jitter Specifications
Table 53: Memory Output Clock Jitter Specifications for Arria 10 Devices—Preliminary
The clock jitter specification applies to the memory output clock pins clocked by an integer PLL, or generated using differential signal-splitter and double
data I/O circuits clocked by a PLL output routed on a PHY clock network as specified. Altera recommends using PHY clock networks for better jitter
performance.
The memory output clock jitter is applicable when an input jitter of 10 ps peak-to-peak is applied with bit error rate (BER) 10–12, equivalent to 14 sigma.
–E1L, –E1M (79), –E1S,
–I1L, –I1M (79), –I1S
–E2L, –E2S, –I2L, –I2S
–E1M (80), –I1M (80), –E3S,
–I3S
Parameter
Clock Network
Symbol
Unit
Min
58
Max
58
Min
58
Max
58
Min
58
Max
58
Clock period jitter
tJIT(per)
tJIT(cc)
ps
ps
ps
PHY
clock
Cycle-to-cycle period jitter
Duty cycle jitter
58
58
58
58
58
58
tJIT(duty)
58
58
58
58
58
58
OCT Calibration Block Specifications
Table 54: OCT Calibration Block Specifications for Arria 10 Devices—Preliminary
Symbol
OCTUSRCLK
TOCTCAL
Description
Min
Typ
—
Max
20
Unit
Clock required by OCT calibration blocks
—
MHz
Number of OCTUSRCLK clock cycles required for
RS OCT /RT OCT calibration
> 2000
—
—
Cycles
TOCTSHIFT
TRS_RT
Number of OCTUSRCLK clock cycles required for OCT
code to shift out
—
—
32
—
—
Cycles
ns
Time required between the dyn_term_ctrland oesignal
transitions in a bidirectional I/O buffer to dynamically
switch between RS OCT and RT OCT
2.5
(79)
(80)
When you power VCC and VCCP at nominal voltage of 0.90 V.
When you power VCC and VCCP at lower voltage of 0.83 V.
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HPS Specifications
Figure 5: Timing Diagram for on oe and dyn_term_ctrl Signals
Tristate
TX
Tristate
RX
RX
oe
dyn_term_ctrl
TRS_RT
TRS_RT
HPS Specifications
This section provides HPS specifications and timing for Arria 10 devices. The specifications are preliminary.
HPS Reset Input Requirements
Table 55: HPS Reset Input Requirements for Arria 10 Devices—Preliminary
Description
Min
600
600
—
Max
—
Unit
HPS cold reset pulse width
ns
HPS warm reset pulse width
—
ns
osc1 clocks
μs
Cold reset deassertion to BSEL sampling, using osc1 clock
1000
100
Cold reset deassertion to BSEL sampling, using secure clock,
without RAM clearing
—
Cold reset deassertion to BSEL sampling, using secure clock, with
RAM clearing
—
50
ms
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HPS Clock Performance
HPS Clock Performance
Table 56: HPS Clock Performance for Arria 10 Devices—Preliminary
Symbol/Description
–3 Speed Grade
–2 Speed Grade
–1 Speed Grade
Unit
mpu_base_clk
noc_base_clk
h2f_user0_clk
h2f_user1_clk
hmc_free_clk
800
400
400
400
433
1200
400
400
400
533
1500
500
400
400
533
MHz
MHz
MHz
MHz
MHz
HPS PLL Specifications
HPS PLL Input Requirements
Table 57: HPS PLL Input Requirements for Arria 10 Devices—Preliminary
Description
Min
10
Typ
—
Max
50
2
Unit
MHz
%
Clock input range
Clock input jitter tolerance
Clock input duty cycle
—
—
45
50
55
%
HPS PLL Performance
Table 58: HPS PLL Performance for Arria 10 Devices—Preliminary
–3 Speed Grade
Description
–2 Speed Grade
–1 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
HPS PLL VCO output
320
1600
320
2400
320
3000
MHz
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HPS PLL Output Specifications
HPS PLL Output Specifications
The maximum HPS PLL lock time is 10 μs for all speed grades.
Quad SPI Flash Timing Characteristics
Table 59: Quad Serial Peripheral Interface (SPI) Flash Timing Requirements for Arria 10 Devices—Preliminary
The input parameters are still pending characterization. Note that the Arria 10 HPS boot loader calibrates the input timing automatically.
Symbol
Tqspi_clk
Tclk
Description
Min
2.5
10
45
0.5
–2
1
Typ
—
—
50
—
—
—
—
Max
—
—
55
3
Unit
ns
ns
%
QSPI_CLK clock period (internal reference clock)
SCLK_OUT clock period (external clock)
SCLK_OUT duty cycle
Tdutycycle
(81)
Tdssfrst
QSPI_SS asserted to first SCLK_OUT edge
Last SCLK_OUT edge to QSPI_SS deasserted
QSPI_DATA output delay
ns
ns
ns
ns
(81)
Tdsslst
0.5
3
Tdo
Tdin_start
Valid input data start from falling clock edge
—
[(2 + Rdelay) ×
Tqspi_clk] – 4
Tdin_end
Valid input data end from falling clock edge
[(2 + Rdelay) ×
Tqspi_clk] + 2.2
—
—
—
ns
(82)
Tdssb2b
Minimum delay of slave select deassertion between
two back-to-back transfer
1
—
SCLK_OUT
(81)
(82)
You can increase this delay using the delay register in the Quad SPI module.
This delay is programmable in whole QSPI_CLK increments using the delay register in the Quad SPI module.
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SPI Timing Characteristics
Figure 6: Quad SPI Flash Serial Output Timing Diagram
Tdio (min)
Tdssfrst
Tdsslst
Tdio (max)
QSPI_SS
SCLK_OUT
QSPI_DATA
OUT0
OUT1
OUTn
Figure 7: Quad SPI Flash Serial Input Timing Diagram
QSPI_SS
SCLK_OUT
Tdin_start
QSPI_DATA
IN0
IN1
INn
Tdin_end
SPI Timing Characteristics
Table 60: SPI Master Timing Requirements for Arria 10 Devices—Preliminary
You can adjust the input delay timing using the rx_sample_dlyregister.
Symbol
Description
Min
16.67
45
Typ
—
Max
—
Unit
ns
Tclk
Tdutycycle
SPI_CLK clock period
SPI_CLK duty cycle
50
55
%
(83)
Tdssfrst
SPI_SS asserted to first SPI_CLK edge
1.5
—
3.5
ns
(83)
SPI_SS behavior differs depending on Motorola SPI, TI SSP or Microwire operational mode.
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SPI Timing Characteristics
Symbol
Description
Min
–0.6
1
Typ
—
—
—
—
—
Max
1.4
4
Unit
(83)
Tdsslst
Tdio
Last SPI_CLK edge to SPI_SS deasserted
Master-out slave-in (MOSI) output delay
Input setup in respect to SPI_CLK capture edge
Input hold in respect to SPI_CLK capture edge
ns
ns
(84)
Tsu
Th
2
—
ns
(84)
0
—
ns
Tdssb2b
Minimum delay of slave select deassertion
between two back-to-back transfers (frames)
1
—
SPI_CLK
Figure 8: SPI Master Output Timing Diagram
Tdssfrst (max)
Tdssfrst (min)
SPI_SS
SPI_CLK
SPI_MOSI
SPI_MISO
OUT0
OUT1
OUTn
Tdsslst (min)
Tdsslst (max)
Tdio (min)
Tdio (max)
(84)
The capture edge differs depending on the operational mode. For Motorola SPI, the capture edge can be the rising or falling edge depending on the
scpolregister bit; for TI SSP, the capture edge is the falling edge; for Microwire, the capture edge is the rising edge.
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SPI Timing Characteristics
Figure 9: SPI Master Input Timing Diagram
SPI_SS
SPI_CLK
SPI_MOSI
SPI_MISO
IN0
IN1
INn
Tsu Th
Table 61: SPI Slave Timing Requirements for Arria 10 Devices—Preliminary
Symbol
Tclk
Description
Min
20
45
5
Typ
—
50
—
—
—
—
—
—
—
Max
—
55
—
—
—
—
—
—
4
Unit
ns
%
SPI_CLK clock period
SPI_CLK duty cycle
Tdutycycle
Ts
SPI slave input setup time
ns
ns
ns
ns
ns
ns
ns
Th
SPI slave input hold time
5
Tssfsu
Tssfh
Tsslsu
Tsslh
Td
SPI_SS asserted to first active SPI_CLK edge setup (85)
SPI_SS asserted to first active SPI_CLK edge hold (85)
SPI_SS deasserted to last active SPI_CLK edge setup (85)
SPI_SS deasserted to last active SPI_CLK edge hold (85)
Master-in slave-out (MISO) output delay
5
5
5
5
1
(85)
The active edge differs depending on the operational mode. For Motorola SPI, the active edge can be the rising or falling edge depending on the
scpolregister bit; for TI SSP, the active edge is the falling edge; for Microwire, the active edge is the rising edge.
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SPI Timing Characteristics
Figure 10: SPI Slave Output Timing Diagram
Td (max)
Td (min)
SPI_SS
SPI_CLK
SPI_MISO
SPI_MOSI
OUT0
OUT1
OUTn
Figure 11: SPI Slave Input Timing Diagram
Tsslh
Tssfsu
Tssfh
Tsslsu
SPI_SS
SPI_CLK
SPI_MISO
SPI_MOSI
IN0
IN1
INn
Ts Th
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SD/MMC Timing Characteristics
SD/MMC Timing Characteristics
Table 62: Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Arria 10 Devices—Preliminary
These timings apply to SD, MMC, and embedded MMC cards operating at 1.8 V and 3.3 V.
Symbol
Description
Min
Typ
Max
Unit
SDMMC_CLK_OUT clock period (Identification
mode)
—
2500
—
ns
Tsdmmc_clk_
out
SDMMC_CLK_OUT clock period (Standard SD
mode)
—
—
40
20
—
—
ns
ns
SDMMC_CLK_OUT clock period (High speed SD
mode)
Tdutycycle
Tsu
SDMMC_CLK_OUT duty cycle
45
4.0
1.0
8.5
50
—
—
—
55
—
%
ns
ns
ns
SDMMC_CMD/SDMMC_D[7:0] input setup (86)
SDMMC_CMD/SDMMC_D[7:0] input hold (87)
SDMMC_CMD/SDMMC_D[7:0] output delay (88)
Th
—
Td
11.5
(86)
(87)
(88)
These values assume the use of the phase shift implemented in the Boot ROM using smplsel= 0 and TSDMMC_CLK_OUT= 50 MHz (20 ns) in this
equation: 4 – (TSDMMC_CLK_OUT× smpl_sel/ 8) ns. The smplselfield is in the sdmmcregister in the System Manager module.
These values assume the use of the phase shift implemented in the Boot ROM using smplsel= 0 and TSDMMC_CLK_OUT= 50 MHz (20 ns) in this
equation: 1 + (TSDMMC_CLK_OUT× smpl_sel/ 8) ns. The smplselfield is in the sdmmcregister in the System Manager module.
These values assume the use of the phase shift implemented in the Boot ROM using drvsel= 3 and TSDMMC_CLK_OUT= 50 MHz (20 ns) in the
following equations:
•
•
For min value: (TSDMMC_CLK_OUT× drv_sel/ 8) + 1 ns
For max value: (TSDMMC_CLK_OUT× drv_sel/ 8) + 4 ns
The drvselfield is in the sdmmcregister in the System Manager module. You must not set drvselto 0 because this does not provide the necessary
delay to meet the hold time of the flash device.
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USB ULPI Timing Characteristics
Figure 12: SD/MMC Timing Diagram
SDMMC_CLK_OUT
Td
SDMMC_CMD and SDMMC_D (Out)
SDMMC_CMD and SDMMC_D (In)
Command/Data Out
TSU
Th
Command/Data In
USB ULPI Timing Characteristics
Table 63: USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) Low Pin Interface (ULPI) Timing Requirements for Arria 10 Devices—Preliminary
Symbol
Description
Min
—
Typ
16.667
—
Max
—
8
Unit
ns
Tclk
Td
USB_CLK clock period
Clock to USB_STP/USB_DATA[7:0] output delay
1.5
2
ns
Tsu
Setup time for USB_DIR/USB_NXT/USB_
DATA[7:0]
—
—
ns
Th
Hold time for USB_DIR/USB_NXT/USB_
DATA[7:0]
1
—
—
ns
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Ethernet Media Access Controller (EMAC) Timing Characteristics
Figure 13: USB ULPI Timing Diagram
USB_CLK
USB_STP
Td
USB_DATA[7:0]
To PHY
From PHY
TSU Th
USB_DIR and USB_NXT
Ethernet Media Access Controller (EMAC) Timing Characteristics
Table 64: Reduced Gigabit Media Independent Interface (RGMII) TX Timing Requirements for Arria 10 Devices—Preliminary
Symbol
Tclk (1000Base-T)
Tclk (100Base-T)
Tclk (10Base-T)
Tdutycycle
Description
Min
—
Typ
8
Max
—
Unit
ns
TX_CLK clock period
TX_CLK clock period
TX_CLK clock period
TX_CLK duty cycle
—
40
400
50
—
—
ns
—
—
ns
45
55
%
Td
TX_CLK to TXD/TX_CTL output data delay
–0.5
0.5
ns
Figure 14: RGMII TX Timing Diagram
TX_CLK
TX_D[3:0]
D0
D1
Td
TX_CTL
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Ethernet Media Access Controller (EMAC) Timing Characteristics
Table 65: RGMII RX Timing Requirements for Arria 10 Devices—Preliminary
Symbol
Description
Min
—
—
—
1
Typ
8
Max
—
Unit
ns
Tclk (1000Base-T)
Tclk (100Base-T)
Tclk (10Base-T)
Tsu
RX_CLK clock period
RX_CLK clock period
RX_CLK clock period
40
400
—
—
ns
—
ns
RX_D/RX_CTL setup time
RX_D/RX_CTL hold time
—
ns
Th
2.5
—
—
ns
Figure 15: RGMII RX Timing Diagram
RX_CLK
TSU
Th
RX_D[3:0]
RX_CTL
D0
D1
Table 66: Reduced Media Independent Interface (RMII) Clock Timing Requirements for Arria 10 Devices—Preliminary
Symbol
Tclk (100Base-T)
Tclk (10Base-T)
Tdutycycle
Description
Min
—
Typ
20
Max
—
Unit
ns
ns
%
TX_CLK clock period
TX_CLK clock period
—
20
—
Clock duty cycle, internal clock source
Clock duty cycle, external clock source
45
35
50
55
Tdutycycle
50
65
%
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Ethernet Media Access Controller (EMAC) Timing Characteristics
Table 67: RMII TX Timing Requirements for Arria 10 Devices—Preliminary
Symbol
Description
Min
Typ
Max
Unit
Td
TX_CLK to TXD/TX_CTL output data delay
0.45
—
4
ns
Table 68: RMII RX Timing Requirements for Arria 10 Devices—Preliminary
Symbol
Description
Min
1
Typ
—
Max
—
Unit
ns
Tsu
Th
RX_D/RX_CTL setup time
RX_D/RX_CTL hold time
0.4
—
—
ns
Table 69: Management Data Input/Output (MDIO) Timing Requirements for Arria 10 Devices—Preliminary
Symbol
Description
Min
—
Typ
400
—
Max
—
Unit
Tclk
MDC clock period
ns
ns
ns
ns
Td
Tsu
Th
MDC to MDIO output data delay
Setup time for MDIO data
Hold time for MDIO data
10.2
10
20
—
—
10
—
—
Figure 16: MDIO Timing Diagram
MDC
Td
MDIO_OUT
Dout0
Dout1
TSU
Th
Din0
MDIO_IN
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I2C Timing Characteristics
I2C Timing Characteristics
Table 70: I2C Timing Requirements for Arria 10 Devices—Preliminary
Standard Mode
Fast Mode
Symbol
Description
Unit
Min
Max
—
Min
2.5
0.6
1.3
0.1
Max
—
Tclk
Serial clock (SCL) clock period
SCL high period
10
4
μs
μs
μs
μs
tHIGH
tLOW
tSU;DAT
—
—
SCL low period
4.7
0.25
—
—
Setup time for serial data line (SDA) data to
SCL
—
—
(89)
tHD;DAT
Hold time for SCL to SDA data
SCL to SDA output data delay
0
3.15
3.45
0
0.6
0.9
μs
μs
tVD;DAT
and
—
—
tVD;ACK
tSU;STA
tHD;STA
tSU;STO
tBUF
Setup time for a repeated start condition
Hold time for a repeated start condition
Setup time for a stop condition
4.7
4
—
—
—
—
0.6
0.6
0.6
1.3
—
—
—
—
μs
μs
μs
μs
4
SDA high pulse duration between STOP and
START
4.7
tr
tf
SCL rise time
SCL fall time
—
—
1000
300
20
300
300
ns
ns
20 × (Vdd
5.5) (90)
/
/
tr
tf
SDA rise time
SDA fall time
—
—
1000
300
20
300
300
ns
ns
20 × (Vdd
5.5) (90)
(89)
(90)
You must enable an internal delay in the embedded software. The delay is programmable using the ic_sda_holdregister in the I2C controller.
Vdd is the I2C bus voltage.
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I2C Timing Characteristics
Figure 17: I2C Timing Diagram
tSU;DAT
tf
tr
SDA
SCL
tHIGH
tVD;DAT
tHD;DAT
tf
tr
tHD;STA
Tclk
tLOW
tBUF
SDA
SCL
tSU;STA
tHD;STA
tVD;ACK
tSU;STO
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NAND Timing Characteristics
NAND Timing Characteristics
Table 71: NAND ONFI 1.0 Timing Requirements for Arria 10 Devices—Preliminary
Symbol
Description
Min
10
7
Max
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(91)
tWP
Write enable pulse width
Write enable hold time
Read enable pulse width
Read enable hold time
(91)
tWH
—
(91)
tRP
10
7
—
(91)
tREH
—
(91)
tCLS
Command latch enable to write enable setup time
Command latch enable to write enable hold time
Chip enable to write enable setup time
Chip enable to write enable hold time
Address latch enable to write enable setup time
Address latch enable to write enable hold time
Data to write enable setup time
10
5
—
(91)
tCLH
—
(91)
tCS
15
5
—
(91)
tCH
—
(91)
(91)
tALS
10
5
—
tALH
—
(91)
tDS
7
—
(91)
tDH
Data to write enable hold time
5
—
tCEA
tREA
tRHZ
tRR
Chip enable to data access time
—
—
—
20
—
100
40
200
—
Read enable to data access time
Read enable to data high impedance
Ready to read enable low
(91)
tWB
Write enable high to R/B low
200
(91)
This timing is software programmable.
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NAND Timing Characteristics
Figure 18: NAND Command Latch Timing Diagram
CLE
CE
tCLS
tCS
tCLH
tCH
tWP
WE
tALS
tALH
ALE
tDS
Command
tDH
IO0-7
R/B
tWB
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NAND Timing Characteristics
Figure 19: NAND Address Latch Timing Diagram
tCLS
CLE
tCS
tWC
CE
tWP
WE
tWH
tALS
tDS
tALH
tDH
ALE
IO0-7
Address
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NAND Timing Characteristics
Figure 20: NAND Data Output Cycle Timing Diagram
tCLH
CLE
tCH
CE
tWP
tWP
tWP
WE
tWH
tALS
ALE
tDS tDH
DOUT 0
tDS tDH
DOUT 1
tDS tDH
DOUT n
IOx
Figure 21: NAND Data Input Cycle Timing Diagram
tCEA
CE
tRP
tRP
tRP
RE
tREH
tRR
R/B
tREA
tRHZ
DIN 0
tREA
tRHZ
DIN 1
tREA
tRHZ
DIN n
IOx
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NAND Timing Characteristics
Figure 22: NAND Data Input Timing Diagram for Extended Data Output (EDO) Cycle
CE
RE
tRP
tREH
tRR
tREA
tREA
tRHOH
R/B
IOx
tRHZ
DIN n
DIN 0
DIN 1
tCEA
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NAND Timing Characteristics
Figure 23: NAND Read Status Timing Diagram
tCLR
CLE
tCLS
tCLH
tCH
tCS
tCEA
CE
tWP
WE
tRHZ
RE
tDS
tDH
IO0-7
70h
Status
tREA
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Trace Timing Characteristics
Figure 24: NAND Read Status Enhanced Timing Diagram
tCLS
tCS
tCLH
CLE
CE
tCH
tCEA
tWP
tWP
tALS
WE
tALH
tALH
tWH
ALE
RE
tREA
tRHZ
tDS tDH
78h
R1
R2
R3
Status
IO0-7
Trace Timing Characteristics
Table 72: Trace Timing Requirements for Arria 10 Devices—Preliminary
Symbol
Description
Min
5
Typ
—
Max
—
55
1
Unit
ns
Tclk
Tdutycycle
Td
CLK clock period
CLK maximum duty cycle
45
50
%
CLK to D0–D3 output data delay
–0.5
—
ns
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GPIO Interface
Figure 25: Trace Timing Diagram
Tclk
D0 - D3 (DDR)
D0
D1
D2
D3
D4
td
td
GPIO Interface
The general-purpose I/O (GPIO) interface has debounce circuitry included to remove signal glitches. The debounce clock frequency ranges from
125 Hz to 32 kHz. The minimum pulse width is 2 debounce clock cycles and the minimum detectable GPIO pulse width is 62.5 us (at 32 kHz). Any
pulses shorter than 2 debounce clock cycles are filtered by the GPIO peripheral.
Configuration Specifications
This section provides configuration specifications and timing for Arria 10 devices.
POR Specifications
Power-on reset (POR) delay is defined as the delay between the time when all the power supplies monitored by the POR circuitry reach the
minimum recommended operating voltage to the time when the nSTATUSis released high and your device is ready to begin configuration.
Table 73: Fast and Standard POR Delay Specification for Arria 10 Devices—Preliminary
POR Delay
Minimum
Maximum
12 (92)
Unit
ms
Fast
4
Standard
100
300
ms
(92)
The maximum pulse width of the fast POR delay is 12 ms, providing enough time for the PCIe hard IP to initialize after the POR trip.
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JTAG Configuration Timing
Related Information
MSEL Pin Settings
Provides more information about POR delay based on MSEL pin settings for each configuration scheme.
JTAG Configuration Timing
Table 74: JTAG Timing Parameters and Values for Arria 10 Devices—Preliminary
Symbol
Description
Min
Max
—
—
—
—
—
—
11
14
14
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
tJCP
tJCH
tJCL
TCKclock period
30, 167 (93)
TCKclock high time
14
14
2
TCKclock low time
tJPSU (TDI)
tJPSU (TMS)
tJPH
TDIJTAG port setup time
TMSJTAG port setup time
JTAG port hold time
JTAG port clock to output
3
5
tJPCO
—
—
—
tJPZX
JTAG port high impedance to valid output
JTAG port valid output to high impedance
tJPXZ
FPP Configuration Timing
DCLK-to-DATA[] Ratio (r) for FPP Configuration
Fast passive parallel (FPP) configuration requires a different DCLK-to-DATA[]ratio when you turn on encryption or the compression feature.
Depending on the DCLK-to-DATA[]ratio, the host must send a DCLKfrequency that is r times the DATA[]rate in byte per second (Bps) or word per
second (Wps). For example, in FPP ×16 where the r is 2, the DCLKfrequency must be 2 times the DATA[]rate in Wps.
(93)
The minimum TCK clock period is 167 ns if VCCBAT is within the range 1.2 V – 1.5 V when you perform the volatile key programming.
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FPP Configuration Timing when DCLK-to-DATA[] = 1
Table 75: DCLK-to-DATA[] Ratio for Arria 10 Devices—Preliminary
You cannot turn on encryption and compression at the same time for Arria 10 devices.
Configuration Scheme
Encryption
Compression
DCLK-to-DATA[] Ratio (r)
Off
Off
Off
On
Off
Off
On
Off
Off
On
1
1
2
1
2
4
1
4
8
FPP (8-bit wide)
On
Off
Off
FPP (16-bit wide)
FPP (32-bit wide)
On
Off
Off
On
Off
FPP Configuration Timing when DCLK-to-DATA[] = 1
Note: When you enable decompression or the design security feature, the DCLK-to-DATA[]ratio varies for FPP ×8, FPP ×16, and FPP ×32. For the
respective DCLK-to-DATA[]ratio, refer to the DCLK-to-DATA[]Ratio for Arria 10 Devices table.
Table 76: FPP Timing Parameters When the DCLK-to-DATA[] Ratio is 1 for Arria 10 Devices—Preliminary
Use these timing parameters when the decompression and design security features are disabled.
Symbol
Parameter
nCONFIGlow to CONF_DONElow
nCONFIGlow to nSTATUSlow
nCONFIGlow pulse width
Minimum
Maximum
600
Unit
ns
tCF2CD
tCF2ST0
tCFG
tSTATUS
tCF2ST1
—
—
2
600
ns
—
3,000 (94)
3,000 (95)
μs
nSTATUSlow pulse width
268
—
μs
nCONFIGhigh to nSTATUShigh
μs
(94)
This value is applicable if you do not delay configuration by extending the nCONFIGor nSTATUSlow pulse width.
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FPP Configuration Timing when DCLK-to-DATA[] = 1
Symbol
Parameter
nCONFIGhigh to first rising edge on DCLK
nSTATUShigh to first rising edge of DCLK
DATA[]setup time before rising edge on DCLK
DATA[]hold time after rising edge on DCLK
DCLKhigh time
Minimum
Maximum
Unit
μs
μs
ns
ns
s
(96)
tCF2CK
3,010
—
—
(96)
tST2CK
tDSU
tDH
10
5.5
—
0
0.45 × 1/fMAX
0.45 × 1/fMAX
1/fMAX
—
tCH
—
tCL
DCLKlow time
—
s
tCLK
fMAX
tCD2UM
tCD2CU
DCLK period
—
s
DCLKfrequency (FPP ×8/×16/×32)
—
100
830
—
MHz
μs
—
(97)
CONF_DONEhigh to user mode
175
CONF_DONEhigh to CLKUSRenabled
4 × maximum DCLK
period
tCD2UMC
CONF_DONEhigh to user mode with CLKUSRoption on
tCD2CU
+
—
—
(600 × CLKUSR
period)
Related Information
FPP Configuration Timing
Provides the FPP configuration timing waveforms.
(95)
(96)
(97)
This value is applicable if you do not delay configuration by externally holding the nSTATUSlow.
If nSTATUSis monitored, follow the tST2CK specification. If nSTATUSis not monitored, follow the tCF2CK specification.
The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
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FPP Configuration Timing when DCLK-to-DATA[] >1
FPP Configuration Timing when DCLK-to-DATA[] >1
Table 77: FPP Timing Parameters When the DCLK-to-DATA[] Ratio is >1 for Arria 10 Devices—Preliminary
Use these timing parameters when you use the decompression and design security features.
Symbol
Parameter
nCONFIGlow to CONF_DONElow
nCONFIGlow to nSTATUSlow
nCONFIGlow pulse width
Minimum
Maximum
Unit
ns
ns
μs
μs
μs
μs
μs
ns
s
tCF2CD
tCF2ST0
tCFG
tSTATUS
tCF2ST1
—
—
600
600
—
2
nSTATUSlow pulse width
268
—
3,000 (98)
3,000 (98)
—
nCONFIGhigh to nSTATUShigh
nCONFIGhigh to first rising edge on DCLK
nSTATUShigh to first rising edge of DCLK
DATA[]setup time before rising edge on DCLK
DATA[]hold time after rising edge on DCLK
DCLKhigh time
(99)
tCF2CK
tST2CK
tDSU
tDH
3,010
10
(99)
—
5.5
—
(100)
N–1/fDCLK
—
tCH
0.45 × 1/fMAX
—
s
tCL
DCLKlow time
0.45 × 1/fMAX
—
s
tCLK
fMAX
tR
DCLKperiod
1/fMAX
—
—
s
DCLKfrequency (FPP ×8/×16/×32)
Input rise time
100
40
MHz
ns
ns
μs
—
tF
Input fall time
CONF_DONEhigh to user mode (101)
—
40
tCD2UM
175
830
(98)
(99)
You can obtain this value if you do not delay configuration by extending the nCONFIGor nSTATUSlow pulse width.
If nSTATUSis monitored, follow the tST2CK specification. If nSTATUSis not monitored, follow the tCF2CK specification.
N is the DCLK-to-DATAratio and fDCLK is the DCLKfrequency the system is operating.
(100)
(101)
The minimum and maximum numbers apply only if you use the internal oscillator as the clock source for initializing the device.
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AS Configuration Timing
Symbol
Parameter
Minimum
Maximum
Unit
tCD2CU
CONF_DONEhigh to CLKUSRenabled
4 × maximum DCLK
—
—
period
tCD2UMC
CONF_DONEhigh to user mode with CLKUSRoption on
tCD2CU
+
—
—
(600 × CLKUSR
period)
Related Information
FPP Configuration Timing
Provides the FPP configuration timing waveforms.
AS Configuration Timing
Table 78: AS Timing Parameters for AS ×1 and AS ×4 Configurations in Arria 10 Devices—Preliminary
The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for initializing the device.
The tCF2CD, tCF2ST0, tCFG, tSTATUS, and tCF2ST1 timing parameters are identical to the timing parameters for passive serial (PS) mode listed in PS Timing
Parameters for Arria 10 Devices table.
Symbol
Parameter
Minimum
Maximum
Unit
ns
tCO
tSU
DCLKfalling edge to AS_DATA0/ASDOoutput
Data setup time before falling edge on DCLK
Data hold time after falling edge on DCLK
CONF_DONEhigh to user mode
—
1
4
—
ns
tDH
1.5
175
—
ns
tCD2UM
tCD2CU
830
—
μs
CONF_DONEhigh to CLKUSRenabled
4 × maximum DCLK
—
period
tCD2UMC
CONF_DONEhigh to user mode with CLKUSRoption on
tCD2CU + (600 ×
—
—
CLKUSRperiod)
Related Information
•
PS Configuration Timing on page 86
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DCLK Frequency Specification in the AS Configuration Scheme
•
AS Configuration Timing
Provides the AS configuration timing waveform.
DCLK Frequency Specification in the AS Configuration Scheme
Table 79: DCLK Frequency Specification in the AS Configuration Scheme—Preliminary
This table lists the internal clock frequency specification for the AS configuration scheme.
The DCLKfrequency specification applies when you use the internal oscillator as the configuration clock source.
The AS multi-device configuration scheme does not support DCLKfrequency of 100 MHz.
You can only set 12.5, 25, 50, and 100 MHz in the Quartus Prime software.
Parameter
Minimum
5.3
Typical
7.9
Maximum
12.5
Unit
MHz
MHz
MHz
MHz
10.6
15.7
31.4
62.9
25.0
DCLK frequency in AS configuration
scheme
21.3
50.0
42.6
100.0
PS Configuration Timing
Table 80: PS Timing Parameters for Arria 10 Devices—Preliminary
Symbol
Parameter
nCONFIGlow to CONF_DONElow
nCONFIGlow to nSTATUSlow
nCONFIGlow pulse width
Minimum
Maximum
Unit
tCF2CD
tCF2ST0
tCFG
tSTATUS
tCF2ST1
—
—
2
600
600
ns
ns
μs
μs
μs
—
nSTATUSlow pulse width
268
—
3,000 (102)
3,000 (103)
nCONFIGhigh to nSTATUShigh
(102)
(103)
This value is applicable if you do not delay configuration by extending the nCONFIGor nSTATUSlow pulse width.
This value is applicable if you do not delay configuration by externally holding the nSTATUSlow.
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Initialization
Symbol
Parameter
nCONFIGhigh to first rising edge on DCLK
nSTATUShigh to first rising edge of DCLK
DATA[]setup time before rising edge on DCLK
DATA[]hold time after rising edge on DCLK
DCLKhigh time
Minimum
Maximum
Unit
μs
μs
ns
ns
s
(104)
tCF2CK
3,010
—
—
(104)
tST2CK
tDSU
tDH
10
5.5
—
0
0.45 × 1/fMAX
0.45 × 1/fMAX
1/fMAX
—
tCH
—
tCL
DCLKlow time
—
s
tCLK
fMAX
tCD2UM
tCD2CU
DCLKperiod
—
s
DCLKfrequency
CONF_DONEhigh to user mode (105)
—
125
830
—
MHz
μs
—
175
CONF_DONEhigh to CLKUSRenabled
4 × maximum DCLK
period
tCD2UMC
CONF_DONEhigh to user mode with CLKUSRoption on
tCD2CU + (600 ×
—
—
CLKUSRperiod)
Related Information
PS Configuration Timing
Provides the PS configuration timing waveform.
Initialization
Table 81: Initialization Clock Source Option and the Maximum Frequency for Arria 10 Devices—Preliminary
Initialization Clock Source
Internal Oscillator
CLKUSR(106)(107)
Configuration Scheme
AS, PS, and FPP
Maximum Frequency (MHz)
Minimum Number of Clock Cycles
12.5
100
600
AS, PS, and FPP
(104)
(105)
If nSTATUSis monitored, follow the tST2CK specification. If nSTATUSis not monitored, follow the tCF2CK specification.
The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for initializing the device.
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Configuration Files
Configuration Files
There are two types of configuration bit stream formats for different configuration schemes:
•
•
PS and FPP—Raw Binary File (.rbf)
AS—Raw Programming Data File (.rpd)
The .rpd file size follows the Altera configuration devices capacity. However, the actual configuration bit stream size for .rpd file is the same as .rbf
file.
Table 82: Configuration Bit Stream Sizes for Arria 10 Devices—Preliminary
Use this table to estimate the file size before design compilation. Different configuration file formats, such as a hexadecimal file (.hex) or tabular text file
(.ttf) format, have different file sizes.
For the different types of configuration file and file sizes, refer to the Quartus Prime software. However, for a specific version of the Quartus Prime
software, any design targeted for the same device has the same uncompressed configuration file size.
Variant
Product Line
Uncompressed Configuration
Bit Stream Size (bits)
IOCSR .rbf Size (bits)
Recommended EPCQ-L Serial Configuration
Device
GX 016
GX 022
GX 027
GX 032
GX 048
GX 057
GX 066
GX 900
GX 1150
81,923,582
81,923,582
122,591,622
122,591,622
177,341,246
252,831,072
252,831,072
351,292,512
351,292,512
1,356,716
1,356,716
1,360,284
1,360,284
1,454,656
1,549,028
1,549,028
1,885,396
1,885,396
EPCQ-L256 or higher density
EPCQ-L256 or higher density
EPCQ-L256 or higher density
EPCQ-L256 or higher density
EPCQ-L256 or higher density
EPCQ-L256 or higher density
EPCQ-L256 or higher density
EPCQ-L512 or higher density
EPCQ-L512 or higher density
Arria 10 GX
(106)
(107)
To enable CLKUSRas the initialization clock source, turn on the Enable user-supplied start-up clock (CLKUSR) option in the Quartus Prime
software from the General panel of the Device and Pin Options dialog box.
If you use the CLKUSRpin for AS and transceiver calibration simultaneously, the only allowed frequency is 100 MHz.
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Configuration Files
Variant
Product Line
Uncompressed Configuration
Bit Stream Size (bits)
IOCSR .rbf Size (bits)
Recommended EPCQ-L Serial Configuration
Device
GT 900
GT 1150
SX 016
SX 022
SX 027
SX 032
SX 048
SX 057
SX 066
351,292,512
351,292,512
81,923,582
81,923,582
122,591,622
122,591,622
177,341,246
252,831,072
252,831,072
1,885,396
1,885,396
1,356,716
1,356,716
1,360,284
1,360,284
1,454,656
1,549,028
1,549,028
EPCQ-L512 or higher density
EPCQ-L512 or higher density
EPCQ-L256 or higher density
EPCQ-L256 or higher density
EPCQ-L256 or higher density
EPCQ-L256 or higher density
EPCQ-L256 or higher density
EPCQ-L256 or higher density
EPCQ-L256 or higher density
Arria 10 GT
Arria 10 SX
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Minimum Configuration Time Estimation
Minimum Configuration Time Estimation
Table 83: Minimum Configuration Time Estimation for Arria 10 Devices—Preliminary
The estimated values are based on the uncompressed configuration bit stream sizes in the Configuration Bit Stream Sizes for Arria 10 Devices table.
Active Serial (108)
Fast Passive Parallel (109)
Variant
Product Line
Width
DCLK (MHz) Minimum Configuration
Time (ms)
Width
DCLK (MHz) Minimum Configuration Time
(ms)
GX 016
GX 022
GX 027
GX 032
GX 048
GX 057
GX 066
GX 900
GX 1150
GT 900
GT 1150
4
4
4
4
4
4
4
4
4
4
4
100
100
100
100
100
100
100
100
100
100
100
204.81
204.81
306.48
306.48
443.35
632.08
632.08
883.20
883.20
883.20
883.20
32
32
32
32
32
32
32
32
32
32
32
100
100
100
100
100
100
100
100
100
100
100
25.60
25.60
38.31
38.31
55.42
79.01
79.01
110.40
110.40
110.40
110.40
Arria 10 GX
Arria 10 GT
(108)
The minimum configuration time is calculated based on DCLK frequency of 100 MHz. Only external CLKUSRmay guarantee the frequency accuracy
of 100 MHz. If you use internal oscillator of 100 MHz, you may not get the actual frequency of 100 MHz. For the DCLK frequency using internal
oscillator, refer to the DCLK Frequency Specification in the AS Configuration Scheme table.
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Remote System Upgrades
Active Serial (108)
Fast Passive Parallel (109)
Variant
Product Line
Width
DCLK (MHz) Minimum Configuration
Time (ms)
Width
DCLK (MHz) Minimum Configuration Time
(ms)
SX 016
SX 022
SX 027
SX 032
SX 048
SX 057
SX 066
4
4
4
4
4
4
4
100
100
100
100
100
100
100
204.81
204.81
306.48
306.48
443.35
632.08
632.08
32
32
32
32
32
32
32
100
100
100
100
100
100
100
25.60
25.60
38.31
38.31
55.42
79.01
79.01
Arria 10 SX
Related Information
•
•
Configuration Files on page 88
DCLK Frequency Specification in the AS Configuration Scheme on page 86
Provides the DCLK frequency using internal oscillator.
Remote System Upgrades
Table 84: Remote System Upgrade Circuitry Timing Specifications for Arria 10 Devices—Preliminary
Parameter
Minimum
Maximum
Unit
(110)
fMAX_RU_CLK
—
40
MHz
(108)
The minimum configuration time is calculated based on DCLK frequency of 100 MHz. Only external CLKUSRmay guarantee the frequency accuracy
of 100 MHz. If you use internal oscillator of 100 MHz, you may not get the actual frequency of 100 MHz. For the DCLK frequency using internal
oscillator, refer to the DCLK Frequency Specification in the AS Configuration Scheme table.
Maximum FPGA FPP bandwidth may exceed bandwidth available from some external storage or control logic.
Maximum FPGA FPP bandwidth may exceed bandwidth available from some external storage or control logic.
This clock is user-supplied to the remote system upgrade circuitry. If you are using the ALTREMOTE_UPDATE megafunction IP core, the clock
user-supplied to the ALTREMOTE_UPDATE IP core must meet this specification.
(109)
(109)
(110)
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User Watchdog Internal Circuitry Timing Specifications
Parameter
Minimum
250
Maximum
Unit
ns
(111)
tRU_nCONFIG
—
—
(112)
tRU_nRSTIMER
250
ns
Related Information
•
Remote System Upgrade State Machine
Provides more information about configuration reset (RU_CONFIG) signal.
User Watchdog Timer
•
Provides more information about reset_timer (RU_nRSTIMER) signal.
User Watchdog Internal Circuitry Timing Specifications
Table 85: User Watchdog Internal Oscillator Frequency Specifications for Arria 10 Devices—Preliminary
Parameter
Minimum
Typical
Maximum
Unit
User watchdog internal oscillator frequency
5.3
7.9
12.5
MHz
I/O Timing
Altera offers two ways to determine I/O timing—the Excel-based I/O Timing and the Quartus Prime Timing Analyzer.
Excel-based I/O timing provides pin timing performance for each device density and speed grade. The data is typically used prior to designing the
FPGA to get an estimate of the timing budget as part of the link timing analysis.
The Quartus Prime Timing Analyzer provides a more accurate and precise I/O timing data based on the specifics of the design after you complete
place-and-route.
Related Information
Arria 10 I/O Timing Spreadsheet
Provides the Arria 10 Excel-based I/O timing spreadsheet.
(111)
(112)
This is equivalent to strobing the reconfiguration input of the ALTREMOTE_UPDATE IP core high for the minimum timing specification.
This is equivalent to strobing the reset_timer input of the ALTREMOTE_UPDATE IP core high for the minimum timing specification.
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Programmable IOE Delay
Programmable IOE Delay
Table 86: IOE Programmable Delay for Arria 10 Devices—Preliminary
For the exact values for each setting, use the latest version of the Quartus Prime software.
Fast Model
Slow Model
–I3S
Available
Settings
Minimum
Offset (114)
Parameter (113)
Unit
Extended
Industrial
–I1L
–I2S
–E2S
–E3S
Input Delay
Chain Setting
(IO_IN_DLY_
CHN)
64
16
0
0
1.829
1.820
4.128
4.764
5.485
4.764
5.485
ns
Output Delay
Chain Setting
(IO_OUT_
0.433
0.430
0.990
1.145
1.326
1.145
1.326
ns
DLY_CHN)
(113)
(114)
You can set this value in the Quartus Prime software by selecting Input Delay Chain Setting or Output Delay Chain Setting in the Assignment
Name column.
Minimum offset does not include the intrinsic delay.
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Glossary
Glossary
Table 87: Glossary
Term
Definition
Differential I/O Standards
Receiver Input Waveforms
Single-Ended Waveform
Positive Channel (p) = V
IH
V
ID
Negative Channel (n) = V
IL
V
CM
Ground
Differential Waveform
V
ID
p - n = 0 V
V
ID
Transmitter Output Waveforms
Single-Ended Waveform
Positive Channel (p) = V
OH
V
OD
Negative Channel (n) = V
Ground
OL
V
CM
Differential Waveform
V
OD
p - n = 0 V
V
OD
fHSCLK
fHSDR
Left/right PLL input clock frequency.
High-speed I/O block—Maximum/minimum LVDS data transfer rate
(fHSDR = 1/TUI), non-DPA.
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Glossary
Term
Definition
fHSDRDPA
High-speed I/O block—Maximum/minimum LVDS data transfer rate
(fHSDRDPA = 1/TUI), DPA.
J
High-speed I/O block—Deserialization factor (width of parallel data bus).
JTAG Timing Specifications:
JTAG Timing Specifications
TMS
TDI
tJCP
tJCH
t JCL
tJPH
tJPSU
TCK
tJPXZ
tJPZX
tJPCO
TDO
Preliminary
Some tables show the designation as “Preliminary”. Preliminary characteristics are created using
simulation results, process data, and other known parameters.
Final numbers are based on actual silicon characterization and testing. The numbers reflect the actual
performance of the device under worst-case silicon process, voltage, and junction temperature conditions.
There are no preliminary designations on finalized tables.
RL
Receiver differential input discrete resistor (external to the Arria 10 device).
Sampling window (SW)
Timing Diagram—the period of time during which the data must be valid in order to capture it correctly.
The setup and hold times determine the ideal strobe position in the sampling window, as shown:
Bit Time
Sampling Window
(SW)
RSKM
RSKM
0.5 x TCCS
0.5 x TCCS
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Glossary
Term
Definition
Single-ended voltage referenced I/O
standard
The JEDEC standard for the SSTL and HSTL I/O defines both the AC and DC input signal values. The
AC values indicate the voltage levels at which the receiver must meet its timing specifications. The DC
values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined.
After the receiver input has crossed the AC value, the receiver changes to the new logic state.
The new logic state is then maintained as long as the input stays beyond the DC threshold. This approach
is intended to provide predictable receiver timing in the presence of input waveform ringing.
Single-Ended Voltage Referenced I/O Standard
V CCIO
V OH
V IH(AC)
V IH(DC)
V REF
V IL(DC)
V IL(AC)
V OL
V SS
tC
High-speed receiver/transmitter input and output clock period.
TCCS (channel-to-channel-skew)
The timing difference between the fastest and slowest output edges, including the tCO variation and clock
skew, across channels driven by the same PLL. The clock is included in the TCCS measurement (refer to
the Timing Diagram figure under SW in this table).
tDUTY
High-speed I/O block—Duty cycle on high-speed transmitter output clock.
Signal high-to-low transition time (80–20%)
tFALL
tINCCJ
Cycle-to-cycle jitter tolerance on the PLL clock input
Period jitter on the GPIO driven by a PLL
tOUTPJ_IO
tOUTPJ_DC
Period jitter on the dedicated clock output driven by a PLL
Signal low-to-high transition time (20–80%)
tRISE
Timing Unit Interval (TUI)
The timing budget allowed for skew, propagation delays, and the data sampling window.
(TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w).
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Glossary
Term
Definition
VCM(DC)
DC Common mode input voltage.
Input Common mode voltage—The common mode of the differential signal at the receiver.
VICM
VID
Input differential voltage swing—The difference in voltage between the positive and complementary
conductors of a differential transmission at the receiver.
VDIF(AC)
VDIF(DC)
VIH
AC differential input voltage—Minimum AC input differential voltage required for switching.
DC differential input voltage— Minimum DC input differential voltage required for switching.
Voltage input high—The minimum positive voltage applied to the input which is accepted by the device
as a logic high.
VIH(AC)
VIH(DC)
VIL
High-level AC input voltage
High-level DC input voltage
Voltage input low—The maximum positive voltage applied to the input which is accepted by the device as
a logic low.
VIL(AC)
VIL(DC)
VOCM
VOD
Low-level AC input voltage
Low-level DC input voltage
Output Common mode voltage—The common mode of the differential signal at the transmitter.
Output differential voltage swing—The difference in voltage between the positive and complementary
conductors of a differential transmission at the transmitter.
VSWING
VIX
Differential input voltage
Input differential cross point voltage
Output differential cross point voltage
High-speed I/O block—Clock Boost Factor
VOX
W
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Document Revision History
Date
Version
Changes
December 2015
2015.12.31
•
•
•
Updated M20K block specifications for "True dual port, all supported widths" and "ROM, all supported
widths" in the Memory Clock Performance Specifications (VCC and VCCP at 0.9 V Typical Value) table.
Updated maximum resolution from 8 bit 6 bit and added minimum clock frequency of 0.1 MHz in Internal
Voltage Sensor Specifications for Arria 10 Devices table.
Updated the sinusoidal jitter from 0.35 UI to 0.28 UI in LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance
Specifications.
December 2015
November 2015
2015.12.18
2015.11.02
•
•
Changed the minimum specifications in the "Transceiver Power Supply Operating Conditions for Arria 10
GT Devices" table.
Changed conditions in the "Transmitter and Receiver Data Rate Performance" table.
•
•
Added power option V which is supported with the SmartVID feature (lowest static power).
Added note for SmartVID in Recommended Operating Conditions for Arria 10 Devices table. Note:
SmartVID is supported in devices with –2V and –3V speed grades only.
Removed 20-Ω RT in OCT Calibration Accuracy Specifications for Arria 10 Devices table.
Updated specifications in OCT Without Calibration Resistance Tolerance Specifications for Arria 10
Devices table.
•
•
•
•
Updated the note for Value column in the Internal Weak Pull-Up Resistor Values for Arria 10 Devices table.
Added Internal Weak Pull-Down Resistor Values for Arria 10 Devices table.
Updated fractional PLL specifications:
•
Updated fIN minimum from 50 MHz to 30 MHz and maximum from 1000 MHz to 800 MHz for all
speed grades.
•
•
•
•
•
Updated fINPFD minimum from 50 MHz to 30 MHz and maximum from 325 MHz to 700 MHz.
Updated fVCO minimum from 3.125 GHz to 3.5 GHz and maximum from 6.25 GHz to 7.05 GHz.
Updated tEINDUTY minimum from 40% to 45% and maximum from 60% to 55%.
Removed the conditions for fOUT and fCLBW
.
Updated the descriptions for fDYCONFIGCLK, tLOCK, and tARESET
.
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Date
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Changes
•
•
•
•
Added –E2V, –I2V, –E3V, and –I3V speed grades in DSP Block Performance Specifications for Arria 10
Devices (VCC and VCCP at 0.9 V Typical Value) table.
Updated Memory Block Performance Specifications for Arria 10 Devices table for VCC and VCCP at 0.9 V
typical value. Added memory block performance specifications for VCC and VCCP at 0.95 V typical value.
Removed the "Minimum Resolution with no Missing Codes" column in Internal Temperature Sensing
Diode Specifications for Arria 10 Devices table.
Added a link in the Internal Temperature Sensing Diode Specifications section: Transfer Function for
Internal TSD topic in the Power Management in Arria 10 Devices chapter, Arria 10 Core Fabric and General
Purpose I/Os Handbook.
•
•
Added descriptions to External Temperature Sensing Diode Specifications for Arria 10 Devices table.
Updated Internal Voltage Sensor Specifications for Arria 10 Devices table.
•
•
•
•
•
•
Updated maximum resolution from 12 bits to 8 bits. Removed minimum resolution value.
Updated maximum integral non-linearity (INL) from 3 LSB to 1 LSB.
Updated maximum clock frequency from 20 MHz to 11 MHz.
Added gain error and offset error specifications.
Removed signal to noise and distortion ratio (SNR) specifications.
Removed Bipolar input mode specifications.
•
•
Updated "slow clock" to "core clock" in DPA Lock Time Specifications with DPA PLL Calibration Enabled
diagram.
Updated the maximum values of the following conditions for Transmitter True Differential I/O Standards -
fHSDR (data rate) parameter in High-Speed I/O Specifications for Arria 10 Devices table.
•
•
SERDES factor J = 2, uses DDR registers
SERDES factor J = 1, uses DDR registers
•
•
Added the following tables:
•
•
Memory Standards Supported by the Hard Memory Controller for Arria 10 Devices
Memory Standards Supported by the Soft Memory Controller for Arria 10 Devices
Updated minimum TOCTCAL value from 1000 cycles to 2000 cycles in OCT Calibration Block Specifications
for Arria 10 Devices table.
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Date
Version
Changes
•
•
Updated the hmc_free_clk specifications for the following speed grades in HPS Clock Performance for
Arria 10 Devices table:
•
•
–1 speed grade: Updated from 667 MHz to 533 MHz.
–2 speed grade: Updated from 544 MHz to 533 MHz.
Changed from Tsclk to Tclk and added the following specifications in the Quad Serial Peripheral Interface
(SPI) Flash Timing Requirements for Arria 10 Devices table.
•
•
•
Tqspi_clk
Tdin_start
Tdin_end
•
Updated SPI Master Timing Requirements for Arria 10 Devices table.
•
•
•
•
Changed the symbol from Tspi_clk to Tclk
Added note to Tdssfrst, Tdsslst, and Th.
Updated note to Tsu.
.
Updated the description for Tsu and Th.
•
•
Updated the note to Tssfsu, Tssfh, Tsslsu, and Tsslh in the SPI Slave Timing Requirements for Arria 10 Devices
table.
Updated the following timing diagrams:
•
•
•
Quad SPI Flash Serial Output Timing Diagram
SPI Master Output Timing Diagram
SPI Slave Output Timing Diagram
•
Added the following timing diagrams:
•
•
•
Quad SPI Flash Serial Input Timing Diagram
SPI Master Input Timing Diagram
SPI Slave Input Timing Diagram
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Date
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Changes
•
•
Updated Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Arria 10 Devices table.
•
•
•
Changed Tclk to Tsdmmc_clk_out and TMMC_CLKto TSDMMC_CLK_OUT.
Updated Td min from 5.5 ns to 8.5 ns and max from 12.5 ns to 11.5 ns.
Updated note to Td.
Changed the title and symbols in the following timing diagrams:
•
•
•
Changed from "NAND Data Input Cycle Timing Diagram" to "NAND Data Output Cycle Timing
Diagram". Changed from DIN to DOUT
Changed from "NAND Data Output Cycle Timing Diagram" to "NAND Data Input Cycle Timing
Diagram". Changed from DOUT to DIN.
Changed from "NAND Extended Data Output (EDO) Cycle Timing Diagram" to "NAND Data Input
Timing Diagram for Extended Data Output (EDO) Cycle". Changed from DOUT to DIN.
.
•
•
•
Changed from "ARM Trace Timing Characteristics" to "Trace Timing Characteristics".
Updated the description in the GPIO Interface topic.
Updated FPP Timing Parameters When the DCLK-to-DATA[] Ratio is 1 for Arria 10 Devices table.
•
•
•
•
•
Updated the maximum value for tSTATUS and tCF2ST1 from 1,506 μs to 3,000 μs.
Updated fMAX for FPP ×8/×16 from 125 MHz to 100 MHz.
Updated the minimum value for tCF2CK from 1,506 μs to 3,010 μs.
Updated the minimum value for tST2CK from 2 μs to 10 μs.
Updated the maximum value for tCD2UM from 437 μs to 830 μs.
•
•
Updated FPP Timing Parameters When the DCLK-to-DATA[] Ratio is >1 for Arria 10 Devices table.
•
•
•
•
•
Updated the maximum value for tSTATUS and tCF2ST1 from 1,506 μs to 3,000 μs.
Updated fMAX for FPP ×8/×16 from 125 MHz to 100 MHz.
Updated the minimum value for tCF2CK from 1,506 μs to 3,010 μs.
Updated the minimum value for tST2CK from 2 μs to 10 μs.
Updated the maximum value for tCD2UM from 437 μs to 830 μs.
Updated maximum value for tCD2UM from 437 μs to 830 μs in AS Timing Parameters for AS ×1 and AS ×4
Configurations in Arria 10 Devices table.
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Date
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Changes
•
Updated PS Timing Parameters for Arria 10 Devices table.
•
•
•
•
Updated the maximum value for tSTATUS and tCF2ST1 from 1,506 μs to 3,000 μs
Updated the minimum value for tCF2CK from 1,506 μs to 3,010 μs.
Updated the minimum value for tST2CK from 2 μs to 10 μs.
Updated the maximum value for tCD2UM from 437 μs to 830 μs.
•
•
Added description about .rbf and .rpd files in the Configuration Files section. Changed the table title from
"Uncompressed Uncompressed .rbf Sizes Sizes for Arria 10 Devices" to "Configuration Bit Stream Sizes for
Arria 10 Devices".
Updated the note to Active Serial in Minimum Configuration Time Estimation for Arria 10 Devices table.
Note: The minimum configuration time is calculated based on DCLK frequency of 100 MHz. Only external
CLKUSRmay guarantee the frequency accuracy of 100 MHz. If you use internal oscillator of 100 MHz, you
may not get the actual frequency of 100 MHz. For the DCLK frequency using internal oscillator, refer to the
DCLK Frequency Specification in the AS Configuration Scheme table.
Changed instances of Quartus II to Quartus Prime.
Changed voltages and conditions in the "Transceiver Power Supply Operating Conditions for Arria 10 GX/
SX Devices" table.
•
•
•
•
Changed maximum data rate conditions in the "Transmitter and Receiver Data Rate Performance" table.
Changed conditions in the "Transmitter and Receiver Data Rate Performance" table in the Transceiver
Performance for Arria 10 GT Devices section.
•
•
•
•
•
Changed conditions in the "Reference Clock Specifications" table.
Changed the clock networks in the "Transceiver Clock Network Maximum Data Rate Specifications" table.
Changed conditions in the "Receiver Specifications" table.
Changed conditions in the "Transmitter Specifications" table.
Changed the minimum frequeny in the "ATX PLL Performance," "Fractional PLL Performance," and "CMU
PLL Performance" tables in the Transceiver Performance for Arria 10 GX/SX Devices section.
Changed the minimum frequeny in the "ATX PLL Performance," "Fractional PLL Performance," and "CMU
PLL Performance" tables in the Transceiver Performance for Arria 10 GT Devices section.
Added a parameter to the "Reference Clock Specifications" table.
•
•
•
Added footnote to the "Transmitter Specifications" table.
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Date
Version
Changes
June 2015
2015.06.12
•
Changed the specifications for the backplane maximum data rate condition in the "Transmitter and Receiver
Data Rate Performance" table for Arria 10 GX/SX devices.
•
•
Changed the specifications for transmitter REFCLKphase noise in the "Reference Clock Specifications" table.
Added note in the following tables:
•
•
•
Absolute Maximum Ratings for Arria 10 Devices: VCCPGM
Maximum Allowed Overshoot During Transitions for Arria 10 Devices: LVDS I/O
Recommended Operating Conditions for Arria 10 Devices: VI
•
•
Added HPS Specifications.
Updated recommended EPCQ-L serial configuration devices in the Uncompressed .rbf Sizes table.
May 2015
May 2015
2015.05.08 Made the following changes:
•
•
•
Changed the specifications for the VICM (AC coupled) parameter in the "Reference Clock Specifications"
table.
Changed the maximum frequency in the "CMU PLL Performance" table in the Transceiver Performance for
GT Devices section.
Added a footnote to the transceiver speed grade 5 column in the "Transmitter and Receiver Data Rate
Performance" table.
2015.05.04
•
•
Updated the Maximum Allowed Overshoot During Transitions for Arria 10 Devices table.
Added a note to tramp in the Recommended Operating Conditions for Arria 10 Devices table. Note: tramp is
the ramp time of each individual power supply, not the ramp time of all combined power supplies.
Changed the minimum, typical, and maximum values for the transmitter and receiver power supply in the
"Transceiver Power Supply Operating Conditions for Arria 10 GT Devices" table.
•
•
Added –1 speed grade in the condition column for VCCL_HPS at 0.95 V in HPS Power Supply Operating
Conditions for Arria 10 SX Devices table.
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Date
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Changes
•
Added –I1S, –I2S, and –E2S speed grades to the following tables:
•
•
•
•
•
Clock Tree Performance for Arria 10 Devices
DSP Block Performance Specifications for Arria 10 Devices
Memory Block Performance Specifications for Arria 10 Devices
High-Speed I/O Specifications for Arria 10 Devices
Memory Output Clock Jitter Specifications for Arria 10 Devices
•
•
•
•
Updated fIN minimum value from 27 MHz to 50 MHz for all speed grades in the Fractional PLL Specifica‐
tions for Arria 10 Devices table.
Changed the description for fINPFD to "Input clock frequency to the PFD" in the I/O PLL Specifications for
Arria 10 Devices table.
Updated DSP Block Performance Specifications for Arria 10 Devices table for VCC and VCCP at 0.9 V typical
value. Added DSP specifications for VCC and VCCP at 0.95 V typical value.
Updated Ibias minimum value from 8 μA to 10 μA and maximum value from 200 μA to 100 μA in the
External Temperature Sensing Diode Specifications for Arria 10 Devices table.
Added DPA (soft CDR mode) specifications in High-Speed I/O Specifications for Arria 10 Devices table.
Added description in POR Specifications section: Power-on reset (POR) delay is defined as the delay
between the time when all the power supplies monitored by the POR circuitry reach the minimum
recommended operating voltage to the time when the nSTATUSis released high and your device is ready to
begin configuration.
•
•
•
•
Moved the following timing diagrams to the Configuration, Design Security, and Remote System Upgrades
in Arria 10 Devices chapter.
•
•
•
•
FPP Configuration Timing Waveform When the DCLK-to-DATA[] Ratio is 1
FPP Configuration Timing Waveform When the DCLK-to-DATA[] Ratio is >1
AS Configuration Timing Waveform
PS Configuration Timing Waveform
Removed the DCLK-to-DATA[] ratio when both encryption and compression are turned on. Added
description to the table: You cannot turn on encryption and compression at the same time for Arria 10
devices.
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Date
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Changes
•
Updated the AS Timing Parameters for AS ×1 and AS ×4 Configurations in Arria 10 Devices table as
follows:
•
•
•
Changed the symbol for data hold time from tH to tDH
Updated the minimum value for tSU from 0 ns to 1 ns.
Updated the minimum value for tDH from 2.5 ns to 1.5 ns.
.
•
•
Added a note to the DCLK Frequency Specification in the AS Configuration Scheme table. Note: You can
only set 12.5, 25, 50, and 100 MHz in the Quartus Prime software.
Added a note to the Initialization Clock Source Option and the Maximum Frequency for Arria 10 Devices.
Note: If you use the CLKUSRpin for AS and transceiver calibration simultaneously, the only allowed
frequency is 100 MHz.
•
Changed Arria 10 GS to Arria 10 SX in Uncompressed .rbf Sizes and Minimum Configuration Time
Estimation tables.
•
•
Added IO_IN_DLY_CHN and IO_OUT_DLY_CHN in the IOE Programmable Delay table.
Changed the Min/Typ/Max description for the VICM (AC coupled) parameter in the "Reference Clock
Specifications" table.
•
•
•
•
Changed the Min/Typ/Max values in the "Transceiver Power Supply Operating Conditions for Arria 10 GX/
SX Devices" table.
Changed the Min/Typ/Max values in the "Transceiver Power Supply Operating Conditions for Arria 10 GT
Devices" table.
Added a footnote to the maximum data rate for GT channels in the "Transceiver Performance for GT
Devices" section.
Made the following changes to the "Transceiver Performance for Arria 10 GX/SX Devices" section.
•
Changed the maximum data rate condition for chip-to-chip and backplane in the "Transmitter and
Receiver Data Rate Performance" table.
•
•
•
•
Added TX minimum data rate to the "Transmitter and Receiver Data Rate Performance" table.
Changed the minimum frequency in the "ATX PLL Performance" table.
Changed the minimum frequency in the "Fractional PLL Performance" table.
Changed the minimum and maximum frequency in the "CMU PLL Performance" table.
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Date
Version
Changes
•
•
Made the following changes to the "Transceiver Performance for Arria 10 GT Devices" section.
•
•
Added TX minimum data rate to the "Transmitter and Receiver Data Rate Performance" table.
Changed the maximum data rate condition for chip-to-chip and backplane in the "Transmitter and
Receiver Data Rate Performance" table.
•
•
•
Changed the minimum frequency in the "ATX PLL Performance" table.
Changed the minimum frequency in the "Fractional PLL Performance" table.
Changed the minimum frequency in the "CMU PLL Performance" table.
Added voltage condition to the maximum peak-to-peak diff p-p after configuration and to the VICM specifi‐
cations in the "Receiver Specifications" table.
•
•
•
Changed the voltage conditions for VOCM in the "Transmitter Specifications" table.
Changed the VOD/VCCT Ratios in the "Typical Transmitter VOD Settings" table.
Added the "Transceiver Clock Network Maximum Data Rate Specifications" table.
January 2015
2015.01.23
•
•
Added a note in the "Transceiver Power Supply Operating Conditions" section.
Made the following changes to the "Reference Clock Specifications" table:
•
•
•
•
Added the input reference clock frequency parameters for the CMU PLL, ATX PLL, and fPLL PLL.
Changed the maximum specification for rise time and fall time.
Added the VICM (AC and DC coupled) parameters.
Changed the maximum value for Transmitter REFCLK Phase Noise (622 MHz) when ≥ 1 MHz.
•
•
Changed the Min, Typ, and Max values for the reconfig_clksignal in the "Transceiver Clocks Specifica‐
tions" table.
Made the following changes to the "Receiver Specifications" table:
•
•
Added the maximum peak-to-peak differential input voltage after device configuration specifications.
Changed the minimum specification for the minimum differential eye opening at receiver serial input
pins parameter.
•
Removed the 120-ohm and 150-ohm conditions for the differential on-chip termination resistors
parameter.
•
•
Added the VICM (AC and DC coupled) parameter.
Added the Programmable DC Gain parameter.
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Changes
•
Made the following changes to the "Transmitter Specifications" table:
•
•
•
Added the VOCM (AC coupled) parameter.
Added the VOCM (DC coupled) parameter.
Changed the rise and fall time mimimum and maximum specifications.
•
•
Added the "Typical Transmitter VOD Settings" table.
Added a note to VCC, VCCP, and VCCERAM typical values in Recommended Operating Conditions table.
Note: You can operate –1 and –2 speed grade devices at 0.9 V or 0.95 V typical value. You can operate -3
speed grade device at only 0.9 V typical value. Core performance shown in this datasheet is applicable for the
operation at 0.9 V. Operating at 0.95 V results in higher core performance and higher power consumption.
For more information about the performance and power consumption of 0.95 V operation, refer to the
Quartus Prime software timing reports and Early Power Estimator (EPE).
•
•
Removed military grade operating junction temperature specifications (TJ) in Recommended Operating
Conditions table.
Updated the VCCIO range for HSTL-18 I/O standard in Differential HSTL and HSUL I/O Standards for
Arria 10 Devices table as follows:
•
•
•
Min: Updated from 1.425 V to 1.71 V
Typ: Updated from 1.5 V to 1.8 V
Max: Updated from 1.575 V to 1.89 V
•
•
•
Added a statement to Differential I/O Standards Specifications for Arria 10 Devices table: Differential inputs
are powered by VCCPT which requires 1.8 V.
Added statement in I/O Standard Specifications: You must perform timing closure analysis to determine the
maximum achievable frequency for general purpose I/O standards.
Updated fractional PLL specifications.
•
•
•
Updated fOUT_C to fOUT and updated the maximum value to 644 MHz for all speed grades.
Updated fVCO minimum value from 2.4 GHz to 3.125 GHz.
Removed fOUT_L, kVALUE, and fRES parameters.
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Date
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Changes
•
Updated I/O PLL specifications.
•
•
Updated fOUT_C to fOUT and updated the maximum value to 644 MHz for all speed grades.
Updated fOUT_EXT maximum value to 800 MHz (–1 speed grade), 720 MHz (–2 speed grade), and 650
MHz (–3 speed grade).
•
Removed fRES parameter.
•
•
Updated the description in Periphery Performance Specifications to mention that proper timing closure is
required in design.
Updated AS Timing Parameters for AS x1 and AS x4 Configurations in Arria 10 Devices.
•
•
Updated tSU minimum value from 1.5 ns to 0 ns.
Updated tH minimum value from 0 ns to 2.5 ns.
•
•
•
Updated CLKUSRinitialization clock source maximum frequency from 125 MHz to 100 MHz for passive
configuration schemes (PS and FPP).
Added uncompressed .rbf sizes and minimum configuration time estimation for Arria 10 GX and GS
devices.
Updated uncompressed .rbf sizes for Arria 10 GX 900 and 1150 devices, and Arria 10 GT 900 and 1150
devices.
•
•
Updated configuration .rbf size from 335,106,890 bits to 351,292,512 bits.
Updated IOCSR .rbf size from 6,702,138 bits to 1,885,396 bits.
•
Updated minimum configuration time estimation for Arria 10 GX 900 and 1150 devices, and Arria 10 GT
900 and 1150 devices for the following configuration modes:
•
•
Active serial: Updated from 837.77 ms to 883.20 ms.
Fast Passive Parallel: Updated from 104.72 ms to 110.40 ms.
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Changes
August 2014
2014.08.18
•
•
Changed the 3 V I/O conditions in Table 2.
Table 3:
•
•
•
Added a note to the Minimum and Maximum operating conditions.
Changed VCCERAM values.
Changed the Maximum recommended operating conditions for 3 V I/O VI.
•
•
•
Added a note to the I/O pin pull-up tolerance in Table 12.
Changed the VIH values for LVTTL, LVCMOS and 2.5 I/O standards in Table 13.
Table 14, Table 15, and Table 16:
•
•
Added SSTL-12 I/O standard.
Removed Class I, II for SSTL-135 and SSTL-125 I/O standards.
•
Table 19:
•
•
•
Changed the minimum data rate specification for transmitter and receiver data rates.
Changed the minimum frequency specification for the fractional PLL.
Changed the minimum frequency specification for the CMU PLL.
•
•
Changed the Core Speed Grade with Power Options section in Table 20.
Table 21:
•
•
•
•
Changed the minimum data rate specification for transmitter and receiver data rates.
Changed the minimum frequency specification for the Fractional PLL.
Changed the minimum frequency specification for the CMU PLL.
Changed the minimum frequency of the ATX PLL.
•
Table 23:
•
•
Added a note to the High Speed Differential I/O standard.
Changed the specifications for CLKUSR pin.
•
•
•
•
Added columns in Table 29.
Changed the maximum fHSCLK_in and txJitter in Table 32.
Changed the minimum formula for tCD2UMC in Table 42, Table 43, Table 44, and Table 46.
Changed the CLKUSR maximum frequency and minimum number of cycles in Table 47.
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•
Table 48:
•
•
Changed the IOCSR .rbf size.
Added Recommended EPCQ-L Serial Configuration Device.
•
•
Changed the DCLK frequency and minimum configuration time for FPP in Table 49.
Added the following tables:
•
•
External Temperature Sensing Diode Specifications for Arria 10 Devices
IOE Programmable Delay for Arria 10 Devices
•
Removed the following figures:
•
•
CTLE Response in High Gain Mode for Arria 10 Devices with Data Rates ≥ 8 Gbps
Removed the CTLE Response in High Gain Mode for Arria 10 Devices with Data Rates < 8 Gbps
March 2014
2014.03.14 Updated Table 3, Table 5, Table 21, Table 23, Table 24, Table 32, and Table 41.
2013.12.06 Updated Figure 1 and Figure 2.
December 2013
December 2013
2013.12.02 Initial release.
Arria 10 Device Datasheet
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Altera Corporation
相关型号:
10AX066H5F34I3SG
Field Programmable Gate Array, 660000-Cell, CMOS, PBGA1152, 35 X 35 MM, ROHS COMPLIANT, FBGA-1152
INTEL
10AX066H5F34I3SP
Field Programmable Gate Array, 660000-Cell, CMOS, PBGA1152, 35 X 35 MM, FBGA-1152
INTEL
10AX066K2F40I2LG
Field Programmable Gate Array, 660000-Cell, CMOS, PBGA1517, 40 X 40 MM, ROHS COMPLIANT, FBGA-1517
INTEL
10AX066K3F40E2SG
Field Programmable Gate Array, 660000-Cell, CMOS, PBGA1517, 40 X 40 MM, ROHS COMPLIANT, FBGA-1517
INTEL
10AX066N2F40E2SG
Field Programmable Gate Array, 660000-Cell, CMOS, PBGA1517, 40 X 40 MM, ROHS COMPLIANT, FBGA-1517
INTEL
10AX066N2F40I2LG
Field Programmable Gate Array, 660000-Cell, CMOS, PBGA1517, 40 X 40 MM, ROHS COMPLIANT, FBGA-1517
INTEL
10AX066N3F40E2SG
Field Programmable Gate Array, 660000-Cell, CMOS, PBGA1517, 40 X 40 MM, ROHS COMPLIANT, FBGA-1517
INTEL
10AX090H2F34I2SG
Field Programmable Gate Array, 900000-Cell, CMOS, PBGA1152, 35 X 35 MM, ROHS COMPLIANT, FBGA-1152
INTEL
10AX090H4F34E3SG
Field Programmable Gate Array, 900000-Cell, CMOS, PBGA1152, 35 X 35 MM, ROHS COMPLIANT, FBGA-1152
INTEL
10AX090H4F34I3SG
Field Programmable Gate Array, 900000-Cell, CMOS, PBGA1152, 35 X 35 MM, ROHS COMPLIANT, FBGA-1152
INTEL
10AX090N2F40E1SG
Field Programmable Gate Array, 900000-Cell, CMOS, PBGA1517, 40 X 40 MM, ROHS COMPLIANT, FBGA-1517
INTEL
10AX090N3F40I2SG
Field Programmable Gate Array, 900000-Cell, CMOS, PBGA1517, 40 X 40 MM, ROHS COMPLIANT, FBGA-1517
INTEL
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