XDPL8221 [INFINEON]
Digital high power factor XDP™ controller for advanced, dual stage LED drivers with constant voltage primary side regulation;
| 型号： | XDPL8221 |
| 厂家： | 
Infineon |
| 描述： | Digital high power factor XDP™ controller for advanced, dual stage LED drivers with constant voltage primary side regulation |
| 文件： | 总57页 (文件大小：749K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
XDPL822x Controller Family
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Data Sheet
Revision 1.1
Features
•
•
•
UART interface to control driver output and reading operating status
Flicker-free output dimming by analog reduction of driving current down to 1%
Integrated two stage digital controller allows a reduced number of external parts, optimizes Bill of
Materials (BOM) and form factor.
•
•
•
•
•
Two-stage design eliminates AC ripple on output.
Supports universal AC and DC input voltage (90 V rms to 305 V rms) nominal.
High efficiency up to 90%
Multi-control output (Constant Current (CC)/Constant Voltage (CV)/Limited Power (LP))
Performance and protection related driver parameters are configurable via UART interface allowing for
design flexibility and optimization.
•
•
•
•
Low harmonic distortion (Total Harmonic Distortion (THD) < 15%) down to 30% nominal load
Integrated 600V high voltage start-up cell ensures fast time to light (< 250 ms)
Configurable Adaptive Temperature Protection
Automatic switching of the Power Factor Correction (PFC) between Quasi-Resonant Mode (QRM) and
Discontinuous Conduction Mode (DCM)
•
•
Automatic switching of the Flyback (FB) between QRM, DCM and Active Burst Mode (ABM)
Pulse Width Modulation (PWM) dimming input
For safe operation, the XDPL8221 contains a comprehensive set of protection features with configurable
reaction like auto-restart or latch:
•
•
•
•
•
•
Output over-voltage protection (open load)
Output under-voltage protection (output short)
VCC over- and under-voltage lockout
Input over- and under-voltage protection
Bus over- and under-voltage protection
Over-current protection for both PFC and FB stages
Applications
•
AC/DC LED Drivers for Light Emitting Diode (LED) luminaires
Data Sheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Description
L
Input
voltage
CoolMOS™
GDPFC
LED+
LED-
CSPFC
CoolMOS™
GDFB
CSFB
N
TEMP
XDPL8221
VCC
HV
VS
ZCD
GND
UART
PWM
PWM
UART
GND
Vsupply
Figure 1
Typical Application for XDPL8221
Product Type
Package
PG-DSO-16
XDPL8221
Description
XDPL8221 is a highly integrated next-generation device combining a multimode (QRM and DCM) PFC plus a
multimode (QRM, DCM and ABM) FB with primary-side regulation. The integration of PFC and FB into a single
controller enables reduction of external parts and optimizes performance by harmonized operation of the two
stages.
The two-stage approach divides the PFC responsibilities from the output current regulations functions. This
ensures low variation in the output current (flicker) to a non-visible level and allows for low THD , high power
factor and a greater ability to withstand AC line perturbations.
XDPL8221 PFC comprises of constant on-time scheme with a THD improvement algorithm to provide a high
power factor and excellent performance down to 30% nominal load.
XDPL8221 FB can be configured to operate in Constant Voltage (CV), Constant Current (CC) or Limited Power
(LP) mode offering a large degree of flexibility.
The on-chip One Time Programmable Memory (OTP) memory allows user to adjust electrical and performance
parameters that control the behavior of the circuit. Examples of this include: output current limit or the
maximum output power. This enables the user of the device to create a platform concept with significantly
fewer different hardware versions while still covering the same application range.
The Universal Asynchronous Receiver Transmitter (UART) command interface allows connecting XDPL8221 to
any microcontroller, wireless interface or sensor for many different applications.
During low power mode, the XDPL8221 power consumption is less than 100mW.
Data Sheet
2
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Table of contents
Table of contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1
2
3
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.1.5.1
3.1.6
3.1.6.1
3.1.6.2
3.1.6.3
3.1.7
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
PFC Controller Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Shared CS/ZCD Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Quasi-resonant Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Bus Voltage Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Input Voltage Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Multimode Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Frequency Law . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
THD Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Light Load Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Peak Current Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Protection Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Bus Under-voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Bus Over-voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Input Under-voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Input Over-voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Other PFC Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Flyback Controller Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Primary Side Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Primary Side Current Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Primary Side Output Voltage Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Output Current Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Output control scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Multimode Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Flyback Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Protection features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Primary Over-current Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Output Under-voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Output Over-voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
3.1.8
3.1.8.1
3.1.8.2
3.1.8.3
3.1.8.4
3.1.8.5
3.2
3.2.1
3.2.1.1
3.2.1.2
3.2.1.3
3.2.1.4
3.2.1.5
3.2.1.6
3.2.2
3.2.3
3.2.3.1
3.2.3.2
3.2.3.3
Data Sheet
3
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Table of contents
3.2.3.4
3.2.3.5
3.2.3.6
3.2.3.6.1
3.3
3.3.1
3.3.2
3.3.3
3.3.4
Output Over-current Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Output Over-power Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Other Flyback Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Flyback Bus Voltage Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
General Controller Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Configurable Gate Driver Strengths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
External Temperature Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Adaptive temperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
PWM Dimming Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
UART Command Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Protection features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Overtemperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
VCC Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
VCC Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
VCC Undervoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Other General Controller Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Protection Reactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Auto restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Fast Auto Restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Latch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.3.5
3.3.6
3.3.6.1
3.3.6.2
3.3.6.3
3.3.6.4
3.3.6.5
3.3.7
3.3.7.1
3.3.7.2
3.3.7.3
3.3.7.4
4
Electrical Characteristics and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.1
4.2
4.3
4.4
5
6
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Data Sheet
4
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Pin Configuration
1
Pin Configuration
Pin assignments and basic pin description information are shown below.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GDFB
CSFB
VCC
GND
ZCD
VS
N.C.
N.C.
UART
GDPFC
N.U.
CSPFC
TEMP
PWM
N.U.
HV
PG-DSO-16 (150mil)
Figure 2
Table 1
Pinning of XDPL8221
Pin Definitions and Functions
Name
Pin
Type
Function
GDFB
1
O
Gate driver for FB:
The GDFB pin is an output for directly driving a power MOSFET of the FB
stage.
CSFB
2
I
Current sensing for FB:
The CSFB pin is connected to an external shunt resistor and the source of the
power MOSFET of the FB stage.
VCC
GND
ZCD
3
4
5
I
-
I
Voltage supply
Power and signal ground
Zero-crossing detection of the FB:
The ZCD pin is connected to an auxiliary winding of the FB stage for zero-
crossing detection as well as primary-side output voltage and additional bus
voltage sensing for functional safety.
VS
6
7
8
I
-
I
Bus voltage sensing
N.U.
HV
Not used. Externally to be connected to GND.
High voltage:
The HV pin is connected to the rectified input voltage via an external resistor.
An internal 600 V HV startup-cell is used to initially charge VCC. In addition,
sampled high-voltage sensing is also used for synchronization with the input
frequency.
PWM
9
I
I
PWM dimming:
The PWM pin is used as a dimming input.
TEMP
10
External temperature sensor:
Measurement of external temperature using an Negative Temperature
Coefficient Thermistor (NTC).
CSPFC
11
I
Current sensing for PFC:
The CSPFC pin is connected to an external shunt resistor and the source of
the power MOSFET of the PFC stage.
Data Sheet
5
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Functional Block Diagram
Table 1
Pin Definitions and Functions (continued)
Name
N.U.
Pin
12
Type
Function
-
Not used. Externally to be connected to GND.
GDPFC
13
O
Gate driver for PFC:
The GDPFC pin is an output for directly driving a power MOSFET of the PFC
stage.
UART
14
I/O
UART communication:
The UART pin is used for the UART interface to support parametrization and
for application commands during run-time.
N.U.
N.U.
15
16
-
-
Not used. Externally to be connected to GND.
Not used. Externally to be connected to GND.
2
Functional Block Diagram
The functional block diagram shows the basic data flow from input pins via signal processing to the output pins.
Power Factor Correction
Flyback
Input Voltage
Sensing and
Startup
Output Voltage
Sensing and Zero
Crossing Detection
HV
GDPFC
CSPFC
VS
ZCD
PFC Control
Loop
Output Current
Calculation
CSFB
GDFB
Current Sensing and
Zero Crossing
Detection
FB Control Loop
Bus Voltage
Sensing
Adaptive
Temperature
Protection
PWM Dimming
Sensing
PWM
UART
VCC
Management
UART Command
Interface
VCC
External
Temperature
Sensing
TEMP
Figure 3
XDPL8221 Simplified Functional Block Diagram
Data Sheet
6
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Functional Description
3
Functional Description
This chapter provides a summary of the integrated functions and features, and describes the relationships
between them. The parameters and equations are based on typical values at TA = 25 °C.
XDPL8221 is a digital dual-stage PFC and FB controller IC supporting PWM dimming functionality. Both stages
use configurable multi-mode operation to select the best mode of operation for every operation condition.
Multi-mode operation automatically switches between QRM, DCM and ABM (only for FB)
XDPL8221 features a comprehensive set of configurable protection modes to detect fault conditions.
XDPL8221 provides a high degree of flexibility in design-in of the application. A Graphic User Interface (GUI)
tool supports users in the configuration of the operational and protection parameters.
Data Sheet
7
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Functional Description
3.1
PFC Controller Features
The PFC stage ensures high power quality by maximizing the power factor and minimizing harmonic distortion.
The PFC stage operates in Quasi-Resonant Mode, switching in first valley (QRM1) and Quasi-Resonant Mode,
switching in valley n (QRMn), to support light load conditions and ensure efficient operation.
The PFC stage is implemented as a boost converter and provides stabilized Direct Current (DC) voltage rail.
3.1.1
Shared CS/ZCD Function
The PFC stage makes use of combined Current Sense and Zero-Crossing Detection (CS/ZCD) functionality at the
CSPFC pin.
During the PFC MOSFET on-time, the CSPFC pin has the function of sensing the PFC inductor current ensuring
inductor does not enter saturation, and the converter limits maximum switching current.
The CSPFC pin is connected to an external shunt resistors, which converts the inductor current to voltage. The
sensed voltage at the CSPFC pin is compared with reference voltages on internal comparators to either limit the
on-time cycle by cycle or enter the protection mode when over-current happens.
During the PFC MOSFET off-time, the CSPFC pin has the function of current zero crossing detection (ZCD). This
detection minimizes the turn-on losses of the PFC MOSFET by ensuring the MOSFET turns-on during the
resonant valley of the PFC MOSFET drain-source voltage (VDS) (QRM). The CSPFC pin is connected via an
external resistor divider composed of RZCD,1,PFC and RZCD,2,PFC and a set of diodes to the auxiliary winding of the
PFC inductor.
Diode D1 allows positive voltage at the CSPFC pin as the valley detection is implemented by the internal
hysteretic comparator with a positive reference of nominal THRHYS for falling edges.
Vg
L
Vbus
RZCD,1,PFC
D1
GDPFC
CSPFC
RZCD,2,PFC
RCS,PFC
VCC
Figure 4
Shared CS/ZCD Schematic
3.1.2
Quasi-resonant Mode
The quasi-resonant mode maintains a high efficiency level.
XDPL8221 PFC Quasi-resonant mode reduces PFC MOSFET switching losses and ensures highest possible
efficiency of the system. See Multi-mode Scheme description for detailed QRM operation in section 3.1.6.
Data Sheet
8
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Functional Description
tsw
tsw
iL
iL,pk
iL,ave
tw
0
t
t
ton
tLEB
t1stV
vCSPFC
vL,pk
tosc
4
0
tdisch
QRM2
QRM1
QRM1
Figure 5
PFC QRM2 Waveforms
Equations for the quasi-resonant operation are shown below. Delay time tw is an additional delay realized in
each switching cycle when PFC MOSFET turn-on beyond first resonant valley and valley n (n>1) is selected
(QRMn).
Vg · ton
iL, pk
=
L
iL, pk · L
Vbus − Vg
tdisch
=
t1stV = tdisch + tosc/2
tw = tosc · n − 1
tsw = ton + t1stV + tw
toff = t1stV + tw
Equation 1
3.1.3
Bus Voltage Sensing
The PFC output bus voltage is scaled down using a simple resistor divider and measured at the pin VS. A
capacitor shall be added at the pin to ground to filter high-frequency switching noise.
Vbus
RVS,1
VS
RVS,2
Figure 6
PFC Bus Voltage Sensing Circuit
The Analog-to-Digital Converter (ADC) input at the VS pin utilizes two voltage ranges. The wider voltage range
from 0 to VREF results in lower resolution. The narrower voltage range from 5/6 VREF to 7/6 VREF gives better
voltage resolution. Steady state operation therefore normally takes place in the high-resolution range and soꢀ
start operation in the low-resolution range.
Data Sheet
9
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Functional Description
VS
7/6 VREF
High
resolution
range
VREF
5/6 VREF
Low
resolution
range
0 V
t
Figure 7
Sensing Ranges
3.1.4
Input Voltage Sensing
The input voltage is sensed at the HV pin for Alternating Current (AC) zero-crossing detection and protection
features.
iac
vac
Input
voltage
RHV
Vin
HV
C1
C2
Figure 8
Input Voltage Sensing Schematic
The RHV sense resistor is usually split into two or more resistors for redundancy and safety purposes. A RC filter
structure to the HV pin is implemented as shown above to reduce the unwanted noise.
Data Sheet
10
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Functional Description
3.1.5
Control Scheme
The PFC bus voltage controller embeds a controller that calculates a control output representing load and line
conditions from the bus voltage error signal.
The bus voltage controller implements regulation during both soꢀ start and steady states.
3.1.5.1
Startup
At system startup, the PFC initiates soꢀ start to minimize the switching stress on the power MOSFET, diode and
inductor.
PFC soꢀ start is executed once the PFC bus voltage is charged due to rectified AC line to a voltage threshold
Vbus,start,PFC but lower than Vbus,OVP1. The PFC soꢀ start is aborted if the input under- or over-voltage protections
are triggered. During soꢀ start, the PFC operates in QRM1mode. Once the Vbus,stdy,entr,UV threshold is reached,
the steady state PFC operation starts.
Vbus
Vbus,set
Vbus,stdy,entr,UV
Vbus,start,PFC
t
VCC startup
passive charging
steady state
charging
Figure 9
Vbus Soꢀ Start and Regulation
3.1.6
Multimode Control Scheme
The XDPL8221 multi-mode control scheme provides an option to dynamically change the operating point by
switching between the MOSFET Vds voltage valleys while following a frequency law and applying THD
optimization.
The multi-mode controller uses three different modes of operation:
•
QRM1: operation occurs during normal operation of the PFC converter at nominal to heavy loads. This
operation maximizes the efficiency by switching on at the 1st valley of the PFC ZCD signal. This ensures zero
current switching with a minimum switching losses. During QRM1, the PFC MOSFET is turned on with a
constant on-time for a line and load condition, while the off- time varies within an AC half-cycle depending
on the instantaneously rectified AC input voltage. Subsequently, the PFC switching frequency varies within
each AC half-cycle with the lowest switching frequency at the peak of the AC input voltage and the highest
switching frequency near the zero crossings of the input voltage.
•
•
QRMn: PFC MOSFET on-time reduces as the load decreases, this results in higher switching frequencies,
particularly near the zero-crossing of the input voltage. Higher switching frequencies will increase
switching losses, resulting in poor efficiency at light loads. The XDPL8221 controller extends to the next
switching valley aꢀer the 1st valley to control the bus voltage following a frequency law which limits the
switching frequency to minimize the switching losses.
DCM: The controller regulates the power transfer by adjusting the switching frequency with fixed minimum
on-time. This enables the light load optimization.
Data Sheet
11
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Functional Description
The multimode optimization consists of the following:
•
•
•
•
Frequency law
THD optimization
DC switching frequency dithering
Light load optimization
3.1.6.1
Frequency Law
A PFC converter is used to emulate a resistive load re to the AC input such that iac follows vac in both wave shape
and phase. The output of the PFC bus voltage controller ton,des,PFC is inversely proportional to the emulated
resistive load re such that a smaller re or a higher Iac,rms will give a larger ton,des,PFC. Thus, ton,des,PFC varies as the
AC line voltage magnitude varies and is proportional to the RMS input current Iac,rms
.
The rule for selecting QRMn is based on the frequency law. A maximum switching frequency fswmax and a
minimum switching frequency fswmin are defined for the complete ton,des,PFC/Iac,rms range. The frequency law
ensures that the switching frequency is within the desired frequency range. The frequency law is depicted in the
figure below.
fsw
fswmax
fswmin
sample
ton,des,PFC
/ Iac,rms
operating
point
Figure 10
PFC Frequency Law
As long as the PFC controller operating mode satisfies the frequency law, the operating mode does not change.
The QR-valley is increased when the highest frequency limit is reached. The QR-valley is decremented when the
lowest frequency limit is reached.
To ensure proper ZCD detection before the ZCD signal becomes too small in amplitude, only the first up to
Nvalley,max,PFC valleys operations are supported.
3.1.6.2
THD Optimization
QRMn selection beyond the first valley during light load and/or AC high line reduces the switching frequency but
distorts the input current waveform with constant on-time control andTHD may suffer. The multi-mode PFC
control consists of a THD optimization algorithm that optimizes the applied on-time in order to ensure good
input current shaping and improved PFC THD performance.
Data Sheet
12
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Functional Description
Vin
t
ton
QRM3
QRM2
QRM1
BCM
t
Figure 11
THD optimization on-time
Figure 11 shows the on-time at different valley selection at the same line and load conditions.
Note:
Boundary Conduction Mode (BCM) is an operating mode where the switch turns on at the first
occurrence of inductor zero current .
3.1.6.3
Light Load Optimization
This paragraph describes how the PFC manages light load conditions.
DCM
PFC converter will eventually enter DCM operation as load decreases and/or AC line increases to reduce the
switching frequency and switching losses. XDPL8221 PFC control enters DCM when the internal on-time is less
than ton,dcm. The PFC leaves DCM when the switching period is less than tsw,min,dcm. When the PFC is operating in
DCM, the bus voltage controller regulates the switching period keeping the on-time constant. Due to the on-
time dependency on the input voltage, the PFC enters and exits DCM at different power levels. This has the
advantage to operate in QRM for an extended power range at low line maintaining high efficiency.
3.1.7
Peak Current Limitation
The peak current through the switching MOSFET is sensed via the PFC shunt resistor RCS,PFC to limit the
maximum current through the MOSFET, the choke, and freewheeling diode.
Overcurrent Protection Level 1 (OCP1) is implemented by hardware. If the voltage VCS,PFC across the shunt
resistor exceeds the over-current threshold VCS,OCP1, PFC for longer than the blanking time tblank,OCP1,PFC, the
MOSFET is turned off. The MOSFET is turned on when ZCD occurs or the PFC maximum period time-out signal
triggers the start of the next switching cycle. Overcurrent Protection Level 2 (OCP2) is a second-level
overcurrent protection implemented by hardware. The OCP2 overcurrent threshold is fixed. The OCP2 blanking
time is tblank,OCP2,PFC
.
Data Sheet
13
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Functional Description
3.1.8
Protection Features
Protections features are triggered if fault conditions are present longer than the blanking times for each
protection.
Attention: The controller may continue operation aꢀer exceeding protection thresholds because of
blanking times as shown in Figure 12. All protection thresholds have to be set with respect to
tolerances, blanking times and worst case transients.
Note:
The blanking time as specified in the csv file does not include the protection notification time.
Sampled voltage
Protection
or sampled current
Sampled voltage
triggering
Overvoltage or Overcurrent
protection threshold
Protection
triggering
Undervoltage
protection threshold
Time
Time
tblank
tblank
Figure 12
Blanking Times cause Excess of Threshold
3.1.8.1
Bus Under-voltage Protection
Under-voltage detection of the PFC bus voltage Vbus is sensed at the VS pin.
The PFC bus voltage is sensed and compared to a configurable under-voltage protection threshold Vbus,UV. If the
bus voltage is below the threshold for longer than the blanking time tblank,Vbus,UV, the protection will be
triggered.
3.1.8.2
Bus Over-voltage Protection
Over-voltage detection of the PFC bus voltage Vbus is sensed at the VS pin.
The PFC bus voltage is sensed and compared to a configurable over-voltage protection threshold Vbus,OVP1 in
Firmware (FW). If this threshold is exceeded for longer than the blanking time tblank,Vbus,OVP1, the PFC stops
switching. The PFC resumes operation when Vbus falls below Vbus,stdy,entr,OV
.
Vbus,OVP2 is implemented in Hardware (HW) and it is fixed at a voltage which is represented as 7/6 VREF at the
bus voltage sensing pin (VS). The HW permits a blanking time tblank,Vbus,OVP2 to be programmed.
Data Sheet
14
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Functional Description
Vbus
Vbus,ovp2
Vbus,ovp1
Vbus,stdy,entr,OV
Vbus,set
Vbus,uv
t
Figure 13
Vbus protections
3.1.8.3
Input Under-voltage Protection
Under-voltage detection of the input voltage Vin is sensed at the HV pin.
Values of Vin,rms are compared to a configurable input undervoltage protection threshold Vin,UV. If the input
voltage is below the threshold for longer than the blanking time tblank,Vin,UV, the protection will be triggered.
XDPL8221 features a configurable start-up threshold Vin,start,min to create hysteresis for flicker-free operation
before the second stage starts switching.
3.1.8.4
Input Over-voltage Protection
Over-voltage detection of the input voltage Vin is sensed at the HV pin.
Values of Vin,rms are compared to a configurable input over-voltage protection threshold Vin,OV. If the threshold is
exceeded for longer than the blanking time tblank,Vin,OV, the protection will be triggered. XDPL8221 features a
configurable start-up threshold Vin,start,max to create hysteresis for flicker-free operation before the second stage
starts switching.
Vin
Vin,OV
Vin,start,max
Vin,start,min
Vin,UV
t
tstart,delay,FB
Figure 14
Vin protections
Data Sheet
15
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Functional Description
3.1.8.5
Other PFC Protections
Current Sense (CS) Resistor Short Protection
The input fuse should be chosen appropriately to protect converter if current-sense resistor is shorted.
Current Sense (CS) Resistor Open Protection
CS/ZCD external circuitry pulls the CSPFC pin high when CS resistor is open, OCP2 protection is triggered.
CSPFC Pin Short to GND Protection
In case of CSPFC pin short to ground the missing of quasi-resonant oscillations will trigger the CCM Protection.
CCM Protection
Continuous conduction mode (CCM) operation may occur during PFC startup for a limited time and is allowed.
In normal operation, extended CCM operation in the PFC converter is considered a failure.
Circumstances where the PFC converter may experience CCM operation:
•
•
•
Shorted PFC bypass diode
Heavy load step which is out of specification
Low input voltage outside the normal operating range
During CCM operation, the magnetizing current in the PFC choke does not decay to zero prior to MOSFET turn-
on. Quasi-resonant oscillation is missing in the ZCD signal before the maximum switching period time-out is
reached that turns the MOSFET on. This turn-on event without ZCD oscillation is monitored to protect the PFC
converter from continuous CCM operation. Extended CCM operation protection is implemented within FW.
If quasi-resonant oscillation is missing in the ZCD signal for longer than the blanking time tblank,CCM,PFC, the
protection is triggered.
Soꢀ Start Failure
PFC start-up time maybe extended due to abnormally heavy loads or a low input voltages. PFC steady state
operation may not be reached if tstart,PFC reaches tstart,max,PFC before the soꢀ start has ended, and the protection
is triggered.
Data Sheet
16
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Functional Description
3.2
Flyback Controller Features
The Flyback converter stage provides isolation and primary side control of the output current. Primary side
regulation of the output current eliminates secondary side control feedback loop circuitry usually needed in
isolated power converters. This feature reduces part count to reduce costs.
The Flyback stage features multi-mode operation (QRM, DCM and ABM) which ensures efficiency and
performance is optimized.
3.2.1
Primary Side Regulation
The XDPL8221 FB stage provides primary side control of output current and output voltage. No external
feedback components are necessary for the current control.
Figure 15 shows typical current and voltage waveforms of the FB application operating in QRM1.
In DCM, the MOSFET will not turn on at the first valley of the resonant oscillation seen at VAUX, but instead
delayed.
Primary side regulation of the average output current is accomplished by sensing the primary peak current Ip,pk
,
the period of conduction of the output diode tdemag and the switching period tsw,FB
.
The voltage signal VAUX of the auxiliary winding of the transformer contains information on the reflected output
voltage Vout. The reflected output voltage is measured at the ZCD pin using a resistor divider.
VAUX
Reflected output voltage sampling
Zero crossing detection
0 V
Bus voltage sampling
Valley switching
Ip
Is
time
Vbus
Vout
tCS,sample
tZCD,sample
Np Ns
Na
Itransformer
tsw,FB
Ip,pk
Ip
VAUX
Ip
Is
time
tdemag
VGD
time
Figure 15
Typical Waveforms of a Flyback Converter
Data Sheet
17
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Functional Description
3.2.1.1
Primary Side Current Sensing
The primary side peak current Ip,pk is controlled by the control loop using the VCS,OCP1 level at the CSFB pin. This
control scheme ensures suppression of any variation in the bus voltage.
Several delays exist from the time at which the OCP1 level VCS,OCP1 is exceeded at the CSFB pin until the gate
switches off and the transformer current finally reaches its peak value. For a higher accuracy, the primary peak
current VCS,SH is sampled a fixed time before turn-off of the gate. The primary side peak current is used to
calculate the secondary side current and for protection. The propagation delay compensation parameter tPDC
allows optimization of the accuracy of the primary side peak current:
V
t
+ t
CS, SH
on, FB PDC
− t
Ip, pk
=
⋅
t
CS, FB on, FB CSFB, offset
R
Equation 2
Note:
If an RC low pass filter is added in front of the CSFB pin, the related low pass filter delay has to be
included in tPDC
.
Ip
VCS,pk
RCS,FB
Ip,pk
=
VCS,SH
RCS,FB
t
t
tPDC
VGD
tCSFB,offset
ton,FB
Figure 16
Propagation Delay Compensation for accurate Primary Peak Current Calculation
3.2.1.2
Primary Side Output Voltage Sensing
The output voltage is determined by measuring the reflected output voltage on the auxiliary winding. A resistor
divider adapts the voltage to the operating range of the ZCD pin.
The output voltage is measured at the ZCD pin using the voltage VZCD,SH at the end of the demagnetization time
at the time tZCD,sample. The voltage measured at the ZCD pin, the dimensioning of the resistor dividers RZCD,FB,1
and RZCD,FB,2, transformer turns Ns and Na as well as an offset Vout,offset (caused by the secondary diode, for
example) are used to calculate the output voltage Vout as follows:
R
+ R
N
N
ZCD, FB, 1 ZCD, FB, 2
s
Vout = VZCD, SH
+ Vout, offset
R
ZCD, FB, 2
a
Equation 3
Vout is used for Primary Side Regulated (PSR) control loops in CV and LP modes as well as for output over- and
undervoltage protections.
Data Sheet
18
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Functional Description
Vout,offset
Na Ns
RZCD,FB,1
VOut
ZCD
VZCD,SH
RZCD,FB,2
Figure 17
Primary Side Output Voltage Sensing using ZCD S&H
Note:
Any relation between VCC and ZCD in self-supplied applications can be decoupled – e.g. by adding a
linear regulator for VCC.
Attention: Please note that the time (tdemag) has to be longer than 2.0 μs to ensure that the reflected output
voltage can be sensed correctly at the ZCD pin.
3.2.1.3
Output Current Calculation
The output current is calculated based on the primary side peak current and the timing of the switching cycle.
The output current Iout is calculated using the duration of conduction of the output diode tdemag, the switching
period tsw,FB as well as the number of transformer turns Np, Ns and the transformer coupling Kcoupling. The
following equation is valid in QRM1 and DCM:
N
t
p
demag
Iout
=
21 Ip, pk
⋅
⋅ Kcoupling ⋅
N t
s sw, FB
Equation 4
In ABM the average output current depends on the number of pulses NABM,PI and the burst period tburst,FB
:
N
t
⋅ N
demag ABM, PI
p
Iout
=
21 Ip, pk
⋅
⋅ Kcoupling ⋅
N
s
t
burst, FB
Equation 5
The coupling of the transformer can be approximated using the transformer primary inductance Lp and the
transformer primary leakage inductance Lp,lk as follows:
L
p
Kcoupling
≈
L
+ L
p
p, lk
Equation 6
The calculated current Iout is used for the control loop in the modes CC and LP. The calculated current is also
used for output overcurrent protection.
3.2.1.4
Output control scheme
The XDPL8221 includes three different control schemes for a CC, CV or LP output.
Different use cases require the controller to operate according to different operation schemes:
•
In the case of typical LED strings, the forward voltage of the LED string determines the output voltage of the
driver. XDPL8221 operates in CC and drives a constant output current Iout,full to the load. The forward
voltage of the connected LED string has to be below a configurable maximum value Vout,set
.
Data Sheet
19
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Functional Description
•
•
In the case of LED loads including a power stage (e.g. Infineon BCR linear regulators or Infineon DC/DC buck
ILD2111), XDPL8221 operates in CV, ensuring a constant voltage Vout,set to the load. The total output current
drawn by the load has to be below a configurable maximum value Iout,full
.
In the case of a high output current setpoint Iout,full and an overly long LED string which exceeds the
configurable power limit Pout,set, XDPL8221 operates in LP to ensure that the power limit of the driver is not
exceeded. The controller reduces the output current automatically, ensuring light output without any
interruption even for overly long LED strings. The forward voltage of the connected LED string has to be
below a configurable maximum value Vout,set
.
For every update of the control loop, the control scheme is selected on the basis of the current operation
conditions (output voltage Vout and output current Iout) and their distance to the three limiting setpoints
(Vout,set, Pout,set and Iout,full):
•
For CC schemes, the internal reference current Iout,full is weighted according to thermal management and a
dimming curve to yield Iout,set. The calculated output current Iout is compared with the weighted reference
current Iout,set to generate an error signal for the output current.
•
•
For CV schemes, the sensed output voltage Vout at the ZCD pin is compared to a reference voltage Vout,set to
generate an error signal for the output voltage.
For LP schemes, the output current is limited to a maximum of Iout,set = Pout,set / Vout
.
Out of these three schemes, for each step the most critical error is selected (see Figure 18):
1.
If any setpoint is exceeded, the largest error for power decrease is selected to bring the controller back to
the desired operating point as quickly as possible.
2.
If the current operating conditions are below all three setpoints, the smallest error for power increase is
selected to avoid overshooting any setpoint.
The selected error signal is fed into a compensator to control the gate driver switching parameters (i.e. duty
cycle and frequency) for the power MOSFET of the FB.
Output
voltage
Output
open
Pout,set
Vout,OV
Vout,set
Pout,OPP
Constant voltage
Limited
power
Constant
current
Output
short
Vout,start
Vout,UV
Output current
Iout,min
Iout,full Iout,OCP
Figure 18
Control scheme for CC/CV/LP modes (non-dimmed)
In dimming cases, the output current setpoint Iout,set is located between Iout,min and Iout,full and varies according
to the sensed PWM duty cycle DDIM. Dimming can be visualized by moving the vertical line for the output current
setpoint in Figure 19 from right to leꢀ.
Note:
In the limited power mode, the maximum output current is limited to Iout,set = Pout,set / Vout. which is
smaller than Iout,full. It can be selected through parameter, whether Iout,set or Iout,full should be mapped
to 100% dimming level. If the Iout,full is mapped to 100% dimming level in the limited power mode, the
dimmer will experience the dead-travel between Iout,set and Iout,full (no current change while the
dimming level is changing).
Data Sheet
20
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Functional Description
Output
voltage
Output
open
Legend:
Pout,set
Operating range
Vout,OV
Constant voltage
Vout,set
Limited
power
Dimming
Constant
current
Output
short
Vout,start
Vout,UV
Dim-to-Off
Iout,min
Output current
Iout,full
Figure 19
Control scheme for CC/CV/LP modes (including dimming)
One or more of the output control schemes can be deactivated by configuration of the setpoints. Some
examples are given below:
•
The LP scheme is not active for Pout,set > Vout,set * Iout,full. For such a configuration, the controller will only
select between a CC and CV scheme.
•
•
The CV scheme is not active for Vout,set = Vout,OV as the output overvoltage protection will be triggered.
The CC scheme is not active for Iout,full = Iout,OC as the output overcurrent protection will be triggered.
Compensation of output losses
In case any output of flyback windings is not only supplying a current to LEDs, but also supplying other
consumers (e.g. bleeders, CDM10VD, etc.), the primary side regulation of the output current will not be
accurate. Parameter Gloss allows to compensate ohmic losses on the secondary side:
Iout,corrected = Iout,uncorrected + Gloss * Vout
Output current slew rate limitation
As the transient response of the PFC stage is rather slow (especially if the PFC is in low power mode), a fast
increase of the flyback power can cause a significant undershoot of the bus voltage. To limit this undershoot,
the rising slew rate of the flyback output current can be limited using parameter Iout,slew,rate,step as shown in
Figure 20.
Data Sheet
21
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Functional Description
Voltage or
current
Vbus,set
Vbus
Iout,corrected
Iout,set
Iout,slew,rate,step / 160 µs
Time
Figure 20
Output slew rate limitation
3.2.1.5
Multimode Scheme
The control loop of XDPL8221 uses three different switching modes: QRM1 is optimized for high efficiency at
high loads, DCM is used for medium loads and ABM is used for very light load conditions.
Power
VCS,max,FB
Peak-current controlled
QRM1
VCS,min,FB
tsw,min,FB
Pmax
Frequency controlled
tsw,max,FB
DCM
ABM
Pulse number controlled
NABM,min
Pmin
Bus Voltage
Vbus,UV
Vbus,OVP1
Figure 21
Flyback Multimode Operation Scheme
•
QRM1: This mode maximizes the efficiency by switching on the 1st valley of the VAUX signal. This ensures
zero current switching with a minimum of switching losses. The power is controlled by regulating the
primary peak current using VCS,OCP1
:
2
V
1
2
CS, OCP1
1
N V
Pout
=
⋅ Lp ⋅
⋅
L
p
R
⋅ V
t
CS, FB
CS, OCP1
s
bus
out
OSC, FB
2
1 +
+
R
N
V
p
CS, FB ⋅ V
bus
Equation 7
Data Sheet
22
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Functional Description
•
DCM: This mode is used if VCS,OCP1has reached its minimum value VCS,min,FB. To allow lower output power,
the controller extends the switching period tsw,FB later than the 1st valley:
2
V
1
2
CS, min, FB
1
Pout
=
⋅ Lp ⋅
⋅
R
t
CS, FB
sw, FB
Equation 8
•
ABM: This mode is used if VCS,OCP1 cannot be reduced and tsw,FB cannot be increased anymore. To reduce
power transfer, the controller will stop switching for some time, causing bursts of pulses:
2
V
N
1
2
CS, min, FB
ABM, PI
Pout
=
⋅ Lp ⋅
⋅
t
burst, FB
R
CS, FB
Equation 9
The frequency of the bursts is defined by 1/tburst,FB. The pulses of each burst have a peak current of
VCS,min,FB and a switching frequency of 1/tsw,max,FB. The number of pulses NABM,PI is regulated to control the
average power transfer during one burst period tburst,FB
.
The minimum power in DCM is limited by the transformer primary inductance Lp, maximum switching period
tsw,max,FB, minimum primary peak voltage VCS,min,FB, maximum bus voltage Vbus,OVP1 and two timing parameters:
2
2
V
V
L
1
2
bus, OVP1
CS, min, FB
p
1
Pmin
=
+ tOCP1, FB + tPDC
L
R
V
t
p
CS, FB
bus, OVP1
sw, max, FB
Equation 10
The minimum power in ABM is limited by the transformer primary inductance Lp, burst period tburst,FB
,
minimum number of pulses NABM,min, minimum primary peak voltage VCS,min,FB, maximum bus voltage Vbus,OVP1
and two timing parameters:
2
2
V
V
L
N
t
1
2
bus, OVP1
CS, min, FB
p
ABM, min
Pmin
=
+ tOCP1, FB + tPDC
L
R
V
p
CS, FB
bus, OVP1
burst, FB
Equation 11
Note:
If the load drops below the minimum load of Pmin, the output voltage will rise up to the output
overvoltage threshold Vout,OV and trigger the protection. An auto-restart can be used to keep the
output voltage close to Vout,OV until the load increases again.
3.2.1.6
Active Burst Mode
The sense and control scheme for the active burst mode of the FB is described.
The typical waveform for the gate drivers, the secondary side flyback transformer current, the output voltage
and the bus voltage are shown in the figure. The bursts are repeated with a configurable burst period tburst,FB. It
is advised to choose a burst frequency faster than 200 Hz to ensure a sufficient light quality and reduce output
ripple. On the other hand, the burst frequency should not be too high as the human ear is more sensitive to
higher frequencies.
Data Sheet
23
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Functional Description
GDFB
Vout
Isec
Burst
Burst Pause
tburst,FB
Figure 22
Example Waveforms in Active Burst Mode (not drawn to scale)
The FB switching pulses of each burst will boost the output voltage to a higher level. During the burst pause, the
output voltage drops due to the load of the power converter.
To control the average output current or the average output voltage, the FB controller calculates the average
secondary current and measures the output voltage once at the beginning and once at the end of each burst.
These measurements are used to calculate the average output current and average output voltage for the
complete burst. Based on these average values, the control loop updates the number of pulses per burst.
3.2.2
Flyback Startup
Aꢀer startup, the FB of the XDPL8221 initiates a soꢀ start to minimize the switching stress for the power
MOSFET and secondary diode.
The controller switches with a configurable switching frequency of fsw,start,FB and increases the cycle-by-cycle
current limit in steps of VCS,step with a configurable duration tsoꢀstart for each step. Aꢀer the final VCS,OCP1,start
limit level has been reached, the output will be charged until the minimum output voltage Vout,start, which
ensures self-supply has been reached. At this condition, Continuous Conduction Mode (CCM) protection as well
as output undervoltage protection are activated and the control loop takes over. The starting point for the
control loop is to operate in ABM at lowest number of pulses, lowest switching frequency and lowest primary
peak-current. These switching parameters avoid an overshoot of output current for a LED string with low
forward voltage when dimmed down to a low output current.
Output voltage
Peak current
Soft Start
Control loop
active
Vout
Vout,start
VCS,OCP1
VCS,OCP1,start
VCS,step
time
tsoftstart
Figure 23
Flyback Startup Sequence
Data Sheet
24
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Functional Description
3.2.3
Protection features
Protections ensure the operation of the controller under restricted conditions. The protection monitoring
signal(s) sampling rate, protection triggering condition(s) and protection reaction are described in this section.
Attention: The sampled protection monitoring signal accuracy is subjective to the digital quantization,
tolerances of components (including Integrated Circuit (IC)) and estimations with indirect
sensing (e.g. input and output voltage estimations based on ZCD, CS pin signals), while the
protection level triggering accuracy is subjective to the sampled signal accuracy, sampling
delay, indirect sensing delay (e.g. reflected output voltage signal cannot be sensed by ZCD pin
near AC input phase angle of 0° and 180°) and blanking time.
3.2.3.1
Primary Over-current Protection
The primary side over-current protection implemented in hardware covers fault conditions like a short in the
transformer primary winding or an open CS pin.
The primary side current is compared to an over-current protection threshold VCS,OCP2. If the threshold is
exceeded for longer than the blanking time tOCP2,FB, the protection will be triggered.
3.2.3.2
Output Under-voltage Protection
In case of a short of the output or an overload, the output voltage may drop to a low level. Detection of under-
voltage in the output voltage Vout is enabled by measurement of the reflected voltage at the ZCD pin.
During operation, the output voltage is compared to a configurable under-voltage protection threshold Vout,UV
If the threshold is exceeded for longer than the blanking time tblank,out,UV, the protection will be triggered.
.
During startup,a shorted output or a strong capacitive loading may not allow the controller charging the output
voltage to Vout,UV,start within a timeout of tstart,max,FB. If this timeout expires the protection will be triggered. The
timeout starts when the controller starts switching.
Note:
The startup under-voltage threshold Vout,UV,start has to be configured sufficiently above the under-
voltage threshold Vout,UV to allow undershoots at start-up which may occur, especially for resistive
loads which already consume power from the beginning.
Attention: Output under-voltage protection is not available while the controller operates in ABM.
3.2.3.3
Output Over-voltage Protection
In case of a open output, the output voltage may rise to a high level. Over-voltage detection of the output
voltage Vout is provided by measurement at the ZCD pin.
The output voltage is compared to an over-voltage protection threshold Vout,OV. If the threshold is exceeded for
longer than the blanking time tblank,out,OV, the protection will be triggered.
Note:
The blanking time tblank,Vout,OV must be taken into account because overshoots of the output voltage
above the protection threshold can occur due to this time.
Note:
This protection is usually triggered if the output is open or the output load drops below the minimum
load Pmin
.
Attention: Output over-voltage protection is not available while the controller operates in ABM.
Data Sheet
25
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Functional Description
3.2.3.4
Output Over-current Protection
Over-current detection in the output current Iout is provided on the basis of the calculated output current.
The calculated output current is compared to a configurable over-current protection threshold Iout,OC. If the
threshold is exceeded for longer than the blanking time tblank,out,OC, the protection will be triggered.
3.2.3.5
Output Over-power Protection
Over-power detection in the output power Pout is provided on the basis of the calculated output power.
The calculated output power is compared to a configurable over-power protection threshold Pout,OP. If the
threshold is exceeded for longer than the blanking time tblank,out,OP, the protection will be triggered.
3.2.3.6
Other Flyback Protections
XDPL8221 includes additional protections to ensure the integrity and correct flow of the firmware.
•
•
•
•
•
A hardware weak pull-up protects against an open CSFB pin. The CSFB OCP2 will be triggered for an open
CSFB pin.
A firmware watchdog protects against the CSFB pin becoming shorted to GND. The protection triggers if the
sampled CSFB voltage is less than 97.6 mV for longer than the blanking time of tsoꢀstart
.
A firmware state monitor supervises correct operation of the flyback in QRM1, DCM or ABM. A protection is
triggered if the flyback enters CCM.
A firmware plausibility check ensures that both bus voltage measurements using the ZCD andVS pins are
consistent.
A firmware watchdog supervises correct data handling of the flyback.
3.2.3.6.1
Flyback Bus Voltage Sensing
The FB can sense the bus voltage using the reflection of bus voltage on the auxiliary winding while the gate is
turned on. A resistor divider adapts the negative voltage to the operating range of the ZCD pin. This second
measurement path is required to protect against component failures in the VS measurement path (open loop
protection for the PFC stage).
The reflected bus voltage appears as a negative voltage at VAUX. This negative voltage is internally clamped at
the ZCD pin to the negative voltage VINPCLN. The internal clamping current IZCD is measured at the end of the on-
time at the time tCS,sample. The measured clamping current of the ZCD pin, the dimensioning of the resistor
dividers RZCD,FB,1 and RZCD,FB,2 as well as the number of transformer turns Na and Np are used to calculate the
bus voltage Vbus,FB as follows:
V
N
N
INPCLN
p
a
Vbus, FB
=
IZCD
+
RZCD, FB, 1 + VINPCLN
R
ZCD, FB, 2
Equation 12
Vbus,FB is used for a plausibility check with the bus voltage Vbus as measured using the VS pin.
Na Np
RZCD,FB,1
Vbus,FB
IZCD
ZCD
VINPCLN
RZCD,FB,2
Figure 24
Bus Voltage Sensing using ZCD Clamp Current
Data Sheet
26
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Functional Description
3.3
General Controller Features
XDPL8221 provides general features using device level measurements (DLM) for firmware task scheduling, VCC
control and temperature control which are independent of the target application.
3.3.1
Configurable Gate Driver Strengths
The gate driver output signals can be configured with respect to their rising slopes for switching on the power
MOSFET and with respect to their high voltage levels.
This feature can save BOM components (1 diode & 1 resistor per gate driver) which are conventionally added to
achieve the same purpose to lower any Electro-Magnetic Interference (EMI).
3.3.2
External Temperature Sensing
The external temperature is measured by measuring the voltage of an NTC with respect to the internal VREF
voltage.
Controller
VREF
RPU
TEMP
VTEMP
RNTC
Figure 25
External Temperature Sensing using NTC
The controller calculates the resistance of the NTC based on the measured voltage VTemp, the internal reference
voltage VREF and the internal pull-up resistance RPU
:
V
⋅ R
Temp
− V
PU
Temp
RNTC
=
V
REF
Equation 13
3.3.3
Adaptive temperature protection
XDPL8221 offers adaptive temperature protection using the external temperature sensor. This feature reduces
the output current according to temperature to protect the load and/or driver against overtemperature.
As long as the resistance of the NTC is lower than the temperature threshold RNTC,hot of the NTC, the current is
gradually reduced from the maximum current Iout,set, as shown in Figure 26. If the resistance of the NTC is
higher than threshold RNTC,hot, the output current is gradually increased again. This allows the controller to
ensure operation at or below a temperature matching to RNTC,hot
.
If a reduction down to a minimum current Iout,red is not able to compensate for any continued increase in
temperature (causing a continuing reduction of NTC resistance), XDPL8221 will trigger external
overtemperature protection if the external sensor exceeds RNTC,critical
.
Data Sheet
27
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Functional Description
Temperature reduced
Temperature reduced
output current
output current
Iout,full
Iout,full
Iout,red
Iout,red
R≥ RNTC,hot
R<RNTC,hot
R=RNTC,hot R≥ RNTC,hot R=RNTC,hot
NTC
resistance
Time
RNTC,hot
RNTC,critical
Figure 26
Adaptive temperature protection for external sensors
3.3.4
PWM Dimming Interface
The duty cycle sensed at the PWM pin is used to determine the output current level. The XDPL8221 can be
configured to use either a linear or a quadratic dimming curve. Either normal or inverted dimming curves can
be selected.
Figure 27 shows the relationship of the PWM duty cycle to the output current target value. Configurable levels
DDIM,min and DDIM,max ensure that the minimum current Iout,min and maximum current Iout,set can always be
achieved, thereby making the application robust against component tolerances. The dimming curve can be
mirrored by changing its direction from normal to inverted PWM duty cycle.
An optional hysteresis can be enabled for the sensing of the PWM signal. This hysteresis can suppress jitter in
the PWM signal. Any change of the PWM duty cycle within the hysteresis will not affect the output current.
Output current
Iout,set
Output current
Iout,set
Constant
current
Constant
current
Limited
power
Limited
power
Iout,min
Iout,min
PWM duty cycle
PWM duty cycle
DDIM,off
DDIM,min
DDIM,max
DDIM,off
DDIM,min
DDIM,max
DDIM,on
DDIM,on
Figure 27
Selectable Dimming Curves
Using the optional Dim-to-Off feature, the light output can be stopped without removal of input voltage. In Dim-
to-Off, the controller will enter auto-restart operation to minimize power consumption. The auto-restart
recharges the output voltage to a minimum output voltage of Vout,start to measure the PWM duty cycle during a
time of tblank,DIM,off. Aꢀer tblank,DIM,off, the controller decides if it stays in Dim-to-off by triggering an auto-restart
or if it starts the control loop. With the Dim-to-Off feature, the output voltage can be maintained in a specific
range by configuration of the startup voltage Vout,start and auto-restart time tAR, and by dimensioning of an
active or passive output bleeder. If Vout,start is configured to be low enough below the minimum forward voltage
of the LED string, the LEDs will show no light in this state.
Note:
A sufficient output bleeder is required to allow the controller to maintain the output voltage if the
Dim-to-Off feature is enabled.
Dim-to-Off is entered if the PWM duty cycle exceeds the configurable threshold DDIM,off (see purple line in Figure
27). As soon as the duty cycle exceeds DDIM,on, the controller will start to continuously regulate output voltage or
output current again.
Data Sheet
28
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Functional Description
In case the product of output current and output voltage would exceed the power limit, the controller will
automatically enter the LP mode by reducing the output current to achieve the configured power limit (see light
blue curve in Figure 27). As a consequence, the dimmer may show extended dead travel at the highest output
level. When dimming down, as soon as the product of dimmed output current and output voltage drops below
the power limit, the output current will follow the regular dimming curve (green curve).
3.3.5
UART Command Interface
The UART command interface allows to control the operation of the LED driver as well as reading out status
information from the controller. The electrical UART interface and the protocol are described.
XDPL8221 uses a common half-duplex UART interface with a baudrate of 57.600 baud. In half-duplex mode,
both communication partners share one line to exchange data with a wired-AND structure. Therefore, both data
transmit outputs (driver type: open-drain) are connected together to a common pull-up resistor to maximum
3.3 V. The value of the resistor define the rise time of the data signal at a 0-1 transition. The data receivers are
connected to the same line and are always active to detect data collision. Each device also reads the data it is
currently transmitting and checks the read data against the data that was intended to be written. In case of a
mismatch, a data collision has occurred.
The UART communication is based on data bytes with 8 bit width, LSB first as shown in Figure 28. Each data
transfer starts with a start bit at low level and stops with two stop bits at high level (STOP). The idle level of the
transmit and receive signals is the high level.
Start
D0
D1
D2
D3
D4
D5
D6
D7
Stop
Figure 28
UART Byte Frame
Before a command is send, sending one or multiple SYNC commands (0x7F) is recommended. If a UART sync
request occurs during a power saving state, the XDPL8221 will first recharge it's VCC voltage before responding
with an ACK (0x00). Aꢀer the XDPL8221 answered one or more sync requests with ACK, the external master can
send subsequent GET or SET commands. The UART communication has to finish within a configurable timeout,
otherwise a VCC undervoltage can occur.
In case UART communication is requested while the XDPL8221 is in power-saving state, a SYNC command will
trigger a wakeup. In preparation of the communication, the XDPL8221 will first charge up the VCC. This ensures
a wakeup with full VCC to be ready for communication. The XDPL8221 will be available for communication for a
timeout of tUART which can be adjusted based on the VCC capacitance. Aꢀer the timeout, the XDPL8221 will
continue with the protection reaction which was interrupted by the communication.
Note:
The UART line is pulled low for typically 500 µs during an auto-restart of the XDPL8221. This must not
be misinterpret as UART frame error by other UART devices.
A GET or SET command frame consists of 9 bytes as listed in Table 2. The time between each byte must not
exceed tUART,intra-byte. The checksum at the end of the command ensures that XDPL8221 does not react to any
disturbed communication. The checksum is the XOR combination of the previous bytes of the command.
Table 2
UART Commands
Command
Class Comm ARG0 ARG1 ARG2 ARG3 ARG4 ARG5 Check
and
sum
SYNC
0x7F
-
-
-
-
-
-
-
-
GET status
0x7C
0x7C
0x7C
0x04
0x04
0x04
0x41
0x44
0x45
ID
ID
ID
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xXX
0xXX
0xXX
GET internal temperature
GET external NTC resistance
Data Sheet
29
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Functional Description
Table 2
UART Commands (continued)
Command
Class Comm ARG0 ARG1 ARG2 ARG3 ARG4 ARG5 Check
and
sum
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0x7C
0x7D
0xB7
GET output voltage
GET RMS input voltage
GET bus voltage
GET output current
SET non-dimmed current
GET non-dimmed current
SET dimming level
GET dimming level
START
0x7C
0x7C
0x7C
0x7C
0x7C
0x7C
0x7C
0x7C
0x7C
0x7C
0x7C
0x04
0x04
0x04
0x04
0x84
0x04
0x84
0x04
0x00
0x01
0x84
0x64
0x65
0x66
0x6A
0x68
0x68
0x84
0x84
0x00
0x00
0x4F
ID
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
ID
0x00
ID
0x00
ID
0x00
ID
Current
0x00
ID
0x00
ID
Dimming Level 0x00
ID
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
STOP1)
SET sleep2)
Restrictions apply to the non-dimmed current which can be set via UART SET command:
•
•
•
Iout,min < current set via UART < Iout,full
This is the normal operation range. The current will be regulated according to the UART command.
Current set via UART > Iout,full
This case would overload the design. The controller will limit the output current to Iout,full
Current set via UART < Iout,min
:
:
.
:
This configuration is not allowed as it causes an invalid dimming curve. The UART master must not program
a current in this range.
A response frame can consist of either 1 byte or 9 bytes. As the power stage is a noisy environment, the UART
communication may occasionally be disturbed. In case of a mismatching checksum of the request or an
incomplete frame, XDPL8221 will not provide any response. If a response to a command is missing, the UART
master must not send any new request within tUART,error
.
Table 3
UART responses to commands
Response
ACK/ ARG0 ARG1 ARG2 ARG3 ARG4 ARG5 ARG6 Check
NACK
sum
Successful answer to SYNC or SET 0x00
-
-
-
-
-
-
-
-
command
(ACK)
Successful response to a GET
command
0x00
Value (see
00
-
00
-
00
-
00
-
00
-
0xXX
-
(ACK) coding below)
Generic Error Code for general
protocol purposes or used as a
non-contextualized generic NACK
0x01
-
-
One of the arguments in the
given command is not valid
0x02
0x03
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
The command is not known
1
This command requires external VCC supply. Without external VCC supply, a VCC undervoltage protection
will occur.
To wakeup from sleep by UART, the "UART during Latch" feature needs to be enabled.
2
Data Sheet
30
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Functional Description
The ID field allows to address one out of multiple XDPL8221s on a shared UART bus. Only devices with a
matching ID will react to a UART command. Commands can use the broadcast ID 0x00 to address any XDPL8221
on a shared bus. A broadcast GET command will cause a collision on the shared bus in case multiple devices are
connected. It is advised to use only GET commands with a device ID to ensure a response from a single, unique
device.
Note:
All IDs of any XDPL8221s on a shared UART bus must be unique!
The coding of the electrical values to their digital number representation is listed in Table 4. For all 16 bit values
the lower byte is transferred first.
Table 4
Value
Number Representation of Values
Conversion Factor
Offset
Minimum decimal
value
Maximum decimal
value
Current
4096 LSB / A
81.92 LSB / %
16 LSB / V
0
1 (≡ 244 µA)
0 (≡ 0 %3))
1 (≡ 62.5 mV)
0 (≡ 0 Ω)
40960 (≡ 10 A)
8192 (≡ 100%)
8000 (≡ 500 V)
32768 (≡ 32.768 kΩ)
190 (≡ 150°C)
Dimming Level
Voltage
0
0
NTC resistance
Temperature
1 LSB / Ω
0
1 LSB / °C
40
0 (≡ -40°C)
The status value of the controller answered to a "GET status" command is coded as listed in Table 5.
Table 5
Coding of Status
Bit
Description
15 to 14
The output current is determined by:
•
•
•
00: Dimming
01: Advanced temperature protection
10: Limited power
13
The flyback regulates in
•
•
0: CC or Limited Power mode
1: CV mode
12
The dimming level is determined by:
•
•
0: PWM
1: UART
11
AC or DC input voltage:
•
•
0: AC input voltage
1: DC input voltage
10 to 9
Current protection reaction is
•
•
•
•
00: Auto-restart
01: Fast Auto-restart
10: Latch
11: Stop Mode
8
7
The on-going protection requires a VCC charging for the restart (1) or not (0)
A protection reaction is on-going (1) or not (0)
3
A UART dimming level of 0% triggers dim-to-off if it is enabled.
Data Sheet
31
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Functional Description
Table 5
Coding of Status (continued)
Bit
Description
6
A DLM protection was triggered (ProtectionDLM > 0)
A FB protection was triggered (ProtectionFB > 0)
A PFC protection was triggered (ProtectionPFC > 0)
Bit number of any bit set in either ProtectionPFC, ProtectionFB or ProtectionDLM
5
4
4)
3 to 0
The coding of system protections indicated by the value of the lowest 7 bits (bit 0-6) in the Table 5 is given in the
following table :
Table 6
Coding of System Protections
Value (bit 6-0)
000 0000
001 0001
001 0010
001 0011
001 0100
001 0101
001 0110
001 0111
010 0000
010 0001
010 0010
010 0011
010 0100
010 0101
010 0110
010 0111
010 1000
010 1001
010 1010
010 1011
010 1100
100 0000
100 0001
100 0010
100 0011
100 0100
System Protections
No Protection
Bus Over-voltage Protection Level 2
Input Under-voltage Protection
Input Over-voltage Protection
PFC CCM Protection
PFC Soꢀ-start Failure Protection
Bus Under-voltage Protection
PFC Over-current Protection Level 2
Flyback CS Pin Short to GND Protection
Flyback Output Under-voltage Protection at Start-up
Flyback Output Under-voltage Protection during Operation
Flyback Output Over-voltage Protection
Flyback Output Over-current Protection
Flyback Over-current Protection Level 2
Flyback CCM Protection
Flyback Maximum TOSC Exceeding Protection
Dim-to-off at Start-up
Dim-to-off during Operation
Flyback Output Over-power Protection
Flyback Vbus Plausibility Check Failure Protection
Flyback Data Missing Protection
External Over-Temperature Protection
Internal Over-Temperature Protection
Task scheduler protection
VCC Under-voltage Lock Out Protection
VCC Out of Range Protection
4
This assumes only one bit will be set in all three signals at a time. If multiple bits would be present, only
the first error found will be chosen.
Data Sheet
32
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Functional Description
Table 6
Coding of System Protections (continued)
Value (bit 6-0)
100 0101
System Protections
RAM Parity Error Protection
Watch Dog Error Protection
Clock Check Error Protection
100 0110
100 0111
3.3.6
Protection features
Protections ensure the operation of the controller under restricted conditions. The protection monitoring
signal(s) sampling rate, protection triggering condition(s) and protection reaction are described in this section.
Attention: The sampled protection monitoring signal accuracy is subjective to the digital quantization,
tolerances of components (including IC) and estimations with indirect sensing (e.g. input and
output voltage estimations based on ZCD, CS pin signals), while the protection level triggering
accuracy is subjective to the sampled signal accuracy, sampling delay, indirect sensing delay
(e.g. reflected output voltage signal cannot be sensed by ZCD pin near AC input phase angle of 0°
and 180°) and blanking time.
3.3.6.1
Overtemperature Protection
Overtemperature protection initiates a shutdown once the critical temperature level Tcritical or the critical NTC
resistance RNTC,critical is exceeded.
If the internal temperature sensor exceeds Tcritical or the external resistance drops below RNTC,critical, XDPL8221
will trigger internal or external overtemperature protection.
Output current
Iout,full
Temperature
Tstart
Tcritical
Figure 29
If the controller is configured to react with auto-restart to internal or external overtemperature protection, it will
only restart aꢀer the temperature drops below Tstart and the NTC resistance exceeds RNTC,hot
If latch mode is selected instead, the IC will turn off and only restart aꢀer recycling of input power with a
temperature below Tcritical
Temperature protection
.
.
Note:
Please note that the internal temperature sensor can only protect external components which have
sufficient thermal coupling to XDPL8221. The external temperature sensor can be used to protect the
temperature of external components (e.g. transformer, power MOSFETs or linear regulators).
3.3.6.2
VCC Undervoltage Lockout
A Undervoltage Lockout (UVLO) is implemented in hardware. It ensures defined enabling and disabling of the
IC operation depending on the supply voltage VVCC at the VCC pin in accordance with defined thresholds.
The UVLO contains a hysteresis with the voltage thresholds VVCCon for enabling the controller and VUVoff for
disabling the controller. Once the mains input voltage is applied, current flows through an external resistor into
the HV pin via the integrated depletion cell and diode to the VCC pin. The controller is enabled once VVCC
Data Sheet
33
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Functional Description
exceeds the threshold VVCCon and enters normal operation if no fault condition is detected. In this phase, VVCC
will drop until either external supply or the self-supply via the auxiliary winding takes over the supply at the VCC
pin.
Note:
The self-supply via the auxiliary winding must be in place before VVCC falls below the VUVoff threshold.
Otherwise, the system will perform a fast restart.
Note:
It is possible to supply VCC externally from an auxiliary power supply. In this case, the VCC also needs
initially to ramp to VVCCon to enable the IC.
3.3.6.3
VCC Overvoltage Protection
Overvoltage protection ensures that the voltage at the VCC pin is not exceeded.
The VCC voltage is compared to a configurable overvoltage protection threshold VVCC,OV. If the threshold is
exceeded for longer than the blanking time tblank,VCC, the protection will be triggered.
Note:
The reaction to this protection is fixed to stop mode to ensure a discharge of VCC.
3.3.6.4
VCC Undervoltage Protection
The VCC voltage is compared to a configurable undervoltage protection threshold VVCC,UV. If the threshold is
exceeded for longer than the blanking time tblank,VCC, the protection will be triggered.
3.3.6.5
Other General Controller Protections
XDPL8221 includes several protections to ensure the integrity and correct flow of the firmware.
•
A hardware watchdog checks correct execution of firmware. A protection is triggered in the event that the
firmware does not service the watchdog within a defined period.
•
A hardware Random Access Memory (RAM) parity check triggers a protection if a bit in the memory changes
unintentionally.
•
•
A hardware clock check watchdog checks that no clock oscillator is failing.
A firmware Cyclic Redundancy Check (CRC) at each startup verifies the integrity of firmware code and its
parameters.
•
A firmware task execution watchdog triggers a protection if the firmware tasks are not executed as
expected.
3.3.7
Protection Reactions
The reaction to each protection can be separately selected. Available reactions may include auto restart, fast
auto restart, latch or stop mode.
Figure 30 depicts the timing of an auto-restart reaction:
1.
If a protection threshold is exceeded for longer than the related blanking time tblank, the protection is
triggered.
2.
3.
4.
Within a maximum t1 = 4 * 40 µs, the gate driver of the power stage related to the protection is disabled.
Within a maximum t2 = 4 * 40 µs, the gate drivers of other stages are disabled.
The reaction depends on the configuration of the protection:
•
•
•
In case of latch mode, the application will enter latch mode at this time. No further steps are done,
the reaction ends here.
In case of stop mode, the application will stop and enter UART parametrization mode which allows
to read out the error code. No further steps are done, the reaction ends here.
In case of a (fast) auto-restart reaction, the controller will enter a power saving mode for the auto-
restart time tAR or tAR,fast respectively.
Data Sheet
34
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Functional Description
5.
The auto restart may include a new VCC charging cycle. The time t3 typically depends on the input
voltage.
6.
7.
The first power stage will enable its gate driver according to its startup sequence (soꢀ start) again.
The second power stage will enable its gate driver according to its startup sequence (soꢀ start) again. The
startup of a subsequent power stage may be delayed by a time t4 depending on any startup condition for
the subsequent stage.
Threshold is exceeded
Protection is triggered
Related gate driver is disabled
Other gate drivers are disabled
Startup, charging of VCC
Restart of the first stage
Restart of the second stage
Value
Threshold
Other gate driver
Related gate driver
Time
tblank t1 t2
tAR
t3
t4
Figure 30
Protection Reaction for auto-restart
For some failures the system may eventually not be able to recover. These failures include:
•
•
•
•
•
•
•
•
•
•
•
•
•
PFC OVP2
PFC OCP2
Bus voltage plausibility check
Flyback CSFB short to GND
Flyback OCP2
Flyback oscillation period too long
Flyback CCM protection
Flyback output overcurrent protection
RAM parity
Watchdog
Clock check protection
VCC out-of-range protection
Task Execution protection
For these cases, the controller features a limitation of auto-restarts. The controller will only restart a limited
number of times NAR,max. Aꢀerward, the controller will latch. The counter for the limited number of restarts is
reset whenever a restart due to a protection without limitation occurs.
Data Sheet
35
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Functional Description
3.3.7.1
Auto restart
When auto restart mode is activated, XDPL8221 stops switching at the GD pins. Aꢀer a configurable auto restart
time tAR, XDPL8221 initiates a new startup including recharging of VCC and a soꢀ start.
During the time in which the gate is not switching, the internal HV startup cell is automatically enabled and
disabled to keep the VCC voltage between the VUVLO and VOVLO thresholds for the supply of XDPL8221. Due to the
recharging of VCC for a restart, the time between stopping and starting gate driver pulses is longer than tAR
.
3.3.7.2
Fast Auto Restart
When fast auto restart mode is activated, XDPL8221 stops switching at the GD pins. Aꢀer a configurable fast auto
restart time tAR,fast, XDPL8221 initiates a new startup including recharging of VCC and a soꢀ start.
During the time in which the gate is not switching, the internal HV startup cell is automatically enabled and
disabled to keep the VCC voltage between the VUVLO and VOVLO thresholds for the supply of XDPL8221. Due to the
recharging of VCC for a restart, the time between stopping and starting gate driver pulses is longer than tAR,fast
.
3.3.7.3
Latch Mode
When latch mode is activated, XDPL8221 stops switching at the GD pins. The device stays in this state until input
voltage is completely removed and the VCC voltage drops below the VUVLO threshold. Only then can XDPL8221
be restarted by applying input voltage.
To maintain this state, the internal HV startup cell is automatically enabled and disabled to keep the VCC
voltage between the VUVLO and VOVLO thresholds for the supply of XDPL8221. The current consumption is
reduced to a minimum.
3.3.7.4
Stop Mode
When stop mode is activated, XDPL8221 stops switching at the GD pins. XDPL8221 enters UART communication
mode to allow debugging of the system state.
Note:
The VCC for XDPL8221 needs to be supplied by an external source. Without an external supply, VCC will
drain to VUVLO and XDPL8221 performs a restart.
Data Sheet
36
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Electrical Characteristics and Parameters
4
Electrical Characteristics and Parameters
All signals are measured with respect to the ground pin, GND. The voltage levels are valid provided other ratings
are not violated.
4.1
Package Characteristics
Table 7
Package Characteristics
Parameter
Symbol
Limit Values
Unit Remarks
min
max
Thermal resistance for PG-
DSO-16
RthJA
—
119
K/W
4.2
Absolute Maximum Ratings
Attention: Stresses above the values listed below may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Maximum ratings are absolute ratings; exceeding only one of these values may cause
irreversible damage to the integrated circuit. These values are not tested during production test.
Table 8
Absolute Maximum Ratings
Symbol Limit Values
Parameter
Unit Remarks
min
max
Voltage externally supplied VVCCEXT
to pin VCC
–0.5
26
V
voltage that can be applied
to pin VCC by an external
voltage source
Voltage at pin GDx
VGDx
TJ
–0.5
–40
VVCC + 0.3
125
V
if gate driver is not
configured for digital I/O
Junction temperature
°C
max. operating frequency
66 MHz fMCLK
Storage temperature
Soldering temperature
Latch-up capability
TS
–55
—
150
260
150
°C
TSOLD
ILU
°C
Wave Soldering 5)
6) Pin voltages acc. to abs.
max. ratings
—
mA
7)
8)
ESD capability HBM
ESD capability CDM
Input Voltage Limit
VHBM
VCDM
VIN
—
2000
500
3.6
V
V
V
—
–0.5
Voltage externally supplied
to pins GPIO, MFIO, CS, ZCD,
GPIO, VS, GDx (if GDx is
configured as digital I/O). (If
not stated different)
5
According to JESD22-A111 Rev A.
6
7
8
Latch-up capability according to JEDEC JESD78D, TA= 85°C.
ESD-HBM according to ANSI/ESDA/JEDEC JS-001-2012.
ESD-CDM according to JESD22-C101F.
Data Sheet
37
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Electrical Characteristics and Parameters
Table 8
Absolute Maximum Ratings (continued)
Parameter
Symbol
Limit Values
Unit Remarks
min
max
Maximum permanent
negative clamping current
for ZCD and CS
–ICLN_DC
—
2.5
mA
mA
RMS
Maximum transient negative –ICLN_TR
clamping current for ZCD
and CS
—
10
pulse < 500ns
Maximum negative transient –VIN_ZCD
input voltage for ZCD
—
—
—
1.5
3.0
2.5
V
pulse < 500ns
pulse < 500ns
RMS
Maximum negative transient –VIN_CS
input voltage for CS
V
Maximum permanent
positive clamping current for
CS
ICLP_DC
mA
Maximum transient positive ICLP_TR
clamping current for CS
—
—
—
10
mA
mA
µA
pulse < 500ns
Maximum current into pin
VIN
IAC
10
for charging operation
Maximum sum of input
clamping high currents for
digital input stages of device
ICLH_sum
300
limits for each individual
digital input stage have to
be respected
Voltage at HV pin
VHV
-0.5
600
V
4.3
Operating Conditions
The recommended operating conditions are shown for which the DC Electrical Characteristics are valid.
Table 9
Operating Range
Symbol
Parameter
Limit Values
min
Unit Remarks
max
125
—
Junction Temperature
Lower VCC limit
TJ
–40
°C
V
max. 66 MHz fMCLK
VVCC
VUVOFF
device is held in reset when
VVCC < VUVOFF
Voltage externally supplied VVCCEXT
to VCC pin
—
24
V
V
maximum voltage that can
be applied to pin VCC by an
external voltage source
Gate driver pin voltage
VGD
–0.5
VVCC + 0.3
4.4
DC Electrical Characteristics
The electrical characteristics provide the spread of values applicable within the specified supply voltage and
junction temperature range, TJ from -40 °C to +125 °C.
Devices are tested in production at TA = 25 °C. Values have been verified either with simulation models or by
device characterization up to 125 °C.
Data Sheet
38
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Electrical Characteristics and Parameters
Typical values represent the median values related to TA = 25 °C. All voltages refer to GND, and the assumed
supply voltage is VVCC = 18 V if not otherwise specified.
Note:
Not all values given in the tables are tested during production testing. Values not tested are explicitly
marked.
Attention: The Vcc pin voltage must be higher than 3.4V before the voltage of any other pins (except GND
and HV pins) exceeds 1.2V.
Table 10
Power Supply Characteristics
Parameter
Symbol
Min.
Values
Typ.
Unit Note or Test Condition
Max.
VCC_ON threshold
VVCCon
—
VSELF
—
V
Self-powered startup
(default)
VCC_ON_SELF threshold VSELF
19
—
20.5
—
22
V
dVVCC/dt = 0.2 V/ms
VCC_ON_SELF delay
tSELF
2.1
µs
Reaction time of VVCC
monitor
VCC_UVOFF current
IVCCUVOFF
5
20
40
µA
VVCC < VSELF(min) - 0.3 V
or VVCC < VEXT(min) -
0.3 V9)
UVOFF threshold
VUVOFF
ΔUVOFF
—
—
6.0
—
—
V
SYS_CFG0.SELUVTHR = 0
0B
UVOFF threshold
tolerance
±5
%
This value defines the
tolerance of VUVOFF
UVOFF filter constant
tUVOFF
VUVLO
600
—
—
—
—
ns
V
1V overdrive
UVLO (UVWAKE)
threshold
VUVOFF
1.25
·
UVWAKE threshold
tolerance
ΔUVLO
tUVLO
VOVLO
tOVLO
VADCVCC
RADCVCC
—
0.6
—
0.6
0
—
±5
2.2
—
%
µs
V
This value defines the
tolerance of VUVLO
UVLO (UVWAKE) filter
constant
—
1 V overdrive
OVLO (OVWAKE)
threshold
VSELF
—
OVLO (OVWAKE) filter
constant
2.4
µs
V
1 V overdrive
10)
Nominal range 0% to
100%
—
VREF
92
VADCVCC = 0.09 · VVCC
11)12)
Reduced VCC range for
ADC measurement
8
—
%
9
Tested at VVCC = 5.5 V
Theoretical minimum value, real minimum value is related to VUVOFF threshold.
Operational values.
10
11
12
Note that the system is turned off if VVCC < VUFOFF
.
Data Sheet
39
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Electrical Characteristics and Parameters
Table 10
Power Supply Characteristics (continued)
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
Max.
Maximum error for ADC
measurement (8-bit
result)
TET0VCC
—
—
—
—
—
—
3.8
5.2
LSB8
Maximum error for ADC
measurement (8-bit
result)
TET256VCC
LSB8
Gate driver current
consumption excl. gate
charge current
IVCCGD
0.26
11
0.35
13
mA Tj ≤ 125°C
VCC quiescent current in IVCCPMD0
PMD0
mA All registers have reset
values, clock is active at
66 MHz, CPU is stopped,
Tj ≤ 85 °C
VCC quiescent current in IVCCPMD0
PMD0
—
—
—
—
14.5
0.45
0.23
mA All registers have reset
values, clock is active at
66 MHz, CPU is stopped,
Tj ≤ 125 °C
VCC quiescent current in IVCCPSMD3
power saving mode
PSDM3 with standby
logic active
0.25
0.14
mA Tj ≤ 125 °C
WU_PWD_CFG = 28H
VCC quiescent current in IVCCPSMD4
power saving mode
mA Tj ≤ 125 °C
WU_PWD_CFG = 00H
PSDM4 with standby
logic active
Table 11
Electrical Characteristics of the GDFB Pin
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
Max.
APD low voltage (active
pull-down while device is
not powered or gate
VAPD
—
—
1.6
V
IGD = 5 mA
driver is not enabled)
RPPD value
RPPD
ΔPPD
RGDL
—
—
—
600
—
—
kΩ
%
Ω
Permanent pull-down
resistor inside gate
driver
RPPD tolerance
±25
4.4
Permanent pull-down
resistor inside gate
driver
Driver output low
impedance for GD0
—
TJ ≤ 125 °C, IGD = 0.1 A
Data Sheet
40
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Electrical Characteristics and Parameters
Table 11
Electrical Characteristics of the GDFB Pin (continued)
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
Max.
Nominal output high
voltage in PWM mode
VGDH
—
—
10.5
—
V
GDx_CFG.VOL = 3,
IGDH = –1 mA
Output voltage tolerance ΔVGDH
—
±5
%
Tolerance of
programming options if
VGDH > 10 V, IGDH = –1 mA
Rail-to-rail output high
voltage
VGDHRR
VVCC– 0.5
—
VVCC
V
If VVCC < programmed
VGDH and output at high
state
Output high current in
PWM mode for GD0
–IGDH
—
100
—
mA GDx_CFG.CUR = 8
Output high current
tolerance in PWM mode
ΔIGDH
—
±15
—
%
Calibrated 13)
Discharge current for
GD0
IGDDIS
800
—
—
mA VGD = 4 V and driver at
low state
Output low reverse
current
–IGDREVL
IGDREVH
—
100
—
mA Applies if VGD < 0 V and
driver at low state
Output high reverse
current in PWM mode
—
1/6 of IGDH
Applies if
VGD > VGDH + 0.5 V (typ)
and driver at high state
Table 12
Electrical Characteristics of the CSFB Pin
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
–0.5
Max.
Input voltage operating VINP
range
—
3.0
—
V
OCP2 comparator
reference voltage,
derived from VVDDA, given
values assuming
VOCP2
—
1.6
V
SYS_CFG0.OCP2 = 00B
VVDDA = VVDDA,typ
Threshold voltage
tolerance
ΔVOCP2
—
—
—
—
—
±5
%
Voltage divider tolerance
Comparator propagation tOCP2PD
delay
15
—
35
ns
ns
ns
Minimum comparator
input pulse width
tOCP2PW
30
OCP2F comparator
propagation delay
tOCP2FPD
70
170
dVCS/dt = 100 V/µs
13
referred to GDx_CFG.CUR = 16
Data Sheet
41
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Electrical Characteristics and Parameters
Table 12
Electrical Characteristics of the CSFB Pin (continued)
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
Max.
190
Delay from VCS crossing tCSGDxOCP2 125
VCSOCP2 to begin of GDx
turn-off (IGD0 > 2mA)
135
ns
dVCS/dt = 100 V/µs;
fMCLK = 66 MHz. GDx
driven by QR_GATE
FIL_OCP2.STABLE = 3
OCP1 operating range
VOCP1
0
—
VREF/2
1266
V
RANGE =00B
OCP1 threshold at full
scale setting
VOCP1FS
1192
1229
mV RANGE =00B
(CS_OCP1LVL=FFH) for
CS0
Delay from VCS crossing tCSOCP1
VCSOCP1 to CS_OCP1
rising edge, 1.2 V range
90
170
250
ns
Input signal slope dVCS/
dt = 150 mV/µs. This
slope represents a use
case of a switch-mode
power supply with
minimum input voltage.
Delay from CS_OCP1
rising edge to QR_GATE
falling edge
tOCP1GATE
—
1
—
3
12
5
ns
ns
ns
STB_RET31.
OCP_ASM_SEL=0
Delay from QR_GATE
falling edge to start of
GDx turn-off
tGATEGDx
GDx driven by QR_GATE.
Measured up to
IGDx > 2 mA
OCP1 comparator input tOCP1PW
single pulse width filter
60
—
95
Shorter pulses than min.
are suppressed, longer
pulses than max. are
passed
Nominal S&H operating VCSH
range 0% to 100%
0
—
—
—
VREF/2
92
V
CS_ICR.RANGE =00B
Reduced S&H operating RRCVSH
range
8
%
CS_ICR.RANGE =00B
Operational values
Maximum error of CS0
S&H for corrected
measurement (8-bit
result)
TET0CS0S
—
4.7
LSB CS_ICR.RANGE =00B
Maximum error of CS0
S&H for corrected
measurement (8-bit
result)
TET256CS0S
—
—
6.0
LSB CS_ICR.RANGE =00B
Nominal S&H operating VCSH
range 0% to 100%
0
—
—
VREF/6
80
V
CS_ICR.RANGE =11B
Reduced S&H operating RRCVSH
range
20
%
CS_ICR.RANGE =11B
Operational values
Data Sheet
42
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Electrical Characteristics and Parameters
Table 12
Electrical Characteristics of the CSFB Pin (continued)
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
Max.
Maximum error of CS0
S&H for corrected
measurement (8-bit
result)
TET0CS0S
—
—
—
—
—
—
8.0
8.7
LSB CS_ICR.RANGE =11B
Maximum error of CS0
S&H for corrected
measurement (8-bit
result)
TET256CS0S
LSB CS_ICR.RANGE =11B
S&H delay of input buffer tCSHST
510
ns
Referring to jump in
input voltage. Limits the
minimum gate driver Ton
time.
Table 13
Electrical Characteristics of the ZCD Pin
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
–0.5
Max.
Input voltage operating VINP
range
—
—
3.3
V
Input clamping current, ICLH
high
—
100
µA
Zero-crossing threshold VZCTHR
15
30
40
50
70
70
mV
Comparator propagation tZCPD
delay
ns
dVZCD/dt = 4 V/µs
Input voltage negative
clamping level
–VINPCLN
140
0
180
—
220
4
mV Analog clamp activated
Nominal I/V-conversion –IIV
operating range 0% to
100%
mA CRNG =00B Gain = 600
mV/mA
Reduced I/V-conversion RRIV
operating range
5
—
—
80
%
Maximum error for
corrected ADC
measurement (8-bit
result)
TET0IV
—
4.1
LSB8 CRNG =00B
Maximum error for
corrected ADC
measurement (8-bit
result)
TET256IV
—
—
9.7
LSB8 CRNG =00B
Data Sheet
43
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Electrical Characteristics and Parameters
Table 13
Electrical Characteristics of the ZCD Pin (continued)
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
Max.
Maximum deviation
between ZCD clamp
voltage and trim result
stored in OTP
EZCDClp
—
—
±5
%
–IIV > 0.25 mA
IV-conversion delay of
input buffer
tIVST
VZSH
—
0
—
—
900
ns
V
Refers to jump in input
current14)
Nominal S&H input
voltage range 0% to
100%
2/3 · VREF
SHRNG =0B
Nominal S&H input
voltage range 0% to
100%
VZSH
VREF /2
—
7/6 · VREF
V
SHRNG =1B
Reduced S&H input
voltage range
RRZVSH
4
—
—
95
%
Maximum error for
corrected ADC
measurement (8-bit
result)
TET0ZVS0
—
3.7
LSB8 SHRNG =0B
LSB8 SHRNG =0B
LSB8 SHRNG =1B
LSB8 SHRNG =1B
Maximum error for
corrected ADC
measurement (8-bit
result)
TET256ZVS0
TET0ZVS1
—
—
—
—
—
—
4.9
4.2
5.8
Maximum error for
corrected ADC
measurement (8-bit
result)
Maximum error for
corrected ADC
measurement (8-bit
result)
TET256ZVS1
S&H delay of input buffer tZSHST
referring to jump of input
voltage
—
—
—
—
1.0
1.6
µs
µs
SHRNG =0BTj ≤ 125 °C
S&H delay of input buffer tZSHST
referring to jump of input
voltage
SHRNG =1BTj ≤ 125 °C
14
Limits the minimum gate driver Ton time.
Data Sheet
44
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Electrical Characteristics and Parameters
Table 14
Electrical Characteristics of the VS Pin
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
Max.
VREF
Nominal measurement
range 0% to 100%
VVS
VVS
0
—
—
V
V
Gain 1, no offset
Nominal measurement
range 0% to 100%
5/6·VREF
7/6·VREF
Gain 3, with offset
Reduced operating range RRVVS
Reduced operating range RRVVS
5
—
—
—
95
90
4.1
%
%
Gain 1, no offset
10
—
Gain 3, with offset
Maximum error for
corrected measurement
(8-bit result)
TET0VS
LSB8 Range 1, no offset
LSB8 Range 1, no offset
LSB8 Range 2, with offset
LSB8 Range 2, with offset
V
Maximum error for
corrected measurement
(8-bit result)
TET256VS
TET0VS
—
—
—
—
—
—
5.6
Maximum error for
corrected measurement
(8-bit result)
12.0
12.9
Maximum error for
corrected measurement
(8-bit result)
TET256VS
Overvoltage comparator THROV
threshold
2.70
—
2.8
—
2.90
300
Overvoltage comparator tPDOV
propagation delay
µs
Step at input
Table 15
Electrical Characteristics of the HV Pin
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
Max.
Leakage current at HV
pin
IHVleak
IMEAS
—
0
—
—
10
µA
VHV = 600 V HV startup
cell disabled
Nominal current for
measurement path 0% to
100%
9.6
mA CURRNG = 11B
Reduced measurement
range for current path
RRIMEAS
TET0DP
5
—
—
78
%
CURRNG = 11B.
Operational values.
Maximum error for
corrected ADC
—
5.7
LSB8 CURRNG = 11B
measurement (8-bit
result, temperature gain
correction applied)
Data Sheet
45
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Electrical Characteristics and Parameters
Table 15
Electrical Characteristics of the HV Pin (continued)
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
Max.
Maximum error for
corrected ADC
TET256DP
—
—
6.3
LSB8 CURRNG = 11B
measurement (8-bit
result, temperature gain
correction applied)
Table 16
Electrical Characteristics of the PWM Pin
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
Max.
Input capacitance
Input low voltage
Input high voltage
CINPUT
VIL
—
—
—
—
—
10
1.0
—
pF
V
—
VIH
2.0
–5
V
Input leakage current, no ILK
pull device
+1
µA
µA
µA
VMFIO = 0 V / 3 V
Input low current with
active weak pull-up WPU
–ILPU
30
90
—
—
90
Measured at max. VIL
Measured at min. VIH
Input high current with
active weak pull-down
WPD
IHPD
300
Pull-up resistor value
RPU
—
2.25
—
—
kΩ
%
RPU=1111B
Pull-up resistor tolerance ΔRPU
—
±20
2000
95
Overall tolerance
PWM input frequency
PWM duty cycle
fPWM
500
5
—
Hz
%
DPWM
—
Table 17
Electrical Characteristics of the TEMP Pin
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
Max.
MFIO reference voltage
VMFIOREF
VMFIO
—
0
VREF
—
V
V
Selection = VREF
Gain = 1
Nominal range 0% to
100%
—
—
—
VREF
Reduced operating range RRVMFIO
4
96
%
Gain = 1. Operational
values.
Maximum error for
corrected measurement
(8-bit result)
TET0MFI0
—
4.0
LSB8 Gain = 1
Maximum error for
corrected measurement
(8-bit result)
TET256MFI0
—
—
4.8
LSB8 Gain = 1
Data Sheet
46
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Electrical Characteristics and Parameters
Table 17
Electrical Characteristics of the TEMP Pin (continued)
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
Max.
Offset calibration voltage VCAL
—
—
VMFIOREF/8
—
—
V
Offset calibration voltage ΔVCAL
±3
LSB Ref. to VMFIOREF =VREF
Gain = 1
,
,
absolute tolerance
Offset calibration voltage ΔVCAL_TMP
variation over
—
—
±1
LSB Ref. to VMFIOREF =VREF
Gain = 1
temperature
Pull-up resistor value
RPU
—
—
11
—
—
kΩ
%
RPU=0110B
Pull-up resistor tolerance ΔRPU
±20
Overall tolerance
Table 18
Electrical Characteristics of the CSPFC Pin
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
–0.5
Max.
Input voltage operating VINP
range
—
—
3.0
V
OCP1 operating range
VOCP1
0
VREF/2
—
V
V
RANGE =00B
OCP2 comparator
reference voltage,
derived from VVDDA, given
values assuming
VOCP2
—
1.6
SYS_CFG0.OCP2 = 00B
VVDDA = VVDDA,typ
Threshold voltage
tolerance
ΔVOCP2
—
—
±5
%
Voltage divider tolerance
Comparator propagation tOCP2PD
delay
15
—
—
35
ns
ns
ns
ns
Minimum comparator
input pulse width
tOCP2PW
—
30
OCP2F comparator
propagation delay
tOCP2FPD
70
—
170
190
dVCS/dt = 100 V/µs
Delay from VCS crossing tCSGDxOCP2 125
VCSOCP2 to begin of GDx
135
dVCS/dt = 100 V/µs;
fMCLK = 66 MHz. GDx
driven by QR_GATE
FIL_OCP2.STABLE = 3
turn-off (IGD0 > 2mA)
Nominal S&H operating VCSH
range 0% to 100%
0
—
VREF/2
90
V
CS_ICR.RANGE =00B
Operational values
1 → 0 transition
Reduced S&H operating RRCVSH
range
4
—
%
V
Hysteretic comparator
threshold
THRHYS
—
0.54
—
Data Sheet
47
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Electrical Characteristics and Parameters
Table 18
Electrical Characteristics of the CSPFC Pin (continued)
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
Max.
Hysteretic comparator
threshold
THRHYS
ΔTHRHYS
tPDHYS
—
—
—
—
—
1.53
—
V
0 → 1 transition
Hysteretic comparator
threshold tolerance
—
±120
—
mV
ns
ns
ns
Hysteretic comparator
propagation delay
90
40
—
Rising edge
Falling edge
Hysteretic comparator
propagation delay
tPDHYS
—
Hysteretic comparator
minimum input pulse
width
tPWHYS
300
Table 19
Electrical Characteristics of the UART Pin
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
Max.
Input clamping current, –ICLL
low
—
—
—
—
—
—
100
100
1.6
µA
µA
V
only digital input
only digital input
IGD = 5 mA
Input clamping current, ICLH
high
APD low voltage (active
pull-down while device is
not powered or gate
VAPD
driver is not enabled)
Input capacitance
Input low voltage
Input high voltage
CINPUT
VIL
—
—
—
—
—
25
1.0
—
pF
V
—
VIH
2.1
30
V
Input low current with
–ILPU
90
µA
Measured at max. VIL
active weak pull-up WPU
UART baudrate
fUART
-5%
—
57600
—
+5%
500
baud
µs
Time between bytes
within a UART frame
tUART,intra-
byte
Waiting time aꢀer a
tUART,error
15
—
—
ms
missing response
Data Sheet
48
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Electrical Characteristics and Parameters
Table 20
Electrical Characteristics of the GDPFC Pin
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
Max.
APD low voltage (active
pull-down while device is
not powered or gate
VAPD
—
—
1.6
—
V
IGD = 5 mA
driver is not enabled)
RPPD value
RPPD
—
—
600
—
kΩ
%
Permanent pull-down
resistor inside gate
driver
RPPD tolerance
ΔPPD
±25
Permanent pull-down
resistor inside gate
driver
Driver output low
impedance for GD1/2
RGDL
VGDH
—
—
—
—
7.0
—
Ω
V
TJ ≤ 125 °C, IGD = 0.1 A
Nominal output high
voltage in PWM mode
10.5
—
GDx_CFG.VOL = 3,
IGDH = –1 mA
Output voltage tolerance ΔVGDH
±5
%
Tolerance of
programming options if
VGDH > 10 V, IGDH = –1 mA
Rail-to-rail output high
voltage
VGDHRR
VVCC– 0.5
—
VVCC
V
If VVCC < programmed
VGDH and output at high
state
Output high current in
PWM mode for GD1/2
–IGDH
—
104
—
mA GDx_CFG.CUR = 24
Output high current
tolerance in PWM mode
ΔIGDH
—
±15
—
%
Calibrated 15)
Discharge current for
GD1/2
IGDDIS
500
—
—
mA VGD = 4 V and driver at
low state
Output low reverse
current
–IGDREVL
IGDREVH
—
100
—
mA Applies if VGD < 0 V and
driver at low state
Output high reverse
current in PWM mode
—
1/6 of IGDH
Applies if
VGD > VGDH + 0.5 V (typ)
and driver at high state
15
referred to GDx_CFG.CUR = 16
Data Sheet
49
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Electrical Characteristics and Parameters
Table 21
Electrical Characteristics of the A/D Converter
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
Max.
16)
Integral non-linearity
INL
—
—
1
LSB8
Table 22
Electrical Characteristics of the Reference Voltage
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
Max.
Reference voltage
VREF
—
—
2.428
—
V
VREF overall tolerance
ΔVREF
—
±1.5
%
Trimmed, Tj ≤ 125 °C and
aging
Table 23
Electrical Characteristics of the OTP Programming
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
7.35
Max.
7.65
OTP programming
voltage at the VCC pin for
range C000H to CFFFH
VPP
7.5
V
V
Operational values
Operational values
OTP programming
voltage at the VCC pin for
range D000H to DFFFH
VPP
9.0
—
—
VVCC
OTP programming
current
IPP
1.6
—
mA Programming of 4 bits in
parallel
Table 24
Electrical Characteristics of the Clock Oscillators
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
19.2
Max.
21.1
Master clock oscillation tMCLK
period including all
variations
20.0
ns
%
In reference to 50 MHz
fMCLK
Main clock oscillator
frequency variation of
stored DPARAM
ΔMCLK
–3.2
—
+2.0
Temperature driꢀ and
aging only, 50 MHz fMCLK
frequency
Standby clock oscillator fSTBCLK
frequency
96
90
100
100
104
110
kHz Trimming tolerance at
TA = 25 °C
Standby clock oscillator fSTBCLK
frequency
kHz Overall tolerance
16
ADC capability measured via channel MFIO without errors due to switching of neighbouring pins, e.g. gate
drivers, measured with STC = 5. MFIO buffer non-linearity masked out by taking ADC output values ≥ 30
only.
Data Sheet
50
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Electrical Characteristics and Parameters
Table 25
Electrical Characteristics of the Temperature Sensor
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
Max.
190
Temperature sensor ADC ADCTEMP
output operating range
0
—
—
LSB ADCTEMP = 40 +
temperature / °C)
Temperature sensor
tolerance
ΔTEMP
—
±6
K
Incl. ADC conversion
accuracy at 3 σ
Data Sheet
51
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Package Dimensions
5
Package Dimensions
The package dimensions of PG-DSO-16 are provided.
Figure 31
Package Dimensions for PG-DSO-16
Dimensions in mm.
Note:
Note:
You can find all of our packages, packing types and other package information on our Infineon
Internet page “Products”: http://www.infineon.com/products.
Data Sheet
52
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
References
6
References
1.
2.
3.
4.
5.
Infineon Technologies AG: XDPL8221 Design Guide
Infineon Technologies AG: XDPL8221 Reference Board Test Report
Infineon Technologies AG: CoolMOS P7 power MOSFETs, http://www.infineon.com/P7
Infineon Technologies AG: .dp Vision User Manual
Infineon Technologies AG: .dp Interface Gen2 which can be ordered at http://ehitex.com/programmer/
486/.dp-interface-board-gen2
6.
7.
Infineon Technologies AG: .dp Interface Gen2 User Manual
Infineon Technologies AG: XDP Programming Manual
Revision History
Major changes since previous revision
Revision History
Revision
Description
1.1
•
•
•
Indication of ambient temperature for IC is deleted.
UART dimming changed from duty cycle to dimming level.
Minor Change of wording
1.0
•
Minor change of wording
Glossary
ABM
Active Burst Mode (ABM)
Active Burst Mode is an operating mode of a switched-mode power supply for very light load conditions. The
controller switches in bursts of pulses with a pause between bursts in which no switching is done.
AC
Alternating Current (AC)
An Alternating Current is a form of power supply in which the flow of electric charge periodically reverses
direction.
ADC
Analog-to-Digital Converter (ADC)
An analog-to-digital converter is a device that converts a continuous physical quantity (usually voltage) to a
digital number that represents the quantity's amplitude.
BOM
Bill of Materials (BOM)
A bill of materials is a list of the raw materials, sub-assemblies, intermediate assemblies, sub-components,
parts and the quantities of each needed to manufacture an end product.
CC
Constant Current (CC)
Constant Current is a mode of a power supply in which the output current is kept constant regardless of the
load.
Data Sheet
53
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Glossary
CCM
Continuous Conduction Mode (CCM)
Continuous Conduction Mode is an operational mode of a switching power supply in which the current is
continuously flowing and does not return to zero.
CRC
Cyclic Redundancy Check (CRC)
A cyclic redundancy check is an error-detecting code commonly used to detect accidental changes to raw data.
CV
Constant Voltage (CV)
Constant Voltage is a mode of a power supply in which the output voltage is kept constant regardless of the
load.
DAC
Digital-to-Analog Converter (DAC)
A digital-to-analog converter is a device that converts digital data into an analog signal (typically voltage).
DC
Direct Current (DC)
A Direct Current is a form of power supply in which the flow of electric charge is only into one direction.
DCM
Discontinuous Conduction Mode (DCM)
Discontinuous Conduction Mode is an operational mode of a switching power supply in which the current starts
and returns to zero.
ECG
Electronic Control Gear (ECG)
An electronic control gear is a power supply which provides one or more light module(s) with the appropriate
voltage or current.
EMI
Electro-Magnetic Interference (EMI)
Also called Radio Frequency Interference (RFI), this is a (usually undesirable) disturbance that affects an
electrical circuit due to electromagnetic radiation emitted from an external source. The disturbance may
interrupt, obstruct, or otherwise degrade or limit the effective performance of the circuit.
FB
Flyback (FB)
A flyback converter is a power converter with the inductor split to form a transformer, so that the voltage ratios
are multiplied with an additional advantage of galvanic isolation between the input and any outputs.
FW
Firmware (FW)
A proprietary soꢀware exploiting a set of functions.
GUI
Graphic User Interface (GUI)
A graphical user interface is a type of interface that allows users to interact with electronic devices through
graphical icons and visual indicators.
HW
Hardware (HW)
The collection of physical elements that comprise a computer system.
Data Sheet
54
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Glossary
IC
Integrated Circuit (IC)
A miniaturized electronic circuit that has been manufactured in the surface of a thin substrate of semiconductor
material. An IC may also be referred to as micro-circuit, microchip, silicon chip, or chip.
IIR
Infinite Impulse Response (IIR)
Infinite impulse response is a property applying to many linear time-invariant systems. Common examples of
linear time-invariant systems are most electronic and digital filters. Systems with this property have an impulse
response which does not become exactly zero past a certain point, but continues indefinitely.
LED
Light Emitting Diode (LED)
A light-emitting diode is a two-lead semiconductor light source which emits light when activated.
LP
Limited Power (LP)
Limited Power is a mode of a power supply in which the output power is limited regardless of the load.
NTC
Negative Temperature Coefficient Thermistor (NTC)
A negative temperature coefficient thermistor is a type of resistor whose resistance declines over temperature.
OCP1
Overcurrent Protection Level 1 (OCP1)
The Overcurrent Protection Level 1 is limiting the current in a switched-mode power supply to limit the power
delivered to the output of the power supply.
OCP2
Overcurrent Protection Level 2 (OCP2)
The Overcurrent Protection Level 2 is protecting the current in a switched-mode power supply from exceeding a
maximum threshold.
OTP
One Time Programmable Memory (OTP)
A One-Time Programmable memory is a form of memory to which data can be written once. Aꢀer writing, the
data is stored permanently and cannot be further changed.
PF
Power Factor (PF)
Power factor is the ratio between the real power and the apparent power.
PFC
Power Factor Correction (PFC)
Power factor correction increases the power factor of an AC power circuit closer to 1 which corresponds to
minimizing the reactive power of the power circuit.
PSR
Primary Side Regulated (PSR)
A Primary Side Regulated power supply controls its operation based on a property sensed on primary side of an
isolated power supply.
PWM
Pulse Width Modulation (PWM)
Pulse-width modulation is a technique to encode an analog value into the duty cycle of a pulsing signal with
arbitrary amplitude.
Data Sheet
55
Revision 1.1
2018-10-31
XDPL8221 Digital PFC+Flyback Controller IC
™
XDP Digital Power
Glossary
QRM
Quasi-Resonant Mode (QRM)
Quasi-Resonant Mode is an operating mode of a switched-mode power supply which maximizes efficiency. This
is achieved by only switching at preferred times when switching losses are low.
QRM1
Quasi-Resonant Mode, switching in first valley (QRM1)
Quasi-Resonant Mode is an operating mode of a switched-mode power supply which maximizes efficiency. This
is achieved by switching at the occurrence of the first valley of a signal which corresponds to a time when
switching losses are low.
QRMn
Quasi-Resonant Mode, switching in valley n (QRMn)
Quasi-Resonant Mode is an operating mode of a switched-mode power supply which maximizes efficiency. This
is achieved by switching at the occurence of an nth valley of a signal which corresponds to a time when
switching losses are low.
RAM
Random Access Memory (RAM)
Random-access memory is a form of computer data storage which allows data items to be read and written
regardless of the order in which data items are accessed.
THD
Total Harmonic Distortion (THD)
The total harmonic distortion of a signal is a measurement of the harmonic distortion present and is defined as
the ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency.
UART
Universal Asynchronous Receiver Transmitter (UART)
A universal asynchronous receiver transmitter is used for serial communications over a peripheral device serial
port by translating data between parallel and serial forms.
USB
Universal Serial Bus (USB)
Universal Serial Bus is an industry standard that defines cables, connectors and communications protocols
used in a bus for connection, communication, and power supply between computers and electronic devices.
UVLO
Undervoltage Lockout (UVLO)
The Undervoltage-Lockout is an electronic circuit used to turn off the power of an electronic device in the event
of the voltage dropping below the operational value.
Data Sheet
56
Revision 1.1
2018-10-31
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2018-10-31
Published by
IMPORTANT NOTICE
WARNINGS
The information given in this document shall in no
event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”) .
With respect to any examples, hints or any typical values
stated herein and/or any information regarding the
application of the product, Infineon Technologies
hereby disclaims any and all warranties and liabilities of
any kind, including without limitation warranties of
non-infringement of intellectual property rights of any
third party.
In addition, any information given in this document is
subject to customer’s compliance with its obligations
stated in this document and any applicable legal
requirements, norms and standards concerning
customer’s products and any use of the product of
Infineon Technologies in customer’s applications.
Due to technical requirements products may contain
dangerous substances. For information on the types
in question please contact your nearest Infineon
Technologies office.
Except as otherwise explicitly approved by Infineon
Technologies in a written document signed by
authorized representatives of Infineon Technologies,
Infineon Technologies’ products may not be used in
any applications where a failure of the product or
any consequences of the use thereof can reasonably
be expected to result in personal injury
Infineon Technologies AG
81726 Munich, Germany
©
2018 Infineon Technologies AG
All Rights Reserved.
Do you have a question about any
aspect of this document?
Email: erratum@infineon.com
Document reference
IFX-ddk1479303396071
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer’s technical departments to
evaluate the suitability of the product for the intended
application and the completeness of the product
information given in this document with respect to such
application.
相关型号：
XDPP1100-Q024
英飞凌推出业界中尺寸最小的 24 引脚 VQFN 封装数字电源控制器。这款高度集成的可编程XDP™ 数字电源控制器 XDPP1100-Q024 可提供先进的电源控制解决方案。该产品面向广泛的直流-直流电源应用，并支持各种隔离和非隔离拓扑。
INFINEON
XDPP1100-Q040
XDPP1100-Q040 是一款高度集成的可编程 XDP™数字电源控制器。该器件为各种直流-直流电源应用提供高级电源控制解决方案，并支持各种隔离和非隔离拓扑。
INFINEON
XDPS21081
英飞凌 XDPS21081 是一款反激式控制器IC，其初级侧引入 ZVS （零电压开关），通过简化电路和经济型开关来实现更高的工作效率。与传统的谷值开关方案相比，通过驱动外部低压开关产生负电流使主高压开关 MOSFET 放电，从而进一步降低开关损耗。 为了以同步整流实现更高效率，XDPS21081 多模式数字强制准谐振 (FQR) 反激控制器 IC 通过谷值检测来确保 DCM （非连续导通模式）工作模式，从而实现更安全可靠的运行。
INFINEON
XDPS2201
XDP™ 数字电源 XDPS2201是一种多模式、数字可配置的混合反激控制器，它结合了传统简化的反激拓扑结构和谐振变换器的性能。通过使用两个高压MOSFET，例如CoolMOSTM，混合反激XDPS2201控制器能够在不对称半桥反激拓扑中驱动高压侧和低压侧MOSFET。通过调节正负磁化电流的方法，可以在初级实现零电压开关和次级实现零电流开关，提高了效率。此外，变压器漏感能量被回收，更进一步提高效率。
INFINEON
XDRA821UXXGALM
Dual Arm Cortex-A72, quad Cortex-R5F, 4-port Ethernet switch, and a PCIe controller | ALM | 433 | -40 to 125
TI
©2020 ICPDF网 联系我们和版权申明