TLS850F0TAV33ATMA1_技术文档

Low Dropout Linear Voltage Regulator

TLS850F0TAV33

Linear Voltage Regulator

Data Sheet

Rev. 1.0, 2015-12-01

Automotive Power

TLS850F0TAV33

Table of Contents

1

2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3

3.1

3.2

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin Assignment TLS850F0TAV33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin Definitions and Functions TLS850F0TAV33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4

General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.1

4.2

4.3

5

Block Description and Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Voltage Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Typical Performance Characteristics Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Typical Performance Characteristics Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Typical Performance Characteristics Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Typical Performance Characteristics Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Standard Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Typical Performance Characteristics Standard Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.1

5.2

5.3

5.4

5.5

5.6

5.7

5.8

5.9

5.10

6

Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Selection of External Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Further Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.1

6.2

6.2.1

6.2.2

6.3

6.4

6.5

7

8

Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Data Sheet

2

Rev. 1.0, 2015-12-01

Low Dropout Linear Voltage Regulator

TLS850F0TAV33

1

Overview

Features

•

Wide Input Voltage Range from 3.0 V to 40 V

Fixed Output Voltage 3.3 V

Output Voltage Precision ≤ ±2 %

Output Current Capability up to 500 mA

Ultra Low Current Consumption typ. 40 µA

Very Low Dropout Voltage typ. 80 mV@100 mA

Stable with Ceramic Output Capacitor of 1 µF

Delayed Reset at Power-On: 16.5 ms

Adjustable Reset Threshold down to 2.50 V

Figure 1

PG-TO263-7

Watchdog with fixed timing and current dependent deactivation: 96 ms,

Activated at I_Q> 5.5 mA

•

Enable, Undervoltage Reset, Overtemperature Shutdown

Output Current Limitation

Wide Temperature Range

Green Product (RoHS compliant)

AEC Qualified

Data Sheet

3

Rev. 1.0, 2015-12-01

TLS850F0TAV33

Overview

Functional Description

The TLS850F0TAV33 is a high performance very low dropout linear voltage regulator for 3.3 V supply in a PG-

TO263-7 package.

With an input voltage range of 3 V to 40 V and very low quiescent of only 40 µA, these regulators are perfectly

suitable for automotive or any other supply systems connected to the battery permanently. The TLS850F0TAV33

provides an output voltage accuracy of 2 % and a maximum output current up to 500 mA.

The new loop concept combines fast regulation and very good stability while requiring only one small ceramic

capacitor of 1 µF at the output. At currents below 100 mA the device will have a very low typical dropout voltage

of only 80 mV. The operating range starts already at input voltages of only 3 V (extended operating range). This

makes the TLS850F0TAV33 also suitable to supply automotive systems that need to operate during cranking

condition.

The device can be switched on and off by the Enable feature as described in Chapter 5.5.

The output voltage is supervised by the Reset feature, including Undervoltage Reset, delayed Reset at Power-On

and an adjustable lower Reset Threshold, more details can be found in Chapter 5.7.

In addition, a Watchdog circuit with fixed timing is integrated to monitor the microcontroller‘s operation.

Internal protection features like output current limitation and overtemperature shutdown are implemented to

protect the device against immediate damage due to failures like output short circuit to GND, over-current and

over-temperatures.

Choosing External Components

An input capacitor C_Iis recommended to compensate line influences. The output capacitor C_Qis necessary for

the stability of the regulating circuit. TLS850F0TAV33 is designed to be also stable with low ESR ceramic

capacitors.

Type

Package

Marking

TLS850F0TAV33

PG-TO263-7

850F0V33

Data Sheet

4

Rev. 1.0, 2015-12-01

TLS850F0TAV33

Block Diagram

2

Block Diagram

I

Q

Current

Limitation

RO/WO

RADJ

Reset

EN

Enable

Bandgap

Reference

WI

Temperature

Shutdown

Watchdog

GND

Figure 2

Block Diagram TLS850F0TAV33

Data Sheet

5

Rev. 1.0, 2015-12-01

TLS850F0TAV33

Pin Configuration

3

Pin Configuration

3.1

Pin Assignment TLS850F0TAV33

1 2 3 4 5 6 7

Figure 3

Pin Configuration

3.2

Pin Definitions and Functions TLS850F0TAV33

Symbol

Function

Input

1

I

It is recommended to place a small ceramic capacitor (e.g. 100 nF) to GND, close

to the IC terminals, in order to compensate line influences. See also Chapter 6.2.1

2

3

EN

Enable (integrated pull-down resistor)

Enable the IC with high level input signal;

Disable the IC with low level input signal;

RO/WO

Reset Output / Watchdog Output (intergrated pull-up resistor to Q)

Open collector output;

Leave open if the reset and watchdog function are not needed

4

5

GND

Ground

RADJ

Reset Threshold Adjustment

Connect to GND to use standard value;

Connect an external voltage divider to adjust reset threshold

6

7

WI

Q

Watchdog Input (integrated pull-down resistor)

Serve Watchdog with trigger input signal (usable for microcontroller monitoring)

Output Voltage

Connect output capacitor C_Qto GND close to the IC’s terminals, respecting the

values specified for its capacitance and ESR in “Functional Range” on Page 8

Heat

Slug

–

Heat Slug

Connect to heatsink area;

Connect to GND

Data Sheet

6

Rev. 1.0, 2015-12-01

TLS850F0TAV33

General Product Characteristics

4

General Product Characteristics

4.1

Absolute Maximum Ratings

Table 1

Absolute Maximum Ratings¹⁾

T_j= -40 °C to +150 °C; all voltages with respect to ground (unless otherwise specified)

Parameter

Symbol

Values

Unit Note /

Test Condition

Number

Min. Typ. Max.

Input I, Enable EN

Voltage

V_I, V_EN

-0.3

–

45

7

V

–

P_4.1.1

P_4.1.3

P_4.1.5

Output Q, Reset/Watchdog Output RO/WO

Voltage V_Q, V_RO/WO-0.3

Watchdog Input WI, Reset Threshold Adjustment RADJ

–

Voltage

V_WI, V_RADJ-0.3

7

Temperatures

Junction Temperature

Storage Temperature

ESD Absorption

T_j

-40

-55

–

150

°C

–

P_4.1.7

P_4.1.8

T_stg

ESD Susceptibility to GND

V_ESD

-2

–

2

kV

V

²⁾HBM

³⁾CDM

P_4.1.9

-500

-750

500

750

P_4.1.10

P_4.1.12

ESD Susceptibility Pin 1, 7 (corner pins) V_ESD1,7

to GND

V

1) Not subject to production test, specified by design.

2) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS001 (1.5 kΩ, 100 pF)

3) ESD susceptibility, Charged Device Model “CDM” according JEDEC JESD22-C101

Note:

1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the

data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not

designed for continuous repetitive operation.

Data Sheet

7

Rev. 1.0, 2015-12-01

TLS850F0TAV33

General Product Characteristics

4.2

Functional Range

Table 2

Functional Range

T_j= -40 °C to +150 °C; all voltages with respect to ground (unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note /

Test Condition

Number

Min.

V

Max.

40

1)

Input Voltage Range

V_I

_Q,nom+ V_dr

–

V

–

P_4.2.1

P_4.2.3

P_4.2.5

P_4.2.6

2)

Extended Input Voltage Range

Enable Voltage Range

V_I,ext

V_EN

C_Q

3.0

0

40

V

40

V

–

3)4)

Output Capacitor’s

1

–

µF

–

Requirements for Stability

3)

ESR

ESR(C_Q) –

T_j-40

–

100

150

Ω

–

P_4.2.7

P_4.2.9

Junction Temperature

°C

–

1) Output current is limited internaly and depends on the input voltage, see Electrical Characteristics for more details.

2) When V_Iis between V_I,ext,minand V_Q,nom+ V_dr, V_Q= V_I- V_dr. When V_Iis below V_I,ext,min, V_Qcan drop down to 0 V.

3) Not subject to production test, specified by design.

4) The minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30%

Note:Within the functional or operating range, the IC operates as described in the circuit description. The electrical

characteristics are specified within the conditions given in the Electrical Characteristics table.

Data Sheet

8

Rev. 1.0, 2015-12-01

TLS850F0TAV33

General Product Characteristics

4.3

Thermal Resistance

Note:This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go

to www.jedec.org.

Table 3

Thermal Resistance

Parameter

Symbol

Values

Typ.

Unit

Note /

Test Condition

Number

Min.

Max.

Package Version PG-TO263-7

Junction to Case

1)

R_thJC

R_thJA

–

3

–

K/W

–

P_4.3.6

P_4.3.7

P_4.3.8

Junction to Ambient

21

75

¹⁾²⁾2s2p board

¹⁾³⁾1s0p board,

Junction to Ambient

footprint only

Junction to Ambient

R_thJA

–

42

34

–

K/W

¹⁾³⁾1s0p board,

300 mm²heatsink

area on PCB

¹⁾³⁾1s0p board,

600 mm²heatsink

area on PCB

P_4.3.9

R_thJA

P_4.3.10

1) Not subject to production test, specified by design

2) Specified R_thJAvalue is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product

(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).

Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.

3) Specified R_thJAvalue is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product

(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm³board with 1 copper layer (1 x 70µm Cu).

Data Sheet

9

Rev. 1.0, 2015-12-01

TLS850F0TAV33

Block Description and Electrical Characteristics

5

Block Description and Electrical Characteristics

5.1

Voltage Regulation

The output voltage V_Qis divided by a resistor network. This fractional voltage is compared to an internal voltage

reference and the pass transistor is driven accordingly.

The control loop stability depends on the output capacitor C_Q, the load current, the chip temperature and the

internal circuit design. To ensure stable operation, the output capacitor’s capacitance and its equivalent series

resistor (ESR) requirements given in “Functional Range” on Page 8 have to be maintained. For details, also see

the typical performance graph “Output Capacitor Series Resistor ESR(CQ) versus Output Current IQ” on

Page 13. As the output capacitor also has to buffer load steps, it should be sized according to the application’s

needs.

An input capacitor C_Iis recommended to compensate line influences. In order to block influences like pulses and

HF distortion at input side, an additional reverse polarity protection diode and a combination of several capacitors

for filtering should be used. Connect the capacitors close to the component’s terminals.

In order to prevent overshoots during start-up, a smooth ramp up function is implemented. This ensures almost

no output voltage overshoots during start-up, mostly independent from load and output capacitance.

Whenever the load current exceeds the specified limit, e.g. in case of a short circuit, the output current is limited

and the output voltage decreases.

The overtemperature shutdown circuit prevents the IC from immediate destruction under fault conditions (e.g.

output continuously short-circuit) by switching off the power stage. After the chip has cooled down, the regulator

restarts. This leads to an oscillatory behavior of the output voltage until the fault is removed. However, junction

temperatures above 150 °C are outside the maximum ratings and therefore significantly reduce the IC’s lifetime.

Regulated

Output Voltage

Supply

I_Q

I_I

I

Q

RO/WO

RADJ

Current

Limitation

Reset

EN

C

Enable

C_I

V_I

V_Q

Bandgap

Reference

LOAD

ESR

Temperature

Shutdown

C_Q

WI

Watchdog

GND

Figure 4

Voltage Regulation

V

V_I

V_dr

V_Q,nom

V_I,ext,min

V_Q

t

Figure 5

Output Voltage vs. Input Voltage

Data Sheet

10

Rev. 1.0, 2015-12-01

TLS850F0TAV33

Block Description and Electrical Characteristics

Table 4

Electrical Characteristics Voltage Regulator 3.3 V version

T_j= -40 °C to +150 °C, V_I= 13.5 V, all voltages with respect to ground (unless otherwise specified)

Typical values are given at T_j= 25 °C

Parameter

Symbol

Values

Unit Note / Test Condition

Number

Min. Typ. Max.

Output Voltage Precision

V_Q

3.23 3.3

3.37

18

V

0.05 mA < I_Q< 500 mA

4.23 V < V_I< 28 V

P_5.1.23

P_5.1.24

P_5.1.27

3.23 3.3

0.05 mA < I_Q< 200 mA

3.72 V < V_I< 40 V

Output Voltage Start-up

slew rate

dV_Q/dt 3.0

7.5

V/ms V_I> 18 V/ms

C_Q= 1 µF

0.33 V < V_Q< 2.97 V

650 1100 mA 0 V < V_Q< 3.1 V

Output Current Limitation

I_Q,max

501

P_5.1.29

P_5.1.31

Load Regulation

steady-state

∆V_Q,load-20

-1.5

5

mV

I_Q= 0.05 mA to 500 mA

V_I= 6 V

Line Regulation

steady-state

∆V_Q,line-15

0

15

mV

V_I= 8 V to 32 V

I_Q= 5 mA

P_5.1.33

P_5.1.36

P_5.1.37

P_5.1.38

P_5.1.39

P_5.1.40

Dropout Voltage

V_dr= V_I- V_Q

V_dr

–

200 430 mV ¹⁾I_Q= 250 mA

Dropout Voltage

V_dr= V_I- V_Q

V_dr

–

80

63

–

175 mV ¹⁾I_Q= 100 mA

Power Supply Ripple Rejection

PSRR

T_j,sd

T_j,sdh

–

dB

²⁾f_ripple= 100 Hz

_ripple= 0.5 Vpp

V

Overtemperature Shutdown

Threshold

151

–

200 °C

²⁾T_jincreasing

Overtemperature Shutdown

Threshold Hysteresis

15

–

K

²⁾T_jdecreasing

1) Measured when the output voltage V_Qhas dropped 100 mV from the nominal value obtained at V_I= 13.5V

2) Not subject to production test, specified by design

Data Sheet

11

Rev. 1.0, 2015-12-01

TLS850F0TAV33

Block Description and Electrical Characteristics

5.2

Typical Performance Characteristics Voltage Regulator

Typical Performance Characteristics

Output Voltage V_Qversus

Junction Temperature T_j

Dropout Voltage V_drversus

Junction Temperature T_j

3.5

350

I_Q= 100mA

I_Q= 100 mA

I_Q= 250 mA

3.45

3.4

300

V_Q= 3.3 V

250

200

150

100

50

3.35

3.3

3.25

3.2

3.15

3.1

0

−40

0

50

100

150

0

50

100

150

T_j[°C]

Load Regulation ∆V_Q,loadversus

Output Current Change I_Q

Line Regulation ∆V_Q,lineversus

Input Voltage V_I

8

0

−2

I_Q= 5 mA

T_j= −40 ^o

T_j= 25 ^o

T_j= 150 ^oC

C

6

4

−4

−6

2

−8

−10

−12

0

−2

−4

−6

−8

−14

V_I= 6 V

−16

T_j= −40 ^o

C

T_j= 25 ^o

T_j= 150 ^oC

100 200

C

−18

−20

0

300

I_Q[mA]

400

500

10

15

20

25

30

V_I[V]

Data Sheet

12

Rev. 1.0, 2015-12-01

TLS850F0TAV33

Block Description and Electrical Characteristics

Output Voltage V_Qversus

Input Voltage V_I

Power Supply Ripple Rejection PSRR versus

ripple frequency f

4

80

T_j= 25 ^o

C

T_j= −40 °C

T_j= 25 °C

3.5

70

60

50

40

30

20

10

0

T_j= 150 °C

I_Q= 100 mA

3

2.5

2

1.5

1

I_Q= 10 mA

_Q= 1 μF

_ripple= 0.5 V_pp

0.5

0

C

V

10⁻²

10⁻¹

10⁰

10¹

10²

10³

0

1

2

3

4

5

6

V_I[V]

f [kHz]

Output Capacitor Series Resistor ESR(C_Q) versus

Output Current I_Q

Maximum Output Current I_Qversus

Input Voltage V_I

10³

1200

1000

800

Unstable Region

10²

10¹

Stable Region

600

10⁰

400

V_Q= 0 V

T_j= −40 ^o

T_j= 25 ^o

T_j= 150 ^oC

30

10⁻¹

C

200

0

C_Q= 1 μF

C

T_j= 25 ^o

C

10⁻²

0.05

0

10

20

V_I[V]

40

1

10

I_Q[mA]

100

500

Data Sheet

13

Rev. 1.0, 2015-12-01

TLS850F0TAV33

Block Description and Electrical Characteristics

Dropout Voltage V_drversus

Output Current I_Q

500

T_j= 25 ^o

C

450

400

350

300

250

200

150

100

50

0

100

200

300

400

500

I_Q[mA]

Data Sheet

14

Rev. 1.0, 2015-12-01

TLS850F0TAV33

Block Description and Electrical Characteristics

5.3

Current Consumption

Table 5

Electrical Characteristics Current Consumption

T_j= -40 °C to +150 °C, V_I= 13.5 V (unless otherwise specified)

Typical values are given at T_j= 25 °C

Conditions of other pins: WI = GND

Parameter

Symbol

Values

Unit Note / Test Condition

Number

Min. Typ. Max.

Current Consumption

I_q= I_I

I_q,off

I_q

–

1.3

5

µA

V

_EN= 0 V; T_j< 105 °C

_EN= 0.4 V; T_j< 125 °C

P_5.3.1

P_5.3.3

P_5.3.4

Current Consumption

I_q= I_I

–

8

Current Consumption

I_q= I_I- I_Q

40

52

I_Q= 0.05 mA

T_j= 25 °C

Watchdog disabled

Current Consumption

I_q= I_I- I_Q

I_q

–

62

77

82

µA

I_Q= 0.05 mA

T_j< 125 °C

Watchdog disabled

¹⁾I_Q= 500 mA

P_5.3.7

Current Consumption

P_5.3.11

I_q= I_I- I_Q

T_j< 125 °C

Watchdog enabled

1) Not subject to production test, specified by design

Data Sheet

15

Rev. 1.0, 2015-12-01

TLS850F0TAV33

Block Description and Electrical Characteristics

5.4

Typical Performance Characteristics Current Consumption

Typical Performance Characteristics

Current Consumption I_qversus

Output Current I_Q

Current Consumption I_qversus

Input Voltage V_I

200

100

T_j= 25 ^o

C

T_j= −40 °C

180

90

80

70

60

50

40

30

20

10

0

T_j= 25 °C

T_j= 150 °C

160

V_EN= 5 V

I_Q= 50 uA

140

120

100

80

60

40

20

0

100

200

300

400

500

5

10

15

20

V_I[V]

25

30

35

40

I_Q[mA]

Data Sheet

16

Rev. 1.0, 2015-12-01

TLS850F0TAV33

Block Description and Electrical Characteristics

5.5

Enable

The TLS850F0TAV33 can be switched on and off by the Enable feature: Connect a HIGH level as specified below

(e.g. the battery voltage) to pin EN to enable the device; connect a LOW level as specified below (e.g. GND) to

shut it down. The enable has a built in hysteresis to avoid toggling between ON/OFF state, if signals with slow

slopes are applied to the EN input.

Table 6

Electrical Characteristics Enable

T_j= -40 °C to +150 °C, V_I= 13.5 V, all voltages with respect to ground (unless otherwise specified)

Typical values are given at T_j= 25 °C

Parameter

Symbol

Values

Unit

Note / Test Condition

Number

Min. Typ. Max.

High Level Input Voltage

Low Level Input Voltage

Enable Threshold Hysteresis

High Level Input Current

V_EN,H

V_EN,L

V_EN,Hy

I_EN,H

2

–

V

V_Qsettled

V_Q≤ 0.1 V

–

P_5.5.1

P_5.5.2

P_5.5.3

P_5.5.4

P_5.5.6

P_5.5.7

–

0.8

–

V

100

–

mV

µA

MΩ

3.5

22

2.6

V

–

_EN= 3.3 V

I_EN,H

–

_EN≤ 18 V

Enable internal pull-down resistor R_EN

0.95 1.5

Data Sheet

17

Rev. 1.0, 2015-12-01

TLS850F0TAV33

Block Description and Electrical Characteristics

5.6

Typical Performance Characteristics Enable

Typical Performance Characteristics

Input Current I_INversus

Input Voltage V_IN(condition: V_EN= 0 V)

Enabled Input Current I_ENversus

Enabled Input Voltage V_EN

30

50

T_j= −40 °C

45

T_j= 25 °C

25

T_j= 150 °C

40

35

30

25

20

15

10

5

V_EN= 0V

20

15

10

5

0

10

20

30

40

0

10

20

30

40

V_IN[V]

V_EN[V]

Output Voltage V_Qversus

time (EN switched ON)

6

5

4

3

2

1

0

I_Q= 100 mA

T_j= −40 °C

T_j= 25 °C

T_j= 150 °C

V_EN

0

500

1000

t [us]

1500

2000

Data Sheet

18

Rev. 1.0, 2015-12-01

TLS850F0TAV33

Block Description and Electrical Characteristics

5.7

Reset

The TLS850F0TAV33’s output voltage is supervised by the Reset feature, including Undervoltage Reset, delayed

Reset at Power-On and an adjustable Reset Threshold.

The Undervoltage Reset function sets the pin RO/WO to LOW, in case V_Qis falling for any reason below the Reset

Threshold V_RT,low

.

When the regulator is powered on, the pin RO/WO is held at LOW for the duration of the Power-On Reset Delay

Time t_rd.

Supply

I

Q

VDD

C_Q

R_{RO /WO,int}

Control

RO/WO

Reset

S

R

I_RO/WO

Reference

OR

Q

OR

Micro-

Controller

R_{ADJ ,1}

Timer

RADJ

I_RADJ

GND

R_{ADJ ,2}

Figure 6

Block Diagram Reset Circuit

Reset Delay Time

The Reset Delay Time t_rdis fix defined according to Table 7.

Table 7

Reset DelayTime

Reset delay timing

t_rd

fix

16.5 ms

Power-On Reset Delay Time

The power-on reset delay time is defined by the parameter t_rdand allows a microcontroller and oscillator to start

up. This delay time is the time period from exceeding the upper reset switching threshold V_RT,highuntil the reset is

released by switching the reset output “RO/WO” from “LOW” to “HIGH”.

Undervoltage Reset Delay Time

Unlike the power-on reset delay time, the undervoltage reset delay time is defined by the parameter t_rdand

considers an output undervoltage event where the output voltage V_Qtrigger the V_RT,lowthreshold.

Reset Blanking Time

The reset blanking time t_rr,blankavoids that short undervoltage spikes trigger an unwanted reset “low” signal.

Data Sheet

19

Rev. 1.0, 2015-12-01

TLS850F0TAV33

Block Description and Electrical Characteristics

Reset Reaction Time

In case the output voltage of the regulator drops below the output undervoltage lower reset threshold V_RT,low, the

reset output “RO/WO” is set to low, after the delay of the internal reset reaction time t_rr,int. The reset blanking time

t

_rr,blankis part of the reset reaction time t_rr,int

.

Reset Output “RO/WO”

The reset output “RO/WO” is an open collector output with an integrated pull-up resistor. In case a lower-ohmic

“RO/WO” signal is desired, an external pull-up resistor can be connected to the output “Q”. Since the maximum

“RO/WO” sink current is limited, the minimum value of the optional external resistor “R_RO/WO,ext” is given in Table

“Reset Output / Watchdog Output RO/WO” on Page 22.

Reset Output “RO/WO” Low for VQ ≥ 1 V

In case of an undervoltage reset condition reset output “RO/WO” is held “low” for V_Q≥ 1 V, even if the input voltage

V_Iis 0 V. This is achieved by supplying the reset circuit from the output capacitor.

Reset Adjust Function

The undervoltage reset switching threshold can be adjusted according to the application’s needs by connecting

an external voltage divider (R_ADJ1, R_ADJ2) at pin “RADJ”. For selecting the default threshold connect pin “RADJ” to

GND. The reset adjustment range for the TLS850F0TAV33 is given in Reset Threshold Adjustment Range.

When dimensioning the voltage divider, take into consideration that there will be an additional current constantly

flowing through the resistors.

With a voltage divider connected, the reset switching threshold V_RT,newis calculated as follows

(neglecting the Reset Adjust Pin Current I_RADJ):

V_RT,lo,new= V_RADJ,th× (R_ADJ,1+ R_ADJ,2) / R_ADJ,2

(1)

with

•

V

_RT,lo,new: Desired undervoltage reset switching threshold.

R

V

_ADJ,1, R_ADJ,2: Resistors of the external voltage divider, see Figure 6.

_RADJ,th: Reset adjust switching threshold given in Reset Adjustment Switching Threshold.

Data Sheet

20

Rev. 1.0, 2015-12-01

TLS850F0TAV33

Block Description and Electrical Characteristics

V_I

t

t < t_rr,blank

V_Q

V_RH

V_RT,high

V_RT,low

1 V

t

t_rd

t_rr,int

t_rd

t_rr,int

t_rd

t_rr,int

V_RO/WO

t_rd

1V

V_RO/WO,low

t

Thermal

Shutdown

Input

Voltage Dip

Under-

voltage

Spike at Over-

output load

Figure 7

Typical Timing Diagram Reset

Data Sheet

21

Rev. 1.0, 2015-12-01

TLS850F0TAV33

Block Description and Electrical Characteristics

Table 8

Electrical Characteristics Reset

T_j= -40 °C to +150 °C, V_I= 13.5 V, all voltages with respect to ground (unless otherwise specified)

Typical values are given at T_j= 25 °C

Parameter

Symbol

Values

Unit Note / Test Condition

Number

Min. Typ. Max.

Output Undervoltage Reset 3V3 Version only

Output Undervoltage Reset Upper V_RT,high

Switching Threshold

3.08 3.15 3.22

V

V_Qincreasing

P_5.7.5

P_5.7.6

Output Undervoltage Reset Lower V_RT,low

Switching Threshold - Default

3.0

60

3.05 3.13

V_Qdecreasing

RADJ = GND

Output Undervoltage Reset

Switching Hysteresis

V_RT,hy

V_RH

100

–

mV RADJ connected to GND P_5.7.7

Output Undervoltage Reset

100 250

mV RADJ = GND

P_5.7.8

Headroom V_Q- V_RT

Reset Threshold Adjustment

Reset Adjustment Switching

Threshold

V_RADJ,th

1.15 1.20 1.25

V

–

P_5.7.9

Reset Threshold Adjustment Range V_RT,range

2.5

–

2.9

for V_Q,nom= 3.3 V

P_5.7.11

Reset Output / Watchdog Output RO/WO

Reset Output Watchdog Output

Low Voltage

V_RO/WO,low

0.2

20

–

0.4

36

–

V

1 V ≤ V_Q≤ V_RT;

R

P_5.7.16

_RO/WO≥ 5.1 kΩ

Reset Output Watchdog Output

Internal Pull-Up Resistor

R_RO/WO,int13

R_RO/WO,ext5.1

kΩ

internally connected to Q P_5.7.17

Reset Output Watchdog Output

External Pull-up Resistor to V_Q

1 V ≤ V_Q≤ V_RT;

_RO/WO≤ 0.4 V

P_5.7.18

V

Reset Delay Timing

Reset Delay Time

t_rd

13.2 16.5 19.8 ms

Fixed Timing

¹⁾for V_Q,nom= 3.3 V

P_5.7.39

P_5.7.22

P_5.7.23

Reset blanking time

t_rr,blank

–

6

7

–

µs

Internal Reset Reaction Time

t_rr,int

20

for V_Q,nom= 3.3 V

1) Not subject to production test, specified by design.

Data Sheet

22

Rev. 1.0, 2015-12-01

TLS850F0TAV33

Block Description and Electrical Characteristics

5.8

Typical Performance Characteristics Reset

Typical Performance Characteristics

Undervoltage Reset Threshold V_RTversus

Junction Temperature T_j

Power On Reset Delay Time t_rdversus

Junction Temperature T_j

25

20

15

10

5

3.5

3.4

3.3

3.2

3.1

3

2.9

2.8

I_Q= 1 mA

V_Q= 3.3 V

2.7

2.6

2.5

RADJ set to GND

V_{RT, high}

V_{RT, low}

0

50

T_j[°C]

100

150

−40

0

50

T_j[°C]

100

150

Internal Reset Reaction Time t_rr,intversus

Junction Temperature T_j

20

18

16

14

12

10

8

6

4

2

0

−40

0

50

100

150

T_j[°C]

Data Sheet

23

Rev. 1.0, 2015-12-01

TLS850F0TAV33

Block Description and Electrical Characteristics

5.9

Standard Watchdog

The TLS850F0TAV33 features a load dependent watchdog function. The watchdog function monitors a

microcontroller, including time base failures. In case of a missing falling edge within a certain pulse repetition time,

the watchdog output “RO/WO” is set to “low”.

The watchdog uses an internal oscillator as timebase. The effective trigger window is derived from the watchdog

timebase.

The watchdog output signal is provided by a combined Reset Output / Watchdog Output “RO/WO” pin.

Supply

I

Q

VDD

C_Q

R_{RO /WO,int}

RO/WO

Reset

I_RO/WO

Reference

Control

WD core

Micro-

Controller

Control

GND

WI

I_WI

GND

Figure 8

Block Diagram Watchdog Circuit

Watchdog Timing

Figure 9 shows the state diagram of the watchdog (WD) and the mode selection. After power-on, the reset output

signal at the “RO/WO” pin (microcontroller reset) is kept LOW for the reset delay time t_rd. With the LOW to HIGH

transition of the signal at “RO/WO” the device starts the watchdog ignore time t_WI.i. Next, the WD starts the

watchdog trigger time (time frame within a trigger at WI must occur).

From now on, the timing of the signal on WI from the microcontroller must fit to the WD-trigger time t_WI,tr. A Re-

Trigger of the WD-trigger time is done with a HIGH-to-LOW transient at the WI-pin within the active t_WI,tr

.

Watchdog Output “RO/WO”

The watchdog output “RO/WO” is an open collector output with an integrated pull-up resistor. In case a lower-

ohmic “RO/WO” signal is desired, an external pull-up resistor can be connected to the output “Q”. Since the

maximum “RO/WO” sink current is limited, the minimum value of the optional external resistor “R_RO/WO,ext” is given

in Table “Reset Output / Watchdog Output RO/WO” on Page 22. A HIGH to LOW transition of the watchdog

trigger signal on pin WI is taken as a trigger. A watchdog signal is generated (“RO/WO” goes LOW), if there is no

trigger pulse during the Watchdog trigger time.

Data Sheet

24

Rev. 1.0, 2015-12-01

TLS850F0TAV33

Block Description and Electrical Characteristics

V_I

t

V_RT,high

V_RT,low

V_Q

t

I_Q

I_Q,W,act

I_Q,W,deact

t

Current Controlled

WD-turn off

Trigger

V_WI

t_rd

(WD-trigger time t_WI,tr

96ms

)

Ignore Time

t_WI,i

96ms *)

16.5ms typ.

t

WD Trigger

NO WD Trigger

WD Trigger

Don’t care WI

during t _WO,lowand

ignore time

Don’t care WI

during WD-off

and ignore time

Don’t care WI

during t_rdand ignore time

Power

Fail

V_RO/WO

t_rd

t_WO,low

No WO assertion during

Current shut down

Normal operation

t_rr,int

*) watchdog trigger time interrupted by correct WI signal serving the watchdog

Figure 9

Typical Watchdog Timing Diagram, Watchdog and Reset Modes

Watchdog Input “WI”

The watchdog is triggered by a falling edge at the watchdog input pin “WI”. The amplitude and slope of this signal

has to comply with the specification (Table “Watchdog Input WI” on Page 26). For details regarding test pulses,

see Figure 10 “Test Pulses Watchdog Input WI” on Page 25.

V_WI

t_WI,ph

V_WI,high

t_WI,pl

V_WI,low

dV_WI/ dt

t

Figure 10 Test Pulses Watchdog Input WI

Data Sheet

25

Rev. 1.0, 2015-12-01

TLS850F0TAV33

Block Description and Electrical Characteristics

Table 9

Electrical Characteristics Watchdog

T_j= -40 °C to +150 °C, V_I= 13.5 V, all voltages with respect to ground (unless otherwise specified)

Typical values are given at T_j= 25 °C

Parameter

Symbol

Values

Unit Note / Test Condition

Number

Min. Typ. Max.

Watchdog Timing

Watchdog Ignore Time

Watchdog Trigger Time

Watchdog Output Low Time

t_WI,i

12.8 16

76.8 96

19.2 ms

115.2 ms

–

P_5.9.1

P_5.9.2

P_5.9.6

t_WI,tr

–

t_WO,low

6.4

8

9.6

ms

Load Dependent Watchdog Activation

Watchdog Activation Current

Threshold

I_Q,W,act

I_Q,W,deact

I_Q,W,hy

–

5.5

mA for V_Q,nom= 3.3 V:

V_I> 4.23 V;

P_5.9.45

high current condition must

be applied at least for the

time of t_W,filter,max

Watchdog Deactivation Current

Threshold

1

–

mA for V_Q,nom= 3.3 V:

P_5.9.46

V_I> 4.23 V;

low current condition must

be applied at least for the

time of t_W,filter,max

Watchdog Deactivation Current

Hysteresis

0.35

–

mA for V_Q,nom= 3.3 V:

P_5.9.47

P_5.9.14

P_5.9.15

V_I> 4.23 V;

Watchdog Minimum Filter Time

state transition by current

t_W,IQ,filter,100

–

µs

¹⁾– see Page 27

min

Watchdog Maximum Filter Time t_W,IQ,filter,

–

500

¹⁾– see Page 27

state transition by current

max

Watchdog Input WI

2)

Watchdog Input

Low Signal Valid

V_WI,low

V_WI,high

t_WI,ph

–

0.8

–

V

–

P_5.9.16

P_5.9.17

P_5.9.19

P_5.9.20

P_5.9.21

2)

Watchdog Input

High Signal Valid

2.0

1

V

–

2)

Watchdog Input

High Signal Pulse Length

–

µs

V/µs

V

≥ V_WI,high

WI

2)

Watchdog Input

Low Signal Pulse Length

t_WI,pl

1

–

≤ V_WI,low

< V_WI< V_WI,high

Watchdog Input

Signal Slew Rate

dV_WI/dt

1

–

WI,low

High Level Input Current

I_WI,H

–

3.5

2.6

µA

V

_WI= 3.3 V

P_5.9.22

P_5.9.23

Watchdog Input internal pull-down R_WI

0.9

1.5

MΩ

–

resistor

Watchdog Disable Threshold

WI Signal Value

V_WI,dis

1.15

–

1.40

V

for V_Q,nom= 3.3 V:

V_I> 4.6 V;

P_5.9.24

signal must be applied for

> t_W,filter,maxto deactivate

and activate the watchdog

Data Sheet

26

Rev. 1.0, 2015-12-01

TLS850F0TAV33

Block Description and Electrical Characteristics

Table 9

Electrical Characteristics Watchdog (cont’d)

T_j= -40 °C to +150 °C, V_I= 13.5 V, all voltages with respect to ground (unless otherwise specified)

Typical values are given at T_j= 25 °C

Parameter

Symbol

Values

Unit Note / Test Condition

Number

Min. Typ. Max.

Watchdog Minimum Filter Time

state transition by WI

t_{WI,filter,min}100

–

µs

³⁾– see Page 28

P_5.9.25

P_5.9.26

Watchdog Maximum Filter Time t_{WI,filter,max}

–

500

state transition by WI

Reset Output / Watchdog Output RO/WO is defined in chapter Reset Output / Watchdog Output RO/WO

–

1) Not subject to production test, specified by design.

2) For details on applied test pulse, see Figure 10

3) Not subject to production test, specified by design.

Watchdog Trigger Time

The Watchdog Trigger Time t_WI,tris fixed to a static value according to Table 10.

Table 10 Watchdog Trigger Time

Watchdog trigger timing

t_WI,tr,typ

fix to

96 ms

Watchdog deactivation by current control

The Watchdog is load dependent inactive. This ensures, that if the microcontroller is in a power save mode

(I_Q≤ I_Q,W,deact) and not able to provide a correct watchdog trigger signal at pin “WI”, no watchdog signal

“RO/WO = low” is generated. The transition from an active to an inactive state will be performed after a dead time

of t_{W,IQ,filter,max}, when output current keeps below the deactivation threshold. This protects against an unintended

entering of the watchdog deactivation state caused by short dynamic current drops. In case of very short current

drops up to the time of t_{W,IQ,filter,min}, the activation state will definitely be kept. These scenarios are also valid for the

transition from deactivation to activation state. For details see also

I_Q

Scenario „D“

>t_WO,low

<t_WO,low

I_Q,W,act

I_Q,W,deact

t

V_RO/WO

WD disabled

Scenario „A“

WD-trigger time t_WI,tr*)

WD disabled

ignore time t_WI,i

WD-trigger time t_WI,tr

t_WO,low

ignore time t_WI,i

WD-trigger time t_WI,tr

*) interrupted by entering in „Watchdog deactivation by current control“

Watchdog filter time t_W,IQ,filter

Scenario „B“

WD-trigger time t_WI,tr

t_WO,low

WD-trigger time t_WI,tr

Scenario „C“

WD-trigger time t_WI,tr

t_WO,low

WD disabled

*)

WD-trigger time t_WI,tr

Figure 11 Watchdog Output behavior for Watchdog deactivation by current control

Data Sheet

27

Rev. 1.0, 2015-12-01

TLS850F0TAV33

Block Description and Electrical Characteristics

Scenario “A”

In scenario “A” the watchdog logic expects a next trigger at WI pin within the WD-trigger time t_WI,tr. This state is

interrupted by the low current load state (I_Q≤ I_Q,W,deact). During this state, the watchdog is disabled. The watchdog

output signal “RO/WO” will stay high while the watchdog is disabled. After leaving the low current load state

(I_Q≥ I_Q,W,act), an ignore window t_WI,ifollows. After this, the watchdog trigger time t_WI,trstarts. This behavior is

defined for cases with a low current load time greater than t_WO,low

.

Scenario “B”

In scenario “B” the watchdog is not served within WD-trigger time t_WI,trwith an trigger event at WI pin. As a result

the “RO/WO” is set to low. This state is interrupted by the low current load state (I_Q≤ I_Q,W,deact). During this state,

the watchdog is disabled. The watchdog output signal “RO/WO” is kept in low state for t_WO,lowand then the

“RO/WO” is set to high. After leaving the low current load state (I_Q≥ I_Q,W,act), an ignore window t_WI,ifollows. After

this, the watchdog trigger time t_WI,trstarts. This behavior is defined for cases with a low current load time greater

than t_WO,low

.

Scenario “C”

In scenario “C” the watchdog is not served within WD-trigger time t_WI,trwith an trigger event at WI pin. As a result

the “RO/WO” is set to low. After this an ignore window follows. This state is interrupted by the low current load

state (I_Q≤ I_Q,W,deact). During this state, the watchdog is disabled. The watchdog output signal “RO/WO” will stay

high while the watchdog is disabled. After leaving the low current load state (I_Q≥ I_Q,W,act), an ignore window t_WI,i

follows. After this, the watchdog trigger time t_WI,trstarts. This behavior is defined for cases with a low current load

time greater than t_WO,low

.

Scenario “D”

In scenario “D” the watchdog is not served within WD-trigger time t_WI,trwith a trigger event at WI pin. As a result

the “RO/WO” is set to low. This state is interrupted by the low current load state (I_Q≤ I_Q,W,deact). During this state,

the watchdog is disabled. The watchdog output signal “RO/WO” is kept in low state for the time of low current load

state. After leaving the low current load state (I_Q≥ I_Q,W,act), an ignore window t_WI,ifollows. After this, the watchdog

trigger time t_WI,trstarts. This behavior is defined for cases with a low current load time less than t_WO,low

.

Watchdog deactivation by external signal (pin “WI”)

Note:Disabling the watchdog should only considered when the application is not running in the normal operating

conditions as the safe operation is not ensured any more. Example would be the flashing process of the

microcontroller.

The Watchdog can be disabled by connecting a voltage level between the range of 1.15 V to 1.40 V to WI. By

entering the Watchdog deactivation, the “RO/WO” signal behaves like it is described in . The transition from active

to an inactive state will be performed after a dead time of t_{WI,filter,max}, when correct level to WI pin is applied. This

protects against the unintended entering of watchdog deactivation state. After leaving the deactivation voltage

range 1.15 V to 1.40 V, the Watchdog is again active and starts with an ignore window. This scenario is also valid

for the transition from deactivation to activation state.

Data Sheet

28

Rev. 1.0, 2015-12-01

TLS850F0TAV33

Block Description and Electrical Characteristics

V_WI

Scenario „D“

<t_WO,low

>t_WO,low

V_WI,dis.high

V_WI,dis,low

V_WI,dis.high

V_WI,dis,low

t

V_RO/WO

WD disabled

Scenario „A“

WD-trigger time t_WI,tr*)

WD disabled

ignore time t_WI,i

WD-trigger time t_WI,tr

t_WO,low

ignore time t_WI,i

WD-trigger time t_WI,tr

t

*) interrupted by entering in „Watchdog deactivation by WI pin“

Watchdog filter time t_W,IQ,filter

Scenario „B“

WD-trigger time t_WI,tr

t_WO,low

WD-trigger time t_WI,tr

Scenario „C“

WD-trigger time t_WI,tr

t_WO,low

WD disabled

*)

WD-trigger time t_WI,tr

Figure 12 Watchdog Output behavior for Watchdog deactivation by WI pin

Scenario “A”

In scenario “A” the watchdog logic expects a next trigger at WI pin within the WD-trigger time t_WI,tr. This state is

interrupted by setting V_WIto the disable condition (V_WI,dis,low≤ V_WI≤ V_WI,dis,high). During this state, the watchdog is

disabled. The watchdog output signal “RO/WO” will stay high while the watchdog is disabled. After leaving the

disable condition (V_WI≥ V_WI,dis,highor V_WI≤ V_WI,dis,low), an ignore window t_WI,ifollows. After this, the watchdog trigger

time t_WI,trstarts. This behavior is defined for cases with a low current load time greater than t_WO,low

.

Scenario “B”

In scenario “B” the watchdog is not served within WD-trigger time t_WI,trwith an trigger event at WI pin. As a result

the “RO/WO” is set to low. This state is interrupted by setting V_WIto the disable condition

(V_WI,dis,low≤ V_WI≤ V_WI,dis,high). During this state, the watchdog is disabled. The watchdog output signal “RO/WO” is

kept in low state for t_WO,lowand then the “RO/WO” is set to high. After leaving the disable condition (V_WI≥ V_WI,dis,high

or V_WI≤ V_WI,dis,low), an ignore window t_WI,ifollows. After this, the watchdog trigger time t_WI,trstarts. This behavior is

defined for cases with a low current load time greater than t_WO,low

.

Scenario “C”

In scenario “C” the watchdog is not served within WD-trigger time t_WI,trwith an trigger event at WI pin. As a result

the “RO/WO” is set to low. After this an ignore window follows. This state is interrupted by setting V_WIto the disable

condition (V_WI,dis,low≤ V_WI≤ V_WI,dis,high). During this state, the watchdog is disabled. The watchdog output signal

“RO/WO” will stay high while the watchdog is disabled. After leaving the disable condition (V_WI≥ V_WI,dis,highor

V_WI≤ V_WI,dis,low), an ignore window t_WI,ifollows. After this, the watchdog trigger time t_WI,trstarts. This behavior is

defined for cases with a low current load time greater than t_WO,low

.

Scenario “D”

In scenario “D” the watchdog is not served within WD-trigger time t_WI,trwith a trigger event at WI pin. As a result

the “RO/WO” is set to low. This state is interrupted by setting V_WIto the disable condition

(V_WI,dis,low≤ V_WI≤ V_WI,dis,high). During this state, the watchdog is disabled. The watchdog output signal “RO/WO” is

kept in low state for the time of low current load state. After leaving the disable condition (V_WI≥ V_WI,dis,highor

V_WI≤ V_WI,dis,low), an ignore window t_WI,ifollows. After this, the watchdog trigger time t_WI,trstarts. This behavior is

defined for cases with a low current load time less than t_WO,low

.

Data Sheet

29

Rev. 1.0, 2015-12-01

TLS850F0TAV33

Block Description and Electrical Characteristics

5.10

Typical Performance Characteristics Standard Watchdog

Typical Performance Characteristics

Watchdog Trigger Time t_WI,trversus

Junction Temperature T_j

Watchdog Output Low Time t_WO,lowversus

Junction Temperature T_j

15

I_Q= 10 mA

120

100

80

10

60

5

40

20

I_Q= 10 mA

0

−40

0

50

100

150

0

50

100

150

T_j[°C]

Watchdog Activation/Deactivation Current I_Q,W,act

,

Watchdog Disable V_WI,disThreshold versus

Junction Temperature T_j

I_Q,W,deactversus Junction Temperature T_j

3

2.5

2

7

6

5

4

3

2

1.5

1

0.5

1

I_Q= 10 mA

I_Q,W,deact

low

high

I_Q,W,act

0

50

T_j[°C]

100

150

0

50

T_j[°C]

100

150

Data Sheet

30

Rev. 1.0, 2015-12-01

TLS850F0TAV33

Application Information

6

Application Information

6.1

Application Diagram

Note:The following information is given as a hint for the implementation of the device only and shall not be

regarded as a description or warranty of a certain functionality, condition or quality of the device.

Supply

Regulated Output Voltage

I

Q

RO/WO

RADJ

Load

e . g.

Micro

Controller

XC22xx

D_I1

Current

Limitation

Reset

EN

D

C

I1

C_Q

I 2

I2

R₁

1 µF

100nF

< 45V

47µF

Enable

Bandgap

Reference

WI

Temperature

Shutdown

R₂

Watchdog

GND

e.g. Ignition

Figure 13 Application Diagram

Note:This is a very simplified example of an application circuit. The function must be verified in the real application.

6.2

Selection of External Components

6.2.1

Input Pin

The typical input circuitry for a linear voltage regulator is shown in the application diagram above.

A ceramic capacitor at the input, in the range of 100 nF to 470 nF, is recommended to filter out the high frequency

disturbances imposed by the line e.g. ISO pulses 3a/b. This capacitor must be placed very close to the input pin

of the linear voltage regulator on the PCB.

An aluminum electrolytic capacitor in the range of 10 µF to 470 µF is recommended as an input buffer to smooth

out high energy pulses, such as ISO pulse 2a. This capacitor should be placed close to the input pin of the linear

voltage regulator on the PCB.

An overvoltage suppressor diode can be used to further suppress any high voltage beyond the maximum rating

of the linear voltage regulator and protect the device against any damage due to over-voltage.

The external components at the input are not mandatory for the operation of the voltage regulator, but they are

recommended in case of possible external disturbances.

6.2.2

Output Pin

An output capacitor is mandatory for the stability of linear voltage regulators.

The requirement to the output capacitor is given in “Functional Range” on Page 8. The graph “Output

Capacitor Series Resistor ESR(CQ) versus Output Current IQ” on Page 13 shows the stable operation range

of the device.

Data Sheet

31

Rev. 1.0, 2015-12-01

TLS850F0TAV33

Application Information

TLS850F0TAV33 is designed to be also stable with low ESR capacitors. According to the automotive

requirements, ceramic capacitors with X5R or X7R dielectrics are recommended.

The output capacitor should be placed as close as possible to the regulator’s output and GND pins and on the

same side of the PCB as the regulator itself.

In case of rapid transients of input voltage or load current, the capacitance should be dimensioned in accordance

and verified in the real application that the output stability requirements are fulfilled.

6.3

Thermal Considerations

Knowing the input voltage, the output voltage and the load profile of the application, the total power dissipation

can be calculated:

P_D= (V_I- V_Q) × I_Q+ V_I× I_q

(2)

with

•

P_D: continuous power dissipation

V_I: input voltage

V_Q: output voltage

I_Q: output current

I_q: quiescent current

The maximum acceptable thermal resistance R_thJAcan then be calculated:

R_thJA,max= ( T_j,max- T_a) / P_D

(3)

with

•

T

_j,max: maximum allowed junction temperature

T_a: ambient temperature

Based on the above calculation the proper PCB type and the necessary heat sink area can be determined with

reference to the specification in “Thermal Resistance” on Page 9.

Example

Application conditions:

V_I= 13.5 V

V_Q= 3.3 V

I_Q= 175 mA

T_a= 85 °C

Calculation of R_thJA,max

:

P_D= (V_I– V_Q) × I_Q+ V_I× I_q

= (13.5 V – 3.3 V) × 175 mA

= 1.785 W

(V_I× I_qcan be neglected because of very low I_q)

R_thJA,max= (T_j,max– T_a) / P_D

= (150 °C – 85 °C) / 1.785 W = 36.41 K/W

Data Sheet

32

Rev. 1.0, 2015-12-01

TLS850F0TAV33

Application Information

As a result, the PCB design must ensure a thermal resistance R_thJAlower than 36.41 K/W. According to “Thermal

Resistance” on Page 9, at least 600 mm²heatsink area is needed on the FR4 1s0p PCB, or the FR4 2s2p board

can be used to ensure a proper cooling for the TLS850F0TAV33 in package.

6.4

Reverse Polarity Protection

TLS850F0TAV33 is not self protected against reverse polarity faults and must be protected by external

components against negative supply voltage. An external reverse polarity diode is needed. The absolute

maximum ratings of the device as specified in “Absolute Maximum Ratings” on Page 7 must be kept.

6.5

Further Application Information

•

For further information you may contact http://www.infineon.com/

Data Sheet

33

Rev. 1.0, 2015-12-01

TLS850F0TAV33

Package Outlines

7

Package Outlines

4.4

±0.1

±0.2

1.27

0.05

10

0...0.3

8.5¹⁾

A

B

2.4

0.1

0...0.15

±0.1

7x 0.6

1.27

6x

8° MAX.

M

0.25

A B

0.1

B

1) Typical

Metal surface min. X = 7.25, Y = 6.9

All metal surfaces tin plated, except area of cut.

PG-TO263-7

Figure 14 PG-TO263-7

Green Product (RoHS compliant)

To meet the world-wide customer requirements for environmentally friendly products and to be compliant with

government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e

Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).

For further information on alternative packages, please visit our website:

http://www.infineon.com/packages.

Dimensions in mm

Data Sheet

34

Rev. 1.0, 2015-12-01

TLS850F0TAV33

Revision History

8

Revision History

Revision

Date

Changes

Data Sheet - Initial version

1.0

2015-12-01

Data Sheet

35

Rev. 1.0, 2015-12-01

Trademarks of Infineon Technologies AG

AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, CoolMOS™, CoolSET™, CORECONTROL™, CROSSAVE™, DAVE™, DI-POL™, EasyPIM™, EconoBRIDGE™,

EconoDUAL™, EconoPIM™, EconoPACK™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™, ISOFACE™, IsoPACK™, LITIX™, MIPAQ™,

ModSTACK™, my-d™, NovalithIC™, OptiMOS™, ORIGA™, POWERCODE™, PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™,

ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SmartLEWIS™, SPOC™, SOLID FLASH™, TEMPFET™, thinQ!™, TRENCHSTOP™, TriCore™.

Other Trademarks

Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™, PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited,

UK. AUTOSAR™ is licensed by AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™, FirstGPS™ of

Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG. FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay

Consortium. HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data Association

Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc.

MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA

MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of OmniVision Technologies, Inc. Openwave™ Openwave

Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™

of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc.

TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas

Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited.

Last Trademarks Update 2011-11-11

www.infineon.com

Edition 2015-12-01

Published by

Infineon Technologies AG

81726 Munich, Germany

Legal Disclaimer

The information given in this document shall in

no event be regarded as

Warnings

Due to technical requirements, components

may contain dangerous substances. For

information on the types in question, please

contact the nearest Infineon Technologies

Office. Infineon Technologies components may

be used in life-support devices or systems only

with the express written approval of Infineon

Technologies, if a failure of such components

can reasonably be expected to cause the failure

of that life-support device or system or to affect

the safety or effectiveness of that device or

system. Life support devices or systems are

intended to be implanted in the human body or

to support and/or maintain and sustain and/or

protect human life. If they fail, it is reasonable to

assume that the health of the user or other

persons may be endangered.

a guarantee of

conditions or characteristics. With respect to any

examples or hints given herein, any typical

values stated herein and/or any information

regarding the application of the device, Infineon

Technologies hereby disclaims any and all

warranties and liabilities of any kind, including

without limitation, warranties of non-

infringement of intellectual property rights of

any third party.

Do you have a question about any

aspect of this document?

Email: erratum@infineon.com

Information

For further information on technology, delivery

terms and conditions and prices, please contact

the nearest Infineon Technologies Office

(www.infineon.com).


型号：	TLS850F0TAV33ATMA1
厂家：	Infineon
描述：	Fixed Positive LDO Regulator, 3.3V, 0.43V Dropout, PSSO7, GREEN, PLASTIC, TO-263, 7 PIN
文件：	总36页 (文件大小：1438K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TLS850F0TAV33ATMA1 [INFINEON]

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