TLS710B0_15 [INFINEON]

Low Dropout Linear Voltage Regulator;


型号：	TLS710B0_15
厂家：	Infineon
描述：	Low Dropout Linear Voltage Regulator
文件：	总20页 (文件大小：1894K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TLS710B0

Low Dropout Linear Voltage Regulator

TLS710B0EJV50

Data Sheet

Rev. 1.0, 2015-03-12

Automotive Power

Low Dropout Linear Voltage Regulator

TLS710B0

Overview

Features

•

Wide Input Voltage Range from 4.0 V to 40 V

Output Voltage 5 V

Output Voltage Precision ±2 %

Output Current up to 100 mA

Low Current Consumption of 40 µA

Very Low Dropout Voltage of typ. 250 mV at 100 mA Output Current

Stable with Small Output Capacitor of 1 µF

Enable

PG-DSO-8 EP

Overtemperature Shutdown

Output Current Limitation

Wide Temperature Range from -40 °C up to 150 °C

Green Product (RoHS compliant)

AEC Qualified

Description

The TLS710B0 is a low dropout linear voltage regulator for load current up to 100 mA. An input voltage of up to

40 V is regulated to V_Q,nom= 5 V with ±2 % precision.

The TLS710B0, with a typical quiescent current of 40 µA, is the ideal solution for systems requiring very low

operating current, such as those permanently connected to the battery.

It features a very low dropout voltage of 250 mV, when the output current is less than 100 mA. In addition, the

dropout region begins at input voltages of 4.0 V (extended operating range). This makes the TLS710B0 suitable

to supply automotive systems with start-stop requirements.

The device can be switched on and off by the Enable feature as described on Chapter “Enable” on Page 13.

In addition, the TLS710B0’s new fast regulation concept requires only a single, 1 µF output capacitor to maintain

stable regulation.

The device is designed for the harsh environment of automotive applications. Therefore standard features like

output current limitation and overtemperature shutdown are implemented and protect the device against failures

like output short circuit to GND, over-current and over-temperature. The TLS710B0 can be also used in all other

applications requiring a stabilized 5 V supply voltage.

Type

Package

Marking

TLS710B0EJV50

PG-DSO-8 EP

710B0V50

Data Sheet

Rev. 1.0, 2015-03-12

TLS710B0

Block Diagram

Current

Limitation

Enable

Bandgap

Reference

Temperature

Shutdown

GND

Figure 1

Block Diagram TLS710B0EJV50

Data Sheet

Rev. 1.0, 2015-03-12

TLS710B0

Pin Configuration

3.1

Pin Assignment PG-DSO-8 EP

n.c.

GND

n.c.

Figure 2

Pin Configuration

3.2

Pin Definitions and Functions PG-DSO-8 EP

Symbol

Function

Input

For compensating line influences, a capacitor to GND close to the IC terminals is

recommended.

Enable (integrated pull-down resistor)

Enable the IC with high level input signal.

Disable the IC with low level input signal.

GND

Ground

4, 5, 6, n.c.

Not connected

Leave open or connect to GND.

Output

Block to GND with a capacitor close to the IC terminals, respecting the values given

for its capacitance C_Qand ESR in the table “Functional Range” on Page 6.

Pad

–

Exposed Pad

Connect to heatsink area.

Connect with GND on PCB.

Data Sheet

Rev. 1.0, 2015-03-12

TLS710B0

General Product Characteristics

4.1

Absolute Maximum Ratings

Table 1

Absolute Maximum Ratings¹⁾

T_j= -40 °C to +150 °C; all voltages with respect to ground (unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note /

Test Condition

Number

Min.

-0.3

Max.

Input I, Enable EN

Voltage

V_I, V_EN

–

P_4.1.1

P_4.1.2

Output Q

Voltage

V_Q

–

Temperature

Junction Temperature

Storage Temperature

ESD Absorption

ESD Susceptibility to GND

T_j

-40

-55

–

150

°C

–

P_4.1.3

P_4.1.4

T_stg

V_ESD

-2

–

HBM²⁾

CDM³⁾

P_4.1.5

P_4.1.6

-500

500

1) Not subject to production test, specified by design.

2) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS001 (1.5 kΩ, 100 pF)

3) ESD susceptibility, Charged Device Model “CDM” according JEDEC JESD22-C101

Notes

1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the

data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not

designed for continuous repetitive operation.

Data Sheet

Rev. 1.0, 2015-03-12

TLS710B0

General Product Characteristics

4.2

Functional Range

Table 2

Functional Range

Parameter

Symbol

Values

Typ. Max.

Unit

Note /

Test Condition

Number

Min.

Input Voltage Range for Normal

Operation

V_I

_Q,nom+ V_dr

–

P_4.2.1

–

Extended Input Voltage Range

Enable Voltage Range

V_I,ext

V_EN

4.0

–

P_4.2.2

P_4.2.3

P_4.2.4

–

Output Capacitor’s Requirements C_Q

µF

–

for Stability

Output Capacitor’s ESR

Junction Temperature

ESR(C_Q)

T_i

–

Ω

–

P_4.2.5

P_4.2.6

-40

150

°C

–

1) When V_Iis between V_I,ext.minand V_Q,nom+ V_dr, V_Q= V_I- V_dr. When V_Iis below V_I,ext,min, V_Qcan drop down to 0 V.

2) The minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30%

3) Relevant ESR value at f = 10 kHz

Note:Within the functional range the IC operates as described in the circuit description. The electrical

characteristics are specified within the conditions given in the related electrical characteristics table.

4.3

Thermal Resistance

Note:This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go

to www.jedec.org.

Table 3

Thermal Resistance

Symbol

Parameter

Values

Typ.

Unit

Note / Test Condition Number

Min.

Max.

Package Version PG-DSO-8 EP

Junction to Case¹⁾

Junction to Ambient

R_thJC

–

K/W

–

P_4.3.1

P_4.3.2

P_4.3.3

R_thJA

2s2p board²⁾

153

1s0p board, footprint

only³⁾

Junction to Ambient

R_thJA

–

K/W

1s0p board, 300 mm²

P_4.3.4

P_4.3.5

heatsink area on PCB³⁾

1s0p board, 600 mm²

heatsink area on PCB³⁾

1) Not subject to production test, specified by design

2) Specified R_thJAvalue is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product

(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).

Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.

3) Specified R_thJAvalue is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product

(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm³board with 1 copper layer (1 x 70µm Cu).

Data Sheet

Rev. 1.0, 2015-03-12

TLS710B0

Block Description and Electrical Characteristics

5.1

Voltage Regulation

The output voltage V_Qis divided by a resistor network. This fractional voltage is compared to an internal voltage

reference and drives the pass transistor accordingly.

The control loop stability depends on the output capacitor C_Q, the load current, the chip temperature and the

internal circuit design. To ensure stable operation, the output capacitor’s capacitance and its equivalent series

resistor ESR requirements given in Table 2 “Functional Range” on Page 6 must be maintained. For details see

the typical performance graph “Output Capacitor Series Resistor ESR(C_Q) versus Output Current I_Q” on

Page 10. Since the output capacitor is used to buffer load steps, it should be sized according to the application’s

needs.

An input capacitor C_Iis not required for stability, but is recommended to compensate line fluctuations. An

additional reverse polarity protection diode and a combination of several capacitors for filtering should be used, in

case the input is connected directly to the battery line. Connect the capacitors close to the regulator terminals.

Whenever the load current exceeds the specified limit, e.g. in case of a short circuit, the output current is limited

and the output voltage decreases.

The overtemperature shutdown circuit prevents the IC from immediate destruction under fault conditions (e.g.

output continuously short-circuited) by switching off the power stage. After the chip has cooled, the regulator

restarts. This oscillatory thermal behaviour causes the junction temperature to exceed the maximum rating of

150°C and can significantly reduce the IC’s lifetime.

Regulated

Output Voltage

Supply

I_Q

I_I

Current

Limitation

Enable

LOAD

Bandgap

Reference

C_I

V_I

V_Q

ESR

Temperature

Shutdown

C_Q

GND

Figure 3

Block Diagram Voltage Regulation

Data Sheet

Rev. 1.0, 2015-03-12

TLS710B0

Block Description and Electrical Characteristics

Table 4

Electrical Characteristics Voltage Regulator

V_I= 13.5 V; T_j= -40 °C to +150 °C; all voltages with respect to ground (unless otherwise specified).

Typical values are given at T_j= 25 °C, V_I= 13.5 V.

Parameter

Symbol

Values

Unit Note / Test Condition Number

Min. Typ. Max.

Output Voltage Precision

V_Q

4.9

5.0

5.1

0.05 mA < I_Q<

100 mA

P_5.1.1

6 V < V_I< 28 V

Output Voltage Precision

Output Current Limitation

V_Q

4.9

101

–

5.0

250

5.1

350

500

–

0.05 mA < I_Q< 50 mA P_5.1.2

6 V < V_I< 40 V

I_Q,max

°C

0 V < V_Q< 4.8 V

4 V < V_I< 28 V

P_5.1.7

Load Regulation

steady-state

|ΔV_Q,load

|ΔV_Q,line

V_dr

I_Q= 0.05 mA to 100 mA P_5.1.9

V_I= 6 V

Line Regulation

steady-state

Dropout Voltage¹⁾

V_dr= V_I- V_Q

Power Supply Ripple Rejection²⁾

–

V_I= 8 V to 32 V

I_Q= 5 mA

P_5.1.10

P_5.1.11

P_5.1.12

P_5.1.13

P_5.1.14

–

200

–

I_Q= 100 mA

PSRR

T_j,sd

–

_ripple= 100 Hz

_ripple= 0.5 Vpp

Overtemperature Shutdown

Threshold

151

–

200

–

T_jincreasing²⁾

Overtemperature Shutdown

Threshold Hysteresis

T_j,sdh

T_jdecreasing²⁾

1) Measured when the output voltage V_Qhas dropped 100 mV from the nominal value obtained at V_I= 13.5V

2) Not subject to production test, specified by design

Data Sheet

Rev. 1.0, 2015-03-12

TLS710B0

Block Description and Electrical Characteristics

5.2

Typical Performance Characteristics Voltage Regulator

Typical Performance Characteristics

Output Voltage V_Qversus

Junction Temperature T_j

Output Current I_Qversus

Input Voltage V_I

400

T_j= −40 °C

T_j= 25 °C

5.15

5.1

350

T_j= 150 °C

300

5.05

250

200

150

100

4.95

4.9

4.85

V = 13.5 V

= 50 mA

4.8

100

150

V_I[V]

T [°C]

Dropout Voltage V_drversus

Junction Temperature T_j

Dropout Voltage V_drversus

Output Current I_Q

600

I_Q= 10 mA

T_j= −40 °C

I_Q= 50 mA

T_j= 25 °C

I_Q= 100 mA

500

400

300

200

100

500

T_j= 150 °C

400

300

200

100

150

100

T_j[°C]

I_Q[mA]

Data Sheet

Rev. 1.0, 2015-03-12

TLS710B0

Block Description and Electrical Characteristics

Output Voltage V_Qversus

Input Voltage V_I

Power Supply Ripple Rejection PSRR versus

Ripple Frequency f_r

100

= 10 mA

= 1 μF

V = 13.5 V

T = 25 °C

= 50 mA

= 0.5 Vpp

ripple

T = 25 °C

10⁻²

10⁻¹

10⁰

10¹

10²

10³

V [V]

f [kHz]

Output Capacitor Series Resistor ESR(C_Q) versus

Output Current I_Q

10²

Unstable Region

10¹

10⁰

Stable Region

10⁻¹

= 1 μF

V = 3...28 V

10⁻²

100

[mA]

Data Sheet

Rev. 1.0, 2015-03-12

TLS710B0

Block Description and Electrical Characteristics

5.3

Current Consumption

Table 5

Electrical Characteristics Current Consumption

V_I= 13.5 V; T_j= -40 °C to +150 °C (unless otherwise specified).

Typical values are given at T_j= 25 °C, V_I= 13.5 V.

Parameter

Symbol

Values

Typ.

1.5

Unit

Note / Test Condition

Number

Min.

Max.

Current Consumption

I_q= I_I

I_q,off

I_q

–

µA

_EN≤ 0.4 V

P_5.3.1

T_j< 105 °C

Current Consumption

–

0.05 mA < I_Q< 100 mA P_5.3.2

I_q= I_I- I_Q

Data Sheet

Rev. 1.0, 2015-03-12

TLS710B0

Block Description and Electrical Characteristics

5.4

Typical Performance Characteristics Current Consumption

Typical Performance Characteristics

Current Consumption I_qversus

Output Current I_Q

Current Consumption I_qversus

Input Voltage V_I

T = −40 °C

T = 25 °C

T = 150 °C

V = 13.5 V

= 50 μA

100

[mA]

V [V]

Current Consumption I_qversus

Junction Temperature T_j

Current Consumption in OFF mode I_q,offversus

Junction Temperature T_j

V_I= 13.5 V

V_EN≤ 0.4 V

3.5

2.5

1.5

0.5

V_I= 13.5 V

I_Q= 50 μA

T_j[°C]

100

150

T_j[°C]

Data Sheet

Rev. 1.0, 2015-03-12

TLS710B0

Block Description and Electrical Characteristics

5.5

Enable

The TLS710B0 can be switched on and off by the Enable feature. Connect a HIGH level as specified below (e.g.

the battery voltage) to pin EN to enable the device; connect a LOW level as specified below (e.g. GND) to switch

it off. The Enable function has a build-in hysteresis to avoid toggling between ON/OFF state, if signals with slow

slopes are appiled to the input.

Table 6

Electrical Characteristics Enable

V_I= 13.5 V; T_j= -40 °C to +150 °C; all voltages with respect to ground (unless otherwise specified).

Typical values are given at T_j= 25 °C, V_I= 13.5 V.

Parameter

Symbol

Values

Unit

Note / Test Condition

Number

Min. Typ. Max.

Enable Voltage High Level

Enable Voltage Low Level

Enable Threshold Hysteresis

V_EN,H

V_EN,L

V_EN,Hy

I_EN,H

–

V_Qsettled

V_Q≤ 0.1 V

–

P_5.5.1

P_5.5.2

P_5.5.3

P_5.5.4

–

0.8

–

µA

Enable Input Current

Low Level

5.5

–

_EN= 5 V

Enable Input Current

High Level

I_EN,H

–

µA

_EN< 18 V

P_5.5.5

P_5.5.6

Enable internal pull-down resistor R_EN

0.9

1.5

2.6

MΩ

Data Sheet

Rev. 1.0, 2015-03-12

TLS710B0

Block Description and Electrical Characteristics

5.6

Typical Performance Characteristics Enable

Typical Performance Characteristics

Enabled Input Current I_ENversus

Enabled Input Voltage V_EN

T = −40 °C

T = 25 °C

T = 150 °C

[V]

Data Sheet

Rev. 1.0, 2015-03-12

TLS710B0

Application Information

6.1

Application Diagram

Supply

Regulated Output Voltage

Load

e. g.

Micro

D_I1

Current

Limitation

Controller

XC22xx

C_Q

D_I2

C_I2

C_I1

1µF

(ESR <5ꢀ)

100nF

<45V

10µF

Enable

Bandgap

Reference

GND

Temperature

Shutdown

GND

Figure 4

Application Diagram

6.2

Selection of External Components

6.2.1

Input Pin

The typical input circuitry for a linear voltage regulator is shown in the application diagram above.

A ceramic capacitor at the input, in the range of 100 nF to 470 nF, is recommended to filter out the high frequency

disturbances imposed by the line e.g. ISO pulses 3a/b. This capacitor must be placed very close to the input pin

of the linear voltage regulator on the PCB.

An aluminum electrolytic capacitor in the range of 10 µF to 470 µF is recommended as an input buffer to smooth

out high energy pulses, such as ISO pulse 2a. This capacitor should be placed close to the input pin of the linear

voltage regulator on the PCB.

An overvoltage suppressor diode can be used to further suppress any high voltage beyond the maximum rating

of the linear voltage regulator and protect the device against any damage due to over-voltage above 45 V.

The external components at the input are not mandatory for the operation of the voltage regulator, but they are

recommended in order to protect the voltage regulator against external disturbances and damages.

6.2.2

Output Pin

An output capacitor is mandatory for the stability of linear voltage regulators.

The requirement to the output capacitor is given in “Functional Range” on Page 6. The graph “Output

Capacitor Series Resistor ESR(C_Q) versus Output Current I_Q” on Page 10 shows the stable operation range

of the device.

TLS710B0 is designed to be stable with extremely low ESR capacitors. According to the automotive requirements,

ceramic capacitors with X5R or X7R dielectrics are recommended.

The output capacitor should be placed as close as possible to the regulator’s output and GND pins and on the

same side of the PCB as the regulator itself.

Data Sheet

Rev. 1.0, 2015-03-12

TLS710B0

Application Information

In case of rapid transients of input voltage or load current, the capacitance should be dimensioned in accordance

and verified in the real application that the output stability requirements are fulfilled.

6.3

Thermal Considerations

Knowing the input voltage, the output voltage and the load profile of the application, the total power dissipation

can be calculated:

P_D= (V_I- V_Q) × I_Q+ V_I× I_q

(1)

with

•

P_D: continuous power dissipation

V_I: input voltage

V_Q: output voltage

I_Q: output current

I_q: quiescent current

The maximum acceptable thermal resistance R_thJAcan then be calculated:

R_thJA,max= ( T_j,max- T_a) / P_D

(2)

with

•

_j,max: maximum allowed junction temperature

T_a: ambient temperature

Based on the above calculation the proper PCB type and the necessary heat sink area can be determined with

reference to the specification in “Thermal Resistance” on Page 6.

Example

Application conditions:

V_I= 13.5 V

V_Q= 5 V

I_Q= 100 mA

T_a= 85 °C

Calculation of R_thJA,max

P_D= (V_I– V_Q) × I_Q+ V_I× I_q

= (13.5 V – 5 V) × 100 mA

= 0.85 W

(V_I× I_qcan be neglected because of very low I_q)

R_thJA,max= (T_j,max– T_a) / P_D

= (150 °C – 85 °C) / 0.85 W = 76.47 K/W

As a result, the PCB design must ensure a thermal resistance R_thJAlower than 76.47 K/W. According to “Thermal

Resistance” on Page 6, at least 300 mm²heatsink area is needed on the FR4 1s0p PCB, or the FR4 2s2p board

can be used.

Data Sheet

Rev. 1.0, 2015-03-12

TLS710B0

Application Information

6.4

Reverse Polarity Protection

TLS710B0 is not self protected against reverse polarity faults and must be protected by external components

against negative supply voltage. An external reverse polarity diode is needed. The absolute maximum ratings of

the device as specified in “Absolute Maximum Ratings” on Page 5 must be kept.

6.5

Further Application Information

•

For further information you may contact http://www.infineon.com/

Data Sheet

Rev. 1.0, 2015-03-12

TLS710B0

Package Outlines

0.35 x 45°

±0.1

3.9

0.1 C D 2x

+0.06

0.19

0.08

Seating Plane

0.64_±0.25

0.2

1.27

±0.09

0.41

±0.2

D 8x

0.2

C A-B D 8x

Bottom View

±0.2

0.1 C A-B 2x

±0.1

4.9

Index Marking

1) Does not include plastic or metal protrusion of 0.15 max. per side

2) Dambar protrusion shall be maximum 0.1 mm total in excess of lead width

3) JEDEC reference MS-012 variation BA

Figure 5

PG-DSO-8 EP

Data Sheet

Rev. 1.0, 2015-03-12

TLS710B0

Revision History

Revision

Date

Changes

1.0

2015-03-12

Data Sheet - Initial Version

Data Sheet

Rev. 1.0, 2015-03-12

Edition 2015-03-12

Published by

Infineon Technologies AG

81726 Munich, Germany

Legal Disclaimer

The information given in this document shall in no event be regarded as a guarantee of conditions or

characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any

information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties

and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights

of any third party.

Information

For further information on technology, delivery terms and conditions and prices, please contact the nearest

Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements, components may contain dangerous substances. For information on the types in

question, please contact the nearest Infineon Technologies Office.

Infineon Technologies components may be used in life-support devices or systems only with the express written

approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure

of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support

devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain

and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may

be endangered.

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