TLI5012B E1000_技术文档

Angle Sensor

GMR-Based Angle Sensor

TLI5012B E1000

Data Sheet

Rev. 1.1, 2015-09

Sense & Control

TLI5012B E1000

Data Sheet

2

Rev. 1.1, 2015-09

TLI5012B E1000

Revision History

Page or Item

Subjects (major changes since previous revision)

Rev. 1.1, 2015-09

Chapter 1.4

Disclaimer modified

Trademarks of Infineon Technologies AG

AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, EconoPACK™, CoolMOS™, CoolSET™,

CORECONTROL™, CROSSAVE™, DAVE™, DI-POL™, EasyPIM™, EconoBRIDGE™, EconoDUAL™,

EconoPIM™, EconoPACK™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™,

ISOFACE™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OptiMOS™, ORIGA™,

POWERCODE™; PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™,

ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SmartLEWIS™, SOLID FLASH™, TEMPFET™,

thinQ!™, TRENCHSTOP™, TriCore™.

Other Trademarks

Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™,

PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR

development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™,

FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG.

FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of

Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data

Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of

MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics

Corporation. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA

MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of

OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF

Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™

of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co.

TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™

of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas

Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes

Zetex Limited.

Last Trademarks Update 2011-11-11

Data Sheet

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Rev. 1.1, 2015-09

TLI5012B E1000

Table of Contents

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1

Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.1

1.2

1.3

1.4

2

2.1

2.2

2.2.1

2.2.2

2.2.3

2.2.4

2.2.5

2.3

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Internal Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

SD-ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Digital Signal Processing Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Sensing Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.4

2.5

3

Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4

4.1

4.2

4.3

Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Input/Output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

GMR Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Angle Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Clock Supply (CLK Timing Definition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

External clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Incremental Interface (IIF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Synchronous Serial Communication (SSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

SSC Timing Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

SSC Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Supply Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Internal Supply Voltage Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.3.1

4.3.2

4.3.3

4.3.4

4.3.5

4.3.6

4.3.6.1

4.4

4.4.1

4.4.2

4.4.2.1

4.4.2.2

4.4.3

4.4.3.1

4.4.3.2

4.4.3.3

4.4.3.4

V

_DDOvervoltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

GND - Off Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

_DD- Off Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

V

5

Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.1

5.2

5.3

5.4

Data Sheet

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TLI5012B E1000

Table of Contents

5.5

Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Data Sheet

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Rev. 1.1, 2015-09

TLI5012B E1000

List of Figures

Figure 1-1 PG-DSO-8 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 2-1 TLI5012B E1000 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 2-2 Sensitive bridges of the GMR sensor (not to scale) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 2-3 Ideal output of the GMR sensor bridges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 2-4 Pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 3-1 Application circuit for TLI5012B E1000 with IIF interface and SSC (using internal CLK). . . . . . . . 14

Figure 3-2 SSC configuration in sensor-slave mode with push-pull outputs (high-speed application) . . . . . . 15

Figure 3-3 SSC configuration in sensor-slave mode and open-drain (bus systems). . . . . . . . . . . . . . . . . . . . 15

Figure 4-1 Allowed magnetic field range as function of junction temperature.. . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 4-2 Offset and amplitude definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 4-3 Additional angle error for temperature changes above 5 Kelvin within 1.5 revolutions . . . . . . . . . 21

Figure 4-4 Signal path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 4-5 Delay of sensor output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 4-6 External CLK timing definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 4-7 Incremental interface with A/B mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 4-8 Incremental interface with Step/Direction mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 4-9 SSC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 4-10 SSC data transfer (data-read example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 4-11 SSC data transfer (data-write example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 4-12 SSC bit ordering (read example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 4-13 Update of update registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 4-14 Fast CRC polynomial division circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 4-15 Overvoltage comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 4-16 GND - off comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 4-17 V_DD- off comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 5-1 PG-DSO-8 package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 5-2 Position of sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 5-3 Footprint of PG-DSO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 5-4 Tape and Reel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Data Sheet

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Rev. 1.1, 2015-09

TLI5012B E1000

List of Tables

Table 1-1 Derivate Ordering codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 2-1 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 4-1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 4-2 Operating range and parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 4-3 Input voltage and output currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 4-4 Driver strength characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 4-5 Electrical parameters for 4.5 V < V_DD< 5.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 4-6 Electrical parameters for 3.0 V < V_DD< 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 4-7 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 4-8 Basic GMR parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 4-9 Angle performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 4-10 Signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 4-11 Internal clock timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 4-12 External Clock Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 4-13 Incremental Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 4-14 SSC push-pull timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 4-15 SSC open-drain timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 4-16 Structure of the Command Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 4-17 Structure of the Safety Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 4-18 Bit Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 4-19 Test comparator threshold voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 5-1 Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 5-2 Sensor IC placement tolerances in package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Data Sheet

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Rev. 1.1, 2015-09

TLI5012B E1000

Product Description

1

Product Description

Figure 1-1 PG-DSO-8 package

1.1

Overview

The TLI5012B E1000 is a 360° angle sensor that detects the orientation of a magnetic field. This is achieved by

measuring sine and cosine angle components with monolithic integrated Giant Magneto Resistance (iGMR)

elements. These raw signals (sine and cosine) are digitally processed internally to calculate the angle orientation

of the magnetic field (magnet).

The TLI5012B E1000 is a pre-calibrated sensor. The calibration parameters are stored in laser fuses. At start-up

the values of the fuses are written into flip-flops, where these values can be changed by the application-specific

parameters. Further precision of the angle measurement over a wide temperature range and a long lifetime are

improved with the internal autocalibration algorithm.

Data communications are accomplished with a bi-directional Synchronous Serial Communication (SSC) that is

SPI-compatible. The sensor configuration is stored in registers, which are accessible by the SSC interface.

Additionally the TLI5012B E1000 has Incremental Interface (IIF),

Table 1-1 Derivate Ordering codes

Product Type

Marking

Ordering Code

Package

TLI5012B E1000

I12B1000

SP001415550

PG-DSO-8

Data Sheet

8

Rev. 1.1, 2015-09

TLI5012B E1000

Product Description

1.2

Features

The TLI5012B E1000 has the following features and pre-configuration. The configuration can be changed via SSC

interface.

•

Giant Magneto Resistance (GMR)-based principle.

Integrated magnetic field sensing for angle measurement.

360° angle measurement with revolution counter and angle speed measurement.

Max. 1.9° angle error over lifetime and temperature-range with activated auto-calibration

Synchronous Serial Communication (SSC) with 15 bit representation of absolute angle value (0.01° resolution)

Incremental Interface (IIF) with 12 bit resolution of angle value on the output (one count per 0.088° angle step).

Incremental Interface (IIF) in A/B mode with absolut count enabled (provides absolute value at output)

Fast angle update period (42.7µs).

Autocalibration mode 1 enabled.

Prediction disabled.

Hysteresis set to 0.703°.

Bus mode operation of multiple sensors on one line is possible with SSC in open-drain configuration.

Diagnostic functions and status information.

IFA/IFB/IFC pins set to push-pull output.

Bi-directional SSC interface. DATA pin set to push-pull output with 8Mbit/s baud rate (2Mbit/s in open-drain).

IFA/IFB/IFC pins set to strong driver, DATA pin set to strong driver, fast edge.

Voltage spike filter on input pads disabled.

Two separate highly accurate single bit SD-ADC.

RoHS compliant (Pb-free package).

Halogen-free.

1.3

Application Example

The TLI5012B E1000 GMR-based angle sensor is designed for angular position sensing in industrial and

consumer applications such as electrical commutated motor (e.g. BLDC), fans or pumps.

1.4

Disclaimer

The qualification of this product is based on JEDEC JESD47 and may reference existing qualification results of

similar products. Such referring is justified by the structural similarity of the products. The product is not qualified

and manufactured according to the requirements of Infineon Technologies with regard to automotive applications.

Data Sheet

9

Rev. 1.1, 2015-09

TLI5012B E1000

Functional Description

2

Functional Description

2.1

Block Diagram

TLI5012B E1000

V_DD

VRG

VRA

VRD

GND

CSQ

SCK

DATA

IFA

X

GMR

SD-

ADC

Digital

Signal

Processing

Unit

SSC Interface

ISM

CORDIC

CCU

Y

GMR

SD-

ADC

Incremental

Interface

IFB

SD-

ADC

RAM

Temp

IFC

Fuses

Osc

PLL

Figure 2-1 TLI5012B E1000 block diagram

2.2

Functional Block Description

2.2.1

Internal Power Supply

The internal stages of the TLI5012B E1000 are supplied with several voltage regulators:

•

GMR Voltage Regulator, VRG

Analog Voltage Regulator, VRA

Digital Voltage Regulator, VRD (derived from VRA)

These regulators are directly connected to the supply voltage V_DD

.

2.2.2

Oscillator and PLL

The digital clock of the TLI5012B E1000 is given by the Phase-Locked Loop (PLL), which is by default fed by an

internal oscillator. In order to synchronize the TLI5012B E1000 with other ICs in a system, the TLI5012B E1000

Data Sheet

10

Rev. 1.1, 2015-09

TLI5012B E1000

Functional Description

can be configured via SSC interface to use an external clock signal supplied on the IFC pin as source for the PLL,

instead of the internal clock. External clock mode is only available in PWM or SPC interface configuration.

2.2.3

SD-ADC

The Sigma-Delta Analog-Digital-Converters (SD-ADC) transform the analog GMR voltages and temperature

voltage into the digital domain.

2.2.4

Digital Signal Processing Unit

The Digital Signal Processing Unit (DSPU) contains the:

•

Intelligent State Machine (ISM), which does error compensation of offset, offset temperature drift, amplitude

synchronicity and orthogonality of the raw signals from the GMR bridges, and performs additional features

such as auto-calibration, prediction and angle speed calculation

•

COordinate Rotation DIgital Computer (CORDIC), which contains the trigonometric function for angle

calculation

•

Capture Compare Unit (CCU), which is used to generate the PWM and SPC signals

Random Access Memory (RAM), which contains the configuration registers

Laser Fuses, which contain the calibration parameters for the error-compensation and the IC default

configuration, which is loaded into the RAM at startup

2.2.5

Interfaces

Bi-directional communication with the TLI5012B E1000 is enabled by a three-wire SSC interface. In parallel to the

SSC interface, an Incremental Interface (IIF) can be selected, which is available on the IFA, IFB, IFC pins.

2.3

Sensing Principle

The Giant Magneto Resistance (GMR) sensor is implemented using vertical integration. This means that the

GMR-sensitive areas are integrated above the logic part of the TLI5012B E1000 device. These GMR elements

change their resistance depending on the direction of the magnetic field.

Four individual GMR elements are connected to one Wheatstone sensor bridge. These GMR elements sense one

of two components of the applied magnetic field:

•

X component, V_x(cosine) or the

Y component, V_y(sine)

With this full-bridge structure the maximum GMR signal is available and temperature effects cancel out each other.

In Figure 2-2, the arrows in the resistors represent the magnetic direction which is fixed in the reference layer. If

the external magnetic field is parallel to the direction of the Reference Layer, the resistance is minimal. If they are

anti-parallel, resistance is maximal.

The output signal of each bridge is only unambiguous over 180° between two maxima. Therefore two bridges are

oriented orthogonally to each other to measure 360°.

With the trigonometric function ARCTAN2, the true 360° angle value is calculated out of the raw X and Y signals

from the sensor bridges.

Data Sheet

11

Rev. 1.1, 2015-09

TLI5012B E1000

Functional Description

GMR Resistors

V_X

V_Y

0°

S

N

ADC_X+

ADC_X-

GND

ADC_Y+

ADC_Y-

V_DD

90°

Figure 2-2 Sensitive bridges of the GMR sensor (not to scale)

Attention: Due to the rotational placement inaccuracy of the sensor IC in the package, the sensors 0°

position may deviate by up to 3° from the package edge direction indicated in Figure 2-2.

Y Component (SIN)

V_Y

X Component (COS)

V_X

V

V_X(COS)

0°

90°

180°

270°

360°

Angle α

V_Y(SIN)

Figure 2-3 Ideal output of the GMR sensor bridges

Data Sheet

12

Rev. 1.1, 2015-09

TLI5012B E1000

Functional Description

2.4

Pin Configuration

8

7

6

5

Center of Sensitive

Area

1

2

3

4

Figure 2-4 Pin configuration (top view)

2.5

Pin Description

Table 2-1 Pin Description

Pin No.

Symbol

In/Out

Function

1

2

3

4

5

6

7

8

IFC (IIF_IDX)

SCK

O

I

Interface C: IIF Index

SSC Clock

CSQ

I

SSC Chip Select

SSC Data

DATA

I/O

O

-

IFA (IIF_A)

V_DD

Interface A: IIF Phase A

Supply Voltage

Ground

GND

-

IFB (IIF_B)

O

Interface B: IIF Phase B

Data Sheet

13

Rev. 1.1, 2015-09

TLI5012B E1000

Application Circuits

3

Application Circuits

The application circuits in this chapter show the various communication possibilities of the TLI5012B E1000. The

pin output mode configuration is device-specific and it can be either push-pull or open-drain. The bit IFAB_OD

(register IFAB, 0D_H) indicates the output mode for the IFA, IFB and IFC pins. The SSC pins are by default push-

pull (bit SSC_OD, register MOD_3, 09_H).

Figure 3-1 shows a basic block diagram of a TLI5012B E1000 with Incremental Interface and SSC configuration.

The derivate TLI5012B E1000 is by default configured with push-pull IFA (IIF_A), IFB (IIF_ B) and IFC (IIF_IDX)

pins.

V_DD(3.0 – 5.5V)

TLI5012B E1000

100nF

VRG

VRA

VRD

*)

CSQ

X

GMR

SD-

ADC

Digital

Signal

Processing

Unit

*)

SCK

SSC

SSC Interface

**)

DATA

ISM

CORDIC

CCU

Y

GMR

SD-

ADC

IFA (IIF_A)

IFB (IIF_B)

Incremental

Interface

IIF

SD-

ADC

RAM

Temp

IFC (IIF_IDX)

GND

Fuses

Osc

PLL

*) recommended, e.g. 100Ω

**) recommended, e.g. 470Ω

Figure 3-1 Application circuit for TLI5012B E1000 with IIF interface and SSC (using internal CLK)

In case that the IFA, IFB and IFC pins are configurated via the SSC interface as open-drain pins, three resistors

(one for each line) between output line and V_DDwould be recommended (e.g. 2.2kΩ).

Data Sheet

14

Rev. 1.1, 2015-09

TLI5012B E1000

Application Circuits

Synchronous Serial Communication (SSC) configuration

In Figure 3-1 the SSC interface has the default push-pull configuration (see details in Figure 3-2). Series resistors

on the DATA, SCK (serial clock signal) and CSQ (chip select) lines are recommended to limit the current in the

erroneous case that either the sensor pushes high and the microcontroller pulls low at the same time or vice versa.

The resistors in the SCK and CSQ lines are only necessary in case of disturbances or noise.

(SSC Slave) TLI5012B E1000

µC (SSC Master)

**)

MTSR

DATA

Shift Reg.

EN

MRST

SCK

*)

SCK

Clock Gen.

*)

CSQ

*) optional, e.g. 100Ω

**) optional, e.g. 470Ω

Figure 3-2 SSC configuration in sensor-slave mode with push-pull outputs (high-speed application)

It is also possible to use an open-drain setup for the DATA, SCK and CSQ lines. This setup is designed to

communicate with a microcontroller in a bus system, together with other SSC slaves (e.g. two TLI5012B E1000

devices for redundancy reasons). This mode can be activated using the bit SSC_OD.

The open-drain configuration can be seen in Figure 3-3. Series resistors on the DATA, SCK, and CSQ lines are

recommended to limit the current in case either the microcontroller or the sensor are accidentally switched to push-

pull. A pull-up resistor of typ. 1 kΩ is required on the DATA line.

(SSC Slave) TLI5012B E1000

µC (SSC Master)

typ. 1kΩ

*)

MTSR

DATA

Shift Reg.

MRST

SCK

*)

SCK

Clock Gen.

*)

CSQ

*) optional, e.g. 100Ω

Figure 3-3 SSC configuration in sensor-slave mode and open-drain (bus systems)

Data Sheet

15

Rev. 1.1, 2015-09

TLI5012B E1000

Specification

4

Specification

4.1

Absolute Maximum Ratings

Table 4-1 Absolute maximum ratings

Parameter Symbol

Values

Typ.

Unit Note / Test Condition

Min.

-0.5

Max.

6.5 V

Voltage on V_DDpin with respect to V_DD

ground (V_SS)

Max 40 h/Lifetime

Voltage on any pin with respect to V_IN

ground (V_SS)

-0.5

-40

6.5 V

V

_DD+ V

0.5

Junction temperature

T_J

B

125 °C

Magnetic field induction

200 mT Max. 5 min @ T_A= 25°C

150 mT Max. 5 h @ T_A= 25°C

Storage temperature

T_ST

-40

125 °C

Without magnetic field

Attention: Stresses above the max. values listed here may cause permanent damage to the device.

Exposure to absolute maximum rating conditions for extended periods may affect device

reliability. Maximum ratings are absolute ratings; exceeding only one of these values may

cause irreversible damage to the device.

4.2

Operating Range

The following operating conditions must not be exceeded in order to ensure correct operation of the TLI5012B

E1000. All parameters specified in the following sections refer to these operating conditions, unless otherwise

noted. Table 4-2 is valid for -40°C < T_J< 125°C unless otherwise noted.

Table 4-2 Operating range and parameters

Parameter

Symbol

Values

Typ.

5.0

Unit Note / Test Condition

Min.

3.0

Max.

5.5 V

1)

Supply voltage

Supply current

V_DD

I_DD

14

16 mA

Magnetic induction at T_J=

25°C²⁾³⁾

B_XY

30

25

50 mT -40°C < T_J< 125°C

60 mT -40°C < T_J< 100°C

70 mT -40°C < T_J< 85°C

30 mT Additional angle error of 0.1°

Extended magnetic induction

range at T_J= 25°C²⁾³⁾

B_XY

Angle range

POR level

Ang

0

360 °

V_POR

V_PORhy

2.0

2.9 V

mV

Power-on reset

POR hysteresis

30

Data Sheet

16

Rev. 1.1, 2015-09

TLI5012B E1000

Specification

Table 4-2 Operating range (cont’d)and parameters

Parameter

Symbol

Values

Typ.

5

Unit Note / Test Condition

Min.

Max.

Power-on time⁴⁾

Fast Reset time⁵⁾

t_Pon

7 ms V_DD> V_DDmin;

t_Rfast

0.5 ms Fast reset is triggered by

disabling startup BIST

(S_BIST = 0), then enabling

chip reset (AS_RST = 1)

1) Directly blocked with 100-nF ceramic capacitor

2) Values refer to a homogeneous magnetic field (B_XY) without vertical magnetic induction (B_Z= 0mT).

3) See Figure 4-1

4) During “Power-on time,” write access is not permitted (except for the switch to External Clock which requires a readout as

a confirmation that external clock is selected)

5) Not subject to production test - verified by design/characterization

The field strength of a magnet can be selected within the colored area of Figure 4-1. By limitation of the junction

temperature, a higher magnetic field can be applied. In case of a maximum temperature T_J= 100°C, a magnet

with up to 60mT at T_J= 25°C is allowed.

It is also possible to widen the magnetic field range for higher temperatures. In that case, additional angle errors

have to be considered.

100

90

80

70

60

65

60

50

54

50

44

40

30

26

+0.1° angle error @ 25mT

-40

25

85 100

125

Temperature (°C)

Figure 4-1 Allowed magnetic field range as function of junction temperature.

Data Sheet

17

Rev. 1.1, 2015-09

TLI5012B E1000

Specification

4.3

Characteristics

4.3.1

Input/Output characteristics

The indicated parameters apply to the full operating range, unless otherwise specified. The typical values

correspond to a supply voltage V_DD= 5.0 V and 25 °C, unless individually specified. All other values correspond

to -40 °C < T_J< 125°C.

Within the register MOD_3, the driver strength and the slope for push-pull communication can be varied depending

on the sensor output. The driver strength is specified in Table 4-3 and the slope fall and rise time in Table 4-4.

Table 4-3 Input voltage and output currents

Parameter

Symbol

Values

Min. Typ.

Unit Note / Test Condition

Max.

5.5 V

_DD+ 0.3 V

-25 mA PAD_DRV =’0x’, sink current¹⁾²⁾

Input voltage

V_IN

-0.3

V

Output current (DATA-Pad)

I_Q

-5 mA PAD_DRV =’10’, sink current¹⁾²⁾

-0.4 mA PAD_DRV =’11’, sink current¹⁾²⁾

-15 mA PAD_DRV =’0x’, sink current¹⁾²⁾

-5 mA PAD_DRV =’1x’, sink current¹⁾²⁾

Output current (IFA / IFB / IFC - I_Q

Pad)

1) Max. current to GND over open-drain output

2) At V_DD= 5 V

Table 4-4 Driver strength characteristic

Parameter

Symbol

Values

Typ.

Unit

Note / Test Condition

Min.

Max.

Output rise/fall time

t_fall, t_rise

8 ns

DATA, 50 pF,

PAD_DRV=’00’¹⁾²⁾

28 ns

45 ns

DATA, 50 pF,

PAD_DRV=’01’¹⁾²⁾

DATA, 50 pF,

PAD_DRV=’10’¹⁾²⁾

130 ns

15 ns

30 ns

DATA, 50 pF,

PAD_DRV=’11’¹⁾²⁾

IFA/IFB, 20 pF,

PAD_DRV=’0x’¹⁾²⁾

IFA/IFB, 20 pF,

PAD_DRV=’1x’¹⁾²⁾

1) Valid for push-pull output

2) Not subject to production test - verified by design/characterization

Data Sheet

18

Rev. 1.1, 2015-09

TLI5012B E1000

Specification

Table 4-5 Electrical parameters for 4.5 V < V_DD< 5.5 V

Parameter

Symbol

Values

Typ.

Unit

Note / Test Condition

Min.

Max.

Input signal low-level

Input signal high level

Output signal low-level

V_L5

0.3 V_DD

V

V_H5

V_OL5

0.7 V_DD

1 V

DATA; I_Q= -25 mA (PAD_DRV=’0x’),

I_Q= -5 mA (PAD_DRV=’10’), I_Q= -0.4

mA (PAD_DRV=’11’)

1 V

IFA,B,C; I_Q= -15 mA (PAD_DRV=’0x’),

I_Q= -5 mA (PAD_DRV=’1x’)

Pull-up current¹⁾

I_PU

-10

10

-225 μA

-150 μA

225 μA

150 μA

CSQ

DATA

Pull-down current²⁾

I_PD

SCK

10

IFA, IFB, IFC

1) Internal pull-ups on CSQ and DATA pin are always enabled.

2) Internal pull-downs on IFA, IFB and IFC are enabled during startup and in open-drain mode, internal pull-down on SCK is

always enabled.

Table 4-6 Electrical parameters for 3.0 V < V_DD< 3.6 V

Parameter

Symbol

Values

Typ.

Unit

Note / Test Condition

Min.

Max.

Input signal low-level

Input signal high level

Output signal low-level

V_L3

0.3 V_DD

V

V_H3

V_OL3

0.7 V_DD

0.9 V

DATA; I_Q= -15 mA

(PAD_DRV=’0x’), I_Q= -3 mA

(PAD_DRV=’10’), I_Q= -0.24 mA

(PAD_DRV=’11’)

0.9 V

IFA,IFB; I_Q= - 10 mA

(PAD_DRV=’0x’), I_Q= -3 mA

(PAD_DRV=’1x’)

Pull-up current¹⁾

I_PU

-3

3

-225 μA

-150 μA

225 μA

150 μA

CSQ

DATA

Pull-down current²⁾

I_PD

SCK

3

IFA, IFB, IFC

1) Internal pull-ups on CSQ and DATA pin are always enabled.

2) Internal pull-downs on IFA, IFB and IFC are enabled during startup and in open-drain mode, internal pull-down on SCK is

always enabled.

Data Sheet

19

Rev. 1.1, 2015-09

TLI5012B E1000

Specification

4.3.2

ESD Protection

Table 4-7 ESD protection

Parameter

Symbol

Values

Unit

Notes

Min.

Max.

±4.0 kV

±0.5 kV

1)

2)

ESD voltage

V_HBM

V_CDM

1) Human Body Model (HBM) according to ANSI/ESDA/JEDEC JS-001

2) Charged Device Model (CDM) according to JESD22-C101

4.3.3

GMR Parameters

All parameters apply over B_XY= 30mT and T_A= 25°C, unless otherwise specified.

Table 4-8 Basic GMR parameters

Parameter

Symbol

Values

Typ.

Unit

Note / Test Condition

Min.

Max.

X, Y output range

X, Y amplitude²⁾

RG_ADC

A_X, A_Y

±23230 digits Operating range¹⁾

15781 digits At ambient temperature

20620 digits Operating range¹⁾

112.49 %

6000 9500

3922

X, Y synchronicity³⁾

X, Y offset⁴⁾

k

87.5

-2048

-11.25

100

0

O_X, O_Y

ϕ

+2047 digits

X, Y orthogonality error

X, Y amplitude without magnet

0

+11.24 °

+4096 digits Operating range¹⁾

X₀, Y₀

1) Not subject to production test - verified by design/characterization

2) See Figure 4-2

3) k = 100*(A_X/A_Y)

4) O_Y=(Y_MAX+ Y_MIN) / 2; O_X= (X_MAX+ X_MIN) / 2

V_Y

+A

Offset

0

0°

90°

180°

270°

360°

Angle

-A

Figure 4-2 Offset and amplitude definition

Data Sheet

20

Rev. 1.1, 2015-09

TLI5012B E1000

Specification

4.3.4

Angle Performance

After internal calculation, the sensor has a remaining error, as shown in Table 4-9. The error value refers to B_Z=

0mT and the operating conditions given in Table 4-2 “Operating range and parameters” on Page 16.

The overall angle error represents the relative angle error. This error describes the deviation from the reference

line after zero-angle definition. It is valid for a static magnetic field. If the magnetic field is rotating during the

measurement, an additional propagation error is caused by the angle delay time (see Table 4-10 “Signal

processing” on Page 23), which the sensor needs to calculate the angle from the raw sine and cosine values

from the MR bridges. In fast-turning applications, prediction can be enabled to reduce this propagation error.

Table 4-9 Angle performance

Parameter

Symbol

Values

Unit Note / Test Condition

Min. Typ. Max.

Overall angle error at 25°C

α_Err

1.0 °

1.9 °

Including lifetime drift¹⁾²⁾³⁾

Including temperature & lifetime drift^1)2)3)4)

.

Overall angle error -40°C...125°C α_Err

1) Including hysteresis error, caused by revolution direction change

2) Relative error after zero angle definition

3) With autocalibration (pre-configured by default). No temperature changes >5 Kelvin within 1.5 revolutions considered.

4) Not subject to production test - verified by design/characterization

Autocalibration enables online parameter calculation and therefore reduces the angle error due to temperature

and lifetime drifts. The TLI5012B E1000 needs 1.5 revolutions to generate new autocalibration parameters. These

parameters are continuously updated. The parameters are updated in a smooth way (one Least-Significant Bit

within the chosen range or time) to avoid an angle jump on the output.

If the temperature changes by more than 5 Kelvin during 1.5 revolutions an additional error has to be added to the

specified angle error in Table 4-9. This error depends on the temperature change (Delta Temperature) as well as

from the initial temperature (Tstart) as shown in Figure 4-3. Once the temperature stabilizes and the application

completes 1.5 revolutions, then the angle error is as specified in Table 4-9.

For negative Delta Temperature changes (from higher to lower temperatures) the additional angle error will be

smaller than the corresponding positive Delta Temperature changes (from lower to higher temperatures) shown

in Figure 4-3. The Figure 4-3 applies to the worst case.

2.5

2

1.5

1

0.5

0

Tstart -40°C

Tstart -20°C

Tstart 25°C

Tstart 85°C

Tstart 105°C

0

10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160

Delta Temperature (Kelvin) within 1.5 revolutions

Figure 4-3 Additional angle error for temperature changes above 5 Kelvin within 1.5 revolutions

Data Sheet 21 Rev. 1.1, 2015-09

TLI5012B E1000

Specification

4.3.5

Signal Processing

TLI5012B E1000

Microcontroller

X

GMR

SD-

ADC

Filter

Angle

Calculation

IF

Y

GMR

SD-

ADC

Filter

t_delIF

t_adelSSC

t_adelIIF

Figure 4-4 Signal path

The signal path of the TLI5012B E1000 is depicted in Figure 4-4. It consists of the GMR-bridge, ADC, filter and

angle calculation. The delay time between a physical change in the GMR elements and a signal on the output

depends on the filter and interface configurations. In fast turning applications, this delay causes an additional

rotation speed dependent angle error.

The TLI5012B E1000 has an optional prediction feature, which serves to reduce the speed dependent angle error

in applications where the rotation speed does not change abruptly. Prediction uses the difference between current

and last two angle values to approximate the angle value which will be present after the delay time (see

Figure 4-5). The output value is calculated by adding this difference to the measured value, according to

Equation (4.1).

(4.1)

α (t +1) = α (t) + α (t −1) −α (t − 2)

Sensor output

Angle

With

Without

Prediction

Magnetic field

direction

time

t_adel

t_upd

Figure 4-5 Delay of sensor output

Data Sheet

22

Rev. 1.1, 2015-09

TLI5012B E1000

Specification

Table 4-10 Signal processing

Parameter

Symbol

Values

Typ.

42.7

85.3

170.6

85

Unit

Note / Test Condition

Min.

Max.

Filter update period

t_upd

μs

FIR_MD = 1 (default)¹⁾

FIR_MD = 2¹⁾

FIR_MD = 3¹⁾

FIR_MD = 1¹⁾

FIR_MD = 2¹⁾

FIR_MD = 3¹⁾

FIR_MD = 1¹⁾

FIR_MD = 2¹⁾

FIR_MD = 3¹⁾

Angle delay time without

prediction²⁾

t_adelSSC

95 μs

150

165 μs

300 μs

135 μs

200 μs

330 μs

50 μs

275

t_adelIIF

120

180

305

Angle delay time with prediction²⁾t_adelSSC

45

FIR_MD = 1; PREDICT =

1¹⁾

65

105

75

70 μs

115 μs

90 µs

FIR_MD = 2; PREDICT =

1¹⁾

FIR_MD = 3; PREDICT = 1

1)

t_adelIIF

FIR_MD = 1; PREDICT =

1¹⁾

95

110 µs

150 µs

FIR_MD = 2; PREDICT =

1¹⁾

135

FIR_MD = 3; PREDICT = 1

1)

Angle noise (RMS)

N_Angle

0.08

0.05

0.04

°

FIR_MD = 1¹⁾

FIR_MD = 2¹⁾(default)

FIR_MD = 3¹⁾

1) Not subject to production test - verified by design/characterization

2) Valid at constant rotation speed

All delay times specified in Table 4-10 are valid for an ideal internal oscillator frequency of 24 MHz. For the exact

timing, the variation of the internal oscillator frequency has to be taken into account (see Chapter 4.3.6)

Data Sheet

23

Rev. 1.1, 2015-09

TLI5012B E1000

Specification

4.3.6

Clock Supply (CLK Timing Definition)

The internal clock supply of the TLI5012B E1000 is subject to production-specific variations, which have to be

considered for all timing specifications.

Table 4-11 Internal clock timing specification

Parameter

Symbol

Values

Typ.

24

Unit

Note / Test Condition

Min.

22.3

3.7

Max.

Digital clock

f_DIG

f_CLK

26.3 MHz

4.4 MHz

Internal oscillator frequency

4.0

4.3.6.1

External clock operation

In order to fix the IC timing and synchronize the TLI5012B E1000 with other ICs in a system, it can be switched to

operate with an external clock signal supplied to the IFC pin. The clock input signal must fulfill certain

requirements:

•

The high or low pulse width must not exceed the specified values, because the PLL needs a minimum pulse

width and must be spike-filtered.

•

The duty cycle factor should typically be 50%, but it can vary between 30% and 70%.

The PLL is triggered at the positive edge of the clock. If more than 2 edges are missing, a chip reset is

generated automatically and the sensor restarts with the internal clock. This is indicated by the S_RST, and

CLK_SEL bits, and additionally by the Safety Word (see Chapter 4.4.2.2).

t_CLK

t_CLKh

t_CLKl

V_H

V_L

t

Figure 4-6 External CLK timing definition

Table 4-12 External Clock Specification

Parameter

Symbol

Values

Typ.

4.0

Unit

Note / Test Condition

Min.

3.7

30

Max.

Input frequency

CLK duty cycle¹⁾²⁾

CLK rise time

f_CLK

4.4 MHz

70 %

CLK_DUTY

t_CLKr

50

30 ns

From V_Lto V_H

From V_Hto V_L

CLK fall time

t_CLKf

30 ns

1) Minimum duty cycle factor: t_CLKh(min)/ t_CLKwith t_CLK= 1 / f_CLK

2) Maximum duty cycle factor: t_CLKh(max)/ t_CLKwith t_CLK= 1 / f_CLK

Data Sheet

24

Rev. 1.1, 2015-09

TLI5012B E1000

Specification

4.4

Interfaces

4.4.1

Incremental Interface (IIF)

The Incremental Interface (IIF) emulates the operation of an optical quadrature encoder with a 50% duty cycle. It

transmits a square pulse per angle step, where the width of the steps can be configured from 9bit (512 steps per

full rotation) to 12bit (4096 steps per full rotation) within the register MOD_4 (IFAB_RES). The rotation direction is

given either by the phase shift between the two channels IFA and IFB (A/B mode) or by the level of the IFB channel

(Step/Direction mode), as shown in Figure 4-7 and Figure 4-8. The incremental interface can be configured for

A/B mode or Step/Direction mode in register MOD_1 (IIF_MOD).

Using the Incremental Interface requires an up/down counter on the microcontroller, which counts the pulses and

thus keeps track of the absolute position. The counter can be synchronized periodically by using the SSC interface

in parallel. The angle value (AVAL register) read out by the SSC interface can be compared to the stored counter

value. In case of a non-synchronization, the microcontroller adds the difference to the actual counter value to

synchronize the TLI5012B E1000 with the microcontroller.

After startup, the IIF transmits a number of pulses which correspond to the actual absolute angle value. Thus, the

microcontroller gets the information about the absolute position. The Index Signal that indicates the zero crossing

is available on the IFC pin.

Sensors with preset IIF are available as TLI5012B E1000.

A/B Mode

The phase shift between phases A and B indicates either a clockwise (A follows B) or a counterclockwise (B

follows A) rotation of the magnet.

Incremental Interface

(A/B Mode)

90° el . Phase shift

V_H

Phase A

V_L

V_H

Phase B

V_L

Counter

0

1

2

3

4

5

6

7

6

5

4

3

2

1

Figure 4-7 Incremental interface with A/B mode

Step/Direction Mode

Phase A pulses out the increments and phase B indicates the direction.

Incremental Interface

(Step/Direction Mode)

V_H

Step

V_L

V_H

Direction

V_L

Counter

0

1

2

3

4

5

6

7

6

5

4

3

2

1

Figure 4-8 Incremental interface with Step/Direction mode

Data Sheet

25

Rev. 1.1, 2015-09

TLI5012B E1000

Specification

Table 4-13 Incremental Interface

Parameter

Symbol

Values

Typ.

Unit

Note / Test Condition

Min.

Max.

Incremental output frequency

Index pulse width

f_Inc

t_0°

1.0 MHz

Frequency of phase A and

phase B¹⁾

0°¹⁾

5

μs

1) Not subject to production test - verified by design/characterization

Data Sheet

26

Rev. 1.1, 2015-09

TLI5012B E1000

Specification

4.4.2

Synchronous Serial Communication (SSC)

The 3-pin SSC interface consists of a bi-directional push-pull (tri-state on receive) or open-drain data pin

(configurable with SSC_OD bit) and the serial clock and chip-select input pins. The SSC Interface is designed to

communicate with a microcontroller peer-to-peer for fast applications.

4.4.2.1

SSC Timing Definition

t_CSs

t_CSh

t_CSoff

t_SCKp

CSQ

t_SCKh

t_SCKl

SCK

DATA

t_DATAst_DATAh

Figure 4-9 SSC timing

SSC Inactive Time (CS_off)

The SSC inactive time defines the delay time after a transfer before the TLI5012B E1000 can be selected again.

Table 4-14 SSC push-pull timing specification

Parameter

Symbol

Values

Typ.

Unit

Note / Test Condition

Min.

Max.

1)

SSC baud rate

CSQ setup time

CSQ hold time

CSQ off

f_SSC

8.0

Mbit/s

ns

t_CSs

105

t_CSh

105

600

120

40

ns

t_CSoff

ns

SSC inactive time¹⁾

1)

SCK period

t_SCKp

t_SCKh

t_SCKl

125

ns

1)

SCK high

ns

SCK low

30

ns

DATA setup time

DATA hold time

Write read delay

Update time

SCK off

t_DATAs

t_DATAh

t_{wr_delay}

t_CSupdate

t_SCKoff

25

ns

40

ns

130

1

ns

μs

See Figure 4-13¹⁾

1)

170

ns

1) Not subject to production test - verified by design/characterization

Data Sheet

27

Rev. 1.1, 2015-09

TLI5012B E1000

Specification

Table 4-15 SSC open-drain timing specification

Parameter

Symbol

Values

Typ.

Unit

Note / Test Condition

Min.

Max.

SSC baud rate

CSQ setup time

CSQ hold time

CSQ off

f_SSC

2.0

Mbit/s Pull-up Resistor = 1kΩ¹⁾

1)

t_CSs

300

ns

1)

t_CSh

400

600

500

ns

t_CSoff

ns

μs

ns

SSC inactive time¹⁾

1)

SCK period

t_SCKp

t_SCKh

t_SCKl

1)

SCK high

190

SCK low

DATA setup time

DATA hold time

Write read delay

Update time

SCK off

t_DATAs

t_DATAh

t_{wr_delay}

t_CSupdate

t_SCKoff

25

40

130

1

See Figure 4-13¹⁾

1)

170

1) Not subject to production test - verified by design/characterization

4.4.2.2

SSC Data Transfer

The SSC data transfer is word-aligned. The following transfer words are possible:

•

Command Word (to access and change operating modes of the TLI5012B E1000)

Data words (any data transferred in any direction)

Safety Word (confirms the data transfer and provides status information)

t_{wr_delay}

SAFETY-WORD

COMMAND

READ Data 1

READ Data2

SSC-Master is driving DATA

SSC-Slave is driving DATA

Figure 4-10 SSC data transfer (data-read example)

t_{wr_delay}

SAFETY-WORD

COMMAND

WRITE Data 1

SSC-Master is driving DATA

SSC-Slave is driving DATA

Figure 4-11 SSC data transfer (data-write example)

Data Sheet

28

Rev. 1.1, 2015-09

TLI5012B E1000

Specification

Command Word

SSC Communication between the TLI5012B E1000and a microcontroller is initiated by a command word. The

structure of the command word is shown in Table 4-16. If an update is triggered by shortly pulling low CSQ without

a clock on SCK a snapshot of all system values is stored in the update registers simultaneously. A read command

with the UPD bit set then allows to readout this consistent set of values instead of the current values. Bits with an

update buffer are marked by an “u” in the Type column in register descriptions.

Table 4-16 Structure of the Command Word

Name

Bits

Description

RW

[15]

Read - Write

0: Write

1: Read

Lock

UPD

[14..11]

[10]

4-bit Lock Value

0000_B: Default operating access for addresses 0x00:0x04

1010_B: Configuration access for addresses 0x05:0x11

Update-Register Access

0: Access to current values

1: Access to values in update buffer

ADDR

ND

[9..4]

[3..0]

6-bit Address

4-bit Number of Data Words

Safety Word

The safety word consists of the following bits:

Table 4-17 Structure of the Safety Word

Name

Bits

Description

STAT¹⁾

Chip and Interface Status

[15]

[14]

Indication of chip reset or watchdog overflow (resets after readout) via SSC

0: Reset occurred

1: No reset

System error (e.g. overvoltage; undervoltage; V_DD-, GND- off; ROM;...)

0: Error occurred (S_VR; S_DSPU; S_OV; S_XYOL: S_MAGOL; S_FUSE;

S_ROM; S_ADCT)

1: No error

[13]

[12]

Interface access error (access to wrong address; wrong lock)

0: Error occurred

1: No error

Valid angle value (NO_GMR_A = 0; NO_GMR_XY = 0)

0: Angle value invalid

1: Angle value valid

RESP

CRC

[11..8]

[7..0]

Sensor number response indicator

The sensor number bit is pulled low and the other bits are high

Cyclic Redundancy Check (CRC)

1) When an error occurs, the corresponding status bit in the safety word remains “low” until the STAT register (address 00_H)

is read via SSC interface.

Data Sheet

29

Rev. 1.1, 2015-09

TLI5012B E1000

Specification

Bit Types

The types of bits used in the registers are listed here:

Table 4-18 Bit Types

Abbreviation

Function

Read

Description

r

Read-only registers

Read and write registers

w

u

Write

Update

Update buffer for this bit is present. If an update is issued and the Update-

Register Access bit (UPD in Command Word) is set, the immediate values

are stored in this update buffer simultaneously. This allows a snapshot of all

necessary system parameters at the same time.

Data communication via SSC

SSC Transfer

t_{wr_delay}

Command Word

Data Word (s)

SCK

DATA

CSQ

MSB 14

13

12

11

10

9

8

7

6

5

4

3

2

1

LSB

MSB

1

LSB

RW

LOCK

UPD

ADDR

LENGTH

SSC -Master is driving DAT A

SSC -Slave is driving DAT A

Figure 4-12 SSC bit ordering (read example)

Update -Signal

Update -Event

Command Word

MSB

Data Word (s)

SCK

DATA

CSQ

LSB

t_CSupdate

SSC -Master is driving DAT A

SSC-Slave is driving DAT A

Figure 4-13 Update of update registers

The data communication via SSC interface has the following characteristics:

•

The data transmission order is Most-Significant Bit (MSB) first, Last-Significant Bit (LSB) last.

Data is put on the data line with the rising edge on SCK and read with the falling edge on SCK.

The SSC Interface is word-aligned. All functions are activated after each transmitted word.

After every data transfer with ND ≥ 1, the 16-bit Safety Word is appended by the TLI5012B E1000.

A “high” condition on the Chip Select pin (CSQ) of the selected TLI5012B E1000 interrupts the transfer

immediately. The CRC calculator is automatically reset.

•

After changing the data direction, a delay t_{wr_delay}(see Table 4-15) has to be implemented before continuing

the data transfer. This is necessary for internal register access.

If in the Command Word the number of data is greater than 1 (ND > 1), then a corresponding number of

consecutive registers is read, starting at the address given by ADDR.

Data Sheet

30

Rev. 1.1, 2015-09

TLI5012B E1000

Specification

•

In case an overflow occurs at address 3F_H, the transfer continues at address 00_H.

If in the Command Word the number of data is zero (ND = 0), the register at the address given by ADDR is

read, but no Safety Word is sent by the TLI5012B E1000. This allows a fast readout of one register.

At a rising edge of CSQ without a preceding data transfer (no SCK pulse, see Figure 4-13), the content of all

registers which have an update buffer is saved into the buffer. This procedure serves to take a snapshot of all

relevant sensor parameters at a given time. The content of the update buffer can then be read by sending a

read command for the desired register and setting the UPD bit of the Command Word to “1”.

•

After sending the Safety Word, the transfer ends. To start another data transfer, the CSQ has to be deselected

once for at least t_CSoff

.

By default, the SSC interface is set to push-pull. The push-pull driver is active only if the TLI5012B E1000 has

to send data, otherwise the DATA pin is set to high-impedance.

Cyclic Redundancy Check (CRC)

•

This CRC is according to the J1850 Bus Specification.

Every new transfer restarts the CRC generation.

Every Byte of a transfer will be taken into account to generate the CRC (also the sent command(s)).

Generator polynomial: X8+X4+X3+X2+1, but for the CRC generation the fast-CRC generation circuit is used

(see Figure 4-14)

•

The seed value of the fast CRC circuit is ’11111111_B’.

The remainder is inverted before transmission.

Serial

CRC

X7

X6

X5

X4

X3

X2

X1

X0

xor

&

xor

1

xor

1

Input

output

TX_CRC

parallel

Remainder

Figure 4-14 Fast CRC polynomial division circuit

Data Sheet

31

Rev. 1.1, 2015-09

TLI5012B E1000

Specification

4.4.3

Supply Monitoring

The internal voltage nodes of the TLI5012B E1000 are monitored by a set of comparators in order to ensure error-

free operation. An over- or undervoltage condition must be active at least 256 periods of the digital clock to set the

corresponding error bits in the Status register. This works as digital spike suppression.

Over- or undervoltage errors trigger the S_VR bit of Status register. This error condition is signaled via the in the

Safety Word of the SSC protocol, the status nibble of the SPC interface or the lower diagnostic range of the PWM

interface.

Table 4-19 Test comparator threshold voltages

Parameter

Symbol

Values

Typ.

2.80

6.05

2.70

-0.55

0.55

10

Unit

Note / Test Condition

Min.

Max.

1)

Overvoltage detection

V_OVG

V_OVA

V

μs

V_OVD

V_DDovervoltage

V_DDundervoltage

GND - off voltage

V_DD- off voltage

Spike filter delay

V_DDOV

V_DDUV

V_GNDoff

V_VDDoff

t_DEL

1) Not subject to production test - verified by design/characterization

4.4.3.1

Internal Supply Voltage Comparators

Every voltage regulator has an overvoltage (OV) comparator to detect malfunctions. If the nominal output voltage

of 2.5 V is larger than V_OVG, V_OVAand V_OVD, then this overvoltage comparator is activated.

4.4.3.2

V_DDOvervoltage Detection

The overvoltage detection comparator monitors the external supply voltage at the V_DDpin.

V_DDA

REF

-

10µs

Spike

V_DD

V_RG

V_RA

V_RD

xxx_OV

Filter

+

GND

Figure 4-15 Overvoltage comparator

GND

4.4.3.3

GND - Off Comparator

The GND - Off comparator is used to detect a voltage difference between the GND pin and SCK. This circuit can

detect a disconnection of the supply GND Pin.

Data Sheet

32

Rev. 1.1, 2015-09

TLI5012B E1000

Specification

V_DD

V_DDA

Diode-

reference

SCK

GND

+dV

-

1µs

Mono

Flop

10µs

Spike

Filter

GND_OFF

+

GND

Figure 4-16 GND - off comparator

4.4.3.4

V_DD- Off Comparator

The V_DD- Off comparator detects a disconnection of the VDD pin supply voltage. In this case, the TLI5012B E1000

is supplied by the SCK and CSQ input pins via the ESD structures.

V_DDA

V_DD

-

1µs

Mono

Flop

10µs

Spike

Filter

V_VDDoff

-dV

VDD_OFF

CSQ

SCK

+

GND

Figure 4-17 V_DD- off comparator

Data Sheet

33

Rev. 1.1, 2015-09

TLI5012B E1000

Package Information

5

Package Information

5.1

Package Parameters

Table 5-1 Package Parameters

Parameter

Symbol Limit Values

Min. Typ. Max.

Unit

Notes

Thermal resistance

R_thJA

R_thJC

R_thJL

150

200 K/W

75 K/W

85 K/W

Junction to air¹⁾

Junction to case

Junction to lead

260°C

Soldering moisture level

Lead Frame

MSL 3

Cu

Sn 100%

Plating

> 7 μm

1) according to Jedec JESD51-7

5.2

Package Outline

Figure 5-1 PG-DSO-8 package dimension

Data Sheet

34

Rev. 1.1, 2015-09

TLI5012B E1000

Package Information

Figure 5-2 Position of sensing element

Table 5-2 Sensor IC placement tolerances in package

Parameter

Values

Unit

Notes

Min.

-200

Max.

200 µm

position eccentricity

in X- and Y-direction

rotation

tilt

-3

3 °

affects zero position offset of sensor

5.3

Footprint

0.65

1.27

Figure 5-3 Footprint of PG-DSO-8

Data Sheet

35

Rev. 1.1, 2015-09

TLI5012B E1000

Package Information

5.4

Packing

0.3

8

1.75

2.1

6.4

Figure 5-4 Tape and Reel

5.5

Marking

Position

1st Line

2nd Line

3rd Line

Marking

I12B1000

xxx

Description

See ordering table on Page 8

Lot code

Gxxxx

G..green, 4-digit..date code

Processing

Note: For processing recommendations, please refer to Infineon’s Notes on processing

Data Sheet

36

Rev. 1.1, 2015-09

w w w . i n f i n e o n . c o m

Published by Infineon Technologies AG


型号：	TLI5012B E1000
厂家：	Infineon
描述：	The Infineon TLI5012B E1000 is an 360° angle sensor that detects the orientation of a magnetic field, achieved by measuring sine and cosine angle components with monolithic integrated Giant Magneto Resistance (iGMR) elements. These raw signals (sine and cosine) are digitally processed internally to calculate the angle orientation of the magnetic field (magnet).
文件：	总37页 (文件大小：2098K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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