TLF30682QVS01 [INFINEON]
The TLF30682QVS01, member of the OPTIREG™ PMIC-family, is a multi-rail supply for ADAS-applications like 76-79GHz radar, multi-purpose camera or display cluster or center stack applications.;
| 型号： | TLF30682QVS01 |
| 厂家： | 
Infineon |
| 描述： | The TLF30682QVS01, member of the OPTIREG™ PMIC-family, is a multi-rail supply for ADAS-applications like 76-79GHz radar, multi-purpose camera or display cluster or center stack applications. 集成电源管理电路 |
| 文件： | 总97页 (文件大小：3596K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Features
•
High-efficiency multi-rail power supply chip optimized for the use in
Advanced Driver Assistance Systems (ADAS)
•
Step-down pre-regulator for wide input voltage range from 3.7 V to 35 V
(40 V limited time) with low over-all power loss and fast transient
performance. Suitable for operation with ceramic capacitors
•
High-efficiency step-down post-regulator for second output voltage
generation
•
•
•
•
•
Step-up post-regulator with 5 V output voltage
Voltage monitoring for two external voltage rails including enable signals
Configurable window watchdog
16-bit SPI
Green Product (RoHS compliant)
Potential applications
•
Automotive applications
•
Advanced Driver Assistance Systems (ADAS)
–
–
77 GHz radar ECUs
Camera ECUs
•
Human Machine Interface (HMI) applications
Product validation
Qualified for automotive applications. Product validation according to AEC-Q100.
Description
The OPTIREG™ PMIC TLF30682QVS01 is a multi-output Power Management IC (PMIC) for automotive
applications. The device consists of a battery connected buck regulator (Buck1) providing 3.3 V to external
loads and to two low voltage post-regulators. The first post-regulator (Buck2) is a buck regulator providing an
output voltage of 1.25 V. The second post-regulator (Boost1) provides an output voltage of 5.0 V and is
intended to supply one or two CAN transceivers.
The TLF30682QVS01 supports 16-bit SPI communication to a microcontroller. The SPI commands support
reading status information from the device and control of features such as PWM synchronization and control
of the power regulators.
Data Sheet
1.01
2019-07-03
www.infineon.com/dcdc-automotive
1
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
The device operates at a nominal switching frequency of 2.2 MHz. The switching frequency can be selected via
SPI with an operating range from 1.8 MHz to 2.5 MHz in steps of 100 kHz. The switching regulators can be
synchronized to an external clock signal. The TLF30682 can provide a synchronization signal for other DC/DC
regulators in the system.
The TLF30682QVS01 provides two voltage monitoring channels with monitoring inputs and enable outputs.
The monitoring channels can be used to control and monitor external voltage regulators. The external voltage
regulator can be either LDOs or DC/DC switching regulators.
Type
Package
Marking
TLF30682QVS01
PG-VQFN-48
TLF30682
S01
Data Sheet
2
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Potential applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Product validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
2.1
2.2
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin definitions and functions PG-VQFN-48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Quiescent current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1
3.2
3.3
3.4
3.4.1
4
4.1
Power converters and power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
High voltage step-down regulator – Buck1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Functional description Buck1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Electrical characteristics Buck1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Post-regulator step-down converter – Buck2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Functional description Buck2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Electrical characteristics Buck2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Post-regulator step-up converter – Boost1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Functional description Boost1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Electrical characteristics Boost1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Support of external voltage rails . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.1.1
4.1.2
4.1.2.1
4.2
4.2.1
4.2.2
4.2.2.1
4.3
4.3.1
4.3.2
4.3.2.1
4.4
5
5.1
5.2
5.2.1
5.2.2
5.3
5.4
5.4.1
5.5
Central functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Supply voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Enable functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
ENA pin configurability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Power sequencing and soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Switching frequency generation and clock synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
IOVDD - Overvoltage and undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6
6.1
6.1.1
6.1.2
6.1.3
Monitoring functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Monitoring of R1VSx – battery supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Monitoring of output voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Monitoring of external voltage rails . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Data Sheet
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OPTIREG™ PMIC TLF30682QVS01
Power Management IC
6.1.4
6.1.5
6.2
Monitoring of internal supply voltages and bandgaps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7
7.1
7.1.1
7.2
Microcontroller interface and supervisory functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Microcontroller interface supply – IOVDD pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
SPI introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
SPI write access to protected registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
SPI write initiated state transition request and regulator configuration . . . . . . . . . . . . . . . . . . . . . 48
Configuration of Buck2 output voltage via SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Reset signal ROT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Electrical characteristics – ROT pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Interrupt signal INT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Electrical characteristics – INT pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Microcontroller programming support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.3
7.3.1
7.4
7.4.1
7.5
7.5.1
7.6
8
State machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Operation states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
State transitions and trigger signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
8.1
8.2
8.3
8.4
9
9.1
SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
SPI register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Device configuration registers (device start-up default configuration) . . . . . . . . . . . . . . . . . . . . . . . 65
Read-only registers for protected configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Special device configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
General registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Event status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Device status information registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Device information registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
9.1.1
9.1.2
9.1.3
9.1.4
9.1.5
9.1.6
9.1.7
10
11
12
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Data Sheet
4
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2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Block diagram
1
Block diagram
R1VSx
V_S (T30)
SYNCI
SYNC_In
SYNC_Out
Clock
Generation
Buck1
Driver
Supply
Internal
Supply
SYNCO
NC
Logic
R1BTSV
R1BTS
ENABLE
R1SWx
R1PGx
SMPR
Buck1
V_Buck1
ENA
ENABLE
Feedback
MPS
R3VS
IOVDD
R1FB
Interface_supply
INT
R3SW
INTERRUPT
Generator
Interrupt
SMPR
Boost
V_Boost
V_Buck2
SCS
SCL
SDI
R3PG
R3FB
SPI_ChipSelect
SPI_Clock
Feedback
SPI
SPI_DataIn
R2VS1x
R2SWx
SDO
SPI_DataOut
SMPR
Buck2
WDI
Window
Watchdog
Watchdog_TriggerIn
R2PGx
R2FB
Feedback
Bandgap 1
NC
Fault
VM1EN
VM1FB
Manager
ExtRail1_Enable
TM1
ExtRail1_Feedback
TM2
ROT
UV/OV-Monitoring/
Enable Handling
VM2EN
VM2FB
ExtRail2_Enable
μC_Reset
Bandgap 2
for V- Mon.
Reset Generator
ExtRail2_Feedback
AG1 AG2
AG3 AG4 AG5
AG6
Figure 1
Block diagram
Data Sheet
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2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Pin configuration
2
Pin configuration
2.1
Pin assignment
E
SDO 37
SDI 38
SCL 39
24 R2PG2
23 R2PG1
22 R2FB
21 AG4
SCS 40
ROT 41
INT 42
WDI 43
TM2 44
20 R1FB
19 AG3
18 AG2
Top View
17 AG1
16 R1BTS
15 R1SW3
14 R1SW2
13 R1SW1
VM1EN 45
VM2EN 46
VM1FB 47
VM2FB 48
E
E
Figure 2
Pin configuration
2.2
Pin definitions and functions PG-VQFN-48
Pin
Symbol Function
1
AG5
Analog ground, pin 5:
Connect directly (low ohmic and low inductive) to ground.
2
3
4
5
6
NC
Not connected:
Leave the pin floating in the application.
AG6
Analog ground, pin 6:
Connect directly (low ohmic and low inductive) to ground.
R1BTSV Decoupling pin for internal supply voltage:
Connect a decoupling capacitor between the pin and R1PGx.
NC
Not connected:
Leave the pin floating in the application.
ENA
Enable input:
A valid enable condition at the pin will enable the device.
Data Sheet
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1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Pin configuration
Pin
Symbol Function
7
R1VS1 High voltage regulator supply voltage, pin 1:
Connect in parallel with R1VS2 and R1VS3 and then to the supply (battery) voltage via
a reverse protection diode. Additionally connect a capacitor between the pin and
ground. An EMC filter is recommended.
8
9
R1VS2 High voltage regulator supply voltage, pin 2:
Connect in parallel with R1VS1 and R1VS3 and then to the supply (battery) voltage via
a reverse protection diode. Additionally connect a capacitor between the pin and
ground. An EMC filter is recommended.
R1VS3 High voltage regulator supply voltage, pin 3:
Connect in parallel with R1VS1 and R1VS2 and then to the supply (battery) voltage via
a reverse protection diode. Additionally connect a capacitor between the pin and
ground. An EMC filter is recommended.
10
11
12
13
14
15
R1PG1 High voltage regulator power ground, pin 1:
Connect in parallel with R1PG2 and R1PG3 and then to the Buck1 output capacitor
ground terminal to ground.
R1PG2 High voltage regulator power ground, pin 2:
Connect in parallel with R1PG1 and R1PG3 and then to the Buck1 output capacitor
ground terminal to ground.
R1PG3 High voltage regulator power ground, pin 3:
Connect in parallel with R1PG1 and R1PG2 and to the Buck1 output capacitor ground
terminal to ground.
R1SW1 High voltage regulator power stage output, pin 1:
Connect in parallel with R1SW2 and R1SW3 and then to the pre-regulator (Buck1)
output filter inductor.
R1SW2 High voltage regulator power stage output, pin 2:
Connect in parallel with R1SW1 and R1SW3 and then to the pre-regulator output filter
inductor.
R1SW3 High voltage regulator power stage output, pin 3:
Connect in parallel with R1SW1 and R1SW2 and then to the pre-regulator output filter
inductor.
16
17
18
19
20
21
22
R1BTS Bootstrap supply voltage:
Connect via the bootstrap capacitor to the R1SWx pins.
AG1
AG2
AG3
R1FB
AG4
R2FB
Analog ground, pin 1:
Connect directly (low ohmic and low inductive) to ground.
Analog ground, pin 2:
Connect directly (low ohmic and low inductive) to ground.
Analog ground, pin 3:
Connect directly (low ohmic and low inductive) to ground.
High voltage regulator output voltage feedback pin:
Connect to the Buck1 output capacitor.
Analog ground, pin 4:
Connect directly (low ohmic and low inductive) to ground.
Post-regulator output voltage feedback pin:
Connect to the Buck2 output capacitor.
Data Sheet
7
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Pin configuration
Pin
Symbol Function
23
R2PG1 Pre-regulator power ground, pin 1:
Connect in parallel with R2PG2 and then to the Buck2 output capacitor ground
terminal to ground.
24
R2PG2 Pre-regulator power ground, pin 2:
Connect in parallel with R2PG1 and then to the Buck2 output capacitor ground
terminal to ground.
25
26
27
28
29
30
31
32
33
R2SW1 Post-regulator power stage output, pin 1:
Connect in parallel with R2SW2 and then to the Buck2 output filter inductor.
R2SW2 Post-regulator power stage output, pin 2:
Connect in parallel with R2SW1 and then to the Buck2 output filter inductor.
R2VS1 Post-regulator supply voltage, pin 1:
Connect to the Buck1 output capacitor.
R2VS2 Post-regulator supply voltage, pin 2:
Connect to the Buck1 output capacitor.
R3SW1 Regulator 3 power stage output, pin 1:
Connect to Boost1 inductor and external rectifying diode.
R3PG1 Regulator 3 power ground, pin 1:
Connect to Boost1 output capacitor ground terminal to ground.
R3FB
TM1
MPS
Regulator 3 output voltage feedback pin:
Connect to Boost1 output capacitor.
Test mode 1 pin:
Not for customer use. Leave the pin floating in the application.
Microcontroller programming mode pin
Connect to ground for normal operation in the application. Optionally the pin can be
used for microcontroller programming purposes. For details please refer to the
application information section.
34
35
IOVDD I/O supply voltage:
Connect to the I/O supply voltage of the microcontroller.
SYNCO Synchronization output signal:
Connect to an optional external switch-mode post-regulator synchronization input.
The signal delivers the internal switching frequency either in phase or shifted by 180°
(configurable via SPI). The switch-mode post-regulator synchronizes to the rising
edge.
If the pin is not used, it should be left floating.
36
SYNCI Synchronization input signal:
Connect to an optional external synchronization signal to synchronize the switching of
the internal switch-mode regulators. The feature needs to be enabled via SPI.
If the pin is not used, it should be left floating.
37
38
SDO
SDI
Serial peripheral interface, signal data output:
SPI signalling port, connect to SPI port "data input" of microcontroller to send status
information during SPI communication.
Serial peripheral interface, signal data input:
SPI signalling port, connect to SPI port "data output" of microcontroller to receive
commands during SPI communication.
Data Sheet
8
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Pin configuration
Pin
Symbol Function
39
SCL
SCS
ROT
Serial peripheral interface, signal clock:
SPI signalling port, connect to SPI port "clock" of microcontroller to clock the device
for SPI communication.
40
41
Serial peripheral interface, signal chip select:
SPI signalling port, connect to SPI port "chip select" of microcontroller to address the
device for SPI communication.
Reset output:
Open drain structure with internal pull up resistor. A "low" signal at this pin indicates
a reset event for the microcontroller.
Connect to microcontroller reset input.
42
43
INT
Interrupt signal:
Push-pull output. A "low" pulse at this pin indicates an interrupt, and the
microcontroller reads the SPI status registers.
Connect to a non-maskable interrupt port (NMI) of the microcontroller.
WDI
TM2
Watchdog input, trigger signal:
Input for trigger signal. Connect the "trigger signal output" of the microcontroller to
the pin.
If the pin is not used it should be left floating (internal pull-down).
44
45
Test mode 2 pin:
Not for customer use. Connect the pin to GND in the application.
VM1EN Enable signal for external voltage rails 1:
Connect to the enable pin of a optional external voltage regulator 1.
If the optional external regulator is not used, connect to ground.
46
47
VM2EN Enable signal for external voltage rails 2:
Connect to the enable pin of a optional external voltage regulator 2.
If the optional external regulator is not used, connect to ground.
VM1FB Input for optional external voltage monitoring rail 1:
Connect an external resistor divider to adjust the overvoltage threshold and the
undervoltage threshold of the monitored external voltage generated by the optional
external voltage regulator 1.
If the optional external regulator is not used, connect to ground.
48
VM2FB Input for optional external voltage monitoring rail 2:
Connect an external resistor divider to adjust the overvoltage threshold and the
undervoltage threshold of the monitored external voltage generated by the optional
external voltage regulator 2.
If the optional external regulator is not used, connect to ground.
Cooling Tab GND
EP1
Cooling tab:
Internally connected to GND
Edge pin no 1:
Keep the area below the pin free of ground or other signals. Do not solder this pin to
ground or any other signal. This pin must be kept free of soldering.
EP2
Edge pin no 2:
Keep the area below the pin free of ground or other signals. Do not solder this pin to
ground or any other signal. This pin must be kept free of soldering.
Data Sheet
9
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Pin configuration
Pin
Symbol Function
EP3
Edge pin no 3:
Keep the area below the pin free of ground or other signals. Do not solder this pin to
ground or any other signal. This pin must be kept free of soldering.
EP4
Edge pin no 4:
Keep the area below the pin free of ground or other signals. Do not solder this pin to
ground or any other signal. This pin must be kept free of soldering.
Data Sheet
10
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
General product characteristics
3
General product characteristics
3.1
Absolute maximum ratings
Table 1
Absolute maximum ratings1)
Tj = -40°C to 150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min.
Typ. Max.
Pin
MPS
VMPS
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-5.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
0.3
0.3
0.3
0.3
0.3
0.3
6.0
6.0
6.0
35
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mA
–
P_3.1.1
IOVDD
SCS
VIOVDD
VSCS
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
P_3.1.2
P_3.1.3
SCL
VSCL
P_3.1.4
SDI
VSDI
P_3.1.5
SDO
VSDO
P_3.1.6
WDI
VWDI
P_3.1.7
INT
VINT
P_3.1.10
P_3.1.13
P_3.1.14
P_3.1.15
P_3.1.16
P_3.1.17
P_3.1.18
P_3.1.19
P_3.1.20
P_3.1.22
P_3.1.23
P_3.1.24
P_3.1.25
P_3.1.26
P_3.1.27
P_3.1.28
P_3.1.29
P_3.1.30
P_3.1.31
P_3.1.32
P_3.1.33
P_3.1.34
AG1
VAG1
AG2
VAG2
AG3
VAG3
AG4
VAG4
AG5
VAG5
AG6
VAG6
SYNCI
SYNCO
TM1
VSYNCI
VSYNCO
VTM1
–
2)
ENA
VENA
ENA
IENA
–
–
–
R1BTS
R1BTSV
R1VS1
R1VS2
R1VS3
R1SW1
R1SW2
R1SW3
R1PG1
R1PG2
VR1BTS
VR1BTSV
VR1VS1
VR1VS2
VR1VS3
VR1SW1
VR1SW2
VR1SW3
VR1PG1
VR1PG2
VR1SWx - 0.3 –
VR1SWx + 6.0 V
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
–
–
–
–
–
–
–
–
–
6.0
V
V
V
V
V
V
V
V
V
–
2)
35
2)
2)
35
35
VR1VSx+2.0
VR1VSx+2.0
VR1VSx+2.0
0.3
–
–
–
–
–
0.3
Data Sheet
11
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
General product characteristics
Table 1
Absolute maximum ratings1) (cont’d)
Tj = -40°C to 150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min.
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
Typ. Max.
R1PG3
VR1PG3
VR1FB
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0.3
7.0
7.0
7.0
7.0
7.0
0.3
0.3
7.0
7.0
0.3
7.0
6.0
6.0
6.0
6.0
6.0
6.0
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
–
P_3.1.35
P_3.1.36
P_3.1.37
P_3.1.38
P_3.1.39
P_3.1.40
P_3.1.41
P_3.1.42
P_3.1.43
P_3.1.44
P_3.1.45
P_3.1.46
P_3.1.47
P_3.1.48
P_3.1.49
P_3.1.50
P_3.1.51
P_3.1.52
R1FB
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
R2VS1
VR2VS1
VR2VS2
VR2SW1
VR2SW2
VR2PG1
VR2PG2
VR2FB
R2VS2
R2SW1
R2SW2
R2PG1
R2PG2
R2FB
R3SW1
VR3SW1
VR3PG1
VR3FB
R3PG1
R3FB
VM1FB
VVM1FB
VVM1EN
VVM2FB
VVM2EN
VROT
VM1EN
VM2FB
VM2EN
ROT
TM2
VTM2
Temperatures
Junction temperature
Storage temperature
ESD susceptibility
Tj
-40
-55
–
–
150
150
°C
°C
–
–
P_3.1.53
P_4.1.9
Tstg
ESD susceptibility all pins VESD,HBM -2
ESD susceptibility all pins VESD,CDM -500
–
–
–
2
kV HBM3)
P_4.1.10
P_4.1.12
P_4.1.13
500
750
V
V
CDM4)
CDM4)
ESD susceptibility of
corner pins to GND
VESD,Corner -750
1) Not subject to production test, specified by design.
2) Maximum rating is extended to 40 V for an overall time of 7 minutes during the lifetime of the product (load dump
requirement)
3) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS001 (1.5k Ω, 100 pF)
4) ESD susceptibility, Charged Device Model "CDM" according JEDEC JESD22-C101
Notes
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Data Sheet
12
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
General product characteristics
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as "outside" normal operating range. Protection functions are
not designed for continuous repetitive operation.
3.2
Functional range
Note:
Within the functional or operating range, the IC operates as described in the circuit description. The
electrical characteristics are specified within the conditions given in the Electrical Characteristics
table.
Table 2
Functional Range
Parameter
Symbol
Values
Typ.
–
Unit Note or
Test Condition
Number
Min.
Max.
1)
Supply Voltage Range for
Normal Operation
VR1VSx
VR1VSx
Tj
5.0
35
V
P_3.2.1
P_4.2.5
P_4.2.9
1)2)
Supply Voltage Range for
Reduced Operation
3.7
–
–
5.0
V
Junction Temperature
-40
150
°C
–
1) When first powered up, a proper startup of the device can only be assured by applying minimum 6 V at pins R1VSx for
at least 2 ms. The device may start at even lower voltages.
2) The current capability of Buck1 is reduced to limit the current stress in the device.
Data Sheet
13
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
General product characteristics
3.3
Thermal resistance
Note:
This thermal data was generated in accordance with JEDEC JESD51 standards. For more
information, go to www.jedec.org.
Table 3
Thermal resistance1)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min.
–
Typ.
Max.
12.2
22.1
Junction to case
RthJC
–
–
K/W
K/W JEDEC 2s2p,
measured to pin 1, 3,
–
P_4.3.1
P_3.3.1
Junction to soldering point RthJSP
(pin)
20.1
17, 18, 19, 21
Junction to soldering point RthJSP
34.9
–
37.6
K/W JEDEC 1s0p,
P_3.3.2
(pin)
measured to pin 1, 3,
17, 18, 19, 21
Junction to soldering point RthJSP
(soldering pad)
11.0
13.1
–
–
14.7
18.0
–
K/W JEDEC 2s2p
P_3.3.3
P_4.3.2
P_4.3.3
Junction to soldering point RthJSP
(soldering pad)
–
K/W JEDEC 1s0p
2)
Junction to ambient
RthJA
37
K/W
1) Not subject to production test, specified by design.
2) Specified RthJA value is according to JEDEC JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The product
(Chip and Package) was simulated on a 76.2 × 114.3 × 1.5 mm³ board with two inner copper layers (2 × 70 µm Cu,
2 × 35 µm Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
Data Sheet
14
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
General product characteristics
3.4
Quiescent current consumption
Table 4
Quiescent current consumption
Tj = -40°C to 150°C, VR1VSx = 9 V to 25 V (unless otherwise specified)
Parameter
Symbol
Values
Typ.
–
Unit Note or
Test Condition
Number
Min.
Max.
ACTIVE state
Iq,OP
–
20
mA
Tj ≤ 85°C
P_3.4.1
9 V ≤ VR1VSx ≤ 25 V
No load, Watchdog
disabled
DISABLED state
DISABLED state
FAULT state
Iq,DIS
Iq,DIS
Iq,FLT
Iq,LCK
–
–
–
–
13
11
1
17.5
13.5
2
µA
µA
mA
µA
Tj ≤ 85°C
9 V ≤ VR1VSx ≤ 25 V
P_3.4.2
P_3.4.3
P_3.4.4
P_3.4.5
Tj = 25°C
V
R1VSx = 13.5 V
Tj ≤ 85°C
9 V ≤ VR1VSx ≤ 25 V
LOCKED state
35
50
Tj ≤ 85°C
9 V ≤ VR1VSx ≤ 25 V
Data Sheet
15
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
General product characteristics
3.4.1
Typical performance characteristics
DISABLED state - Quiescent current
LOCKED state - Quiescent current
consumption Iq versus supply voltage VR1VSx
consumption Iq versus supply voltage VR1VSx
Data Sheet
16
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Power converters and power management
4
Power converters and power management
4.1
High voltage step-down regulator – Buck1
4.1.1
Functional description Buck1
The high-voltage step-down regulator (Buck1) converts the battery voltage (R1VSx) to the Buck1 voltage.
A synchronous current-mode-controlled buck converter with internal power switches is integrated for this
purpose. The output rail VBuck1 can be used as direct supply rail as well as pre-regulated rail for post-
regulators.
The N-/N-MOS power stage is driven by an integrated driver circuit supplied by an external boot-strap
capacitor. The integrated dead-time optimization prevents cross-conduction, minimizes dead-time and
increases system efficiency. The output voltage is set with an internal voltage divider. Internal compensation
allows for fast loop performance across a wide range of output capacitance. External tuning of the loop is not
required. The design supports both ceramic and electrolytic capacitors. For detailed information on the
selection of the external power stage components, namely the inductor and input/output filter capacitors,
please refer to Chapter 10.
The converter offers various configuration options. It offers a selectable switching frequency, which can be
configured via the SPI. Synchronization of the switching frequency with the other integrated converters as
well as an external synchronization signal is included. Various protection features, such as overcurrent and
overtemperature detection, prevent damage to the converter due to fault conditions.
Vbat
R1VSx
R1BTS
Bandgap 1
Pre-
Regulator
Buck1
R1SWx
R1PGx
V_Buck1
Feedback
R1FB
Logic
SYNCI
SYNC_In
SYNC_Out
Clock
Generation
SYNCO
Figure 3
Block Diagram Buck1
Data Sheet
17
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Power converters and power management
Modulation concept
The converter uses several modulation schemes depending on the operation mode. A PWM scheme is used for
most of the operating area. It supports synchronization to internal and external clock sources. For light-load
and high-line operation, pulse-skipping operation is used. This allows for an improved system efficiency and
ensures a minimum turn-on time to ensure correct operation of the switches.
The transition between PWM and pulse-skipping is automatically handled by the converter and does not
require any configuration. The current and voltage thresholds for this transition are dependent on the
selected power stage components.
Loop compensation
The converter uses a cascaded current-mode, voltage-mode control scheme. The inductor current is
controlled by an inner current-loop, while the output voltage is regulated by the external voltage
compensation loop. The compensation loop can operate with a range of power stages. For detailed
information on the selection of the external components, please refer to Chapter 10. The dynamic
performance of the system is a function of the power stage components and the internal compensation loop.
Follow the design considerations in Chapter 10 for optimum performance.
Cycle-by-cycle current limitation
The device features cycle-by-cycle current limitation to protect the switches and external components in case
of a fault condition. If a defined current threshold is reached, then the peak current monitoring turns off the
high-side switch. The device also monitors the current in the low side switch. If the current in the low side
switch exceeds the overcurrent threshold at the end of the switching period, then the high side switch is not
turned on in the following switching period. This allows the device to work as a constant current source.
If the current in the inductor exceeds the overcurrent protection threshold for a defined time, TR1OCP, then an
overcurrent time-out event is signalized with an interrupt (OCSF1.BUCK1OCW). It is up to the user to decide,
how to react in this situation, for example by shutting down the converter.
Overtemperature protection
The converter includes an overtemperature warning and shutdown function to protect the device against
damage. If the junction temperature exceeds the overtemperature warning threshold, an overtemperature
warning flag is set (OTSF1.BUCK1OTW) and an interrupt is generated. If the junction temperature continues
to rise and exceeds the overtemperature shutdown threshold, then the converter shuts down and generates
a thermal shut-down (TSD) event. The OTSF0.BUCK1OT status flag is set and can be read by the
microcontroller after re-entering ACTIVE state.
The current status of the overtemperature warning can be accessed at OTSTAT0.BUCK1OTW, while
OTSF1.BUCK1OTW contains the latched information.
Soft-start
The integrated soft-start feature limits the in-rush current and allows for smooth start-up of the converter.
Power-sequencing together with the other output rails is supported. Please refer to Chapter 5.3 for more
information.
Data Sheet
18
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Power converters and power management
4.1.2
Electrical characteristics Buck1
Table 5
Electrical characteristics Buck1
Tj = -40°C to 150°C, VR1VSx = 3.7 V to 35 V, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
12
Unit Note or
Test Condition
Number
Min.
Max.
Input voltage - TLF30682
S01
VR1VSx
3.7
35
V
VR1FB = 3.3 V
P_4.1.2.1
P_4.1.2.2
P_4.1.2.9
Output voltage – TLF30682 VR1FB
S01
–
3.3
–
V
–
Output voltage tolerance
Maximum output current
VR1FB,TOL
IR1IOUT
-2
–
–
–
+2
–
%
A
3.5
2.0
5.0 V ≤ VR1VSx ≤ 35 V P_4.1.2.10
3.7 V ≤ VR1VSx < 5.0 V P_4.1.2.11
Maximum output current – IR1IOUT,DR
–
A
derated
High-side switch on-
resistance
RDSOn,R1HS
45
–
77
–
145
160
135
150
mΩ
mΩ
mΩ
mΩ
5.0 V ≤ VR1VSx ≤ 35 V P_4.1.2.16
3.7 V ≤ VR1VSx < 5.0 V P_4.1.2.17
5.0V ≤ VR1VSx ≤ 35 V P_4.1.2.18
3.7V ≤ VR1VSx < 5.0 V P_4.1.2.19
High-side switch on-
resistance derated
RDSOn,R1HS,DR
RDSOn,R1LS
Low-side switch on-
resistance
35
–
72
–
Low-side switch on-
resistance derated
RDSOn,R1LS,DR
–
–
–
–
–
P_4.1.2.20
P_4.1.2.21
Overcurrent protection
threshold
IR1OCP
tR1OCP
4.1
4.5
6.0
A
Overcurrent time out
95
–
100
–
115
–
µs
–
–
P_4.1.2.23
P_4.1.2.24
Minimum ON time
50
58
72
ns
Minimum ON time P_4.1.2.25
for internal HS
control signal. The
actual ON time on
the R1SWx pins
depends on the
application design.
Overtemperature warning
threshold
Tj,R1OT,WRN
Tj,R1OT,WRN
130
120
175
165
–
145
135
190
180
160
150
205
195
–
°C
°C
°C
°C
nF
1) Tj increasing
1) Tj decreasing
1) Tj increasing
1) Tj decreasing
–
P_4.1.2.26
P_4.1.2.27
P_4.1.2.28
P_4.1.2.29
P_4.1.2.30
Overtemperature warning
threshold
Overtemperature shutdown Tj,R1OT,FLT
threshold
Overtemperature shutdown Tj,R1OT,FLT
threshold
Bootstrap capacitor
CR1BST
100
Data Sheet
19
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Power converters and power management
Table 5
Electrical characteristics Buck1 (cont’d)
Tj = -40°C to 150°C, VR1VSx = 3.7 V to 35 V, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
External power stage components
Effective inductance LR1
2)
2.64
75
1
3.3
100
5
4.0
240
30
µH
µF
P_4.1.2.33
P_4.1.2.35
P_4.1.2.36
2)3)
Effective output capacitance CR1
ESR of output capacitance RR1C
mΩ
–
1) Not subject to production test, specified by design.
2) See Chapter 10 for additional information on the allowed L,C combinations.
3) Effective capacitance including de-rating over the temperature range, bias voltage and aging. Electrolytic and
ceramic capacitors are supported.
4.1.2.1 Typical performance characteristics
Buck1 output voltage VR1FB
versus load current IR1IOUT
Buck1 output voltage VR1FB
versus supply voltage VR1VSx (drop-out region)
Data Sheet
20
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Power converters and power management
4.2
Post-regulator step-down converter – Buck2
Functional description Buck2
4.2.1
The low-voltage step-down regulator (Buck2) converts the output voltage of Buck1 into the VBuck2 voltage.
A synchronous current-mode-controlled buck converter with internal P-/N-MOS power stage is integrated for
this purpose. The output voltage is set with an internal voltage divider. Internal compensation allows for fast
loop performance across a wide range of output capacitance. External tuning of the loop is not required. The
design supports both ceramic and electrolytic capacitors. For detailed information on the selection of the
external power stage components, namely the inductor and input/output filter capacitors, please refer to
Chapter 10.
Synchronization of the switching frequency with the other integrated converters as well as an external
synchronization signal is included. Various protection features, for example overcurrent, overtemperature
and overvoltage detection, prevent damage to the converter due to fault conditions.
Loop compensation
Due to the integrated loop compensation no external components are required for loop compensation.
The dynamic performance of the system is a function of the power stage components and the internal
compensation loop. Follow the design considerations in Chapter 10 for optimum performance.
Cycle-by-cycle current limitation
The device features cycle-by-cycle current limitation to protect the switches and external components in case
of a fault condition. If a defined current threshold is reached, then the peak current monitoring turns off the
high-side switch. The device also monitors the current in the low side switch. If the current in the low side
switch exceeds the overcurrent threshold at the end of the switching period, then the high side switch is not
turned on in the following switching period. This allows the device to work as a constant current source.
If this operation mode persists for a defined time, an overcurrent time-out event, tR2OCP, is signalized with an
interrupt (OCSF1.BUCK2OCW). It is up to the user to decide how to react in this situation, by, for example
shutting down the converter.
Overtemperature protection
The converter includes an overtemperature warning and shutdown function to protect the device against
damage. If the junction temperature exceeds the overtemperature warning threshold, an overtemperature
warning flag is set (OTSF1.BUCK2OTW) and an interrupt is generated. If the junction temperature continues
to rise and exceeds the overtemperature shutdown threshold, then the converter shuts down and generates
a thermal shut-down (TSD) event. The OTSF0.BUCK2OT status flag is set and can be read by the
microcontroller after re-entering ACTIVE state.
The current status of the overtemperature warning can be accessed at OTSTAT0.BUCK2OTW, while
OTSF1.BUCK2OTW contains the latched information.
Output voltage adjustment via SPI
The device features output voltage adjustment via SPI. Therefore, the microcontroller can adjust the output
voltage during ACTIVE state using SPI registers (B2VCTRL, B2VCTRLN). Changes of the output voltage must be
limited to 50 mV at a time. That means that the register value of B2VCTRL and B2VCTRLN must only be
changed by +1 or -1. This is important to avoid false triggering of a Buck2 UV or Buck2 OV event. The settling
time of the output voltage for a 50 mV step is typically 50 µs, but it may be longer depending on the output
filter selection and load current condition.
Data Sheet
21
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2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Power converters and power management
Automatic use detection
The integrated automatic use detection for Buck2 allows the system to detect whether Buck2 is used in the
application. Therefore, the input voltage on the R2VSx pins is checked prior to startup of Buck2. If the pins are
connected to the output voltage, a voltage above the detection threshold is present at the pins and the device
assumes that Buck2 is required in the application. To indicate to the device that Buck2 is not required in the
application, the R2VSx pins should be connected to R2PGx.
The result of the detection is stored in HWDECT0.BUCK2AVA in order to allow the microcontroller to verify
correct detection for the specific application and to differentiate the result from a possible fault present on the
PCB.
Soft-start
The integrated soft-start feature limits the in-rush current and allows for smooth start-up of the converter.
Power-sequencing together with the other output rails is supported. Please refer to Chapter 5.3 for more
information.
Data Sheet
22
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2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Power converters and power management
4.2.2
Electrical characteristics Buck2
Table 6
Electrical characteristics Buck2
Tj = -40°C to 150°C, VR1VSx = 3.7 V to 35 V, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
VR1FB
–
Unit Note or
Test Condition
Number
Min.
Max.
4.0
Input voltage
VR2VSx
2.9
V
V
P_4.2.2.1
P_4.2.2.3
Output voltage adjustment VR2FB,RANGE 0.9
1.3
–
range
Output voltage adjustment VR2FB,STEP
step size
–
–
50
–
–
mV
V
VR2FB = VR2FB,RANGE P_4.2.2.4
Default output voltage
VR2FB
1.25
–
P_4.2.2.5
TLF30682
S01
Output voltage tolerance
Maximum output current
VR2FB,TOL
IR2IOUT
-2
–
+2
–
%
–
P_4.2.2.10
P_4.2.2.11
P_4.2.2.15
2.0
–
A
–
High-side switch on-
resistance
RDSOn,R2HS 60
113
180
mΩ
VR2VSx = 3.3 V
Low-side switch on-
resistance
RDSOn,R2LS
35
80
140
mΩ
VR2VSx = 3.3 V
P_4.2.2.16
–
–
–
–
–
P_4.2.2.17
P_4.2.2.18
Overcurrent protection
threshold
IR2,OCP
tR2,OCP
2.9
3.45
4.0
A
Overcurrent time out
95
–
100
–
115
–
µs
–
–
P_4.2.2.20
P_4.2.2.21
Minimum ON time
64
79
87
ns
Minimum ON time P_4.2.2.22
for internal HS
control signal. The
actual ON time on
the R2SWx pins is
dependent on the
application
design.
Overtemperature warning Tj,R2OT,WRN 130
threshold
145
135
190
180
160
150
205
195
°C
°C
°C
°C
1) Tj increasing
1) Tj decreasing
1) Tj increasing
1) Tj decreasing
P_4.2.2.23
P_4.2.2.24
P_4.2.2.25
P_4.2.2.26
Overtemperature warning Tj,R2OT,WRN 120
threshold
Overtemperatureshutdown Tj,R2OT,FLT
threshold
175
165
Overtemperatureshutdown Tj,R2OT,FLT
threshold
External power stage components
2)
Effective inductance
LR2
1.2
2.2
4.0
µH
P_4.2.2.28
Data Sheet
23
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Power converters and power management
Table 6
Electrical characteristics Buck2 (cont’d)
Tj = -40°C to 150°C, VR1VSx = 3.7 V to 35 V, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
66
Unit Note or
Test Condition
Number
Min.
Max.
2)3)
Effective output
capacitance
CR2
52
120
µF
P_4.2.2.30
P_4.2.2.31
ESR of output capacitance RR2C
1
5
30
mΩ
–
1) Not subject to production test, specified by design.
2) See Chapter 10 for additional information on the allowed L, C combinations.
3) Effective capacitance including de-rating across temperature range, bias voltage and aging. Electrolytic and ceramic
capacitors are supported.
4.2.2.1 Typical performance characteristics
Buck2 output voltage VR2FB
versus load current IR2IOUT
Data Sheet
24
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Power converters and power management
4.3
Post-regulator step-up converter – Boost1
4.3.1
Functional description Boost1
The device integrates a dedicated step-up converter to generate a 5 V output voltage rail from the Buck1
voltage. An asynchronous boost topology with internal low-side switch and an external diode is used.
Loop compensation
The Boost1 converter uses an internal compensation circuit with no need for external components.
For selection of the required external components please refer to Chapter 10.
Synchronization of the switching frequency with the other integrated converters as well as an external
synchronization signal is included.
Overcurrent protection
The device incorporates an overcurrent protection to protect the internal low-side switch of the boost
converter. Due to the nature of the boost topology the boost output rail is not protected against a short circuit
directly. However, indirect protection via an undervoltage protection and current limitation of the front-end
converter (Buck1) is available.
Automatic use detection
An automatic use detection is implemented for Boost1 which allows the system to detect if Boost1 is used in
the application. Therefore, the input voltage on the R3FB pin is checked prior to startup of Boost1. If the R3FB
pin is connected to the output voltage of Buck1 through the boost inductor and rectifying diode, a voltage
above the detection threshold is present at the pin and the device assumes that Boost1 is required in the
application. To indicate to the device that Boost1 is not required in the application, the R3FB pin should be
connected to R3PG. The result of the detection is stored in HWDECT0.BOOST1AVA in order to allow the
microcontroller to verify correct detection for the specific application and differentiate the result from a
possible fault present on the PCB.
Data Sheet
25
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2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Power converters and power management
4.3.2
Electrical characteristics Boost1
Table 7
Electrical characteristics Boost1
Tj = -40°C to 150°C, VR1VSx = 3.7 V to 35 V, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
VR1FB
5.0
Unit Note or
Test Condition
Number
Min.
2.7
–
Max.
4.5
–
Input voltage
VR3VS
V
–
P_4.3.2.1
P_4.3.2.2
P_4.3.2.3
P_4.3.2.4
P_4.3.2.5
Output voltage
VR3FB
V
–
–
–
–
Output voltage tolerance
Maximum output current
VR3FB,TOL
IR3IOUT
IR3,OCP
-2
–
2
%
250
740
–
–
mA
mA
Overcurrent detection
threshold
820
900
Overcurrent time out
tR3,OCP
170
220
260
µs
–
P_4.3.2.6
External power stage components
Effective inductance LR3
1)
3.8
5.5
1
6.8
10
20
9.8
18
50
µH
µF
P_4.3.2.8
P_4.3.2.10
P_4.3.2.11
1)2)
Effective output capacitance CR3
ESR of output capacitance RR3C
mΩ
–
1) See Chapter 10 for additional information on the allowed L, C combinations.
2) Effective capacitance including derating over the temperature range, bias voltage and aging. Electrolytic and ceramic
capacitors are supported.
4.3.2.1 Typical performance characteristics
Boost1 output voltage VR3FB
versus load current IR3IOUT
Data Sheet
26
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Power converters and power management
4.4
Support of external voltage rails
The device supports monitoring of two externally generated voltage rails via voltage monitors. Each voltage
monitor consists of an enable pin (VMxEN) to control the respective regulator and a monitoring input pin
(VMxFB) for monitoring the respective voltage rail. The expected voltage on the monitoring input is fixed. If
higher voltages should be monitored, an external voltage divider may be used to reduce the voltage to the
expected range.
Automatic use detection
The integrated automatic use detection for each voltage monitor allows the system to detect whether it is
used in the application.
The device assumes that an external power regulator is connected (and the voltage monitoring is used) when
it is possible to drive the respective enable pin "high". Conversely, to indicate to the device that a voltage
monitor is not required by the application, the respective enable pin VMxEN should be connected to ground.
The result of the detection is stored in HWDECT0.VM1AVA and HWDECT0.VM2AVA respectively, in order to
allow the microcontroller to verify correct detection for the specific application and differentiate the result
from a possible fault condition on the PCB.
Table 8
Electrical characteristics external voltage rails
Tj = -40°C to 150°C, VR1VSx = 3.7 V to 35 V, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
Enable signal: VMxEN
Output level – "high"
Output level – "low"
VVMxEN,high
VVMxEN,low
0.7
–
–
–
–
–
VIOVDD IVMxEN = -7 mA
P_4.4.0.1
P_4.4.0.2
P_4.4.0.3
0.7
–
V
IVMxEN = -5.5 mA
VVMxEN = 0.8 V
Internal pull-down current IVMxEN
10
µA
Monitoring signals: VMxFB
Nominal input voltage1)
VVMxFB,nom
IVMxFB
–
–
0.8
–
V
–
P_4.4.0.4
P_4.4.0.5
Input pull-up current
100
130
nA
VVMxFB = 0.8 V
1) For information on the monitoring thresholds please refer to Table 14 in Chapter 6.1.3.
Data Sheet
27
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Central functions
5
Central functions
5.1
Supply voltages
The device generates an internal supply voltage from the voltage supplied at the R1VSx pins. This supply
voltage, R1BTSV, is used to power the driver circuit for the power switches of Buck1. It cannot be used to
supply any external loads in the system.
To handle the dynamic gate drive current of the power switches, a ceramic capacitor for decoupling must be
placed between R1BTSV and the respective ground pin.
In order to operate the digital outputs of the device, a supply voltage is required at the IOVDD pin. Please refer
to Chapter 7.1 for detailed information.
Table 9
Electrical characteristics supply voltages
Tj = -40°C to 150°C, VR1VSx = 3.7 V to 35 V, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
Decoupling capacitor for internal supply
Internal supply decoupling –
connect between R1BTSV
and GND
0.8
1.0
1.2
µF
–
P_5.1.1
Data Sheet
28
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Central functions
5.2
Enable functionality
The device features an enable functionality which allows powering up the device using the ENA pin. For
example, this pin may be connected to the outside of the ECU or to a wake output of a CAN transceiver.
The pin is level-sensitive with a duration-based de-glitching where a "high" signal indicates the "enabled"
state. With respect to Figure 4, the enable signal is considered "high", when it is above the enable detection
threshold VENA,high for a minimum time of tENA,det. A signal above the detection threshold for a duration shorter
than tENA,filt is not considered a valid "high" signal.
Respectively, the enable signal is considered "low" when it is below VENA,low for a minimum time of tENA,det. A
signal below the detection threshold for a duration shorter than tENA,filt is not considered a valid "low" signal.
The state of the enable signal can be accessed at VMONSTAT0.ENA.
The device incorporates an enable event detection where a "low-to-high" transition or a "high-to-low"
transition of the enable signal is considered an enable event. Upon detection of an enable event, an interrupt
is generated (SYSSF1.ENA). Depending on the device state, an enable event may trigger a state transition
(refer to Chapter 8.3), for example power up the device.
An enable event does not disable the device automatically. It is up to the microcontroller to react to the
generated interrupt and react accordingly.
The state of the enable signal can be accessed at VMONSTAT0.ENA and may be used by the microcontroller
to determine the current state of the enable signal. This information may be used to differentiate between an
enable or disable condition on ECU level.
ENA
Enable
Signal
t
tENA,filt
tENA,det
Figure 4
Enable signal – timing enable event
5.2.1
ENA pin configurability
The ENA pin is by default configured to be edge triggered. The device can only detect an ENA event if the
voltage on the pin rises from a low level to a high level. The functionality of the ENA pin can be configured by
the microcontroller as edge-triggered or level-sensitive in register DEVCFG0.ENA_CONFIG.
If the configuration of the ENA pin is set to level-sensitive, then the device automatically re-enters the ACTIVE
state from the FAULT state if the ENA pin is high. That means that the device does not enter the LOCKED state
after three consecutive faults with the ENA pin configured to level-sensitive as long as the ENA pin is high.
If the device enters the DISABLED state on an SPI request to DEVCTRL/DEVCTRLN, then the DEVCFG0 register
is reset to the default value. The device can therefore only recognize an ENA event in DISABLED state if the ENA
pin has a low to high transition.
Data Sheet
29
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Central functions
Table 10
Electrical characteristics enable signal
Tj = -40°C to 150°C, VR1VSx = 3.7 V to 35 V, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
Enable signal – pin ENA
Input level – "high"
Input level – "low"
Input hysteresis
VENA,high
VENA,low
VENA,hys
IENA,high
IENA,low
1.30
1.00
250
–
1.60
1.20
400
3
2.00
1.40
550
5
V
VENA increasing
P_5.2.1
P_5.2.2
P_5.2.3
P_5.2.4
P_5.2.5
P_5.2.6
P_5.2.7
V
VENA decreasing
mV
µA
µA
µs
µs
–
Input current – "high"
Input current – "low"
VENA ≥ 2V
–
–
0.1
20
VENA ≤ 1V
Enable signal, filtering time tENA,filt
–
–
–
–
Enable signal, detection
time
tENA,det
40
–
–
5.2.2
Typical performance characteristics
ENA pin input levels VENA versus
junction temperature Tj
Data Sheet
30
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Central functions
5.3
Power sequencing and soft-start
The individual output rails are power sequenced to reduce the in-rush current during power-up. A passive
power sequencing method is used where the individual rails are enabled when the preceding rail is within its
total operating band, that is between the respective undervoltage and overvoltage fault thresholds.
Sequence of the output rails:
•
•
•
Buck1
Buck2, Boost1
(VM1), (VM2)
Power sequencing is active any time a power rail is enabled or disabled, for example at the transition into
ACTIVE.
In case a rail is not active, that is the automatic use detection has detected that a rail is not used, this rail is
skipped during the power sequencing and the subsequent rail is enabled.
Two conditions must to be fulfilled before the power sequence can proceed to the next stage:
•
•
The output voltage on the individual rails must be above the undervoltage threshold
The rise time must be completed before the next stage is reached
For example when Buck1 is ramped up the device waits until the output voltage is above the undervoltage
threshold and the rise time tBuck1 has elapsed before it initiates the ramping of Buck2 and Boost1. Under
normal operating conditions the output voltage on Buck1, Buck2 and Boost1 will cross their respective
undervoltage thresholds before the rise time has elapsed.
The undervoltage monitoring is enabled as soon as the corresponding rail is enabled. However, the
undervoltage event is only indicated once the voltage rail has crossed the undervoltage threshold for the first
time. The short-to-ground detection is active and used as a time out function for the power sequencing, this
means that, if a voltage rail is not valid within the short-to-ground detection time, a fault event is indicated.
Depending on the configured response to the short-to-ground event (see Table 25), the device may either
move into a different state or continue operation and sequencing.
The overvoltage monitoring is active as soon as the corresponding rails is enabled.
Data Sheet
31
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2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Central functions
R1VS or ENA
tSTARTUP
VBUCK1,UV
Actual value
BUCK1
tBUCK1
VBUCK2,UV
Actual value
BUCK2
tBUCK2
VBOOST, UV
Actual value
BOOST1
tBOOST1
VM1EN
VVM1,UV
Actual value
VM1
VM2EN
VVM2,UV
Actual value
VM2
tStartup,Total
tVM1*
tRD
ROT
Figure 5
Power sequencing
The microcontroller reset signal is released with a configurable delay once the microcontroller supply voltage
is within the operating band for a selectable time period (DEVCFG0.RESDEL). For generation of the
microcontroller reset signal (ROT), please refer to Chapter 7.3.
The external voltage regulator monitored by VM1 must have a rise time, tVM1, that is shorter than the short-to-
ground detection time, tVM1,StG (see Table 14).
Table 11
Electrical characteristics power sequencing
Tj = -40°C to 150°C, VR1VSx = 3.7 V to 35 V, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
300
Unit Note or
Test Condition
Number
Min.
Max.
Internal device start up time tSTARTUP
–
–
–
–
µs
µs
–
P_5.3.1
P_5.3.2
Output voltage rise time
Buck1
tBUCK1
320
VBUCK1 = 3.3 V
Data Sheet
32
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Central functions
Table 11
Electrical characteristics power sequencing (cont’d)
Tj = -40°C to 150°C, VR1VSx = 3.7 V to 35 V, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
320
Unit Note or
Test Condition
Number
Min.
Max.
Output voltage rise time
Buck2
tBUCK2
–
–
µs
VBUCK2 = 1.25 V
P_5.3.4
P_5.3.5
Output voltage rise time
Boost1
tBOOST1
–
640
–
µs
VBUCK1 = 3.3 V,
V
BOOST1 = 5.0 V
Data Sheet
33
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Central functions
5.4
Switching frequency generation and clock synchronization
The switching frequencies for the different integrated converters are generated by an integrated clock
generation and a clock manager. Synchronization to an external clock signal as well as generation of the
synchronization signal for external circuits is supported. Spread spectrum modulation for EMC/EMI
improvements is available for all converters.
SYNCI
Spread-
spectrum
Modulator
Internal
Clock
Generator
Clock
Synchroni-
zation
fMain
fMain
Main Clock
Selector
180°
180°
180°
Buck1
Selector
Buck2
Selector
Boost1
Selector
SYNCO
Selector
fSYNCO
fR1
fR2
fR3
Figure 6
Clock generation and clock manager
Main frequency generation
Figure 6 shows that the internal clock generation uses an internal main frequency to derive the switching
frequency for the power converters and the external synchronization signal. The main frequency of the system
can be adjusted using CLKCFG1 within a given range.
Synchronization
The power converters can be synchronized to an external clock signal (SYNCI) to improve EMC/EMI
performance and reduce cross-talk to the loads.
Table 12 shows the specification of the signal. The clock manager synchronizes the switching frequency to
this signal according to the configuration in the SPI registers. The synchronization functionality is disabled by
default.
To enable synchronization of the switching frequency, an external reference signal is required at the SYNCI pin
and the synchronization functionality must be enabled via SPI. The external clock source must not be
removed while the device is running in synchronized mode.
The device supports a dynamic change of the synchronization frequency during synchronization mode with
minimal disturbance of the output voltage. It is recommended to keep the same phase and change the
switching frequency with the next rising edge of the synchronization signal to minimize the impact on the
output voltage. The output voltage settles within a maximum time of 50 µs.
In addition, the device features a synchronization output signal SYNCO, which can be used to synchronize an
external switched-mode post-regulator. The output frequency is equal to the switching frequency of Buck1.
Data Sheet
34
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2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Central functions
The signal has a 50% duty cycle with a selectable phase shift of 0° or 180° with respect to the main clock. The
synchronization output is disabled by default. The synchronization output can be enabled via SPI.
In addition, the phase shift between the individual converters can be adjusted using CLKCFG0. The phase shift
is defined between rising edge of the clock signal and the rising edge of the switch node for the buck
converters and the falling edge of the boost converter respectively. Furthermore the converters Buck1 and
Buck2, as well as SYNCO can be controlled independently with a phase shift of 0° or 180° with respect to the
main clock.
Spread-spectrum modulation
The device incorporates spread-spectrum modulation in order to improve EMC/EMI performance. The spread-
spectrum modulation is applied to the main clock source, hence affects all power converters. The spread-
spectrum modulation is disabled by default and can be enabled via SPI register CLKCFG0.SSEN.
Table 12
Electrical characteristics frequency generation
Tj = -40°C to 150°C, VR1VSx = 3.7 V to 35 V, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
Internal clock source
Frequency
fMAIN
1800
2200
2500
kHz
Switching
P_5.4.1
frequency
selectable via SPI
Frequency tolerance
fMAIN,tol
-10
–
–
10
–
%
–
–
P_5.4.3
P_5.4.4
Frequency adjustment step fMAIN,step
100
kHz
size
Synchronization input signal SYNCI1)
Input level – "high"
Input level – "low"
Input level hysteresis
Input capacitance
Frequency range
Duty cycle
VSYNCI, high
VSYNCI, low
VSYNCI, hys
CSYNCI
0.7
–
–
–
VIOVDD VSYNCI increasing
P_5.4.5
P_5.4.6
P_5.4.7
P_5.4.8
P_5.4.9
P_5.4.10
P_5.4.11
–
0.8
–
V
VSYNCI decreasing
–
0.06
4
VIOVDD
pF
–
2)
–
15
2800
60
–
fSync
1600
40
–
2200
50
30
kHz
%
–
–
–
Phase delay between
ns
SYNCIN and switching edges
Output voltage settling time tSync
–
–
50
µs
–
P_5.4.12
Synchronization output signal SYNCO1)
Output level – "high"
Output level – "low"
Frequency
VSYNCO, high 0.7
–
–
VIOVDD IIOVDD = -7 mA
P_5.4.13
P_5.4.14
P_5.4.15
P_5.4.16
P_5.4.17
P_5.4.18
P_5.4.19
VSYNCO, low
–
–
–
–
–
–
–
0.7
–
V
IIOVDD = -5.5 mA
fMAIN
50
–
–
–
–
–
–
Duty cycle
–
%
–
–
–
–
–
Data Sheet
35
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Central functions
Table 12
Electrical characteristics frequency generation (cont’d)
Tj = -40°C to 150°C, VR1VSx = 3.7 V to 35 V, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
Spread spectrum modulation
Maximum modulation
variation from fMAIN,Range
-7.5
–
–
9
7.5
–
%
5 steps
P_5.4.22
P_5.4.23
Modulation frequency
kHz
–
1) The voltage levels on this pin are dependent on the IOVDD supply voltage provided (see Chapter 7.1)
2) Not subject to production test, specified by design.
5.4.1
Typical performance characteristics
Switching frequency fMAIN
versus junction temperature Tj
Data Sheet
36
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Central functions
5.5
IOVDD - Overvoltage and undervoltage detection
The IOVDD pin is the supply voltage input for the communication interface towards to the microcontroller. The
pin can be supplied from one of the voltages generated by the TLF30682QVS01.
The TLF30682QVS01 monitors the voltage on the IOVDD pin. An overvoltage event or an undervoltage event
triggers a reset and pulls ROT to GND. As long as no reset event occurs, ROT is "high" (VIOVDD) due to an internal
pull-up resistor and follows VIOVDD. Figure 7 shows an example of various events with delay and deglitching
times.
In addition to the undervoltage and overvoltage detection the TLF30682QVS01 also features a short-to-
ground detection for the IOVDD voltage. If the IOVDD voltage is below the undervoltage threshold for a period
longer the short-to-ground detection time, then the device generates a short-to-ground event. A short-to-
ground event on IOVDD triggers a hard reset in the device and the SYSSF0.IOVDDUV.
VIOVDD
VIOVDD,OV
VIOVDD,UV
1 V
t
tIOVDD,deg
tRD
tIOVDD,deg
tRD
tRD
ROT
t
Figure 7
Table 13
Overvoltage and undervoltage detection
Electrical characteristics IOVDD - Overvoltage and undervoltage detection
Tj = -40°C to 150°C, VR1VSx = 3.7 V to 35 V, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
–
Unit Note or
Test Condition
Number
Min.
Max.
IOVDD - Overvoltage
threshold
VIOVDD,OV
5.5
5.8
V
P_5.6.1
P_5.6.2
P_5.6.3
P_5.6.4
IOVDD - Overvoltage
hysteresis
VIOVDD,OV,Hys 0.4
–
–
–
2.25
2.86
2.25
%
V
IOVDD - Undervoltage
threshold
VIOVDD,UV
2.74
IOVDD - Undervoltage
hysteresis
VIOVDD,UV,Hys 0.4
%
Deglitching time
tIOVDD,deg
8
–
20
µs
P_5.6.5
P_5.6.6
Short-to-ground detection tIOVDD,StG
3.6
4.0
4.4
ms
time
Data Sheet
37
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Monitoring functions
6
Monitoring functions
The device incorporates various features for using the device as a supply backbone. These features include:
•
•
Integrated voltage monitors for the output voltages, see Chapter 6.1.
Integrated window watchdog for supervising microcontroller timing, see Chapter 7.5.
6.1
Voltage monitoring
6.1.1
Monitoring of R1VSx – battery supply
If the battery voltage drops below VR1VSx,UV, then the undervoltage monitoring feature for R1VSx sets the SPI
status flag GSF.R1VSxUV.
6.1.2
Monitoring of output voltages
The voltage monitoring function supervises the voltages on the feedback pins R1FB, R2FB and R3FB of the
switched-mode converters with respect to the thresholds for undervoltage and overvoltage, see Table 14.
Signals exceeding the respective thresholds for a time shorter than the deglitching time are not detected as a
fault event. When a signal exceeds a threshold for a duration longer than the deglitching time, an undervoltage
event or an overvoltage event is generated. If the voltage is below the undervoltage threshold for a duration
longer than the short-to-ground detection time, then the device additionally generates a short-to-ground
event. In addition to the long short-to-ground detection time the monitoring also features deep undervoltage
detection for Buck1 and Buck2. If the voltage on the feedback pins R1FB or R2FB drops below the deep
undervoltage threshold for a duration longer than the deglitching time, then a short-to-ground event is
generated.
Depending on the type of fault, the appropriate actions are executed as described in Chapter 8.3.
The voltage monitoring is activated automatically when the respective power rail is enabled. For information
on the behavior during sequencing, please refer to Chapter 5.3.
6.1.3
Monitoring of external voltage rails
The device supports monitoring of two external voltage rails on the pins VM1FB, VM2FB. The external voltages
are compared using window comparators against predefined thresholds. These thresholds define levels
relative to the assumed nominal input voltage according to Table 14. Resistor dividers are to be used to map
the output voltage of the respective voltage rail externally.
Signals exceeding the thresholds for a time shorter than the deglitching time are not detected as a fault event.
When a signal exceeds the thresholds for a duration longer than the deglitching time, an undervoltage or an
overvoltage event is generated. If the voltage is below the undervoltage threshold for a duration longer than
the short-to-ground detection time, then the device generates an additional short-to-ground event.
Depending on the type of fault, the appropriate actions are executed as described in Chapter 8.3.
Voltage monitoring is enabled when the respective power rail is enabled. For information on the behavior
during sequencing, please refer to Chapter 5.3.
If an overvoltage event or a short-to-ground event occurs, then the device shuts down the respective voltage
rail to protect the load and the device.
Data Sheet
38
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Monitoring functions
6.1.4
Monitoring of internal supply voltages and bandgaps
The integrated voltage monitoring function monitors internal supply voltages in order to ensure proper
operation. In case proper operation can not be ensured, the device reacts accordingly, see Table 26.
The device features two independent voltage references:
•
•
for the voltage regulators
for voltage monitoring
The device supervises the difference between the voltage references internally.
In case the difference exceeds a predefined warning threshold, the device generates an interrupt and sets one
of the following status flags depending on the internal root cause: SYSSF1.BGWARN1 or SYSSF1.BGWARN2.
Based on this information the system can be designed to react appropriately.
In case the difference exceeds a predefined fault threshold the device will shut down and change into FAULT
state, as proper operation of the device can not be ensured. SYSSF0.BGFLT1 or SYSSF0.BGFLT2 is set
depending on the internal root cause.
6.1.5
Electrical characteristics
Table 14
Electrical characteristics voltage monitoring
Tj = -40°C to 150°C, VR1VSx = 3.7 V to 35 V, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Input voltage battery supply – (R1VSx-AGx)
Max.
Undervoltage threshold
VR1VSx,UV
4.9
5.025 5.15
V
–
P_6.1.5.1
P_6.1.5.3
Output voltage Buck1 – (R1FB-AGx)
Overvoltage threshold
VBuck1,OV
+6.0
+8.0
+10
%
Referenced to
Buck1 nominal
output voltage
VR1FB
Overvoltage hysteresis
Undervoltage threshold
VBuck1,OV,Hys 0.4
VBuck1,UV -6.0
–
2.25
-10
%
%
P_6.1.5.5
P_6.1.5.7
-8.0
Referenced to
Buck1 nominal
output voltage
VR1FB
Undervoltage hysteresis
VBuck1,UV,Hys 0.4
VBuck1,DUV -38
–
2.25
-42
%
%
–
–
P_5.2.1.6
P_6.1.5.9
Deep undervoltage
threshold
-40
Deep undervoltage
hysteresis
VBuck1,DUV,Hys 0.8
3.15
%
–
P_6.1.5.10
Deglitching time
tBuck1,deg
8
-
20
µs
–
–
P_6.1.5.11
P_6.1.5.12
Short-to-ground detection tBuck1,StG
2.7
3.0
3.3
ms
time
–
–
–
–
–
–
–
–
P_6.1.5.13
P_6.1.5.14
Data Sheet
39
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Monitoring functions
Table 14
Electrical characteristics voltage monitoring (cont’d)
Tj = -40°C to 150°C, VR1VSx = 3.7 V to 35 V, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
Output voltage Buck2- (R2FB-AGx)
Overvoltage threshold
VBuck2,OV
+6.0
+8.0
+10
%
Referenced to
Buck2 nominal
output voltage
VR2FB
P_6.1.5.16
Overvoltage hysteresis
Undervoltage threshold
VBuck2,OV,Hys 0.4
VBuck2,UV -6.0
–
2.25
-10
%
%
–
P_6.1.5.18
P_6.1.5.20
-8.0
Referenced to
Buck2 nominal
output voltage
VR2FB
Undervoltage hysteresis
VBuck2,UV,Hys 0.4
VBuck2,DUV -38
–
2.25
-42
%
%
–
–
P_6.1.5.22
P_6.1.5.23
Deep undervoltage
threshold
-40
Deep undervoltage
hysteresis
VBuck2,DUV,Hys 0.8
3.15
%
–
P_6.1.5.24
Deglitching time
tBuck2,deg
8
-
20
µs
–
–
P_6.1.5.25
P_6.1.5.26
Short-to-ground detection tBuck2,StG
2.7
3.0
3.3
ms
time
Output voltage Boost1 – (R3FB-AGx)
Overvoltage threshold
VBoost1,OV
+6.0
+8.0
+10
%
Referenced to
Boost1 nominal
output voltage
VR3FB
P_6.1.5.28
Overvoltage hysteresis
Undervoltage threshold
VBoost1,OV,Hys 0.4
VBoost1,UV -6.0
–
2.25
-10
%
%
–
P_6.1.5.30
P_6.1.5.32
-8.0
Referenced to
Boost1 nominal
output voltage
VR3FB
Undervoltage hysteresis
Deglitching time
VBoost1,UV,Hys 0.4
–
2.25
20
%
–
–
–
P_6.1.5.34
P_6.1.5.35
P_6.1.5.36
tBoost1,deg
8
-
µs
ms
Short-to-ground detection tBoost1,StG
2.7
3.0
3.3
time
External voltage monitors VM1 (VM1FB-AGx)
Overvoltage threshold
VVM1,OV
+6.0
+8.0
–
+10
%
%
Referenced to VM1 P_6.1.5.38
nominal reference
voltage VVM1FB,nom
Overvoltage hysteresis
VVM1,OV,Hys
0.4
2.25
–
P_6.1.5.40
Data Sheet
40
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Monitoring functions
Table 14
Electrical characteristics voltage monitoring (cont’d)
Tj = -40°C to 150°C, VR1VSx = 3.7 V to 35 V, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
Undervoltage threshold
VVM1,UV
-6.0
-8.0
-10
%
Referenced to VM1 P_6.1.5.42
nominal reference
voltage VVM1FB,nom
Undervoltage hysteresis
Deglitching time
VVM1,UV,Hys
tVM1,deg
0.4
8
–
2.25
20
%
–
–
–
P_6.1.5.44
P_6.1.5.45
P_6.1.5.46
-
µs
ms
Short-to-ground detection tVM1,StG
2.7
3.0
3.3
time
External voltage monitor VM2 (VM2FB-AGx)
Overvoltage threshold
VVM2,OV
+6.0
+8.0
+10
%
Referenced to VM2 P_6.1.5.48
nominal reference
voltage VVM2FB,nom
Overvoltage hysteresis
Undervoltage threshold
VVM2,OV,Hys
VVM2,UV
0.4
–
2.25
-10
%
%
–
P_6.1.5.50
-6.0
-8.0
Referenced to VM2 P_6.1.5.52
nominal reference
voltage VVM2FB,nom
Undervoltage hysteresis
Deglitching time
VVM2,UV,Hys
tVM2,deg
0.4
8
–
2.25
20
%
–
–
–
P_6.1.5.54
P_6.1.5.55
P_6.1.5.56
-
µs
ms
Short-to-ground detection tVM2,StG
2.7
3.0
3.3
time
6.2
Thermal protection
The device incorporates multiple independent temperature sense elements to monitor its temperature,
specifically of the high-voltage regulator Buck1 and the post-regulator Buck2. Please refer to the respective
sections for more information on the individual blocks.
A third temperature sensor is located in the monitoring block of the device. Table 15 shows the temperature
thresholds for the sensor in the monitoring block.
While the temperature is monitored in the individual blocks, the thermal shutdown (TSD) events of these
measurements are globally collected. For each individual warning and fault event an appropriate bit in the SPI
registers OTSF0 and OTSF1 is set.
An overtemperature warning event for any of the three temperature sensors generates an interrupt for the
microcontroller.
A thermal shutdown event (TSD) for any of the three sensors triggers a move to the FAULT state. If a thermal
shutdown event occurs, then the fault time is extended to approximately one second (see Table 27) in order
to allow the temperature to drop prior to the restart of the device.
Data Sheet
41
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Monitoring functions
Table 15
Electrical characteristics temperature sensor monitoring block
VR1VSx = 3.7 V to 35 V; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
145
Unit Note or
Test Condition
Number
Min.
Max.
Overtemperature warning
threshold
Tj,MONOT,WRN 130
Tj,MONOT,WRN 120
Tj,MONOT,FLT 175
Tj,MONOT,FLT 165
160
°C
°C
°C
°C
1) Tj increasing
1) Tj decreasing
1) Tj increasing
1) Tj decreasing
P_6.2.0.1
P_6.2.0.2
P_6.2.0.3
P_6.2.0.4
Overtemperature warning
threshold
135
190
180
150
205
195
Overtemperature fault
threshold
Overtemperature fault
threshold
1) Not subject to production test, specified by design.
Data Sheet
42
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Microcontroller interface and supervisory functions
7
Microcontroller interface and supervisory functions
This section describes the connections between the device and the microcontroller.
Figure 8 shows that the microcontroller and the device use several signals for communication and for mutual
monitoring of correct operation. An SPI configures the device and monitors status information. A dedicated
interrupt signal of the device notifies the microcontroller about any interaction required. To ensure safe
operation of the microcontroller a watchdog trigger line (WDI) is available. The device can use a reset-output
signal (ROT) to reset the microcontroller if required.
μC
TLF30682
IOVDD
INT
INTERRUPT INPUT
Interrupt Generator
SCS
SCL
SDI
SPI
SPI
SDO
μC
TRIGGER OUTPUT
WDI
Window
Wacthdog
Series
protection
resistors
ROT
Reset
Control
Reset Generator
Figure 8
Interface between the TLF30682 and microcontroller
7.1
Microcontroller interface supply – IOVDD pin
The device can handle microcontrollers with different IO supply voltages. This is accommodated by a
dedicated supply pin (IOVDD) at which the IO supply voltage is externally supplied to the device. This voltage
then drives the logic output pins to the microcontroller. It is also used to determine the input thresholds for
the input cells. The affected pins are:
•
•
•
•
•
•
•
•
•
SCS
SCL
SDI
SDO
INT
ROT
WDI
SYNCI
SYNCO
Data Sheet
43
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Microcontroller interface and supervisory functions
7.1.1
Electrical characteristics
Table 16
Electrical characteristics microcontroller interface supply
Tj = -40°C to 150°C, VR1VSx = 3.7 V to 35 V, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
Microcontroller interface
Supply voltage
VIOVDD
IIOVDD
3.0
–
–
5.5
–
V
–
P_7.1.1.1
P_7.1.1.2
Supply current
2.5
mA
VIOVDD= 3.3 V
SDO, SDI and SCL
switching at
10 MHz
SYNCI and SYNCO
switching at
2.5 MHz
SCS, ROT, INT and
WDI are static
signals
Data Sheet
44
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Microcontroller interface and supervisory functions
7.2
Serial peripheral interface (SPI)
SPI introduction
7.2.1
The serial peripheral interface (SPI) is a synchronous serial data link that operates in full duplex mode. The SDI
pin receives data and the SDO pin transmits data.
The device communicates in slave mode where the master, for example the microcontroller, provides a clock
on the SCL pin and initiates the data frame. The device is addressed via a dedicated chip select line (SCS pin).
Functional description SPI
The data on pin SDI is captured on the falling edge of the SPI clock signal (pin SCL) and shifted on the rising
edge of the SPI clock signal. The data on pin SDO is set on the falling edge of SPI clock signal (pin SCL) and
shifted on the rising edge of the SPI clock signal. The SPI master should capture the data on the falling edge of
the SPI clock signal.
An SPI command consists of the following (Figure 9):
•
•
•
•
command bit CMD
6 address bits A0-A5
8 data bits D0-D7
parity bit P
The SPI response for read operations consists of the following:
•
•
•
•
command bit CMD
6 status bits S0-S5
8 data bits D0-D7
parity bit P
For a write operation, the data read on SDI is looped back via SDO.
t trail
t lead
t spi_clk
t interframe
SCL
t max frame duration
SCS
P
P
P
CMD
A5
A5
A4
A4
A3
A2
A2
A1
A1
A0
A0
D7
D7
D7
D6
D6
D6
D5
D5
D5
D4
D4
D4
D3
D3
D3
D2
D2
D2
D1
D1
D1
D0
D0
D0
P
P
P
SDI
1'b1
A3
SDO (W)
1'b1
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
SDO (R)
Figure 9
SPI frame format
The command bit in the SPI command is set to 1’b0 for a read and 1’b1 for a write operation. In the reply, the
command bit is always set to 1’b1.
The parity bit P is calculated from the 15 data bits of the SPI message consisting of the CMD bit, the 6 address
and 8 data bits. The parity bit is set to ‘1’, if the number of ‘1’s in the data bits is odd, that is it is a XOR function
of the 15 data bits. The receiver of the SPI message should verify the parity bit prior processing the payload of
the message.
Data Sheet
45
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Microcontroller interface and supervisory functions
The SPI performs several checks on the communication to ensure proper behavior:
•
•
•
If a parity fault is detected, then the device ignores the data, sets the SPI status bit SPISF.PAR and
generates an interrupt.
If a write operation to an invalid address occurs, then the device ignores the data, sets the SPI status
SPISF.ADDR and generates an interrupt.
If a read operation from an invalid address occurs, then the device reads all data bits as zero and sets the
parity bit to a wrong value to indicate an incorrect message to the SPI master. In addition the device sets
the SPI status bit SPISF.ADDR and generates an interrupt.
•
•
If a write operation with an incorrect number of SPI clock cycles occurs while SCS is "low", then the device
ignores the data, sets the SPI status SPISF.LEN and generates an interrupt.
If a read operation with an incorrect number of SPI clock cycles occurs, then the device sets the SPI status
SPISF.LEN and generates an interrupt to indicate an invalid data message to the SPI master. The SDO pin
provides the data during this operation. At the end of the message it indicates its correctness.
•
If the frame duration exceeds the maximum frame time tSPI_fl, then the device terminates communication
by disabling the output driver of the SDO pin. In addition the device sets the SPI status bit SPISF.DUR and
generates an interrupt.
Interrupts on SPI errors are initiated only after SCS is driven "high" or after a frame time-out occurs.
Data Sheet
46
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Microcontroller interface and supervisory functions
7.2.2
SPI write access to protected registers
Certain registers are protected against accidental write operations.
These so-called protected registers are implemented in pairs where a protected register (for example
PWDCFG0) is used to store a configuration request, while an associated read-only register (for example
RWDCFG0) is used to store the currently active configuration.
By default, write access to protected registers is disabled. The status of the protection can be checked using
PROTSTAT.LOCK.
Write access must be enabled using the UNLOCK sequence prior to updating the registers. After completing
the register update, the configuration must be activated using the LOCK sequence. This disables the write
access to the protected register and copies the data to the read-only registers.
After the LOCK sequence an internal configuration time of maximum of 60 µs has to be considered to ensure
that the new configuration is applied in the device.
Read access to protected configuration registers is always possible. Read operations invert the data.
The device does not support updating a single protected register. The microcontroller must ensure that all
protected registers are configured properly by writing a new value into particular registers and by verifying the
content of unchanged registers.
UNLOCK sequence
An UNLOCK sequence consists of four consecutive key bytes (1: ABH; 2: EFH; 3: 56H; 4: 12H) written into the
PROTCFG register. The respective SPI write operations must be atomic, so that they are not interrupted by an
SPI write operation to a different register. Read operations to any register are permitted. The progress of the
UNLOCK sequence can be monitored in the PROTCFG register where the respective key bit is set for each
correctly written key byte. If an incorrect UNLOCK sequence occurs due to a wrong key or an SPI write
operation to a different address, then the device resets the UNLOCK sequence and clears all key bits. The
device sets the SPISF.LOCK bit and generates an interrupt. The microcontroller must restart the UNLOCK
sequence.
LOCK sequence
A LOCK sequence consists of four consecutive key bytes (1: DFH; 2: 34H; 3: BEH; 4: CAH) written into the
PROTCFG register. The respective SPI write operations must be atomic, so that they are not interrupted by an
SPI write operation to a different register. Read operations to any register are permitted. The progress of the
LOCK sequence can be monitored in the PROTCFG register where the respective key bit is set for each
correctly written key byte. In case of an incorrect LOCK sequence, that is a wrong key or an SPI write operation
to a different address, then the device resets the LOCK sequence and clears all key bits. The device sets the
SPISF.LOCK bit and generates an interrupt. The microcontroller must restart the LOCK sequence.
Data Sheet
47
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Microcontroller interface and supervisory functions
7.2.3
SPI write initiated state transition request and regulator configuration
State machine transitions and configuration of output rails can be performed with direct write access to
dedicated registers. A defined protocol protects the registers from unintended changes.
In order to request a state transition and/or a change of the configuration of an output rail the request data
must be written to two separate, inverted registers (DEVCTRL and DEVCTRLN). The write operation must be
atomic with no other SPI write operation to a different address interrupting the initial write. The data is
applied on the rising edge of the CS at the end of the second command.
If an invalid protocol occurs, the device rejects the request, sets the SPI status flag SPISF.DEVCTRL and
generates an interrupt.
The following items are invalid requests:
•
•
An SPI write operation to another address interrupting the write operation to DEVCTRL and DEVCTRLN.
The data in DEVCTRL and DEVCTRLN is not consistent.
If an invalid state transition request occurs, according to the state machine in Chapter 8, the device ignores
the transition request without generating an interrupt. The device executes the change in configuration of
output rails.
7.2.4
Configuration of Buck2 output voltage via SPI
The output voltage of Buck2 can be configured with direct write access to dedicated registers. A specific
protocol is used to avoid unintentional changes to the registers.
In order to request a change of the Buck2 output voltage the configuration data must be written to two
separate, inverted registers (B2VCTRL and B2VCTRLN). The write operation must be atomic with no other SPI
write operation to a different address interrupting the initial write. The data is applied on the rising edge of the
CS at the end of the second command.
If an invalid protocol occurs, the device rejects the request, sets the SPI status flag SPISF.B2VCTRL and
generates an interrupt.
The following items are invalid requests:
•
•
An SPI write operation to another address interrupting the write operation to B2VCTRL and B2VCTRLN.
The data in B2VCTRL.B2VOUTF and B2VCTRLN.B2VOUTF is not consistent.
If a Buck2 output voltage configuration request is invalid, the device ignores the request without generating
an interrupt.
Data Sheet
48
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Microcontroller interface and supervisory functions
7.2.5
Electrical characteristics
Table 17
Electrical characteristics SPI
Tj = -40°C to 150°C, VR1VSx = 3.7 V to 35 V, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
SPI chip select – SCS
Valid input level – "high"
Valid input level – "low"
Input hysteresis
VSCS, high
VSCS, low
VSCS, hys
ISCS
0.7
–
–
–
VIOVDD VSCS increasing
P_7.2.5.1
P_7.2.5.2
P_7.2.5.3
P_7.2.5.4
P_7.2.5.5
–
0.8
–
V
VSCS decreasing
–
0.06
-55
4
VIOVDD
µA
Pull-up current
-180
–
–
VIOVDD ≤ 5.0 V
1)
Input capacitance
CSCS
15
pF
SPI clock, pin SCL
Valid input level – "high"
Valid input level – "low"
Input hysteresis
VSCL, high
VSCL, low
VSCL, hys
ISCL
0.7
–
–
–
VIOVDD VSCL increasing
P_7.2.5.6
P_7.2.5.7
P_7.2.5.8
P_7.2.5.9
P_7.2.5.10
–
0.8
–
V
VSCL decreasing
–
0.06
-55
4
VIOVDD
µA
Pull-up current
-180
–
–
VIOVDD ≤ 5.0 V
1)
Input capacitance
CSCL
15
pF
SPI data input, pin SDI
Valid input level – "high"
Valid input level – "low"
Input hysteresis
VSDI, high
VSDI, low
VSDI, hys
ISDI
0.7
–
–
–
VIOVDD VSDI increasing
P_7.2.5.11
P_7.2.5.12
P_7.2.5.13
P_7.2.5.14
P_7.2.5.15
–
0.8
–
V
VSDI decreasing
–
0.06
135
4
VIOVDD
µA
Pull-down current
Input capacitance
–
330
15
VSDI = VIOVDD
1)
CSDI
–
pF
SPI data output, pin SDO
Output level – "high"
Output level – "low"
Output rise time
VSDO, high
VSDO, low
tSDO,rise
tSDO,fall
0.7
–
–
–
–
–
4
–
–
VIOVDD ISDO = -7 mA
P_7.2.5.16
P_7.2.5.17
P_7.2.5.18
P_7.2.5.19
P_7.2.5.20
P_7.2.5.21
0.7
25
25
15
10
V
ISDO = -5.5 mA
–
ns
ns
pF
µA
CSDO,Load = 50 pF
Output fall time
–
CSDO,Load = 50 pF
1)
Output tristate capacitance CSDO,tri
–
Output tristate leakage ISDO,tri
-10
–
1) Not subject to production test, specified by design.
Data Sheet
49
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Microcontroller interface and supervisory functions
O
P
J
SCS
L
N
C
E
D
M
A
B
K
SCL
SDI
F
G
H
Q
I
SDO
A : t SPI_wsclkl
B : t SPI_wsclkh
C : t SPI_clk
D : t SPI_clkr
E : t SPI_clkf
F : t SPI_su
G : t SPI_hi
H : t SPI_a
I : t SPI_v
J : t SPI_fl
K : t SPI_dis
L : t SPI_lead
M : t SPI_lag
N : t SPI_td
O : t SPI_csf
P : t SPI_csr
Q : t SPI_dr
Figure 10 SPI timing
Table 18
Electrical characteristics SPI timing
Tj = -40°C to 150°C, VR1VSx = 3.7 V to 35 V, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
CLK_SPI operating
frequency
fSPI_clk
–
–
10
MHz –
P_7.2.5.22
CLK signal duty cycle DSCL
45
45
45
–
50
–
55
%
–
P_7.2.5.23
P_7.2.5.24
P_7.2.5.25
P_7.2.5.26
P_7.2.5.27
P_7.2.5.28
P_7.2.5.29
P_7.2.5.30
P_7.2.5.31
CLK_SPI "high" time tSPI_wsclkh
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
CLK_SPI "low" time
CLK_SPI fall time
CLK_SPI fall time
CLK_SPI rise time
CLK_SPI rise time
CLK_SPI lead time
CLK_SPI lag time
tSPI_wsclkl
tSPI_clkf
tSPI_clkf
tSPI_clkr
tSPI_clkr
tSPI_lead
tSPI_lag
–
–
–
–
100
fSPI_clk < 1 MHz
fSPI_clk ≥ 1 MHz
fSPI_clk < 1 MHz
fSPI_clk ≥ 1 MHz
–
–
0.1/fSPI_clk
–
–
100
–
–
0.1/fSPI_clk
100
50
–
–
–
–
–
SPI chip select (SCS) tSPI_csr
rise time
–
200
tSPI_lead = 100 ns P_7.2.5.32
tSPI_lead > 100 ns P_7.2.5.33
tSPI_lead = 100 ns P_7.2.5.34
tSPI_lead > 100 ns P_7.2.5.35
SPI chip select (SCS) tSPI_csr
rise time
–
–
–
–
–
0.2 × tSPI_lead ns
200 ns
0.2 × tSPI_lead ns
ns
SPI chip select (SCS) tSPI_csf
rise time
–
SPI chip select (SCS) tSPI_csf
fall time
–
SPI data input (SDI)
setup
tSPI_su
10
–
–
P_7.2.5.36
Data Sheet
50
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Microcontroller interface and supervisory functions
Table 18
Electrical characteristics SPI timing (cont’d)
Tj = -40°C to 150°C, VR1VSx = 3.7 V to 35 V, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
SPI data input (SDI)
hold time
tSPI_hi
10
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ms
–
P_7.2.5.37
SPI data output (SDO) tSPI_v
valid after CLK_SPI
–
36 +
(0.1/fSPI_clk)
CSDO,load = 50 pF P_7.2.5.38
fSPI_clk > =1 MHz
SPI data output (SDO) tSPI_v
valid after CLK_SPI
–
136
35
CSDO,load = 50 pF P_7.2.5.39
f
SPI_clk < 1 MHz
SPI write propagation tSPI_wpd
delay SDI to SDO
–
–
P_7.2.5.40
SPI data output (SDO) tSPI_a
access
–
50
CSDO,load = 50 pF P_7.2.5.41
P_7.2.5.42
CSDO,load = 50 pF P_7.2.5.43
SPI data output (SDO) tSPI_lag
lag
50
–
–
–
SPI data output (SDO) tSPI_dis
disable time
100
–
Sequential transfer
delay
tSPI_td
350
–
–
–
P_7.2.5.44
P_7.2.5.45
Frame duration (SCS tSPI_fl
1.85
"low")
Data Sheet
51
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Microcontroller interface and supervisory functions
7.3
Reset signal ROT
Reset output pin ROT
The reset output pin ROT is an open drain structure. As soon as a reset condition occurs, the ROT pin is pulled
below VROT,low. Once the internal reset signal is released, an internal pull-up current pulls the ROT pin towards
the microcontroller supply voltage VIOVDD. An external pull-up resistor may be connected between the ROT and
IOVDD pins to speed up the transition. As soon as all events leading to the reset are cleared and the reset delay
time expires, the device releases the internal reset signal.
Reset events
Several different internal events can trigger an activation of the reset signal. Please refer to Table 26 for
detailed information on the respective events. Additionally the reset signal is activated when voltage supply
rails are out of their total operating band. Information on the respective voltage rails can be found in Table 25.
Sometimes the activation of the reset is coupled with a deactivation of the supply signals to generate a hard
reset. During a hard reset the ROT pin is forced "low" and the supply rails of the microcontroller are turned off.
During a soft reset the ROT pin is forced "low", while the supply voltages remain in operation.
7.3.1
Electrical characteristics – ROT pin
Table 19
Electrical characteristics ROT pin
Tj = -40°C to 150°C, VR1VSx = 3.7 V to 35 V, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
Reset output pin ROT
Pull-up current
IROT,high
VROT,low
VROT,low
tROT,fall
-180
-120
–
µA
V
VROT ≤ 2.0V
P_7.3.1.1
P_7.3.1.2
P_7.3.1.3
P_7.3.1.5
Output level – "low"
Output level – "low"
–
–
–
–
–
–
0.4
0.4
25
VIOVDD = 5.0 V
ROT = 3.5 mA
VIOVDD = 3.3 V
ROT = 3.5 mA
I
V
I
Output fall time
Reset timing
ns
CROT,load = 50 pF
Reset cycle time
tcycle
tRD
–
10
–
–
µs
–
–
P_7.3.1.6
P_7.3.1.7
Reset delay time –
adjustment range
20
2000
tcycle
1)
Reset delay time – default
value
–
100
–
tcycle
P_7.3.1.8
1) The default configuration for the reset contributor might not generate a reset at the first start up of the device.
Data Sheet
52
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Microcontroller interface and supervisory functions
7.4
Interrupt signal INT
An interrupt is generated to inform the connected microcontroller that a non-severe event has occurred. This
allows the microcontroller to perform proper action based on the source of the interrupt. A single low-active
interrupt line is used.
If one or more new flags in the interrupt flag registers (Chapter 9.1.5) are set, then the device indicates an
interrupt to the microcontroller.
Interrupt pin INT
The interrupt pin INT is a push-pull output using the microcontroller supply voltage VIOVDD
.
The device indicates an interrupt by pulling the INT pin "low". If all register flags are cleared via SPI, then the
device drives the interrupt line "high".
The interrupt signal is subject to a minimum "low" time, tINT, which means that the interrupt pin will remain
"low" for this time even if the interrupt is serviced faster. The implemented interrupt minimum "high" timing
keeps the interrupt "high" for a minimum time of tINT,high. If a new interrupt is triggered during this time period,
the interrupt signal remains "high" and indicates the interrupt after the minimum "high" time, tINT,high, elapses.
The interrupt time-out, tINTTO, is implemented after which the device drives the interrupt signal "high",
regardless of whether the interrupt is serviced or not. In this case the device generates a missed interrupt
event and sets GSF.INTMISS. This does not generate another interrupt. The microcontroller must read this
flag autonomously.
7.4.1
Electrical characteristics – INT pin
Table 20
Electrical characteristics INT pin
Tj = -40°C to 150°C, VR1VSx = 3.7 V to 35 V, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
Interrupt signal INT
Output level – "high"
Output level – "low"
Output rise time
VINT,high
VINT,low
tINT,rise
tINT,fall
tINT,low
0.7
–
–
–
VIOVDD IINT = -7 mA
P_7.4.1.1
P_7.4.1.2
P_7.4.1.3
P_7.4.1.4
P_7.4.1.5
–
0.7
25
25
110
V
IINT = -5.5 mA
CINT,load = 50 pF
CINT,load = 50 pF
–
–
–
ns
ns
µs
Output fall time
–
–
Minimum interrupt "low"
time
90
100
Interrupt "low" time-out
tINTTO
270
270
300
300
330
µs
ROT signal for the P_7.4.1.6
microcontroller
must be released:
ROT = “high”
Minimum interrupt "high"
time
tINT,high
330
µs
–
P_7.4.1.7
Data Sheet
53
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Microcontroller interface and supervisory functions
7.5
Window watchdog
Principle of operation
The integrated window watchdog (WWD) can monitor the microcontroller. The monitored microcontroller
must provide periodical triggering during the "open window". A trigger signal can consist of a falling edge on
the WDI pin or an SPI write operation to the register WWDSCMD, depending on the configuration. Failure to
provide correct trigger signals will lead to an increase of the window watchdog failure counter, which is used
to monitor the fault events. If the window watchdog failure counter reaches a configurable threshold, it then
triggers an appropriate response.
Normal operation
Within the "open window" a trigger signal is expected. If the device receives a trigger signal during the "open
window", the window watchdog then terminates the "open window" cycle and starts the "closed window"
cycle with a duration of tWD,CW, followed by another "open window" cycle. If the window watchdog error
counter is greater than zero, any valid window watchdog trigger signal decrements the window watchdog
error counter by 1. This does not generate an interrupt.
In normal operation no trigger signal is allowed during the "closed window". If the device receives a trigger
signal within the "closed window", the window watchdog recognizes an invalid WWD trigger signal. The
window watchdog terminates the "closed window" cycle with an invalid trigger signal and starts another
"open window" cycle. Any invalid WWD trigger signal increments the window watchdog error counter by 2.
This then generates an interrupt.
If the device does not receive any valid trigger signal during the "open window" cycle, then the window
watchdog recognizes invalid WWD triggering, increments the window watchdog error counter by 2 and starts
another "open window". This also generates an interrupt.
Configuration
The following parameters of the window watchdog can be configured via SPI in ACTIVE:
•
The trigger signal can be configured as either pin triggering (pin WDI) or triggering via SPI command
(register WWDSCMD). The default configuration is the triggering via SPI.
•
The duration of the "open window" and "closed window" cycles can be modified according to the
application needs (combination of cycle time WDCYC and number of cycles for open window OW and
closed window CW).
•
The threshold for the window watchdog error counter overflow can be configured.
Initialization
As soon as the device releases the microcontroller reset output (ROT) it enables the window watchdog in
ACTIVE state. After activation the watchdog opens a so-called "long open window" (LOW) cycle of duration of
tWD,LOW. During the "long open window" cycle the window watchdog expects a valid trigger signal (or a change
of configuration).
The default configuration expects watchdog triggering via SPI. Therefore, glitches at the microcontroller
output connected to the WDI have no effect during startup and initialization.
The microcontroller can change the configuration of the window watchdog during the "long open window"
cycle. After a reconfiguration the window watchdog restarts with the new configuration. The window
watchdog starts a regular "open window" cycle accordingly, expecting a valid trigger signal by the selected
triggering input.
Data Sheet
54
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Microcontroller interface and supervisory functions
Watchdog trigger signals
Two different trigger sources can be selected as watchdog trigger signal. This can be either an SPI write
operation to WWDSCMD or a valid trigger event on the watchdog input pin WDI.
The WDI pin has an integrated pull-down current source. A falling edge (transition from VWDI,high to VWDI,low) on
the pin is considered a trigger signal for the watchdog. The rising edge can occur at any time and is not
considered a trigger signal. For calculation of the external provided WDI the watchdog sampling time (tWDI_filter
)
has to be considered. For SPI watchdog trigger the positive edge of signal chip select (SCS) must be
considered.
Watchdog error counter and event generation
The window watchdog includes a watchdog error counter for invalid watchdog trigger events. The device
compares the watchdog error counter to the window watchdog error threshold continuously. If the counter
exceeds the threshold, it generates a window watchdog error event. The window watchdog error threshold is
configurable via SPI.
7.5.1
Electrical characteristics
Table 21
Electrical characteristics window watchdog function
Tj = -40°C to 150°C, VR1VSx = 3.7 V to 35 V, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
10
Unit Note or
Test Condition
Number
Min.
Max.
Watchdog cycle time,
configuration option 0
tWDCYC
tWDCYC
tLOW
9.5
10.5
µs
µs
ms
–
P_7.5.1.1
P_7.5.1.2
P_7.5.1.3
Watchdog cycle time,
configuration option 1
95
100
600
105
630
–
–
Long open window time
Watchdog input, pin WDI
Watchdog sampling time
Valid input level – "high"
Valid input level – "low"
Input hysteresis
570
tWDI_filter
VWDI, high
VWDI, low
VWDI, hyst
IWDI
380
0.7
–
400
–
420
–
µs
–
P_7.5.1.4
P_7.5.1.5
P_7.5.1.6
P_7.5.1.7
P_7.5.1.8
P_7.5.1.9
VIOVDD VWDI increasing
–
0.8
–
V
VWDI decreasing
–
0.06
135
4
VIOVDD
µA
–
Pull-down current
–
330
15
–
1)
Input capacitance
CWDI
–
pF
1) Not subject to production test, specified by design.
7.6
Microcontroller programming support
The device includes a feature to support programming of microcontroller’s firmware during production or in
the field by preventing periodic reset triggering during the initialization period.
Programming mode can be enabled by pulling the MPS pin "high". In programming mode the reset generation
to the microcontroller is modified, so that fault events of microcontroller monitoring features do not generate
a microcontroller reset. All other monitoring features that generate a microcontroller reset are still active (see
Table 25). The interrupt generation and the state transitions are still active. However, the initialization timer
is disabled, so that the device can remain in ACTIVE state.
Data Sheet
55
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Microcontroller interface and supervisory functions
Operation of the internal state machine and the programming mode are independent, which allows the
transition to any state while the microcontroller programming mode is active. However, the microcontroller
monitoring is still active and will move the device into ACTIVE state. Therefore, leave the device in ACTIVE state
during a programming operation.
Voltage monitoring is active and generates the respective fault events. This may generate interrupts or move
the device into FAULT state depending on the nature of the event.
Table 22
Electrical characteristics microcontroller programming mode
Tj = -40°C to 150°C, VR1VSx = 3.7 V to 35 V, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
MPS pin
Valid input level – "high"
Valid input level – "low"
Input hysteresis
VMPS, high
VMPS, low
VMPS, hys
IMPS
2.4
–
–
–
V
VMPS increasing
P_7.8.0.1
P_7.8.0.2
P_7.8.0.3
P_7.8.0.4
P_7.8.0.5
–
0.8
–
V
VMPS decreasing
1)
–
350
140
4
mV
µA
pF
Pull-down current
–
330
15
VMPS=5.0V
1)
Input capacitance
CMPS
–
1) Not subject to production test, specified by design.
Data Sheet
56
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
State machine
8
State machine
8.1
Introduction
The integrated state machine controls operation in different situations. Figure 11 shows the complete state-
diagram. Table 23 and Table 24 describe each state and the transitions.
LOCKED
VM1, VM2
Watchdog
OFF
Buck1
OFF
Boost1
Buck2
OFF
ROT
OFF
REGISTERS
OFF
LOW
EVENTS
Enable ev
o t
Fault has occured three times
and
DEVCFG0.ENA_CONFIG = 0
SPI: Got
en
DEV
CF
t
G0.ENA_C
o
and
L
OCKED
ONFIG = 0
FAULT
ACTIVE
DISABLED
SPI: Go to DISABLED
Enable event
VM1, VM2
Watchdog
VM1, VM2
Watchdog
VM1, VM2
Watchdog
Timer expired
OFF
Buck1
OFF
Boost1
ON*
Buck1
ON*
Boost1
OFF
Buck1
OFF
Boost1
Buck2
Buck2
Buck2
OFF
ROT
OFF
REGISTERS
OFF
ON
ROT
ON*
REGISTERS
ON*
OFF
ROT
OFF
REGISTERS
OFF
LOW
EVENTS
ACTIVE**
ALL
LOW
NONE
Generate interrupt
Move to FAULT State
POR event
Generate ROT
Boost1:
VM2:
UV
Buck1:
Buck2:
Boost1:
VM1:
IOVDD:
Monitoring:
Bandgap faults
OV, StG, TSD
Internal Supply
UV, OV
Buck1:
Buck2:
VM1:
UV
UV
UV
UV
OV, UV, StG
OV, StG, TSD
OV, StG
OV, StG
OV, StG
TSD
Watchdog error counter increased
Over-temperature warnings
Bandgap warnings
IOVDD:
Watchdog error counter overflow
INIT timer expired
R1VSx UV warning
REACTION ON DETECTED FAULTS
*: Switched ON by entering the ACTIVE then selectable via SPI
**: ROT will be ACTIVE (pulled high) after the reset delay time has expired
Figure 11 State machine
Data Sheet
57
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
State machine
8.2
Operation states
ACTIVE
The ACTIVE state is the first state that the device enters after power-on. The device powers up all voltage rails
and expects configuration from the microcontroller within the initialization time window according to the INIT
timer.
On deactivation of the microcontroller reset the INIT timer starts. If the following conditions are fulfilled, then
the INIT timer stops:
•
•
The device receives valid SPI communication from the microcontroller.
The window watchdog is serviced once according to its configuration.
If the INIT timer is not stopped and expires, then an initialization error is detected. The first initialization error
triggers a soft reset, which activates the reset signal ROT, but no state transition. The second initialization
error triggers a hard reset, which activates the reset signal ROT and shuts down the supply rails, thus the
device enters FAULT state and the system restarts.
The microcontroller can request a transition from ACTIVE state to either DISABLED or LOCKED state with an
SPI command. On an SPI request to change the state to DISABLED or LOCKED the TLF30682QVS01 enters the
FAULT state for 20 ms before it enters the requested state. This is done to ensure a proper discharge of the
output voltages of all switching regulators before the device can be re-enabled.
DISABLED
During DISABLED state the device is powered off and it only monitors the enable signal (ENA) for a valid enable
condition. Once a valid enable event is detected, the device enters ACTIVE state and expects configuration
from the microcontroller. In DISABLED state the register content of all registers is reset. The device needs to
be configured again during the ACTIVE state.
FAULT
On detection of a severe fault the device enters FAULT state. In FAULT state all regulators are switched off and
the microcontroller reset (ROT) is asserted. The device remains in FAULT state for the specified fault time prior
to a transition into ACTIVE state. In FAULT state the event registers are retained to store the reason for entering
the FAULT state. All other device registers are reset.
A soft reset condition on the first detection of a fault condition triggers the reset signal ROT, but no state
transition. If the device detects the same soft reset fault condition again, then it increases the severity of the
fault to a severe fault. In this case the device enters the FAULT state. This applies for all soft reset faults except
the Window Watchdog error counter overflow.
LOCKED
The device enters LOCKED state after three severe faults, brought on by expiration of the initialization counter
or by request of the microcontroller. The power consumption in LOCKED state is reduced. The device remains
in LOCKED state until it detects the next valid enable event. In LOCKED state only a limited set of the event
registers are retained to store the reason for entering the LOCKED state. All other device registers are reset.
Data Sheet
58
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OPTIREG™ PMIC TLF30682QVS01
Power Management IC
State machine
Table 23
Operational states functional overview.
ACTIVE
FAULT
LOCKED
DISABLED
Block or function
Buck1
ON
ON
ON
ON
ON
R
OFF
OFF
OFF
OFF
OFF
R
R
R
R
R
OFF
OFF
OFF
OFF
OFF
R
R
R
R
R
OFF
OFF
OFF
OFF
OFF
R
R
R
R
R
Buck2
RW
RW
RW
RW
Boost1
VM1
VM2
Window watchdog ON
RW
OFF
R
OFF
R
OFF
R
Microcontroller
reset – ROT
ACTIVE
R
-
"low"
R
-
"low"
R
-
"low"
-
R
-
Persistent registers All
Event
Event
registers
registers
registers
•
•
ON: Function is automatically activated when entering the state . Function may be configured via SPI
within the current state.
SEL: Function is operating as configured via SPI (during the mode transition or within the current operation
mode).
•
•
•
•
•
•
OFF: Function is automatically deactivated when entering the operation mode.
R: The state of the feature cannot be changed in the current operation mode.
RW: The state of the feature can be changed in the current operation mode.
"high": The signal is "high" in this operation mode.
"low": The signal is "low" in this operation mode.
ACTIVE: The reset signal may generate a reset event (edge) in this operation mode.
Data Sheet
59
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2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
State machine
8.3
State transitions and trigger signals
This section describes the state transitions of the integrated state machine.
Table 24 shows the static state transitions with the respective source and destination states, the condition
required to trigger the state transition and a transition specific action executed during the transition.
Each row refers to one state transition. With multiple conditions in the same row all of the conditions must be
met.
Table 24
Source
State Transitions
Destination
ACTIVE
Condition
Action
Unpowered
Device supplied
First POR event
ACTIVE
ACTIVE
ACTIVE
DISABLED
FAULT
DISABLED
LOCKED
FAULT
SPI command
SPI command
Hard reset fault detected
Enable event
ACTIVE
Generate MCU reset
Generate MCU reset
ACTIVE
FAULT timer expired
FAULT
LOCKED
Hard reset fault has
occurred three times.1)
LOCKED
ACTIVE
Enable event
Generate MCU reset
1) ENA pin must be configured as edge-triggered or the ENA pin must be low to trigger the transition from FAULT to
LOCKED state
Table 25 and Table 26 show the mapping between the fault events and the associated actions.
Data Sheet
60
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2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
State machine
Table 25
Event
Event response mapping – voltage rails
Move to
FAULT
Move to
ACTIVE
Generate
RESET
Move to
DISABLED
No transition
Generate interrupt
Buck1: OV
Buck1: UV
Buck1: StG
X
–
X
–
X
–
–
–
–
–
–
–
Buck2: OV
Buck2: UV
Buck2: StG
X
–
X
–
X
–
–
–
–
–
–
–
Boost1: OV
Boost1: UV
Boost1: StG
X
–
X
–
–
–
–
–
–
–
X
–
VM1: OV
VM1: UV
VM1: StG
X
–
X
–
X
–
–
–
–
–
–
–
VM2: OV
VM2: UV
VM2: StG
–
–
–
–
–
–
–
–
–
X
X
X
Data Sheet
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2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
State machine
Table 26
Event
Event response mapping – other events
Move to
FAULT
Move to
ACTIVE
Generate
RESET
Move to
DISABLED
No transition
Generate
interrupt
WWD: counter increase
–
–
–
X
–
X
X
–
–
–
–
–
X
–
–
–
WWD: counter overflow
INIT timer expired – first time
INIT timer expired – second time
Internal protection: band gap warning
Internal protection: band gap fault
IOVDD: OV
–
X
X
–
X
–
–
–
–
–
–
–
–
X
–
–
–
–
–
–
–
IOVDD: UV
X
IOVDD: StG
–
X1)
Internal protection: internal supplies
(UV,OV)
Buck1: OT warning
Buck1: OT fault
–
X
–
X
–
X
–
–
–
–
–
–
–
–
–
–
–
–
X
–
X
–
X
–
Buck2: OT warning
Buck2: OT fault
Monitoring: OT warning
Monitoring: OT fault
1) If the TLF30682QVS01an detects an UV or OV fault condition on the internal supplies, then it turns of completely. The
TLF30682QVS01 enters the ACTIVE state when the UV or OV condition is no longer present.
8.4
Electrical characteristics
Table 27
Electrical characteristics state machine
Tj = -40°C to 150°C; VR1VSx = 3.7 V to 35 V; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
600
Unit Note or
Test Condition
Number
Min.
Max.
Initialization time-out (INIT tINIT
550
650
ms
–
timer)
Fault time
tFault
–
–
–
20
–
ms
ms
µs
–
–
–
Fault time TSD
State transition time
tFault,TSD
ttrans
1000
–
–
100
Data Sheet
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OPTIREG™ PMIC TLF30682QVS01
Power Management IC
SPI registers
9
SPI registers
Table 28
Abbreviations
R0
R1
R2
Register is reset on a POR event and on a transition into DISABLE state.
Register is reset with reset class R0 and additionally on a transition into LOCKED state.
Register is reset with reset class R1 and additionally on a microcontroller reset.
r
Bit is readable (read-only).
rw
Bit is readable and writable (read-write).
rw1p
rw1c
Bit is protected. Read data is inverted. Write via LOCK/UNLOCK mechanism only.
Bit is readable and can be cleared by a write operation with 1.
Bit is updated based on hardware inputs (flags).
rwhc
rwhu
Bit is readable and writable. After a write operation with 1 an operation is triggered
which upon its completion sets the bit to 0.
Bit is readable and writable.
Bit is updated based on hardware inputs (flags).
Table 29
Register overview
Register ID
Description
Address Reset Reset Page
Value Class
DEVCFG0
CLKCFG0
CLKCFG1
PROTCFG
PWDCFG0
RWDCFG0
PWDCFG1
RWDCFG1
PWDCFG2
RWDCFG2
B2VCTRL
B2VCTRLN
GSF
Device configuration 0
00H
01H
02H
03H
06H
07H
08H
09H
0AH
0BH
10H
11H
1AH
1BH
1CH
1DH
1EH
1FH
F3H
00H
04H
00H
9BH
9BH
46H
46H
78H
78H
02H
0DH
00H
00H
00H
00H
00H
00H
00H
00H
R0
R2
R2
R2
R2
R2
R2
R2
R2
R2
R1
R1
R0
R0
R1
R0
R1
R1
R0
R0
Page 65
Page 66
Page 67
Page 74
Page 67
Page 69
Page 68
Page 69
Page 68
Page 70
Page 73
Page 73
Page 76
Page 77
Page 78
Page 79
Page 79
Page 80
Page 81
Page 82
Clock configuration 0
Clock configuration 1
Configuration protection
Protected watchdog configuration 0
Read-only watchdog configuration 0
Protected watchdog configuration 1
Read-only watchdog configuration 1
Protected Watchdog Configuration 2
Read-only watchdog configuration 2
Buck2 output voltage control
Buck2 output voltage control inverted
Global status flags
SYSSF0
System status flags – faults
SYSSF1
System status flags – interrupts
Microcontroller status flags 0 – faults
Microcontroller status flags 1 – warnings
SPI status flags
MCUSF0
MCUSF1
SPISF
MONSF0
MONSF1
Voltage monitoring status flags 0 – short to ground 20H
Voltage monitoring status flags 1 – overvoltage
21H
Data Sheet
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OPTIREG™ PMIC TLF30682QVS01
Power Management IC
SPI registers
Table 29
Register overview (cont’d)
Register ID
Description
Address Reset Reset Page
Value Class
MONSF2
OTSF0
Voltage monitoring status flags 2 – undervoltage
Overtemperature events 0 – faults
Overtemperature flags 1 – warnings
Overcurrent flags – warnings
22H
23H
24H
25H
26H
27H
28H
29H
2AH
33H
34H
35H
37H
00H
00H
00H
00H
00H
00H
00H
01H
00H
00H
00H
00H
03H
R0
R0
R1
R1
R1
R1
R1
R2
R2
R2
R1
R1
R1
Page 83
Page 84
Page 84
Page 85
Page 86
Page 86
Page 87
Page 88
Page 89
Page 74
Page 71
Page 72
Page 89
OTSF1
OCSF1
OTSTAT0
Overtemperature status 0 – warnings
VMONSTAT0 Voltage monitoring
DEVSTAT
Device state information
PROTSTAT
WWDSTAT
WWDSCMD
DEVCTRL
Protection status information
Window watchdog status information
Window watchdog service command
Device state control
DEVCTRLN
MPSSTAT0
Device state control inverted
Microcontroller programming support status
information
B2VSTAT
HWDECT0
DEVID
Buck2 output voltage status
Hardware option information
Device identification
39H
3BH
3CH
02H
D3H
10H
R1
R1
R1
Page 90
Page 91
Page 92
Data Sheet
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OPTIREG™ PMIC TLF30682QVS01
Power Management IC
SPI registers
9.1
SPI register definition
9.1.1
Device configuration registers (device start-up default configuration)
DEVCFG0
Device configuration 0
(00H)
ResetValue:F3H
7
6
5
4
3
2
1
0
VM2ENAS
VM1ENAS BOOST1ENAS BUCK2ENAS ENA_CONFIG
RESDEL
r
r
r
r
rw
rw
Field
Bits
Type Description
VM2ENAS
7
r
External voltage monitoring 2 enable at start up
0H disabled
1H enabled
Reset: 1H
VM1ENAS
6
r
External voltage monitoring 1 enable at start up
0H disabled
1H enabled
Reset: 1H
BOOST1ENAS
BUCK2ENAS
ENA_CONFIG
RESDEL
5
r
Boost1 enable at start up
0H disabled
1H enabled
Reset: 1H
4
r
Buck2 enable at start up
0H disabled
1H enabled
Reset: 1H
3
rw
rw
ENA pin configuration
0H edge triggered
1H level sensitive
Reset: 0H
2:0
Reset release delay time
00H 200 µs
01H 400 µs
02H 800 µs
03H 1 ms
04H 2 ms
05H 4 ms
06H 10 ms
07H 20 ms
Reset: 3H
Data Sheet
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2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
SPI registers
CLKCFG0
Clock configuration 0
(01H)
ResetValue:00H
7
6
5
4
3
2
1
0
nu
PHBUCK2
PHBUCK1
PHSO
nu
SSEN
SIEN
SOEN
r
rw
rw
rw
r
rw
rwhc
rw
Field
nu
Bits
7
Type Description
r
Not used
PHBUCK2
PHBUCK1
PHSO
6
rw
Buck2 phase alignment
0H 0° phase shift
1H 180° phase shift
Reset: 0H
5
4
rw
rw
Buck1 phase alignment
0H 0° phase shift
1H 180° phase shift
Reset: 0H
External clock synchronization phase alignment
0H 0° phase shift
1H 180° phase shift
Reset: 0H
nu
3
2
r
Not used
SSEN
rw
Spread spectrum modulation enable
0H disabled
1H enabled
Reset: 0H
SIEN
1
0
rwhc
rw
External clock synchronization input enable
0H disabled
1H enabled
Reset: 0H
SOEN
External clock synchronization output enable
0H disabled
1H enabled
Reset: 0H
Data Sheet
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OPTIREG™ PMIC TLF30682QVS01
Power Management IC
SPI registers
CLKCFG1
Clock configuration 1
(02H)
ResetValue:04H
7
6
5
4
3
2
1
0
nu
FREQSEL
r
rw
Field
nu
Bits
7:3
Type Description
r
Not used
FREQSEL
2:0
rw
Main switching frequency
0H 1.8 MHz
1H 1.9 MHz
2H 2.0 MHz
3H 2.1 MHz
4H 2.2 MHz
5H 2.3 MHz
6H 2.4 MHz
7H 2.5 MHz
Reset: 4H
PWDCFG0
Protected watchdog configuration 0
(06H)
ResetValue:9BH
7
6
5
4
3
2
1
0
WWDETHR
WWDEN
nu
WWDTSEL
WDCYC
rwp
rwp
r
rwp
rwp
Field
Bits
Type Description
WWDETHR
7:4
rwp
Window watchdog error threshold
0H
1H
...
0
1
FH 15
Reset: 9H
WWDEN
3
rwp
Window watchdog enable
0B disabled
1B enabled
Reset: 1H
nu
2
1
r
Not used
WWDTSEL
rwp
Window watchdog trigger selection
0B external WDI input used as WWD trigger
1B WWD is triggered by SPI write to WWDSCMD register
Reset: 1H
Data Sheet
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OPTIREG™ PMIC TLF30682QVS01
Power Management IC
SPI registers
Field
Bits
Type Description
rwp Watchdog cycle time
WDCYC
0
0B 10 µs tick period
1B 100 µs tick period
Reset: 1H
PWDCFG1
Protected watchdog configuration 1
(08H)
ResetValue:46H
7
6
5
4
3
2
1
0
nu
CW
r
rwp
Field
nu
Bits
7
Type Description
r
Not used
CW
6:0
rwp
Window watchdog closed window size
00H 0 watchdog cycles
01H 50 watchdog cycles
02H 100 watchdog cycles
...
7FH 6350 watchdog cycles
Reset: 46H
PWDCFG2
Protected Watchdog Configuration 2
(0AH)
ResetValue:78H
7
6
5
4
3
2
1
0
nu
OW
r
rwp
Field
nu
Bits
7
Type Description
r
Not used
OW
6:0
rwp
Window watchdog open window size
00H 50 watchdog cycles
01H 50 watchdog cycles
02H 100 watchdog cycles
...
7FH 6350 watchdog cycles
Reset: 78H
Data Sheet
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OPTIREG™ PMIC TLF30682QVS01
Power Management IC
SPI registers
9.1.2
Read-only registers for protected configuration registers
RWDCFG0
Read-only watchdog configuration 0
(07H)
ResetValue:9BH
7
6
5
4
3
2
1
0
WWDETHR
WWDEN
nu
WWDTSEL
WDCYC
r
r
r
r
r
Field
Bits
Type Description
WWDETHR
7:4
r
Window watchdog error threshold ACTIVE
0H
1H
...
0
1
FH 15
Reset: 9H
WWDEN
3
r
Window watchdog enable STATUS
0B disabled
1B enabled
Reset: 1H
nu
2
1
r
r
Not used
WWDTSEL
Window watchdog trigger selection ACTIVE
0B external WDI input used as WWD trigger
1B WWD is triggered by SPI write to WWDSCMD register
Reset: 1H
WDCYC
0
r
Watchdog cycle time ACTIVE
0B 10 µs tick period
1B 100 µs tick period
Reset: 1H
RWDCFG1
Read-only watchdog configuration 1
(09H)
ResetValue:46H
7
6
5
4
3
2
1
0
nu
CW
r
r
Field
nu
Bits
Type Description
Not used
7
r
Data Sheet
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2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
SPI registers
Field
CW
Bits
Type Description
Window watchdog closed window size ACTIVE
6:0
r
00H 0 watchdog cycles
01H 50 watchdog cycles
02H 100 watchdog cycles
...
7FH 6350 watchdog cycles
Reset: 46H
RWDCFG2
Read-only watchdog configuration 2
(0BH)
ResetValue:78H
7
6
5
4
3
2
1
0
nu
OW
r
r
Field
nu
Bits
7
Type Description
r
r
Not used
OW
6:0
Window watchdog open window size ACTIVE
00H 50 watchdog cycles
01H 50 watchdog cycles
02H 100 watchdog cycles
...
7FH 6350 watchdog cycles
Reset: 78H
Data Sheet
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OPTIREG™ PMIC TLF30682QVS01
Power Management IC
SPI registers
9.1.3
Special device configuration registers
The registers in this section are specially protected by a defined access procedure. This procedure is based on
the access to two individual registers writing inverted information. For detailed information please refer to
Chapter 7.2.3.
DEVCTRL
Device state control
(34H)
ResetValue:00H
7
6
5
4
3
2
1
0
VM2EN
VM1EN
BOOST1EN
BUCK2EN
nu
STATEREQ
rw
rw
rw
rw
r
rw
Field
Bits
Type Description
VM2EN
7
rw
rw
rw
rw
External voltage monitoring 2 enable request
0H disable
1H enable
Reset: 0H
VM1EN
6
5
4
External voltage monitoring 1 enable request
0H disable
1H enable
Reset: 0H
BOOST1EN
BUCK2EN
Boost1 enable request
0H disable
1H enable
Reset: 0H
Buck2 enable request
0H disable
1H enable
Reset: 0H
nu
3
r
Not used
STATEREQ
2:0
rw
Device state request
00H Reserved
01H ACTIVE state
02H Reserved
03H DISABLED state
04H Reserved
05H Reserved
06H Reserved
07H LOCKED state
Reset: 0H
Data Sheet
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OPTIREG™ PMIC TLF30682QVS01
Power Management IC
SPI registers
DEVCTRLN
Device state control inverted
(35H)
ResetValue:00H
7
6
5
4
3
2
1
0
VM2EN
VM1EN
BOOST1EN
BUCK2EN
nu
STATEREQ
rw
rw
rw
rw
r
rw
Field
Bits
Type Description
VM2EN
7
rw
rw
rw
rw
External voltage monitoring 2 enable request
0H enable
1H disable
Reset: 0H
VM1EN
6
5
4
External voltage monitoring 1 enable request
0H enable
1H disable
Reset: 0H
BOOST1EN
BUCK2EN
Boost1 enable request
0H enable
1H disable
Reset: 0H
Buck2 enable request
0H enable
1H disable
Reset: 0H
nu
3
r
Not used
STATEREQ
2:0
rw
Device state request
07H Reserved
06H ACTIVE state
05H Reserved
04H DISABLED state
03H Reserved
02H Reserved
01H Reserved
00H LOCKED state
Reset: 0H
Data Sheet
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OPTIREG™ PMIC TLF30682QVS01
Power Management IC
SPI registers
B2VCTRL
Buck2 output voltage control
(10H)
ResetValue:02H
7
6
5
4
3
2
1
0
nu
B2VOUTF
r
rwhu
Field
nu
Bits
7:4
Type Description
Not used
r
B2VOUTF
3:0
rwhu Buck2 output voltage setting fine resolution
0H 1.30 V
1H 1.20 V
2H 1.25 V
3H 1.15 V
4H 1.10 V
5H 1.00 V
6H 1.05 V
7H 0.95 V
8H 0.90 V
Reset: 02H
B2VCTRLN
Buck2 output voltage control inverted
(11H)
ResetValue:0DH
7
6
5
4
3
2
1
0
nu
B2VOUTF
r
rwhu
Field
nu
Bits
7:4
Type Description
Not used
r
B2VOUTF
3:0
rwhu Buck2 output voltage setting fine resolution
FH 1.30 V
EH 1.20 V
DH 1.25 V
CH 1.15 V
BH 1.10 V
AH 1.00 V
9H 1.05 V
8H 0.95 V
7H 0.90 V
Reset: 0DH
Data Sheet
73
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OPTIREG™ PMIC TLF30682QVS01
Power Management IC
SPI registers
9.1.4
General registers
PROTCFG
Configuration protection
(03H)
ResetValue:00H
7
6
5
4
3
2
1
0
KEY
rw
Field
KEY
Bits
Type Description
rw Protection key
Reset: 00H
7:0
WWDSCMD
Window watchdog service command
(33H)
ResetValue:00H
7
6
5
4
3
2
1
0
TRIG_STATU
S
nu
TRIG
r
r
rw
Field
Bits
Type Description
TRIG_STATUS
7
r
Window watchdog last trigger received via SPI
Reset: 00H
nu
6:1
0
r
Not used
TRIG
rw
Window watchdog trigger command
Reset: 00H
Data Sheet
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2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
SPI registers
9.1.5
Event status registers
The event status registers of the device are organized hierarchically. The global status register is used to
collect information of the status flags set in other registers to enable the user to speed up the event source
determination.
A bit in the global status register is automatically set, when a bit in the respective status register is set (event
based, not level based).
If a bit in the global status register is set, the user should read out the corresponding status register for the
detailed information on the event source.
The bits in the global status flag register can be cleared without effect on the other status registers. Clearing a
bit in any of the other status registers does not reset the corresponding bit in the global status register.
Data Sheet
75
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2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
SPI registers
GSF
Global status flags
(1AH)
ResetValue:00H
7
6
5
4
3
2
1
0
INTMISS
nu
R1VSxUV
OT
MON
SPI
MCU
SYS
r
r
rw1c
rw1c
rw1c
rw1c
rw1c
rw1c
Field
Bits
Type Description
INTMISS
7
r
Interrupt time out event
0H no event
1H event occurred, cleared by hardware when all other flags in IF are
cleared.
Reset: 0H
nu
6
5
r
Not used
R1VSxUV
rw1c
Battery voltage undervoltage event
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
OT
4
rw1c
Overtemperature or overcurrent monitoring event flag:
OTSF0,OTSF1, OCSF1
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
MON
SPI
3
2
1
0
rw1c
rw1c
rw1c
rw1c
Voltage monitoring event flag: MONSF0, MONSF1, MONSF2
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
SPI event flag: SPISF
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
MCU
SYS
MCU event flag: MCUSF0,MCUSF1
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
System event flag: SYSSF0,SYSSF1
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
Data Sheet
76
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
SPI registers
SYSSF0
System status flags – faults
(1BH)
ResetValue:00H
7
6
5
4
3
2
1
0
BGFLT2
BGFLT1
IOVDDOV
IOVDDUV
nu
FUSEERR
rw1c
rw1c
rw1c
rw1c
r
rw1c
Field
Bits
Type Description
BGFLT2
7
rw1c
rw1c
rw1c
rw1c
Bandgap fault event 2
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
BGFLT1
6
5
4
Bandgap fault event 1
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
IOVDDOV
IOVDDUV
IOVDD overvoltage event
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
IOVDD undervoltage event
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
nu
3:1
0
r
Not used
FUSEERR
rw1c
Double bit error in fuse memory
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
Data Sheet
77
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
SPI registers
SYSSF1
System status flags – interrupts
(1CH)
ResetValue:00H
7
6
5
4
3
2
1
0
BGWARN2
BGWARN1 ENA_PWRUP
nu
SYNC
ENA
CFG2
CFG
rw1c
rw1c
rw1c
r
rw1c
rw1c
rw1c
rw1c
Field
Bits
Type Description
BGWARN2
BGWARN1
ENA_PWRUP
7
rw1c
rw1c
rw1c
Bandgap warning event 2
(VBG1+4%>VBG2)
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
6
5
Bandgap warning event 1
(VBG1-4%<VBG2)
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
Device wake-up condition
0H device wake-up on a power-on-reset event, write 0 – no action
1H device wake-up on ENA event, write 1 to clear the flag
Reset: 0H
nu
4
3
r
Not used
SYNC
rw1c
External clock synchronization fault event
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
ENA
CFG2
CFG
2
1
0
rw1c
rw1c
rw1c
Enable interrupt event
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
Output voltage configuration change fault event
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
Supervision functions configuration change fault event
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
Data Sheet
78
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
SPI registers
MCUSF0
Microcontroller status flags 0 – faults
(1DH)
ResetValue:00H
7
6
5
4
3
2
1
0
HARDRES
SOFTRES
nu
WWDF
nu
INITF
rw1c
rw1c
rw1c
rw1c
r
rw1c
Field
Bits
Type Description
HARDRES
SOFTRES
7
rw1c
Hard reset event
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
6
rw1c
Soft reset event
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
nu
5:4
3
rw1c
rw1c
Not used
WWDF
Window watchdog fault event
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
nu
2:1
0
r
Not used
INITF
rw1c
INIT timer error event
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
MCUSF1
Microcontroller status flags 1 – warnings
(1EH)
ResetValue:00H
7
6
5
4
3
2
1
0
nu
WWDMISS
nu
r
rw1c
r
Field
nu
Bits
7:4
3
Type Description
r
Not used
WWDMISS
rw1c
Window watchdog missed trigger event
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
nu
2:0
r
Not used
Data Sheet
79
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2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
SPI registers
SPISF
SPI status flags
(1FH)
Reset Value:00H
7
6
5
4
3
2
1
0
nu
B2VCTRL
DEVCTRL
LOCK
DUR
ADDR
LEN
PAR
r
rw1c
rw1c
rw1c
rw1c
rw1c
rw1c
rw1c
Field
nu
Bits
7
Type Description
r
Not used
B2VCTRL
DEVCTRL
LOCK
6
rw1c
SPI protocol B2VCTRL access error event
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
5
4
3
rw1c
rw1c
rw1c
SPI protocol DEVCTRL access error event
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
SPI protocol LOCK or UNLOCK access error event
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
DUR
SPI duration error event
Chip select signal CS "low" for more than 2 ms
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
ADDR
LEN
2
1
rw1c
rw1c
SPI invalid address error event
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
SPI frame length error event
Number of detected SPI clock cycles different than 16
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
PAR
0
rw1c
SPI parity error event
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
Data Sheet
80
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
SPI registers
MONSF0
Voltage monitoring status flags 0 – short to ground(20H)
Reset Value:00H
7
6
5
4
3
2
1
0
VM2STG
VM1STG
nu
BOOST1STG
nu
BUCK2STG BUCK1STG
rw1c rw1c
rw1c
rw1c
r
rw1c
r
Field
Bits
Type Description
VM2STG
VM1STG
7
rw1c
rw1c
External voltage monitoring 2 short to ground event
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
6
External voltage monitoring 1 short to ground event
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
nu
5
4
r
Not used
BOOST1STG
rw1c
Boost1 short to ground event
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
nu
3:2
1
r
Not used
BUCK2STG
rw1c
Buck2 short to ground event
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
BUCK1STG
0
rw1c
Buck1 short to ground event
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
Data Sheet
81
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2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
SPI registers
MONSF1
Voltage monitoring status flags 1 – overvoltage (21H)
ResetValue:00H
7
6
5
4
3
2
1
0
VM2OV
VM1OV
nu
BOOST1OV
nu
BUCK2OV
BUCK1OV
rw1c
rw1c
r
rw1c
r
rw1c
rw1c
Field
Bits
Type Description
VM2OV
VM1OV
7
rw1c
rw1c
External voltage monitoring 2 overvoltage event
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
6
External voltage monitoring 1 overvoltage event
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
nu
5
4
r
Not used
BOOST1OV
rw1c
Boost1 overvoltage event
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
nu
3:2
1
r
Not used
BUCK2OV
rw1c
Buck2 overvoltage event
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
BUCK1OV
0
rw1c
Buck1 overvoltage event
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
Data Sheet
82
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
SPI registers
MONSF2
Voltage monitoring status flags 2 – undervoltage(22H)
ResetValue:00H
7
6
5
4
3
2
1
0
VM2UV
VM1UV
nu
BOOST1UV
nu
BUCK2UV
BUCK1UV
rw1c
rw1c
r
rw1c
r
rw1c
rw1c
Field
Bits
Type Description
VM2UV
VM1UV
7
rw1c
rw1c
External voltage monitoring 2 undervoltage event
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
6
External voltage monitoring 1 undervoltage event
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
nu
5
4
r
Not used
BOOST1UV
rw1c
Boost1 undervoltage event
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
nu
3:2
1
r
Not used
BUCK2UV
rw1c
Buck2 undervoltage event
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
BUCK1UV
0
rw1c
Buck1 undervoltage event
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
Data Sheet
83
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
SPI registers
OTSF0
Overtemperature events 0 – faults
(23H)
ResetValue:00H
7
6
5
4
3
2
1
0
MONOT
nu
BUCK2OT
BUCK1OT
rw1c
r
rw1c
rw1c
Field
Bits
Type Description
MONOT
7
rw1c
Monitoring overtemperature fault event
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
nu
6:2
1
r
Not used
BUCK2OT
rw1c
Buck2 overtemperature fault event
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
BUCK1OT
OTSF1
0
rw1c
Buck1 overtemperature fault event
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
Overtemperature flags 1 – warnings
(24H)
ResetValue:00H
7
6
5
4
3
2
1
0
MONOTW
nu
BUCK2OTW BUCK1OTW
rw1c rw1c
rw1c
r
Field
Bits
Type Description
MONOTW
7
rw1c
Monitoring overtemperature warning event
0H no event, write 0 – no action
1B event detected – write 1 to clear flag
Reset: 0H
nu
6:2
1
r
Not used
BUCK2OTW
rw1c
Buck2 overtemperature warning event
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
BUCK1OTW
0
rw1c
Buck1 overtemperature warning event
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
Data Sheet
84
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
SPI registers
OCSF1
Overcurrent flags – warnings
(25H)
ResetValue:00H
7
6
5
4
3
2
1
0
nu
BOOST1OCW
nu
BUCK2OCW BUCK1OCW
rw1c rw1c
r
rw1c
r
Field
nu
Bits
7:5
4
Type Description
r
Not used
BOOST1OCW
rw1c
Boost1 overcurrent warning event
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
nu
3:2
1
r
Not used
BUCK2OCW
rw1c
Buck2 overcurrent warning event
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
BUCK1OCW
0
rw1c
Buck1 overcurrent warning event
0H no event, write 0 – no action
1H event occurred, write 1 to clear the flag
Reset: 0H
Data Sheet
85
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
SPI registers
9.1.6
Device status information registers
The device status information registers reflect the current status of the device irrespective of the latched
status information in the interrupt flag registers. Therefore, reading these registers reflects the current status
of the device, for example the currently active power rails or the temperature warnings.
OTSTAT0
Overtemperature status 0 – warnings
(26H)
ResetValue:00H
7
6
5
4
3
2
1
0
MONOTW
nu
BUCK2OTW BUCK1OTW
r
r
r
r
Field
Bits
Type Description
MONOTW
7
r
Monitoring overtemperature warning STATUS
0H no overtemperature warning
1B overtemperature warning present
Reset: 0H
nu
6:2
1
r
r
Not used
BUCK2OTW
Buck2 overtemperature warning STATUS
0H no overtemperature warning
1B overtemperature warning present
Reset: 0H
BUCK1OTW
VMONSTAT0
0
r
Buck1 overtemperature warning STATUS
0H no overtemperature warning
1B overtemperature warning present
Reset: 0H
Voltage monitoring
(27H)
Reset Value:00H
7
6
5
4
3
2
1
0
VM2OK
VM1OK
R1VSxUV
BOOST1OK
SYNCOK
ENA
BUCK2OK
BUCK1OK
r
r
r
r
r
r
r
r
Field
Bits
Type Description
VM2OK
VM1OK
7
r
External voltage monitoring 2 STATUS
0H output rail disabled or not in total operation band
1H output rail enabled and in total operation band
Reset: 0H
6
r
External voltage monitoring 1 STATUS
0H output rail disabled or not in total operation band
1H output rail enabled and in total operation band
Reset: 0H
Data Sheet
86
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
SPI registers
Field
Bits
Type Description
Battery undervoltage STATUS
R1VSxUV
5
r
r
r
r
r
r
0H battery voltage undervoltage not present.
1H battery voltage undervoltage present.
Reset: 0H
BOOST1OK
SYNCOK
ENA
4
3
2
1
0
Boost1 STATUS
0H output rail disabled or not in total operation band
1H output rail enabled and in total operation band
Reset: 0H
External clock synchronization STATUS
0H clock synchronization is not operating
1H clock synchronization is operating.
Reset: 0H
Enable signal level
0H enable signal is "low"
1H enable signal is "high"
Reset: 0H
BUCK2OK
BUCK1OK
Buck2 STATUS
0H output rail disabled or not in total operation band
1H output rail enabled and in total operation band
Reset: 0H
Buck1 STATUS
0H output rail disabled or not in total operation band
1H output rail enabled and in total operation band
Reset: 0H
DEVSTAT
Device state information
(28H)
ResetValue:00H
7
6
5
4
3
2
1
0
VM2EN
VM1EN
BOOST1EN
BUCK2EN
nu
STATE
r
r
r
r
r
r
Field
Bits
Type Description
VM2EN
7
r
r
r
External voltage monitoring 2 enable STATUS
0H voltage is disabled
1H voltage is enabled
Reset: 0H
VM1EN
6
5
External voltage monitoring 1 enable STATUS
0H voltage is disabled
1H voltage is enabled
Reset: 0H
BOOST1EN
Boost 1 enable STATUS
0H voltage is disabled
1H voltage is enabled
Reset: 0H
Data Sheet
87
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
SPI registers
Field
Bits
Type Description
BUCK2EN
4
r
Buck 2 enable STATUS
0H voltage is disabled
1H voltage is enabled
Reset: 0H
nu
3
r
r
Not used
STATE
2:0
Device state
0H reserved
1H ACTIVE state
2H reserved
3H reserved
4H reserved
5H reserved
6H reserved
7H reserved
Reset: 0H
PROTSTAT
Protection status information
(29H)
ResetValue:01H
7
6
5
4
3
2
1
0
KEY4OK
KEY3OK
KEY2OK
KEY1OK
nu
LOCK
r
r
r
r
r
r
Field
Bits
Type Description
KEY4OK
KEY3OK
KEY2OK
KEY1OK
7
r
r
r
r
Fourth protection key valid STATUS
0H key not valid
1H key valid
Reset: 0H
6
5
4
Third protection key valid STATUS
0H key not valid
1H key valid
Reset: 0H
Second protection key valid STATUS
0H key not valid
1H key valid
Reset: 0H
First protection key valid STATUS
0H key not valid
1H key valid
Reset: 0H
nu
3:1
0
r
r
Not used
LOCK
Lock STATUS
0H access to protected registers is unlocked.
1H access to protected registers is locked.
Reset: 0H
Data Sheet
88
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
SPI registers
WWDSTAT
Window watchdog status information
(2AH)
ResetValue:00H
7
6
5
4
3
2
1
0
nu
WWDECNT
r
r
Field
nu
Bits
7:4
Type Description
r
r
Not used
Window watchdog error counter level
WWDECNT
3:0
0H
1H
...
0
1
FH 15
Reset: 0H
MPSSTAT0
Microcontroller programming support status information(37H)
ResetValue:03H
7
6
5
4
3
2
1
0
nu
MPSSTAT
r
r
Field
nu
Bits
7:4
Type Description
r
r
Not used
MPSSTAT
3:0
MPS STATUS
3H device in operating mode
6H device in programming mode
9H device in test mode (production test mode, read-back only)
Reset: 3H
Data Sheet
89
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
SPI registers
B2VSTAT
Buck2 output voltage status
(39H)
ResetValue:02H
7
6
5
4
3
2
1
0
BUCK2VOUTC
BUCK2VOUTF
r
r
Field
Bits
Type Description
BUCK2VOUTC 7:4
r
Buck2 output voltage setting coarse resolution STATUS
0H Range 0.9 – 1.3 V. Fine resolution is evaluated.
1H 1.5 V
2H 1.8 V
3H 2.45 V
4H 3.3 V
Reset: 00H
BUCK2VOUTF
3:0
r
Buck2 output voltage setting fine resolution STATUS
0H 1.30 V
1H 1.20 V
2H 1.25 V
3H 1.15 V
4H 1.10 V
5H 1.00 V
6H 1.05 V
7H 0.95 V
8H 0.90 V
Reset: 02H
Data Sheet
90
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
SPI registers
9.1.7
Device information registers
HWDECT0
Hardware option information
(3BH)
ResetValue:D3H
7
6
5
4
3
2
1
0
VM2AVA
VM1AVA
nu
BOOST1AVA
nu
BUCK2AVA
FRE
r
r
r
r
r
r
r
Field
Bits
Type Description
VM2AVA
VM1AVA
7
r
External voltage monitoring 2 automatic use detection
0H VM2 is not used in this application.
1H VM2 is used in this application.
Reset: 1H
6
r
External voltage monitoring 1 automatic use detection
0H VM1 is not used in this application.
1H VM1 is used in this application.
Reset: 1H
nu
5
4
r
r
Not used
BOOST1AVA
Boost1 automatic use detection
0H Boost1 is not used in this application.
1H Boost1 is used in this application.
Reset: 1H
nu
3:2
1
r
r
Not used
BUCK2AVA
Buck2 automatic use detection
0H Buck2 is not used in this application.
1H Buck2 is used in this application.
Reset: 1H
FRE
0
r
Frequency selection information
0H LF frequency setting
1H HF frequency setting
Reset: 1H
Data Sheet
91
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2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
SPI registers
DEVID
Device identification
(3CH)
ResetValue:10H
7
6
5
4
3
2
1
0
DEVTYPE
r
Field
Bits
Type Description
Device family
DEVTYPE
7:0
r
10H TLF30682 device
Reset: 10H
Data Sheet
92
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Application information
10
Application information
The component values recommended in this section are typical values. The component names in Table 30
refer to the application diagram in Figure 12.
Note:
The following information is given as a hint for the implementation of the device only and shall not
be regarded as a description or warranty of a certain functionality, condition or quality of the device.
•
•
Please contact us for additional supportive documentation.
For further information you may contact http://www.infineon.com/
Table 30
Recommended values for the passive components in the application diagram (see
Figure 12)
Name
Value
Comments
LBuck1
3.3 µH
Buck1 inductor
It is recommended to chose an inductor with a saturation current which is
greater than the Buck1 over-current protection threshold IR1,OCP
.
CBuck1_1
10 µF
Buck1 output capacitor #1
This capacitor should be placed close to the R2VSx input of Buck2 and
connected between the R2VSx and R2PGx pins directly.
It is recommended to use a ceramic capacitor in X7R material with a voltage
rating of 6.3 V or higher.
CBuck1_2
CBuck1_3
47 µF
Buck1 output capacitors #2 and #3
It is recommended to use a ceramic capacitor in X7R material with a voltage
rating of 6.3 V or higher.
CBuck1_BST
100 nF
2.2 µH
22 µF
Buck1 bootstrap capacitor
It is recommended to use a ceramic capacitor in X7R material with a voltage
rating of 16 V or higher.
LBuck2
Buck2 inductor
It is recommended to choose an inductor with a saturation current which is
greater than the Buck2 over-current protection threshold IR2,OCP
.
CBuck2_1
CBuck2_2
CBuck2_3
Buck2 output capacitors #1 to #3
It is recommended to use a ceramic capacitor in X7R material with a voltage
rating of 6.3 V or higher.
LBoost1
6.8 µH
100nF
10 µF
Boost1 inductor
It is recommended to chose an inductor with a saturation current which is
greater than the Boost1 over-current protection threshold IR3,OCP
.
CBoost1_1
Boost1 output capacitor #1
It is recommended to use a ceramic capacitor in X7R material with a voltage
rating of 10 V or higher.
CBoost1_2
Boost1 output capacitor #2
It is recommended to use a ceramic capacitor in X7R material with a voltage
rating of 10 V or higher.
Note:
This following figure is a very simplified example of an application circuit. The function must be
verified in the real application.
Data Sheet
93
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Application information
R1VSx
V_S (T30)
SYNCI
SYNC_In
SYNC_Out
Clock
Generation
Buck1
Driver
Supply
Internal
Supply
SYNCO
NC
Logic
R1BTSV
R1BTS
CBuck1_BST
LBuck1
ENABLE
R1SWx
R1PGx
SMPR
Buck1
VBuck1
ENA
ENABLE
Feedback
MPS
IOVDD
R1FB
Interface_supply
LBoost1
INT
R3SW
INTERRUPT
Generator
Interrupt
SMPR
Boost
CBoost1_2
VBoost1
SCS
SCL
SDI
R3PG
R3FB
CBoost1_1
SPI_ChipSelect
SPI_Clock
Feedback
SPI
SPI_DataIn
R2VS1x
R2SWx
SDO
SPI_DataOut
LBuck2
SMPR
Buck2
WDI
Window
Watchdog
VBuck2
Watchdog_TriggerIn
R2PGx
R2FB
Feedback
Bandgap 1
NC
Fault
VM1EN
VM1FB
Manager
ExtRail1_Enable
TM1
ExtRail1_Feedback
TM2
ROT
UV/OV-Monitoring/
Enable Handling
VM2EN
VM2FB
ExtRail2_Enable
μC_Reset
Bandgap 2
for V- Mon.
Reset Generator
ExtRail2_Feedback
AG1 AG2
AG3 AG4 AG5
AG6
Figure 12 Application diagram
Data Sheet
94
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Package information
11
Package information
Figure 13 PG-VQFN-481)
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant
with government regulations the device is available as a green product. Green products are RoHS-Compliant
(i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
Further information on packages
https://www.infineon.com/packages
1) Dimensions in mm
Data Sheet
95
1.01
2019-07-03
OPTIREG™ PMIC TLF30682QVS01
Power Management IC
Revision History
12
Revision History
Revision Date
Changes
1.01
1.0
2019-07-03 Updated meta data.
2019-04-05 Initial release of data sheet.
Data Sheet
96
1.01
2019-07-03
Trademarks
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IMPORTANT NOTICE
The information given in this document shall in no For further information on technology, delivery terms
Edition 2019-07-03
Published by
Infineon Technologies AG
81726 Munich, Germany
event be regarded as a guarantee of conditions or and conditions and prices, please contact the nearest
characteristics ("Beschaffenheitsgarantie").
Infineon Technologies Office (www.infineon.com).
With respect to any examples, hints or any typical
values stated herein and/or any information regarding
the application of the product, Infineon Technologies
hereby disclaims any and all warranties and liabilities
of any kind, including without limitation warranties of
non-infringement of intellectual property rights of any
third party.
In addition, any information given in this document is
subject to customer's compliance with its obligations
stated in this document and any applicable legal
requirements, norms and standards concerning
customer's products and any use of the product of
Infineon Technologies in customer's applications.
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer's technical departments to
evaluate the suitability of the product for the intended
application and the completeness of the product
information given in this document with respect to
such application.
WARNINGS
Due to technical requirements products may contain
dangerous substances. For information on the types
in question please contact your nearest Infineon
Technologies office.
© 2019 Infineon Technologies AG.
All Rights Reserved.
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Email: erratum@infineon.com
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expected to result in personal injury.
Document reference
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